From: Michael McMaster Date: Fri, 29 Aug 2014 12:35:05 +0000 (+1000) Subject: Added glitch filter to ACK, RST, SEL, BSY and ATN lines. X-Git-Tag: v3.6-RC1^0 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=5456126c99b46da1d824367dd67775446d60694d;p=SCSI2SD.git Added glitch filter to ACK, RST, SEL, BSY and ATN lines. --- diff --git a/CHANGELOG b/CHANGELOG index 656e944..bd1346d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,6 +1,6 @@ 201408XX 3.6 - Fix handling requests for LUNs other than 0 from SCSI-2 hosts. - - Handle glitches of the ACK line to improve stability and operate with + - Handle glitches of the scsi signals to improve stability and operate with multiple devices on the SCSI bus. - Re-add parity checking. This can be disabled using scsi2sd-config if required. diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index 12600de..0488522 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -275,10 +275,10 @@ void debugPoll() debugBuffer[14] = scsiDev.lastStatus; debugBuffer[15] = scsiDev.lastSense; debugBuffer[16] = scsiDev.phase; - debugBuffer[17] = SCSI_ReadPin(SCSI_In_BSY); - debugBuffer[18] = SCSI_ReadPin(SCSI_In_SEL); - debugBuffer[19] = SCSI_ReadPin(SCSI_ATN_INT); - debugBuffer[20] = SCSI_ReadPin(SCSI_RST_INT); + debugBuffer[17] = SCSI_ReadFilt(SCSI_Filt_BSY); + debugBuffer[18] = SCSI_ReadFilt(SCSI_Filt_SEL); + debugBuffer[19] = SCSI_ReadFilt(SCSI_Filt_ATN); + debugBuffer[20] = SCSI_ReadFilt(SCSI_Filt_RST); debugBuffer[21] = scsiDev.rstCount; debugBuffer[22] = scsiDev.selCount; debugBuffer[23] = scsiDev.msgCount; diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index 74fe177..eb09721 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -473,8 +473,8 @@ static void enter_SelectionPhase() static void process_SelectionPhase() { - int sel = SCSI_ReadPin(SCSI_In_SEL); - int bsy = SCSI_ReadPin(SCSI_In_BSY); + int sel = SCSI_ReadFilt(SCSI_Filt_SEL); + int bsy = SCSI_ReadFilt(SCSI_Filt_BSY); // Only read these pins AFTER SEL and BSY - we don't want to catch them // during a transition period. @@ -489,7 +489,7 @@ static void process_SelectionPhase() // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says // move to MESSAGE OUT if ATN is true before we assert BSY. // The initiator should assert ATN with SEL. - scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN); // Unit attention breaks many older SCSI hosts. Disable it completely for // SCSI-1 (and older) hosts, regardless of our configured setting. @@ -512,7 +512,7 @@ static void process_SelectionPhase() // Wait until the end of the selection phase. while (!scsiDev.resetFlag) { - if (!SCSI_ReadPin(SCSI_In_SEL)) + if (!SCSI_ReadFilt(SCSI_Filt_SEL)) { break; } @@ -562,7 +562,7 @@ static void process_MessageOut() // Skip the remaining message bytes, and then start the MESSAGE_OUT // phase again from the start. The initiator will re-send the // same set of messages. - while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag) + while (SCSI_ReadFilt(SCSI_Filt_ATN) && !scsiDev.resetFlag) { scsiReadByte(); } @@ -673,7 +673,7 @@ static void process_MessageOut() } // Re-check the ATN flag in case it stays asserted. - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN); } void scsiPoll(void) @@ -681,7 +681,7 @@ void scsiPoll(void) if (scsiDev.resetFlag) { scsiReset(); - if ((scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT))) + if ((scsiDev.resetFlag = SCSI_ReadFilt(SCSI_Filt_RST))) { // Still in reset phase. Do not try and process any commands. return; @@ -691,7 +691,7 @@ void scsiPoll(void) switch (scsiDev.phase) { case BUS_FREE: - if (SCSI_ReadPin(SCSI_In_BSY)) + if (SCSI_ReadFilt(SCSI_Filt_BSY)) { scsiDev.phase = BUS_BUSY; } @@ -699,7 +699,7 @@ void scsiPoll(void) // one initiator in the chain. Support this by moving // straight to selection if SEL is asserted. // ie. the initiator won't assert BSY and it's own ID before moving to selection. - else if (SCSI_ReadPin(SCSI_In_SEL)) + else if (SCSI_ReadFilt(SCSI_Filt_SEL)) { enter_SelectionPhase(); } @@ -708,11 +708,11 @@ void scsiPoll(void) case BUS_BUSY: // Someone is using the bus. Perhaps they are trying to // select us. - if (SCSI_ReadPin(SCSI_In_SEL)) + if (SCSI_ReadFilt(SCSI_Filt_SEL)) { enter_SelectionPhase(); } - else if (!SCSI_ReadPin(SCSI_In_BSY)) + else if (!SCSI_ReadFilt(SCSI_Filt_BSY)) { scsiDev.phase = BUS_FREE; } @@ -745,7 +745,7 @@ void scsiPoll(void) break; case DATA_IN: - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN); if (scsiDev.atnFlag) { process_MessageOut(); @@ -757,7 +757,7 @@ void scsiPoll(void) break; case DATA_OUT: - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN); if (scsiDev.atnFlag) { process_MessageOut(); @@ -769,7 +769,7 @@ void scsiPoll(void) break; case STATUS: - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN); if (scsiDev.atnFlag) { process_MessageOut(); @@ -781,7 +781,7 @@ void scsiPoll(void) break; case MESSAGE_IN: - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN); if (scsiDev.atnFlag) { process_MessageOut(); diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index 46852fb..b6c4e64 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -61,7 +61,6 @@ CY_ISR_PROTO(scsiResetISR); CY_ISR(scsiResetISR) { scsiDev.resetFlag = 1; - SCSI_RST_ClearInterrupt(); } uint8_t @@ -425,8 +424,4 @@ void scsiPhyInit() scsiPhyInitDMA(); SCSI_RST_ISR_StartEx(scsiResetISR); - - // Interrupts may have already been directed to the (empty) - // standard ISR generated by PSoC Creator. - SCSI_RST_ClearInterrupt(); } diff --git a/software/SCSI2SD/src/scsiPhy.h b/software/SCSI2SD/src/scsiPhy.h index b6a1426..97e5f45 100755 --- a/software/SCSI2SD/src/scsiPhy.h +++ b/software/SCSI2SD/src/scsiPhy.h @@ -47,6 +47,19 @@ typedef enum #define SCSI_ReadPin(pin) \ (CyPins_ReadPin((pin)) == 0) +// These signals go through a glitch filter - we do not access the pin +// directly +enum FilteredInputs +{ + SCSI_Filt_ATN = 0x01, + SCSI_Filt_BSY = 0x02, + SCSI_Filt_SEL = 0x04, + SCSI_Filt_RST = 0x08, + SCSI_Filt_ACK = 0x10 +}; +#define SCSI_ReadFilt(filt) \ + ((SCSI_Filtered_Read() & (filt)) == 0) + // Contains the odd-parity flag for a given 8-bit value. extern const uint8_t Lookup_OddParity[256]; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c new file mode 100644 index 0000000..2fc815b --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: SCSI_Filtered.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware to read the value of a Status +* Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Filtered.h" + +#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */ + + +/******************************************************************************* +* Function Name: SCSI_Filtered_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The current value in the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Filtered_Read(void) +{ + return SCSI_Filtered_Status; +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_InterruptEnable +******************************************************************************** +* +* Summary: +* Enables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_InterruptEnable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL; + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_InterruptDisable +******************************************************************************** +* +* Summary: +* Disables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_InterruptDisable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_WriteMask +******************************************************************************** +* +* Summary: +* Writes the current mask value assigned to the Status Register. +* +* Parameters: +* mask: Value to write into the mask register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_WriteMask(uint8 mask) +{ + #if(SCSI_Filtered_INPUTS < 8u) + mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u); + #endif /* End SCSI_Filtered_INPUTS < 8u */ + SCSI_Filtered_Status_Mask = mask; +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_ReadMask +******************************************************************************** +* +* Summary: +* Reads the current interrupt mask assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The value of the interrupt mask of the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Filtered_ReadMask(void) +{ + return SCSI_Filtered_Status_Mask; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h new file mode 100644 index 0000000..759a85b --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_Filtered.h +* Version 1.80 +* +* Description: +* This file containts Status Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */ +#define CY_STATUS_REG_SCSI_Filtered_H + +#include "cytypes.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +uint8 SCSI_Filtered_Read(void) ; +void SCSI_Filtered_InterruptEnable(void) ; +void SCSI_Filtered_InterruptDisable(void) ; +void SCSI_Filtered_WriteMask(uint8 mask) ; +uint8 SCSI_Filtered_ReadMask(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define SCSI_Filtered_STATUS_INTR_ENBL 0x10u + + +/*************************************** +* Parameter Constants +***************************************/ + +/* Status Register Inputs */ +#define SCSI_Filtered_INPUTS 5 + + +/*************************************** +* Registers +***************************************/ + +/* Status Register */ +#define SCSI_Filtered_Status (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG ) +#define SCSI_Filtered_Status_PTR ( (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG ) +#define SCSI_Filtered_Status_Mask (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG ) +#define SCSI_Filtered_Status_Aux_Ctrl (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG ) + +#endif /* End CY_STATUS_REG_SCSI_Filtered_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h old mode 100755 new mode 100644 index 729fd56..ca51951 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h @@ -30,15 +30,9 @@ #define SCSI_In_2 SCSI_In__2__PC #define SCSI_In_3 SCSI_In__3__PC #define SCSI_In_4 SCSI_In__4__PC -#define SCSI_In_5 SCSI_In__5__PC -#define SCSI_In_6 SCSI_In__6__PC -#define SCSI_In_7 SCSI_In__7__PC #define SCSI_In_DBP SCSI_In__DBP__PC -#define SCSI_In_BSY SCSI_In__BSY__PC -#define SCSI_In_ACK SCSI_In__ACK__PC #define SCSI_In_MSG SCSI_In__MSG__PC -#define SCSI_In_SEL SCSI_In__SEL__PC #define SCSI_In_CD SCSI_In__CD__PC #define SCSI_In_REQ SCSI_In__REQ__PC #define SCSI_In_IO SCSI_In__IO__PC diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h new file mode 100644 index 0000000..ffd841d --- /dev/null +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SCSI_Noise.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */ +#define CY_PINS_SCSI_Noise_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Noise_0 SCSI_Noise__0__PC +#define SCSI_Noise_1 SCSI_Noise__1__PC +#define SCSI_Noise_2 SCSI_Noise__2__PC +#define SCSI_Noise_3 SCSI_Noise__3__PC +#define SCSI_Noise_4 SCSI_Noise__4__PC + +#define SCSI_Noise_ATN SCSI_Noise__ATN__PC +#define SCSI_Noise_BSY SCSI_Noise__BSY__PC +#define SCSI_Noise_SEL SCSI_Noise__SEL__PC +#define SCSI_Noise_RST SCSI_Noise__RST__PC +#define SCSI_Noise_ACK SCSI_Noise__ACK__PC + +#endif /* End Pins SCSI_Noise_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 1335c5f..2ee57e0 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -26,10 +26,10 @@ /* SCSI_TX_DMA_COMPLETE */ #define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u #define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3 #define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -54,32 +54,32 @@ /* SD_RX_DMA_COMPLETE */ #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u -#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u #define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SD_TX_DMA_COMPLETE */ #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u #define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -94,41 +94,59 @@ /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL + +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB00_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB00_ST /* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u @@ -143,15 +161,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL /* USBFS_arb_int */ #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -176,24 +194,24 @@ /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -632,40 +650,40 @@ /* SCSI_RST_ISR */ #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x400u -#define SCSI_RST_ISR__INTC_NUMBER 10u +#define SCSI_RST_ISR__INTC_MASK 0x04u +#define SCSI_RST_ISR__INTC_NUMBER 2u #define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2 #define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u @@ -680,8 +698,8 @@ #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -691,26 +709,26 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1 +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB05_06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB05_06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB05_06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB05_06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB05_06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB05_06_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB05_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB05_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB05_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB05_F1 /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1200,11 +1218,281 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT12_AG +#define SCSI_Noise__0__BIE CYREG_PRT12_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT12_BYP +#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2 +#define SCSI_Noise__0__DR CYREG_PRT12_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Noise__0__MASK 0x20u +#define SCSI_Noise__0__PC CYREG_PRT12_PC5 +#define SCSI_Noise__0__PORT 12u +#define SCSI_Noise__0__PRT CYREG_PRT12_PRT +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT12_PS +#define SCSI_Noise__0__SHIFT 5 +#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Noise__0__SLW CYREG_PRT12_SLW +#define SCSI_Noise__1__AG CYREG_PRT6_AG +#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT6_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT6_BYP +#define SCSI_Noise__1__CTL CYREG_PRT6_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__1__DR CYREG_PRT6_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__1__MASK 0x10u +#define SCSI_Noise__1__PC CYREG_PRT6_PC4 +#define SCSI_Noise__1__PORT 6u +#define SCSI_Noise__1__PRT CYREG_PRT6_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT6_PS +#define SCSI_Noise__1__SHIFT 4 +#define SCSI_Noise__1__SLW CYREG_PRT6_SLW +#define SCSI_Noise__2__AG CYREG_PRT5_AG +#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT5_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT5_BYP +#define SCSI_Noise__2__CTL CYREG_PRT5_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2 +#define SCSI_Noise__2__DR CYREG_PRT5_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Noise__2__MASK 0x01u +#define SCSI_Noise__2__PC CYREG_PRT5_PC0 +#define SCSI_Noise__2__PORT 5u +#define SCSI_Noise__2__PRT CYREG_PRT5_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT5_PS +#define SCSI_Noise__2__SHIFT 0 +#define SCSI_Noise__2__SLW CYREG_PRT5_SLW +#define SCSI_Noise__3__AG CYREG_PRT6_AG +#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT6_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT6_BYP +#define SCSI_Noise__3__CTL CYREG_PRT6_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__3__DR CYREG_PRT6_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__3__MASK 0x40u +#define SCSI_Noise__3__PC CYREG_PRT6_PC6 +#define SCSI_Noise__3__PORT 6u +#define SCSI_Noise__3__PRT CYREG_PRT6_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT6_PS +#define SCSI_Noise__3__SHIFT 6 +#define SCSI_Noise__3__SLW CYREG_PRT6_SLW +#define SCSI_Noise__4__AG CYREG_PRT6_AG +#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT6_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT6_BYP +#define SCSI_Noise__4__CTL CYREG_PRT6_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__4__DR CYREG_PRT6_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__4__MASK 0x20u +#define SCSI_Noise__4__PC CYREG_PRT6_PC5 +#define SCSI_Noise__4__PORT 6u +#define SCSI_Noise__4__PRT CYREG_PRT6_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT6_PS +#define SCSI_Noise__4__SHIFT 5 +#define SCSI_Noise__4__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT6_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT6_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__ACK__MASK 0x20u +#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5 +#define SCSI_Noise__ACK__PORT 6u +#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT6_PS +#define SCSI_Noise__ACK__SHIFT 5 +#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT12_AG +#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP +#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT12_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Noise__ATN__MASK 0x20u +#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5 +#define SCSI_Noise__ATN__PORT 12u +#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT12_PS +#define SCSI_Noise__ATN__SHIFT 5 +#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT6_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT6_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__BSY__MASK 0x10u +#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4 +#define SCSI_Noise__BSY__PORT 6u +#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT6_PS +#define SCSI_Noise__BSY__SHIFT 4 +#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Noise__RST__AG CYREG_PRT6_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT6_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__RST__MASK 0x40u +#define SCSI_Noise__RST__PC CYREG_PRT6_PC6 +#define SCSI_Noise__RST__PORT 6u +#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT6_PS +#define SCSI_Noise__RST__SHIFT 6 +#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT5_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT5_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_Noise__SEL__MASK 0x01u +#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0 +#define SCSI_Noise__SEL__PORT 5u +#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT5_PS +#define SCSI_Noise__SEL__SHIFT 0 +#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW + /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1214,58 +1502,58 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1280,40 +1568,40 @@ /* USBFS_ep_1 */ #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x20u -#define USBFS_ep_1__INTC_NUMBER 5u +#define USBFS_ep_1__INTC_MASK 0x40u +#define USBFS_ep_1__INTC_NUMBER 6u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x40u -#define USBFS_ep_2__INTC_NUMBER 6u +#define USBFS_ep_2__INTC_MASK 0x80u +#define USBFS_ep_2__INTC_NUMBER 7u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x80u -#define USBFS_ep_3__INTC_NUMBER 7u +#define USBFS_ep_3__INTC_MASK 0x100u +#define USBFS_ep_3__INTC_NUMBER 8u #define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ #define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x100u -#define USBFS_ep_4__INTC_NUMBER 8u +#define USBFS_ep_4__INTC_MASK 0x200u +#define USBFS_ep_4__INTC_NUMBER 9u #define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9 #define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -1467,41 +1755,6 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 #define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -/* SCSI_ATN */ -#define SCSI_ATN__0__MASK 0x20u -#define SCSI_ATN__0__PC CYREG_PRT12_PC5 -#define SCSI_ATN__0__PORT 12u -#define SCSI_ATN__0__SHIFT 5 -#define SCSI_ATN__AG CYREG_PRT12_AG -#define SCSI_ATN__BIE CYREG_PRT12_BIE -#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK -#define SCSI_ATN__BYP CYREG_PRT12_BYP -#define SCSI_ATN__DM0 CYREG_PRT12_DM0 -#define SCSI_ATN__DM1 CYREG_PRT12_DM1 -#define SCSI_ATN__DM2 CYREG_PRT12_DM2 -#define SCSI_ATN__DR CYREG_PRT12_DR -#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS -#define SCSI_ATN__INT__MASK 0x20u -#define SCSI_ATN__INT__PC CYREG_PRT12_PC5 -#define SCSI_ATN__INT__PORT 12u -#define SCSI_ATN__INT__SHIFT 5 -#define SCSI_ATN__MASK 0x20u -#define SCSI_ATN__PORT 12u -#define SCSI_ATN__PRT CYREG_PRT12_PRT -#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN -#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 -#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 -#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 -#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 -#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT -#define SCSI_ATN__PS CYREG_PRT12_PS -#define SCSI_ATN__SHIFT 5 -#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG -#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF -#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN -#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ -#define SCSI_ATN__SLW CYREG_PRT12_SLW - /* SCSI_CLK */ #define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 #define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 @@ -2055,44 +2308,6 @@ #define SCSI_Out__SEL__SHIFT 3 #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW -/* SCSI_RST */ -#define SCSI_RST__0__MASK 0x40u -#define SCSI_RST__0__PC CYREG_PRT6_PC6 -#define SCSI_RST__0__PORT 6u -#define SCSI_RST__0__SHIFT 6 -#define SCSI_RST__AG CYREG_PRT6_AG -#define SCSI_RST__AMUX CYREG_PRT6_AMUX -#define SCSI_RST__BIE CYREG_PRT6_BIE -#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_RST__BYP CYREG_PRT6_BYP -#define SCSI_RST__CTL CYREG_PRT6_CTL -#define SCSI_RST__DM0 CYREG_PRT6_DM0 -#define SCSI_RST__DM1 CYREG_PRT6_DM1 -#define SCSI_RST__DM2 CYREG_PRT6_DM2 -#define SCSI_RST__DR CYREG_PRT6_DR -#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT -#define SCSI_RST__INT__MASK 0x40u -#define SCSI_RST__INT__PC CYREG_PRT6_PC6 -#define SCSI_RST__INT__PORT 6u -#define SCSI_RST__INT__SHIFT 6 -#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_RST__MASK 0x40u -#define SCSI_RST__PORT 6u -#define SCSI_RST__PRT CYREG_PRT6_PRT -#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_RST__PS CYREG_PRT6_PS -#define SCSI_RST__SHIFT 6 -#define SCSI_RST__SLW CYREG_PRT6_SLW -#define SCSI_RST__SNAP CYREG_PICU6_SNAP - /* USBFS_Dm */ #define USBFS_Dm__0__MASK 0x80u #define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 @@ -2200,8 +2415,8 @@ #define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS #define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG #define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__1__MASK 0x10u -#define SCSI_In__1__PC CYREG_PRT6_PC4 +#define SCSI_In__1__MASK 0x80u +#define SCSI_In__1__PC CYREG_PRT6_PC7 #define SCSI_In__1__PORT 6u #define SCSI_In__1__PRT CYREG_PRT6_PRT #define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL @@ -2212,62 +2427,62 @@ #define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 #define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT #define SCSI_In__1__PS CYREG_PRT6_PS -#define SCSI_In__1__SHIFT 4 +#define SCSI_In__1__SHIFT 7 #define SCSI_In__1__SLW CYREG_PRT6_SLW -#define SCSI_In__2__AG CYREG_PRT6_AG -#define SCSI_In__2__AMUX CYREG_PRT6_AMUX -#define SCSI_In__2__BIE CYREG_PRT6_BIE -#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__2__BYP CYREG_PRT6_BYP -#define SCSI_In__2__CTL CYREG_PRT6_CTL -#define SCSI_In__2__DM0 CYREG_PRT6_DM0 -#define SCSI_In__2__DM1 CYREG_PRT6_DM1 -#define SCSI_In__2__DM2 CYREG_PRT6_DM2 -#define SCSI_In__2__DR CYREG_PRT6_DR -#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__2__MASK 0x20u -#define SCSI_In__2__PC CYREG_PRT6_PC5 -#define SCSI_In__2__PORT 6u -#define SCSI_In__2__PRT CYREG_PRT6_PRT -#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__2__PS CYREG_PRT6_PS -#define SCSI_In__2__SHIFT 5 -#define SCSI_In__2__SLW CYREG_PRT6_SLW -#define SCSI_In__3__AG CYREG_PRT6_AG -#define SCSI_In__3__AMUX CYREG_PRT6_AMUX -#define SCSI_In__3__BIE CYREG_PRT6_BIE -#define SCSI_In__3__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__3__BYP CYREG_PRT6_BYP -#define SCSI_In__3__CTL CYREG_PRT6_CTL -#define SCSI_In__3__DM0 CYREG_PRT6_DM0 -#define SCSI_In__3__DM1 CYREG_PRT6_DM1 -#define SCSI_In__3__DM2 CYREG_PRT6_DM2 -#define SCSI_In__3__DR CYREG_PRT6_DR -#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__3__MASK 0x80u -#define SCSI_In__3__PC CYREG_PRT6_PC7 -#define SCSI_In__3__PORT 6u -#define SCSI_In__3__PRT CYREG_PRT6_PRT -#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__3__PS CYREG_PRT6_PS -#define SCSI_In__3__SHIFT 7 -#define SCSI_In__3__SLW CYREG_PRT6_SLW +#define SCSI_In__2__AG CYREG_PRT5_AG +#define SCSI_In__2__AMUX CYREG_PRT5_AMUX +#define SCSI_In__2__BIE CYREG_PRT5_BIE +#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__2__BYP CYREG_PRT5_BYP +#define SCSI_In__2__CTL CYREG_PRT5_CTL +#define SCSI_In__2__DM0 CYREG_PRT5_DM0 +#define SCSI_In__2__DM1 CYREG_PRT5_DM1 +#define SCSI_In__2__DM2 CYREG_PRT5_DM2 +#define SCSI_In__2__DR CYREG_PRT5_DR +#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__2__MASK 0x02u +#define SCSI_In__2__PC CYREG_PRT5_PC1 +#define SCSI_In__2__PORT 5u +#define SCSI_In__2__PRT CYREG_PRT5_PRT +#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__2__PS CYREG_PRT5_PS +#define SCSI_In__2__SHIFT 1 +#define SCSI_In__2__SLW CYREG_PRT5_SLW +#define SCSI_In__3__AG CYREG_PRT5_AG +#define SCSI_In__3__AMUX CYREG_PRT5_AMUX +#define SCSI_In__3__BIE CYREG_PRT5_BIE +#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK +#define SCSI_In__3__BYP CYREG_PRT5_BYP +#define SCSI_In__3__CTL CYREG_PRT5_CTL +#define SCSI_In__3__DM0 CYREG_PRT5_DM0 +#define SCSI_In__3__DM1 CYREG_PRT5_DM1 +#define SCSI_In__3__DM2 CYREG_PRT5_DM2 +#define SCSI_In__3__DR CYREG_PRT5_DR +#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS +#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG +#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN +#define SCSI_In__3__MASK 0x04u +#define SCSI_In__3__PC CYREG_PRT5_PC2 +#define SCSI_In__3__PORT 5u +#define SCSI_In__3__PRT CYREG_PRT5_PRT +#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL +#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN +#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 +#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 +#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 +#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 +#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT +#define SCSI_In__3__PS CYREG_PRT5_PS +#define SCSI_In__3__SHIFT 2 +#define SCSI_In__3__SLW CYREG_PRT5_SLW #define SCSI_In__4__AG CYREG_PRT5_AG #define SCSI_In__4__AMUX CYREG_PRT5_AMUX #define SCSI_In__4__BIE CYREG_PRT5_BIE @@ -2281,8 +2496,8 @@ #define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS #define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG #define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_In__4__MASK 0x01u -#define SCSI_In__4__PC CYREG_PRT5_PC0 +#define SCSI_In__4__MASK 0x08u +#define SCSI_In__4__PC CYREG_PRT5_PC3 #define SCSI_In__4__PORT 5u #define SCSI_In__4__PRT CYREG_PRT5_PRT #define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL @@ -2293,143 +2508,8 @@ #define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 #define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT #define SCSI_In__4__PS CYREG_PRT5_PS -#define SCSI_In__4__SHIFT 0 +#define SCSI_In__4__SHIFT 3 #define SCSI_In__4__SLW CYREG_PRT5_SLW -#define SCSI_In__5__AG CYREG_PRT5_AG -#define SCSI_In__5__AMUX CYREG_PRT5_AMUX -#define SCSI_In__5__BIE CYREG_PRT5_BIE -#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_In__5__BYP CYREG_PRT5_BYP -#define SCSI_In__5__CTL CYREG_PRT5_CTL -#define SCSI_In__5__DM0 CYREG_PRT5_DM0 -#define SCSI_In__5__DM1 CYREG_PRT5_DM1 -#define SCSI_In__5__DM2 CYREG_PRT5_DM2 -#define SCSI_In__5__DR CYREG_PRT5_DR -#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_In__5__MASK 0x02u -#define SCSI_In__5__PC CYREG_PRT5_PC1 -#define SCSI_In__5__PORT 5u -#define SCSI_In__5__PRT CYREG_PRT5_PRT -#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_In__5__PS CYREG_PRT5_PS -#define SCSI_In__5__SHIFT 1 -#define SCSI_In__5__SLW CYREG_PRT5_SLW -#define SCSI_In__6__AG CYREG_PRT5_AG -#define SCSI_In__6__AMUX CYREG_PRT5_AMUX -#define SCSI_In__6__BIE CYREG_PRT5_BIE -#define SCSI_In__6__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_In__6__BYP CYREG_PRT5_BYP -#define SCSI_In__6__CTL CYREG_PRT5_CTL -#define SCSI_In__6__DM0 CYREG_PRT5_DM0 -#define SCSI_In__6__DM1 CYREG_PRT5_DM1 -#define SCSI_In__6__DM2 CYREG_PRT5_DM2 -#define SCSI_In__6__DR CYREG_PRT5_DR -#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_In__6__MASK 0x04u -#define SCSI_In__6__PC CYREG_PRT5_PC2 -#define SCSI_In__6__PORT 5u -#define SCSI_In__6__PRT CYREG_PRT5_PRT -#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_In__6__PS CYREG_PRT5_PS -#define SCSI_In__6__SHIFT 2 -#define SCSI_In__6__SLW CYREG_PRT5_SLW -#define SCSI_In__7__AG CYREG_PRT5_AG -#define SCSI_In__7__AMUX CYREG_PRT5_AMUX -#define SCSI_In__7__BIE CYREG_PRT5_BIE -#define SCSI_In__7__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_In__7__BYP CYREG_PRT5_BYP -#define SCSI_In__7__CTL CYREG_PRT5_CTL -#define SCSI_In__7__DM0 CYREG_PRT5_DM0 -#define SCSI_In__7__DM1 CYREG_PRT5_DM1 -#define SCSI_In__7__DM2 CYREG_PRT5_DM2 -#define SCSI_In__7__DR CYREG_PRT5_DR -#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_In__7__MASK 0x08u -#define SCSI_In__7__PC CYREG_PRT5_PC3 -#define SCSI_In__7__PORT 5u -#define SCSI_In__7__PRT CYREG_PRT5_PRT -#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_In__7__PS CYREG_PRT5_PS -#define SCSI_In__7__SHIFT 3 -#define SCSI_In__7__SLW CYREG_PRT5_SLW -#define SCSI_In__ACK__AG CYREG_PRT6_AG -#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX -#define SCSI_In__ACK__BIE CYREG_PRT6_BIE -#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__ACK__BYP CYREG_PRT6_BYP -#define SCSI_In__ACK__CTL CYREG_PRT6_CTL -#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0 -#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1 -#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2 -#define SCSI_In__ACK__DR CYREG_PRT6_DR -#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__ACK__MASK 0x20u -#define SCSI_In__ACK__PC CYREG_PRT6_PC5 -#define SCSI_In__ACK__PORT 6u -#define SCSI_In__ACK__PRT CYREG_PRT6_PRT -#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__ACK__PS CYREG_PRT6_PS -#define SCSI_In__ACK__SHIFT 5 -#define SCSI_In__ACK__SLW CYREG_PRT6_SLW -#define SCSI_In__BSY__AG CYREG_PRT6_AG -#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX -#define SCSI_In__BSY__BIE CYREG_PRT6_BIE -#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__BSY__BYP CYREG_PRT6_BYP -#define SCSI_In__BSY__CTL CYREG_PRT6_CTL -#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0 -#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1 -#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2 -#define SCSI_In__BSY__DR CYREG_PRT6_DR -#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__BSY__MASK 0x10u -#define SCSI_In__BSY__PC CYREG_PRT6_PC4 -#define SCSI_In__BSY__PORT 6u -#define SCSI_In__BSY__PRT CYREG_PRT6_PRT -#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__BSY__PS CYREG_PRT6_PS -#define SCSI_In__BSY__SHIFT 4 -#define SCSI_In__BSY__SLW CYREG_PRT6_SLW #define SCSI_In__CD__AG CYREG_PRT5_AG #define SCSI_In__CD__AMUX CYREG_PRT5_AMUX #define SCSI_In__CD__BIE CYREG_PRT5_BIE @@ -2565,33 +2645,6 @@ #define SCSI_In__REQ__PS CYREG_PRT5_PS #define SCSI_In__REQ__SHIFT 2 #define SCSI_In__REQ__SLW CYREG_PRT5_SLW -#define SCSI_In__SEL__AG CYREG_PRT5_AG -#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX -#define SCSI_In__SEL__BIE CYREG_PRT5_BIE -#define SCSI_In__SEL__BIT_MASK CYREG_PRT5_BIT_MASK -#define SCSI_In__SEL__BYP CYREG_PRT5_BYP -#define SCSI_In__SEL__CTL CYREG_PRT5_CTL -#define SCSI_In__SEL__DM0 CYREG_PRT5_DM0 -#define SCSI_In__SEL__DM1 CYREG_PRT5_DM1 -#define SCSI_In__SEL__DM2 CYREG_PRT5_DM2 -#define SCSI_In__SEL__DR CYREG_PRT5_DR -#define SCSI_In__SEL__INP_DIS CYREG_PRT5_INP_DIS -#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG -#define SCSI_In__SEL__LCD_EN CYREG_PRT5_LCD_EN -#define SCSI_In__SEL__MASK 0x01u -#define SCSI_In__SEL__PC CYREG_PRT5_PC0 -#define SCSI_In__SEL__PORT 5u -#define SCSI_In__SEL__PRT CYREG_PRT5_PRT -#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL -#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN -#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0 -#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1 -#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0 -#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1 -#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT -#define SCSI_In__SEL__PS CYREG_PRT5_PS -#define SCSI_In__SEL__SHIFT 0 -#define SCSI_In__SEL__SLW CYREG_PRT5_SLW /* SD_DAT1 */ #define SD_DAT1__0__MASK 0x01u @@ -2923,7 +2976,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000001Eu +#define CYDEV_INTR_RISING 0x0000003Eu #define CYDEV_PROJ_TYPE 2 #define CYDEV_PROJ_TYPE_BOOTLOADER 1 #define CYDEV_PROJ_TYPE_LOADABLE 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 365ce1d..ff81377 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 37u +#define CY_CFG_BASE_ADDR_COUNT 41u CYPACKED typedef struct { uint8 offset; @@ -378,1035 +378,1140 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40004502u, /* Base address: 0x40004500 Count: 2 */ + 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ - 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x4001004Au, /* Base address: 0x40010000 Count: 74 */ - 0x40010137u, /* Base address: 0x40010100 Count: 55 */ - 0x4001024Au, /* Base address: 0x40010200 Count: 74 */ - 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */ - 0x4001043Au, /* Base address: 0x40010400 Count: 58 */ - 0x4001055Cu, /* Base address: 0x40010500 Count: 92 */ - 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ - 0x40010757u, /* Base address: 0x40010700 Count: 87 */ - 0x4001091Au, /* Base address: 0x40010900 Count: 26 */ - 0x40010A3Bu, /* Base address: 0x40010A00 Count: 59 */ - 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */ - 0x40010D23u, /* Base address: 0x40010D00 Count: 35 */ - 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */ - 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */ - 0x4001145Bu, /* Base address: 0x40011400 Count: 91 */ - 0x40011543u, /* Base address: 0x40011500 Count: 67 */ - 0x4001161Eu, /* Base address: 0x40011600 Count: 30 */ - 0x40011750u, /* Base address: 0x40011700 Count: 80 */ - 0x4001190Du, /* Base address: 0x40011900 Count: 13 */ - 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */ - 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ - 0x40014119u, /* Base address: 0x40014100 Count: 25 */ - 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */ - 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */ - 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */ + 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ + 0x40006401u, /* Base address: 0x40006400 Count: 1 */ + 0x40006501u, /* Base address: 0x40006500 Count: 1 */ + 0x40010047u, /* Base address: 0x40010000 Count: 71 */ + 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */ + 0x40010249u, /* Base address: 0x40010200 Count: 73 */ + 0x40010354u, /* Base address: 0x40010300 Count: 84 */ + 0x40010453u, /* Base address: 0x40010400 Count: 83 */ + 0x4001054Fu, /* Base address: 0x40010500 Count: 79 */ + 0x40010651u, /* Base address: 0x40010600 Count: 81 */ + 0x40010747u, /* Base address: 0x40010700 Count: 71 */ + 0x4001090Bu, /* Base address: 0x40010900 Count: 11 */ + 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */ + 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */ + 0x40010C39u, /* Base address: 0x40010C00 Count: 57 */ + 0x40010D5Cu, /* Base address: 0x40010D00 Count: 92 */ + 0x40010E44u, /* Base address: 0x40010E00 Count: 68 */ + 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */ + 0x40011465u, /* Base address: 0x40011400 Count: 101 */ + 0x4001154Fu, /* Base address: 0x40011500 Count: 79 */ + 0x40011650u, /* Base address: 0x40011600 Count: 80 */ + 0x40011744u, /* Base address: 0x40011700 Count: 68 */ + 0x40011804u, /* Base address: 0x40011800 Count: 4 */ + 0x40011907u, /* Base address: 0x40011900 Count: 7 */ + 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */ + 0x40014018u, /* Base address: 0x40014000 Count: 24 */ + 0x4001411Du, /* Base address: 0x40014100 Count: 29 */ + 0x40014210u, /* Base address: 0x40014200 Count: 16 */ + 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ + 0x40014411u, /* Base address: 0x40014400 Count: 17 */ 0x40014514u, /* Base address: 0x40014500 Count: 20 */ - 0x40014609u, /* Base address: 0x40014600 Count: 9 */ + 0x4001460Du, /* Base address: 0x40014600 Count: 13 */ 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */ - 0x40014805u, /* Base address: 0x40014800 Count: 5 */ - 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */ - 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */ - 0x40015002u, /* Base address: 0x40015000 Count: 2 */ + 0x40014809u, /* Base address: 0x40014800 Count: 9 */ + 0x40014910u, /* Base address: 0x40014900 Count: 16 */ + 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ + 0x40014D04u, /* Base address: 0x40014D00 Count: 4 */ + 0x40015004u, /* Base address: 0x40015000 Count: 4 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - {0x36u, 0x02u}, {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x27u}, - {0x00u, 0x04u}, - {0x01u, 0x11u}, - {0x18u, 0x04u}, + {0x0Au, 0x36u}, + {0x00u, 0x12u}, + {0x01u, 0x04u}, + {0x18u, 0x08u}, {0x1Cu, 0x61u}, - {0x20u, 0x68u}, - {0x21u, 0xC0u}, - {0x2Cu, 0x0Fu}, - {0x30u, 0x09u}, - {0x31u, 0x0Au}, - {0x34u, 0x90u}, - {0x64u, 0x20u}, + {0x20u, 0x50u}, + {0x21u, 0x90u}, + {0x2Cu, 0x0Eu}, + {0x30u, 0x0Au}, + {0x31u, 0x09u}, + {0x34u, 0x80u}, {0x7Cu, 0x40u}, - {0x24u, 0x02u}, + {0x2Cu, 0x02u}, {0x86u, 0x0Fu}, - {0x03u, 0x80u}, - {0x06u, 0x80u}, + {0x02u, 0x10u}, + {0x03u, 0x08u}, + {0x04u, 0x01u}, + {0x06u, 0x02u}, {0x07u, 0x07u}, - {0x09u, 0x44u}, - {0x0Bu, 0x88u}, - {0x0Eu, 0x07u}, - {0x10u, 0xAAu}, - {0x11u, 0xAAu}, - {0x12u, 0x55u}, - {0x13u, 0x55u}, - {0x14u, 0x99u}, + {0x0Bu, 0x70u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x44u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x88u}, + {0x14u, 0x02u}, {0x15u, 0x99u}, - {0x16u, 0x22u}, + {0x16u, 0x05u}, {0x17u, 0x22u}, - {0x1Au, 0x70u}, - {0x1Bu, 0x70u}, - {0x27u, 0x08u}, - {0x28u, 0x44u}, - {0x2Au, 0x88u}, - {0x2Eu, 0x08u}, - {0x30u, 0x0Fu}, + {0x18u, 0x02u}, + {0x1Au, 0x09u}, + {0x1Cu, 0x10u}, + {0x1Du, 0xAAu}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x55u}, + {0x26u, 0x20u}, + {0x28u, 0x02u}, + {0x2Au, 0x01u}, + {0x2Bu, 0x80u}, + {0x30u, 0x04u}, + {0x32u, 0x08u}, {0x33u, 0x0Fu}, - {0x34u, 0xF0u}, + {0x34u, 0x03u}, {0x35u, 0xF0u}, - {0x56u, 0x08u}, + {0x36u, 0x30u}, + {0x3Au, 0x20u}, + {0x3Eu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x90u}, + {0x5Cu, 0x19u}, {0x5Fu, 0x01u}, - {0x82u, 0x20u}, - {0x84u, 0x02u}, - {0x85u, 0x08u}, - {0x86u, 0x0Du}, - {0x88u, 0x02u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x19u}, - {0x8Cu, 0x0Du}, - {0x8Du, 0x33u}, - {0x8Fu, 0x4Cu}, - {0x90u, 0x10u}, - {0x91u, 0x18u}, - {0x92u, 0x20u}, - {0x93u, 0x60u}, - {0x94u, 0x0Du}, - {0x99u, 0x2Au}, - {0x9Au, 0x10u}, - {0x9Bu, 0x55u}, - {0x9Cu, 0x0Du}, - {0x9Du, 0x01u}, - {0x9Fu, 0x06u}, - {0xA0u, 0x02u}, - {0xA2u, 0x08u}, - {0xA3u, 0x10u}, - {0xA4u, 0x0Du}, - {0xA5u, 0x3Au}, - {0xA7u, 0x45u}, - {0xA8u, 0x01u}, - {0xAAu, 0x02u}, - {0xABu, 0x01u}, - {0xACu, 0x0Du}, - {0xB1u, 0x07u}, - {0xB2u, 0x0Fu}, - {0xB6u, 0x30u}, - {0xB7u, 0x78u}, - {0xBAu, 0x08u}, - {0xBBu, 0x82u}, - {0xBEu, 0x40u}, + {0x81u, 0x02u}, + {0x83u, 0x01u}, + {0x87u, 0x04u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x01u}, + {0x91u, 0x01u}, + {0x92u, 0x02u}, + {0x93u, 0x02u}, + {0x9Au, 0x04u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x01u}, + {0xA2u, 0x01u}, + {0xA5u, 0x02u}, + {0xA7u, 0x11u}, + {0xAAu, 0x08u}, + {0xAFu, 0x08u}, + {0xB0u, 0x01u}, + {0xB1u, 0x10u}, + {0xB2u, 0x0Cu}, + {0xB3u, 0x04u}, + {0xB4u, 0x02u}, + {0xB5u, 0x08u}, + {0xB7u, 0x03u}, + {0xBBu, 0x80u}, + {0xBEu, 0x04u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x99u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x01u, 0x01u}, + {0x03u, 0x02u}, + {0x08u, 0x10u}, + {0x0Au, 0x22u}, + {0x0Bu, 0x01u}, + {0x0Du, 0x10u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0x01u}, + {0x11u, 0x24u}, + {0x16u, 0x88u}, + {0x18u, 0x04u}, + {0x19u, 0x10u}, + {0x1Au, 0x21u}, + {0x1Bu, 0x12u}, + {0x1Cu, 0x20u}, + {0x1Eu, 0x80u}, + {0x1Fu, 0x10u}, + {0x20u, 0x08u}, + {0x21u, 0x14u}, + {0x22u, 0x08u}, + {0x24u, 0x02u}, + {0x25u, 0x91u}, + {0x27u, 0x12u}, + {0x2Bu, 0x08u}, + {0x2Fu, 0x12u}, + {0x30u, 0x80u}, + {0x31u, 0x04u}, + {0x36u, 0x40u}, + {0x37u, 0x02u}, + {0x38u, 0x80u}, + {0x39u, 0x28u}, + {0x3Bu, 0x02u}, + {0x3Du, 0x02u}, + {0x3Eu, 0x80u}, + {0x3Fu, 0x04u}, + {0x58u, 0x40u}, + {0x5Au, 0x18u}, + {0x5Bu, 0x02u}, + {0x5Cu, 0x80u}, + {0x5Du, 0x20u}, + {0x62u, 0x80u}, + {0x66u, 0xA0u}, + {0x67u, 0x04u}, + {0x80u, 0x80u}, + {0x81u, 0x90u}, + {0x82u, 0x80u}, + {0x84u, 0x10u}, + {0x88u, 0x10u}, + {0x89u, 0x20u}, + {0x8Au, 0x02u}, + {0x8Du, 0x40u}, + {0xC0u, 0x0Du}, + {0xC2u, 0xD7u}, + {0xC4u, 0x56u}, + {0xCAu, 0x54u}, + {0xCCu, 0x9Au}, + {0xCEu, 0xDFu}, + {0xD6u, 0x3Fu}, + {0xD8u, 0x38u}, + {0xE2u, 0x04u}, + {0xE4u, 0x05u}, + {0xE6u, 0xA2u}, + {0x01u, 0x02u}, + {0x02u, 0x10u}, + {0x03u, 0x01u}, + {0x04u, 0x05u}, + {0x05u, 0x02u}, + {0x06u, 0x02u}, + {0x07u, 0x05u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x09u}, + {0x10u, 0x04u}, + {0x11u, 0x01u}, + {0x12u, 0x03u}, + {0x13u, 0x02u}, + {0x14u, 0x01u}, + {0x16u, 0x06u}, + {0x19u, 0x02u}, + {0x1Bu, 0x11u}, + {0x1Eu, 0x08u}, + {0x28u, 0x03u}, + {0x2Au, 0x04u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x10u}, + {0x30u, 0x07u}, + {0x31u, 0x04u}, + {0x33u, 0x10u}, + {0x34u, 0x18u}, + {0x35u, 0x08u}, + {0x36u, 0x07u}, + {0x37u, 0x03u}, + {0x3Au, 0x82u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x10u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x05u}, + {0x82u, 0x0Au}, + {0x83u, 0xFFu}, + {0x84u, 0x06u}, + {0x86u, 0x09u}, + {0x89u, 0x55u}, + {0x8Bu, 0xAAu}, + {0x90u, 0x0Fu}, + {0x92u, 0xF0u}, + {0x97u, 0xFFu}, + {0x98u, 0x60u}, + {0x99u, 0x0Fu}, + {0x9Au, 0x90u}, + {0x9Bu, 0xF0u}, + {0x9Cu, 0x03u}, + {0x9Du, 0xFFu}, + {0x9Eu, 0x0Cu}, + {0xA1u, 0x69u}, + {0xA3u, 0x96u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x50u}, + {0xA9u, 0xFFu}, + {0xAAu, 0xA0u}, + {0xACu, 0x30u}, + {0xADu, 0x33u}, + {0xAEu, 0xC0u}, + {0xAFu, 0xCCu}, + {0xB2u, 0xFFu}, + {0xB5u, 0xFFu}, + {0xBBu, 0x20u}, + {0xBEu, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x48u}, - {0x05u, 0x56u}, - {0x09u, 0x0Au}, - {0x0Au, 0x04u}, - {0x0Du, 0x20u}, - {0x0Eu, 0x11u}, - {0x0Fu, 0x40u}, - {0x11u, 0x50u}, - {0x15u, 0x24u}, - {0x16u, 0x02u}, - {0x17u, 0x01u}, - {0x18u, 0x40u}, - {0x1Au, 0x0Cu}, - {0x1Bu, 0x01u}, - {0x1Cu, 0x02u}, - {0x1Du, 0x04u}, - {0x21u, 0x24u}, - {0x27u, 0x42u}, - {0x2Au, 0x08u}, - {0x2Fu, 0x54u}, - {0x31u, 0x2Au}, - {0x36u, 0x10u}, - {0x37u, 0x42u}, + {0x00u, 0x08u}, + {0x03u, 0x80u}, + {0x04u, 0x04u}, + {0x06u, 0x80u}, + {0x08u, 0x01u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0xA1u}, + {0x0Fu, 0x02u}, + {0x10u, 0x40u}, + {0x13u, 0x52u}, + {0x14u, 0x01u}, + {0x17u, 0x20u}, + {0x18u, 0x10u}, + {0x1Eu, 0x80u}, + {0x1Fu, 0x60u}, + {0x21u, 0x20u}, + {0x25u, 0x05u}, + {0x26u, 0x20u}, + {0x27u, 0x02u}, + {0x29u, 0x90u}, + {0x2Au, 0x06u}, + {0x30u, 0x81u}, + {0x31u, 0x24u}, + {0x32u, 0x01u}, + {0x36u, 0x20u}, + {0x37u, 0x02u}, {0x38u, 0x02u}, - {0x39u, 0x18u}, - {0x3Bu, 0x24u}, - {0x3Du, 0x08u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x20u}, - {0x59u, 0x80u}, - {0x5Bu, 0x20u}, - {0x60u, 0x04u}, + {0x39u, 0x20u}, + {0x3Cu, 0x40u}, + {0x3Du, 0x0Au}, + {0x44u, 0x10u}, + {0x45u, 0x08u}, + {0x58u, 0x10u}, + {0x59u, 0x01u}, + {0x5Au, 0x40u}, + {0x5Bu, 0x08u}, {0x62u, 0x80u}, - {0x63u, 0x08u}, - {0x6Cu, 0x02u}, - {0x6Du, 0x08u}, - {0x6Fu, 0x18u}, - {0x83u, 0x18u}, - {0x84u, 0x50u}, - {0x88u, 0x01u}, - {0x89u, 0x04u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x02u}, - {0x8Fu, 0x04u}, - {0xC0u, 0xF5u}, - {0xC2u, 0xFEu}, - {0xC4u, 0xF3u}, - {0xCAu, 0xE2u}, - {0xCCu, 0xB7u}, - {0xCEu, 0x77u}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x0Cu}, + {0x69u, 0x55u}, + {0x6Cu, 0x10u}, + {0x6Du, 0xA0u}, + {0x71u, 0x80u}, + {0x72u, 0x88u}, + {0x73u, 0x54u}, + {0x80u, 0x10u}, + {0x81u, 0x10u}, + {0x85u, 0x80u}, + {0x89u, 0x40u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0xC0u}, + {0x8Fu, 0x0Au}, + {0x90u, 0x02u}, + {0x92u, 0x40u}, + {0x94u, 0x80u}, + {0x95u, 0x44u}, + {0x96u, 0x1Au}, + {0x97u, 0x02u}, + {0x99u, 0x10u}, + {0x9Au, 0x22u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x40u}, + {0x9Du, 0x04u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x04u}, + {0xA2u, 0x08u}, + {0xA3u, 0x10u}, + {0xA7u, 0x08u}, + {0xACu, 0x80u}, + {0xAEu, 0x01u}, + {0xB1u, 0x01u}, + {0xB6u, 0x40u}, + {0xC0u, 0x3Cu}, + {0xC2u, 0xBBu}, + {0xC4u, 0xC3u}, + {0xCAu, 0x0Fu}, + {0xCCu, 0xAEu}, + {0xCEu, 0xD5u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, {0xE0u, 0x04u}, - {0xE2u, 0xA0u}, - {0xE6u, 0x02u}, - {0x01u, 0x60u}, - {0x04u, 0x06u}, - {0x06u, 0x01u}, - {0x08u, 0x04u}, - {0x09u, 0x04u}, - {0x0Bu, 0x03u}, - {0x10u, 0x1Fu}, - {0x11u, 0x2Du}, - {0x13u, 0x12u}, - {0x16u, 0x1Eu}, - {0x18u, 0x01u}, - {0x19u, 0x1Bu}, - {0x1Au, 0x18u}, - {0x1Bu, 0x44u}, - {0x24u, 0x07u}, - {0x26u, 0x08u}, - {0x29u, 0x19u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x26u}, - {0x2Cu, 0x17u}, - {0x30u, 0x1Eu}, - {0x31u, 0x70u}, - {0x33u, 0x07u}, - {0x34u, 0x01u}, - {0x35u, 0x08u}, - {0x39u, 0x02u}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x10u}, + {0xE2u, 0x08u}, + {0xE6u, 0x28u}, + {0xE8u, 0x08u}, + {0xEEu, 0x42u}, + {0x04u, 0x30u}, + {0x06u, 0xC0u}, + {0x07u, 0x80u}, + {0x08u, 0xFFu}, + {0x09u, 0x0Fu}, + {0x0Cu, 0x05u}, + {0x0Du, 0xC0u}, + {0x0Eu, 0x0Au}, + {0x0Fu, 0x1Fu}, + {0x10u, 0x03u}, + {0x12u, 0x0Cu}, + {0x13u, 0x70u}, + {0x15u, 0x90u}, + {0x16u, 0xFFu}, + {0x17u, 0x2Fu}, + {0x18u, 0xFFu}, + {0x19u, 0x05u}, + {0x1Bu, 0x0Au}, + {0x1Cu, 0x0Fu}, + {0x1Eu, 0xF0u}, + {0x20u, 0x09u}, + {0x21u, 0x03u}, + {0x22u, 0x06u}, + {0x23u, 0x0Cu}, + {0x27u, 0x80u}, + {0x28u, 0x50u}, + {0x29u, 0x06u}, + {0x2Au, 0xA0u}, + {0x2Bu, 0x09u}, + {0x2Cu, 0x90u}, + {0x2Du, 0xA0u}, + {0x2Eu, 0x60u}, + {0x2Fu, 0x4Fu}, + {0x31u, 0x7Fu}, + {0x36u, 0xFFu}, + {0x37u, 0x80u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x10u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x40u}, - {0x81u, 0x02u}, - {0x85u, 0x01u}, - {0x8Au, 0x07u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x08u}, - {0x90u, 0x0Au}, - {0x92u, 0x05u}, - {0x94u, 0x09u}, + {0x82u, 0x70u}, + {0x84u, 0x02u}, + {0x85u, 0xC8u}, + {0x86u, 0x05u}, + {0x87u, 0x03u}, + {0x88u, 0x40u}, + {0x8Cu, 0x70u}, + {0x8Fu, 0x0Cu}, + {0x93u, 0x01u}, + {0x94u, 0x01u}, {0x96u, 0x02u}, - {0x97u, 0x04u}, - {0x98u, 0x04u}, - {0x99u, 0x02u}, - {0x9Au, 0x08u}, - {0xA1u, 0x02u}, - {0xA2u, 0x08u}, - {0xA6u, 0x10u}, - {0xABu, 0x08u}, + {0x97u, 0x20u}, + {0x98u, 0x02u}, + {0x99u, 0x04u}, + {0x9Au, 0x09u}, + {0x9Bu, 0xA3u}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x01u}, + {0xA4u, 0x02u}, + {0xA6u, 0x01u}, + {0xA9u, 0x01u}, + {0xAAu, 0x20u}, + {0xABu, 0x62u}, {0xACu, 0x10u}, - {0xADu, 0x02u}, - {0xAEu, 0x20u}, - {0xB0u, 0x30u}, - {0xB1u, 0x02u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x01u}, - {0xB4u, 0x40u}, - {0xB7u, 0x0Cu}, - {0xB9u, 0x02u}, - {0xBEu, 0x11u}, - {0xBFu, 0x45u}, - {0xD6u, 0x08u}, + {0xAFu, 0x12u}, + {0xB0u, 0x70u}, + {0xB1u, 0x10u}, + {0xB2u, 0x03u}, + {0xB4u, 0x04u}, + {0xB5u, 0xE0u}, + {0xB6u, 0x08u}, + {0xB7u, 0x0Fu}, + {0xBAu, 0x08u}, + {0xBEu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x01u}, - {0xDDu, 0x90u}, + {0xDCu, 0x09u}, {0xDFu, 0x01u}, - {0x00u, 0x20u}, - {0x02u, 0x82u}, - {0x03u, 0x08u}, - {0x04u, 0x20u}, - {0x05u, 0x08u}, - {0x09u, 0x0Au}, - {0x0Au, 0x04u}, - {0x0Eu, 0x44u}, - {0x0Fu, 0x20u}, - {0x11u, 0x01u}, - {0x13u, 0x44u}, - {0x14u, 0x21u}, - {0x17u, 0x10u}, - {0x19u, 0x20u}, - {0x1Au, 0x80u}, - {0x1Bu, 0x08u}, - {0x1Du, 0x02u}, - {0x1Eu, 0x40u}, - {0x1Fu, 0x20u}, - {0x20u, 0x12u}, - {0x22u, 0x01u}, - {0x24u, 0x80u}, - {0x25u, 0x01u}, - {0x27u, 0x28u}, - {0x28u, 0x04u}, - {0x29u, 0x01u}, - {0x2Bu, 0x02u}, - {0x2Eu, 0x20u}, - {0x32u, 0x28u}, - {0x35u, 0x10u}, - {0x37u, 0x01u}, - {0x38u, 0x04u}, - {0x39u, 0x22u}, - {0x3Au, 0x20u}, - {0x3Bu, 0x40u}, - {0x3Du, 0x02u}, - {0x3Fu, 0x10u}, - {0x45u, 0x40u}, - {0x46u, 0x02u}, - {0x58u, 0x98u}, - {0x5Cu, 0x40u}, - {0x5Fu, 0x30u}, - {0x60u, 0x02u}, - {0x62u, 0x14u}, - {0x66u, 0x80u}, - {0x80u, 0x02u}, - {0x81u, 0x02u}, - {0x82u, 0x40u}, - {0x84u, 0x01u}, - {0x85u, 0x80u}, - {0x88u, 0x04u}, - {0x8Au, 0x01u}, - {0x8Bu, 0x20u}, - {0x8Cu, 0x0Au}, - {0x90u, 0x04u}, - {0x92u, 0x08u}, - {0x93u, 0x04u}, - {0x94u, 0x02u}, - {0x95u, 0x64u}, - {0x96u, 0x51u}, - {0x97u, 0xE8u}, - {0x98u, 0x10u}, - {0x99u, 0x01u}, - {0x9Bu, 0x50u}, - {0x9Cu, 0x40u}, - {0x9Du, 0xD2u}, - {0x9Eu, 0x0Au}, - {0x9Fu, 0x01u}, - {0xA0u, 0x02u}, - {0xA1u, 0x04u}, - {0xA2u, 0x80u}, - {0xA3u, 0x11u}, - {0xA4u, 0x04u}, - {0xA5u, 0x0Au}, - {0xA6u, 0x10u}, - {0xABu, 0x10u}, + {0x00u, 0x90u}, + {0x01u, 0x04u}, + {0x05u, 0x80u}, + {0x06u, 0x88u}, + {0x07u, 0x10u}, + {0x09u, 0x01u}, + {0x0Au, 0x06u}, + {0x0Bu, 0x20u}, + {0x0Eu, 0x1Au}, + {0x11u, 0x50u}, + {0x12u, 0x40u}, + {0x16u, 0x22u}, + {0x17u, 0x20u}, + {0x1Bu, 0x40u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x1Au}, + {0x21u, 0x02u}, + {0x22u, 0x80u}, + {0x23u, 0x80u}, + {0x25u, 0x40u}, + {0x26u, 0x02u}, + {0x27u, 0x08u}, + {0x28u, 0x88u}, + {0x2Bu, 0x12u}, + {0x2Cu, 0x02u}, + {0x2Fu, 0x04u}, + {0x31u, 0x26u}, + {0x36u, 0x02u}, + {0x37u, 0x28u}, + {0x38u, 0xA0u}, + {0x39u, 0x08u}, + {0x3Bu, 0x20u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x88u}, + {0x58u, 0x40u}, + {0x63u, 0x01u}, + {0x87u, 0x01u}, + {0x88u, 0x80u}, + {0x89u, 0x10u}, + {0x8Au, 0x02u}, + {0x8Bu, 0x04u}, + {0x8Fu, 0x08u}, + {0x90u, 0xB2u}, + {0x91u, 0x5Du}, + {0x93u, 0x80u}, + {0x94u, 0x04u}, + {0x95u, 0x20u}, + {0x96u, 0x1Au}, + {0x99u, 0x04u}, + {0x9Au, 0x20u}, + {0x9Bu, 0x10u}, + {0x9Fu, 0x20u}, + {0xA1u, 0xA0u}, + {0xA2u, 0x08u}, + {0xA3u, 0x12u}, + {0xA6u, 0x90u}, + {0xA7u, 0x01u}, + {0xA9u, 0x05u}, + {0xABu, 0x01u}, + {0xADu, 0x08u}, {0xAFu, 0x20u}, - {0xB1u, 0x20u}, + {0xB1u, 0x04u}, + {0xB3u, 0x08u}, {0xB4u, 0x40u}, - {0xB5u, 0x01u}, - {0xC0u, 0x6Bu}, - {0xC2u, 0x7Eu}, - {0xC4u, 0xEDu}, - {0xCAu, 0x2Du}, - {0xCCu, 0xA6u}, - {0xCEu, 0xABu}, - {0xD6u, 0x1Eu}, - {0xD8u, 0x1Eu}, - {0xE0u, 0x01u}, - {0xE2u, 0x28u}, - {0xEAu, 0x02u}, - {0xEEu, 0x01u}, - {0x00u, 0x02u}, + {0xB6u, 0x04u}, + {0xB7u, 0x80u}, + {0xC0u, 0xF7u}, + {0xC2u, 0xEFu}, + {0xC4u, 0xEBu}, + {0xCAu, 0x3Fu}, + {0xCCu, 0xE7u}, + {0xCEu, 0x5Eu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE2u, 0x18u}, + {0xE6u, 0x48u}, + {0xEAu, 0x06u}, + {0xEEu, 0x05u}, + {0x01u, 0x0Du}, + {0x04u, 0x7Fu}, + {0x05u, 0x02u}, + {0x06u, 0x80u}, + {0x07u, 0x08u}, {0x09u, 0x01u}, - {0x14u, 0x01u}, - {0x28u, 0x04u}, - {0x2Du, 0x02u}, - {0x30u, 0x02u}, - {0x31u, 0x01u}, - {0x34u, 0x04u}, - {0x36u, 0x01u}, - {0x37u, 0x02u}, - {0x3Eu, 0x51u}, - {0x3Fu, 0x41u}, - {0x40u, 0x24u}, - {0x41u, 0x03u}, - {0x42u, 0x10u}, - {0x45u, 0xFCu}, - {0x46u, 0xD2u}, - {0x47u, 0x0Eu}, - {0x48u, 0x1Fu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Fu, 0x2Cu}, - {0x56u, 0x01u}, + {0x0Au, 0xFFu}, + {0x0Bu, 0x02u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x9Fu}, + {0x0Fu, 0x0Du}, + {0x10u, 0x80u}, + {0x11u, 0x0Du}, + {0x14u, 0xC0u}, + {0x15u, 0x10u}, + {0x16u, 0x08u}, + {0x18u, 0xC0u}, + {0x19u, 0x02u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x04u}, + {0x1Cu, 0xC0u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x02u}, + {0x20u, 0x90u}, + {0x21u, 0x0Du}, + {0x22u, 0x40u}, + {0x25u, 0x0Du}, + {0x26u, 0x60u}, + {0x28u, 0x1Fu}, + {0x29u, 0x0Du}, + {0x2Au, 0x20u}, + {0x2Cu, 0xC0u}, + {0x2Eu, 0x01u}, + {0x35u, 0x10u}, + {0x36u, 0xFFu}, + {0x37u, 0x0Fu}, + {0x39u, 0x20u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x40u}, + {0x54u, 0x09u}, + {0x56u, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Du, 0x01u}, {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x66u, 0x80u}, - {0x68u, 0x40u}, - {0x69u, 0x40u}, - {0x6Eu, 0x08u}, - {0x84u, 0x0Bu}, - {0x86u, 0x14u}, - {0x8Du, 0x01u}, - {0x90u, 0x34u}, - {0x92u, 0x0Bu}, - {0x96u, 0x3Fu}, - {0x98u, 0x08u}, - {0x9Au, 0x22u}, - {0x9Eu, 0x10u}, - {0xA8u, 0x01u}, - {0xAFu, 0x02u}, - {0xB2u, 0x07u}, - {0xB3u, 0x02u}, - {0xB4u, 0x38u}, - {0xB5u, 0x01u}, - {0xBFu, 0x10u}, - {0xD4u, 0x09u}, - {0xD6u, 0x04u}, + {0x80u, 0x20u}, + {0x81u, 0x02u}, + {0x82u, 0x90u}, + {0x83u, 0x11u}, + {0x88u, 0x4Du}, + {0x8Au, 0xB2u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x01u}, + {0x94u, 0x08u}, + {0x95u, 0x01u}, + {0x96u, 0x44u}, + {0x97u, 0x02u}, + {0x99u, 0x02u}, + {0x9Bu, 0x09u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x22u}, + {0x9Fu, 0x05u}, + {0xA8u, 0x04u}, + {0xAAu, 0x09u}, + {0xB0u, 0xC0u}, + {0xB1u, 0x04u}, + {0xB2u, 0x03u}, + {0xB3u, 0x03u}, + {0xB4u, 0x3Cu}, + {0xB5u, 0x10u}, + {0xB7u, 0x08u}, + {0xBBu, 0x08u}, + {0xBEu, 0x15u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x90u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x02u, 0x40u}, - {0x05u, 0x04u}, - {0x08u, 0x08u}, - {0x0Du, 0x42u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x20u}, - {0x12u, 0x04u}, - {0x17u, 0x10u}, - {0x18u, 0x04u}, - {0x19u, 0x01u}, - {0x1Bu, 0x40u}, - {0x1Du, 0x0Cu}, - {0x1Eu, 0x24u}, - {0x1Fu, 0x30u}, - {0x23u, 0x81u}, - {0x27u, 0x24u}, - {0x28u, 0x06u}, - {0x2Au, 0x10u}, - {0x2Cu, 0x02u}, - {0x3Au, 0x10u}, - {0x3Eu, 0x80u}, - {0x41u, 0x0Au}, - {0x42u, 0x04u}, - {0x43u, 0x40u}, - {0x49u, 0x08u}, - {0x4Bu, 0x02u}, - {0x50u, 0x10u}, - {0x51u, 0x40u}, - {0x52u, 0x08u}, - {0x53u, 0x40u}, - {0x59u, 0x21u}, - {0x5Bu, 0x84u}, + {0x01u, 0x01u}, + {0x03u, 0x08u}, + {0x04u, 0xA4u}, + {0x09u, 0x84u}, + {0x0Cu, 0x10u}, + {0x0Eu, 0x99u}, + {0x12u, 0x08u}, + {0x16u, 0x06u}, + {0x17u, 0x05u}, + {0x19u, 0x08u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x02u}, + {0x1Du, 0x40u}, + {0x21u, 0x28u}, + {0x22u, 0x84u}, + {0x23u, 0x40u}, + {0x25u, 0x40u}, + {0x27u, 0x04u}, + {0x2Cu, 0x10u}, + {0x2Eu, 0x12u}, + {0x31u, 0x28u}, + {0x32u, 0x80u}, + {0x35u, 0x40u}, + {0x37u, 0x29u}, + {0x3Bu, 0x41u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x21u}, + {0x5Bu, 0x80u}, {0x5Cu, 0x40u}, - {0x5Du, 0x10u}, + {0x5Du, 0x20u}, {0x5Eu, 0x02u}, {0x5Fu, 0x04u}, - {0x60u, 0x14u}, - {0x63u, 0x81u}, - {0x64u, 0x40u}, - {0x65u, 0x80u}, - {0x68u, 0x04u}, - {0x69u, 0x49u}, - {0x70u, 0x09u}, - {0x72u, 0x0Au}, - {0x83u, 0x01u}, - {0x86u, 0x08u}, - {0x88u, 0x20u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x04u}, - {0x8Cu, 0x98u}, - {0x90u, 0x90u}, + {0x66u, 0x01u}, + {0x67u, 0x02u}, + {0x82u, 0x01u}, + {0x8Au, 0x01u}, + {0x8Bu, 0x08u}, + {0x8Du, 0x01u}, + {0x90u, 0x12u}, + {0x91u, 0x55u}, + {0x93u, 0xA1u}, + {0x94u, 0x04u}, + {0x96u, 0x0Eu}, + {0x97u, 0x08u}, + {0x99u, 0x01u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x40u}, + {0x9Du, 0x80u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x20u}, + {0xA1u, 0x84u}, + {0xA2u, 0x08u}, + {0xA3u, 0x40u}, + {0xA4u, 0x42u}, + {0xA5u, 0x01u}, + {0xA6u, 0x10u}, + {0xA9u, 0x04u}, + {0xB1u, 0x10u}, + {0xB4u, 0x08u}, + {0xC0u, 0xEAu}, + {0xC2u, 0xF5u}, + {0xC4u, 0xF2u}, + {0xCAu, 0xE0u}, + {0xCCu, 0xFEu}, + {0xCEu, 0xF9u}, + {0xD6u, 0xF8u}, + {0xD8u, 0x90u}, + {0xE2u, 0x08u}, + {0xE6u, 0x48u}, + {0xEAu, 0x04u}, + {0x91u, 0x40u}, {0x92u, 0x08u}, - {0x93u, 0x10u}, - {0x94u, 0x22u}, - {0x95u, 0x67u}, - {0x96u, 0x15u}, - {0x97u, 0xE8u}, - {0x98u, 0x02u}, - {0x99u, 0x20u}, - {0x9Au, 0x94u}, - {0x9Bu, 0x58u}, - {0x9Cu, 0x60u}, - {0x9Du, 0x58u}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x10u}, - {0xA1u, 0x06u}, - {0xA2u, 0x80u}, - {0xA3u, 0x11u}, - {0xA4u, 0x04u}, - {0xA5u, 0x48u}, - {0xA6u, 0x30u}, - {0xA7u, 0x02u}, - {0xA8u, 0x40u}, - {0xAAu, 0x02u}, - {0xACu, 0x01u}, - {0xADu, 0x0Au}, - {0xAEu, 0x08u}, - {0xB0u, 0x80u}, - {0xB6u, 0x04u}, - {0xC0u, 0x28u}, - {0xC2u, 0xF4u}, - {0xC4u, 0x42u}, - {0xCAu, 0x18u}, - {0xCEu, 0x14u}, - {0xD0u, 0x0Fu}, - {0xD6u, 0xFFu}, - {0xD8u, 0x9Fu}, - {0xE0u, 0x08u}, - {0xE4u, 0x04u}, - {0xEAu, 0x09u}, - {0xEEu, 0x0Cu}, - {0x08u, 0x14u}, - {0x0Au, 0x43u}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0xE0u}, - {0x0Du, 0x69u}, - {0x0Fu, 0x96u}, - {0x11u, 0x0Fu}, - {0x12u, 0x02u}, - {0x13u, 0xF0u}, - {0x15u, 0x33u}, - {0x17u, 0xCCu}, - {0x18u, 0x21u}, - {0x1Au, 0x12u}, - {0x1Bu, 0xFFu}, - {0x1Du, 0x55u}, - {0x1Eu, 0xECu}, - {0x1Fu, 0xAAu}, - {0x20u, 0x88u}, + {0x93u, 0x80u}, + {0xA1u, 0x40u}, + {0xABu, 0x10u}, + {0xB1u, 0x88u}, + {0xB4u, 0x81u}, + {0xE2u, 0x08u}, + {0xE6u, 0x08u}, + {0xE8u, 0x80u}, + {0xEAu, 0x40u}, + {0x00u, 0xFFu}, + {0x01u, 0x55u}, + {0x03u, 0xAAu}, + {0x09u, 0xFFu}, + {0x0Au, 0xFFu}, + {0x0Du, 0x0Fu}, + {0x0Eu, 0xFFu}, + {0x0Fu, 0xF0u}, + {0x10u, 0x33u}, + {0x12u, 0xCCu}, + {0x13u, 0xFFu}, + {0x17u, 0xFFu}, + {0x18u, 0x55u}, + {0x19u, 0x69u}, + {0x1Au, 0xAAu}, + {0x1Bu, 0x96u}, + {0x1Cu, 0x0Fu}, + {0x1Eu, 0xF0u}, + {0x1Fu, 0xFFu}, {0x21u, 0xFFu}, - {0x22u, 0x13u}, - {0x27u, 0xFFu}, - {0x2Au, 0x01u}, - {0x2Bu, 0xFFu}, - {0x30u, 0x10u}, + {0x22u, 0xFFu}, + {0x24u, 0xFFu}, + {0x2Cu, 0x96u}, + {0x2Du, 0x33u}, + {0x2Eu, 0x69u}, + {0x2Fu, 0xCCu}, {0x31u, 0xFFu}, - {0x34u, 0xE0u}, - {0x36u, 0x0Fu}, + {0x36u, 0xFFu}, + {0x3Au, 0x80u}, {0x3Bu, 0x02u}, - {0x3Eu, 0x11u}, - {0x56u, 0x02u}, - {0x57u, 0x28u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x10u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x40u}, - {0x85u, 0x03u}, - {0x86u, 0x1Fu}, - {0x87u, 0x0Cu}, - {0x89u, 0x50u}, - {0x8Au, 0x70u}, - {0x8Bu, 0xA0u}, - {0x8Cu, 0x03u}, - {0x8Du, 0x0Fu}, - {0x8Eu, 0x0Cu}, - {0x8Fu, 0xF0u}, - {0x90u, 0x20u}, - {0x92u, 0x4Fu}, - {0x94u, 0x10u}, - {0x95u, 0x05u}, - {0x96u, 0x2Fu}, - {0x97u, 0x0Au}, - {0x98u, 0x05u}, - {0x9Au, 0x0Au}, - {0x9Bu, 0xFFu}, - {0x9Fu, 0xFFu}, - {0xA1u, 0x60u}, - {0xA3u, 0x90u}, - {0xA4u, 0x0Fu}, - {0xA5u, 0xFFu}, - {0xA9u, 0x30u}, - {0xABu, 0xC0u}, - {0xACu, 0x06u}, - {0xADu, 0x06u}, - {0xAEu, 0x09u}, - {0xAFu, 0x09u}, - {0xB4u, 0x7Fu}, - {0xB5u, 0xFFu}, - {0xB9u, 0x80u}, - {0xBFu, 0x50u}, + {0x82u, 0x08u}, + {0x83u, 0x80u}, + {0x85u, 0xAAu}, + {0x86u, 0x80u}, + {0x87u, 0x55u}, + {0x88u, 0x0Au}, + {0x8Au, 0x05u}, + {0x8Bu, 0x08u}, + {0x8Eu, 0x07u}, + {0x8Fu, 0x07u}, + {0x91u, 0x44u}, + {0x92u, 0x40u}, + {0x93u, 0x88u}, + {0x95u, 0x99u}, + {0x96u, 0x20u}, + {0x97u, 0x22u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x70u}, + {0x9Cu, 0x04u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x50u}, + {0xA2u, 0xA0u}, + {0xA4u, 0x09u}, + {0xA6u, 0x02u}, + {0xB0u, 0xC0u}, + {0xB2u, 0x30u}, + {0xB3u, 0xF0u}, + {0xB6u, 0x0Fu}, + {0xB7u, 0x0Fu}, + {0xBEu, 0x05u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x20u}, {0x02u, 0x02u}, - {0x03u, 0x20u}, - {0x04u, 0x80u}, - {0x05u, 0x10u}, - {0x08u, 0x10u}, - {0x09u, 0x0Au}, - {0x0Bu, 0x80u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x90u}, - {0x11u, 0x08u}, - {0x12u, 0x01u}, - {0x17u, 0x21u}, - {0x19u, 0x20u}, - {0x1Cu, 0x48u}, - {0x1Du, 0x80u}, - {0x21u, 0x40u}, - {0x22u, 0x20u}, - {0x26u, 0x02u}, - {0x28u, 0x40u}, - {0x29u, 0x02u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x05u}, - {0x2Fu, 0x64u}, - {0x32u, 0x44u}, - {0x33u, 0x10u}, - {0x34u, 0x04u}, - {0x36u, 0x92u}, - {0x38u, 0x04u}, - {0x3Bu, 0x60u}, - {0x3Eu, 0x80u}, - {0x3Fu, 0x20u}, - {0x58u, 0xA0u}, - {0x60u, 0x08u}, - {0x62u, 0x40u}, - {0x67u, 0x10u}, - {0x6Du, 0xC4u}, - {0x6Eu, 0x15u}, - {0x75u, 0xC0u}, - {0x80u, 0x20u}, - {0x82u, 0x08u}, - {0x84u, 0x04u}, - {0x8Au, 0x40u}, - {0x8Bu, 0x40u}, - {0x8Cu, 0x08u}, - {0x8Du, 0x40u}, - {0x90u, 0x80u}, - {0x91u, 0x08u}, - {0x92u, 0x08u}, - {0x93u, 0x18u}, - {0x94u, 0x40u}, - {0x95u, 0x36u}, - {0x96u, 0x11u}, - {0x97u, 0x44u}, - {0x98u, 0x94u}, - {0x9Au, 0x83u}, - {0x9Bu, 0x30u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x50u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x10u}, - {0xA1u, 0x0Eu}, - {0xA2u, 0x90u}, - {0xA3u, 0x31u}, - {0xA4u, 0x02u}, - {0xA5u, 0x40u}, - {0xA6u, 0x21u}, - {0xA7u, 0x02u}, - {0xA9u, 0x08u}, - {0xAAu, 0x01u}, - {0xADu, 0x80u}, - {0xAFu, 0x08u}, - {0xB0u, 0x10u}, - {0xB5u, 0x08u}, - {0xC0u, 0xC7u}, - {0xC2u, 0xDEu}, - {0xC4u, 0x55u}, - {0xCAu, 0xEFu}, - {0xCCu, 0xFEu}, - {0xCEu, 0x3Eu}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x4Cu}, - {0xE2u, 0x02u}, - {0xE6u, 0x1Du}, - {0xEAu, 0x06u}, - {0xECu, 0x04u}, - {0x81u, 0x80u}, - {0x8Bu, 0x0Au}, - {0x8Fu, 0x80u}, - {0x90u, 0x02u}, - {0x92u, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Fu, 0x48u}, - {0xA0u, 0x80u}, - {0xA1u, 0x80u}, - {0xA2u, 0x04u}, - {0xA3u, 0x08u}, - {0xA4u, 0x10u}, - {0xA6u, 0x20u}, - {0xA7u, 0x80u}, - {0xA8u, 0x08u}, - {0xABu, 0x10u}, - {0xADu, 0x21u}, - {0xB3u, 0x10u}, - {0xB4u, 0x08u}, - {0xB5u, 0x02u}, - {0xE0u, 0x40u}, - {0xE2u, 0x22u}, - {0xE4u, 0x80u}, - {0xE6u, 0x0Cu}, - {0xEAu, 0x22u}, - {0xECu, 0x10u}, - {0x00u, 0x06u}, - {0x0Bu, 0x02u}, - {0x0Cu, 0x04u}, - {0x0Eu, 0x03u}, + {0x03u, 0x84u}, + {0x05u, 0x48u}, + {0x07u, 0x48u}, + {0x08u, 0x02u}, + {0x09u, 0x10u}, + {0x0Au, 0x01u}, + {0x0Du, 0x04u}, + {0x0Eu, 0x0Au}, + {0x0Fu, 0x80u}, + {0x10u, 0x01u}, {0x11u, 0x02u}, - {0x13u, 0x04u}, - {0x14u, 0x06u}, + {0x13u, 0x08u}, + {0x17u, 0x05u}, {0x18u, 0x02u}, - {0x1Au, 0x04u}, - {0x1Bu, 0x04u}, - {0x23u, 0x01u}, + {0x1Au, 0x01u}, + {0x1Du, 0x40u}, + {0x1Fu, 0x0Au}, + {0x23u, 0x40u}, + {0x25u, 0x40u}, + {0x27u, 0x10u}, + {0x2Bu, 0x81u}, + {0x31u, 0x20u}, + {0x32u, 0x42u}, + {0x33u, 0x04u}, + {0x36u, 0x03u}, + {0x37u, 0x14u}, + {0x3Au, 0x10u}, + {0x3Bu, 0x41u}, + {0x3Du, 0x89u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x80u}, + {0x59u, 0xA0u}, + {0x5Cu, 0x80u}, + {0x60u, 0x02u}, + {0x61u, 0x10u}, + {0x63u, 0x04u}, + {0x64u, 0x01u}, + {0x66u, 0x80u}, + {0x6Cu, 0x02u}, + {0x6Du, 0x40u}, + {0x6Fu, 0x01u}, + {0x85u, 0x60u}, + {0x8Bu, 0x44u}, + {0x8Fu, 0x0Au}, + {0x91u, 0x09u}, + {0x92u, 0x98u}, + {0x93u, 0x81u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x4Cu}, + {0x9Du, 0x10u}, + {0x9Eu, 0x80u}, + {0xA1u, 0x35u}, + {0xA2u, 0x06u}, + {0xA3u, 0x81u}, + {0xA4u, 0x02u}, + {0xA8u, 0x04u}, + {0xAAu, 0x03u}, + {0xACu, 0x08u}, + {0xADu, 0x80u}, + {0xB0u, 0x80u}, + {0xB6u, 0x46u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xFBu}, + {0xC4u, 0x3Du}, + {0xCAu, 0x09u}, + {0xCCu, 0xEFu}, + {0xCEu, 0xFDu}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x1Cu}, + {0xE2u, 0x38u}, + {0xE6u, 0x22u}, + {0xEAu, 0x48u}, + {0xEEu, 0x90u}, + {0x00u, 0x01u}, + {0x03u, 0xE7u}, + {0x05u, 0x20u}, + {0x09u, 0x08u}, + {0x11u, 0x01u}, + {0x13u, 0x44u}, + {0x15u, 0x61u}, + {0x17u, 0x82u}, + {0x18u, 0x04u}, + {0x19u, 0x10u}, + {0x20u, 0x02u}, + {0x27u, 0x02u}, + {0x28u, 0x08u}, + {0x29u, 0x86u}, + {0x2Bu, 0x61u}, {0x30u, 0x01u}, - {0x31u, 0x06u}, - {0x33u, 0x01u}, - {0x34u, 0x06u}, - {0x3Au, 0x20u}, - {0x3Fu, 0x01u}, - {0x54u, 0x01u}, + {0x31u, 0x07u}, + {0x32u, 0x08u}, + {0x33u, 0x08u}, + {0x34u, 0x04u}, + {0x35u, 0xE0u}, + {0x36u, 0x02u}, + {0x37u, 0x10u}, + {0x3Eu, 0x55u}, + {0x3Fu, 0x44u}, + {0x40u, 0x53u}, + {0x41u, 0x06u}, + {0x42u, 0x40u}, + {0x45u, 0xC2u}, + {0x46u, 0x0Eu}, + {0x47u, 0xDFu}, + {0x48u, 0x37u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x10u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x01u}, {0x5Fu, 0x01u}, - {0x82u, 0xFFu}, - {0x84u, 0x0Fu}, - {0x86u, 0xF0u}, - {0x87u, 0xFFu}, - {0x88u, 0x33u}, - {0x89u, 0xFFu}, - {0x8Au, 0xCCu}, - {0x92u, 0xFFu}, - {0x93u, 0xFFu}, - {0x94u, 0x55u}, - {0x95u, 0x0Fu}, - {0x96u, 0xAAu}, - {0x97u, 0xF0u}, - {0x9Au, 0xFFu}, - {0x9Cu, 0xFFu}, - {0x9Du, 0x33u}, - {0x9Fu, 0xCCu}, - {0xA1u, 0x96u}, - {0xA3u, 0x69u}, - {0xA4u, 0x69u}, - {0xA6u, 0x96u}, - {0xA7u, 0xFFu}, - {0xABu, 0xFFu}, - {0xADu, 0x55u}, - {0xAEu, 0xFFu}, - {0xAFu, 0xAAu}, - {0xB3u, 0xFFu}, - {0xB4u, 0xFFu}, - {0xBAu, 0x20u}, - {0xBBu, 0x08u}, - {0xD8u, 0x04u}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0xADu, 0x01u}, + {0xB1u, 0x01u}, + {0xBFu, 0x01u}, + {0xD6u, 0x08u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x60u}, - {0x01u, 0x12u}, - {0x04u, 0x04u}, - {0x07u, 0x88u}, - {0x09u, 0x08u}, - {0x0Au, 0x08u}, - {0x0Du, 0x42u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x20u}, - {0x14u, 0x02u}, - {0x17u, 0x04u}, - {0x19u, 0x03u}, - {0x1Au, 0x0Cu}, - {0x1Cu, 0x04u}, - {0x1Fu, 0x10u}, - {0x21u, 0x08u}, + {0x06u, 0x80u}, + {0x0Du, 0x20u}, + {0x14u, 0x08u}, + {0x16u, 0x40u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x04u}, + {0x1Fu, 0x04u}, {0x23u, 0x40u}, - {0x26u, 0x08u}, - {0x27u, 0x10u}, - {0x29u, 0x01u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x04u}, - {0x2Fu, 0x81u}, - {0x30u, 0x20u}, - {0x32u, 0x01u}, - {0x34u, 0x02u}, - {0x36u, 0x88u}, - {0x39u, 0x10u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x04u}, - {0x5Au, 0x02u}, - {0x5Bu, 0x42u}, - {0x5Cu, 0x28u}, - {0x5Du, 0x81u}, - {0x65u, 0x40u}, - {0x6Cu, 0x21u}, - {0x6Eu, 0x89u}, - {0x6Fu, 0x08u}, - {0x74u, 0x81u}, - {0x76u, 0x24u}, - {0x80u, 0x20u}, - {0x85u, 0x80u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x84u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x20u}, - {0x90u, 0x40u}, - {0x91u, 0x80u}, - {0x92u, 0x10u}, - {0x93u, 0x02u}, - {0x94u, 0x01u}, - {0x97u, 0x44u}, - {0x98u, 0x02u}, - {0x99u, 0x40u}, - {0x9Bu, 0x06u}, - {0x9Eu, 0x24u}, - {0xA1u, 0x80u}, - {0xA2u, 0x80u}, - {0xA3u, 0x10u}, - {0xA4u, 0x11u}, - {0xA5u, 0x02u}, - {0xA6u, 0x64u}, - {0xA7u, 0x08u}, - {0xAAu, 0x04u}, - {0xACu, 0x01u}, - {0xAEu, 0x03u}, - {0xB0u, 0x40u}, - {0xB7u, 0x04u}, - {0xC0u, 0x79u}, - {0xC2u, 0xF6u}, - {0xC4u, 0xA0u}, - {0xCAu, 0xF1u}, - {0xCCu, 0xD5u}, - {0xCEu, 0x64u}, - {0xD6u, 0xF8u}, - {0xD8u, 0x10u}, - {0xE2u, 0x90u}, - {0xE4u, 0x70u}, - {0xEAu, 0x20u}, - {0xECu, 0x10u}, - {0xEEu, 0x04u}, - {0x81u, 0x40u}, - {0x82u, 0x12u}, - {0x87u, 0x40u}, - {0x89u, 0x40u}, - {0x8Au, 0x20u}, - {0x8Fu, 0x10u}, - {0x90u, 0x40u}, - {0x92u, 0x01u}, - {0x93u, 0x02u}, - {0x94u, 0x01u}, - {0x97u, 0x04u}, - {0x98u, 0x02u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x26u}, - {0xA1u, 0x80u}, - {0xA2u, 0x80u}, - {0xA4u, 0x10u}, - {0xA5u, 0x02u}, - {0xA6u, 0x66u}, - {0xA7u, 0x08u}, - {0xA8u, 0x02u}, - {0xAEu, 0x04u}, + {0x24u, 0x08u}, + {0x25u, 0x88u}, + {0x26u, 0x12u}, + {0x27u, 0x04u}, + {0x2Bu, 0x01u}, + {0x2Du, 0x04u}, + {0x2Eu, 0x20u}, + {0x31u, 0xCCu}, + {0x35u, 0x10u}, + {0x36u, 0x02u}, + {0x37u, 0x04u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x22u}, + {0x3Fu, 0x20u}, + {0x45u, 0x06u}, + {0x46u, 0x30u}, + {0x47u, 0x08u}, + {0x4Cu, 0x84u}, + {0x4Du, 0x04u}, + {0x4Eu, 0x82u}, + {0x54u, 0x08u}, + {0x56u, 0x01u}, + {0x57u, 0x42u}, + {0x58u, 0x20u}, + {0x59u, 0x80u}, + {0x5Cu, 0x01u}, + {0x5Du, 0x20u}, + {0x5Eu, 0x04u}, + {0x5Fu, 0x40u}, + {0x60u, 0x02u}, + {0x63u, 0x09u}, + {0x65u, 0x45u}, + {0x67u, 0x08u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x41u}, + {0x6Eu, 0x10u}, + {0x75u, 0x08u}, + {0x76u, 0x0Au}, + {0x77u, 0x40u}, + {0x80u, 0x04u}, + {0x86u, 0x40u}, + {0x89u, 0x04u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x0Cu}, + {0x92u, 0x88u}, + {0x93u, 0x80u}, + {0x94u, 0x2Cu}, + {0x95u, 0x44u}, + {0x96u, 0x40u}, + {0x98u, 0x28u}, + {0x99u, 0x20u}, + {0x9Au, 0x40u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x08u}, + {0xA1u, 0x23u}, + {0xA2u, 0x04u}, + {0xA3u, 0x91u}, + {0xA4u, 0x02u}, + {0xA6u, 0x92u}, + {0xA7u, 0x42u}, + {0xA9u, 0x01u}, + {0xAAu, 0x10u}, + {0xB0u, 0xA0u}, {0xB2u, 0x04u}, - {0xB3u, 0x08u}, - {0xB4u, 0x90u}, - {0xB7u, 0x04u}, - {0xE0u, 0x90u}, - {0xE2u, 0x48u}, - {0xE4u, 0x02u}, - {0xE6u, 0x80u}, - {0xE8u, 0x40u}, - {0xEAu, 0x02u}, - {0xECu, 0x88u}, - {0xEEu, 0x40u}, - {0x02u, 0x08u}, - {0x05u, 0x01u}, - {0x06u, 0x10u}, - {0x0Cu, 0x0Au}, - {0x0Du, 0x02u}, - {0x0Eu, 0x05u}, - {0x0Fu, 0x04u}, - {0x10u, 0x09u}, - {0x12u, 0x02u}, - {0x17u, 0x04u}, - {0x18u, 0x04u}, - {0x1Au, 0x08u}, - {0x1Bu, 0x02u}, - {0x1Eu, 0x07u}, - {0x20u, 0x20u}, - {0x22u, 0x40u}, - {0x26u, 0x20u}, - {0x2Eu, 0x40u}, - {0x30u, 0x10u}, - {0x33u, 0x06u}, - {0x34u, 0x60u}, - {0x35u, 0x01u}, - {0x36u, 0x0Fu}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x04u}, + {0xB3u, 0x40u}, + {0xB7u, 0x40u}, + {0xC0u, 0x10u}, + {0xC2u, 0x40u}, + {0xC4u, 0x50u}, + {0xCAu, 0x68u}, + {0xCCu, 0xE0u}, + {0xCEu, 0xE0u}, + {0xD0u, 0xC0u}, + {0xD2u, 0x30u}, + {0xD6u, 0xFCu}, + {0xD8u, 0xFCu}, + {0xE2u, 0x50u}, + {0xE4u, 0x80u}, + {0xE6u, 0x48u}, + {0xE8u, 0x0Cu}, + {0xEAu, 0x01u}, + {0xEEu, 0xC2u}, + {0x01u, 0x01u}, + {0x02u, 0x04u}, + {0x03u, 0x06u}, + {0x05u, 0x4Au}, + {0x07u, 0x15u}, + {0x0Fu, 0x40u}, + {0x10u, 0x01u}, + {0x11u, 0x22u}, + {0x13u, 0x45u}, + {0x17u, 0x38u}, + {0x19u, 0x53u}, + {0x1Au, 0x02u}, + {0x1Bu, 0x2Cu}, + {0x21u, 0x01u}, + {0x27u, 0x01u}, + {0x2Cu, 0x02u}, + {0x2Eu, 0x04u}, + {0x30u, 0x06u}, + {0x31u, 0x07u}, + {0x33u, 0x78u}, + {0x34u, 0x01u}, + {0x3Bu, 0x02u}, + {0x3Eu, 0x11u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x10u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x50u}, - {0x85u, 0x09u}, - {0x86u, 0xA0u}, - {0x87u, 0x06u}, - {0x88u, 0x60u}, - {0x89u, 0x03u}, - {0x8Au, 0x90u}, - {0x8Bu, 0x0Cu}, - {0x8Cu, 0x0Fu}, - {0x8Eu, 0xF0u}, - {0x8Fu, 0xFFu}, - {0x91u, 0x0Fu}, - {0x93u, 0xF0u}, - {0x95u, 0x30u}, - {0x97u, 0xC0u}, - {0x9Bu, 0xFFu}, - {0x9Cu, 0x05u}, - {0x9Du, 0x90u}, - {0x9Eu, 0x0Au}, - {0x9Fu, 0x60u}, - {0xA3u, 0xFFu}, - {0xA4u, 0x03u}, - {0xA5u, 0x05u}, - {0xA6u, 0x0Cu}, - {0xA7u, 0x0Au}, - {0xA8u, 0x06u}, - {0xA9u, 0x50u}, - {0xAAu, 0x09u}, - {0xABu, 0xA0u}, - {0xACu, 0x30u}, - {0xAEu, 0xC0u}, - {0xB3u, 0xFFu}, - {0xB6u, 0xFFu}, - {0xBEu, 0x40u}, - {0xBFu, 0x04u}, + {0x82u, 0x07u}, + {0x83u, 0x3Fu}, + {0x85u, 0x10u}, + {0x86u, 0x80u}, + {0x87u, 0x01u}, + {0x8Au, 0x08u}, + {0x8Du, 0x30u}, + {0x8Fu, 0xC0u}, + {0x91u, 0x70u}, + {0x93u, 0x8Cu}, + {0x94u, 0x99u}, + {0x95u, 0x6Fu}, + {0x96u, 0x22u}, + {0x97u, 0x90u}, + {0x99u, 0x57u}, + {0x9Au, 0x70u}, + {0x9Bu, 0xA0u}, + {0x9Cu, 0x44u}, + {0x9Du, 0x03u}, + {0x9Eu, 0x88u}, + {0xA1u, 0x08u}, + {0xA3u, 0x03u}, + {0xA4u, 0xAAu}, + {0xA6u, 0x55u}, + {0xA7u, 0x20u}, + {0xADu, 0x02u}, + {0xB4u, 0xF0u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x0Fu}, + {0xB7u, 0xF0u}, + {0xBBu, 0x80u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x09u}, - {0x02u, 0x02u}, - {0x06u, 0x24u}, - {0x07u, 0x02u}, - {0x09u, 0x02u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x01u}, - {0x11u, 0x04u}, - {0x13u, 0x82u}, - {0x14u, 0x04u}, - {0x16u, 0x02u}, + {0x01u, 0x02u}, + {0x04u, 0x21u}, + {0x05u, 0x08u}, + {0x08u, 0x02u}, + {0x0Au, 0x08u}, + {0x0Eu, 0x2Au}, + {0x10u, 0x02u}, {0x17u, 0x08u}, - {0x18u, 0x40u}, - {0x1Au, 0x05u}, - {0x1Du, 0x80u}, - {0x1Fu, 0x80u}, - {0x20u, 0x08u}, + {0x19u, 0x21u}, + {0x1Cu, 0x01u}, + {0x1Eu, 0x08u}, + {0x1Fu, 0x40u}, + {0x21u, 0x0Bu}, {0x22u, 0x04u}, - {0x24u, 0x20u}, - {0x2Cu, 0x20u}, - {0x2Fu, 0x88u}, - {0x30u, 0x20u}, - {0x33u, 0x08u}, - {0x36u, 0x64u}, - {0x37u, 0x82u}, - {0x38u, 0x04u}, - {0x39u, 0x40u}, - {0x3Cu, 0x20u}, - {0x3Du, 0x04u}, - {0x3Fu, 0x88u}, - {0x58u, 0x40u}, - {0x5Bu, 0x10u}, - {0x5Cu, 0x80u}, - {0x60u, 0x04u}, - {0x62u, 0x80u}, - {0x64u, 0x02u}, - {0x69u, 0x40u}, - {0x6Bu, 0x02u}, - {0x83u, 0x40u}, - {0x88u, 0x24u}, - {0x8Fu, 0x11u}, - {0xC0u, 0xEDu}, - {0xC2u, 0x8Bu}, - {0xC4u, 0xEDu}, - {0xCAu, 0xE0u}, - {0xCCu, 0xF6u}, - {0xCEu, 0x7Au}, - {0xD6u, 0x1Cu}, - {0xD8u, 0x1Cu}, + {0x25u, 0x40u}, + {0x26u, 0x20u}, + {0x27u, 0x08u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x80u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x82u}, + {0x31u, 0x08u}, + {0x32u, 0x22u}, + {0x36u, 0x93u}, + {0x37u, 0x08u}, + {0x38u, 0x08u}, + {0x39u, 0x42u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x82u}, + {0x58u, 0x80u}, + {0x5Au, 0x10u}, + {0x5Bu, 0x04u}, + {0x5Eu, 0x44u}, + {0x5Fu, 0x10u}, + {0x61u, 0x20u}, + {0x63u, 0x22u}, + {0x64u, 0x08u}, + {0x66u, 0x40u}, + {0x67u, 0x20u}, + {0x81u, 0x01u}, + {0x82u, 0x48u}, + {0x83u, 0x88u}, + {0x87u, 0x10u}, + {0x88u, 0x08u}, + {0x89u, 0x40u}, + {0x8Bu, 0x10u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x04u}, + {0xC0u, 0x78u}, + {0xC2u, 0xEAu}, + {0xC4u, 0x21u}, + {0xCAu, 0xD3u}, + {0xCCu, 0xF7u}, + {0xCEu, 0xDBu}, + {0xD6u, 0x7Eu}, + {0xD8u, 0x7Eu}, {0xE0u, 0x40u}, - {0xE4u, 0xA0u}, - {0xE6u, 0x02u}, + {0xE2u, 0xA0u}, + {0xE6u, 0x20u}, {0x00u, 0x09u}, {0x02u, 0x06u}, - {0x04u, 0x03u}, - {0x05u, 0x03u}, - {0x06u, 0x0Cu}, - {0x07u, 0x0Cu}, - {0x08u, 0x05u}, + {0x04u, 0x30u}, + {0x05u, 0x30u}, + {0x06u, 0xC0u}, + {0x07u, 0xC0u}, {0x09u, 0x50u}, - {0x0Au, 0x0Au}, + {0x0Au, 0xFFu}, {0x0Bu, 0xA0u}, - {0x0Du, 0x0Fu}, - {0x0Fu, 0xF0u}, - {0x10u, 0x0Fu}, - {0x12u, 0xF0u}, - {0x15u, 0x05u}, + {0x0Cu, 0x05u}, + {0x0Du, 0x06u}, + {0x0Eu, 0x0Au}, + {0x0Fu, 0x09u}, + {0x11u, 0x0Fu}, + {0x13u, 0xF0u}, {0x16u, 0xFFu}, - {0x17u, 0x0Au}, - {0x18u, 0xFFu}, + {0x1Au, 0xFFu}, {0x1Bu, 0xFFu}, - {0x1Cu, 0x90u}, - {0x1Du, 0xFFu}, - {0x1Eu, 0x60u}, - {0x20u, 0xFFu}, - {0x21u, 0x60u}, - {0x23u, 0x90u}, - {0x24u, 0x50u}, - {0x26u, 0xA0u}, - {0x27u, 0xFFu}, - {0x28u, 0x30u}, - {0x29u, 0x30u}, - {0x2Au, 0xC0u}, - {0x2Bu, 0xC0u}, - {0x2Du, 0x06u}, - {0x2Fu, 0x09u}, + {0x1Cu, 0x0Fu}, + {0x1Du, 0x03u}, + {0x1Eu, 0xF0u}, + {0x1Fu, 0x0Cu}, + {0x20u, 0x03u}, + {0x21u, 0x05u}, + {0x22u, 0x0Cu}, + {0x23u, 0x0Au}, + {0x25u, 0xFFu}, + {0x28u, 0x50u}, + {0x2Au, 0xA0u}, + {0x2Bu, 0xFFu}, + {0x2Cu, 0x90u}, + {0x2Du, 0x60u}, + {0x2Eu, 0x60u}, + {0x2Fu, 0x90u}, {0x30u, 0xFFu}, {0x31u, 0xFFu}, {0x3Eu, 0x01u}, @@ -1414,411 +1519,492 @@ void cyfitter_cfg(void) {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Fu, 0x01u}, - {0x80u, 0x22u}, - {0x82u, 0x10u}, - {0x83u, 0x9Fu}, - {0x84u, 0x17u}, - {0x85u, 0xC0u}, - {0x86u, 0x28u}, - {0x87u, 0x04u}, - {0x88u, 0x29u}, - {0x89u, 0xC0u}, - {0x8Au, 0x16u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x16u}, - {0x8Du, 0x80u}, - {0x90u, 0x04u}, - {0x91u, 0x7Fu}, - {0x93u, 0x80u}, - {0x94u, 0x40u}, - {0x97u, 0x60u}, - {0x98u, 0x12u}, - {0x99u, 0x1Fu}, - {0x9Au, 0x04u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x16u}, - {0x9Du, 0xC0u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x31u}, - {0xA1u, 0xC0u}, - {0xA2u, 0x0Eu}, - {0xA3u, 0x02u}, - {0xA4u, 0x40u}, - {0xA7u, 0xFFu}, - {0xA8u, 0x10u}, - {0xAAu, 0x06u}, - {0xACu, 0x06u}, - {0xADu, 0x90u}, - {0xAEu, 0x10u}, - {0xAFu, 0x40u}, - {0xB0u, 0x30u}, - {0xB2u, 0x40u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0xFFu}, - {0xB8u, 0x28u}, - {0xBAu, 0x02u}, + {0x80u, 0x01u}, + {0x81u, 0x68u}, + {0x85u, 0x12u}, + {0x87u, 0xE1u}, + {0x89u, 0x08u}, + {0x8Bu, 0x60u}, + {0x8Fu, 0x08u}, + {0x91u, 0x60u}, + {0x93u, 0x08u}, + {0x95u, 0x28u}, + {0x97u, 0x40u}, + {0x99u, 0x91u}, + {0x9Bu, 0x64u}, + {0x9Du, 0x06u}, + {0xA1u, 0x68u}, + {0xA5u, 0x40u}, + {0xA9u, 0x71u}, + {0xABu, 0x82u}, + {0xADu, 0x20u}, + {0xB1u, 0x07u}, + {0xB3u, 0xF0u}, + {0xB5u, 0x08u}, + {0xB6u, 0x01u}, + {0xB9u, 0x0Au}, {0xBFu, 0x10u}, + {0xC0u, 0x62u}, + {0xC1u, 0x03u}, + {0xC2u, 0x10u}, + {0xC4u, 0x04u}, + {0xC5u, 0xBEu}, + {0xC6u, 0xFDu}, + {0xC7u, 0xBCu}, + {0xC8u, 0x3Fu}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x22u}, + {0xCEu, 0xF0u}, + {0xCFu, 0x08u}, + {0xD0u, 0x04u}, {0xD4u, 0x40u}, {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDAu, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x09u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x02u, 0x48u}, - {0x05u, 0x91u}, - {0x07u, 0x20u}, - {0x08u, 0x50u}, - {0x0Au, 0x20u}, - {0x0Bu, 0x40u}, - {0x0Eu, 0x25u}, - {0x0Fu, 0x80u}, - {0x10u, 0x84u}, - {0x12u, 0x10u}, - {0x15u, 0x50u}, - {0x17u, 0x09u}, - {0x1Bu, 0x02u}, - {0x1Du, 0x15u}, - {0x1Eu, 0x40u}, - {0x1Fu, 0x20u}, - {0x21u, 0x01u}, - {0x27u, 0x08u}, - {0x28u, 0x54u}, - {0x2Au, 0x48u}, - {0x2Bu, 0x05u}, - {0x2Du, 0x40u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x20u}, + {0xE2u, 0xC0u}, + {0xE4u, 0x40u}, + {0xE5u, 0x01u}, + {0xE6u, 0x10u}, + {0xE7u, 0x11u}, + {0xE8u, 0xC0u}, + {0xE9u, 0x01u}, + {0xEBu, 0x11u}, + {0xECu, 0x40u}, + {0xEDu, 0x01u}, + {0xEEu, 0x40u}, + {0xEFu, 0x01u}, + {0x00u, 0x92u}, + {0x01u, 0x04u}, + {0x02u, 0x41u}, + {0x03u, 0x08u}, + {0x04u, 0x02u}, + {0x08u, 0x10u}, + {0x0Au, 0x26u}, + {0x0Bu, 0x22u}, + {0x10u, 0x81u}, + {0x11u, 0x50u}, + {0x1Bu, 0x01u}, + {0x1Fu, 0x40u}, + {0x21u, 0x02u}, + {0x24u, 0x20u}, + {0x26u, 0x18u}, + {0x27u, 0x60u}, + {0x28u, 0x11u}, + {0x2Au, 0x01u}, + {0x2Bu, 0x08u}, + {0x2Eu, 0x4Au}, + {0x2Fu, 0x04u}, {0x30u, 0x80u}, - {0x32u, 0x5Cu}, - {0x33u, 0x10u}, - {0x35u, 0x84u}, - {0x37u, 0x21u}, - {0x38u, 0x04u}, - {0x3Au, 0x10u}, - {0x3Bu, 0x60u}, - {0x3Du, 0x12u}, - {0x3Eu, 0x54u}, - {0x64u, 0xA0u}, - {0x66u, 0x20u}, - {0x67u, 0x01u}, - {0x84u, 0x80u}, - {0x8Eu, 0x04u}, - {0x90u, 0x04u}, - {0x91u, 0x40u}, - {0x92u, 0x9Du}, - {0x93u, 0x61u}, - {0x95u, 0x02u}, - {0x98u, 0x60u}, - {0x99u, 0x80u}, - {0x9Au, 0x28u}, - {0x9Bu, 0x31u}, - {0x9Du, 0x15u}, - {0xA1u, 0x01u}, - {0xA2u, 0x14u}, - {0xA3u, 0x45u}, - {0xA7u, 0x02u}, - {0xA8u, 0x05u}, - {0xAAu, 0x01u}, - {0xB1u, 0x30u}, - {0xB2u, 0x80u}, - {0xC0u, 0xFEu}, - {0xC2u, 0xFFu}, - {0xC4u, 0xFEu}, - {0xCAu, 0xDFu}, - {0xCCu, 0xFEu}, + {0x32u, 0x11u}, + {0x35u, 0x80u}, + {0x36u, 0x04u}, + {0x37u, 0x61u}, + {0x39u, 0x14u}, + {0x3Au, 0x40u}, + {0x3Cu, 0x04u}, + {0x3Eu, 0x91u}, + {0x44u, 0x80u}, + {0x45u, 0xA8u}, + {0x4Cu, 0x40u}, + {0x4Eu, 0x08u}, + {0x4Fu, 0x04u}, + {0x54u, 0x02u}, + {0x56u, 0x98u}, + {0x5Eu, 0x20u}, + {0x5Fu, 0x10u}, + {0x66u, 0x90u}, + {0x67u, 0x50u}, + {0x80u, 0x80u}, + {0x84u, 0x40u}, + {0x87u, 0x40u}, + {0x88u, 0xC0u}, + {0x8Bu, 0x40u}, + {0x8Fu, 0x01u}, + {0x90u, 0x16u}, + {0x91u, 0x54u}, + {0x92u, 0x55u}, + {0x93u, 0x28u}, + {0x94u, 0xA0u}, + {0x96u, 0x02u}, + {0x97u, 0x04u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x01u}, + {0x9Cu, 0x40u}, + {0x9Du, 0x80u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x20u}, + {0xA0u, 0x01u}, + {0xA1u, 0xA8u}, + {0xA2u, 0x04u}, + {0xA4u, 0xC2u}, + {0xA5u, 0x02u}, + {0xA7u, 0x01u}, + {0xAAu, 0x10u}, + {0xACu, 0x01u}, + {0xC0u, 0x1Fu}, + {0xC2u, 0x07u}, + {0xC4u, 0x0Bu}, + {0xCAu, 0xFFu}, + {0xCCu, 0xFDu}, {0xCEu, 0xFEu}, + {0xD0u, 0xF0u}, + {0xD2u, 0x20u}, {0xD8u, 0xF0u}, - {0xE2u, 0x40u}, - {0xEAu, 0x04u}, - {0x80u, 0x08u}, - {0x82u, 0x84u}, - {0x87u, 0x80u}, - {0x88u, 0x02u}, - {0x8Au, 0x41u}, - {0x8Bu, 0x07u}, - {0x8Cu, 0x04u}, - {0x8Eu, 0x28u}, - {0x90u, 0x53u}, - {0x91u, 0xAAu}, - {0x92u, 0xACu}, - {0x93u, 0x55u}, - {0x94u, 0x01u}, - {0x95u, 0x99u}, - {0x96u, 0x12u}, - {0x97u, 0x22u}, - {0x9Bu, 0x70u}, - {0xA3u, 0x08u}, - {0xA5u, 0x44u}, - {0xA7u, 0x88u}, - {0xB0u, 0x0Fu}, - {0xB3u, 0x0Fu}, - {0xB4u, 0xC0u}, - {0xB5u, 0xF0u}, - {0xB6u, 0x30u}, - {0xBEu, 0x51u}, + {0xE2u, 0x22u}, + {0xEEu, 0x08u}, + {0x01u, 0x41u}, + {0x04u, 0x91u}, + {0x05u, 0x41u}, + {0x06u, 0x0Eu}, + {0x08u, 0x08u}, + {0x09u, 0x40u}, + {0x0Au, 0x10u}, + {0x0Cu, 0x6Cu}, + {0x10u, 0x24u}, + {0x11u, 0x01u}, + {0x13u, 0x40u}, + {0x14u, 0x40u}, + {0x15u, 0x04u}, + {0x16u, 0x2Cu}, + {0x18u, 0x80u}, + {0x19u, 0x88u}, + {0x1Au, 0x2Fu}, + {0x1Bu, 0x61u}, + {0x1Cu, 0x6Cu}, + {0x1Du, 0x81u}, + {0x1Fu, 0x40u}, + {0x20u, 0x2Cu}, + {0x21u, 0x41u}, + {0x22u, 0x40u}, + {0x24u, 0xB1u}, + {0x25u, 0xE2u}, + {0x26u, 0x02u}, + {0x27u, 0x08u}, + {0x28u, 0x64u}, + {0x29u, 0x47u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x98u}, + {0x2Du, 0x10u}, + {0x30u, 0x80u}, + {0x31u, 0x08u}, + {0x32u, 0x0Fu}, + {0x34u, 0x31u}, + {0x35u, 0x3Fu}, + {0x36u, 0x40u}, + {0x37u, 0xC0u}, + {0x39u, 0x20u}, + {0x3Au, 0x30u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x41u}, + {0x3Fu, 0x11u}, + {0x56u, 0x02u}, + {0x57u, 0x2Cu}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Fu, 0x01u}, + {0x80u, 0x06u}, + {0x82u, 0x09u}, + {0x84u, 0x30u}, + {0x86u, 0xC0u}, + {0x88u, 0xFFu}, + {0x8Cu, 0x05u}, + {0x8Eu, 0x0Au}, + {0x91u, 0x01u}, + {0x96u, 0xFFu}, + {0x9Au, 0xFFu}, + {0x9Cu, 0x0Fu}, + {0x9Eu, 0xF0u}, + {0xA0u, 0x03u}, + {0xA1u, 0x01u}, + {0xA2u, 0x0Cu}, + {0xA5u, 0x01u}, + {0xA8u, 0x50u}, + {0xAAu, 0xA0u}, + {0xACu, 0x60u}, + {0xADu, 0x01u}, + {0xAEu, 0x90u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x01u}, + {0xB9u, 0x20u}, + {0xBEu, 0x10u}, + {0xBFu, 0x10u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x20u}, - {0x01u, 0x01u}, - {0x02u, 0x01u}, - {0x05u, 0x95u}, - {0x07u, 0x08u}, - {0x08u, 0x20u}, - {0x09u, 0x10u}, - {0x0Bu, 0x50u}, - {0x0Cu, 0x02u}, - {0x0Eu, 0x09u}, - {0x15u, 0x64u}, - {0x17u, 0x21u}, - {0x18u, 0x02u}, - {0x19u, 0x20u}, - {0x1Au, 0x80u}, - {0x1Eu, 0x28u}, - {0x20u, 0x04u}, - {0x21u, 0x20u}, - {0x23u, 0x10u}, - {0x24u, 0x01u}, - {0x25u, 0x10u}, - {0x26u, 0x03u}, - {0x27u, 0x21u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x20u}, - {0x2Eu, 0x85u}, - {0x31u, 0x2Au}, - {0x35u, 0x81u}, - {0x37u, 0x28u}, - {0x39u, 0x08u}, + {0x00u, 0x92u}, + {0x01u, 0x04u}, + {0x02u, 0x40u}, + {0x05u, 0x20u}, + {0x06u, 0x0Au}, + {0x07u, 0x20u}, + {0x0Au, 0x06u}, + {0x0Bu, 0x20u}, + {0x0Du, 0x20u}, + {0x0Eu, 0x91u}, + {0x10u, 0x80u}, + {0x11u, 0x52u}, + {0x16u, 0x20u}, + {0x17u, 0x11u}, + {0x1Bu, 0x10u}, + {0x1Cu, 0x04u}, + {0x1Du, 0xA8u}, + {0x1Eu, 0x22u}, + {0x1Fu, 0x25u}, + {0x22u, 0x10u}, + {0x24u, 0x40u}, + {0x26u, 0x40u}, + {0x27u, 0x08u}, + {0x2Bu, 0x51u}, + {0x2Cu, 0x02u}, + {0x2Eu, 0x22u}, + {0x2Fu, 0x24u}, + {0x31u, 0x02u}, + {0x36u, 0x40u}, + {0x37u, 0x25u}, + {0x3Au, 0x04u}, + {0x3Bu, 0x08u}, + {0x3Du, 0x08u}, + {0x3Eu, 0x11u}, + {0x5Eu, 0xC0u}, + {0x67u, 0x80u}, + {0x6Du, 0x08u}, + {0x6Eu, 0x19u}, + {0x6Fu, 0x11u}, + {0x76u, 0x02u}, + {0x90u, 0x12u}, + {0x91u, 0x54u}, + {0x92u, 0x04u}, + {0x93u, 0xA0u}, + {0x94u, 0xE4u}, + {0x96u, 0x13u}, + {0x97u, 0x0Eu}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x40u}, + {0x9Du, 0xA0u}, + {0x9Eu, 0x66u}, + {0x9Fu, 0x29u}, + {0xA3u, 0x40u}, + {0xA4u, 0x42u}, + {0xA5u, 0x01u}, + {0xA6u, 0x55u}, + {0xAFu, 0x02u}, + {0xB5u, 0x08u}, + {0xC0u, 0xEFu}, + {0xC2u, 0xF7u}, + {0xC4u, 0x7Bu}, + {0xCAu, 0xFBu}, + {0xCCu, 0xF1u}, + {0xCEu, 0xE0u}, + {0xD8u, 0x80u}, + {0xE2u, 0x08u}, + {0xE8u, 0x08u}, + {0xEAu, 0x40u}, + {0x39u, 0x20u}, + {0x3Fu, 0x10u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x27u, 0x08u}, + {0x87u, 0x08u}, + {0x91u, 0x40u}, + {0x92u, 0x08u}, + {0x93u, 0x80u}, + {0xA1u, 0x40u}, + {0xE8u, 0x08u}, + {0x85u, 0x40u}, + {0x8Bu, 0x40u}, + {0x8Du, 0x40u}, + {0x91u, 0x40u}, + {0x93u, 0x80u}, + {0xA1u, 0x40u}, + {0xAEu, 0x04u}, + {0xE2u, 0xC0u}, + {0xE6u, 0x80u}, + {0x13u, 0x10u}, + {0x17u, 0x48u}, + {0x33u, 0x02u}, + {0x36u, 0x80u}, + {0x37u, 0x08u}, + {0x3Au, 0x01u}, {0x3Bu, 0x10u}, - {0x3Cu, 0x01u}, - {0x3Du, 0x48u}, - {0x3Eu, 0x10u}, - {0x47u, 0x29u}, - {0x4Cu, 0x04u}, - {0x4Eu, 0x02u}, - {0x4Fu, 0x05u}, - {0x54u, 0x02u}, - {0x55u, 0x05u}, - {0x56u, 0xA0u}, - {0x57u, 0x40u}, - {0x7Au, 0x80u}, - {0x7Bu, 0x40u}, - {0x89u, 0x20u}, - {0x8Eu, 0x40u}, - {0x91u, 0x4Du}, - {0x92u, 0x1Du}, - {0x93u, 0x60u}, - {0x94u, 0x04u}, - {0x95u, 0x32u}, - {0x96u, 0x80u}, - {0x97u, 0x04u}, - {0x98u, 0x40u}, - {0x99u, 0x80u}, - {0x9Au, 0x0Au}, - {0x9Bu, 0x10u}, - {0x9Du, 0x10u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x10u}, - {0xA1u, 0x0Au}, - {0xA3u, 0x25u}, - {0xA4u, 0x02u}, - {0xA6u, 0x01u}, - {0xA7u, 0x02u}, - {0xA9u, 0x02u}, - {0xADu, 0x01u}, - {0xB3u, 0x10u}, - {0xB5u, 0x20u}, - {0xB7u, 0x04u}, - {0xC0u, 0xFBu}, - {0xC2u, 0xDCu}, - {0xC4u, 0xF0u}, - {0xCAu, 0xD3u}, - {0xCCu, 0xF7u}, - {0xCEu, 0xF6u}, - {0xD0u, 0xE0u}, - {0xD2u, 0x30u}, - {0xEAu, 0x08u}, - {0xEEu, 0x06u}, - {0x8Eu, 0x20u}, - {0xA0u, 0x80u}, - {0xA4u, 0x10u}, - {0xA6u, 0x20u}, - {0xA8u, 0x01u}, - {0xAEu, 0x01u}, - {0xB3u, 0x08u}, - {0xB6u, 0x04u}, - {0xB7u, 0x40u}, - {0xE0u, 0x30u}, - {0xE8u, 0x10u}, - {0xEAu, 0x60u}, - {0xEEu, 0x02u}, - {0xA8u, 0x80u}, - {0xB0u, 0x10u}, - {0xECu, 0x80u}, - {0x12u, 0x08u}, - {0x15u, 0x80u}, - {0x17u, 0x04u}, - {0x33u, 0x04u}, - {0x36u, 0x28u}, - {0x39u, 0x88u}, - {0x3Du, 0x44u}, - {0x43u, 0x80u}, - {0x56u, 0x08u}, - {0x5Au, 0x08u}, - {0x5Cu, 0x08u}, + {0x3Cu, 0x80u}, + {0x3Eu, 0x08u}, + {0x43u, 0x10u}, + {0x53u, 0x20u}, + {0x59u, 0x04u}, {0x61u, 0x10u}, - {0x65u, 0x04u}, - {0x81u, 0x80u}, - {0x83u, 0x10u}, - {0x87u, 0x80u}, - {0x89u, 0x80u}, - {0x8Au, 0x04u}, + {0x66u, 0x40u}, + {0x67u, 0x08u}, + {0x89u, 0x08u}, + {0x8Au, 0x40u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x40u}, + {0xD4u, 0x20u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x20u}, - {0xE6u, 0x90u}, - {0x30u, 0x20u}, {0x32u, 0x04u}, - {0x34u, 0x01u}, - {0x36u, 0x40u}, - {0x51u, 0x80u}, - {0x57u, 0x10u}, - {0x59u, 0x80u}, - {0x62u, 0x08u}, - {0x81u, 0x04u}, - {0x82u, 0x08u}, + {0x33u, 0x40u}, + {0x34u, 0x08u}, + {0x35u, 0x80u}, + {0x3Au, 0x40u}, + {0x50u, 0x80u}, + {0x52u, 0x02u}, + {0x55u, 0x08u}, + {0x66u, 0x80u}, + {0x80u, 0x80u}, + {0x82u, 0x02u}, {0x84u, 0x08u}, - {0x8Au, 0x08u}, - {0x95u, 0x4Cu}, - {0x99u, 0x80u}, - {0x9Cu, 0x08u}, + {0x8Au, 0x80u}, + {0x97u, 0x08u}, + {0x9Bu, 0x40u}, {0x9Du, 0x14u}, {0x9Eu, 0x08u}, - {0xA1u, 0x80u}, - {0xA3u, 0x10u}, - {0xA6u, 0x20u}, + {0x9Fu, 0x10u}, + {0xA1u, 0x08u}, + {0xA4u, 0x40u}, + {0xA6u, 0x80u}, + {0xA7u, 0x22u}, + {0xB6u, 0x01u}, {0xCCu, 0xF0u}, + {0xCEu, 0x10u}, {0xD4u, 0xE0u}, - {0xD8u, 0x40u}, - {0xE2u, 0x20u}, - {0xE6u, 0x90u}, - {0x12u, 0x20u}, - {0x81u, 0x40u}, - {0x85u, 0x04u}, - {0x95u, 0x4Cu}, + {0xD6u, 0x80u}, + {0xE2u, 0xA0u}, + {0xE6u, 0x10u}, + {0x12u, 0x80u}, + {0x85u, 0x80u}, + {0x8Cu, 0x80u}, + {0x8Du, 0x04u}, {0x96u, 0x08u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x10u}, - {0xA4u, 0x20u}, - {0xA6u, 0x60u}, + {0x9Du, 0x94u}, + {0x9Eu, 0x48u}, + {0x9Fu, 0x10u}, + {0xA6u, 0x80u}, + {0xA7u, 0x22u}, + {0xACu, 0x40u}, + {0xAFu, 0x04u}, {0xC4u, 0x10u}, {0xE2u, 0x10u}, - {0xE6u, 0x20u}, - {0x73u, 0x01u}, - {0x84u, 0x20u}, - {0x86u, 0x24u}, - {0x8Fu, 0x01u}, - {0x95u, 0x04u}, + {0xEAu, 0x40u}, + {0xEEu, 0x10u}, + {0x83u, 0x10u}, + {0x86u, 0x44u}, + {0x8Fu, 0x40u}, {0x96u, 0x08u}, {0x9Du, 0x10u}, - {0xA4u, 0x20u}, - {0xA6u, 0x40u}, - {0xACu, 0x01u}, - {0xDCu, 0x20u}, - {0xE2u, 0x40u}, - {0xE6u, 0x50u}, - {0xEAu, 0x40u}, - {0x09u, 0x80u}, - {0x0Fu, 0x80u}, + {0x9Eu, 0x48u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x80u}, + {0xA7u, 0x22u}, + {0xE2u, 0x30u}, + {0xE6u, 0x10u}, + {0x08u, 0x80u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x01u}, {0x10u, 0x10u}, - {0x53u, 0x80u}, - {0x54u, 0x04u}, - {0x59u, 0x20u}, - {0x5Fu, 0x80u}, - {0x84u, 0x10u}, - {0x8Fu, 0x40u}, - {0xC2u, 0x06u}, - {0xC4u, 0x08u}, + {0x14u, 0x40u}, + {0x50u, 0x10u}, + {0x53u, 0x02u}, + {0x54u, 0x02u}, + {0x56u, 0x20u}, + {0x8Bu, 0x18u}, + {0x8Eu, 0x04u}, + {0xC2u, 0x0Eu}, + {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0xE6u, 0x02u}, - {0x00u, 0x02u}, - {0x03u, 0x01u}, - {0x04u, 0x42u}, - {0x0Bu, 0x22u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x20u}, - {0x85u, 0x20u}, - {0x86u, 0x01u}, - {0x8Cu, 0x40u}, - {0x9Du, 0x20u}, - {0x9Fu, 0x01u}, - {0xA4u, 0x04u}, - {0xAFu, 0x81u}, - {0xB3u, 0x80u}, - {0xB5u, 0x80u}, + {0xE2u, 0x04u}, + {0xE6u, 0x09u}, + {0x01u, 0x01u}, + {0x02u, 0x04u}, + {0x07u, 0x48u}, + {0x0Bu, 0x41u}, + {0x0Cu, 0x82u}, + {0x87u, 0x04u}, + {0x94u, 0x20u}, + {0x97u, 0x01u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x08u}, + {0xA7u, 0x02u}, + {0xA8u, 0x02u}, + {0xABu, 0x01u}, + {0xACu, 0x80u}, + {0xAEu, 0x20u}, + {0xB0u, 0x51u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE2u, 0x02u}, - {0xEAu, 0x08u}, - {0xECu, 0x04u}, - {0x8Fu, 0x10u}, - {0x90u, 0x02u}, - {0xA3u, 0x10u}, - {0xA4u, 0x04u}, - {0xABu, 0x01u}, - {0xB0u, 0x01u}, - {0xB3u, 0x10u}, - {0xE2u, 0x08u}, {0xEAu, 0x05u}, - {0x09u, 0x02u}, + {0xEEu, 0x04u}, + {0x84u, 0x04u}, + {0x87u, 0x40u}, + {0x8Cu, 0x10u}, + {0x91u, 0x01u}, + {0x93u, 0x40u}, + {0x94u, 0x20u}, + {0x97u, 0x08u}, + {0x9Bu, 0x40u}, + {0xA7u, 0x02u}, + {0xACu, 0x80u}, + {0xB4u, 0x02u}, + {0xE4u, 0x02u}, + {0xEEu, 0x02u}, + {0x08u, 0x04u}, {0x0Bu, 0x08u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x40u}, - {0x80u, 0x01u}, - {0x85u, 0x02u}, - {0x87u, 0x04u}, - {0x90u, 0x02u}, - {0x96u, 0x04u}, - {0xA4u, 0x04u}, - {0xAEu, 0x04u}, + {0x0Eu, 0x21u}, + {0x86u, 0x11u}, + {0x97u, 0x08u}, + {0x9Cu, 0x04u}, + {0xA7u, 0x02u}, + {0xB1u, 0x01u}, + {0xB7u, 0x40u}, {0xC2u, 0x0Fu}, - {0x95u, 0x04u}, - {0x9Du, 0x10u}, - {0xA2u, 0x20u}, - {0xAEu, 0x40u}, - {0xEEu, 0x40u}, + {0xEAu, 0x08u}, + {0xEEu, 0x01u}, + {0x67u, 0x80u}, + {0x87u, 0x40u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x80u}, + {0xA3u, 0x40u}, + {0xA7u, 0x22u}, + {0xB5u, 0x10u}, + {0xD8u, 0x80u}, + {0xE2u, 0x10u}, {0x07u, 0x40u}, - {0x52u, 0x20u}, - {0x57u, 0x80u}, - {0x85u, 0x04u}, - {0x8Fu, 0x80u}, - {0x95u, 0x04u}, - {0x9Fu, 0x40u}, - {0xA2u, 0x20u}, - {0xA9u, 0x10u}, - {0xABu, 0x40u}, + {0x50u, 0x80u}, + {0x57u, 0x40u}, + {0x83u, 0x40u}, + {0x87u, 0x02u}, + {0x8Au, 0x08u}, + {0x9Eu, 0x08u}, + {0xA0u, 0x80u}, + {0xA3u, 0x40u}, + {0xA7u, 0x02u}, + {0xABu, 0x20u}, {0xC0u, 0x20u}, {0xD4u, 0x60u}, - {0xE6u, 0x40u}, - {0xECu, 0x80u}, + {0xE2u, 0x10u}, + {0xE4u, 0x80u}, {0xEEu, 0x20u}, - {0x88u, 0x04u}, - {0xA4u, 0x04u}, - {0xAFu, 0x40u}, - {0xE0u, 0x04u}, - {0x10u, 0x03u}, - {0x1Au, 0x03u}, + {0xAFu, 0x02u}, + {0x01u, 0x02u}, + {0x89u, 0x02u}, + {0xC0u, 0x08u}, + {0xE2u, 0x01u}, + {0x10u, 0x01u}, + {0x11u, 0x01u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x01u}, {0x00u, 0xFDu}, - {0x01u, 0xABu}, - {0x02u, 0x02u}, + {0x01u, 0xAFu}, + {0x02u, 0x0Au}, {0x10u, 0x55u}, }; @@ -1841,31 +2027,18 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = { - 0x01u, 0x00u, 0x00u, 0x75u, 0x04u, 0x00u, 0x00u, 0x08u, 0x08u, 0x88u, 0x61u, 0x64u, 0x01u, 0x64u, 0x00u, 0x88u, - 0x10u, 0x24u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x70u, 0x00u, 0x07u, 0x40u, 0x10u, 0x01u, 0xECu, 0x00u, 0x00u, - 0xA2u, 0xECu, 0x08u, 0x00u, 0x01u, 0xACu, 0x00u, 0x40u, 0x07u, 0x00u, 0xD8u, 0x00u, 0x01u, 0x40u, 0x00u, 0x02u, - 0x00u, 0x80u, 0x3Fu, 0x71u, 0xE0u, 0x08u, 0x00u, 0x07u, 0x08u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x04u, 0x11u, - 0x34u, 0x02u, 0x50u, 0x00u, 0x06u, 0xDEu, 0xFCu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 3842dd2..c2cf04a 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -26,10 +26,10 @@ /* SCSI_TX_DMA_COMPLETE */ .set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3 .set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 .set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -54,32 +54,32 @@ /* SD_RX_DMA_COMPLETE */ .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08 -.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4 .set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SD_TX_DMA_COMPLETE */ .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5 .set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -94,41 +94,59 @@ /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL + +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB00_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB00_ST /* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 @@ -143,15 +161,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL /* USBFS_arb_int */ .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -176,24 +194,24 @@ /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -632,40 +650,40 @@ /* SCSI_RST_ISR */ .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x400 -.set SCSI_RST_ISR__INTC_NUMBER, 10 +.set SCSI_RST_ISR__INTC_MASK, 0x04 +.set SCSI_RST_ISR__INTC_NUMBER, 2 .set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 .set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 @@ -680,8 +698,8 @@ .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB05_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -691,26 +709,26 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1 +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB05_06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB05_06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB05_06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB05_06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB05_06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB05_06_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB05_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB05_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB05_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB05_F1 /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1200,11 +1218,281 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT12_AG +.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP +.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT12_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Noise__0__MASK, 0x20 +.set SCSI_Noise__0__PC, CYREG_PRT12_PC5 +.set SCSI_Noise__0__PORT, 12 +.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT12_PS +.set SCSI_Noise__0__SHIFT, 5 +.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW +.set SCSI_Noise__1__AG, CYREG_PRT6_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT6_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__1__MASK, 0x10 +.set SCSI_Noise__1__PC, CYREG_PRT6_PC4 +.set SCSI_Noise__1__PORT, 6 +.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT6_PS +.set SCSI_Noise__1__SHIFT, 4 +.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__2__AG, CYREG_PRT5_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT5_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Noise__2__MASK, 0x01 +.set SCSI_Noise__2__PC, CYREG_PRT5_PC0 +.set SCSI_Noise__2__PORT, 5 +.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT5_PS +.set SCSI_Noise__2__SHIFT, 0 +.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW +.set SCSI_Noise__3__AG, CYREG_PRT6_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT6_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__3__MASK, 0x40 +.set SCSI_Noise__3__PC, CYREG_PRT6_PC6 +.set SCSI_Noise__3__PORT, 6 +.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT6_PS +.set SCSI_Noise__3__SHIFT, 6 +.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__4__AG, CYREG_PRT6_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT6_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__4__MASK, 0x20 +.set SCSI_Noise__4__PC, CYREG_PRT6_PC5 +.set SCSI_Noise__4__PORT, 6 +.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT6_PS +.set SCSI_Noise__4__SHIFT, 5 +.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x20 +.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5 +.set SCSI_Noise__ACK__PORT, 6 +.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS +.set SCSI_Noise__ACK__SHIFT, 5 +.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG +.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP +.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Noise__ATN__MASK, 0x20 +.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5 +.set SCSI_Noise__ATN__PORT, 12 +.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS +.set SCSI_Noise__ATN__SHIFT, 5 +.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x10 +.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4 +.set SCSI_Noise__BSY__PORT, 6 +.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS +.set SCSI_Noise__BSY__SHIFT, 4 +.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT6_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT6_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__RST__MASK, 0x40 +.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6 +.set SCSI_Noise__RST__PORT, 6 +.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT6_PS +.set SCSI_Noise__RST__SHIFT, 6 +.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x01 +.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0 +.set SCSI_Noise__SEL__PORT, 5 +.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS +.set SCSI_Noise__SEL__SHIFT, 0 +.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW + /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1214,58 +1502,58 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1280,40 +1568,40 @@ /* USBFS_ep_1 */ .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x20 -.set USBFS_ep_1__INTC_NUMBER, 5 +.set USBFS_ep_1__INTC_MASK, 0x40 +.set USBFS_ep_1__INTC_NUMBER, 6 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x40 -.set USBFS_ep_2__INTC_NUMBER, 6 +.set USBFS_ep_2__INTC_MASK, 0x80 +.set USBFS_ep_2__INTC_NUMBER, 7 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x80 -.set USBFS_ep_3__INTC_NUMBER, 7 +.set USBFS_ep_3__INTC_MASK, 0x100 +.set USBFS_ep_3__INTC_NUMBER, 8 .set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x100 -.set USBFS_ep_4__INTC_NUMBER, 8 +.set USBFS_ep_4__INTC_MASK, 0x200 +.set USBFS_ep_4__INTC_NUMBER, 9 .set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -1467,41 +1755,6 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 .set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -/* SCSI_ATN */ -.set SCSI_ATN__0__MASK, 0x20 -.set SCSI_ATN__0__PC, CYREG_PRT12_PC5 -.set SCSI_ATN__0__PORT, 12 -.set SCSI_ATN__0__SHIFT, 5 -.set SCSI_ATN__AG, CYREG_PRT12_AG -.set SCSI_ATN__BIE, CYREG_PRT12_BIE -.set SCSI_ATN__BIT_MASK, CYREG_PRT12_BIT_MASK -.set SCSI_ATN__BYP, CYREG_PRT12_BYP -.set SCSI_ATN__DM0, CYREG_PRT12_DM0 -.set SCSI_ATN__DM1, CYREG_PRT12_DM1 -.set SCSI_ATN__DM2, CYREG_PRT12_DM2 -.set SCSI_ATN__DR, CYREG_PRT12_DR -.set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS -.set SCSI_ATN__INT__MASK, 0x20 -.set SCSI_ATN__INT__PC, CYREG_PRT12_PC5 -.set SCSI_ATN__INT__PORT, 12 -.set SCSI_ATN__INT__SHIFT, 5 -.set SCSI_ATN__MASK, 0x20 -.set SCSI_ATN__PORT, 12 -.set SCSI_ATN__PRT, CYREG_PRT12_PRT -.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN -.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 -.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 -.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 -.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 -.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT -.set SCSI_ATN__PS, CYREG_PRT12_PS -.set SCSI_ATN__SHIFT, 5 -.set SCSI_ATN__SIO_CFG, CYREG_PRT12_SIO_CFG -.set SCSI_ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF -.set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN -.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ -.set SCSI_ATN__SLW, CYREG_PRT12_SLW - /* SCSI_CLK */ .set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 .set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 @@ -2055,44 +2308,6 @@ .set SCSI_Out__SEL__SHIFT, 3 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW -/* SCSI_RST */ -.set SCSI_RST__0__MASK, 0x40 -.set SCSI_RST__0__PC, CYREG_PRT6_PC6 -.set SCSI_RST__0__PORT, 6 -.set SCSI_RST__0__SHIFT, 6 -.set SCSI_RST__AG, CYREG_PRT6_AG -.set SCSI_RST__AMUX, CYREG_PRT6_AMUX -.set SCSI_RST__BIE, CYREG_PRT6_BIE -.set SCSI_RST__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_RST__BYP, CYREG_PRT6_BYP -.set SCSI_RST__CTL, CYREG_PRT6_CTL -.set SCSI_RST__DM0, CYREG_PRT6_DM0 -.set SCSI_RST__DM1, CYREG_PRT6_DM1 -.set SCSI_RST__DM2, CYREG_PRT6_DM2 -.set SCSI_RST__DR, CYREG_PRT6_DR -.set SCSI_RST__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_RST__INTSTAT, CYREG_PICU6_INTSTAT -.set SCSI_RST__INT__MASK, 0x40 -.set SCSI_RST__INT__PC, CYREG_PRT6_PC6 -.set SCSI_RST__INT__PORT, 6 -.set SCSI_RST__INT__SHIFT, 6 -.set SCSI_RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_RST__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_RST__MASK, 0x40 -.set SCSI_RST__PORT, 6 -.set SCSI_RST__PRT, CYREG_PRT6_PRT -.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_RST__PS, CYREG_PRT6_PS -.set SCSI_RST__SHIFT, 6 -.set SCSI_RST__SLW, CYREG_PRT6_SLW -.set SCSI_RST__SNAP, CYREG_PICU6_SNAP - /* USBFS_Dm */ .set USBFS_Dm__0__MASK, 0x80 .set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 @@ -2200,8 +2415,8 @@ .set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS .set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG .set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__1__MASK, 0x10 -.set SCSI_In__1__PC, CYREG_PRT6_PC4 +.set SCSI_In__1__MASK, 0x80 +.set SCSI_In__1__PC, CYREG_PRT6_PC7 .set SCSI_In__1__PORT, 6 .set SCSI_In__1__PRT, CYREG_PRT6_PRT .set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL @@ -2212,62 +2427,62 @@ .set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 .set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT .set SCSI_In__1__PS, CYREG_PRT6_PS -.set SCSI_In__1__SHIFT, 4 +.set SCSI_In__1__SHIFT, 7 .set SCSI_In__1__SLW, CYREG_PRT6_SLW -.set SCSI_In__2__AG, CYREG_PRT6_AG -.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__2__BIE, CYREG_PRT6_BIE -.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__2__BYP, CYREG_PRT6_BYP -.set SCSI_In__2__CTL, CYREG_PRT6_CTL -.set SCSI_In__2__DM0, CYREG_PRT6_DM0 -.set SCSI_In__2__DM1, CYREG_PRT6_DM1 -.set SCSI_In__2__DM2, CYREG_PRT6_DM2 -.set SCSI_In__2__DR, CYREG_PRT6_DR -.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__2__MASK, 0x20 -.set SCSI_In__2__PC, CYREG_PRT6_PC5 -.set SCSI_In__2__PORT, 6 -.set SCSI_In__2__PRT, CYREG_PRT6_PRT -.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__2__PS, CYREG_PRT6_PS -.set SCSI_In__2__SHIFT, 5 -.set SCSI_In__2__SLW, CYREG_PRT6_SLW -.set SCSI_In__3__AG, CYREG_PRT6_AG -.set SCSI_In__3__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__3__BIE, CYREG_PRT6_BIE -.set SCSI_In__3__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__3__BYP, CYREG_PRT6_BYP -.set SCSI_In__3__CTL, CYREG_PRT6_CTL -.set SCSI_In__3__DM0, CYREG_PRT6_DM0 -.set SCSI_In__3__DM1, CYREG_PRT6_DM1 -.set SCSI_In__3__DM2, CYREG_PRT6_DM2 -.set SCSI_In__3__DR, CYREG_PRT6_DR -.set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__3__MASK, 0x80 -.set SCSI_In__3__PC, CYREG_PRT6_PC7 -.set SCSI_In__3__PORT, 6 -.set SCSI_In__3__PRT, CYREG_PRT6_PRT -.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__3__PS, CYREG_PRT6_PS -.set SCSI_In__3__SHIFT, 7 -.set SCSI_In__3__SLW, CYREG_PRT6_SLW +.set SCSI_In__2__AG, CYREG_PRT5_AG +.set SCSI_In__2__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__2__BIE, CYREG_PRT5_BIE +.set SCSI_In__2__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__2__BYP, CYREG_PRT5_BYP +.set SCSI_In__2__CTL, CYREG_PRT5_CTL +.set SCSI_In__2__DM0, CYREG_PRT5_DM0 +.set SCSI_In__2__DM1, CYREG_PRT5_DM1 +.set SCSI_In__2__DM2, CYREG_PRT5_DM2 +.set SCSI_In__2__DR, CYREG_PRT5_DR +.set SCSI_In__2__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__2__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__2__MASK, 0x02 +.set SCSI_In__2__PC, CYREG_PRT5_PC1 +.set SCSI_In__2__PORT, 5 +.set SCSI_In__2__PRT, CYREG_PRT5_PRT +.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__2__PS, CYREG_PRT5_PS +.set SCSI_In__2__SHIFT, 1 +.set SCSI_In__2__SLW, CYREG_PRT5_SLW +.set SCSI_In__3__AG, CYREG_PRT5_AG +.set SCSI_In__3__AMUX, CYREG_PRT5_AMUX +.set SCSI_In__3__BIE, CYREG_PRT5_BIE +.set SCSI_In__3__BIT_MASK, CYREG_PRT5_BIT_MASK +.set SCSI_In__3__BYP, CYREG_PRT5_BYP +.set SCSI_In__3__CTL, CYREG_PRT5_CTL +.set SCSI_In__3__DM0, CYREG_PRT5_DM0 +.set SCSI_In__3__DM1, CYREG_PRT5_DM1 +.set SCSI_In__3__DM2, CYREG_PRT5_DM2 +.set SCSI_In__3__DR, CYREG_PRT5_DR +.set SCSI_In__3__INP_DIS, CYREG_PRT5_INP_DIS +.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG +.set SCSI_In__3__LCD_EN, CYREG_PRT5_LCD_EN +.set SCSI_In__3__MASK, 0x04 +.set SCSI_In__3__PC, CYREG_PRT5_PC2 +.set SCSI_In__3__PORT, 5 +.set SCSI_In__3__PRT, CYREG_PRT5_PRT +.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL +.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN +.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 +.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 +.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 +.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 +.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT +.set SCSI_In__3__PS, CYREG_PRT5_PS +.set SCSI_In__3__SHIFT, 2 +.set SCSI_In__3__SLW, CYREG_PRT5_SLW .set SCSI_In__4__AG, CYREG_PRT5_AG .set SCSI_In__4__AMUX, CYREG_PRT5_AMUX .set SCSI_In__4__BIE, CYREG_PRT5_BIE @@ -2281,8 +2496,8 @@ .set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS .set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG .set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_In__4__MASK, 0x01 -.set SCSI_In__4__PC, CYREG_PRT5_PC0 +.set SCSI_In__4__MASK, 0x08 +.set SCSI_In__4__PC, CYREG_PRT5_PC3 .set SCSI_In__4__PORT, 5 .set SCSI_In__4__PRT, CYREG_PRT5_PRT .set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL @@ -2293,143 +2508,8 @@ .set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 .set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT .set SCSI_In__4__PS, CYREG_PRT5_PS -.set SCSI_In__4__SHIFT, 0 +.set SCSI_In__4__SHIFT, 3 .set SCSI_In__4__SLW, CYREG_PRT5_SLW -.set SCSI_In__5__AG, CYREG_PRT5_AG -.set SCSI_In__5__AMUX, CYREG_PRT5_AMUX -.set SCSI_In__5__BIE, CYREG_PRT5_BIE -.set SCSI_In__5__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_In__5__BYP, CYREG_PRT5_BYP -.set SCSI_In__5__CTL, CYREG_PRT5_CTL -.set SCSI_In__5__DM0, CYREG_PRT5_DM0 -.set SCSI_In__5__DM1, CYREG_PRT5_DM1 -.set SCSI_In__5__DM2, CYREG_PRT5_DM2 -.set SCSI_In__5__DR, CYREG_PRT5_DR -.set SCSI_In__5__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_In__5__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_In__5__MASK, 0x02 -.set SCSI_In__5__PC, CYREG_PRT5_PC1 -.set SCSI_In__5__PORT, 5 -.set SCSI_In__5__PRT, CYREG_PRT5_PRT -.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_In__5__PS, CYREG_PRT5_PS -.set SCSI_In__5__SHIFT, 1 -.set SCSI_In__5__SLW, CYREG_PRT5_SLW -.set SCSI_In__6__AG, CYREG_PRT5_AG -.set SCSI_In__6__AMUX, CYREG_PRT5_AMUX -.set SCSI_In__6__BIE, CYREG_PRT5_BIE -.set SCSI_In__6__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_In__6__BYP, CYREG_PRT5_BYP -.set SCSI_In__6__CTL, CYREG_PRT5_CTL -.set SCSI_In__6__DM0, CYREG_PRT5_DM0 -.set SCSI_In__6__DM1, CYREG_PRT5_DM1 -.set SCSI_In__6__DM2, CYREG_PRT5_DM2 -.set SCSI_In__6__DR, CYREG_PRT5_DR -.set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_In__6__MASK, 0x04 -.set SCSI_In__6__PC, CYREG_PRT5_PC2 -.set SCSI_In__6__PORT, 5 -.set SCSI_In__6__PRT, CYREG_PRT5_PRT -.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_In__6__PS, CYREG_PRT5_PS -.set SCSI_In__6__SHIFT, 2 -.set SCSI_In__6__SLW, CYREG_PRT5_SLW -.set SCSI_In__7__AG, CYREG_PRT5_AG -.set SCSI_In__7__AMUX, CYREG_PRT5_AMUX -.set SCSI_In__7__BIE, CYREG_PRT5_BIE -.set SCSI_In__7__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_In__7__BYP, CYREG_PRT5_BYP -.set SCSI_In__7__CTL, CYREG_PRT5_CTL -.set SCSI_In__7__DM0, CYREG_PRT5_DM0 -.set SCSI_In__7__DM1, CYREG_PRT5_DM1 -.set SCSI_In__7__DM2, CYREG_PRT5_DM2 -.set SCSI_In__7__DR, CYREG_PRT5_DR -.set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_In__7__MASK, 0x08 -.set SCSI_In__7__PC, CYREG_PRT5_PC3 -.set SCSI_In__7__PORT, 5 -.set SCSI_In__7__PRT, CYREG_PRT5_PRT -.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_In__7__PS, CYREG_PRT5_PS -.set SCSI_In__7__SHIFT, 3 -.set SCSI_In__7__SLW, CYREG_PRT5_SLW -.set SCSI_In__ACK__AG, CYREG_PRT6_AG -.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE -.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP -.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL -.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0 -.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1 -.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2 -.set SCSI_In__ACK__DR, CYREG_PRT6_DR -.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__ACK__MASK, 0x20 -.set SCSI_In__ACK__PC, CYREG_PRT6_PC5 -.set SCSI_In__ACK__PORT, 6 -.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT -.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__ACK__PS, CYREG_PRT6_PS -.set SCSI_In__ACK__SHIFT, 5 -.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW -.set SCSI_In__BSY__AG, CYREG_PRT6_AG -.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE -.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP -.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL -.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0 -.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1 -.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2 -.set SCSI_In__BSY__DR, CYREG_PRT6_DR -.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__BSY__MASK, 0x10 -.set SCSI_In__BSY__PC, CYREG_PRT6_PC4 -.set SCSI_In__BSY__PORT, 6 -.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT -.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__BSY__PS, CYREG_PRT6_PS -.set SCSI_In__BSY__SHIFT, 4 -.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW .set SCSI_In__CD__AG, CYREG_PRT5_AG .set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX .set SCSI_In__CD__BIE, CYREG_PRT5_BIE @@ -2565,33 +2645,6 @@ .set SCSI_In__REQ__PS, CYREG_PRT5_PS .set SCSI_In__REQ__SHIFT, 2 .set SCSI_In__REQ__SLW, CYREG_PRT5_SLW -.set SCSI_In__SEL__AG, CYREG_PRT5_AG -.set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX -.set SCSI_In__SEL__BIE, CYREG_PRT5_BIE -.set SCSI_In__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK -.set SCSI_In__SEL__BYP, CYREG_PRT5_BYP -.set SCSI_In__SEL__CTL, CYREG_PRT5_CTL -.set SCSI_In__SEL__DM0, CYREG_PRT5_DM0 -.set SCSI_In__SEL__DM1, CYREG_PRT5_DM1 -.set SCSI_In__SEL__DM2, CYREG_PRT5_DM2 -.set SCSI_In__SEL__DR, CYREG_PRT5_DR -.set SCSI_In__SEL__INP_DIS, CYREG_PRT5_INP_DIS -.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG -.set SCSI_In__SEL__LCD_EN, CYREG_PRT5_LCD_EN -.set SCSI_In__SEL__MASK, 0x01 -.set SCSI_In__SEL__PC, CYREG_PRT5_PC0 -.set SCSI_In__SEL__PORT, 5 -.set SCSI_In__SEL__PRT, CYREG_PRT5_PRT -.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL -.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN -.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0 -.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1 -.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0 -.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1 -.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT -.set SCSI_In__SEL__PS, CYREG_PRT5_PS -.set SCSI_In__SEL__SHIFT, 0 -.set SCSI_In__SEL__SLW, CYREG_PRT5_SLW /* SD_DAT1 */ .set SD_DAT1__0__MASK, 0x01 @@ -2923,7 +2976,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000001E +.set CYDEV_INTR_RISING, 0x0000003E .set CYDEV_PROJ_TYPE, 2 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 .set CYDEV_PROJ_TYPE_LOADABLE, 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 9ce179e..0332128 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -26,10 +26,10 @@ SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA_COMPLETE */ SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -54,32 +54,32 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 /* SD_RX_DMA_COMPLETE */ SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SD_TX_DMA_COMPLETE */ SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -94,41 +94,59 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL + +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST /* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -143,15 +161,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL /* USBFS_arb_int */ USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -176,24 +194,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -632,40 +650,40 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW /* SCSI_RST_ISR */ SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x400 -SCSI_RST_ISR__INTC_NUMBER EQU 10 +SCSI_RST_ISR__INTC_MASK EQU 0x04 +SCSI_RST_ISR__INTC_NUMBER EQU 2 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -680,8 +698,8 @@ SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -691,26 +709,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1 /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1200,11 +1218,281 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT12_AG +SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT12_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__0__MASK EQU 0x20 +SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__0__PORT EQU 12 +SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT12_PS +SCSI_Noise__0__SHIFT EQU 5 +SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x10 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 4 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT5_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT5_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__2__MASK EQU 0x01 +SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__2__PORT EQU 5 +SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT5_PS +SCSI_Noise__2__SHIFT EQU 0 +SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW +SCSI_Noise__3__AG EQU CYREG_PRT6_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT6_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__3__PORT EQU 6 +SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT6_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x20 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 5 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x20 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 5 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG +SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__ATN__MASK EQU 0x20 +SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__ATN__PORT EQU 12 +SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS +SCSI_Noise__ATN__SHIFT EQU 5 +SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x10 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 4 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT6_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT6_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__RST__PORT EQU 6 +SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT6_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x01 +SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__SEL__PORT EQU 5 +SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS +SCSI_Noise__SEL__SHIFT EQU 0 +SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW + /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1214,58 +1502,58 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1280,40 +1568,40 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_1 */ USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x20 -USBFS_ep_1__INTC_NUMBER EQU 5 +USBFS_ep_1__INTC_MASK EQU 0x40 +USBFS_ep_1__INTC_NUMBER EQU 6 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x40 -USBFS_ep_2__INTC_NUMBER EQU 6 +USBFS_ep_2__INTC_MASK EQU 0x80 +USBFS_ep_2__INTC_NUMBER EQU 7 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x80 -USBFS_ep_3__INTC_NUMBER EQU 7 +USBFS_ep_3__INTC_MASK EQU 0x100 +USBFS_ep_3__INTC_NUMBER EQU 8 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x100 -USBFS_ep_4__INTC_NUMBER EQU 8 +USBFS_ep_4__INTC_MASK EQU 0x200 +USBFS_ep_4__INTC_NUMBER EQU 9 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -1467,41 +1755,6 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -/* SCSI_ATN */ -SCSI_ATN__0__MASK EQU 0x20 -SCSI_ATN__0__PC EQU CYREG_PRT12_PC5 -SCSI_ATN__0__PORT EQU 12 -SCSI_ATN__0__SHIFT EQU 5 -SCSI_ATN__AG EQU CYREG_PRT12_AG -SCSI_ATN__BIE EQU CYREG_PRT12_BIE -SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_ATN__BYP EQU CYREG_PRT12_BYP -SCSI_ATN__DM0 EQU CYREG_PRT12_DM0 -SCSI_ATN__DM1 EQU CYREG_PRT12_DM1 -SCSI_ATN__DM2 EQU CYREG_PRT12_DM2 -SCSI_ATN__DR EQU CYREG_PRT12_DR -SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_ATN__INT__MASK EQU 0x20 -SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5 -SCSI_ATN__INT__PORT EQU 12 -SCSI_ATN__INT__SHIFT EQU 5 -SCSI_ATN__MASK EQU 0x20 -SCSI_ATN__PORT EQU 12 -SCSI_ATN__PRT EQU CYREG_PRT12_PRT -SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_ATN__PS EQU CYREG_PRT12_PS -SCSI_ATN__SHIFT EQU 5 -SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_ATN__SLW EQU CYREG_PRT12_SLW - /* SCSI_CLK */ SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 @@ -2055,44 +2308,6 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 3 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW -/* SCSI_RST */ -SCSI_RST__0__MASK EQU 0x40 -SCSI_RST__0__PC EQU CYREG_PRT6_PC6 -SCSI_RST__0__PORT EQU 6 -SCSI_RST__0__SHIFT EQU 6 -SCSI_RST__AG EQU CYREG_PRT6_AG -SCSI_RST__AMUX EQU CYREG_PRT6_AMUX -SCSI_RST__BIE EQU CYREG_PRT6_BIE -SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_RST__BYP EQU CYREG_PRT6_BYP -SCSI_RST__CTL EQU CYREG_PRT6_CTL -SCSI_RST__DM0 EQU CYREG_PRT6_DM0 -SCSI_RST__DM1 EQU CYREG_PRT6_DM1 -SCSI_RST__DM2 EQU CYREG_PRT6_DM2 -SCSI_RST__DR EQU CYREG_PRT6_DR -SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT -SCSI_RST__INT__MASK EQU 0x40 -SCSI_RST__INT__PC EQU CYREG_PRT6_PC6 -SCSI_RST__INT__PORT EQU 6 -SCSI_RST__INT__SHIFT EQU 6 -SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_RST__MASK EQU 0x40 -SCSI_RST__PORT EQU 6 -SCSI_RST__PRT EQU CYREG_PRT6_PRT -SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_RST__PS EQU CYREG_PRT6_PS -SCSI_RST__SHIFT EQU 6 -SCSI_RST__SLW EQU CYREG_PRT6_SLW -SCSI_RST__SNAP EQU CYREG_PICU6_SNAP - /* USBFS_Dm */ USBFS_Dm__0__MASK EQU 0x80 USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 @@ -2200,8 +2415,8 @@ SCSI_In__1__DR EQU CYREG_PRT6_DR SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__1__MASK EQU 0x10 -SCSI_In__1__PC EQU CYREG_PRT6_PC4 +SCSI_In__1__MASK EQU 0x80 +SCSI_In__1__PC EQU CYREG_PRT6_PC7 SCSI_In__1__PORT EQU 6 SCSI_In__1__PRT EQU CYREG_PRT6_PRT SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL @@ -2212,62 +2427,62 @@ SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT SCSI_In__1__PS EQU CYREG_PRT6_PS -SCSI_In__1__SHIFT EQU 4 +SCSI_In__1__SHIFT EQU 7 SCSI_In__1__SLW EQU CYREG_PRT6_SLW -SCSI_In__2__AG EQU CYREG_PRT6_AG -SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__2__BIE EQU CYREG_PRT6_BIE -SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__2__BYP EQU CYREG_PRT6_BYP -SCSI_In__2__CTL EQU CYREG_PRT6_CTL -SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__2__DR EQU CYREG_PRT6_DR -SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__2__MASK EQU 0x20 -SCSI_In__2__PC EQU CYREG_PRT6_PC5 -SCSI_In__2__PORT EQU 6 -SCSI_In__2__PRT EQU CYREG_PRT6_PRT -SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__2__PS EQU CYREG_PRT6_PS -SCSI_In__2__SHIFT EQU 5 -SCSI_In__2__SLW EQU CYREG_PRT6_SLW -SCSI_In__3__AG EQU CYREG_PRT6_AG -SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__3__BIE EQU CYREG_PRT6_BIE -SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__3__BYP EQU CYREG_PRT6_BYP -SCSI_In__3__CTL EQU CYREG_PRT6_CTL -SCSI_In__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__3__DR EQU CYREG_PRT6_DR -SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__3__MASK EQU 0x80 -SCSI_In__3__PC EQU CYREG_PRT6_PC7 -SCSI_In__3__PORT EQU 6 -SCSI_In__3__PRT EQU CYREG_PRT6_PRT -SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__3__PS EQU CYREG_PRT6_PS -SCSI_In__3__SHIFT EQU 7 -SCSI_In__3__SLW EQU CYREG_PRT6_SLW +SCSI_In__2__AG EQU CYREG_PRT5_AG +SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__2__BIE EQU CYREG_PRT5_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT5_BYP +SCSI_In__2__CTL EQU CYREG_PRT5_CTL +SCSI_In__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__2__DR EQU CYREG_PRT5_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__2__MASK EQU 0x02 +SCSI_In__2__PC EQU CYREG_PRT5_PC1 +SCSI_In__2__PORT EQU 5 +SCSI_In__2__PRT EQU CYREG_PRT5_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT5_PS +SCSI_In__2__SHIFT EQU 1 +SCSI_In__2__SLW EQU CYREG_PRT5_SLW +SCSI_In__3__AG EQU CYREG_PRT5_AG +SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__3__BIE EQU CYREG_PRT5_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT5_BYP +SCSI_In__3__CTL EQU CYREG_PRT5_CTL +SCSI_In__3__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__3__DR EQU CYREG_PRT5_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__3__MASK EQU 0x04 +SCSI_In__3__PC EQU CYREG_PRT5_PC2 +SCSI_In__3__PORT EQU 5 +SCSI_In__3__PRT EQU CYREG_PRT5_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT5_PS +SCSI_In__3__SHIFT EQU 2 +SCSI_In__3__SLW EQU CYREG_PRT5_SLW SCSI_In__4__AG EQU CYREG_PRT5_AG SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX SCSI_In__4__BIE EQU CYREG_PRT5_BIE @@ -2281,8 +2496,8 @@ SCSI_In__4__DR EQU CYREG_PRT5_DR SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__4__MASK EQU 0x01 -SCSI_In__4__PC EQU CYREG_PRT5_PC0 +SCSI_In__4__MASK EQU 0x08 +SCSI_In__4__PC EQU CYREG_PRT5_PC3 SCSI_In__4__PORT EQU 5 SCSI_In__4__PRT EQU CYREG_PRT5_PRT SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL @@ -2293,143 +2508,8 @@ SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT SCSI_In__4__PS EQU CYREG_PRT5_PS -SCSI_In__4__SHIFT EQU 0 +SCSI_In__4__SHIFT EQU 3 SCSI_In__4__SLW EQU CYREG_PRT5_SLW -SCSI_In__5__AG EQU CYREG_PRT5_AG -SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__5__BIE EQU CYREG_PRT5_BIE -SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__5__BYP EQU CYREG_PRT5_BYP -SCSI_In__5__CTL EQU CYREG_PRT5_CTL -SCSI_In__5__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__5__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__5__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__5__DR EQU CYREG_PRT5_DR -SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__5__MASK EQU 0x02 -SCSI_In__5__PC EQU CYREG_PRT5_PC1 -SCSI_In__5__PORT EQU 5 -SCSI_In__5__PRT EQU CYREG_PRT5_PRT -SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__5__PS EQU CYREG_PRT5_PS -SCSI_In__5__SHIFT EQU 1 -SCSI_In__5__SLW EQU CYREG_PRT5_SLW -SCSI_In__6__AG EQU CYREG_PRT5_AG -SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__6__BIE EQU CYREG_PRT5_BIE -SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__6__BYP EQU CYREG_PRT5_BYP -SCSI_In__6__CTL EQU CYREG_PRT5_CTL -SCSI_In__6__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__6__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__6__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__6__DR EQU CYREG_PRT5_DR -SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__6__MASK EQU 0x04 -SCSI_In__6__PC EQU CYREG_PRT5_PC2 -SCSI_In__6__PORT EQU 5 -SCSI_In__6__PRT EQU CYREG_PRT5_PRT -SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__6__PS EQU CYREG_PRT5_PS -SCSI_In__6__SHIFT EQU 2 -SCSI_In__6__SLW EQU CYREG_PRT5_SLW -SCSI_In__7__AG EQU CYREG_PRT5_AG -SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__7__BIE EQU CYREG_PRT5_BIE -SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__7__BYP EQU CYREG_PRT5_BYP -SCSI_In__7__CTL EQU CYREG_PRT5_CTL -SCSI_In__7__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__7__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__7__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__7__DR EQU CYREG_PRT5_DR -SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__7__MASK EQU 0x08 -SCSI_In__7__PC EQU CYREG_PRT5_PC3 -SCSI_In__7__PORT EQU 5 -SCSI_In__7__PRT EQU CYREG_PRT5_PRT -SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__7__PS EQU CYREG_PRT5_PS -SCSI_In__7__SHIFT EQU 3 -SCSI_In__7__SLW EQU CYREG_PRT5_SLW -SCSI_In__ACK__AG EQU CYREG_PRT6_AG -SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__ACK__DR EQU CYREG_PRT6_DR -SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__ACK__MASK EQU 0x20 -SCSI_In__ACK__PC EQU CYREG_PRT6_PC5 -SCSI_In__ACK__PORT EQU 6 -SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__ACK__PS EQU CYREG_PRT6_PS -SCSI_In__ACK__SHIFT EQU 5 -SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_In__BSY__AG EQU CYREG_PRT6_AG -SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__BSY__DR EQU CYREG_PRT6_DR -SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__BSY__MASK EQU 0x10 -SCSI_In__BSY__PC EQU CYREG_PRT6_PC4 -SCSI_In__BSY__PORT EQU 6 -SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__BSY__PS EQU CYREG_PRT6_PS -SCSI_In__BSY__SHIFT EQU 4 -SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW SCSI_In__CD__AG EQU CYREG_PRT5_AG SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX SCSI_In__CD__BIE EQU CYREG_PRT5_BIE @@ -2565,33 +2645,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT5_PS SCSI_In__REQ__SHIFT EQU 2 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW -SCSI_In__SEL__AG EQU CYREG_PRT5_AG -SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE -SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP -SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL -SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__SEL__DR EQU CYREG_PRT5_DR -SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__SEL__MASK EQU 0x01 -SCSI_In__SEL__PC EQU CYREG_PRT5_PC0 -SCSI_In__SEL__PORT EQU 5 -SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT -SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__SEL__PS EQU CYREG_PRT5_PS -SCSI_In__SEL__SHIFT EQU 0 -SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW /* SD_DAT1 */ SD_DAT1__0__MASK EQU 0x01 @@ -2923,7 +2976,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000001E +CYDEV_INTR_RISING EQU 0x0000003E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 52e34c0..5707cb3 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -26,10 +26,10 @@ SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_TX_DMA_COMPLETE SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -54,32 +54,32 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 ; SD_RX_DMA_COMPLETE SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SD_TX_DMA_COMPLETE SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -94,41 +94,59 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL + +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST ; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -143,15 +161,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL ; USBFS_arb_int USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -176,24 +194,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -632,40 +650,40 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW ; SCSI_RST_ISR SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x400 -SCSI_RST_ISR__INTC_NUMBER EQU 10 +SCSI_RST_ISR__INTC_MASK EQU 0x04 +SCSI_RST_ISR__INTC_NUMBER EQU 2 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -680,8 +698,8 @@ SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -691,26 +709,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1 ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1200,11 +1218,281 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT12_AG +SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT12_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__0__MASK EQU 0x20 +SCSI_Noise__0__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__0__PORT EQU 12 +SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT12_PS +SCSI_Noise__0__SHIFT EQU 5 +SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x10 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 4 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT5_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT5_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__2__MASK EQU 0x01 +SCSI_Noise__2__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__2__PORT EQU 5 +SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT5_PS +SCSI_Noise__2__SHIFT EQU 0 +SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW +SCSI_Noise__3__AG EQU CYREG_PRT6_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT6_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__3__PORT EQU 6 +SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT6_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x20 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 5 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x20 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 5 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG +SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP +SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Noise__ATN__MASK EQU 0x20 +SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5 +SCSI_Noise__ATN__PORT EQU 12 +SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS +SCSI_Noise__ATN__SHIFT EQU 5 +SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x10 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 4 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT6_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT6_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6 +SCSI_Noise__RST__PORT EQU 6 +SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT6_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x01 +SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0 +SCSI_Noise__SEL__PORT EQU 5 +SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS +SCSI_Noise__SEL__SHIFT EQU 0 +SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW + ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1214,58 +1502,58 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1280,40 +1568,40 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_1 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x20 -USBFS_ep_1__INTC_NUMBER EQU 5 +USBFS_ep_1__INTC_MASK EQU 0x40 +USBFS_ep_1__INTC_NUMBER EQU 6 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_2 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x40 -USBFS_ep_2__INTC_NUMBER EQU 6 +USBFS_ep_2__INTC_MASK EQU 0x80 +USBFS_ep_2__INTC_NUMBER EQU 7 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_3 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x80 -USBFS_ep_3__INTC_NUMBER EQU 7 +USBFS_ep_3__INTC_MASK EQU 0x100 +USBFS_ep_3__INTC_NUMBER EQU 8 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_4 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x100 -USBFS_ep_4__INTC_NUMBER EQU 8 +USBFS_ep_4__INTC_MASK EQU 0x200 +USBFS_ep_4__INTC_NUMBER EQU 9 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -1467,41 +1755,6 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -; SCSI_ATN -SCSI_ATN__0__MASK EQU 0x20 -SCSI_ATN__0__PC EQU CYREG_PRT12_PC5 -SCSI_ATN__0__PORT EQU 12 -SCSI_ATN__0__SHIFT EQU 5 -SCSI_ATN__AG EQU CYREG_PRT12_AG -SCSI_ATN__BIE EQU CYREG_PRT12_BIE -SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SCSI_ATN__BYP EQU CYREG_PRT12_BYP -SCSI_ATN__DM0 EQU CYREG_PRT12_DM0 -SCSI_ATN__DM1 EQU CYREG_PRT12_DM1 -SCSI_ATN__DM2 EQU CYREG_PRT12_DM2 -SCSI_ATN__DR EQU CYREG_PRT12_DR -SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_ATN__INT__MASK EQU 0x20 -SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5 -SCSI_ATN__INT__PORT EQU 12 -SCSI_ATN__INT__SHIFT EQU 5 -SCSI_ATN__MASK EQU 0x20 -SCSI_ATN__PORT EQU 12 -SCSI_ATN__PRT EQU CYREG_PRT12_PRT -SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SCSI_ATN__PS EQU CYREG_PRT12_PS -SCSI_ATN__SHIFT EQU 5 -SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SCSI_ATN__SLW EQU CYREG_PRT12_SLW - ; SCSI_CLK SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 @@ -2055,44 +2308,6 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 3 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW -; SCSI_RST -SCSI_RST__0__MASK EQU 0x40 -SCSI_RST__0__PC EQU CYREG_PRT6_PC6 -SCSI_RST__0__PORT EQU 6 -SCSI_RST__0__SHIFT EQU 6 -SCSI_RST__AG EQU CYREG_PRT6_AG -SCSI_RST__AMUX EQU CYREG_PRT6_AMUX -SCSI_RST__BIE EQU CYREG_PRT6_BIE -SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_RST__BYP EQU CYREG_PRT6_BYP -SCSI_RST__CTL EQU CYREG_PRT6_CTL -SCSI_RST__DM0 EQU CYREG_PRT6_DM0 -SCSI_RST__DM1 EQU CYREG_PRT6_DM1 -SCSI_RST__DM2 EQU CYREG_PRT6_DM2 -SCSI_RST__DR EQU CYREG_PRT6_DR -SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT -SCSI_RST__INT__MASK EQU 0x40 -SCSI_RST__INT__PC EQU CYREG_PRT6_PC6 -SCSI_RST__INT__PORT EQU 6 -SCSI_RST__INT__SHIFT EQU 6 -SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_RST__MASK EQU 0x40 -SCSI_RST__PORT EQU 6 -SCSI_RST__PRT EQU CYREG_PRT6_PRT -SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_RST__PS EQU CYREG_PRT6_PS -SCSI_RST__SHIFT EQU 6 -SCSI_RST__SLW EQU CYREG_PRT6_SLW -SCSI_RST__SNAP EQU CYREG_PICU6_SNAP - ; USBFS_Dm USBFS_Dm__0__MASK EQU 0x80 USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 @@ -2200,8 +2415,8 @@ SCSI_In__1__DR EQU CYREG_PRT6_DR SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__1__MASK EQU 0x10 -SCSI_In__1__PC EQU CYREG_PRT6_PC4 +SCSI_In__1__MASK EQU 0x80 +SCSI_In__1__PC EQU CYREG_PRT6_PC7 SCSI_In__1__PORT EQU 6 SCSI_In__1__PRT EQU CYREG_PRT6_PRT SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL @@ -2212,62 +2427,62 @@ SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT SCSI_In__1__PS EQU CYREG_PRT6_PS -SCSI_In__1__SHIFT EQU 4 +SCSI_In__1__SHIFT EQU 7 SCSI_In__1__SLW EQU CYREG_PRT6_SLW -SCSI_In__2__AG EQU CYREG_PRT6_AG -SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__2__BIE EQU CYREG_PRT6_BIE -SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__2__BYP EQU CYREG_PRT6_BYP -SCSI_In__2__CTL EQU CYREG_PRT6_CTL -SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__2__DR EQU CYREG_PRT6_DR -SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__2__MASK EQU 0x20 -SCSI_In__2__PC EQU CYREG_PRT6_PC5 -SCSI_In__2__PORT EQU 6 -SCSI_In__2__PRT EQU CYREG_PRT6_PRT -SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__2__PS EQU CYREG_PRT6_PS -SCSI_In__2__SHIFT EQU 5 -SCSI_In__2__SLW EQU CYREG_PRT6_SLW -SCSI_In__3__AG EQU CYREG_PRT6_AG -SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__3__BIE EQU CYREG_PRT6_BIE -SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__3__BYP EQU CYREG_PRT6_BYP -SCSI_In__3__CTL EQU CYREG_PRT6_CTL -SCSI_In__3__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__3__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__3__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__3__DR EQU CYREG_PRT6_DR -SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__3__MASK EQU 0x80 -SCSI_In__3__PC EQU CYREG_PRT6_PC7 -SCSI_In__3__PORT EQU 6 -SCSI_In__3__PRT EQU CYREG_PRT6_PRT -SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__3__PS EQU CYREG_PRT6_PS -SCSI_In__3__SHIFT EQU 7 -SCSI_In__3__SLW EQU CYREG_PRT6_SLW +SCSI_In__2__AG EQU CYREG_PRT5_AG +SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__2__BIE EQU CYREG_PRT5_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT5_BYP +SCSI_In__2__CTL EQU CYREG_PRT5_CTL +SCSI_In__2__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__2__DR EQU CYREG_PRT5_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__2__MASK EQU 0x02 +SCSI_In__2__PC EQU CYREG_PRT5_PC1 +SCSI_In__2__PORT EQU 5 +SCSI_In__2__PRT EQU CYREG_PRT5_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT5_PS +SCSI_In__2__SHIFT EQU 1 +SCSI_In__2__SLW EQU CYREG_PRT5_SLW +SCSI_In__3__AG EQU CYREG_PRT5_AG +SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX +SCSI_In__3__BIE EQU CYREG_PRT5_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT5_BYP +SCSI_In__3__CTL EQU CYREG_PRT5_CTL +SCSI_In__3__DM0 EQU CYREG_PRT5_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT5_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT5_DM2 +SCSI_In__3__DR EQU CYREG_PRT5_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN +SCSI_In__3__MASK EQU 0x04 +SCSI_In__3__PC EQU CYREG_PRT5_PC2 +SCSI_In__3__PORT EQU 5 +SCSI_In__3__PRT EQU CYREG_PRT5_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT5_PS +SCSI_In__3__SHIFT EQU 2 +SCSI_In__3__SLW EQU CYREG_PRT5_SLW SCSI_In__4__AG EQU CYREG_PRT5_AG SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX SCSI_In__4__BIE EQU CYREG_PRT5_BIE @@ -2281,8 +2496,8 @@ SCSI_In__4__DR EQU CYREG_PRT5_DR SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__4__MASK EQU 0x01 -SCSI_In__4__PC EQU CYREG_PRT5_PC0 +SCSI_In__4__MASK EQU 0x08 +SCSI_In__4__PC EQU CYREG_PRT5_PC3 SCSI_In__4__PORT EQU 5 SCSI_In__4__PRT EQU CYREG_PRT5_PRT SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL @@ -2293,143 +2508,8 @@ SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT SCSI_In__4__PS EQU CYREG_PRT5_PS -SCSI_In__4__SHIFT EQU 0 +SCSI_In__4__SHIFT EQU 3 SCSI_In__4__SLW EQU CYREG_PRT5_SLW -SCSI_In__5__AG EQU CYREG_PRT5_AG -SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__5__BIE EQU CYREG_PRT5_BIE -SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__5__BYP EQU CYREG_PRT5_BYP -SCSI_In__5__CTL EQU CYREG_PRT5_CTL -SCSI_In__5__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__5__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__5__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__5__DR EQU CYREG_PRT5_DR -SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__5__MASK EQU 0x02 -SCSI_In__5__PC EQU CYREG_PRT5_PC1 -SCSI_In__5__PORT EQU 5 -SCSI_In__5__PRT EQU CYREG_PRT5_PRT -SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__5__PS EQU CYREG_PRT5_PS -SCSI_In__5__SHIFT EQU 1 -SCSI_In__5__SLW EQU CYREG_PRT5_SLW -SCSI_In__6__AG EQU CYREG_PRT5_AG -SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__6__BIE EQU CYREG_PRT5_BIE -SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__6__BYP EQU CYREG_PRT5_BYP -SCSI_In__6__CTL EQU CYREG_PRT5_CTL -SCSI_In__6__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__6__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__6__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__6__DR EQU CYREG_PRT5_DR -SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__6__MASK EQU 0x04 -SCSI_In__6__PC EQU CYREG_PRT5_PC2 -SCSI_In__6__PORT EQU 5 -SCSI_In__6__PRT EQU CYREG_PRT5_PRT -SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__6__PS EQU CYREG_PRT5_PS -SCSI_In__6__SHIFT EQU 2 -SCSI_In__6__SLW EQU CYREG_PRT5_SLW -SCSI_In__7__AG EQU CYREG_PRT5_AG -SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__7__BIE EQU CYREG_PRT5_BIE -SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__7__BYP EQU CYREG_PRT5_BYP -SCSI_In__7__CTL EQU CYREG_PRT5_CTL -SCSI_In__7__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__7__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__7__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__7__DR EQU CYREG_PRT5_DR -SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__7__MASK EQU 0x08 -SCSI_In__7__PC EQU CYREG_PRT5_PC3 -SCSI_In__7__PORT EQU 5 -SCSI_In__7__PRT EQU CYREG_PRT5_PRT -SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__7__PS EQU CYREG_PRT5_PS -SCSI_In__7__SHIFT EQU 3 -SCSI_In__7__SLW EQU CYREG_PRT5_SLW -SCSI_In__ACK__AG EQU CYREG_PRT6_AG -SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__ACK__DR EQU CYREG_PRT6_DR -SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__ACK__MASK EQU 0x20 -SCSI_In__ACK__PC EQU CYREG_PRT6_PC5 -SCSI_In__ACK__PORT EQU 6 -SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__ACK__PS EQU CYREG_PRT6_PS -SCSI_In__ACK__SHIFT EQU 5 -SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_In__BSY__AG EQU CYREG_PRT6_AG -SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__BSY__DR EQU CYREG_PRT6_DR -SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__BSY__MASK EQU 0x10 -SCSI_In__BSY__PC EQU CYREG_PRT6_PC4 -SCSI_In__BSY__PORT EQU 6 -SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__BSY__PS EQU CYREG_PRT6_PS -SCSI_In__BSY__SHIFT EQU 4 -SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW SCSI_In__CD__AG EQU CYREG_PRT5_AG SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX SCSI_In__CD__BIE EQU CYREG_PRT5_BIE @@ -2565,33 +2645,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT5_PS SCSI_In__REQ__SHIFT EQU 2 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW -SCSI_In__SEL__AG EQU CYREG_PRT5_AG -SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX -SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE -SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK -SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP -SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL -SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0 -SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1 -SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2 -SCSI_In__SEL__DR EQU CYREG_PRT5_DR -SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS -SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG -SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN -SCSI_In__SEL__MASK EQU 0x01 -SCSI_In__SEL__PC EQU CYREG_PRT5_PC0 -SCSI_In__SEL__PORT EQU 5 -SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT -SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL -SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN -SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0 -SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1 -SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0 -SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1 -SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT -SCSI_In__SEL__PS EQU CYREG_PRT5_PS -SCSI_In__SEL__SHIFT EQU 0 -SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW ; SD_DAT1 SD_DAT1__0__MASK EQU 0x01 @@ -2923,7 +2976,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000001E +CYDEV_INTR_RISING EQU 0x0000003E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 542b2e7..cdd707b 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -39,10 +39,7 @@ #include #include #include -#include -#include -#include -#include +#include #include #include #include @@ -71,6 +68,7 @@ #include #include #include +#include #include #include #include diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml index 94bc6b1..b2b424a 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -130,12 +130,6 @@ .\Generated_Source\PSoC5\SDCard_PM.c .\Generated_Source\PSoC5\SDCard_INT.c .\Generated_Source\PSoC5\SDCard_PVT.h - .\Generated_Source\PSoC5\SCSI_RST_aliases.h - .\Generated_Source\PSoC5\SCSI_RST.c - .\Generated_Source\PSoC5\SCSI_RST.h - .\Generated_Source\PSoC5\SCSI_ATN_aliases.h - .\Generated_Source\PSoC5\SCSI_ATN.c - .\Generated_Source\PSoC5\SCSI_ATN.h .\Generated_Source\PSoC5\SCSI_RST_ISR.c .\Generated_Source\PSoC5\SCSI_RST_ISR.h .\Generated_Source\PSoC5\cymetadata.c @@ -206,6 +200,9 @@ .\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.h .\Generated_Source\PSoC5\SCSI_Parity_Error.c .\Generated_Source\PSoC5\SCSI_Parity_Error.h + .\Generated_Source\PSoC5\SCSI_Noise_aliases.h + .\Generated_Source\PSoC5\SCSI_Filtered.c + .\Generated_Source\PSoC5\SCSI_Filtered.h .\Generated_Source\PSoC5\prebuild.bat .\Generated_Source\PSoC5\postbuild.bat .\Generated_Source\PSoC5\CyElfTool.exe diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index e399342..df7fe9d 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,11 +1,19 @@ - - - + + + + + + - + + + + + + @@ -63,9 +71,93 @@ - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -153,67 +245,11 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - + - + + \ No newline at end of file diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr index 21c2248..ebcde14 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit index 515157a..a39399e 100644 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj index b8c108c..9e13a8a 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -1398,14 +1398,14 @@ - + - + @@ -1414,7 +1414,7 @@ - + @@ -1423,7 +1423,7 @@ - + @@ -1437,14 +1437,14 @@ - + - + @@ -1453,7 +1453,7 @@ - + @@ -1462,7 +1462,7 @@ - + @@ -2973,6 +2973,87 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd index d2edff0..f551ba1 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd @@ -7,9 +7,9 @@ 32 - SCSI_Out_Ctl + SCSI_Out_Bits No description available - 0x4000647E + 0x40006473 0 0x1 @@ -17,7 +17,7 @@ - SCSI_Out_Ctl_CONTROL_REG + SCSI_Out_Bits_CONTROL_REG No description available 0x0 8 @@ -28,7 +28,7 @@ - SCSI_Out_Bits + SCSI_Out_Ctl No description available 0x4000647B @@ -38,7 +38,7 @@ - SCSI_Out_Bits_CONTROL_REG + SCSI_Out_Ctl_CONTROL_REG No description available 0x0 8 @@ -340,6 +340,337 @@ + + SCSI_Filtered + No description available + 0x40006460 + + 0 + 0x31 + registers + + + + SCSI_Filtered_STATUS_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_Filtered_MASK_REG + No description available + 0x20 + 8 + read-write + 0 + 0 + + + SCSI_Filtered_STATUS_AUX_CTL_REG + No description available + 0x30 + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + + + SCSI_Parity_Error + No description available + 0x40006467 + + 0 + 0x31 + registers + + + + SCSI_Parity_Error_STATUS_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_MASK_REG + No description available + 0x20 + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_STATUS_AUX_CTL_REG + No description available + 0x30 + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + + + SCSI_CTL_PHASE + No description available + 0x40006472 + + 0 + 0x1 + registers + + + + SCSI_CTL_PHASE_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + USBFS USBFS @@ -824,181 +1155,5 @@ - - SCSI_Parity_Error - No description available - 0x4000646A - - 0 - 0x31 - registers - - - - SCSI_Parity_Error_STATUS_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - SCSI_Parity_Error_MASK_REG - No description available - 0x20 - 8 - read-write - 0 - 0 - - - SCSI_Parity_Error_STATUS_AUX_CTL_REG - No description available - 0x30 - 8 - read-write - 0 - 0 - - - FIFO0 - FIFO0 clear - 5 - 5 - read-write - - - ENABLED - Enable counter - 1 - - - DISABLED - Disable counter - 0 - - - - - INTRENBL - Enables or disables the Interrupt - 4 - 4 - read-write - - - ENABLED - Interrupt enabled - 1 - - - DISABLED - Interrupt disabled - 0 - - - - - FIFO1LEVEL - FIFO level - 3 - 3 - read-write - - - ENABLED - FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full - 1 - - - DISABLED - FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty - 0 - - - - - FIFO0LEVEL - FIFO level - 2 - 2 - read-write - - - ENABLED - FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full - 1 - - - DISABLED - FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty - 0 - - - - - FIFO1CLEAR - FIFO clear - 1 - 1 - read-write - - - ENABLED - Clear FIFO state - 1 - - - DISABLED - Normal FIFO operation - 0 - - - - - FIFO0CLEAR - FIFO clear - 0 - 0 - read-write - - - ENABLED - Clear FIFO state - 1 - - - DISABLED - Normal FIFO operation - 0 - - - - - - - - - SCSI_CTL_PHASE - No description available - 0x40006471 - - 0 - 0x1 - registers - - - - SCSI_CTL_PHASE_CONTROL_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - \ No newline at end of file diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 70724a2..eccaf89 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v index 0298351..850176a 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -58,27 +58,6 @@ localparam IO_WRITE = 1'b1; localparam IO_READ = 1'b0; -///////////////////////////////////////////////////////////////////////////// -// Input filter -///////////////////////////////////////////////////////////////////////////// -// Do not respond to glitches in the ACK signal. This will cause us to -// transfer rubbish data, or too many bytes, and generally leads to -// hanging the SCSI bus. Reflected signals can cause the ACK signal -// to be dirty. We don't care so much about the others as we don't -// respond to them on the rising edge. -// 4-stage shifter. Ass -reg safeACK; -reg[3:0] ackShift; -always @(posedge op_clk) begin - if (ackShift[3:1] == 0) begin - safeACK <= 0; - end - else if (ackShift[3:1] == 1) begin - safeACK <= 1; - end - ackShift <= {ackShift[2:0], ~nACK}; -end - ///////////////////////////////////////////////////////////////////////////// // STATE MACHINE ///////////////////////////////////////////////////////////////////////////// @@ -184,7 +163,7 @@ wire f0_bus_stat; // Tx FIFO not full wire f0_blk_stat; // Tx FIFO empty wire f1_bus_stat; // Rx FIFO not empty wire f1_blk_stat; // Rx FIFO full -wire txComplete = f0_blk_stat && (state == STATE_IDLE) && ~safeACK; +wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK; cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg ( /* input */ .clock(op_clk), @@ -206,7 +185,7 @@ always @(posedge op_clk) begin // and output FIFO is not full. // Note that output FIFO is unused in TX mode. if (!nRST) state <= STATE_IDLE; - else if (~safeACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat)) + else if (nACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_FIFOLOAD; else state <= STATE_IDLE; @@ -248,7 +227,7 @@ always @(posedge op_clk) begin STATE_READY: if (!nRST) state <= STATE_IDLE; - else if (safeACK) begin + else if (~nACK) begin state <= STATE_RX; fifoStore <= 1'b1; diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c new file mode 100644 index 0000000..2fc815b --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: SCSI_Filtered.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware to read the value of a Status +* Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Filtered.h" + +#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */ + + +/******************************************************************************* +* Function Name: SCSI_Filtered_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The current value in the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Filtered_Read(void) +{ + return SCSI_Filtered_Status; +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_InterruptEnable +******************************************************************************** +* +* Summary: +* Enables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_InterruptEnable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL; + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_InterruptDisable +******************************************************************************** +* +* Summary: +* Disables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_InterruptDisable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_WriteMask +******************************************************************************** +* +* Summary: +* Writes the current mask value assigned to the Status Register. +* +* Parameters: +* mask: Value to write into the mask register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_WriteMask(uint8 mask) +{ + #if(SCSI_Filtered_INPUTS < 8u) + mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u); + #endif /* End SCSI_Filtered_INPUTS < 8u */ + SCSI_Filtered_Status_Mask = mask; +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_ReadMask +******************************************************************************** +* +* Summary: +* Reads the current interrupt mask assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The value of the interrupt mask of the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Filtered_ReadMask(void) +{ + return SCSI_Filtered_Status_Mask; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h new file mode 100644 index 0000000..759a85b --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_Filtered.h +* Version 1.80 +* +* Description: +* This file containts Status Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */ +#define CY_STATUS_REG_SCSI_Filtered_H + +#include "cytypes.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +uint8 SCSI_Filtered_Read(void) ; +void SCSI_Filtered_InterruptEnable(void) ; +void SCSI_Filtered_InterruptDisable(void) ; +void SCSI_Filtered_WriteMask(uint8 mask) ; +uint8 SCSI_Filtered_ReadMask(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define SCSI_Filtered_STATUS_INTR_ENBL 0x10u + + +/*************************************** +* Parameter Constants +***************************************/ + +/* Status Register Inputs */ +#define SCSI_Filtered_INPUTS 5 + + +/*************************************** +* Registers +***************************************/ + +/* Status Register */ +#define SCSI_Filtered_Status (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG ) +#define SCSI_Filtered_Status_PTR ( (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG ) +#define SCSI_Filtered_Status_Mask (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG ) +#define SCSI_Filtered_Status_Aux_Ctrl (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG ) + +#endif /* End CY_STATUS_REG_SCSI_Filtered_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h index 3447a10..66ac80a 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h @@ -30,15 +30,9 @@ #define SCSI_In_2 SCSI_In__2__PC #define SCSI_In_3 SCSI_In__3__PC #define SCSI_In_4 SCSI_In__4__PC -#define SCSI_In_5 SCSI_In__5__PC -#define SCSI_In_6 SCSI_In__6__PC -#define SCSI_In_7 SCSI_In__7__PC #define SCSI_In_DBP SCSI_In__DBP__PC -#define SCSI_In_BSY SCSI_In__BSY__PC -#define SCSI_In_ACK SCSI_In__ACK__PC #define SCSI_In_MSG SCSI_In__MSG__PC -#define SCSI_In_SEL SCSI_In__SEL__PC #define SCSI_In_CD SCSI_In__CD__PC #define SCSI_In_REQ SCSI_In__REQ__PC #define SCSI_In_IO SCSI_In__IO__PC diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h new file mode 100644 index 0000000..ffd841d --- /dev/null +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SCSI_Noise.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */ +#define CY_PINS_SCSI_Noise_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Noise_0 SCSI_Noise__0__PC +#define SCSI_Noise_1 SCSI_Noise__1__PC +#define SCSI_Noise_2 SCSI_Noise__2__PC +#define SCSI_Noise_3 SCSI_Noise__3__PC +#define SCSI_Noise_4 SCSI_Noise__4__PC + +#define SCSI_Noise_ATN SCSI_Noise__ATN__PC +#define SCSI_Noise_BSY SCSI_Noise__BSY__PC +#define SCSI_Noise_SEL SCSI_Noise__SEL__PC +#define SCSI_Noise_RST SCSI_Noise__RST__PC +#define SCSI_Noise_ACK SCSI_Noise__ACK__PC + +#endif /* End Pins SCSI_Noise_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c index 196f01c..6bc5b1e 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -46,7 +46,7 @@ const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { /* bMaxPacketSize0 */ 0x08u, /* idVendor */ 0xB4u, 0x04u, /* idProduct */ 0x37u, 0x13u, -/* bcdDevice */ 0x02u, 0x30u, +/* bcdDevice */ 0x01u, 0x30u, /* iManufacturer */ 0x02u, /* iProduct */ 0x01u, /* iSerialNumber */ 0x80u, diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index e79356b..af27962 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -26,10 +26,10 @@ /* SCSI_TX_DMA_COMPLETE */ #define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u #define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3 #define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -54,36 +54,34 @@ /* SD_RX_DMA_COMPLETE */ #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u -#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u #define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SD_TX_DMA_COMPLETE */ #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u #define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK -#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB11_MSK +#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB11_ST /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -98,32 +96,54 @@ /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL + +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK +#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST /* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u @@ -138,15 +158,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL /* USBFS_arb_int */ #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -171,24 +191,15 @@ /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT5_AG @@ -627,42 +638,42 @@ /* SCSI_RST_ISR */ #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x100u -#define SCSI_RST_ISR__INTC_NUMBER 8u +#define SCSI_RST_ISR__INTC_MASK 0x04u +#define SCSI_RST_ISR__INTC_NUMBER 2u #define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2 #define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB09_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB09_ST -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB09_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB09_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB09_MSK -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -670,11 +681,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -684,32 +697,26 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK -#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB05_06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB05_06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB05_06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB05_06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB05_06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB05_06_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB05_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB05_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB05_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB05_F1 /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1197,11 +1204,283 @@ #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define timer_clock__PM_STBY_MSK 0x04u +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT2_AG +#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX +#define SCSI_Noise__0__BIE CYREG_PRT2_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT2_BYP +#define SCSI_Noise__0__CTL CYREG_PRT2_CTL +#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2 +#define SCSI_Noise__0__DR CYREG_PRT2_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Noise__0__MASK 0x01u +#define SCSI_Noise__0__PC CYREG_PRT2_PC0 +#define SCSI_Noise__0__PORT 2u +#define SCSI_Noise__0__PRT CYREG_PRT2_PRT +#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT2_PS +#define SCSI_Noise__0__SHIFT 0 +#define SCSI_Noise__0__SLW CYREG_PRT2_SLW +#define SCSI_Noise__1__AG CYREG_PRT6_AG +#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT6_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT6_BYP +#define SCSI_Noise__1__CTL CYREG_PRT6_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__1__DR CYREG_PRT6_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__1__MASK 0x08u +#define SCSI_Noise__1__PC CYREG_PRT6_PC3 +#define SCSI_Noise__1__PORT 6u +#define SCSI_Noise__1__PRT CYREG_PRT6_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT6_PS +#define SCSI_Noise__1__SHIFT 3 +#define SCSI_Noise__1__SLW CYREG_PRT6_SLW +#define SCSI_Noise__2__AG CYREG_PRT4_AG +#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT4_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT4_BYP +#define SCSI_Noise__2__CTL CYREG_PRT4_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__2__DR CYREG_PRT4_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__2__MASK 0x08u +#define SCSI_Noise__2__PC CYREG_PRT4_PC3 +#define SCSI_Noise__2__PORT 4u +#define SCSI_Noise__2__PRT CYREG_PRT4_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT4_PS +#define SCSI_Noise__2__SHIFT 3 +#define SCSI_Noise__2__SLW CYREG_PRT4_SLW +#define SCSI_Noise__3__AG CYREG_PRT4_AG +#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT4_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT4_BYP +#define SCSI_Noise__3__CTL CYREG_PRT4_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__3__DR CYREG_PRT4_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__3__MASK 0x80u +#define SCSI_Noise__3__PC CYREG_PRT4_PC7 +#define SCSI_Noise__3__PORT 4u +#define SCSI_Noise__3__PRT CYREG_PRT4_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT4_PS +#define SCSI_Noise__3__SHIFT 7 +#define SCSI_Noise__3__SLW CYREG_PRT4_SLW +#define SCSI_Noise__4__AG CYREG_PRT6_AG +#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT6_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT6_BYP +#define SCSI_Noise__4__CTL CYREG_PRT6_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__4__DR CYREG_PRT6_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__4__MASK 0x04u +#define SCSI_Noise__4__PC CYREG_PRT6_PC2 +#define SCSI_Noise__4__PORT 6u +#define SCSI_Noise__4__PRT CYREG_PRT6_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT6_PS +#define SCSI_Noise__4__SHIFT 2 +#define SCSI_Noise__4__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT6_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT6_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__ACK__MASK 0x04u +#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2 +#define SCSI_Noise__ACK__PORT 6u +#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT6_PS +#define SCSI_Noise__ACK__SHIFT 2 +#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT2_AG +#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX +#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP +#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL +#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT2_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Noise__ATN__MASK 0x01u +#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0 +#define SCSI_Noise__ATN__PORT 2u +#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT +#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT2_PS +#define SCSI_Noise__ATN__SHIFT 0 +#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT6_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT6_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Noise__BSY__MASK 0x08u +#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3 +#define SCSI_Noise__BSY__PORT 6u +#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT6_PS +#define SCSI_Noise__BSY__SHIFT 3 +#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW +#define SCSI_Noise__RST__AG CYREG_PRT4_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT4_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__RST__MASK 0x80u +#define SCSI_Noise__RST__PC CYREG_PRT4_PC7 +#define SCSI_Noise__RST__PORT 4u +#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT4_PS +#define SCSI_Noise__RST__SHIFT 7 +#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT4_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT4_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__SEL__MASK 0x08u +#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3 +#define SCSI_Noise__SEL__PORT 4u +#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT4_PS +#define SCSI_Noise__SEL__SHIFT 3 +#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW + /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1211,54 +1490,54 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B1_UDB04_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B1_UDB04_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB08_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB08_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB08_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB08_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB08_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB08_09_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB08_09_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB08_09_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB08_09_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB08_09_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB08_09_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB08_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB08_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB08_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB08_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB08_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB08_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB08_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB08_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB08_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1273,30 +1552,30 @@ /* USBFS_ep_1 */ #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x20u -#define USBFS_ep_1__INTC_NUMBER 5u +#define USBFS_ep_1__INTC_MASK 0x40u +#define USBFS_ep_1__INTC_NUMBER 6u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x40u -#define USBFS_ep_2__INTC_NUMBER 6u +#define USBFS_ep_2__INTC_MASK 0x80u +#define USBFS_ep_2__INTC_NUMBER 7u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x80u -#define USBFS_ep_3__INTC_NUMBER 7u +#define USBFS_ep_3__INTC_MASK 0x100u +#define USBFS_ep_3__INTC_NUMBER 8u #define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -1314,7 +1593,7 @@ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u #define SD_RX_DMA__NUMBEROF_TDS 0u -#define SD_RX_DMA__PRIORITY 1u +#define SD_RX_DMA__PRIORITY 2u #define SD_RX_DMA__TERMIN_EN 0u #define SD_RX_DMA__TERMIN_SEL 0u #define SD_RX_DMA__TERMOUT0_EN 1u @@ -1460,42 +1739,6 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 #define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN -/* SCSI_ATN */ -#define SCSI_ATN__0__MASK 0x01u -#define SCSI_ATN__0__PC CYREG_PRT2_PC0 -#define SCSI_ATN__0__PORT 2u -#define SCSI_ATN__0__SHIFT 0 -#define SCSI_ATN__AG CYREG_PRT2_AG -#define SCSI_ATN__AMUX CYREG_PRT2_AMUX -#define SCSI_ATN__BIE CYREG_PRT2_BIE -#define SCSI_ATN__BIT_MASK CYREG_PRT2_BIT_MASK -#define SCSI_ATN__BYP CYREG_PRT2_BYP -#define SCSI_ATN__CTL CYREG_PRT2_CTL -#define SCSI_ATN__DM0 CYREG_PRT2_DM0 -#define SCSI_ATN__DM1 CYREG_PRT2_DM1 -#define SCSI_ATN__DM2 CYREG_PRT2_DM2 -#define SCSI_ATN__DR CYREG_PRT2_DR -#define SCSI_ATN__INP_DIS CYREG_PRT2_INP_DIS -#define SCSI_ATN__INT__MASK 0x01u -#define SCSI_ATN__INT__PC CYREG_PRT2_PC0 -#define SCSI_ATN__INT__PORT 2u -#define SCSI_ATN__INT__SHIFT 0 -#define SCSI_ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG -#define SCSI_ATN__LCD_EN CYREG_PRT2_LCD_EN -#define SCSI_ATN__MASK 0x01u -#define SCSI_ATN__PORT 2u -#define SCSI_ATN__PRT CYREG_PRT2_PRT -#define SCSI_ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL -#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN -#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 -#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 -#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 -#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 -#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT -#define SCSI_ATN__PS CYREG_PRT2_PS -#define SCSI_ATN__SHIFT 0 -#define SCSI_ATN__SLW CYREG_PRT2_SLW - /* SCSI_CLK */ #define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 #define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 @@ -2049,44 +2292,6 @@ #define SCSI_Out__SEL__SHIFT 7 #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW -/* SCSI_RST */ -#define SCSI_RST__0__MASK 0x80u -#define SCSI_RST__0__PC CYREG_PRT4_PC7 -#define SCSI_RST__0__PORT 4u -#define SCSI_RST__0__SHIFT 7 -#define SCSI_RST__AG CYREG_PRT4_AG -#define SCSI_RST__AMUX CYREG_PRT4_AMUX -#define SCSI_RST__BIE CYREG_PRT4_BIE -#define SCSI_RST__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_RST__BYP CYREG_PRT4_BYP -#define SCSI_RST__CTL CYREG_PRT4_CTL -#define SCSI_RST__DM0 CYREG_PRT4_DM0 -#define SCSI_RST__DM1 CYREG_PRT4_DM1 -#define SCSI_RST__DM2 CYREG_PRT4_DM2 -#define SCSI_RST__DR CYREG_PRT4_DR -#define SCSI_RST__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_RST__INTSTAT CYREG_PICU4_INTSTAT -#define SCSI_RST__INT__MASK 0x80u -#define SCSI_RST__INT__PC CYREG_PRT4_PC7 -#define SCSI_RST__INT__PORT 4u -#define SCSI_RST__INT__SHIFT 7 -#define SCSI_RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_RST__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_RST__MASK 0x80u -#define SCSI_RST__PORT 4u -#define SCSI_RST__PRT CYREG_PRT4_PRT -#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_RST__PS CYREG_PRT4_PS -#define SCSI_RST__SHIFT 7 -#define SCSI_RST__SLW CYREG_PRT4_SLW -#define SCSI_RST__SNAP CYREG_PICU4_SNAP - /* USBFS_Dm */ #define USBFS_Dm__0__MASK 0x80u #define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 @@ -2181,249 +2386,114 @@ #define SCSI_In__0__PS CYREG_PRT2_PS #define SCSI_In__0__SHIFT 1 #define SCSI_In__0__SLW CYREG_PRT2_SLW -#define SCSI_In__1__AG CYREG_PRT6_AG -#define SCSI_In__1__AMUX CYREG_PRT6_AMUX -#define SCSI_In__1__BIE CYREG_PRT6_BIE -#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__1__BYP CYREG_PRT6_BYP -#define SCSI_In__1__CTL CYREG_PRT6_CTL -#define SCSI_In__1__DM0 CYREG_PRT6_DM0 -#define SCSI_In__1__DM1 CYREG_PRT6_DM1 -#define SCSI_In__1__DM2 CYREG_PRT6_DM2 -#define SCSI_In__1__DR CYREG_PRT6_DR -#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__1__MASK 0x08u -#define SCSI_In__1__PC CYREG_PRT6_PC3 -#define SCSI_In__1__PORT 6u -#define SCSI_In__1__PRT CYREG_PRT6_PRT -#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__1__PS CYREG_PRT6_PS -#define SCSI_In__1__SHIFT 3 -#define SCSI_In__1__SLW CYREG_PRT6_SLW -#define SCSI_In__2__AG CYREG_PRT6_AG -#define SCSI_In__2__AMUX CYREG_PRT6_AMUX -#define SCSI_In__2__BIE CYREG_PRT6_BIE -#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__2__BYP CYREG_PRT6_BYP -#define SCSI_In__2__CTL CYREG_PRT6_CTL -#define SCSI_In__2__DM0 CYREG_PRT6_DM0 -#define SCSI_In__2__DM1 CYREG_PRT6_DM1 -#define SCSI_In__2__DM2 CYREG_PRT6_DM2 -#define SCSI_In__2__DR CYREG_PRT6_DR -#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__1__AG CYREG_PRT4_AG +#define SCSI_In__1__AMUX CYREG_PRT4_AMUX +#define SCSI_In__1__BIE CYREG_PRT4_BIE +#define SCSI_In__1__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__1__BYP CYREG_PRT4_BYP +#define SCSI_In__1__CTL CYREG_PRT4_CTL +#define SCSI_In__1__DM0 CYREG_PRT4_DM0 +#define SCSI_In__1__DM1 CYREG_PRT4_DM1 +#define SCSI_In__1__DM2 CYREG_PRT4_DM2 +#define SCSI_In__1__DR CYREG_PRT4_DR +#define SCSI_In__1__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__1__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_In__1__MASK 0x40u +#define SCSI_In__1__PC CYREG_PRT4_PC6 +#define SCSI_In__1__PORT 4u +#define SCSI_In__1__PRT CYREG_PRT4_PRT +#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__1__PS CYREG_PRT4_PS +#define SCSI_In__1__SHIFT 6 +#define SCSI_In__1__SLW CYREG_PRT4_SLW +#define SCSI_In__2__AG CYREG_PRT4_AG +#define SCSI_In__2__AMUX CYREG_PRT4_AMUX +#define SCSI_In__2__BIE CYREG_PRT4_BIE +#define SCSI_In__2__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_In__2__BYP CYREG_PRT4_BYP +#define SCSI_In__2__CTL CYREG_PRT4_CTL +#define SCSI_In__2__DM0 CYREG_PRT4_DM0 +#define SCSI_In__2__DM1 CYREG_PRT4_DM1 +#define SCSI_In__2__DM2 CYREG_PRT4_DM2 +#define SCSI_In__2__DR CYREG_PRT4_DR +#define SCSI_In__2__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_In__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_In__2__LCD_EN CYREG_PRT4_LCD_EN #define SCSI_In__2__MASK 0x04u -#define SCSI_In__2__PC CYREG_PRT6_PC2 -#define SCSI_In__2__PORT 6u -#define SCSI_In__2__PRT CYREG_PRT6_PRT -#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__2__PS CYREG_PRT6_PS +#define SCSI_In__2__PC CYREG_PRT4_PC2 +#define SCSI_In__2__PORT 4u +#define SCSI_In__2__PRT CYREG_PRT4_PRT +#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_In__2__PS CYREG_PRT4_PS #define SCSI_In__2__SHIFT 2 -#define SCSI_In__2__SLW CYREG_PRT6_SLW -#define SCSI_In__3__AG CYREG_PRT4_AG -#define SCSI_In__3__AMUX CYREG_PRT4_AMUX -#define SCSI_In__3__BIE CYREG_PRT4_BIE -#define SCSI_In__3__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_In__3__BYP CYREG_PRT4_BYP -#define SCSI_In__3__CTL CYREG_PRT4_CTL -#define SCSI_In__3__DM0 CYREG_PRT4_DM0 -#define SCSI_In__3__DM1 CYREG_PRT4_DM1 -#define SCSI_In__3__DM2 CYREG_PRT4_DM2 -#define SCSI_In__3__DR CYREG_PRT4_DR -#define SCSI_In__3__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_In__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_In__3__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_In__3__MASK 0x40u -#define SCSI_In__3__PC CYREG_PRT4_PC6 -#define SCSI_In__3__PORT 4u -#define SCSI_In__3__PRT CYREG_PRT4_PRT -#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_In__3__PS CYREG_PRT4_PS -#define SCSI_In__3__SHIFT 6 -#define SCSI_In__3__SLW CYREG_PRT4_SLW -#define SCSI_In__4__AG CYREG_PRT4_AG -#define SCSI_In__4__AMUX CYREG_PRT4_AMUX -#define SCSI_In__4__BIE CYREG_PRT4_BIE -#define SCSI_In__4__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_In__4__BYP CYREG_PRT4_BYP -#define SCSI_In__4__CTL CYREG_PRT4_CTL -#define SCSI_In__4__DM0 CYREG_PRT4_DM0 -#define SCSI_In__4__DM1 CYREG_PRT4_DM1 -#define SCSI_In__4__DM2 CYREG_PRT4_DM2 -#define SCSI_In__4__DR CYREG_PRT4_DR -#define SCSI_In__4__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_In__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_In__4__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_In__4__MASK 0x08u -#define SCSI_In__4__PC CYREG_PRT4_PC3 -#define SCSI_In__4__PORT 4u -#define SCSI_In__4__PRT CYREG_PRT4_PRT -#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_In__4__PS CYREG_PRT4_PS -#define SCSI_In__4__SHIFT 3 -#define SCSI_In__4__SLW CYREG_PRT4_SLW -#define SCSI_In__5__AG CYREG_PRT4_AG -#define SCSI_In__5__AMUX CYREG_PRT4_AMUX -#define SCSI_In__5__BIE CYREG_PRT4_BIE -#define SCSI_In__5__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_In__5__BYP CYREG_PRT4_BYP -#define SCSI_In__5__CTL CYREG_PRT4_CTL -#define SCSI_In__5__DM0 CYREG_PRT4_DM0 -#define SCSI_In__5__DM1 CYREG_PRT4_DM1 -#define SCSI_In__5__DM2 CYREG_PRT4_DM2 -#define SCSI_In__5__DR CYREG_PRT4_DR -#define SCSI_In__5__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_In__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_In__5__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_In__5__MASK 0x04u -#define SCSI_In__5__PC CYREG_PRT4_PC2 -#define SCSI_In__5__PORT 4u -#define SCSI_In__5__PRT CYREG_PRT4_PRT -#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_In__5__PS CYREG_PRT4_PS -#define SCSI_In__5__SHIFT 2 -#define SCSI_In__5__SLW CYREG_PRT4_SLW -#define SCSI_In__6__AG CYREG_PRT0_AG -#define SCSI_In__6__AMUX CYREG_PRT0_AMUX -#define SCSI_In__6__BIE CYREG_PRT0_BIE -#define SCSI_In__6__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_In__6__BYP CYREG_PRT0_BYP -#define SCSI_In__6__CTL CYREG_PRT0_CTL -#define SCSI_In__6__DM0 CYREG_PRT0_DM0 -#define SCSI_In__6__DM1 CYREG_PRT0_DM1 -#define SCSI_In__6__DM2 CYREG_PRT0_DM2 -#define SCSI_In__6__DR CYREG_PRT0_DR -#define SCSI_In__6__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_In__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_In__6__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_In__6__MASK 0x20u -#define SCSI_In__6__PC CYREG_PRT0_PC5 -#define SCSI_In__6__PORT 0u -#define SCSI_In__6__PRT CYREG_PRT0_PRT -#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_In__6__PS CYREG_PRT0_PS -#define SCSI_In__6__SHIFT 5 -#define SCSI_In__6__SLW CYREG_PRT0_SLW -#define SCSI_In__7__AG CYREG_PRT0_AG -#define SCSI_In__7__AMUX CYREG_PRT0_AMUX -#define SCSI_In__7__BIE CYREG_PRT0_BIE -#define SCSI_In__7__BIT_MASK CYREG_PRT0_BIT_MASK -#define SCSI_In__7__BYP CYREG_PRT0_BYP -#define SCSI_In__7__CTL CYREG_PRT0_CTL -#define SCSI_In__7__DM0 CYREG_PRT0_DM0 -#define SCSI_In__7__DM1 CYREG_PRT0_DM1 -#define SCSI_In__7__DM2 CYREG_PRT0_DM2 -#define SCSI_In__7__DR CYREG_PRT0_DR -#define SCSI_In__7__INP_DIS CYREG_PRT0_INP_DIS -#define SCSI_In__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG -#define SCSI_In__7__LCD_EN CYREG_PRT0_LCD_EN -#define SCSI_In__7__MASK 0x10u -#define SCSI_In__7__PC CYREG_PRT0_PC4 -#define SCSI_In__7__PORT 0u -#define SCSI_In__7__PRT CYREG_PRT0_PRT -#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL -#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN -#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 -#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 -#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 -#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 -#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT -#define SCSI_In__7__PS CYREG_PRT0_PS -#define SCSI_In__7__SHIFT 4 -#define SCSI_In__7__SLW CYREG_PRT0_SLW -#define SCSI_In__ACK__AG CYREG_PRT6_AG -#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX -#define SCSI_In__ACK__BIE CYREG_PRT6_BIE -#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__ACK__BYP CYREG_PRT6_BYP -#define SCSI_In__ACK__CTL CYREG_PRT6_CTL -#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0 -#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1 -#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2 -#define SCSI_In__ACK__DR CYREG_PRT6_DR -#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__ACK__MASK 0x04u -#define SCSI_In__ACK__PC CYREG_PRT6_PC2 -#define SCSI_In__ACK__PORT 6u -#define SCSI_In__ACK__PRT CYREG_PRT6_PRT -#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__ACK__PS CYREG_PRT6_PS -#define SCSI_In__ACK__SHIFT 2 -#define SCSI_In__ACK__SLW CYREG_PRT6_SLW -#define SCSI_In__BSY__AG CYREG_PRT6_AG -#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX -#define SCSI_In__BSY__BIE CYREG_PRT6_BIE -#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK -#define SCSI_In__BSY__BYP CYREG_PRT6_BYP -#define SCSI_In__BSY__CTL CYREG_PRT6_CTL -#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0 -#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1 -#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2 -#define SCSI_In__BSY__DR CYREG_PRT6_DR -#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS -#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG -#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN -#define SCSI_In__BSY__MASK 0x08u -#define SCSI_In__BSY__PC CYREG_PRT6_PC3 -#define SCSI_In__BSY__PORT 6u -#define SCSI_In__BSY__PRT CYREG_PRT6_PRT -#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL -#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN -#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 -#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 -#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 -#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 -#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT -#define SCSI_In__BSY__PS CYREG_PRT6_PS -#define SCSI_In__BSY__SHIFT 3 -#define SCSI_In__BSY__SLW CYREG_PRT6_SLW +#define SCSI_In__2__SLW CYREG_PRT4_SLW +#define SCSI_In__3__AG CYREG_PRT0_AG +#define SCSI_In__3__AMUX CYREG_PRT0_AMUX +#define SCSI_In__3__BIE CYREG_PRT0_BIE +#define SCSI_In__3__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_In__3__BYP CYREG_PRT0_BYP +#define SCSI_In__3__CTL CYREG_PRT0_CTL +#define SCSI_In__3__DM0 CYREG_PRT0_DM0 +#define SCSI_In__3__DM1 CYREG_PRT0_DM1 +#define SCSI_In__3__DM2 CYREG_PRT0_DM2 +#define SCSI_In__3__DR CYREG_PRT0_DR +#define SCSI_In__3__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_In__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_In__3__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_In__3__MASK 0x20u +#define SCSI_In__3__PC CYREG_PRT0_PC5 +#define SCSI_In__3__PORT 0u +#define SCSI_In__3__PRT CYREG_PRT0_PRT +#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_In__3__PS CYREG_PRT0_PS +#define SCSI_In__3__SHIFT 5 +#define SCSI_In__3__SLW CYREG_PRT0_SLW +#define SCSI_In__4__AG CYREG_PRT0_AG +#define SCSI_In__4__AMUX CYREG_PRT0_AMUX +#define SCSI_In__4__BIE CYREG_PRT0_BIE +#define SCSI_In__4__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_In__4__BYP CYREG_PRT0_BYP +#define SCSI_In__4__CTL CYREG_PRT0_CTL +#define SCSI_In__4__DM0 CYREG_PRT0_DM0 +#define SCSI_In__4__DM1 CYREG_PRT0_DM1 +#define SCSI_In__4__DM2 CYREG_PRT0_DM2 +#define SCSI_In__4__DR CYREG_PRT0_DR +#define SCSI_In__4__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_In__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_In__4__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_In__4__MASK 0x10u +#define SCSI_In__4__PC CYREG_PRT0_PC4 +#define SCSI_In__4__PORT 0u +#define SCSI_In__4__PRT CYREG_PRT0_PRT +#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_In__4__PS CYREG_PRT0_PS +#define SCSI_In__4__SHIFT 4 +#define SCSI_In__4__SLW CYREG_PRT0_SLW #define SCSI_In__CD__AG CYREG_PRT4_AG #define SCSI_In__CD__AMUX CYREG_PRT4_AMUX #define SCSI_In__CD__BIE CYREG_PRT4_BIE @@ -2559,33 +2629,6 @@ #define SCSI_In__REQ__PS CYREG_PRT0_PS #define SCSI_In__REQ__SHIFT 5 #define SCSI_In__REQ__SLW CYREG_PRT0_SLW -#define SCSI_In__SEL__AG CYREG_PRT4_AG -#define SCSI_In__SEL__AMUX CYREG_PRT4_AMUX -#define SCSI_In__SEL__BIE CYREG_PRT4_BIE -#define SCSI_In__SEL__BIT_MASK CYREG_PRT4_BIT_MASK -#define SCSI_In__SEL__BYP CYREG_PRT4_BYP -#define SCSI_In__SEL__CTL CYREG_PRT4_CTL -#define SCSI_In__SEL__DM0 CYREG_PRT4_DM0 -#define SCSI_In__SEL__DM1 CYREG_PRT4_DM1 -#define SCSI_In__SEL__DM2 CYREG_PRT4_DM2 -#define SCSI_In__SEL__DR CYREG_PRT4_DR -#define SCSI_In__SEL__INP_DIS CYREG_PRT4_INP_DIS -#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG -#define SCSI_In__SEL__LCD_EN CYREG_PRT4_LCD_EN -#define SCSI_In__SEL__MASK 0x08u -#define SCSI_In__SEL__PC CYREG_PRT4_PC3 -#define SCSI_In__SEL__PORT 4u -#define SCSI_In__SEL__PRT CYREG_PRT4_PRT -#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL -#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN -#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 -#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 -#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 -#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 -#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT -#define SCSI_In__SEL__PS CYREG_PRT4_PS -#define SCSI_In__SEL__SHIFT 3 -#define SCSI_In__SEL__SLW CYREG_PRT4_SLW /* SD_MISO */ #define SD_MISO__0__MASK 0x02u @@ -2886,7 +2929,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x1000 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000001Eu +#define CYDEV_INTR_RISING 0x0000003Eu #define CYDEV_PROJ_TYPE 2 #define CYDEV_PROJ_TYPE_BOOTLOADER 1 #define CYDEV_PROJ_TYPE_LOADABLE 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 4162415..8db788b 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 38u +#define CY_CFG_BASE_ADDR_COUNT 40u CYPACKED typedef struct { uint8 offset; @@ -333,9 +333,9 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { 0x33u, 0xCCu, 0xCCu, 0x00u, 0xCCu, 0x00u, 0x00u, 0x01u}; - /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 0x00u, 0x3Eu, 0x00u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u}; + 0x10u, 0x00u, 0x22u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u}; /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { @@ -378,1449 +378,1688 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40004502u, /* Base address: 0x40004500 Count: 2 */ + 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x40005210u, /* Base address: 0x40005200 Count: 16 */ - 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40010104u, /* Base address: 0x40010100 Count: 4 */ - 0x4001023Du, /* Base address: 0x40010200 Count: 61 */ - 0x40010340u, /* Base address: 0x40010300 Count: 64 */ - 0x40010451u, /* Base address: 0x40010400 Count: 81 */ - 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */ - 0x40010715u, /* Base address: 0x40010700 Count: 21 */ - 0x40010818u, /* Base address: 0x40010800 Count: 24 */ + 0x4000520Fu, /* Base address: 0x40005200 Count: 15 */ + 0x40006401u, /* Base address: 0x40006400 Count: 1 */ + 0x40006501u, /* Base address: 0x40006500 Count: 1 */ + 0x40010102u, /* Base address: 0x40010100 Count: 2 */ + 0x40010306u, /* Base address: 0x40010300 Count: 6 */ + 0x40010510u, /* Base address: 0x40010500 Count: 16 */ + 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ + 0x40010744u, /* Base address: 0x40010700 Count: 68 */ + 0x40010843u, /* Base address: 0x40010800 Count: 67 */ 0x40010952u, /* Base address: 0x40010900 Count: 82 */ - 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */ - 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */ - 0x40010C48u, /* Base address: 0x40010C00 Count: 72 */ - 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */ - 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */ - 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ - 0x4001150Bu, /* Base address: 0x40011500 Count: 11 */ - 0x4001170Fu, /* Base address: 0x40011700 Count: 15 */ - 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */ - 0x40011947u, /* Base address: 0x40011900 Count: 71 */ - 0x40011A48u, /* Base address: 0x40011A00 Count: 72 */ - 0x40011B57u, /* Base address: 0x40011B00 Count: 87 */ - 0x40014016u, /* Base address: 0x40014000 Count: 22 */ - 0x40014114u, /* Base address: 0x40014100 Count: 20 */ - 0x40014211u, /* Base address: 0x40014200 Count: 17 */ - 0x40014306u, /* Base address: 0x40014300 Count: 6 */ + 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */ + 0x40010B52u, /* Base address: 0x40010B00 Count: 82 */ + 0x40010C3Bu, /* Base address: 0x40010C00 Count: 59 */ + 0x40010D47u, /* Base address: 0x40010D00 Count: 71 */ + 0x40010E4Du, /* Base address: 0x40010E00 Count: 77 */ + 0x40010F34u, /* Base address: 0x40010F00 Count: 52 */ + 0x40011455u, /* Base address: 0x40011400 Count: 85 */ + 0x40011551u, /* Base address: 0x40011500 Count: 81 */ + 0x40011657u, /* Base address: 0x40011600 Count: 87 */ + 0x40011752u, /* Base address: 0x40011700 Count: 82 */ + 0x40011850u, /* Base address: 0x40011800 Count: 80 */ + 0x40011955u, /* Base address: 0x40011900 Count: 85 */ + 0x40011A52u, /* Base address: 0x40011A00 Count: 82 */ + 0x40011B60u, /* Base address: 0x40011B00 Count: 96 */ + 0x40014015u, /* Base address: 0x40014000 Count: 21 */ + 0x4001411Cu, /* Base address: 0x40014100 Count: 28 */ + 0x40014212u, /* Base address: 0x40014200 Count: 18 */ + 0x40014305u, /* Base address: 0x40014300 Count: 5 */ 0x40014411u, /* Base address: 0x40014400 Count: 17 */ - 0x40014513u, /* Base address: 0x40014500 Count: 19 */ - 0x40014610u, /* Base address: 0x40014600 Count: 16 */ - 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */ - 0x40014806u, /* Base address: 0x40014800 Count: 6 */ - 0x4001490Du, /* Base address: 0x40014900 Count: 13 */ - 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */ - 0x40014D0Fu, /* Base address: 0x40014D00 Count: 15 */ - 0x40015004u, /* Base address: 0x40015000 Count: 4 */ + 0x40014516u, /* Base address: 0x40014500 Count: 22 */ + 0x40014611u, /* Base address: 0x40014600 Count: 17 */ + 0x40014715u, /* Base address: 0x40014700 Count: 21 */ + 0x40014807u, /* Base address: 0x40014800 Count: 7 */ + 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */ + 0x40014C0Au, /* Base address: 0x40014C00 Count: 10 */ + 0x40014D11u, /* Base address: 0x40014D00 Count: 17 */ + 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { - {0x27u, 0x02u}, {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x4Bu}, + {0x0Au, 0x36u}, {0x00u, 0x08u}, - {0x01u, 0x40u}, + {0x01u, 0x08u}, {0x04u, 0x31u}, - {0x10u, 0x84u}, - {0x11u, 0x08u}, - {0x14u, 0x01u}, + {0x10u, 0xC4u}, + {0x11u, 0x8Cu}, {0x18u, 0x08u}, - {0x19u, 0x0Cu}, + {0x19u, 0x04u}, {0x1Cu, 0x20u}, {0x21u, 0x10u}, - {0x24u, 0x4Cu}, - {0x28u, 0x02u}, - {0x31u, 0x20u}, - {0x34u, 0x08u}, + {0x24u, 0x44u}, + {0x28u, 0x01u}, + {0x29u, 0x01u}, + {0x31u, 0x10u}, {0x78u, 0x20u}, {0x7Cu, 0x40u}, - {0x2Bu, 0x02u}, - {0x89u, 0x0Fu}, - {0x8Bu, 0x01u}, - {0x8Eu, 0x40u}, + {0x28u, 0x02u}, + {0x87u, 0x0Fu}, + {0x8Fu, 0x01u}, + {0xE6u, 0x80u}, + {0x93u, 0x01u}, + {0xE0u, 0x40u}, + {0xE4u, 0x10u}, + {0xE6u, 0x41u}, + {0xEAu, 0x04u}, + {0xEEu, 0x08u}, + {0x60u, 0x20u}, + {0x61u, 0x08u}, + {0x81u, 0x08u}, + {0x82u, 0x80u}, + {0x87u, 0x40u}, + {0x88u, 0x80u}, + {0x8Du, 0x20u}, + {0x91u, 0x20u}, + {0x93u, 0x01u}, + {0x98u, 0x14u}, + {0xACu, 0x14u}, + {0xB1u, 0x10u}, + {0xE2u, 0x2Du}, {0xE4u, 0x04u}, - {0xE6u, 0x22u}, - {0x04u, 0x01u}, + {0xEAu, 0x08u}, + {0xEEu, 0x02u}, + {0x00u, 0x08u}, + {0x01u, 0x01u}, + {0x04u, 0x11u}, + {0x05u, 0xA2u}, + {0x06u, 0x22u}, + {0x07u, 0x08u}, + {0x08u, 0x40u}, + {0x09u, 0x01u}, + {0x0Cu, 0x40u}, + {0x0Du, 0x01u}, + {0x10u, 0x1Cu}, + {0x11u, 0x08u}, + {0x13u, 0x61u}, + {0x14u, 0x10u}, + {0x15u, 0x07u}, + {0x16u, 0x0Cu}, + {0x17u, 0xD8u}, + {0x18u, 0x24u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x40u}, + {0x1Cu, 0x21u}, + {0x1Eu, 0x1Eu}, + {0x20u, 0x0Cu}, + {0x21u, 0x01u}, + {0x22u, 0x10u}, + {0x24u, 0x14u}, + {0x25u, 0x01u}, + {0x26u, 0x08u}, + {0x28u, 0x30u}, + {0x29u, 0x10u}, + {0x2Au, 0x0Fu}, + {0x2Cu, 0x1Cu}, + {0x2Du, 0x04u}, + {0x30u, 0x40u}, + {0x32u, 0x0Fu}, + {0x34u, 0x30u}, + {0x35u, 0xE0u}, + {0x37u, 0x3Fu}, + {0x38u, 0x02u}, + {0x39u, 0x80u}, + {0x3Au, 0x20u}, + {0x3Fu, 0x40u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Fu, 0x01u}, + {0x84u, 0x01u}, + {0x85u, 0x44u}, + {0x86u, 0x02u}, + {0x87u, 0x88u}, + {0x8Du, 0x99u}, + {0x8Fu, 0x22u}, + {0x90u, 0x02u}, + {0x91u, 0xAAu}, + {0x92u, 0x01u}, + {0x93u, 0x55u}, + {0x97u, 0x70u}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x05u}, + {0x9Fu, 0x07u}, + {0xA3u, 0x08u}, + {0xA4u, 0x02u}, + {0xA6u, 0x09u}, + {0xA8u, 0x02u}, + {0xAAu, 0x01u}, + {0xAFu, 0x80u}, + {0xB0u, 0x04u}, + {0xB3u, 0xF0u}, + {0xB4u, 0x03u}, + {0xB6u, 0x08u}, + {0xB7u, 0x0Fu}, + {0xBAu, 0x20u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x19u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x05u, 0x16u}, {0x07u, 0x02u}, - {0x0Fu, 0x01u}, - {0x15u, 0x01u}, - {0x17u, 0x02u}, - {0x1Cu, 0x01u}, - {0x28u, 0x01u}, - {0x2Cu, 0x01u}, - {0x31u, 0x03u}, + {0x0Au, 0x82u}, + {0x0Cu, 0x08u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x0Au}, + {0x10u, 0x10u}, + {0x11u, 0x20u}, + {0x15u, 0x08u}, + {0x16u, 0x02u}, + {0x17u, 0x21u}, + {0x18u, 0x04u}, + {0x1Au, 0x82u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x08u}, + {0x1Du, 0x05u}, + {0x1Eu, 0x28u}, + {0x1Fu, 0x22u}, + {0x21u, 0x88u}, + {0x26u, 0x20u}, + {0x27u, 0x02u}, + {0x29u, 0x80u}, + {0x2Au, 0x01u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x2Au}, + {0x31u, 0x88u}, + {0x32u, 0x02u}, + {0x35u, 0x04u}, + {0x36u, 0x21u}, + {0x38u, 0x80u}, + {0x3Bu, 0x04u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x48u}, + {0x3Eu, 0x02u}, + {0x66u, 0x94u}, + {0x67u, 0x40u}, + {0x81u, 0x04u}, + {0x85u, 0x80u}, + {0x86u, 0x10u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x04u}, + {0x90u, 0x80u}, + {0x91u, 0x20u}, + {0x93u, 0x01u}, + {0x97u, 0x40u}, + {0x98u, 0xB4u}, + {0x9Au, 0x40u}, + {0x9Du, 0x20u}, + {0xA0u, 0x20u}, + {0xA3u, 0x40u}, + {0xA6u, 0x80u}, + {0xA8u, 0x40u}, + {0xABu, 0x40u}, + {0xB0u, 0x20u}, + {0xB2u, 0x40u}, + {0xC0u, 0xF4u}, + {0xC2u, 0xF9u}, + {0xC4u, 0xF6u}, + {0xCAu, 0xF9u}, + {0xCCu, 0xEBu}, + {0xCEu, 0xFAu}, + {0xD8u, 0xF0u}, + {0xE0u, 0x04u}, + {0xE2u, 0x08u}, + {0xE4u, 0x08u}, + {0xEAu, 0x0Du}, + {0xEEu, 0x01u}, + {0x01u, 0x04u}, + {0x02u, 0x01u}, + {0x03u, 0x08u}, + {0x05u, 0x02u}, + {0x15u, 0x08u}, + {0x17u, 0x04u}, + {0x1Du, 0x18u}, + {0x20u, 0x02u}, + {0x25u, 0x04u}, + {0x27u, 0x10u}, + {0x2Du, 0x01u}, + {0x30u, 0x02u}, + {0x31u, 0x01u}, {0x32u, 0x01u}, - {0x38u, 0x08u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, - {0x54u, 0x01u}, + {0x35u, 0x02u}, + {0x37u, 0x1Cu}, + {0x39u, 0x80u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x11u}, + {0x40u, 0x24u}, + {0x41u, 0x03u}, + {0x42u, 0x50u}, + {0x45u, 0xDEu}, + {0x46u, 0x02u}, + {0x47u, 0xCFu}, + {0x48u, 0x37u}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Du, 0x10u}, + {0x5Cu, 0x09u}, + {0x5Du, 0x01u}, {0x5Fu, 0x01u}, - {0x81u, 0x04u}, - {0x85u, 0x08u}, - {0x86u, 0x0Eu}, - {0x88u, 0x14u}, - {0x89u, 0x01u}, - {0x8Au, 0x0Au}, - {0x8Bu, 0x02u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x38u}, - {0x92u, 0x40u}, - {0x93u, 0x40u}, - {0x94u, 0x08u}, - {0x96u, 0x10u}, - {0x97u, 0x01u}, - {0x98u, 0x01u}, - {0x99u, 0x38u}, - {0x9Cu, 0x12u}, - {0x9Eu, 0x04u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x01u}, - {0xA1u, 0x20u}, - {0xA4u, 0x20u}, - {0xA6u, 0x40u}, - {0xAAu, 0x20u}, - {0xABu, 0x02u}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0x81u, 0x80u}, + {0x8Bu, 0x07u}, + {0x91u, 0x6Au}, + {0x93u, 0x15u}, + {0x95u, 0x19u}, + {0x97u, 0x22u}, + {0x99u, 0x14u}, + {0x9Bu, 0x48u}, + {0x9Fu, 0x08u}, + {0xA3u, 0x20u}, + {0xA7u, 0x70u}, + {0xA8u, 0x02u}, {0xACu, 0x01u}, - {0xB1u, 0x04u}, - {0xB2u, 0x1Eu}, - {0xB3u, 0x38u}, - {0xB4u, 0x60u}, - {0xB5u, 0x40u}, - {0xB6u, 0x01u}, - {0xB7u, 0x03u}, - {0xBEu, 0x50u}, - {0xBFu, 0x44u}, - {0xD6u, 0x08u}, + {0xB2u, 0x01u}, + {0xB3u, 0x0Fu}, + {0xB4u, 0x02u}, + {0xB5u, 0x70u}, + {0xB7u, 0x80u}, + {0xBEu, 0x14u}, + {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x90u}, + {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x01u, 0x28u}, - {0x02u, 0x02u}, - {0x04u, 0x04u}, - {0x08u, 0x40u}, - {0x09u, 0x04u}, - {0x0Au, 0x40u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x01u}, - {0x12u, 0x81u}, - {0x13u, 0x28u}, - {0x14u, 0x01u}, - {0x17u, 0x10u}, - {0x18u, 0x02u}, - {0x19u, 0x0Cu}, - {0x1Bu, 0x20u}, - {0x1Cu, 0x20u}, - {0x21u, 0x50u}, - {0x22u, 0x05u}, - {0x24u, 0x80u}, - {0x2Au, 0x11u}, - {0x2Bu, 0x80u}, - {0x31u, 0x14u}, - {0x32u, 0x81u}, + {0x06u, 0x80u}, + {0x09u, 0x02u}, + {0x0Bu, 0x80u}, + {0x12u, 0x05u}, + {0x16u, 0x40u}, + {0x18u, 0x10u}, + {0x19u, 0x10u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x20u}, + {0x21u, 0x30u}, + {0x23u, 0x16u}, + {0x26u, 0x82u}, + {0x27u, 0x08u}, + {0x2Bu, 0x60u}, + {0x2Eu, 0x08u}, + {0x2Fu, 0x01u}, + {0x31u, 0x2Au}, {0x33u, 0x40u}, - {0x37u, 0x08u}, - {0x38u, 0x40u}, - {0x3Au, 0x20u}, - {0x3Bu, 0x05u}, - {0x3Du, 0x80u}, - {0x3Eu, 0x04u}, - {0x5Au, 0x80u}, - {0x5Fu, 0x80u}, - {0x63u, 0x01u}, - {0x6Cu, 0x20u}, - {0x6Fu, 0x09u}, - {0x80u, 0x40u}, - {0x85u, 0x10u}, - {0x87u, 0x80u}, - {0x88u, 0x20u}, - {0x8Bu, 0x20u}, - {0x8Du, 0x10u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x08u}, - {0x92u, 0x80u}, - {0x93u, 0x40u}, - {0x95u, 0x20u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x08u}, - {0xA8u, 0x08u}, - {0xADu, 0x10u}, - {0xB3u, 0x40u}, - {0xC0u, 0x27u}, - {0xC2u, 0x8Fu}, - {0xC4u, 0xCFu}, - {0xCAu, 0x05u}, - {0xCCu, 0x4Fu}, - {0xCEu, 0x5Fu}, - {0xD6u, 0x18u}, - {0xD8u, 0x08u}, - {0xE0u, 0x03u}, - {0xE2u, 0x18u}, - {0xE6u, 0x38u}, - {0xE8u, 0x02u}, - {0xEAu, 0x01u}, - {0x01u, 0x05u}, - {0x03u, 0x0Au}, - {0x04u, 0x05u}, - {0x06u, 0x0Au}, - {0x09u, 0xA0u}, - {0x0Bu, 0x4Fu}, - {0x0Du, 0x03u}, - {0x0Fu, 0x0Cu}, - {0x10u, 0x60u}, - {0x12u, 0x90u}, - {0x13u, 0x70u}, - {0x15u, 0x06u}, - {0x17u, 0x09u}, - {0x18u, 0x30u}, - {0x19u, 0x0Fu}, - {0x1Au, 0xC0u}, - {0x1Cu, 0x03u}, - {0x1Du, 0x90u}, - {0x1Eu, 0x0Cu}, - {0x1Fu, 0x2Fu}, - {0x21u, 0x80u}, - {0x24u, 0x50u}, - {0x26u, 0xA0u}, - {0x27u, 0x80u}, - {0x28u, 0x06u}, - {0x29u, 0xC0u}, - {0x2Au, 0x09u}, - {0x2Bu, 0x1Fu}, - {0x2Cu, 0x0Fu}, - {0x2Eu, 0xF0u}, - {0x30u, 0xFFu}, - {0x31u, 0x7Fu}, - {0x37u, 0x80u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, + {0x34u, 0x40u}, + {0x36u, 0x88u}, + {0x3Bu, 0x11u}, + {0x3Fu, 0x0Au}, + {0x44u, 0x88u}, + {0x45u, 0x2Au}, + {0x49u, 0x80u}, + {0x4Au, 0x02u}, + {0x4Cu, 0x01u}, + {0x4Du, 0x02u}, + {0x4Eu, 0x20u}, + {0x54u, 0x08u}, + {0x56u, 0x02u}, + {0x57u, 0x40u}, + {0x5Cu, 0x10u}, + {0x5Eu, 0x40u}, + {0x5Fu, 0x0Au}, + {0x65u, 0x95u}, + {0x6Du, 0x02u}, + {0x6Fu, 0x16u}, + {0x74u, 0x60u}, + {0x76u, 0x10u}, + {0x77u, 0x40u}, + {0x82u, 0x08u}, + {0x87u, 0x03u}, + {0x89u, 0x10u}, + {0x8Eu, 0x20u}, + {0x90u, 0xCCu}, + {0x91u, 0x40u}, + {0x92u, 0x10u}, + {0x93u, 0x03u}, + {0x96u, 0x20u}, + {0x97u, 0x84u}, + {0x9Au, 0x05u}, + {0x9Cu, 0x92u}, + {0x9Du, 0x40u}, + {0x9Eu, 0xE2u}, + {0x9Fu, 0x20u}, + {0xA0u, 0x96u}, + {0xA1u, 0x0Cu}, + {0xA3u, 0x34u}, + {0xA4u, 0x68u}, + {0xA5u, 0x41u}, + {0xA6u, 0x30u}, + {0xA7u, 0x40u}, + {0xA9u, 0x18u}, + {0xAAu, 0x08u}, + {0xACu, 0x40u}, + {0xB1u, 0x08u}, + {0xB2u, 0x40u}, + {0xB3u, 0x09u}, + {0xC0u, 0x10u}, + {0xC4u, 0x13u}, + {0xCAu, 0x53u}, + {0xCCu, 0x5Fu}, + {0xCEu, 0xC5u}, + {0xD0u, 0xE0u}, + {0xD2u, 0x10u}, + {0xD6u, 0xF0u}, + {0xD8u, 0xF0u}, + {0xE4u, 0x40u}, + {0xE6u, 0x20u}, + {0xEAu, 0x08u}, + {0xEEu, 0xADu}, + {0x04u, 0x02u}, + {0x05u, 0x01u}, + {0x06u, 0x01u}, + {0x07u, 0x02u}, + {0x08u, 0x01u}, + {0x09u, 0x02u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x05u}, + {0x14u, 0x02u}, + {0x15u, 0x02u}, + {0x16u, 0x05u}, + {0x17u, 0x01u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x02u}, + {0x1Eu, 0x01u}, + {0x1Fu, 0x01u}, + {0x20u, 0x02u}, + {0x21u, 0x02u}, + {0x22u, 0x11u}, + {0x23u, 0x09u}, + {0x2Au, 0x08u}, + {0x30u, 0x08u}, + {0x32u, 0x03u}, + {0x33u, 0x03u}, + {0x34u, 0x10u}, + {0x35u, 0x08u}, + {0x36u, 0x04u}, + {0x37u, 0x04u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x08u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x10u}, + {0x5Cu, 0x99u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x03u}, - {0x83u, 0x0Cu}, - {0x85u, 0x09u}, - {0x87u, 0x06u}, - {0x89u, 0x50u}, - {0x8Au, 0xFFu}, - {0x8Bu, 0xA0u}, - {0x8Cu, 0xFFu}, - {0x8Du, 0x0Fu}, - {0x8Fu, 0xF0u}, - {0x90u, 0x05u}, - {0x92u, 0x0Au}, - {0x93u, 0xFFu}, - {0x94u, 0x50u}, - {0x95u, 0x90u}, - {0x96u, 0xA0u}, - {0x97u, 0x60u}, - {0x98u, 0x06u}, - {0x9Au, 0x09u}, - {0x9Bu, 0xFFu}, - {0x9Cu, 0x30u}, - {0x9Du, 0x05u}, - {0x9Eu, 0xC0u}, - {0x9Fu, 0x0Au}, - {0xA0u, 0x03u}, - {0xA1u, 0x30u}, - {0xA2u, 0x0Cu}, - {0xA3u, 0xC0u}, - {0xA6u, 0xFFu}, - {0xA7u, 0xFFu}, - {0xA8u, 0x60u}, - {0xAAu, 0x90u}, - {0xACu, 0x0Fu}, - {0xAEu, 0xF0u}, - {0xB3u, 0xFFu}, - {0xB6u, 0xFFu}, - {0xBEu, 0x40u}, - {0xBFu, 0x04u}, + {0x80u, 0x80u}, + {0x84u, 0x80u}, + {0x85u, 0x44u}, + {0x87u, 0x88u}, + {0x88u, 0x07u}, + {0x8Au, 0x28u}, + {0x8Bu, 0x70u}, + {0x8Cu, 0x80u}, + {0x8Fu, 0x80u}, + {0x92u, 0x02u}, + {0x94u, 0x35u}, + {0x96u, 0x4Au}, + {0x9Au, 0x73u}, + {0x9Bu, 0x07u}, + {0x9Cu, 0x03u}, + {0x9Eu, 0x0Cu}, + {0xA0u, 0x46u}, + {0xA1u, 0xAAu}, + {0xA2u, 0x39u}, + {0xA3u, 0x55u}, + {0xA4u, 0x11u}, + {0xA7u, 0x08u}, + {0xA8u, 0x80u}, + {0xA9u, 0x99u}, + {0xABu, 0x22u}, + {0xB0u, 0x80u}, + {0xB2u, 0x70u}, + {0xB3u, 0x0Fu}, + {0xB5u, 0xF0u}, + {0xB6u, 0x0Fu}, + {0xB8u, 0x02u}, + {0xBAu, 0x80u}, + {0xBEu, 0x01u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x04u, 0x80u}, + {0x00u, 0x04u}, + {0x03u, 0x08u}, + {0x04u, 0x02u}, + {0x05u, 0x44u}, {0x06u, 0x08u}, - {0x09u, 0x40u}, - {0x0Au, 0x44u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x80u}, - {0x0Fu, 0x14u}, - {0x11u, 0x40u}, - {0x12u, 0x10u}, - {0x13u, 0x20u}, - {0x14u, 0x14u}, - {0x15u, 0x41u}, - {0x18u, 0x80u}, + {0x0Au, 0x21u}, + {0x0Eu, 0x1Au}, + {0x0Fu, 0x80u}, + {0x10u, 0x04u}, + {0x12u, 0x80u}, + {0x14u, 0x80u}, + {0x15u, 0x04u}, + {0x17u, 0x20u}, + {0x18u, 0x04u}, {0x19u, 0x02u}, - {0x1Eu, 0x01u}, - {0x21u, 0x02u}, - {0x22u, 0x80u}, - {0x23u, 0x80u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x08u}, + {0x1Du, 0x08u}, + {0x1Eu, 0x92u}, + {0x21u, 0x14u}, + {0x22u, 0x44u}, + {0x25u, 0x10u}, + {0x26u, 0x08u}, {0x27u, 0x10u}, - {0x29u, 0x04u}, - {0x2Au, 0x20u}, - {0x2Bu, 0x80u}, - {0x2Cu, 0x80u}, - {0x2Eu, 0x08u}, - {0x2Fu, 0x20u}, - {0x30u, 0x78u}, - {0x31u, 0x02u}, - {0x32u, 0x20u}, - {0x34u, 0x84u}, - {0x35u, 0x02u}, - {0x36u, 0x64u}, - {0x3Au, 0x01u}, - {0x3Bu, 0x60u}, - {0x3Du, 0x41u}, - {0x3Fu, 0x96u}, - {0x59u, 0x85u}, - {0x5Au, 0x10u}, - {0x62u, 0x80u}, - {0x80u, 0x80u}, - {0x83u, 0x40u}, - {0x84u, 0x40u}, - {0x86u, 0x02u}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x80u}, - {0x92u, 0x10u}, - {0x93u, 0x40u}, - {0x94u, 0x44u}, - {0x96u, 0x45u}, - {0x99u, 0x08u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x41u}, - {0x9Du, 0x20u}, - {0x9Eu, 0x10u}, - {0x9Fu, 0xD0u}, - {0xA0u, 0x28u}, - {0xA3u, 0x40u}, - {0xA5u, 0x44u}, - {0xA6u, 0x02u}, - {0xA9u, 0x40u}, - {0xAEu, 0x04u}, - {0xAFu, 0x04u}, - {0xB0u, 0x10u}, - {0xB4u, 0x01u}, - {0xB6u, 0x20u}, - {0xB7u, 0x68u}, - {0xC0u, 0xC4u}, - {0xC2u, 0xFBu}, - {0xC4u, 0xF7u}, - {0xCAu, 0xC7u}, - {0xCCu, 0xFFu}, - {0xCEu, 0xFDu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x08u}, - {0xE2u, 0x0Eu}, - {0xE6u, 0x39u}, - {0xE8u, 0x01u}, - {0xEAu, 0x02u}, - {0x81u, 0x04u}, - {0x82u, 0x20u}, - {0x89u, 0x40u}, - {0x90u, 0x80u}, - {0x94u, 0x44u}, - {0x96u, 0x44u}, - {0x97u, 0x10u}, - {0x9Cu, 0x81u}, - {0x9Eu, 0x30u}, - {0xA5u, 0x44u}, - {0xA6u, 0x04u}, - {0xA7u, 0x20u}, + {0x29u, 0x02u}, + {0x2Cu, 0x20u}, + {0x2Eu, 0x10u}, + {0x2Fu, 0x40u}, + {0x30u, 0x04u}, + {0x32u, 0x40u}, + {0x37u, 0x10u}, + {0x39u, 0x28u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x24u}, + {0x58u, 0x41u}, + {0x59u, 0x18u}, + {0x5Eu, 0x40u}, + {0x61u, 0x80u}, + {0x62u, 0x05u}, + {0x63u, 0x19u}, + {0x67u, 0x02u}, + {0x80u, 0x09u}, + {0x88u, 0x01u}, + {0x8Au, 0x20u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x40u}, + {0x90u, 0xC8u}, + {0x91u, 0x44u}, + {0x96u, 0x08u}, + {0x97u, 0x96u}, + {0x98u, 0x04u}, + {0x9Bu, 0x09u}, + {0x9Cu, 0x92u}, + {0x9Eu, 0xEBu}, + {0xA0u, 0x96u}, + {0xA1u, 0x04u}, + {0xA2u, 0x84u}, + {0xA3u, 0x20u}, + {0xA5u, 0xC9u}, + {0xA6u, 0x19u}, + {0xA7u, 0x0Cu}, {0xA9u, 0x80u}, - {0xADu, 0x20u}, + {0xACu, 0x10u}, {0xAFu, 0x10u}, - {0xB3u, 0x05u}, - {0xB5u, 0x05u}, - {0xE2u, 0x04u}, - {0xE4u, 0x80u}, + {0xB0u, 0x20u}, + {0xB1u, 0x02u}, + {0xB3u, 0x20u}, + {0xB7u, 0x48u}, + {0xC0u, 0xF6u}, + {0xC2u, 0xF5u}, + {0xC4u, 0x7Au}, + {0xCAu, 0xE1u}, + {0xCCu, 0x2Au}, + {0xCEu, 0x76u}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE0u, 0x10u}, + {0xE2u, 0x2Cu}, {0xEAu, 0x04u}, - {0xEEu, 0x82u}, - {0x03u, 0x08u}, - {0x13u, 0x07u}, - {0x15u, 0x19u}, - {0x17u, 0x22u}, - {0x19u, 0x14u}, - {0x1Bu, 0x48u}, - {0x1Du, 0x80u}, - {0x21u, 0x6Au}, - {0x23u, 0x15u}, - {0x24u, 0x02u}, - {0x27u, 0x20u}, - {0x28u, 0x01u}, - {0x2Fu, 0x70u}, - {0x32u, 0x02u}, - {0x33u, 0x70u}, - {0x34u, 0x01u}, - {0x35u, 0x80u}, - {0x37u, 0x0Fu}, - {0x3Eu, 0x14u}, - {0x3Fu, 0x10u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Fu, 0x01u}, - {0x00u, 0xA0u}, - {0x01u, 0x01u}, - {0x0Au, 0xAAu}, - {0x11u, 0x40u}, - {0x12u, 0x60u}, - {0x13u, 0x02u}, - {0x14u, 0x28u}, - {0x17u, 0x08u}, - {0x19u, 0x02u}, - {0x1Cu, 0x10u}, - {0x1Fu, 0x10u}, - {0x20u, 0x04u}, - {0x21u, 0x10u}, - {0x22u, 0x15u}, - {0x23u, 0x10u}, - {0x27u, 0x15u}, - {0x29u, 0x20u}, - {0x2Au, 0x40u}, - {0x2Bu, 0x08u}, - {0x2Cu, 0x40u}, - {0x2Du, 0x88u}, - {0x2Fu, 0x40u}, - {0x32u, 0x55u}, - {0x34u, 0x80u}, - {0x35u, 0x04u}, - {0x37u, 0x11u}, - {0x39u, 0x55u}, - {0x3Cu, 0x02u}, - {0x40u, 0x40u}, - {0x41u, 0x14u}, - {0x46u, 0x20u}, - {0x47u, 0x04u}, - {0x48u, 0x40u}, - {0x49u, 0x41u}, - {0x4Bu, 0x14u}, - {0x52u, 0x11u}, - {0x53u, 0x0Cu}, - {0x62u, 0x08u}, - {0x68u, 0x1Cu}, - {0x69u, 0x55u}, - {0x73u, 0x02u}, - {0x83u, 0x10u}, - {0x89u, 0x04u}, - {0x8Bu, 0x01u}, - {0x90u, 0x08u}, - {0x92u, 0x04u}, - {0x93u, 0x82u}, - {0x94u, 0x10u}, - {0x95u, 0x65u}, - {0x96u, 0xEAu}, - {0x97u, 0x20u}, - {0x98u, 0x12u}, - {0x99u, 0x8Cu}, - {0x9Au, 0x82u}, - {0x9Cu, 0x88u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x20u}, - {0x9Fu, 0x1Au}, - {0xA0u, 0x81u}, - {0xA1u, 0x08u}, - {0xA2u, 0x30u}, - {0xA4u, 0x54u}, - {0xA5u, 0x04u}, - {0xA6u, 0x02u}, - {0xA7u, 0x01u}, - {0xA9u, 0x20u}, - {0xADu, 0x80u}, - {0xB2u, 0x15u}, - {0xB6u, 0x09u}, - {0xC0u, 0x0Bu}, - {0xC2u, 0x0Fu}, - {0xC4u, 0x6Du}, - {0xCAu, 0xDCu}, - {0xCCu, 0xFFu}, - {0xCEu, 0x8Fu}, - {0xD0u, 0x07u}, - {0xD2u, 0x0Cu}, - {0xD8u, 0x02u}, - {0xE4u, 0x80u}, - {0xE6u, 0x20u}, - {0xEAu, 0x90u}, - {0xEEu, 0xE0u}, - {0x00u, 0xC0u}, - {0x02u, 0x02u}, - {0x04u, 0xC0u}, - {0x06u, 0x08u}, - {0x08u, 0xC0u}, - {0x0Au, 0x04u}, - {0x0Eu, 0x9Fu}, - {0x11u, 0x01u}, - {0x12u, 0xFFu}, - {0x14u, 0x1Fu}, - {0x16u, 0x20u}, - {0x18u, 0x7Fu}, - {0x1Au, 0x80u}, - {0x1Cu, 0x80u}, - {0x20u, 0xC0u}, - {0x21u, 0x02u}, - {0x22u, 0x01u}, - {0x26u, 0x60u}, - {0x29u, 0x02u}, - {0x2Cu, 0x90u}, - {0x2Du, 0x04u}, - {0x2Eu, 0x40u}, - {0x31u, 0x01u}, - {0x34u, 0xFFu}, - {0x35u, 0x02u}, - {0x37u, 0x04u}, - {0x39u, 0x20u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x41u}, + {0xEEu, 0x20u}, + {0x00u, 0x96u}, + {0x02u, 0x69u}, + {0x04u, 0xFFu}, + {0x0Au, 0xFFu}, + {0x10u, 0x0Fu}, + {0x12u, 0xF0u}, + {0x16u, 0xFFu}, + {0x1Au, 0xFFu}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x33u}, + {0x1Eu, 0xCCu}, + {0x20u, 0xFFu}, + {0x24u, 0x55u}, + {0x26u, 0xAAu}, + {0x30u, 0xFFu}, + {0x33u, 0x01u}, + {0x3Au, 0x02u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x91u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x86u, 0x58u}, - {0x89u, 0x01u}, - {0x8Eu, 0xFEu}, - {0x94u, 0x76u}, - {0x96u, 0x80u}, - {0x98u, 0x06u}, - {0x9Au, 0x08u}, - {0x9Cu, 0x9Eu}, - {0x9Eu, 0x60u}, - {0xA0u, 0x20u}, - {0xA2u, 0x02u}, - {0xA8u, 0x06u}, - {0xACu, 0x04u}, - {0xB0u, 0x01u}, - {0xB2u, 0xE0u}, - {0xB5u, 0x01u}, - {0xB6u, 0x1Eu}, - {0xBEu, 0x01u}, - {0xBFu, 0x10u}, - {0xC0u, 0x21u}, - {0xC1u, 0x03u}, - {0xC2u, 0x60u}, - {0xC5u, 0xF2u}, - {0xC6u, 0xE0u}, - {0xC7u, 0xDCu}, - {0xC8u, 0x3Bu}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCFu, 0x2Cu}, - {0xD6u, 0x01u}, + {0x84u, 0x01u}, + {0x86u, 0x02u}, + {0x87u, 0xFFu}, + {0x89u, 0xFFu}, + {0x8Du, 0xFFu}, + {0x90u, 0x02u}, + {0x91u, 0x0Fu}, + {0x92u, 0x09u}, + {0x93u, 0xF0u}, + {0x94u, 0x02u}, + {0x96u, 0x01u}, + {0x97u, 0xFFu}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x11u}, + {0xA1u, 0x55u}, + {0xA3u, 0xAAu}, + {0xA4u, 0x02u}, + {0xA6u, 0x05u}, + {0xA7u, 0xFFu}, + {0xA9u, 0x69u}, + {0xABu, 0x96u}, + {0xADu, 0x33u}, + {0xAFu, 0xCCu}, + {0xB0u, 0x04u}, + {0xB1u, 0xFFu}, + {0xB2u, 0x10u}, + {0xB4u, 0x03u}, + {0xB6u, 0x08u}, + {0xBAu, 0x20u}, + {0xBBu, 0x02u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDAu, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, - {0xDDu, 0x01u}, + {0xDCu, 0x19u}, {0xDFu, 0x01u}, - {0xE2u, 0xC0u}, - {0xE6u, 0x80u}, - {0xE8u, 0x40u}, - {0xE9u, 0x40u}, - {0xEEu, 0x08u}, - {0x00u, 0xA8u}, - {0x01u, 0x01u}, - {0x03u, 0x20u}, - {0x05u, 0x80u}, - {0x06u, 0x40u}, - {0x07u, 0x10u}, - {0x08u, 0x01u}, - {0x0Au, 0xAAu}, + {0x00u, 0x04u}, + {0x06u, 0x68u}, + {0x0Au, 0xA1u}, + {0x0Cu, 0x01u}, {0x0Du, 0x08u}, - {0x0Eu, 0x0Au}, - {0x10u, 0x40u}, - {0x11u, 0x40u}, - {0x12u, 0x20u}, - {0x13u, 0x02u}, - {0x16u, 0x89u}, - {0x17u, 0x01u}, - {0x19u, 0x20u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x8Cu}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x4Cu}, - {0x22u, 0x20u}, - {0x23u, 0x41u}, - {0x24u, 0x04u}, - {0x29u, 0x62u}, - {0x31u, 0x01u}, - {0x3Fu, 0x10u}, - {0x45u, 0x88u}, - {0x47u, 0x10u}, - {0x4Cu, 0x40u}, - {0x4Du, 0x18u}, - {0x4Fu, 0x04u}, - {0x55u, 0x20u}, - {0x56u, 0x09u}, - {0x5Cu, 0x55u}, - {0x66u, 0x20u}, - {0x67u, 0x61u}, - {0x6Cu, 0x95u}, - {0x74u, 0x29u}, - {0x76u, 0x02u}, - {0x81u, 0x04u}, - {0x82u, 0x40u}, - {0x84u, 0x08u}, - {0x87u, 0x04u}, - {0x8Eu, 0x06u}, - {0x8Fu, 0x02u}, - {0x90u, 0x01u}, - {0x91u, 0x10u}, - {0x92u, 0x05u}, - {0x93u, 0x12u}, - {0x94u, 0xA2u}, - {0x95u, 0x65u}, - {0x96u, 0x48u}, - {0x97u, 0x84u}, - {0x98u, 0x12u}, - {0x99u, 0xC1u}, - {0x9Au, 0x40u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0xC9u}, - {0x9Du, 0x04u}, - {0x9Fu, 0x18u}, - {0xA2u, 0x14u}, - {0xA3u, 0x02u}, - {0xA4u, 0x20u}, - {0xA5u, 0x2Cu}, - {0xA6u, 0x01u}, - {0xA7u, 0x29u}, - {0xADu, 0x10u}, - {0xB0u, 0x10u}, - {0xB4u, 0x02u}, - {0xB6u, 0x42u}, - {0xB7u, 0x01u}, - {0xC0u, 0xBFu}, - {0xC2u, 0xEFu}, - {0xC4u, 0xDDu}, - {0xCAu, 0x0Du}, - {0xCCu, 0x01u}, - {0xCEu, 0x20u}, - {0xD0u, 0x70u}, - {0xD2u, 0x20u}, - {0xD6u, 0xF0u}, - {0xD8u, 0xF0u}, - {0xE2u, 0x48u}, - {0xE6u, 0x70u}, - {0xE8u, 0x41u}, - {0xECu, 0x80u}, - {0xEEu, 0x50u}, - {0x02u, 0x08u}, - {0x04u, 0x99u}, - {0x05u, 0x20u}, - {0x06u, 0x22u}, - {0x0Au, 0x80u}, + {0x0Eu, 0x88u}, {0x0Fu, 0x01u}, - {0x13u, 0x0Eu}, - {0x16u, 0x70u}, - {0x19u, 0x08u}, - {0x1Au, 0x07u}, - {0x1Bu, 0x10u}, - {0x1Cu, 0xAAu}, - {0x1Eu, 0x55u}, - {0x21u, 0x14u}, - {0x23u, 0x0Au}, + {0x12u, 0x10u}, + {0x14u, 0x90u}, + {0x18u, 0x04u}, + {0x19u, 0x20u}, + {0x1Au, 0xA1u}, + {0x1Eu, 0x80u}, + {0x20u, 0x80u}, + {0x21u, 0x02u}, {0x27u, 0x10u}, - {0x28u, 0x44u}, - {0x29u, 0x12u}, - {0x2Au, 0x88u}, - {0x2Bu, 0x04u}, - {0x31u, 0x1Eu}, - {0x32u, 0xF0u}, + {0x28u, 0x02u}, + {0x2Au, 0x01u}, + {0x2Bu, 0x24u}, + {0x31u, 0x0Au}, + {0x36u, 0x10u}, + {0x39u, 0x10u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x84u}, + {0x59u, 0x22u}, + {0x5Au, 0x08u}, + {0x5Bu, 0x40u}, + {0x5Du, 0x80u}, + {0x5Eu, 0x04u}, + {0x5Fu, 0x20u}, + {0x63u, 0x02u}, + {0x64u, 0x04u}, + {0x67u, 0x21u}, + {0x68u, 0x90u}, + {0x6Bu, 0x09u}, + {0x70u, 0x66u}, + {0x82u, 0x01u}, + {0x85u, 0x10u}, + {0x87u, 0x01u}, + {0x8Au, 0x04u}, + {0x8Du, 0x44u}, + {0x8Fu, 0x20u}, + {0x90u, 0x40u}, + {0x91u, 0x04u}, + {0x97u, 0x16u}, + {0x9Au, 0x10u}, + {0x9Cu, 0x81u}, + {0x9Eu, 0xA2u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x04u}, + {0xA1u, 0x04u}, + {0xA2u, 0x84u}, + {0xA3u, 0x20u}, + {0xA4u, 0xE0u}, + {0xA5u, 0xC9u}, + {0xA6u, 0x18u}, + {0xA8u, 0x10u}, + {0xAAu, 0x40u}, + {0xADu, 0x10u}, + {0xC0u, 0x74u}, + {0xC2u, 0xFDu}, + {0xC4u, 0x34u}, + {0xCAu, 0x0Fu}, + {0xCCu, 0x23u}, + {0xCEu, 0x0Eu}, + {0xD6u, 0x7Fu}, + {0xD8u, 0x78u}, + {0xE0u, 0x40u}, + {0xE4u, 0x10u}, + {0xE6u, 0x40u}, + {0xECu, 0x01u}, + {0x01u, 0x55u}, + {0x03u, 0xAAu}, + {0x06u, 0x17u}, + {0x07u, 0xFFu}, + {0x09u, 0x69u}, + {0x0Bu, 0x96u}, + {0x0Du, 0x0Fu}, + {0x0Fu, 0xF0u}, + {0x12u, 0x08u}, + {0x14u, 0x09u}, + {0x16u, 0x02u}, + {0x17u, 0xFFu}, + {0x18u, 0x04u}, + {0x1Au, 0x08u}, + {0x1Cu, 0x0Au}, + {0x1Du, 0x33u}, + {0x1Eu, 0x05u}, + {0x1Fu, 0xCCu}, + {0x21u, 0xFFu}, + {0x22u, 0x20u}, + {0x26u, 0x80u}, + {0x27u, 0xFFu}, + {0x29u, 0xFFu}, + {0x2Au, 0x40u}, + {0x2Cu, 0x50u}, + {0x2Eu, 0xA0u}, + {0x30u, 0x30u}, + {0x32u, 0xC0u}, {0x34u, 0x0Fu}, - {0x35u, 0x01u}, - {0x37u, 0x20u}, - {0x3Fu, 0x40u}, + {0x37u, 0xFFu}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x05u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Bu, 0x04u}, {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x55u}, - {0x81u, 0x0Du}, - {0x82u, 0xAAu}, - {0x85u, 0x0Du}, - {0x86u, 0xFFu}, - {0x89u, 0x11u}, - {0x8Au, 0xFFu}, - {0x8Bu, 0x22u}, - {0x8Du, 0x0Du}, - {0x8Eu, 0xFFu}, - {0x90u, 0xFFu}, - {0x95u, 0x22u}, - {0x97u, 0x18u}, - {0x99u, 0x60u}, - {0x9Cu, 0x69u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x96u}, - {0x9Fu, 0x0Du}, - {0xA1u, 0x0Du}, - {0xA4u, 0x33u}, - {0xA5u, 0x0Du}, - {0xA6u, 0xCCu}, - {0xAAu, 0xFFu}, - {0xACu, 0x0Fu}, - {0xADu, 0x12u}, - {0xAEu, 0xF0u}, - {0xAFu, 0x44u}, - {0xB0u, 0xFFu}, - {0xB5u, 0x70u}, - {0xB7u, 0x0Fu}, - {0xB8u, 0x80u}, - {0xB9u, 0x20u}, - {0xBAu, 0x02u}, - {0xBBu, 0x80u}, - {0xBEu, 0x40u}, - {0xD6u, 0x08u}, + {0x80u, 0x02u}, + {0x82u, 0x01u}, + {0x83u, 0x80u}, + {0x85u, 0xC0u}, + {0x87u, 0x1Fu}, + {0x8Bu, 0x80u}, + {0x8Cu, 0x02u}, + {0x8Du, 0x03u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x0Cu}, + {0x93u, 0x70u}, + {0x94u, 0x02u}, + {0x96u, 0x01u}, + {0x98u, 0x09u}, + {0x9Au, 0x02u}, + {0x9Du, 0xA0u}, + {0x9Fu, 0x4Fu}, + {0xA1u, 0x05u}, + {0xA3u, 0x0Au}, + {0xA5u, 0x0Fu}, + {0xA8u, 0x02u}, + {0xA9u, 0x90u}, + {0xAAu, 0x05u}, + {0xABu, 0x2Fu}, + {0xADu, 0x06u}, + {0xAFu, 0x09u}, + {0xB0u, 0x08u}, + {0xB1u, 0x7Fu}, + {0xB4u, 0x03u}, + {0xB6u, 0x04u}, + {0xB7u, 0x80u}, + {0xBAu, 0x20u}, + {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, - {0xDDu, 0x90u}, + {0xDCu, 0x19u}, {0xDFu, 0x01u}, - {0x01u, 0x80u}, - {0x02u, 0x80u}, - {0x03u, 0x18u}, - {0x04u, 0x22u}, - {0x05u, 0x04u}, + {0x00u, 0x0Cu}, + {0x05u, 0x40u}, + {0x06u, 0x80u}, {0x08u, 0x80u}, - {0x0Bu, 0x80u}, - {0x0Eu, 0x26u}, - {0x10u, 0x02u}, - {0x12u, 0x18u}, + {0x09u, 0x09u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x28u}, + {0x10u, 0xA0u}, + {0x11u, 0x80u}, + {0x12u, 0x08u}, {0x17u, 0x10u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x02u}, - {0x1Eu, 0x24u}, - {0x1Fu, 0x04u}, - {0x22u, 0x50u}, - {0x24u, 0x01u}, - {0x25u, 0x10u}, + {0x18u, 0x14u}, + {0x1Au, 0x80u}, + {0x1Du, 0x40u}, + {0x1Eu, 0x08u}, + {0x1Fu, 0x22u}, + {0x21u, 0x40u}, + {0x24u, 0x41u}, {0x26u, 0x02u}, - {0x28u, 0x41u}, + {0x28u, 0x80u}, + {0x2Au, 0x20u}, {0x2Bu, 0x20u}, - {0x2Cu, 0x22u}, - {0x2Fu, 0x4Au}, - {0x32u, 0x54u}, + {0x2Cu, 0x09u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x40u}, + {0x30u, 0x08u}, + {0x31u, 0x88u}, + {0x34u, 0x80u}, {0x36u, 0x02u}, - {0x37u, 0x10u}, - {0x39u, 0x65u}, - {0x3Cu, 0x04u}, - {0x3Du, 0x80u}, - {0x58u, 0x04u}, - {0x59u, 0x12u}, - {0x5Bu, 0x40u}, - {0x60u, 0x04u}, - {0x61u, 0x01u}, - {0x62u, 0x50u}, - {0x63u, 0x10u}, - {0x80u, 0x80u}, - {0x81u, 0x02u}, - {0x83u, 0x50u}, - {0x85u, 0x60u}, - {0x86u, 0x04u}, - {0x8Bu, 0x01u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x10u}, - {0x91u, 0x10u}, - {0x96u, 0x40u}, - {0x97u, 0x1Cu}, - {0x98u, 0x04u}, - {0x99u, 0xD0u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x19u}, - {0xA2u, 0x8Cu}, - {0xA4u, 0x80u}, - {0xA5u, 0x1Cu}, - {0xA6u, 0x01u}, - {0xA7u, 0x01u}, - {0xA9u, 0x40u}, - {0xABu, 0x40u}, - {0xACu, 0x20u}, - {0xB1u, 0x20u}, - {0xB7u, 0x02u}, - {0xC0u, 0x7Fu}, - {0xC2u, 0xE9u}, - {0xC4u, 0x47u}, - {0xCAu, 0xEBu}, - {0xCCu, 0xAEu}, - {0xCEu, 0x5Fu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x81u}, - {0xE2u, 0x40u}, - {0xE4u, 0x20u}, - {0xE6u, 0x15u}, - {0xEAu, 0x20u}, - {0xEEu, 0x01u}, - {0x03u, 0xFFu}, + {0x39u, 0x80u}, + {0x3Bu, 0x96u}, + {0x3Cu, 0x80u}, + {0x3Eu, 0x22u}, + {0x3Fu, 0x04u}, + {0x58u, 0x50u}, + {0x62u, 0x90u}, + {0x6Du, 0x1Cu}, + {0x6Eu, 0x40u}, + {0x82u, 0x40u}, + {0x88u, 0x50u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x01u}, + {0xC0u, 0x94u}, + {0xC2u, 0x6Fu}, + {0xC4u, 0x4Fu}, + {0xCAu, 0xF7u}, + {0xCCu, 0x9Au}, + {0xCEu, 0xFFu}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x0Cu}, + {0xE4u, 0x01u}, + {0xE6u, 0x90u}, + {0x00u, 0x05u}, + {0x02u, 0x0Au}, + {0x05u, 0x05u}, {0x06u, 0xFFu}, - {0x0Au, 0xFFu}, - {0x0Du, 0x0Fu}, - {0x0Eu, 0xFFu}, - {0x0Fu, 0xF0u}, - {0x11u, 0xFFu}, - {0x16u, 0xFFu}, - {0x17u, 0xFFu}, - {0x18u, 0x0Fu}, - {0x1Au, 0xF0u}, - {0x1Bu, 0xFFu}, - {0x20u, 0x33u}, - {0x21u, 0x96u}, - {0x22u, 0xCCu}, - {0x23u, 0x69u}, - {0x24u, 0x55u}, - {0x26u, 0xAAu}, + {0x07u, 0x0Au}, + {0x08u, 0xFFu}, + {0x0Bu, 0xFFu}, + {0x0Cu, 0x50u}, + {0x0Du, 0x50u}, + {0x0Eu, 0xA0u}, + {0x0Fu, 0xA0u}, + {0x10u, 0x0Fu}, + {0x11u, 0x0Fu}, + {0x12u, 0xF0u}, + {0x13u, 0xF0u}, + {0x14u, 0x06u}, + {0x15u, 0x09u}, + {0x16u, 0x09u}, + {0x17u, 0x06u}, + {0x19u, 0x90u}, + {0x1Bu, 0x60u}, + {0x1Cu, 0x03u}, + {0x1Du, 0x03u}, + {0x1Eu, 0x0Cu}, + {0x1Fu, 0x0Cu}, + {0x22u, 0xFFu}, + {0x23u, 0xFFu}, + {0x24u, 0x60u}, + {0x26u, 0x90u}, {0x27u, 0xFFu}, - {0x28u, 0x69u}, - {0x29u, 0x55u}, - {0x2Au, 0x96u}, - {0x2Bu, 0xAAu}, - {0x2Cu, 0xFFu}, - {0x2Du, 0x33u}, - {0x2Fu, 0xCCu}, + {0x28u, 0x30u}, + {0x29u, 0x30u}, + {0x2Au, 0xC0u}, + {0x2Bu, 0xC0u}, {0x34u, 0xFFu}, {0x37u, 0xFFu}, - {0x3Au, 0x20u}, - {0x3Bu, 0x80u}, - {0x56u, 0x08u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x83u, 0x02u}, - {0x87u, 0x80u}, - {0x89u, 0x30u}, - {0x8Bu, 0x01u}, - {0x8Du, 0x30u}, - {0x8Eu, 0x03u}, - {0x90u, 0x03u}, - {0x91u, 0x06u}, - {0x92u, 0x0Cu}, - {0x93u, 0x08u}, - {0x94u, 0x05u}, - {0x95u, 0x10u}, - {0x96u, 0x0Au}, - {0x97u, 0x22u}, - {0x99u, 0x02u}, - {0x9Au, 0x02u}, - {0x9Bu, 0x0Cu}, - {0x9Cu, 0x06u}, - {0x9Du, 0x04u}, - {0x9Eu, 0x09u}, - {0x9Fu, 0x0Au}, - {0xA0u, 0x01u}, - {0xA1u, 0x04u}, - {0xA3u, 0x0Au}, - {0xA5u, 0x20u}, - {0xA7u, 0x10u}, - {0xA8u, 0x07u}, - {0xAAu, 0x08u}, - {0xABu, 0x40u}, - {0xADu, 0x40u}, - {0xAFu, 0x80u}, - {0xB0u, 0x0Fu}, - {0xB1u, 0x01u}, - {0xB3u, 0x30u}, - {0xB5u, 0x0Eu}, - {0xB7u, 0xC0u}, - {0xBAu, 0x02u}, - {0xBBu, 0x28u}, + {0x83u, 0x01u}, + {0x85u, 0x02u}, + {0x8Du, 0x02u}, + {0x93u, 0x02u}, + {0x95u, 0x02u}, + {0xA1u, 0x02u}, + {0xB5u, 0x01u}, + {0xB7u, 0x02u}, {0xBFu, 0x40u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, + {0xC0u, 0x16u}, + {0xC1u, 0x02u}, + {0xC2u, 0x40u}, + {0xC4u, 0x05u}, + {0xC5u, 0xCEu}, + {0xC6u, 0xFBu}, + {0xC7u, 0xDBu}, + {0xC8u, 0x3Fu}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x22u}, + {0xCEu, 0xF0u}, + {0xCFu, 0x08u}, + {0xD0u, 0x04u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD9u, 0x04u}, + {0xDAu, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x90u}, + {0xDCu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x80u}, - {0x02u, 0x08u}, - {0x03u, 0x10u}, - {0x05u, 0x80u}, - {0x09u, 0x08u}, - {0x0Au, 0x04u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x82u}, - {0x0Fu, 0x24u}, - {0x10u, 0x01u}, - {0x12u, 0x40u}, - {0x13u, 0x18u}, - {0x17u, 0x11u}, + {0xE2u, 0xC0u}, + {0xE4u, 0x40u}, + {0xE5u, 0x01u}, + {0xE6u, 0x10u}, + {0xE7u, 0x11u}, + {0xE8u, 0xC0u}, + {0xE9u, 0x01u}, + {0xEBu, 0x11u}, + {0xECu, 0x40u}, + {0xEDu, 0x01u}, + {0xEEu, 0x40u}, + {0xEFu, 0x01u}, + {0x00u, 0x52u}, + {0x03u, 0x20u}, + {0x09u, 0x8Au}, + {0x10u, 0x64u}, {0x19u, 0x20u}, - {0x1Au, 0x04u}, - {0x1Eu, 0x80u}, - {0x21u, 0x40u}, - {0x24u, 0x48u}, - {0x26u, 0x2Cu}, + {0x22u, 0x80u}, + {0x25u, 0x10u}, {0x27u, 0x02u}, - {0x28u, 0x08u}, - {0x29u, 0x01u}, - {0x2Bu, 0x11u}, - {0x2Cu, 0xA0u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x04u}, - {0x30u, 0x01u}, - {0x32u, 0x08u}, - {0x33u, 0x10u}, - {0x34u, 0x01u}, - {0x36u, 0x29u}, - {0x37u, 0x80u}, - {0x39u, 0x80u}, - {0x3Bu, 0x01u}, - {0x3Cu, 0x40u}, - {0x3Du, 0x28u}, - {0x3Fu, 0x01u}, - {0x4Cu, 0x04u}, - {0x4Du, 0x10u}, - {0x5Bu, 0x40u}, - {0x5Du, 0x40u}, - {0x61u, 0x40u}, - {0x62u, 0x80u}, - {0x65u, 0x80u}, - {0x67u, 0x01u}, - {0x81u, 0x40u}, - {0x86u, 0x40u}, - {0x88u, 0x04u}, - {0x89u, 0x08u}, - {0x8Bu, 0x80u}, - {0x8Du, 0x10u}, - {0xC0u, 0x87u}, - {0xC2u, 0xF6u}, - {0xC4u, 0x5Fu}, - {0xCAu, 0xFFu}, - {0xCCu, 0xF7u}, - {0xCEu, 0xF9u}, - {0xD6u, 0x18u}, - {0xD8u, 0x18u}, - {0xE2u, 0x10u}, - {0x86u, 0x04u}, - {0x8Au, 0x10u}, - {0x96u, 0x04u}, - {0x9Eu, 0x10u}, - {0xA8u, 0xC0u}, - {0xB3u, 0x30u}, - {0xB6u, 0x44u}, - {0xE2u, 0x06u}, - {0xE6u, 0x01u}, - {0xE8u, 0x01u}, - {0xEEu, 0x01u}, - {0x80u, 0x40u}, + {0x28u, 0x54u}, + {0x2Bu, 0x20u}, + {0x2Eu, 0x02u}, + {0x30u, 0x20u}, + {0x31u, 0x8Au}, + {0x37u, 0x05u}, + {0x38u, 0x50u}, + {0x3Au, 0x60u}, + {0x3Bu, 0x18u}, + {0x3Cu, 0x80u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x02u}, + {0x47u, 0x92u}, + {0x4Du, 0x06u}, + {0x4Eu, 0x08u}, + {0x4Fu, 0x80u}, + {0x55u, 0x40u}, + {0x56u, 0x18u}, + {0x57u, 0x0Au}, + {0x58u, 0xA9u}, + {0x5Du, 0x14u}, + {0x5Eu, 0x80u}, + {0x5Fu, 0x02u}, + {0x63u, 0x01u}, + {0x66u, 0x01u}, + {0x67u, 0x02u}, + {0x82u, 0x10u}, + {0x83u, 0x40u}, {0x84u, 0x01u}, - {0x90u, 0x80u}, - {0x94u, 0x40u}, - {0x96u, 0x44u}, - {0x97u, 0x10u}, - {0x9Cu, 0x81u}, - {0x9Eu, 0x10u}, - {0xA6u, 0x04u}, - {0xA7u, 0x20u}, - {0xA8u, 0x04u}, + {0x85u, 0x02u}, + {0x86u, 0x20u}, + {0x87u, 0x04u}, + {0x89u, 0x9Au}, + {0x8Au, 0x40u}, + {0x8Cu, 0x20u}, + {0x92u, 0x04u}, + {0x93u, 0x13u}, + {0x96u, 0x20u}, + {0x98u, 0xFDu}, + {0x9Au, 0x42u}, + {0x9Bu, 0x95u}, + {0x9Du, 0x22u}, + {0x9Eu, 0x19u}, + {0xA0u, 0x60u}, + {0xA1u, 0x88u}, + {0xA2u, 0x48u}, + {0xA3u, 0x01u}, + {0xA5u, 0x52u}, + {0xA6u, 0x80u}, + {0xA7u, 0x0Au}, + {0xAFu, 0x01u}, + {0xB0u, 0x01u}, + {0xB1u, 0x10u}, + {0xB2u, 0x09u}, + {0xB4u, 0x80u}, + {0xB5u, 0x04u}, + {0xB7u, 0x01u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x0Du}, + {0xC4u, 0x0Eu}, + {0xCAu, 0x87u}, + {0xCCu, 0xCFu}, + {0xCEu, 0xDEu}, + {0xD0u, 0xB0u}, + {0xD2u, 0x30u}, + {0xD6u, 0xFFu}, + {0xD8u, 0x98u}, + {0xE0u, 0x08u}, {0xE2u, 0x02u}, - {0xE6u, 0x04u}, - {0xEAu, 0x06u}, - {0xEEu, 0x08u}, - {0x01u, 0xFFu}, - {0x05u, 0x30u}, + {0xE6u, 0x0Cu}, + {0xE8u, 0x02u}, + {0xEAu, 0x20u}, + {0xEEu, 0x01u}, + {0x01u, 0x6Cu}, + {0x02u, 0x60u}, + {0x04u, 0x7Fu}, + {0x05u, 0x24u}, {0x06u, 0x80u}, - {0x07u, 0xC0u}, - {0x09u, 0x50u}, - {0x0Bu, 0xA0u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0xFFu}, - {0x11u, 0x05u}, - {0x13u, 0x0Au}, - {0x14u, 0x99u}, - {0x16u, 0x22u}, - {0x19u, 0x03u}, - {0x1Au, 0x07u}, - {0x1Bu, 0x0Cu}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0x70u}, - {0x1Fu, 0xF0u}, - {0x20u, 0xAAu}, - {0x22u, 0x55u}, - {0x25u, 0x06u}, - {0x27u, 0x09u}, - {0x28u, 0x44u}, - {0x2Au, 0x88u}, - {0x2Bu, 0xFFu}, - {0x2Du, 0x60u}, - {0x2Fu, 0x90u}, - {0x33u, 0xFFu}, - {0x34u, 0x0Fu}, - {0x36u, 0xF0u}, + {0x09u, 0x08u}, + {0x0Au, 0x9Fu}, + {0x0Bu, 0x64u}, + {0x0Cu, 0x90u}, + {0x0Du, 0x64u}, + {0x0Eu, 0x40u}, + {0x0Fu, 0x08u}, + {0x11u, 0x93u}, + {0x13u, 0x60u}, + {0x14u, 0x1Fu}, + {0x15u, 0x10u}, + {0x16u, 0x20u}, + {0x17u, 0xE5u}, + {0x18u, 0x80u}, + {0x19u, 0x77u}, + {0x1Bu, 0x80u}, + {0x1Du, 0x6Cu}, + {0x1Eu, 0xFFu}, + {0x20u, 0xC0u}, + {0x21u, 0x40u}, + {0x22u, 0x02u}, + {0x23u, 0x02u}, + {0x24u, 0xC0u}, + {0x25u, 0x2Cu}, + {0x26u, 0x04u}, + {0x27u, 0x40u}, + {0x28u, 0xC0u}, + {0x2Au, 0x08u}, + {0x2Cu, 0xC0u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x08u}, + {0x31u, 0xF0u}, + {0x33u, 0x07u}, + {0x34u, 0xFFu}, + {0x35u, 0x08u}, + {0x37u, 0x80u}, + {0x39u, 0x02u}, + {0x3Bu, 0x0Cu}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x50u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x84u, 0x21u}, + {0x86u, 0xC2u}, + {0x89u, 0x60u}, + {0x8Bu, 0x90u}, + {0x8Du, 0x30u}, + {0x8Fu, 0xC0u}, + {0x90u, 0x80u}, + {0x91u, 0x0Fu}, + {0x92u, 0x60u}, + {0x93u, 0xF0u}, + {0x96u, 0x01u}, + {0x99u, 0x05u}, + {0x9Au, 0x0Cu}, + {0x9Bu, 0x0Au}, + {0x9Eu, 0x12u}, + {0xA1u, 0x06u}, + {0xA3u, 0x09u}, + {0xA5u, 0x50u}, + {0xA7u, 0xA0u}, + {0xA8u, 0xA8u}, + {0xA9u, 0x03u}, + {0xAAu, 0x43u}, + {0xABu, 0x0Cu}, + {0xACu, 0x64u}, + {0xAEu, 0x83u}, + {0xB0u, 0xE0u}, + {0xB2u, 0x10u}, + {0xB3u, 0xFFu}, + {0xB4u, 0x0Fu}, + {0xB8u, 0x80u}, + {0xBAu, 0x02u}, + {0xBEu, 0x40u}, + {0xBFu, 0x04u}, + {0xD6u, 0x02u}, + {0xD7u, 0x2Cu}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x03u, 0x10u}, + {0x05u, 0x01u}, + {0x06u, 0x08u}, + {0x07u, 0x21u}, + {0x09u, 0x40u}, + {0x0Au, 0x98u}, + {0x0Eu, 0x2Au}, + {0x12u, 0x08u}, + {0x13u, 0x80u}, + {0x15u, 0x1Au}, + {0x16u, 0x02u}, + {0x18u, 0x44u}, + {0x1Au, 0x9Au}, + {0x1Du, 0x10u}, + {0x23u, 0x10u}, + {0x24u, 0x08u}, + {0x25u, 0x04u}, + {0x26u, 0x49u}, + {0x27u, 0xA0u}, + {0x29u, 0x04u}, + {0x2Au, 0x20u}, + {0x2Bu, 0x40u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x84u}, + {0x2Fu, 0x02u}, + {0x31u, 0x02u}, + {0x32u, 0x10u}, + {0x35u, 0x40u}, + {0x36u, 0x19u}, + {0x37u, 0x10u}, + {0x38u, 0x88u}, + {0x39u, 0x20u}, + {0x3Au, 0x04u}, + {0x3Cu, 0x08u}, + {0x3Du, 0x50u}, + {0x3Eu, 0x01u}, + {0x60u, 0x40u}, + {0x68u, 0xD8u}, + {0x69u, 0x5Au}, + {0x6Au, 0x05u}, + {0x6Bu, 0x05u}, + {0x71u, 0x40u}, + {0x72u, 0x02u}, + {0x80u, 0x0Cu}, + {0x82u, 0x01u}, + {0x84u, 0x50u}, + {0x88u, 0x10u}, + {0x89u, 0x40u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x01u}, + {0x91u, 0x20u}, + {0x93u, 0x01u}, + {0x95u, 0x4Au}, + {0x96u, 0x01u}, + {0x98u, 0xA4u}, + {0x99u, 0x01u}, + {0x9Au, 0x60u}, + {0x9Du, 0x32u}, + {0x9Eu, 0x96u}, + {0x9Fu, 0x21u}, + {0xA0u, 0x24u}, + {0xA1u, 0x88u}, + {0xA2u, 0x14u}, + {0xA3u, 0x41u}, + {0xA4u, 0x18u}, + {0xA5u, 0x14u}, + {0xA6u, 0x81u}, + {0xA7u, 0x08u}, + {0xAAu, 0x22u}, + {0xB2u, 0x20u}, + {0xB6u, 0x01u}, + {0xC0u, 0xF4u}, + {0xC2u, 0xEFu}, + {0xC4u, 0xF3u}, + {0xCAu, 0xD7u}, + {0xCCu, 0xF5u}, + {0xCEu, 0xFCu}, + {0xD8u, 0x01u}, + {0xE0u, 0x04u}, + {0xE4u, 0x01u}, + {0xE6u, 0x4Eu}, + {0xEAu, 0x01u}, + {0x00u, 0x02u}, + {0x01u, 0x3Fu}, + {0x02u, 0x0Du}, + {0x03u, 0x40u}, + {0x04u, 0x0Du}, + {0x07u, 0x01u}, + {0x08u, 0x82u}, + {0x09u, 0x27u}, + {0x0Au, 0x24u}, + {0x0Bu, 0x50u}, + {0x0Cu, 0x0Du}, + {0x11u, 0x02u}, + {0x12u, 0x70u}, + {0x14u, 0x0Du}, + {0x15u, 0x20u}, + {0x17u, 0x5Cu}, + {0x18u, 0x0Du}, + {0x19u, 0x80u}, + {0x1Cu, 0x91u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x60u}, + {0x20u, 0x70u}, + {0x21u, 0x03u}, + {0x24u, 0xC2u}, + {0x26u, 0x08u}, + {0x27u, 0x1Fu}, + {0x28u, 0x0Du}, + {0x29u, 0x18u}, + {0x2Bu, 0x03u}, + {0x30u, 0x0Fu}, + {0x31u, 0x0Fu}, + {0x32u, 0x70u}, + {0x33u, 0x80u}, + {0x36u, 0x80u}, + {0x37u, 0x70u}, + {0x3Au, 0x02u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x44u}, {0x3Fu, 0x04u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x36u}, - {0x84u, 0x07u}, - {0x85u, 0x11u}, {0x86u, 0x08u}, - {0x87u, 0x62u}, - {0x88u, 0x32u}, - {0x89u, 0x58u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x23u}, - {0x8Cu, 0x06u}, - {0x8Du, 0x34u}, - {0x8Eu, 0x30u}, - {0x8Fu, 0x43u}, - {0x90u, 0x09u}, - {0x92u, 0x06u}, - {0x94u, 0x01u}, - {0x95u, 0x40u}, - {0x96u, 0x0Eu}, - {0x97u, 0x30u}, - {0x98u, 0x04u}, - {0x9Bu, 0x0Cu}, - {0x9Cu, 0x02u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x36u}, - {0xA3u, 0x82u}, - {0xA8u, 0x30u}, - {0xAAu, 0x06u}, - {0xAEu, 0x20u}, - {0xB0u, 0x0Fu}, - {0xB3u, 0x70u}, - {0xB4u, 0x20u}, - {0xB5u, 0x0Fu}, - {0xB6u, 0x10u}, - {0xB7u, 0x80u}, - {0xB8u, 0x02u}, - {0xBBu, 0x08u}, - {0xBEu, 0x50u}, + {0x87u, 0x20u}, + {0x8Du, 0x04u}, + {0x8Fu, 0x88u}, + {0x90u, 0x04u}, + {0x96u, 0x01u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x04u}, + {0xA1u, 0x02u}, + {0xA3u, 0x01u}, + {0xA5u, 0x01u}, + {0xA7u, 0x42u}, + {0xABu, 0x10u}, + {0xADu, 0x53u}, + {0xAEu, 0x02u}, + {0xAFu, 0xACu}, + {0xB0u, 0x04u}, + {0xB1u, 0x30u}, + {0xB2u, 0x08u}, + {0xB3u, 0xC0u}, + {0xB4u, 0x03u}, + {0xB7u, 0x0Fu}, + {0xBEu, 0x11u}, + {0xBFu, 0x45u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x09u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, {0x00u, 0x24u}, - {0x01u, 0x41u}, - {0x04u, 0x08u}, - {0x06u, 0x02u}, - {0x0Au, 0x82u}, - {0x0Bu, 0x18u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x0Au}, - {0x10u, 0x08u}, - {0x12u, 0x01u}, - {0x13u, 0x02u}, + {0x02u, 0x04u}, + {0x05u, 0x09u}, + {0x06u, 0x09u}, + {0x08u, 0x02u}, + {0x09u, 0x40u}, + {0x0Bu, 0x10u}, + {0x0Cu, 0x04u}, + {0x0Fu, 0x86u}, + {0x10u, 0x02u}, + {0x12u, 0x02u}, {0x14u, 0x40u}, - {0x17u, 0x10u}, - {0x18u, 0x40u}, - {0x19u, 0x40u}, - {0x1Au, 0x81u}, - {0x1Bu, 0x10u}, - {0x1Eu, 0x0Au}, - {0x1Fu, 0x10u}, - {0x22u, 0x98u}, - {0x24u, 0x20u}, - {0x29u, 0x01u}, - {0x2Eu, 0x14u}, - {0x2Fu, 0x02u}, - {0x32u, 0x98u}, - {0x36u, 0x11u}, - {0x37u, 0x40u}, - {0x38u, 0x44u}, - {0x3Bu, 0x10u}, - {0x3Cu, 0x02u}, - {0x3Du, 0x08u}, - {0x3Eu, 0xA0u}, - {0x58u, 0x16u}, - {0x59u, 0x80u}, - {0x60u, 0xA8u}, - {0x63u, 0x02u}, - {0x69u, 0x80u}, - {0x6Au, 0x40u}, - {0x81u, 0x80u}, - {0x82u, 0x10u}, - {0x87u, 0x01u}, - {0x90u, 0x0Cu}, - {0x91u, 0x61u}, - {0x92u, 0x06u}, - {0x93u, 0x9Eu}, - {0x94u, 0x60u}, - {0x96u, 0xC0u}, - {0x98u, 0x52u}, - {0x99u, 0x21u}, - {0x9Au, 0x93u}, - {0x9Bu, 0x12u}, - {0x9Cu, 0xA8u}, - {0x9Du, 0x40u}, - {0xA0u, 0x98u}, - {0xA1u, 0x08u}, - {0xA2u, 0x10u}, - {0xA5u, 0x04u}, - {0xA6u, 0x0Au}, - {0xA7u, 0x01u}, - {0xA8u, 0x10u}, - {0xC0u, 0xAFu}, - {0xC2u, 0xEFu}, - {0xC4u, 0x5Bu}, - {0xCAu, 0x71u}, - {0xCCu, 0xBEu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE2u, 0x04u}, - {0xEAu, 0x02u}, - {0xEEu, 0x08u}, - {0x02u, 0x07u}, - {0x04u, 0x04u}, - {0x06u, 0x08u}, - {0x09u, 0x01u}, - {0x0Bu, 0x12u}, - {0x0Du, 0x08u}, - {0x0Fu, 0x84u}, - {0x10u, 0x0Au}, - {0x12u, 0x05u}, + {0x15u, 0x10u}, + {0x17u, 0x08u}, + {0x19u, 0x10u}, + {0x1Au, 0x60u}, + {0x1Du, 0x01u}, + {0x1Fu, 0x88u}, + {0x20u, 0x82u}, + {0x22u, 0x88u}, + {0x24u, 0x02u}, + {0x25u, 0x0Bu}, + {0x26u, 0x40u}, + {0x28u, 0x80u}, + {0x29u, 0x20u}, + {0x2Bu, 0x12u}, + {0x2Eu, 0x22u}, + {0x2Fu, 0x20u}, + {0x30u, 0x80u}, + {0x31u, 0x0Cu}, + {0x34u, 0x18u}, + {0x35u, 0x02u}, + {0x36u, 0x60u}, + {0x37u, 0x01u}, + {0x38u, 0x80u}, + {0x3Au, 0x04u}, + {0x3Du, 0x0Au}, + {0x3Eu, 0x10u}, + {0x5Au, 0x80u}, + {0x5Du, 0x40u}, + {0x62u, 0x40u}, + {0x66u, 0x80u}, + {0x7Du, 0x08u}, + {0x7Fu, 0x10u}, + {0x82u, 0x0Au}, + {0x83u, 0x40u}, + {0x84u, 0x41u}, + {0x87u, 0x10u}, + {0x88u, 0x04u}, + {0x89u, 0x10u}, + {0x8Eu, 0x0Au}, + {0x90u, 0xCCu}, + {0x91u, 0x40u}, + {0x92u, 0x90u}, + {0x93u, 0x10u}, + {0x94u, 0x02u}, + {0x96u, 0x60u}, + {0x98u, 0x48u}, + {0x99u, 0x02u}, + {0x9Au, 0x32u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x12u}, + {0x9Du, 0x44u}, + {0x9Eu, 0xC8u}, + {0x9Fu, 0x20u}, + {0xA0u, 0x96u}, + {0xA1u, 0x24u}, + {0xA3u, 0x31u}, + {0xA5u, 0x42u}, + {0xA9u, 0x02u}, + {0xAAu, 0x40u}, + {0xB3u, 0x10u}, + {0xB7u, 0x10u}, + {0xC0u, 0xF4u}, + {0xC2u, 0xFDu}, + {0xC4u, 0x71u}, + {0xCAu, 0xEFu}, + {0xCCu, 0xF8u}, + {0xCEu, 0xEAu}, + {0xD6u, 0x18u}, + {0xD8u, 0x18u}, + {0xE0u, 0x82u}, + {0xE4u, 0x80u}, + {0xE6u, 0x10u}, + {0xEEu, 0xC1u}, + {0x02u, 0x17u}, + {0x03u, 0x17u}, + {0x07u, 0x20u}, + {0x0Au, 0x08u}, + {0x0Cu, 0x10u}, + {0x0Eu, 0x20u}, + {0x11u, 0x50u}, + {0x12u, 0x20u}, + {0x13u, 0xA0u}, {0x14u, 0x09u}, + {0x15u, 0x09u}, {0x16u, 0x02u}, - {0x1Du, 0x53u}, - {0x1Fu, 0xACu}, - {0x21u, 0x02u}, - {0x22u, 0x08u}, - {0x23u, 0x41u}, - {0x2Du, 0x04u}, - {0x2Fu, 0x28u}, + {0x17u, 0x02u}, + {0x18u, 0x04u}, + {0x19u, 0x04u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x08u}, + {0x20u, 0x0Au}, + {0x21u, 0x0Au}, + {0x22u, 0x05u}, + {0x23u, 0x05u}, + {0x27u, 0x40u}, + {0x2Bu, 0x08u}, + {0x2Fu, 0x80u}, {0x30u, 0x0Fu}, - {0x31u, 0xC0u}, - {0x33u, 0x30u}, - {0x37u, 0x0Fu}, - {0x3Fu, 0x45u}, - {0x54u, 0x40u}, - {0x56u, 0x04u}, + {0x31u, 0x0Fu}, + {0x32u, 0x30u}, + {0x33u, 0xC0u}, + {0x35u, 0x30u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x14u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0xFFu}, - {0x82u, 0x10u}, - {0x85u, 0x30u}, - {0x86u, 0x01u}, - {0x87u, 0xC0u}, - {0x8Cu, 0x80u}, - {0x8Du, 0x90u}, - {0x8Eu, 0x05u}, - {0x8Fu, 0x60u}, + {0x80u, 0x90u}, + {0x82u, 0x60u}, + {0x83u, 0xFFu}, + {0x84u, 0x03u}, + {0x86u, 0x0Cu}, + {0x87u, 0xFFu}, + {0x89u, 0x30u}, + {0x8Au, 0xFFu}, + {0x8Bu, 0xC0u}, + {0x8Cu, 0x0Fu}, + {0x8Du, 0x0Fu}, + {0x8Eu, 0xF0u}, + {0x8Fu, 0xF0u}, + {0x90u, 0xFFu}, {0x91u, 0x05u}, {0x93u, 0x0Au}, - {0x94u, 0x06u}, + {0x94u, 0x30u}, {0x95u, 0x50u}, - {0x96u, 0x80u}, + {0x96u, 0xC0u}, {0x97u, 0xA0u}, - {0x99u, 0x03u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x0Cu}, - {0x9Du, 0x0Fu}, - {0x9Eu, 0x20u}, - {0x9Fu, 0xF0u}, - {0xA5u, 0x09u}, - {0xA6u, 0x40u}, - {0xA7u, 0x06u}, - {0xA9u, 0xFFu}, - {0xAAu, 0x83u}, - {0xACu, 0x28u}, - {0xAEu, 0x50u}, - {0xAFu, 0xFFu}, - {0xB0u, 0x80u}, - {0xB2u, 0x07u}, - {0xB4u, 0x60u}, - {0xB6u, 0x18u}, - {0xB7u, 0xFFu}, - {0xBEu, 0x51u}, - {0xBFu, 0x40u}, - {0xD4u, 0x09u}, - {0xD6u, 0x04u}, + {0x98u, 0x09u}, + {0x9Au, 0x06u}, + {0x9Du, 0xFFu}, + {0xA0u, 0x05u}, + {0xA2u, 0x0Au}, + {0xA4u, 0x50u}, + {0xA5u, 0x06u}, + {0xA6u, 0xA0u}, + {0xA7u, 0x09u}, + {0xA9u, 0x03u}, + {0xABu, 0x0Cu}, + {0xACu, 0xFFu}, + {0xADu, 0x60u}, + {0xAFu, 0x90u}, + {0xB3u, 0xFFu}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, + {0xBFu, 0x04u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, {0x01u, 0x02u}, - {0x03u, 0x10u}, - {0x04u, 0x42u}, - {0x05u, 0x04u}, - {0x09u, 0x08u}, + {0x02u, 0x40u}, + {0x03u, 0x05u}, + {0x06u, 0xA8u}, + {0x07u, 0x01u}, + {0x08u, 0x04u}, + {0x09u, 0x20u}, + {0x0Au, 0x10u}, {0x0Bu, 0x80u}, - {0x0Eu, 0x06u}, - {0x0Fu, 0x10u}, - {0x10u, 0x80u}, - {0x15u, 0xA0u}, - {0x16u, 0x20u}, - {0x17u, 0x44u}, + {0x0Eu, 0x84u}, + {0x0Fu, 0x20u}, + {0x10u, 0x40u}, + {0x11u, 0x02u}, + {0x16u, 0x42u}, + {0x17u, 0x08u}, + {0x18u, 0x20u}, {0x19u, 0x02u}, - {0x1Cu, 0x01u}, - {0x1Du, 0x04u}, - {0x1Eu, 0x48u}, - {0x20u, 0x82u}, - {0x22u, 0x04u}, - {0x27u, 0x01u}, - {0x29u, 0x42u}, - {0x2Eu, 0x94u}, - {0x33u, 0x40u}, - {0x36u, 0x11u}, - {0x37u, 0x44u}, - {0x38u, 0x80u}, - {0x3Bu, 0x20u}, - {0x3Cu, 0x02u}, - {0x3Du, 0x88u}, - {0x44u, 0x02u}, - {0x46u, 0x01u}, - {0x5Du, 0x20u}, - {0x5Eu, 0x41u}, - {0x5Fu, 0x04u}, + {0x1Du, 0x40u}, + {0x20u, 0x10u}, + {0x21u, 0x01u}, + {0x22u, 0x10u}, + {0x27u, 0x20u}, + {0x28u, 0x40u}, + {0x2Au, 0x90u}, + {0x2Bu, 0x20u}, + {0x2Du, 0x20u}, + {0x2Eu, 0xA4u}, + {0x2Fu, 0x20u}, + {0x30u, 0x04u}, + {0x31u, 0x20u}, + {0x33u, 0x01u}, + {0x35u, 0x02u}, + {0x36u, 0xC0u}, + {0x37u, 0x08u}, + {0x38u, 0x08u}, + {0x39u, 0x02u}, + {0x3Bu, 0x02u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x89u}, + {0x3Eu, 0x0Au}, + {0x3Fu, 0x20u}, + {0x58u, 0x10u}, + {0x5Au, 0x40u}, + {0x5Cu, 0x40u}, {0x60u, 0x02u}, - {0x62u, 0x12u}, - {0x63u, 0x20u}, - {0x65u, 0x01u}, - {0x67u, 0x02u}, - {0x6Cu, 0x41u}, - {0x6Du, 0x88u}, - {0x6Fu, 0x06u}, - {0x74u, 0x08u}, - {0x75u, 0x40u}, - {0x77u, 0x88u}, - {0x80u, 0x01u}, - {0x81u, 0x05u}, - {0x82u, 0x04u}, - {0x86u, 0x04u}, - {0x87u, 0x80u}, - {0x88u, 0x08u}, - {0x90u, 0x40u}, - {0x91u, 0xA0u}, - {0x92u, 0x15u}, - {0x93u, 0xB6u}, - {0x94u, 0x02u}, - {0x99u, 0x20u}, - {0x9Au, 0x91u}, - {0x9Bu, 0x10u}, - {0x9Eu, 0x20u}, - {0x9Fu, 0x49u}, - {0xA0u, 0x80u}, - {0xA1u, 0x08u}, - {0xA2u, 0x11u}, - {0xA3u, 0x10u}, - {0xA4u, 0x41u}, - {0xA5u, 0x04u}, - {0xA6u, 0x02u}, + {0x62u, 0x20u}, + {0x6Du, 0x80u}, + {0x6Fu, 0x03u}, + {0x80u, 0x10u}, + {0x82u, 0x40u}, + {0x83u, 0x01u}, + {0x84u, 0x10u}, + {0x85u, 0x43u}, + {0x89u, 0x20u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x48u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x90u}, + {0x90u, 0x48u}, + {0x92u, 0x10u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x60u}, + {0x9Fu, 0x20u}, + {0xA0u, 0x10u}, + {0xA1u, 0x25u}, + {0xA2u, 0x80u}, + {0xA5u, 0x40u}, + {0xA6u, 0x20u}, {0xA7u, 0x02u}, - {0xAAu, 0x11u}, - {0xACu, 0x04u}, - {0xB0u, 0x41u}, - {0xB2u, 0x20u}, - {0xB4u, 0x01u}, - {0xB7u, 0x08u}, - {0xC0u, 0xBCu}, - {0xC2u, 0xECu}, - {0xC4u, 0xE8u}, - {0xCAu, 0x79u}, - {0xCCu, 0xF8u}, - {0xCEu, 0xDCu}, - {0xD6u, 0xF0u}, - {0xD8u, 0x9Fu}, - {0xE0u, 0x01u}, - {0xE4u, 0x0Cu}, - {0xE6u, 0x20u}, - {0xEAu, 0xC8u}, - {0xEEu, 0xC0u}, + {0xA9u, 0x10u}, + {0xABu, 0x08u}, + {0xAFu, 0x04u}, + {0xB0u, 0x84u}, + {0xB1u, 0x08u}, + {0xB3u, 0x09u}, + {0xB4u, 0x04u}, + {0xB6u, 0x01u}, + {0xB7u, 0x80u}, + {0xC0u, 0xFBu}, + {0xC2u, 0x7Eu}, + {0xC4u, 0xB8u}, + {0xCAu, 0x7Fu}, + {0xCCu, 0xD7u}, + {0xCEu, 0xF3u}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x0Cu}, + {0xE0u, 0x20u}, + {0xE2u, 0x04u}, + {0xE4u, 0xB1u}, + {0xE6u, 0x02u}, + {0xE8u, 0x80u}, + {0xEAu, 0x50u}, + {0xECu, 0xC4u}, + {0xEEu, 0x20u}, + {0x04u, 0x80u}, {0x0Fu, 0x08u}, - {0x12u, 0x08u}, - {0x15u, 0x80u}, - {0x17u, 0x04u}, - {0x33u, 0x04u}, - {0x36u, 0x88u}, - {0x39u, 0x81u}, - {0x3Cu, 0x01u}, + {0x13u, 0x10u}, + {0x17u, 0x48u}, + {0x33u, 0x02u}, + {0x36u, 0x80u}, + {0x37u, 0x08u}, + {0x39u, 0x04u}, + {0x3Bu, 0x10u}, {0x3Du, 0x20u}, + {0x3Eu, 0x08u}, {0x40u, 0x04u}, - {0x62u, 0x02u}, - {0x83u, 0x04u}, - {0x86u, 0x08u}, - {0x8Au, 0x02u}, + {0x62u, 0x08u}, + {0x8Bu, 0x02u}, + {0xC0u, 0x80u}, {0xC2u, 0x80u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, {0xD8u, 0x40u}, - {0xE4u, 0x20u}, - {0xE6u, 0x40u}, - {0x33u, 0x81u}, + {0x30u, 0x02u}, + {0x33u, 0x40u}, + {0x34u, 0x02u}, {0x35u, 0x80u}, - {0x3Au, 0x10u}, - {0x50u, 0x08u}, - {0x56u, 0x08u}, - {0x63u, 0x20u}, - {0x85u, 0x01u}, - {0x88u, 0x08u}, - {0x8Du, 0x10u}, - {0x8Fu, 0x10u}, - {0x94u, 0x05u}, - {0x95u, 0x01u}, - {0x9Au, 0x08u}, + {0x3Bu, 0x10u}, + {0x50u, 0x10u}, + {0x5Cu, 0x10u}, + {0x63u, 0x02u}, + {0x80u, 0x10u}, + {0x8Cu, 0x50u}, + {0x8Fu, 0x04u}, + {0x90u, 0x80u}, + {0x94u, 0x04u}, + {0x95u, 0x04u}, + {0x9Bu, 0x40u}, + {0x9Eu, 0x08u}, + {0xA3u, 0x05u}, {0xA5u, 0x10u}, {0xA6u, 0x80u}, - {0xCCu, 0x70u}, + {0xAAu, 0x08u}, + {0xAFu, 0x01u}, + {0xCCu, 0xF0u}, {0xCEu, 0x10u}, - {0xD4u, 0x60u}, - {0xD8u, 0x40u}, - {0xE2u, 0x10u}, + {0xD4u, 0x20u}, + {0xD6u, 0x60u}, + {0xE6u, 0x80u}, + {0xEAu, 0x20u}, + {0xEEu, 0x10u}, {0x12u, 0x80u}, - {0x5Bu, 0x08u}, + {0x80u, 0x02u}, + {0x81u, 0x10u}, {0x85u, 0x80u}, - {0x8Au, 0x10u}, - {0x8Cu, 0x01u}, - {0x94u, 0x05u}, + {0x86u, 0x08u}, + {0x89u, 0x04u}, + {0x94u, 0x04u}, + {0x95u, 0x04u}, + {0x97u, 0x10u}, + {0x9Cu, 0x02u}, {0x9Du, 0x80u}, - {0x9Eu, 0x10u}, - {0x9Fu, 0x01u}, - {0xA2u, 0x10u}, + {0x9Eu, 0x08u}, + {0xA4u, 0x02u}, + {0xA5u, 0x10u}, {0xA6u, 0x80u}, - {0xA7u, 0x80u}, - {0xAEu, 0x10u}, {0xC4u, 0x10u}, - {0xD6u, 0x40u}, - {0xE2u, 0x10u}, - {0xEEu, 0x10u}, - {0x8Au, 0x20u}, + {0xE2u, 0xB0u}, + {0xE6u, 0x40u}, {0x94u, 0x04u}, - {0x9Fu, 0x01u}, - {0xA2u, 0x10u}, - {0xA7u, 0x80u}, - {0xB3u, 0x08u}, - {0x01u, 0x20u}, + {0xA8u, 0x02u}, + {0xAFu, 0x10u}, + {0xEAu, 0x10u}, + {0xEEu, 0x80u}, + {0x02u, 0x02u}, + {0x05u, 0x20u}, {0x08u, 0x20u}, - {0x0Eu, 0x01u}, - {0x13u, 0x02u}, - {0x14u, 0x80u}, + {0x0Fu, 0x08u}, + {0x12u, 0x80u}, + {0x17u, 0x08u}, {0x58u, 0x01u}, {0x60u, 0x10u}, - {0x8Au, 0x01u}, - {0x8Cu, 0x20u}, - {0x8Du, 0x20u}, - {0xC0u, 0x02u}, + {0x80u, 0x10u}, + {0x89u, 0x20u}, + {0x8Bu, 0x80u}, + {0xC0u, 0x03u}, {0xC2u, 0x03u}, {0xC4u, 0x0Cu}, {0xD6u, 0x02u}, {0xD8u, 0x02u}, - {0xE2u, 0x0Au}, - {0xE6u, 0x01u}, - {0x04u, 0x04u}, - {0x0Au, 0x20u}, + {0xE2u, 0x05u}, + {0x03u, 0x80u}, + {0x07u, 0x10u}, + {0x08u, 0x02u}, {0x0Du, 0x01u}, - {0x52u, 0x02u}, - {0x56u, 0x80u}, - {0x63u, 0x02u}, - {0x65u, 0x40u}, - {0x82u, 0x98u}, - {0x8Bu, 0x01u}, - {0x9Bu, 0x02u}, + {0x59u, 0x10u}, + {0x5Du, 0x40u}, + {0x5Fu, 0x02u}, + {0x66u, 0x20u}, + {0x8Au, 0x02u}, + {0x98u, 0x20u}, + {0x9Bu, 0x0Au}, {0x9Cu, 0x01u}, - {0xA8u, 0x80u}, - {0xB4u, 0x10u}, - {0xC0u, 0x04u}, + {0xA2u, 0x82u}, + {0xA3u, 0x04u}, + {0xA7u, 0x80u}, + {0xABu, 0x02u}, + {0xC0u, 0x0Cu}, {0xC2u, 0x0Cu}, - {0xD4u, 0x03u}, - {0xD6u, 0x03u}, - {0xE0u, 0x01u}, - {0xE8u, 0x08u}, - {0x54u, 0x10u}, + {0xD4u, 0x01u}, + {0xD6u, 0x05u}, + {0xD8u, 0x01u}, + {0xE6u, 0x04u}, + {0x57u, 0x08u}, + {0x82u, 0x40u}, {0x87u, 0x10u}, - {0x8Au, 0x04u}, - {0x90u, 0x04u}, + {0x8Bu, 0x01u}, + {0x8Fu, 0x08u}, + {0x91u, 0x02u}, + {0x95u, 0x40u}, + {0x98u, 0x22u}, + {0x9Bu, 0x08u}, {0x9Cu, 0x01u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x08u}, - {0xA0u, 0x10u}, - {0xAAu, 0x02u}, - {0xB0u, 0x10u}, - {0xB1u, 0x01u}, - {0xB7u, 0x02u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x20u}, + {0xA2u, 0x80u}, + {0xA3u, 0x04u}, + {0xABu, 0x10u}, {0xD4u, 0x02u}, - {0xE6u, 0x04u}, - {0xEAu, 0x0Cu}, - {0xECu, 0x01u}, - {0x08u, 0x08u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x10u}, - {0x90u, 0x04u}, - {0x96u, 0x04u}, + {0xE6u, 0x06u}, + {0x08u, 0x80u}, + {0x0Bu, 0x10u}, + {0x0Eu, 0x41u}, + {0x91u, 0x02u}, + {0x95u, 0x40u}, + {0x96u, 0x41u}, {0x97u, 0x10u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x08u}, - {0xC2u, 0x0Fu}, - {0x94u, 0x04u}, + {0x98u, 0x02u}, + {0x9Cu, 0x81u}, + {0x9Du, 0x10u}, {0x9Eu, 0x20u}, - {0xA2u, 0x10u}, - {0xAFu, 0x81u}, - {0xEAu, 0x40u}, - {0xEEu, 0x10u}, - {0x06u, 0x20u}, - {0x5Bu, 0x40u}, - {0x5Eu, 0x20u}, - {0x80u, 0x04u}, - {0x83u, 0x40u}, + {0x9Fu, 0x01u}, + {0xA8u, 0x80u}, + {0xABu, 0x04u}, + {0xACu, 0x20u}, + {0xAEu, 0x01u}, + {0xB2u, 0x80u}, + {0xB3u, 0x08u}, + {0xC2u, 0x0Fu}, + {0xE8u, 0x04u}, + {0xEAu, 0x01u}, + {0x66u, 0x08u}, + {0x8Cu, 0x04u}, {0x94u, 0x04u}, - {0x9Eu, 0x20u}, - {0xA2u, 0x10u}, + {0x99u, 0x20u}, + {0xA9u, 0x20u}, + {0xD8u, 0x80u}, + {0xEEu, 0x80u}, + {0x05u, 0x01u}, + {0x57u, 0x08u}, + {0x59u, 0x20u}, + {0x81u, 0x01u}, + {0x99u, 0x20u}, + {0xA3u, 0x08u}, + {0xABu, 0x08u}, + {0xB2u, 0x08u}, {0xC0u, 0x20u}, - {0xD4u, 0x80u}, - {0xD6u, 0x20u}, - {0xE2u, 0x20u}, - {0xE6u, 0x80u}, - {0x80u, 0x04u}, - {0x90u, 0x04u}, + {0xD4u, 0xC0u}, + {0xE0u, 0x20u}, + {0xEEu, 0x80u}, + {0x84u, 0x01u}, + {0x8Eu, 0x20u}, + {0x91u, 0x02u}, + {0x95u, 0x40u}, {0x9Cu, 0x01u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x08u}, - {0xACu, 0x08u}, - {0xAFu, 0x04u}, - {0x00u, 0x20u}, - {0x06u, 0x08u}, - {0x53u, 0x80u}, - {0x56u, 0x80u}, - {0x82u, 0x80u}, - {0x83u, 0x80u}, - {0x85u, 0x40u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x10u}, - {0xACu, 0x10u}, - {0xB0u, 0x01u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x01u}, + {0xA8u, 0x02u}, + {0xE4u, 0x02u}, + {0x03u, 0x01u}, + {0x04u, 0x20u}, + {0x50u, 0x04u}, + {0x5Eu, 0x40u}, + {0x80u, 0x14u}, + {0x85u, 0x01u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x40u}, + {0x91u, 0x02u}, + {0x9Du, 0x10u}, + {0x9Fu, 0x01u}, + {0xA9u, 0x40u}, {0xC0u, 0x03u}, - {0xD4u, 0x06u}, - {0xECu, 0x04u}, + {0xD4u, 0x04u}, + {0xD6u, 0x04u}, + {0xE0u, 0x02u}, + {0xE4u, 0x02u}, {0x10u, 0x03u}, {0x11u, 0x01u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x01u}, {0x1Cu, 0x03u}, {0x1Du, 0x01u}, {0x00u, 0xFDu}, - {0x01u, 0xABu}, - {0x02u, 0x08u}, + {0x01u, 0xAFu}, + {0x02u, 0x0Au}, {0x10u, 0x55u}, }; @@ -1842,32 +2081,19 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2176u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P4_ROUTE_BASE), 1792u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_0_2_0_CONFIG_VAL[] = { - 0x01u, 0x74u, 0x00u, 0x00u, 0x00u, 0x54u, 0x00u, 0x20u, 0x01u, 0x40u, 0x00u, 0x34u, 0x10u, 0x34u, 0x00u, 0x40u, - 0x08u, 0x94u, 0x21u, 0x40u, 0x07u, 0xC0u, 0x18u, 0x3Du, 0x22u, 0x47u, 0x08u, 0x88u, 0x01u, 0x83u, 0x00u, 0x78u, - 0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x02u, 0x01u, 0x74u, 0x00u, 0x00u, - 0x3Fu, 0xC0u, 0x00u, 0x07u, 0x00u, 0x39u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0x00u, 0x01u, 0x00u, - 0x46u, 0x02u, 0x50u, 0x00u, 0x03u, 0xBEu, 0xF0u, 0xDCu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x28u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x00u, 0x03u, 0x00u, 0x03u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), BS_UDB_0_2_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; @@ -1913,7 +2139,7 @@ void cyfitter_cfg(void) CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0 + 0x00000009u), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u); - CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 7655563..c615655 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -26,10 +26,10 @@ /* SCSI_TX_DMA_COMPLETE */ .set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3 .set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 .set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -54,36 +54,34 @@ /* SD_RX_DMA_COMPLETE */ .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08 -.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4 .set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SD_TX_DMA_COMPLETE */ .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5 .set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK -.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB11_MSK +.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB11_ST /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -98,32 +96,54 @@ /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL + +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK +.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST /* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 @@ -138,15 +158,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL /* USBFS_arb_int */ .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -171,24 +191,15 @@ /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG @@ -627,42 +638,42 @@ /* SCSI_RST_ISR */ .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x100 -.set SCSI_RST_ISR__INTC_NUMBER, 8 +.set SCSI_RST_ISR__INTC_MASK, 0x04 +.set SCSI_RST_ISR__INTC_NUMBER, 2 .set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 .set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB09_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB09_ST -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB09_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB09_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB09_MSK -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -670,11 +681,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -684,32 +697,26 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK -.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB05_06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB05_06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB05_06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB05_06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB05_06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB05_06_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB05_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB05_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB05_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB05_F1 /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1197,11 +1204,283 @@ .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set timer_clock__PM_STBY_MSK, 0x04 +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT2_AG +.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX +.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP +.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL +.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT2_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Noise__0__MASK, 0x01 +.set SCSI_Noise__0__PC, CYREG_PRT2_PC0 +.set SCSI_Noise__0__PORT, 2 +.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT +.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT2_PS +.set SCSI_Noise__0__SHIFT, 0 +.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW +.set SCSI_Noise__1__AG, CYREG_PRT6_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT6_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__1__MASK, 0x08 +.set SCSI_Noise__1__PC, CYREG_PRT6_PC3 +.set SCSI_Noise__1__PORT, 6 +.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT6_PS +.set SCSI_Noise__1__SHIFT, 3 +.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__2__AG, CYREG_PRT4_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT4_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__2__MASK, 0x08 +.set SCSI_Noise__2__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__2__PORT, 4 +.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT4_PS +.set SCSI_Noise__2__SHIFT, 3 +.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__3__AG, CYREG_PRT4_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT4_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__3__MASK, 0x80 +.set SCSI_Noise__3__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__3__PORT, 4 +.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT4_PS +.set SCSI_Noise__3__SHIFT, 7 +.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__4__AG, CYREG_PRT6_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT6_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__4__MASK, 0x04 +.set SCSI_Noise__4__PC, CYREG_PRT6_PC2 +.set SCSI_Noise__4__PORT, 6 +.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT6_PS +.set SCSI_Noise__4__SHIFT, 2 +.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x04 +.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2 +.set SCSI_Noise__ACK__PORT, 6 +.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS +.set SCSI_Noise__ACK__SHIFT, 2 +.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG +.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX +.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP +.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL +.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Noise__ATN__MASK, 0x01 +.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0 +.set SCSI_Noise__ATN__PORT, 2 +.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT +.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS +.set SCSI_Noise__ATN__SHIFT, 0 +.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x08 +.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3 +.set SCSI_Noise__BSY__PORT, 6 +.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS +.set SCSI_Noise__BSY__SHIFT, 3 +.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT4_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT4_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__RST__MASK, 0x80 +.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__RST__PORT, 4 +.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT4_PS +.set SCSI_Noise__RST__SHIFT, 7 +.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x08 +.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__SEL__PORT, 4 +.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS +.set SCSI_Noise__SEL__SHIFT, 3 +.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW + /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1211,54 +1490,54 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B1_UDB04_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B1_UDB04_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB08_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB08_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB08_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB08_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB08_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB08_09_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB08_09_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB08_09_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB08_09_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB08_09_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB08_09_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB08_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB08_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB08_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB08_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB08_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB08_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB08_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB08_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB08_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1273,30 +1552,30 @@ /* USBFS_ep_1 */ .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x20 -.set USBFS_ep_1__INTC_NUMBER, 5 +.set USBFS_ep_1__INTC_MASK, 0x40 +.set USBFS_ep_1__INTC_NUMBER, 6 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x40 -.set USBFS_ep_2__INTC_NUMBER, 6 +.set USBFS_ep_2__INTC_MASK, 0x80 +.set USBFS_ep_2__INTC_NUMBER, 7 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x80 -.set USBFS_ep_3__INTC_NUMBER, 7 +.set USBFS_ep_3__INTC_MASK, 0x100 +.set USBFS_ep_3__INTC_NUMBER, 8 .set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -1314,7 +1593,7 @@ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 .set SD_RX_DMA__NUMBEROF_TDS, 0 -.set SD_RX_DMA__PRIORITY, 1 +.set SD_RX_DMA__PRIORITY, 2 .set SD_RX_DMA__TERMIN_EN, 0 .set SD_RX_DMA__TERMIN_SEL, 0 .set SD_RX_DMA__TERMOUT0_EN, 1 @@ -1460,42 +1739,6 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 .set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN -/* SCSI_ATN */ -.set SCSI_ATN__0__MASK, 0x01 -.set SCSI_ATN__0__PC, CYREG_PRT2_PC0 -.set SCSI_ATN__0__PORT, 2 -.set SCSI_ATN__0__SHIFT, 0 -.set SCSI_ATN__AG, CYREG_PRT2_AG -.set SCSI_ATN__AMUX, CYREG_PRT2_AMUX -.set SCSI_ATN__BIE, CYREG_PRT2_BIE -.set SCSI_ATN__BIT_MASK, CYREG_PRT2_BIT_MASK -.set SCSI_ATN__BYP, CYREG_PRT2_BYP -.set SCSI_ATN__CTL, CYREG_PRT2_CTL -.set SCSI_ATN__DM0, CYREG_PRT2_DM0 -.set SCSI_ATN__DM1, CYREG_PRT2_DM1 -.set SCSI_ATN__DM2, CYREG_PRT2_DM2 -.set SCSI_ATN__DR, CYREG_PRT2_DR -.set SCSI_ATN__INP_DIS, CYREG_PRT2_INP_DIS -.set SCSI_ATN__INT__MASK, 0x01 -.set SCSI_ATN__INT__PC, CYREG_PRT2_PC0 -.set SCSI_ATN__INT__PORT, 2 -.set SCSI_ATN__INT__SHIFT, 0 -.set SCSI_ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG -.set SCSI_ATN__LCD_EN, CYREG_PRT2_LCD_EN -.set SCSI_ATN__MASK, 0x01 -.set SCSI_ATN__PORT, 2 -.set SCSI_ATN__PRT, CYREG_PRT2_PRT -.set SCSI_ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL -.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN -.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 -.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 -.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 -.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 -.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT -.set SCSI_ATN__PS, CYREG_PRT2_PS -.set SCSI_ATN__SHIFT, 0 -.set SCSI_ATN__SLW, CYREG_PRT2_SLW - /* SCSI_CLK */ .set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 .set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 @@ -2049,44 +2292,6 @@ .set SCSI_Out__SEL__SHIFT, 7 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW -/* SCSI_RST */ -.set SCSI_RST__0__MASK, 0x80 -.set SCSI_RST__0__PC, CYREG_PRT4_PC7 -.set SCSI_RST__0__PORT, 4 -.set SCSI_RST__0__SHIFT, 7 -.set SCSI_RST__AG, CYREG_PRT4_AG -.set SCSI_RST__AMUX, CYREG_PRT4_AMUX -.set SCSI_RST__BIE, CYREG_PRT4_BIE -.set SCSI_RST__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_RST__BYP, CYREG_PRT4_BYP -.set SCSI_RST__CTL, CYREG_PRT4_CTL -.set SCSI_RST__DM0, CYREG_PRT4_DM0 -.set SCSI_RST__DM1, CYREG_PRT4_DM1 -.set SCSI_RST__DM2, CYREG_PRT4_DM2 -.set SCSI_RST__DR, CYREG_PRT4_DR -.set SCSI_RST__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_RST__INTSTAT, CYREG_PICU4_INTSTAT -.set SCSI_RST__INT__MASK, 0x80 -.set SCSI_RST__INT__PC, CYREG_PRT4_PC7 -.set SCSI_RST__INT__PORT, 4 -.set SCSI_RST__INT__SHIFT, 7 -.set SCSI_RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_RST__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_RST__MASK, 0x80 -.set SCSI_RST__PORT, 4 -.set SCSI_RST__PRT, CYREG_PRT4_PRT -.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_RST__PS, CYREG_PRT4_PS -.set SCSI_RST__SHIFT, 7 -.set SCSI_RST__SLW, CYREG_PRT4_SLW -.set SCSI_RST__SNAP, CYREG_PICU4_SNAP - /* USBFS_Dm */ .set USBFS_Dm__0__MASK, 0x80 .set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 @@ -2181,249 +2386,114 @@ .set SCSI_In__0__PS, CYREG_PRT2_PS .set SCSI_In__0__SHIFT, 1 .set SCSI_In__0__SLW, CYREG_PRT2_SLW -.set SCSI_In__1__AG, CYREG_PRT6_AG -.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__1__BIE, CYREG_PRT6_BIE -.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__1__BYP, CYREG_PRT6_BYP -.set SCSI_In__1__CTL, CYREG_PRT6_CTL -.set SCSI_In__1__DM0, CYREG_PRT6_DM0 -.set SCSI_In__1__DM1, CYREG_PRT6_DM1 -.set SCSI_In__1__DM2, CYREG_PRT6_DM2 -.set SCSI_In__1__DR, CYREG_PRT6_DR -.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__1__MASK, 0x08 -.set SCSI_In__1__PC, CYREG_PRT6_PC3 -.set SCSI_In__1__PORT, 6 -.set SCSI_In__1__PRT, CYREG_PRT6_PRT -.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__1__PS, CYREG_PRT6_PS -.set SCSI_In__1__SHIFT, 3 -.set SCSI_In__1__SLW, CYREG_PRT6_SLW -.set SCSI_In__2__AG, CYREG_PRT6_AG -.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__2__BIE, CYREG_PRT6_BIE -.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__2__BYP, CYREG_PRT6_BYP -.set SCSI_In__2__CTL, CYREG_PRT6_CTL -.set SCSI_In__2__DM0, CYREG_PRT6_DM0 -.set SCSI_In__2__DM1, CYREG_PRT6_DM1 -.set SCSI_In__2__DM2, CYREG_PRT6_DM2 -.set SCSI_In__2__DR, CYREG_PRT6_DR -.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__1__AG, CYREG_PRT4_AG +.set SCSI_In__1__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__1__BIE, CYREG_PRT4_BIE +.set SCSI_In__1__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__1__BYP, CYREG_PRT4_BYP +.set SCSI_In__1__CTL, CYREG_PRT4_CTL +.set SCSI_In__1__DM0, CYREG_PRT4_DM0 +.set SCSI_In__1__DM1, CYREG_PRT4_DM1 +.set SCSI_In__1__DM2, CYREG_PRT4_DM2 +.set SCSI_In__1__DR, CYREG_PRT4_DR +.set SCSI_In__1__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__1__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_In__1__MASK, 0x40 +.set SCSI_In__1__PC, CYREG_PRT4_PC6 +.set SCSI_In__1__PORT, 4 +.set SCSI_In__1__PRT, CYREG_PRT4_PRT +.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__1__PS, CYREG_PRT4_PS +.set SCSI_In__1__SHIFT, 6 +.set SCSI_In__1__SLW, CYREG_PRT4_SLW +.set SCSI_In__2__AG, CYREG_PRT4_AG +.set SCSI_In__2__AMUX, CYREG_PRT4_AMUX +.set SCSI_In__2__BIE, CYREG_PRT4_BIE +.set SCSI_In__2__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_In__2__BYP, CYREG_PRT4_BYP +.set SCSI_In__2__CTL, CYREG_PRT4_CTL +.set SCSI_In__2__DM0, CYREG_PRT4_DM0 +.set SCSI_In__2__DM1, CYREG_PRT4_DM1 +.set SCSI_In__2__DM2, CYREG_PRT4_DM2 +.set SCSI_In__2__DR, CYREG_PRT4_DR +.set SCSI_In__2__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_In__2__LCD_EN, CYREG_PRT4_LCD_EN .set SCSI_In__2__MASK, 0x04 -.set SCSI_In__2__PC, CYREG_PRT6_PC2 -.set SCSI_In__2__PORT, 6 -.set SCSI_In__2__PRT, CYREG_PRT6_PRT -.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__2__PS, CYREG_PRT6_PS +.set SCSI_In__2__PC, CYREG_PRT4_PC2 +.set SCSI_In__2__PORT, 4 +.set SCSI_In__2__PRT, CYREG_PRT4_PRT +.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_In__2__PS, CYREG_PRT4_PS .set SCSI_In__2__SHIFT, 2 -.set SCSI_In__2__SLW, CYREG_PRT6_SLW -.set SCSI_In__3__AG, CYREG_PRT4_AG -.set SCSI_In__3__AMUX, CYREG_PRT4_AMUX -.set SCSI_In__3__BIE, CYREG_PRT4_BIE -.set SCSI_In__3__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_In__3__BYP, CYREG_PRT4_BYP -.set SCSI_In__3__CTL, CYREG_PRT4_CTL -.set SCSI_In__3__DM0, CYREG_PRT4_DM0 -.set SCSI_In__3__DM1, CYREG_PRT4_DM1 -.set SCSI_In__3__DM2, CYREG_PRT4_DM2 -.set SCSI_In__3__DR, CYREG_PRT4_DR -.set SCSI_In__3__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_In__3__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_In__3__MASK, 0x40 -.set SCSI_In__3__PC, CYREG_PRT4_PC6 -.set SCSI_In__3__PORT, 4 -.set SCSI_In__3__PRT, CYREG_PRT4_PRT -.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_In__3__PS, CYREG_PRT4_PS -.set SCSI_In__3__SHIFT, 6 -.set SCSI_In__3__SLW, CYREG_PRT4_SLW -.set SCSI_In__4__AG, CYREG_PRT4_AG -.set SCSI_In__4__AMUX, CYREG_PRT4_AMUX -.set SCSI_In__4__BIE, CYREG_PRT4_BIE -.set SCSI_In__4__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_In__4__BYP, CYREG_PRT4_BYP -.set SCSI_In__4__CTL, CYREG_PRT4_CTL -.set SCSI_In__4__DM0, CYREG_PRT4_DM0 -.set SCSI_In__4__DM1, CYREG_PRT4_DM1 -.set SCSI_In__4__DM2, CYREG_PRT4_DM2 -.set SCSI_In__4__DR, CYREG_PRT4_DR -.set SCSI_In__4__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_In__4__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_In__4__MASK, 0x08 -.set SCSI_In__4__PC, CYREG_PRT4_PC3 -.set SCSI_In__4__PORT, 4 -.set SCSI_In__4__PRT, CYREG_PRT4_PRT -.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_In__4__PS, CYREG_PRT4_PS -.set SCSI_In__4__SHIFT, 3 -.set SCSI_In__4__SLW, CYREG_PRT4_SLW -.set SCSI_In__5__AG, CYREG_PRT4_AG -.set SCSI_In__5__AMUX, CYREG_PRT4_AMUX -.set SCSI_In__5__BIE, CYREG_PRT4_BIE -.set SCSI_In__5__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_In__5__BYP, CYREG_PRT4_BYP -.set SCSI_In__5__CTL, CYREG_PRT4_CTL -.set SCSI_In__5__DM0, CYREG_PRT4_DM0 -.set SCSI_In__5__DM1, CYREG_PRT4_DM1 -.set SCSI_In__5__DM2, CYREG_PRT4_DM2 -.set SCSI_In__5__DR, CYREG_PRT4_DR -.set SCSI_In__5__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_In__5__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_In__5__MASK, 0x04 -.set SCSI_In__5__PC, CYREG_PRT4_PC2 -.set SCSI_In__5__PORT, 4 -.set SCSI_In__5__PRT, CYREG_PRT4_PRT -.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_In__5__PS, CYREG_PRT4_PS -.set SCSI_In__5__SHIFT, 2 -.set SCSI_In__5__SLW, CYREG_PRT4_SLW -.set SCSI_In__6__AG, CYREG_PRT0_AG -.set SCSI_In__6__AMUX, CYREG_PRT0_AMUX -.set SCSI_In__6__BIE, CYREG_PRT0_BIE -.set SCSI_In__6__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_In__6__BYP, CYREG_PRT0_BYP -.set SCSI_In__6__CTL, CYREG_PRT0_CTL -.set SCSI_In__6__DM0, CYREG_PRT0_DM0 -.set SCSI_In__6__DM1, CYREG_PRT0_DM1 -.set SCSI_In__6__DM2, CYREG_PRT0_DM2 -.set SCSI_In__6__DR, CYREG_PRT0_DR -.set SCSI_In__6__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_In__6__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_In__6__MASK, 0x20 -.set SCSI_In__6__PC, CYREG_PRT0_PC5 -.set SCSI_In__6__PORT, 0 -.set SCSI_In__6__PRT, CYREG_PRT0_PRT -.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_In__6__PS, CYREG_PRT0_PS -.set SCSI_In__6__SHIFT, 5 -.set SCSI_In__6__SLW, CYREG_PRT0_SLW -.set SCSI_In__7__AG, CYREG_PRT0_AG -.set SCSI_In__7__AMUX, CYREG_PRT0_AMUX -.set SCSI_In__7__BIE, CYREG_PRT0_BIE -.set SCSI_In__7__BIT_MASK, CYREG_PRT0_BIT_MASK -.set SCSI_In__7__BYP, CYREG_PRT0_BYP -.set SCSI_In__7__CTL, CYREG_PRT0_CTL -.set SCSI_In__7__DM0, CYREG_PRT0_DM0 -.set SCSI_In__7__DM1, CYREG_PRT0_DM1 -.set SCSI_In__7__DM2, CYREG_PRT0_DM2 -.set SCSI_In__7__DR, CYREG_PRT0_DR -.set SCSI_In__7__INP_DIS, CYREG_PRT0_INP_DIS -.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG -.set SCSI_In__7__LCD_EN, CYREG_PRT0_LCD_EN -.set SCSI_In__7__MASK, 0x10 -.set SCSI_In__7__PC, CYREG_PRT0_PC4 -.set SCSI_In__7__PORT, 0 -.set SCSI_In__7__PRT, CYREG_PRT0_PRT -.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL -.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN -.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 -.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 -.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 -.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 -.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT -.set SCSI_In__7__PS, CYREG_PRT0_PS -.set SCSI_In__7__SHIFT, 4 -.set SCSI_In__7__SLW, CYREG_PRT0_SLW -.set SCSI_In__ACK__AG, CYREG_PRT6_AG -.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE -.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP -.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL -.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0 -.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1 -.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2 -.set SCSI_In__ACK__DR, CYREG_PRT6_DR -.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__ACK__MASK, 0x04 -.set SCSI_In__ACK__PC, CYREG_PRT6_PC2 -.set SCSI_In__ACK__PORT, 6 -.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT -.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__ACK__PS, CYREG_PRT6_PS -.set SCSI_In__ACK__SHIFT, 2 -.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW -.set SCSI_In__BSY__AG, CYREG_PRT6_AG -.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX -.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE -.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK -.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP -.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL -.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0 -.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1 -.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2 -.set SCSI_In__BSY__DR, CYREG_PRT6_DR -.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS -.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG -.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN -.set SCSI_In__BSY__MASK, 0x08 -.set SCSI_In__BSY__PC, CYREG_PRT6_PC3 -.set SCSI_In__BSY__PORT, 6 -.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT -.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL -.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN -.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 -.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 -.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 -.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 -.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT -.set SCSI_In__BSY__PS, CYREG_PRT6_PS -.set SCSI_In__BSY__SHIFT, 3 -.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW +.set SCSI_In__2__SLW, CYREG_PRT4_SLW +.set SCSI_In__3__AG, CYREG_PRT0_AG +.set SCSI_In__3__AMUX, CYREG_PRT0_AMUX +.set SCSI_In__3__BIE, CYREG_PRT0_BIE +.set SCSI_In__3__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_In__3__BYP, CYREG_PRT0_BYP +.set SCSI_In__3__CTL, CYREG_PRT0_CTL +.set SCSI_In__3__DM0, CYREG_PRT0_DM0 +.set SCSI_In__3__DM1, CYREG_PRT0_DM1 +.set SCSI_In__3__DM2, CYREG_PRT0_DM2 +.set SCSI_In__3__DR, CYREG_PRT0_DR +.set SCSI_In__3__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_In__3__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_In__3__MASK, 0x20 +.set SCSI_In__3__PC, CYREG_PRT0_PC5 +.set SCSI_In__3__PORT, 0 +.set SCSI_In__3__PRT, CYREG_PRT0_PRT +.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_In__3__PS, CYREG_PRT0_PS +.set SCSI_In__3__SHIFT, 5 +.set SCSI_In__3__SLW, CYREG_PRT0_SLW +.set SCSI_In__4__AG, CYREG_PRT0_AG +.set SCSI_In__4__AMUX, CYREG_PRT0_AMUX +.set SCSI_In__4__BIE, CYREG_PRT0_BIE +.set SCSI_In__4__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_In__4__BYP, CYREG_PRT0_BYP +.set SCSI_In__4__CTL, CYREG_PRT0_CTL +.set SCSI_In__4__DM0, CYREG_PRT0_DM0 +.set SCSI_In__4__DM1, CYREG_PRT0_DM1 +.set SCSI_In__4__DM2, CYREG_PRT0_DM2 +.set SCSI_In__4__DR, CYREG_PRT0_DR +.set SCSI_In__4__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_In__4__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_In__4__MASK, 0x10 +.set SCSI_In__4__PC, CYREG_PRT0_PC4 +.set SCSI_In__4__PORT, 0 +.set SCSI_In__4__PRT, CYREG_PRT0_PRT +.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_In__4__PS, CYREG_PRT0_PS +.set SCSI_In__4__SHIFT, 4 +.set SCSI_In__4__SLW, CYREG_PRT0_SLW .set SCSI_In__CD__AG, CYREG_PRT4_AG .set SCSI_In__CD__AMUX, CYREG_PRT4_AMUX .set SCSI_In__CD__BIE, CYREG_PRT4_BIE @@ -2559,33 +2629,6 @@ .set SCSI_In__REQ__PS, CYREG_PRT0_PS .set SCSI_In__REQ__SHIFT, 5 .set SCSI_In__REQ__SLW, CYREG_PRT0_SLW -.set SCSI_In__SEL__AG, CYREG_PRT4_AG -.set SCSI_In__SEL__AMUX, CYREG_PRT4_AMUX -.set SCSI_In__SEL__BIE, CYREG_PRT4_BIE -.set SCSI_In__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK -.set SCSI_In__SEL__BYP, CYREG_PRT4_BYP -.set SCSI_In__SEL__CTL, CYREG_PRT4_CTL -.set SCSI_In__SEL__DM0, CYREG_PRT4_DM0 -.set SCSI_In__SEL__DM1, CYREG_PRT4_DM1 -.set SCSI_In__SEL__DM2, CYREG_PRT4_DM2 -.set SCSI_In__SEL__DR, CYREG_PRT4_DR -.set SCSI_In__SEL__INP_DIS, CYREG_PRT4_INP_DIS -.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG -.set SCSI_In__SEL__LCD_EN, CYREG_PRT4_LCD_EN -.set SCSI_In__SEL__MASK, 0x08 -.set SCSI_In__SEL__PC, CYREG_PRT4_PC3 -.set SCSI_In__SEL__PORT, 4 -.set SCSI_In__SEL__PRT, CYREG_PRT4_PRT -.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL -.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN -.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 -.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 -.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 -.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 -.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT -.set SCSI_In__SEL__PS, CYREG_PRT4_PS -.set SCSI_In__SEL__SHIFT, 3 -.set SCSI_In__SEL__SLW, CYREG_PRT4_SLW /* SD_MISO */ .set SD_MISO__0__MASK, 0x02 @@ -2886,7 +2929,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x1000 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000001E +.set CYDEV_INTR_RISING, 0x0000003E .set CYDEV_PROJ_TYPE, 2 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 .set CYDEV_PROJ_TYPE_LOADABLE, 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 02f5ce9..8e9b2fd 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -26,10 +26,10 @@ SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA_COMPLETE */ SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -54,36 +54,34 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 /* SD_RX_DMA_COMPLETE */ SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SD_TX_DMA_COMPLETE */ SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB11_ST /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -98,32 +96,54 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL + +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST /* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -138,15 +158,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL /* USBFS_arb_int */ USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -171,24 +191,15 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG @@ -627,42 +638,42 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW /* SCSI_RST_ISR */ SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x100 -SCSI_RST_ISR__INTC_NUMBER EQU 8 +SCSI_RST_ISR__INTC_MASK EQU 0x04 +SCSI_RST_ISR__INTC_NUMBER EQU 2 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -670,11 +681,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -684,32 +697,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1 /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1197,11 +1204,283 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT2_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT2_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__0__MASK EQU 0x01 +SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__0__PORT EQU 2 +SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT2_PS +SCSI_Noise__0__SHIFT EQU 0 +SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x08 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 3 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT4_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT4_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__2__MASK EQU 0x08 +SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__2__PORT EQU 4 +SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT4_PS +SCSI_Noise__2__SHIFT EQU 3 +SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__3__AG EQU CYREG_PRT4_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT4_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__3__MASK EQU 0x80 +SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__3__PORT EQU 4 +SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT4_PS +SCSI_Noise__3__SHIFT EQU 7 +SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x04 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 2 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x04 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 2 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x01 +SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__ATN__PORT EQU 2 +SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS +SCSI_Noise__ATN__SHIFT EQU 0 +SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x08 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 3 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT4_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT4_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__RST__MASK EQU 0x80 +SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__RST__PORT EQU 4 +SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT4_PS +SCSI_Noise__RST__SHIFT EQU 7 +SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x08 +SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__SEL__PORT EQU 4 +SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS +SCSI_Noise__SEL__SHIFT EQU 3 +SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW + /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1211,54 +1490,54 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B1_UDB04_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B1_UDB04_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB08_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB08_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB08_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB08_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB08_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB08_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB08_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB08_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB08_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB08_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB08_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1273,30 +1552,30 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_1 */ USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x20 -USBFS_ep_1__INTC_NUMBER EQU 5 +USBFS_ep_1__INTC_MASK EQU 0x40 +USBFS_ep_1__INTC_NUMBER EQU 6 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x40 -USBFS_ep_2__INTC_NUMBER EQU 6 +USBFS_ep_2__INTC_MASK EQU 0x80 +USBFS_ep_2__INTC_NUMBER EQU 7 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x80 -USBFS_ep_3__INTC_NUMBER EQU 7 +USBFS_ep_3__INTC_MASK EQU 0x100 +USBFS_ep_3__INTC_NUMBER EQU 8 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -1314,7 +1593,7 @@ USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 SD_RX_DMA__NUMBEROF_TDS EQU 0 -SD_RX_DMA__PRIORITY EQU 1 +SD_RX_DMA__PRIORITY EQU 2 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 @@ -1460,42 +1739,6 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -/* SCSI_ATN */ -SCSI_ATN__0__MASK EQU 0x01 -SCSI_ATN__0__PC EQU CYREG_PRT2_PC0 -SCSI_ATN__0__PORT EQU 2 -SCSI_ATN__0__SHIFT EQU 0 -SCSI_ATN__AG EQU CYREG_PRT2_AG -SCSI_ATN__AMUX EQU CYREG_PRT2_AMUX -SCSI_ATN__BIE EQU CYREG_PRT2_BIE -SCSI_ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_ATN__BYP EQU CYREG_PRT2_BYP -SCSI_ATN__CTL EQU CYREG_PRT2_CTL -SCSI_ATN__DM0 EQU CYREG_PRT2_DM0 -SCSI_ATN__DM1 EQU CYREG_PRT2_DM1 -SCSI_ATN__DM2 EQU CYREG_PRT2_DM2 -SCSI_ATN__DR EQU CYREG_PRT2_DR -SCSI_ATN__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_ATN__INT__MASK EQU 0x01 -SCSI_ATN__INT__PC EQU CYREG_PRT2_PC0 -SCSI_ATN__INT__PORT EQU 2 -SCSI_ATN__INT__SHIFT EQU 0 -SCSI_ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_ATN__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_ATN__MASK EQU 0x01 -SCSI_ATN__PORT EQU 2 -SCSI_ATN__PRT EQU CYREG_PRT2_PRT -SCSI_ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_ATN__PS EQU CYREG_PRT2_PS -SCSI_ATN__SHIFT EQU 0 -SCSI_ATN__SLW EQU CYREG_PRT2_SLW - /* SCSI_CLK */ SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 @@ -2049,44 +2292,6 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 7 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW -/* SCSI_RST */ -SCSI_RST__0__MASK EQU 0x80 -SCSI_RST__0__PC EQU CYREG_PRT4_PC7 -SCSI_RST__0__PORT EQU 4 -SCSI_RST__0__SHIFT EQU 7 -SCSI_RST__AG EQU CYREG_PRT4_AG -SCSI_RST__AMUX EQU CYREG_PRT4_AMUX -SCSI_RST__BIE EQU CYREG_PRT4_BIE -SCSI_RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_RST__BYP EQU CYREG_PRT4_BYP -SCSI_RST__CTL EQU CYREG_PRT4_CTL -SCSI_RST__DM0 EQU CYREG_PRT4_DM0 -SCSI_RST__DM1 EQU CYREG_PRT4_DM1 -SCSI_RST__DM2 EQU CYREG_PRT4_DM2 -SCSI_RST__DR EQU CYREG_PRT4_DR -SCSI_RST__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_RST__INTSTAT EQU CYREG_PICU4_INTSTAT -SCSI_RST__INT__MASK EQU 0x80 -SCSI_RST__INT__PC EQU CYREG_PRT4_PC7 -SCSI_RST__INT__PORT EQU 4 -SCSI_RST__INT__SHIFT EQU 7 -SCSI_RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_RST__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_RST__MASK EQU 0x80 -SCSI_RST__PORT EQU 4 -SCSI_RST__PRT EQU CYREG_PRT4_PRT -SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_RST__PS EQU CYREG_PRT4_PS -SCSI_RST__SHIFT EQU 7 -SCSI_RST__SLW EQU CYREG_PRT4_SLW -SCSI_RST__SNAP EQU CYREG_PICU4_SNAP - /* USBFS_Dm */ USBFS_Dm__0__MASK EQU 0x80 USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 @@ -2181,249 +2386,114 @@ SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT SCSI_In__0__PS EQU CYREG_PRT2_PS SCSI_In__0__SHIFT EQU 1 SCSI_In__0__SLW EQU CYREG_PRT2_SLW -SCSI_In__1__AG EQU CYREG_PRT6_AG -SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__1__BIE EQU CYREG_PRT6_BIE -SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__1__BYP EQU CYREG_PRT6_BYP -SCSI_In__1__CTL EQU CYREG_PRT6_CTL -SCSI_In__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__1__DR EQU CYREG_PRT6_DR -SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__1__MASK EQU 0x08 -SCSI_In__1__PC EQU CYREG_PRT6_PC3 -SCSI_In__1__PORT EQU 6 -SCSI_In__1__PRT EQU CYREG_PRT6_PRT -SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__1__PS EQU CYREG_PRT6_PS -SCSI_In__1__SHIFT EQU 3 -SCSI_In__1__SLW EQU CYREG_PRT6_SLW -SCSI_In__2__AG EQU CYREG_PRT6_AG -SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__2__BIE EQU CYREG_PRT6_BIE -SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__2__BYP EQU CYREG_PRT6_BYP -SCSI_In__2__CTL EQU CYREG_PRT6_CTL -SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__2__DR EQU CYREG_PRT6_DR -SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__1__AG EQU CYREG_PRT4_AG +SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__1__BIE EQU CYREG_PRT4_BIE +SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__1__BYP EQU CYREG_PRT4_BYP +SCSI_In__1__CTL EQU CYREG_PRT4_CTL +SCSI_In__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__1__DR EQU CYREG_PRT4_DR +SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__1__MASK EQU 0x40 +SCSI_In__1__PC EQU CYREG_PRT4_PC6 +SCSI_In__1__PORT EQU 4 +SCSI_In__1__PRT EQU CYREG_PRT4_PRT +SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__1__PS EQU CYREG_PRT4_PS +SCSI_In__1__SHIFT EQU 6 +SCSI_In__1__SLW EQU CYREG_PRT4_SLW +SCSI_In__2__AG EQU CYREG_PRT4_AG +SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__2__BIE EQU CYREG_PRT4_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT4_BYP +SCSI_In__2__CTL EQU CYREG_PRT4_CTL +SCSI_In__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__2__DR EQU CYREG_PRT4_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN SCSI_In__2__MASK EQU 0x04 -SCSI_In__2__PC EQU CYREG_PRT6_PC2 -SCSI_In__2__PORT EQU 6 -SCSI_In__2__PRT EQU CYREG_PRT6_PRT -SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__2__PS EQU CYREG_PRT6_PS +SCSI_In__2__PC EQU CYREG_PRT4_PC2 +SCSI_In__2__PORT EQU 4 +SCSI_In__2__PRT EQU CYREG_PRT4_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT4_PS SCSI_In__2__SHIFT EQU 2 -SCSI_In__2__SLW EQU CYREG_PRT6_SLW -SCSI_In__3__AG EQU CYREG_PRT4_AG -SCSI_In__3__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__3__BIE EQU CYREG_PRT4_BIE -SCSI_In__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__3__BYP EQU CYREG_PRT4_BYP -SCSI_In__3__CTL EQU CYREG_PRT4_CTL -SCSI_In__3__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__3__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__3__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__3__DR EQU CYREG_PRT4_DR -SCSI_In__3__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__3__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__3__MASK EQU 0x40 -SCSI_In__3__PC EQU CYREG_PRT4_PC6 -SCSI_In__3__PORT EQU 4 -SCSI_In__3__PRT EQU CYREG_PRT4_PRT -SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__3__PS EQU CYREG_PRT4_PS -SCSI_In__3__SHIFT EQU 6 -SCSI_In__3__SLW EQU CYREG_PRT4_SLW -SCSI_In__4__AG EQU CYREG_PRT4_AG -SCSI_In__4__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__4__BIE EQU CYREG_PRT4_BIE -SCSI_In__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__4__BYP EQU CYREG_PRT4_BYP -SCSI_In__4__CTL EQU CYREG_PRT4_CTL -SCSI_In__4__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__4__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__4__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__4__DR EQU CYREG_PRT4_DR -SCSI_In__4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__4__MASK EQU 0x08 -SCSI_In__4__PC EQU CYREG_PRT4_PC3 -SCSI_In__4__PORT EQU 4 -SCSI_In__4__PRT EQU CYREG_PRT4_PRT -SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__4__PS EQU CYREG_PRT4_PS -SCSI_In__4__SHIFT EQU 3 -SCSI_In__4__SLW EQU CYREG_PRT4_SLW -SCSI_In__5__AG EQU CYREG_PRT4_AG -SCSI_In__5__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__5__BIE EQU CYREG_PRT4_BIE -SCSI_In__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__5__BYP EQU CYREG_PRT4_BYP -SCSI_In__5__CTL EQU CYREG_PRT4_CTL -SCSI_In__5__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__5__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__5__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__5__DR EQU CYREG_PRT4_DR -SCSI_In__5__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__5__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__5__MASK EQU 0x04 -SCSI_In__5__PC EQU CYREG_PRT4_PC2 -SCSI_In__5__PORT EQU 4 -SCSI_In__5__PRT EQU CYREG_PRT4_PRT -SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__5__PS EQU CYREG_PRT4_PS -SCSI_In__5__SHIFT EQU 2 -SCSI_In__5__SLW EQU CYREG_PRT4_SLW -SCSI_In__6__AG EQU CYREG_PRT0_AG -SCSI_In__6__AMUX EQU CYREG_PRT0_AMUX -SCSI_In__6__BIE EQU CYREG_PRT0_BIE -SCSI_In__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_In__6__BYP EQU CYREG_PRT0_BYP -SCSI_In__6__CTL EQU CYREG_PRT0_CTL -SCSI_In__6__DM0 EQU CYREG_PRT0_DM0 -SCSI_In__6__DM1 EQU CYREG_PRT0_DM1 -SCSI_In__6__DM2 EQU CYREG_PRT0_DM2 -SCSI_In__6__DR EQU CYREG_PRT0_DR -SCSI_In__6__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_In__6__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_In__6__MASK EQU 0x20 -SCSI_In__6__PC EQU CYREG_PRT0_PC5 -SCSI_In__6__PORT EQU 0 -SCSI_In__6__PRT EQU CYREG_PRT0_PRT -SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_In__6__PS EQU CYREG_PRT0_PS -SCSI_In__6__SHIFT EQU 5 -SCSI_In__6__SLW EQU CYREG_PRT0_SLW -SCSI_In__7__AG EQU CYREG_PRT0_AG -SCSI_In__7__AMUX EQU CYREG_PRT0_AMUX -SCSI_In__7__BIE EQU CYREG_PRT0_BIE -SCSI_In__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_In__7__BYP EQU CYREG_PRT0_BYP -SCSI_In__7__CTL EQU CYREG_PRT0_CTL -SCSI_In__7__DM0 EQU CYREG_PRT0_DM0 -SCSI_In__7__DM1 EQU CYREG_PRT0_DM1 -SCSI_In__7__DM2 EQU CYREG_PRT0_DM2 -SCSI_In__7__DR EQU CYREG_PRT0_DR -SCSI_In__7__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_In__7__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_In__7__MASK EQU 0x10 -SCSI_In__7__PC EQU CYREG_PRT0_PC4 -SCSI_In__7__PORT EQU 0 -SCSI_In__7__PRT EQU CYREG_PRT0_PRT -SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_In__7__PS EQU CYREG_PRT0_PS -SCSI_In__7__SHIFT EQU 4 -SCSI_In__7__SLW EQU CYREG_PRT0_SLW -SCSI_In__ACK__AG EQU CYREG_PRT6_AG -SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__ACK__DR EQU CYREG_PRT6_DR -SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__ACK__MASK EQU 0x04 -SCSI_In__ACK__PC EQU CYREG_PRT6_PC2 -SCSI_In__ACK__PORT EQU 6 -SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__ACK__PS EQU CYREG_PRT6_PS -SCSI_In__ACK__SHIFT EQU 2 -SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_In__BSY__AG EQU CYREG_PRT6_AG -SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__BSY__DR EQU CYREG_PRT6_DR -SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__BSY__MASK EQU 0x08 -SCSI_In__BSY__PC EQU CYREG_PRT6_PC3 -SCSI_In__BSY__PORT EQU 6 -SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__BSY__PS EQU CYREG_PRT6_PS -SCSI_In__BSY__SHIFT EQU 3 -SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_In__2__SLW EQU CYREG_PRT4_SLW +SCSI_In__3__AG EQU CYREG_PRT0_AG +SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__3__BIE EQU CYREG_PRT0_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT0_BYP +SCSI_In__3__CTL EQU CYREG_PRT0_CTL +SCSI_In__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__3__DR EQU CYREG_PRT0_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__3__MASK EQU 0x20 +SCSI_In__3__PC EQU CYREG_PRT0_PC5 +SCSI_In__3__PORT EQU 0 +SCSI_In__3__PRT EQU CYREG_PRT0_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT0_PS +SCSI_In__3__SHIFT EQU 5 +SCSI_In__3__SLW EQU CYREG_PRT0_SLW +SCSI_In__4__AG EQU CYREG_PRT0_AG +SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__4__BIE EQU CYREG_PRT0_BIE +SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__4__BYP EQU CYREG_PRT0_BYP +SCSI_In__4__CTL EQU CYREG_PRT0_CTL +SCSI_In__4__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__4__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__4__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__4__DR EQU CYREG_PRT0_DR +SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__4__MASK EQU 0x10 +SCSI_In__4__PC EQU CYREG_PRT0_PC4 +SCSI_In__4__PORT EQU 0 +SCSI_In__4__PRT EQU CYREG_PRT0_PRT +SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__4__PS EQU CYREG_PRT0_PS +SCSI_In__4__SHIFT EQU 4 +SCSI_In__4__SLW EQU CYREG_PRT0_SLW SCSI_In__CD__AG EQU CYREG_PRT4_AG SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX SCSI_In__CD__BIE EQU CYREG_PRT4_BIE @@ -2559,33 +2629,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT0_PS SCSI_In__REQ__SHIFT EQU 5 SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW -SCSI_In__SEL__AG EQU CYREG_PRT4_AG -SCSI_In__SEL__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__SEL__BIE EQU CYREG_PRT4_BIE -SCSI_In__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__SEL__BYP EQU CYREG_PRT4_BYP -SCSI_In__SEL__CTL EQU CYREG_PRT4_CTL -SCSI_In__SEL__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__SEL__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__SEL__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__SEL__DR EQU CYREG_PRT4_DR -SCSI_In__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__SEL__MASK EQU 0x08 -SCSI_In__SEL__PC EQU CYREG_PRT4_PC3 -SCSI_In__SEL__PORT EQU 4 -SCSI_In__SEL__PRT EQU CYREG_PRT4_PRT -SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__SEL__PS EQU CYREG_PRT4_PS -SCSI_In__SEL__SHIFT EQU 3 -SCSI_In__SEL__SLW EQU CYREG_PRT4_SLW /* SD_MISO */ SD_MISO__0__MASK EQU 0x02 @@ -2886,7 +2929,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x1000 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000001E +CYDEV_INTR_RISING EQU 0x0000003E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index a831aed..ce5d807 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -26,10 +26,10 @@ SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_TX_DMA_COMPLETE SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -54,36 +54,34 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 ; SD_RX_DMA_COMPLETE SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SD_TX_DMA_COMPLETE SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB11_ST ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -98,32 +96,54 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL + +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST ; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -138,15 +158,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL ; USBFS_arb_int USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -171,24 +191,15 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG @@ -627,42 +638,42 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW ; SCSI_RST_ISR SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x100 -SCSI_RST_ISR__INTC_NUMBER EQU 8 +SCSI_RST_ISR__INTC_MASK EQU 0x04 +SCSI_RST_ISR__INTC_NUMBER EQU 2 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -670,11 +681,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -684,32 +697,26 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1 ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1197,11 +1204,283 @@ timer_clock__PM_ACT_MSK EQU 0x04 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 timer_clock__PM_STBY_MSK EQU 0x04 +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT2_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT2_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__0__MASK EQU 0x01 +SCSI_Noise__0__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__0__PORT EQU 2 +SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT2_PS +SCSI_Noise__0__SHIFT EQU 0 +SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__1__AG EQU CYREG_PRT6_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT6_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__1__MASK EQU 0x08 +SCSI_Noise__1__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__1__PORT EQU 6 +SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT6_PS +SCSI_Noise__1__SHIFT EQU 3 +SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__2__AG EQU CYREG_PRT4_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT4_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__2__MASK EQU 0x08 +SCSI_Noise__2__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__2__PORT EQU 4 +SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT4_PS +SCSI_Noise__2__SHIFT EQU 3 +SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__3__AG EQU CYREG_PRT4_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT4_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__3__MASK EQU 0x80 +SCSI_Noise__3__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__3__PORT EQU 4 +SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT4_PS +SCSI_Noise__3__SHIFT EQU 7 +SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__4__AG EQU CYREG_PRT6_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT6_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__4__MASK EQU 0x04 +SCSI_Noise__4__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__4__PORT EQU 6 +SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT6_PS +SCSI_Noise__4__SHIFT EQU 2 +SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x04 +SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2 +SCSI_Noise__ACK__PORT EQU 6 +SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS +SCSI_Noise__ACK__SHIFT EQU 2 +SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x01 +SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0 +SCSI_Noise__ATN__PORT EQU 2 +SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS +SCSI_Noise__ATN__SHIFT EQU 0 +SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x08 +SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3 +SCSI_Noise__BSY__PORT EQU 6 +SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS +SCSI_Noise__BSY__SHIFT EQU 3 +SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT4_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT4_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__RST__MASK EQU 0x80 +SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__RST__PORT EQU 4 +SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT4_PS +SCSI_Noise__RST__SHIFT EQU 7 +SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x08 +SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__SEL__PORT EQU 4 +SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS +SCSI_Noise__SEL__SHIFT EQU 3 +SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW + ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1211,54 +1490,54 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B1_UDB04_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B1_UDB04_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB08_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB08_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB08_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB08_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB08_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB08_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB08_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB08_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB08_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB08_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB08_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1273,30 +1552,30 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_1 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x20 -USBFS_ep_1__INTC_NUMBER EQU 5 +USBFS_ep_1__INTC_MASK EQU 0x40 +USBFS_ep_1__INTC_NUMBER EQU 6 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_2 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x40 -USBFS_ep_2__INTC_NUMBER EQU 6 +USBFS_ep_2__INTC_MASK EQU 0x80 +USBFS_ep_2__INTC_NUMBER EQU 7 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_3 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x80 -USBFS_ep_3__INTC_NUMBER EQU 7 +USBFS_ep_3__INTC_MASK EQU 0x100 +USBFS_ep_3__INTC_NUMBER EQU 8 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -1314,7 +1593,7 @@ USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 SD_RX_DMA__NUMBEROF_TDS EQU 0 -SD_RX_DMA__PRIORITY EQU 1 +SD_RX_DMA__PRIORITY EQU 2 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 @@ -1460,42 +1739,6 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN -; SCSI_ATN -SCSI_ATN__0__MASK EQU 0x01 -SCSI_ATN__0__PC EQU CYREG_PRT2_PC0 -SCSI_ATN__0__PORT EQU 2 -SCSI_ATN__0__SHIFT EQU 0 -SCSI_ATN__AG EQU CYREG_PRT2_AG -SCSI_ATN__AMUX EQU CYREG_PRT2_AMUX -SCSI_ATN__BIE EQU CYREG_PRT2_BIE -SCSI_ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK -SCSI_ATN__BYP EQU CYREG_PRT2_BYP -SCSI_ATN__CTL EQU CYREG_PRT2_CTL -SCSI_ATN__DM0 EQU CYREG_PRT2_DM0 -SCSI_ATN__DM1 EQU CYREG_PRT2_DM1 -SCSI_ATN__DM2 EQU CYREG_PRT2_DM2 -SCSI_ATN__DR EQU CYREG_PRT2_DR -SCSI_ATN__INP_DIS EQU CYREG_PRT2_INP_DIS -SCSI_ATN__INT__MASK EQU 0x01 -SCSI_ATN__INT__PC EQU CYREG_PRT2_PC0 -SCSI_ATN__INT__PORT EQU 2 -SCSI_ATN__INT__SHIFT EQU 0 -SCSI_ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG -SCSI_ATN__LCD_EN EQU CYREG_PRT2_LCD_EN -SCSI_ATN__MASK EQU 0x01 -SCSI_ATN__PORT EQU 2 -SCSI_ATN__PRT EQU CYREG_PRT2_PRT -SCSI_ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL -SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN -SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 -SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 -SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 -SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 -SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT -SCSI_ATN__PS EQU CYREG_PRT2_PS -SCSI_ATN__SHIFT EQU 0 -SCSI_ATN__SLW EQU CYREG_PRT2_SLW - ; SCSI_CLK SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 @@ -2049,44 +2292,6 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS SCSI_Out__SEL__SHIFT EQU 7 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW -; SCSI_RST -SCSI_RST__0__MASK EQU 0x80 -SCSI_RST__0__PC EQU CYREG_PRT4_PC7 -SCSI_RST__0__PORT EQU 4 -SCSI_RST__0__SHIFT EQU 7 -SCSI_RST__AG EQU CYREG_PRT4_AG -SCSI_RST__AMUX EQU CYREG_PRT4_AMUX -SCSI_RST__BIE EQU CYREG_PRT4_BIE -SCSI_RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_RST__BYP EQU CYREG_PRT4_BYP -SCSI_RST__CTL EQU CYREG_PRT4_CTL -SCSI_RST__DM0 EQU CYREG_PRT4_DM0 -SCSI_RST__DM1 EQU CYREG_PRT4_DM1 -SCSI_RST__DM2 EQU CYREG_PRT4_DM2 -SCSI_RST__DR EQU CYREG_PRT4_DR -SCSI_RST__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_RST__INTSTAT EQU CYREG_PICU4_INTSTAT -SCSI_RST__INT__MASK EQU 0x80 -SCSI_RST__INT__PC EQU CYREG_PRT4_PC7 -SCSI_RST__INT__PORT EQU 4 -SCSI_RST__INT__SHIFT EQU 7 -SCSI_RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_RST__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_RST__MASK EQU 0x80 -SCSI_RST__PORT EQU 4 -SCSI_RST__PRT EQU CYREG_PRT4_PRT -SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_RST__PS EQU CYREG_PRT4_PS -SCSI_RST__SHIFT EQU 7 -SCSI_RST__SLW EQU CYREG_PRT4_SLW -SCSI_RST__SNAP EQU CYREG_PICU4_SNAP - ; USBFS_Dm USBFS_Dm__0__MASK EQU 0x80 USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 @@ -2181,249 +2386,114 @@ SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT SCSI_In__0__PS EQU CYREG_PRT2_PS SCSI_In__0__SHIFT EQU 1 SCSI_In__0__SLW EQU CYREG_PRT2_SLW -SCSI_In__1__AG EQU CYREG_PRT6_AG -SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__1__BIE EQU CYREG_PRT6_BIE -SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__1__BYP EQU CYREG_PRT6_BYP -SCSI_In__1__CTL EQU CYREG_PRT6_CTL -SCSI_In__1__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__1__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__1__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__1__DR EQU CYREG_PRT6_DR -SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__1__MASK EQU 0x08 -SCSI_In__1__PC EQU CYREG_PRT6_PC3 -SCSI_In__1__PORT EQU 6 -SCSI_In__1__PRT EQU CYREG_PRT6_PRT -SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__1__PS EQU CYREG_PRT6_PS -SCSI_In__1__SHIFT EQU 3 -SCSI_In__1__SLW EQU CYREG_PRT6_SLW -SCSI_In__2__AG EQU CYREG_PRT6_AG -SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__2__BIE EQU CYREG_PRT6_BIE -SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__2__BYP EQU CYREG_PRT6_BYP -SCSI_In__2__CTL EQU CYREG_PRT6_CTL -SCSI_In__2__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__2__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__2__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__2__DR EQU CYREG_PRT6_DR -SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__1__AG EQU CYREG_PRT4_AG +SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__1__BIE EQU CYREG_PRT4_BIE +SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__1__BYP EQU CYREG_PRT4_BYP +SCSI_In__1__CTL EQU CYREG_PRT4_CTL +SCSI_In__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__1__DR EQU CYREG_PRT4_DR +SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_In__1__MASK EQU 0x40 +SCSI_In__1__PC EQU CYREG_PRT4_PC6 +SCSI_In__1__PORT EQU 4 +SCSI_In__1__PRT EQU CYREG_PRT4_PRT +SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__1__PS EQU CYREG_PRT4_PS +SCSI_In__1__SHIFT EQU 6 +SCSI_In__1__SLW EQU CYREG_PRT4_SLW +SCSI_In__2__AG EQU CYREG_PRT4_AG +SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX +SCSI_In__2__BIE EQU CYREG_PRT4_BIE +SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_In__2__BYP EQU CYREG_PRT4_BYP +SCSI_In__2__CTL EQU CYREG_PRT4_CTL +SCSI_In__2__DM0 EQU CYREG_PRT4_DM0 +SCSI_In__2__DM1 EQU CYREG_PRT4_DM1 +SCSI_In__2__DM2 EQU CYREG_PRT4_DM2 +SCSI_In__2__DR EQU CYREG_PRT4_DR +SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN SCSI_In__2__MASK EQU 0x04 -SCSI_In__2__PC EQU CYREG_PRT6_PC2 -SCSI_In__2__PORT EQU 6 -SCSI_In__2__PRT EQU CYREG_PRT6_PRT -SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__2__PS EQU CYREG_PRT6_PS +SCSI_In__2__PC EQU CYREG_PRT4_PC2 +SCSI_In__2__PORT EQU 4 +SCSI_In__2__PRT EQU CYREG_PRT4_PRT +SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_In__2__PS EQU CYREG_PRT4_PS SCSI_In__2__SHIFT EQU 2 -SCSI_In__2__SLW EQU CYREG_PRT6_SLW -SCSI_In__3__AG EQU CYREG_PRT4_AG -SCSI_In__3__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__3__BIE EQU CYREG_PRT4_BIE -SCSI_In__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__3__BYP EQU CYREG_PRT4_BYP -SCSI_In__3__CTL EQU CYREG_PRT4_CTL -SCSI_In__3__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__3__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__3__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__3__DR EQU CYREG_PRT4_DR -SCSI_In__3__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__3__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__3__MASK EQU 0x40 -SCSI_In__3__PC EQU CYREG_PRT4_PC6 -SCSI_In__3__PORT EQU 4 -SCSI_In__3__PRT EQU CYREG_PRT4_PRT -SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__3__PS EQU CYREG_PRT4_PS -SCSI_In__3__SHIFT EQU 6 -SCSI_In__3__SLW EQU CYREG_PRT4_SLW -SCSI_In__4__AG EQU CYREG_PRT4_AG -SCSI_In__4__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__4__BIE EQU CYREG_PRT4_BIE -SCSI_In__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__4__BYP EQU CYREG_PRT4_BYP -SCSI_In__4__CTL EQU CYREG_PRT4_CTL -SCSI_In__4__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__4__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__4__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__4__DR EQU CYREG_PRT4_DR -SCSI_In__4__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__4__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__4__MASK EQU 0x08 -SCSI_In__4__PC EQU CYREG_PRT4_PC3 -SCSI_In__4__PORT EQU 4 -SCSI_In__4__PRT EQU CYREG_PRT4_PRT -SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__4__PS EQU CYREG_PRT4_PS -SCSI_In__4__SHIFT EQU 3 -SCSI_In__4__SLW EQU CYREG_PRT4_SLW -SCSI_In__5__AG EQU CYREG_PRT4_AG -SCSI_In__5__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__5__BIE EQU CYREG_PRT4_BIE -SCSI_In__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__5__BYP EQU CYREG_PRT4_BYP -SCSI_In__5__CTL EQU CYREG_PRT4_CTL -SCSI_In__5__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__5__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__5__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__5__DR EQU CYREG_PRT4_DR -SCSI_In__5__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__5__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__5__MASK EQU 0x04 -SCSI_In__5__PC EQU CYREG_PRT4_PC2 -SCSI_In__5__PORT EQU 4 -SCSI_In__5__PRT EQU CYREG_PRT4_PRT -SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__5__PS EQU CYREG_PRT4_PS -SCSI_In__5__SHIFT EQU 2 -SCSI_In__5__SLW EQU CYREG_PRT4_SLW -SCSI_In__6__AG EQU CYREG_PRT0_AG -SCSI_In__6__AMUX EQU CYREG_PRT0_AMUX -SCSI_In__6__BIE EQU CYREG_PRT0_BIE -SCSI_In__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_In__6__BYP EQU CYREG_PRT0_BYP -SCSI_In__6__CTL EQU CYREG_PRT0_CTL -SCSI_In__6__DM0 EQU CYREG_PRT0_DM0 -SCSI_In__6__DM1 EQU CYREG_PRT0_DM1 -SCSI_In__6__DM2 EQU CYREG_PRT0_DM2 -SCSI_In__6__DR EQU CYREG_PRT0_DR -SCSI_In__6__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_In__6__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_In__6__MASK EQU 0x20 -SCSI_In__6__PC EQU CYREG_PRT0_PC5 -SCSI_In__6__PORT EQU 0 -SCSI_In__6__PRT EQU CYREG_PRT0_PRT -SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_In__6__PS EQU CYREG_PRT0_PS -SCSI_In__6__SHIFT EQU 5 -SCSI_In__6__SLW EQU CYREG_PRT0_SLW -SCSI_In__7__AG EQU CYREG_PRT0_AG -SCSI_In__7__AMUX EQU CYREG_PRT0_AMUX -SCSI_In__7__BIE EQU CYREG_PRT0_BIE -SCSI_In__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK -SCSI_In__7__BYP EQU CYREG_PRT0_BYP -SCSI_In__7__CTL EQU CYREG_PRT0_CTL -SCSI_In__7__DM0 EQU CYREG_PRT0_DM0 -SCSI_In__7__DM1 EQU CYREG_PRT0_DM1 -SCSI_In__7__DM2 EQU CYREG_PRT0_DM2 -SCSI_In__7__DR EQU CYREG_PRT0_DR -SCSI_In__7__INP_DIS EQU CYREG_PRT0_INP_DIS -SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG -SCSI_In__7__LCD_EN EQU CYREG_PRT0_LCD_EN -SCSI_In__7__MASK EQU 0x10 -SCSI_In__7__PC EQU CYREG_PRT0_PC4 -SCSI_In__7__PORT EQU 0 -SCSI_In__7__PRT EQU CYREG_PRT0_PRT -SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL -SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN -SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 -SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 -SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 -SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 -SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT -SCSI_In__7__PS EQU CYREG_PRT0_PS -SCSI_In__7__SHIFT EQU 4 -SCSI_In__7__SLW EQU CYREG_PRT0_SLW -SCSI_In__ACK__AG EQU CYREG_PRT6_AG -SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE -SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP -SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL -SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__ACK__DR EQU CYREG_PRT6_DR -SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__ACK__MASK EQU 0x04 -SCSI_In__ACK__PC EQU CYREG_PRT6_PC2 -SCSI_In__ACK__PORT EQU 6 -SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT -SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__ACK__PS EQU CYREG_PRT6_PS -SCSI_In__ACK__SHIFT EQU 2 -SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW -SCSI_In__BSY__AG EQU CYREG_PRT6_AG -SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX -SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE -SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK -SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP -SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL -SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0 -SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1 -SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2 -SCSI_In__BSY__DR EQU CYREG_PRT6_DR -SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS -SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG -SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN -SCSI_In__BSY__MASK EQU 0x08 -SCSI_In__BSY__PC EQU CYREG_PRT6_PC3 -SCSI_In__BSY__PORT EQU 6 -SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT -SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL -SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN -SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 -SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 -SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 -SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 -SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT -SCSI_In__BSY__PS EQU CYREG_PRT6_PS -SCSI_In__BSY__SHIFT EQU 3 -SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW +SCSI_In__2__SLW EQU CYREG_PRT4_SLW +SCSI_In__3__AG EQU CYREG_PRT0_AG +SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__3__BIE EQU CYREG_PRT0_BIE +SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__3__BYP EQU CYREG_PRT0_BYP +SCSI_In__3__CTL EQU CYREG_PRT0_CTL +SCSI_In__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__3__DR EQU CYREG_PRT0_DR +SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__3__MASK EQU 0x20 +SCSI_In__3__PC EQU CYREG_PRT0_PC5 +SCSI_In__3__PORT EQU 0 +SCSI_In__3__PRT EQU CYREG_PRT0_PRT +SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__3__PS EQU CYREG_PRT0_PS +SCSI_In__3__SHIFT EQU 5 +SCSI_In__3__SLW EQU CYREG_PRT0_SLW +SCSI_In__4__AG EQU CYREG_PRT0_AG +SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX +SCSI_In__4__BIE EQU CYREG_PRT0_BIE +SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_In__4__BYP EQU CYREG_PRT0_BYP +SCSI_In__4__CTL EQU CYREG_PRT0_CTL +SCSI_In__4__DM0 EQU CYREG_PRT0_DM0 +SCSI_In__4__DM1 EQU CYREG_PRT0_DM1 +SCSI_In__4__DM2 EQU CYREG_PRT0_DM2 +SCSI_In__4__DR EQU CYREG_PRT0_DR +SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_In__4__MASK EQU 0x10 +SCSI_In__4__PC EQU CYREG_PRT0_PC4 +SCSI_In__4__PORT EQU 0 +SCSI_In__4__PRT EQU CYREG_PRT0_PRT +SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_In__4__PS EQU CYREG_PRT0_PS +SCSI_In__4__SHIFT EQU 4 +SCSI_In__4__SLW EQU CYREG_PRT0_SLW SCSI_In__CD__AG EQU CYREG_PRT4_AG SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX SCSI_In__CD__BIE EQU CYREG_PRT4_BIE @@ -2559,33 +2629,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT SCSI_In__REQ__PS EQU CYREG_PRT0_PS SCSI_In__REQ__SHIFT EQU 5 SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW -SCSI_In__SEL__AG EQU CYREG_PRT4_AG -SCSI_In__SEL__AMUX EQU CYREG_PRT4_AMUX -SCSI_In__SEL__BIE EQU CYREG_PRT4_BIE -SCSI_In__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK -SCSI_In__SEL__BYP EQU CYREG_PRT4_BYP -SCSI_In__SEL__CTL EQU CYREG_PRT4_CTL -SCSI_In__SEL__DM0 EQU CYREG_PRT4_DM0 -SCSI_In__SEL__DM1 EQU CYREG_PRT4_DM1 -SCSI_In__SEL__DM2 EQU CYREG_PRT4_DM2 -SCSI_In__SEL__DR EQU CYREG_PRT4_DR -SCSI_In__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS -SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG -SCSI_In__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN -SCSI_In__SEL__MASK EQU 0x08 -SCSI_In__SEL__PC EQU CYREG_PRT4_PC3 -SCSI_In__SEL__PORT EQU 4 -SCSI_In__SEL__PRT EQU CYREG_PRT4_PRT -SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL -SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN -SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 -SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 -SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 -SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 -SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT -SCSI_In__SEL__PS EQU CYREG_PRT4_PS -SCSI_In__SEL__SHIFT EQU 3 -SCSI_In__SEL__SLW EQU CYREG_PRT4_SLW ; SD_MISO SD_MISO__0__MASK EQU 0x02 @@ -2886,7 +2929,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x1000 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000001E +CYDEV_INTR_RISING EQU 0x0000003E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 0698be1..44d9993 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -21,10 +21,7 @@ #include #include #include -#include -#include #include -#include #include #include #include @@ -38,10 +35,7 @@ #include #include #include -#include -#include -#include -#include +#include #include #include #include @@ -56,19 +50,23 @@ #include #include #include -#include -#include -#include -#include -#include #include #include #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #include -#include #include #include #include diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml index 5c51d5c..61c4816 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -99,12 +99,6 @@ .\Generated_Source\PSoC5\SD_MOSI_aliases.h .\Generated_Source\PSoC5\SD_MOSI.c .\Generated_Source\PSoC5\SD_MOSI.h - .\Generated_Source\PSoC5\SCSI_RST_aliases.h - .\Generated_Source\PSoC5\SCSI_RST.c - .\Generated_Source\PSoC5\SCSI_RST.h - .\Generated_Source\PSoC5\SCSI_ATN_aliases.h - .\Generated_Source\PSoC5\SCSI_ATN.c - .\Generated_Source\PSoC5\SCSI_ATN.h .\Generated_Source\PSoC5\SCSI_RST_ISR.c .\Generated_Source\PSoC5\SCSI_RST_ISR.h .\Generated_Source\PSoC5\LED1_aliases.h @@ -203,6 +197,9 @@ .\Generated_Source\PSoC5\SCSI_Parity_Error.h .\Generated_Source\PSoC5\SCSI_CLK.c .\Generated_Source\PSoC5\SCSI_CLK.h + .\Generated_Source\PSoC5\SCSI_Noise_aliases.h + .\Generated_Source\PSoC5\SCSI_Filtered.c + .\Generated_Source\PSoC5\SCSI_Filtered.h .\Generated_Source\PSoC5\prebuild.bat .\Generated_Source\PSoC5\postbuild.bat .\Generated_Source\PSoC5\CyElfTool.exe diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx index cf7982a..bf53210 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,10 +1,161 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -12,7 +163,6 @@ - @@ -93,126 +243,12 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + - - - - - - \ No newline at end of file diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr index 42fe714..496f18d 100755 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit index 41419c0..39d0086 100644 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj index 27247b2..9183ed8 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -840,14 +840,14 @@ - + - + @@ -856,7 +856,7 @@ - + @@ -865,7 +865,7 @@ - + @@ -879,14 +879,14 @@ - + - + @@ -895,7 +895,7 @@ - + @@ -904,7 +904,7 @@ - + @@ -2145,6 +2145,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd index 79140a9..708727c 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd @@ -7,159 +7,218 @@ 32 - USBFS - USBFS - 0x40004394 + SCSI_Out_Ctl + No description available + 0x4000657B 0 - 0x1D0A + 0x1 registers - USBFS_PM_USB_CR0 - USB Power Mode Control Register 0 + SCSI_Out_Ctl_CONTROL_REG + No description available 0x0 8 read-write 0 0 - - - fsusbio_ref_en - No description available - 0 - 0 - read-write - - - fsusbio_pd_n - No description available - 1 - 1 - read-write - - - fsusbio_pd_pullup_n - No description available - 2 - 2 - read-write - - - - - USBFS_PM_ACT_CFG - Active Power Mode Configuration Register - 0x11 - 8 - read-write - 0 - 0 + + + + SCSI_Out_Bits + No description available + 0x4000647D + + 0 + 0x1 + registers + + - USBFS_PM_STBY_CFG - Standby Power Mode Configuration Register - 0x21 + SCSI_Out_Bits_CONTROL_REG + No description available + 0x0 8 read-write 0 0 + + + + Debug_Timer + No description available + 0x400043A3 + + 0 + 0xB64 + registers + + - USBFS_PRT_PS - Port Pin State Register - 0xE5D + Debug_Timer_GLOBAL_ENABLE + PM.ACT.CFG + 0x0 8 read-write 0 0 - PinState_DP - No description available - 6 - 6 - read-only - - - PinState_DM - No description available - 7 - 7 - read-only + en_timer + Enable timer/counters. + 0 + 3 + read-write - USBFS_PRT_DM0 - Port Drive Mode Register - 0xE5E + Debug_Timer_CONTROL + TMRx.CFG0 + 0xB5D 8 read-write 0 0 - DriveMode_DP - No description available - 6 - 6 + EN + Enables timer/comparator. + 0 + 0 read-write - DriveMode_DM - No description available - 7 - 7 + MODE + Mode. (0 = Timer; 1 = Comparator) + 1 + 1 + read-write + + + Timer + Timer mode. CNT/CMP register holds timer count value. + 0 + + + Comparator + Comparator mode. CNT/CMP register holds comparator threshold value. + 1 + + + + + ONESHOT + Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. + 2 + 2 read-write - - - - USBFS_PRT_DM1 - Port Drive Mode Register - 0xE5F - 8 - read-write - 0 - 0 - - PullUp_en_DP - No description available - 6 - 6 + CMP_BUFF + Buffer compare register. Compare register updates only on timer terminal count. + 3 + 3 read-write - PullUp_en_DM - No description available - 7 + INV + Invert sense of TIMEREN signal + 4 + 4 + read-write + + + DB + Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. + 5 + 5 + read-write + + + Timer + CMP and TC are output. + 0 + + + Deadband + PHI1 (instead of CMP) and PHI2 (instead of TC) are output. + 1 + + + + + DEADBAND_PERIOD + Deadband Period + 6 7 read-write - USBFS_PRT_INP_DIS - Input buffer disable override - 0xE64 + Debug_Timer_CONTROL2 + TMRx.CFG1 + 0xB5E 8 read-write 0 0 - seinput_dis_dp - No description available - 6 + IRQ_SEL + Irq selection. (0 = raw interrupts; 1 = status register interrupts) + 0 + 0 + read-write + + + FTC + First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + 1 + 1 + read-write + + + Disable_FTC + Disable the single cycle pulse, which signifies the timer is starting. + 0 + + + Enable_FTC + Enable the single cycle pulse, which signifies the timer is starting. + 1 + + + + + DCOR + Disable Clear on Read (DCOR) of Status Register SR0. + 2 + 2 + read-write + + + DBMODE + Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + 3 + 3 + read-write + + + CLK_BUS_EN_SEL + Digital Global Clock selection. + 4 6 read-write - seinput_dis_dm - No description available + BUS_CLK_SEL + Bus Clock selection. 7 7 read-write @@ -167,333 +226,279 @@ - USBFS_EP0_DR0 - bmRequestType - 0x1C6C - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR1 - bRequest - 0x1C6D - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR2 - wValueLo - 0x1C6E - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR3 - wValueHi - 0x1C6F - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR4 - wIndexLo - 0x1C70 - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR5 - wIndexHi - 0x1C71 - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR6 - lengthLo - 0x1C72 - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR7 - lengthHi - 0x1C73 - 8 - read-write - 0 - 0 - - - USBFS_CR0 - USB Control Register 0 - 0x1C74 - 8 - read-write - 0 - 0 - - - device_address - No description available - 6 - 0 - read-only - - - usb_enable - No description available - 7 - 7 - read-write - - - - - USBFS_CR1 - USB Control Register 1 - 0x1C75 + Debug_Timer_CONTROL3_ + TMRx.CFG2 + 0xB5F 8 read-write 0 0 - reg_enable - No description available + TMR_CFG + Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ 0 - 0 - read-write - - - enable_lock - No description available - 1 1 read-write + + + Continuous + Timer runs while EN bit of CFG0 register is set to '1'. + 0 + + + Pulsewidth + Timer runs from positive to negative edge of TIMEREN. + 1 + + + Period + Timer runs from positive to positive edge of TIMEREN. + 2 + + + Irq + Timer runs until IRQ. + 3 + + - bus_activity - No description available + COD + Clear On Disable (COD). Clears or gates outputs to zero. 2 2 read-write - trim_offset_msb - No description available + ROD + Reset On Disable (ROD). Resets internal state of output logic 3 3 read-write - - - - USBFS_SIE_EP1_CR0 - The Endpoint1 Control Register - 0x1C7A - 8 - read-write - 0 - 0 - - - USBFS_USBIO_CR0 - USBIO Control Register 0 - 0x1C7C - 8 - read-write - 0 - 0 - - - rd - No description available - 0 - 0 - read-only - - - td - No description available - 5 - 5 - read-write - - - tse0 - No description available - 6 - 6 - read-write - - - ten - No description available - 7 - 7 - read-write - - - - - USBFS_USBIO_CR1 - USBIO Control Register 1 - 0x1C7E - 8 - read-write - 0 - 0 - - - dmo - No description available - 0 - 0 - read-only - - - dpo - No description available - 1 - 1 - read-only - - - usbpuen - No description available - 2 - 2 - read-write - - iomode - No description available - 5 - 5 - read-write - - - - - USBFS_SIE_EP2_CR0 - The Endpoint2 Control Register - 0x1C8A - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP3_CR0 - The Endpoint3 Control Register - 0x1C9A - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP4_CR0 - The Endpoint4 Control Register - 0x1CAA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP5_CR0 - The Endpoint5 Control Register - 0x1CBA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP6_CR0 - The Endpoint6 Control Register - 0x1CCA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP7_CR0 - The Endpoint7 Control Register - 0x1CDA - 8 - read-write - 0 - 0 + CMP_CFG + Comparator configurations + 4 + 6 + read-write + + + Equal + Compare Equal + 0 + + + Less_than + Compare Less Than + 1 + + + Less_than_or_equal + Compare Less Than or Equal . + 2 + + + Greater + Compare Greater Than . + 3 + + + Greater_than_or_equal + Compare Greater Than or Equal + 4 + + + + + HW_EN + When set Timer Enable controls counting. + 7 + 7 + read-write + + - USBFS_SIE_EP8_CR0 - The Endpoint8 Control Register - 0x1CEA - 8 + Debug_Timer_PERIOD + TMRx.PER0 - Assigned Period + 0xB61 + 16 read-write 0 0 - USBFS_BUF_SIZE - Dedicated Endpoint Buffer Size Register - 0x1CF8 - 8 + Debug_Timer_COUNTER + TMRx.CNT_CMP0 - Current Down Counter Value + 0xB63 + 16 read-write 0 0 + + + + SCSI_Parity_Error + No description available + 0x4000656B + + 0 + 0x31 + registers + + - USBFS_EP_ACTIVE - Endpoint Active Indication Register - 0x1CFA + SCSI_Parity_Error_STATUS_REG + No description available + 0x0 8 read-write 0 0 - USBFS_EP_TYPE - Endpoint Type (IN/OUT) Indication - 0x1CFB + SCSI_Parity_Error_MASK_REG + No description available + 0x20 8 read-write 0 0 - USBFS_USB_CLK_EN - USB Block Clock Enable Register - 0x1D09 + SCSI_Parity_Error_STATUS_AUX_CTL_REG + No description available + 0x30 8 read-write 0 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + - SCSI_Parity_Error + SCSI_Filtered No description available - 0x40006462 + 0x4000646D 0 0x31 @@ -501,7 +506,7 @@ - SCSI_Parity_Error_STATUS_REG + SCSI_Filtered_STATUS_REG No description available 0x0 8 @@ -510,7 +515,7 @@ 0 - SCSI_Parity_Error_MASK_REG + SCSI_Filtered_MASK_REG No description available 0x20 8 @@ -519,7 +524,7 @@ 0 - SCSI_Parity_Error_STATUS_AUX_CTL_REG + SCSI_Filtered_STATUS_AUX_CTL_REG No description available 0x30 8 @@ -646,9 +651,9 @@ - SCSI_Out_Bits + SCSI_CTL_PHASE No description available - 0x4000657B + 0x4000647F 0 0x1 @@ -656,7 +661,7 @@ - SCSI_Out_Bits_CONTROL_REG + SCSI_CTL_PHASE_CONTROL_REG No description available 0x0 8 @@ -667,176 +672,343 @@ - Debug_Timer - No description available - 0x400043A3 + USBFS + USBFS + 0x40004394 0 - 0xB64 + 0x1D0A registers - Debug_Timer_GLOBAL_ENABLE - PM.ACT.CFG - 0x0 + USBFS_PM_USB_CR0 + USB Power Mode Control Register 0 + 0x0 + 8 + read-write + 0 + 0 + + + fsusbio_ref_en + No description available + 0 + 0 + read-write + + + fsusbio_pd_n + No description available + 1 + 1 + read-write + + + fsusbio_pd_pullup_n + No description available + 2 + 2 + read-write + + + + + USBFS_PM_ACT_CFG + Active Power Mode Configuration Register + 0x11 + 8 + read-write + 0 + 0 + + + USBFS_PM_STBY_CFG + Standby Power Mode Configuration Register + 0x21 + 8 + read-write + 0 + 0 + + + USBFS_PRT_PS + Port Pin State Register + 0xE5D 8 read-write 0 0 - en_timer - Enable timer/counters. - 0 - 3 - read-write + PinState_DP + No description available + 6 + 6 + read-only + + + PinState_DM + No description available + 7 + 7 + read-only - Debug_Timer_CONTROL - TMRx.CFG0 - 0xB5D + USBFS_PRT_DM0 + Port Drive Mode Register + 0xE5E 8 read-write 0 0 - EN - Enables timer/comparator. - 0 - 0 + DriveMode_DP + No description available + 6 + 6 read-write - MODE - Mode. (0 = Timer; 1 = Comparator) - 1 - 1 + DriveMode_DM + No description available + 7 + 7 read-write - - - Timer - Timer mode. CNT/CMP register holds timer count value. - 0 - - - Comparator - Comparator mode. CNT/CMP register holds comparator threshold value. - 1 - - + + + + USBFS_PRT_DM1 + Port Drive Mode Register + 0xE5F + 8 + read-write + 0 + 0 + - ONESHOT - Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. - 2 - 2 + PullUp_en_DP + No description available + 6 + 6 read-write - CMP_BUFF - Buffer compare register. Compare register updates only on timer terminal count. - 3 - 3 + PullUp_en_DM + No description available + 7 + 7 read-write + + + + USBFS_PRT_INP_DIS + Input buffer disable override + 0xE64 + 8 + read-write + 0 + 0 + - INV - Invert sense of TIMEREN signal - 4 - 4 + seinput_dis_dp + No description available + 6 + 6 read-write - DB - Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. - 5 - 5 + seinput_dis_dm + No description available + 7 + 7 read-write - - - Timer - CMP and TC are output. - 0 - - - Deadband - PHI1 (instead of CMP) and PHI2 (instead of TC) are output. - 1 - - + + + + USBFS_EP0_DR0 + bmRequestType + 0x1C6C + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR1 + bRequest + 0x1C6D + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR2 + wValueLo + 0x1C6E + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR3 + wValueHi + 0x1C6F + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR4 + wIndexLo + 0x1C70 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR5 + wIndexHi + 0x1C71 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR6 + lengthLo + 0x1C72 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR7 + lengthHi + 0x1C73 + 8 + read-write + 0 + 0 + + + USBFS_CR0 + USB Control Register 0 + 0x1C74 + 8 + read-write + 0 + 0 + - DEADBAND_PERIOD - Deadband Period + device_address + No description available 6 + 0 + read-only + + + usb_enable + No description available + 7 7 read-write - Debug_Timer_CONTROL2 - TMRx.CFG1 - 0xB5E + USBFS_CR1 + USB Control Register 1 + 0x1C75 8 read-write 0 0 - IRQ_SEL - Irq selection. (0 = raw interrupts; 1 = status register interrupts) + reg_enable + No description available 0 0 read-write - FTC - First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + enable_lock + No description available 1 1 read-write - - - Disable_FTC - Disable the single cycle pulse, which signifies the timer is starting. - 0 - - - Enable_FTC - Enable the single cycle pulse, which signifies the timer is starting. - 1 - - - DCOR - Disable Clear on Read (DCOR) of Status Register SR0. + bus_activity + No description available 2 2 read-write - DBMODE - Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + trim_offset_msb + No description available 3 3 read-write + + + + USBFS_SIE_EP1_CR0 + The Endpoint1 Control Register + 0x1C7A + 8 + read-write + 0 + 0 + + + USBFS_USBIO_CR0 + USBIO Control Register 0 + 0x1C7C + 8 + read-write + 0 + 0 + - CLK_BUS_EN_SEL - Digital Global Clock selection. - 4 + rd + No description available + 0 + 0 + read-only + + + td + No description available + 5 + 5 + read-write + + + tse0 + No description available + 6 6 read-write - BUS_CLK_SEL - Bus Clock selection. + ten + No description available 7 7 read-write @@ -844,155 +1016,138 @@ - Debug_Timer_CONTROL3_ - TMRx.CFG2 - 0xB5F + USBFS_USBIO_CR1 + USBIO Control Register 1 + 0x1C7E 8 read-write 0 0 - TMR_CFG - Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ + dmo + No description available 0 + 0 + read-only + + + dpo + No description available + 1 1 - read-write - - - Continuous - Timer runs while EN bit of CFG0 register is set to '1'. - 0 - - - Pulsewidth - Timer runs from positive to negative edge of TIMEREN. - 1 - - - Period - Timer runs from positive to positive edge of TIMEREN. - 2 - - - Irq - Timer runs until IRQ. - 3 - - + read-only - COD - Clear On Disable (COD). Clears or gates outputs to zero. + usbpuen + No description available 2 2 read-write - ROD - Reset On Disable (ROD). Resets internal state of output logic - 3 - 3 - read-write - - - CMP_CFG - Comparator configurations - 4 - 6 - read-write - - - Equal - Compare Equal - 0 - - - Less_than - Compare Less Than - 1 - - - Less_than_or_equal - Compare Less Than or Equal . - 2 - - - Greater - Compare Greater Than . - 3 - - - Greater_than_or_equal - Compare Greater Than or Equal - 4 - - - - - HW_EN - When set Timer Enable controls counting. - 7 - 7 + iomode + No description available + 5 + 5 read-write - Debug_Timer_PERIOD - TMRx.PER0 - Assigned Period - 0xB61 - 16 + USBFS_SIE_EP2_CR0 + The Endpoint2 Control Register + 0x1C8A + 8 read-write 0 0 - Debug_Timer_COUNTER - TMRx.CNT_CMP0 - Current Down Counter Value - 0xB63 - 16 + USBFS_SIE_EP3_CR0 + The Endpoint3 Control Register + 0x1C9A + 8 read-write 0 0 - - - - SCSI_Out_Ctl - No description available - 0x40006579 - - 0 - 0x1 - registers - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x0 + USBFS_SIE_EP4_CR0 + The Endpoint4 Control Register + 0x1CAA 8 read-write 0 0 - - - - SCSI_CTL_PHASE - No description available - 0x40006472 - - 0 - 0x1 - registers - - - SCSI_CTL_PHASE_CONTROL_REG - No description available - 0x0 + USBFS_SIE_EP5_CR0 + The Endpoint5 Control Register + 0x1CBA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP6_CR0 + The Endpoint6 Control Register + 0x1CCA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP7_CR0 + The Endpoint7 Control Register + 0x1CDA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP8_CR0 + The Endpoint8 Control Register + 0x1CEA + 8 + read-write + 0 + 0 + + + USBFS_BUF_SIZE + Dedicated Endpoint Buffer Size Register + 0x1CF8 + 8 + read-write + 0 + 0 + + + USBFS_EP_ACTIVE + Endpoint Active Indication Register + 0x1CFA + 8 + read-write + 0 + 0 + + + USBFS_EP_TYPE + Endpoint Type (IN/OUT) Indication + 0x1CFB + 8 + read-write + 0 + 0 + + + USBFS_USB_CLK_EN + USB Block Clock Enable Register + 0x1D09 8 read-write 0 diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 64952de..ad87ee4 100755 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ