From: Michael McMaster Date: Fri, 30 May 2014 01:09:55 +0000 (+1000) Subject: Use DMA for SCSI and SD card transfers for a massive performance boost. X-Git-Tag: 3.5~8 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=5bcd0c3a18f859e837ef0f9d4236e2bf3a16f77c;p=SCSI2SD.git Use DMA for SCSI and SD card transfers for a massive performance boost. --- diff --git a/CHANGELOG b/CHANGELOG index 9f3b3f0..978feca 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,8 @@ +201404xx 3.5 + - Fixed several performance issues. Transfer rates up to 2.5MB/s are now + possible. + - Implemented the READ BUFFER scsi command for performance testing purposes. + 20140418 3.4 - Critical fix for writes when using non-standard block sizes. - Fix to ensure SCSI phase bits are set atomically. diff --git a/readme.txt b/readme.txt index b93b087..a57e451 100644 --- a/readme.txt +++ b/readme.txt @@ -45,7 +45,7 @@ Performance As currently implemented: -Sequential read: 930kb/sec Sequential write: 900kb/sec +Sequential read: 2.5MB/s Sequential write: 900kb/sec Tested with a 16GB class 10 SD card, via the commands: diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c new file mode 100644 index 0000000..f3a7008 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SCSI_RX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_RX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */ + SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */ + SCSI_RX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start +* or SCSI_RX_DMA_COMPLETE_StartEx will override any effect this method +* would have had. This method should only be called after +* SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_RX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_SetPending(void) +{ + *SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_ClearPending(void) +{ + *SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h new file mode 100644 index 0000000..1d9e146 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_RX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H) +#define CY_ISR_SCSI_RX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_RX_DMA_COMPLETE_Start(void); +void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address); +void SCSI_RX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt); + +void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void); + +void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void); + +void SCSI_RX_DMA_COMPLETE_Enable(void); +uint8 SCSI_RX_DMA_COMPLETE_GetState(void); +void SCSI_RX_DMA_COMPLETE_Disable(void); + +void SCSI_RX_DMA_COMPLETE_SetPending(void); +void SCSI_RX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */ +#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */ +#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */ +#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c new file mode 100644 index 0000000..6bdb2ea --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SCSI_RX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SCSI_RX_DMA__DRQ_CTL_REG +* +* +* SCSI_RX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SCSI_RX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SCSI_RX_DMA__PRIORITY +* +* True if SCSI_RX_DMA_TERMIN_SEL is used. +* SCSI_RX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SCSI_RX_DMA__TERMIN_SEL +* +* +* True if SCSI_RX_DMA_TERMOUT0_SEL is used. +* SCSI_RX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SCSI_RX_DMA__TERMOUT0_SEL +* +* +* True if SCSI_RX_DMA_TERMOUT1_SEL is used. +* SCSI_RX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SCSI_RX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SCSI_RX_DMA dma channel */ +uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SCSI_RX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SCSI_RX_DMA__TERMOUT0_SEL, + (uint8)SCSI_RX_DMA__TERMOUT1_SEL, + (uint8)SCSI_RX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY); + + return SCSI_RX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SCSI_RX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SCSI_RX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SCSI_RX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h new file mode 100644 index 0000000..4030614 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SCSI_RX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__) +#define CY_DMA_SCSI_RX_DMA_DMA_H__ + + + +#include +#include + +#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SCSI_RX_DMA dma channel */ +extern uint8 SCSI_RX_DMA_DmaHandle; + + +uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SCSI_RX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SCSI_RX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_COMPLETE.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_COMPLETE.c new file mode 100644 index 0000000..401086b --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_COMPLETE.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SCSI_TX_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SCSI_TX_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_TX_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_TX_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_TX_COMPLETE Interrupt. */ + SCSI_TX_COMPLETE_SetVector(&SCSI_TX_COMPLETE_Interrupt); + + /* Set the priority. */ + SCSI_TX_COMPLETE_SetPriority((uint8)SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_TX_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_TX_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_TX_COMPLETE Interrupt. */ + SCSI_TX_COMPLETE_SetVector(address); + + /* Set the priority. */ + SCSI_TX_COMPLETE_SetPriority((uint8)SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_TX_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_TX_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_TX_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_TX_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_TX_COMPLETE_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SCSI_TX_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_TX_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_TX_COMPLETE_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_TX_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SCSI_TX_COMPLETE_Start +* or SCSI_TX_COMPLETE_StartEx will override any effect this method +* would have had. This method should only be called after +* SCSI_TX_COMPLETE_Start or SCSI_TX_COMPLETE_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_SetPriority(uint8 priority) +{ + *SCSI_TX_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SCSI_TX_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_TX_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_TX_COMPLETE_INTC_SET_EN = SCSI_TX_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_TX_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_TX_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_TX_COMPLETE_INTC_CLR_EN = SCSI_TX_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_SetPending(void) +{ + *SCSI_TX_COMPLETE_INTC_SET_PD = SCSI_TX_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_COMPLETE_ClearPending(void) +{ + *SCSI_TX_COMPLETE_INTC_CLR_PD = SCSI_TX_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_COMPLETE.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_COMPLETE.h new file mode 100644 index 0000000..ea4d934 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_TX_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_TX_COMPLETE_H) +#define CY_ISR_SCSI_TX_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_TX_COMPLETE_Start(void); +void SCSI_TX_COMPLETE_StartEx(cyisraddress address); +void SCSI_TX_COMPLETE_Stop(void); + +CY_ISR_PROTO(SCSI_TX_COMPLETE_Interrupt); + +void SCSI_TX_COMPLETE_SetVector(cyisraddress address); +cyisraddress SCSI_TX_COMPLETE_GetVector(void); + +void SCSI_TX_COMPLETE_SetPriority(uint8 priority); +uint8 SCSI_TX_COMPLETE_GetPriority(void); + +void SCSI_TX_COMPLETE_Enable(void); +uint8 SCSI_TX_COMPLETE_GetState(void); +void SCSI_TX_COMPLETE_Disable(void); + +void SCSI_TX_COMPLETE_SetPending(void); +void SCSI_TX_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_COMPLETE ISR. */ +#define SCSI_TX_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_COMPLETE__INTC_VECT) + +/* Address of the SCSI_TX_COMPLETE ISR priority. */ +#define SCSI_TX_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SCSI_TX_COMPLETE interrupt. */ +#define SCSI_TX_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_COMPLETE interrupt. */ +#define SCSI_TX_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_COMPLETE interrupt. */ +#define SCSI_TX_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_COMPLETE interrupt state to pending. */ +#define SCSI_TX_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_COMPLETE interrupt. */ +#define SCSI_TX_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_TX_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c new file mode 100644 index 0000000..a9c001e --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SCSI_TX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_TX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */ + SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */ + SCSI_TX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start +* or SCSI_TX_DMA_COMPLETE_StartEx will override any effect this method +* would have had. This method should only be called after +* SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_TX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_SetPending(void) +{ + *SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_ClearPending(void) +{ + *SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h new file mode 100644 index 0000000..5efbf9b --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_TX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H) +#define CY_ISR_SCSI_TX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_TX_DMA_COMPLETE_Start(void); +void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address); +void SCSI_TX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt); + +void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void); + +void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void); + +void SCSI_TX_DMA_COMPLETE_Enable(void); +uint8 SCSI_TX_DMA_COMPLETE_GetState(void); +void SCSI_TX_DMA_COMPLETE_Disable(void); + +void SCSI_TX_DMA_COMPLETE_SetPending(void); +void SCSI_TX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */ +#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */ +#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */ +#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c new file mode 100644 index 0000000..83419f7 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SCSI_TX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SCSI_TX_DMA__DRQ_CTL_REG +* +* +* SCSI_TX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SCSI_TX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SCSI_TX_DMA__PRIORITY +* +* True if SCSI_TX_DMA_TERMIN_SEL is used. +* SCSI_TX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SCSI_TX_DMA__TERMIN_SEL +* +* +* True if SCSI_TX_DMA_TERMOUT0_SEL is used. +* SCSI_TX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SCSI_TX_DMA__TERMOUT0_SEL +* +* +* True if SCSI_TX_DMA_TERMOUT1_SEL is used. +* SCSI_TX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SCSI_TX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SCSI_TX_DMA dma channel */ +uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SCSI_TX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SCSI_TX_DMA__TERMOUT0_SEL, + (uint8)SCSI_TX_DMA__TERMOUT1_SEL, + (uint8)SCSI_TX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY); + + return SCSI_TX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SCSI_TX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SCSI_TX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SCSI_TX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h new file mode 100644 index 0000000..c0a1b00 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SCSI_TX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__) +#define CY_DMA_SCSI_TX_DMA_DMA_H__ + + + +#include +#include + +#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SCSI_TX_DMA dma channel */ +extern uint8 SCSI_TX_DMA_DmaHandle; + + +uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SCSI_TX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SCSI_TX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h old mode 100755 new mode 100644 index bb19eba..124adc7 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -147,7 +147,7 @@ extern uint8 SDCard_initVar; #define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT)) #define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) -#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \ +#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \ SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) #define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT)) #define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT)) @@ -165,7 +165,7 @@ extern uint8 SDCard_initVar; #define SDCard_INT_ON_RX_FULL ((uint8) (0u << \ SDCard_STS_RX_FIFO_FULL_SHIFT)) -#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ +#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \ SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) #define SDCard_INT_ON_RX_OVER ((uint8) (0u << \ SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c deleted file mode 100755 index 6553ced..0000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c +++ /dev/null @@ -1,63 +0,0 @@ -/******************************************************************************* -* File Name: SD_Clk_Ctl.c -* Version 1.70 -* -* Description: -* This file contains API to enable firmware control of a Control Register. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include "SD_Clk_Ctl.h" - -#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ - -/******************************************************************************* -* Function Name: SD_Clk_Ctl_Write -******************************************************************************** -* -* Summary: -* Write a byte to the Control Register. -* -* Parameters: -* control: The value to be assigned to the Control Register. -* -* Return: -* None. -* -*******************************************************************************/ -void SD_Clk_Ctl_Write(uint8 control) -{ - SD_Clk_Ctl_Control = control; -} - - -/******************************************************************************* -* Function Name: SD_Clk_Ctl_Read -******************************************************************************** -* -* Summary: -* Reads the current value assigned to the Control Register. -* -* Parameters: -* None. -* -* Return: -* Returns the current value in the Control Register. -* -*******************************************************************************/ -uint8 SD_Clk_Ctl_Read(void) -{ - return SD_Clk_Ctl_Control; -} - -#endif /* End check for removal by optimization */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h deleted file mode 100755 index 7c6d263..0000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h +++ /dev/null @@ -1,42 +0,0 @@ -/******************************************************************************* -* File Name: SD_Clk_Ctl.h -* Version 1.70 -* -* Description: -* This file containts Control Register function prototypes and register defines -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */ -#define CY_CONTROL_REG_SD_Clk_Ctl_H - -#include "cytypes.h" - - -/*************************************** -* Function Prototypes -***************************************/ - -void SD_Clk_Ctl_Write(uint8 control) ; -uint8 SD_Clk_Ctl_Read(void) ; - - -/*************************************** -* Registers -***************************************/ - -/* Control Register */ -#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) -#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) - -#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c deleted file mode 100755 index c6cd4e2..0000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c +++ /dev/null @@ -1,521 +0,0 @@ -/******************************************************************************* -* File Name: SD_Init_Clk.c -* Version 2.10 -* -* Description: -* This file provides the source code to the API for the clock component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#include -#include "SD_Init_Clk.h" - -/* Clock Distribution registers. */ -#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) -#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) -#define BCFG2_MASK (0x80u) -#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) -#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) - -#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) - - -/******************************************************************************* -* Function Name: SD_Init_Clk_Start -******************************************************************************** -* -* Summary: -* Starts the clock. Note that on startup, clocks may be already running if the -* "Start on Reset" option is enabled in the DWR. -* -* Parameters: -* None -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_Start(void) -{ - /* Set the bit to enable the clock. */ - SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK; - SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_Stop -******************************************************************************** -* -* Summary: -* Stops the clock and returns immediately. This API does not require the -* source clock to be running but may return before the hardware is actually -* disabled. If the settings of the clock are changed after calling this -* function, the clock may glitch when it is started. To avoid the clock -* glitch, use the StopBlock function. -* -* Parameters: -* None -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_Stop(void) -{ - /* Clear the bit to disable the clock. */ - SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); - SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); -} - - -#if(CY_PSOC3 || CY_PSOC5LP) - - -/******************************************************************************* -* Function Name: SD_Init_Clk_StopBlock -******************************************************************************** -* -* Summary: -* Stops the clock and waits for the hardware to actually be disabled before -* returning. This ensures that the clock is never truncated (high part of the -* cycle will terminate before the clock is disabled and the API returns). -* Note that the source clock must be running or this API will never return as -* a stopped clock cannot be disabled. -* -* Parameters: -* None -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_StopBlock(void) -{ - if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) - { -#if HAS_CLKDIST_LD_DISABLE - uint16 oldDivider; - - CLK_DIST_LD = 0u; - - /* Clear all the mask bits except ours. */ -#if defined(SD_Init_Clk__CFG3) - CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; - CLK_DIST_DMASK = 0x00u; -#else - CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; - CLK_DIST_AMASK = 0x00u; -#endif /* SD_Init_Clk__CFG3 */ - - /* Clear mask of bus clock. */ - CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); - - oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR); - CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); - CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; - - /* Wait for clock to be disabled */ - while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } -#endif /* HAS_CLKDIST_LD_DISABLE */ - - /* Clear the bit to disable the clock. */ - SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); - SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); - -#if HAS_CLKDIST_LD_DISABLE - /* Clear the disable bit */ - CLK_DIST_LD = 0x00u; - CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider); -#endif /* HAS_CLKDIST_LD_DISABLE */ - } -} -#endif /* (CY_PSOC3 || CY_PSOC5LP) */ - - -/******************************************************************************* -* Function Name: SD_Init_Clk_StandbyPower -******************************************************************************** -* -* Summary: -* Sets whether the clock is active in standby mode. -* -* Parameters: -* state: 0 to disable clock during standby, nonzero to enable. -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_StandbyPower(uint8 state) -{ - if(state == 0u) - { - SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); - } - else - { - SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; - } -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_SetDividerRegister -******************************************************************************** -* -* Summary: -* Modifies the clock divider and, thus, the frequency. When the clock divider -* register is set to zero or changed from zero, the clock will be temporarily -* disabled in order to change the SSS mode bit. If the clock is enabled when -* SetDividerRegister is called, then the source clock must be running. -* -* Parameters: -* clkDivider: Divider register value (0-65,535). This value is NOT the -* divider; the clock hardware divides by clkDivider plus one. For example, -* to divide the clock by 2, this parameter should be set to 1. -* restart: If nonzero, restarts the clock divider: the current clock cycle -* will be truncated and the new divide value will take effect immediately. If -* zero, the new divide value will take effect at the end of the current clock -* cycle. -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) - -{ - uint8 enabled; - - uint8 currSrc = SD_Init_Clk_GetSourceRegister(); - uint16 oldDivider = SD_Init_Clk_GetDividerRegister(); - - if (clkDivider != oldDivider) - { - enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK; - - if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) - { - /* Moving to/from SSS requires correct ordering to prevent halting the clock */ - if (oldDivider == 0u) - { - /* Moving away from SSS, set the divider first so when SSS is cleared we */ - /* don't halt the clock. Using the shadow load isn't required as the */ - /* divider is ignored while SSS is set. */ - CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); - SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); - } - else - { - /* Moving to SSS, set SSS which then ignores the divider and we can set */ - /* it without bothering with the shadow load. */ - SD_Init_Clk_MOD_SRC |= CYCLK_SSS; - CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); - } - } - else - { - - if (enabled != 0u) - { - CLK_DIST_LD = 0x00u; - - /* Clear all the mask bits except ours. */ -#if defined(SD_Init_Clk__CFG3) - CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; - CLK_DIST_DMASK = 0x00u; -#else - CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; - CLK_DIST_AMASK = 0x00u; -#endif /* SD_Init_Clk__CFG3 */ - /* Clear mask of bus clock. */ - CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); - - /* If clock is currently enabled, disable it if async or going from N-to-1*/ - if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) - { -#if HAS_CLKDIST_LD_DISABLE - CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); - CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; - - /* Wait for clock to be disabled */ - while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } -#endif /* HAS_CLKDIST_LD_DISABLE */ - - SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); - -#if HAS_CLKDIST_LD_DISABLE - /* Clear the disable bit */ - CLK_DIST_LD = 0x00u; -#endif /* HAS_CLKDIST_LD_DISABLE */ - } - } - - /* Load divide value. */ - if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) - { - /* If the clock is still enabled, use the shadow registers */ - CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); - - CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); - while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } - } - else - { - /* If the clock is disabled, set the divider directly */ - CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); - SD_Init_Clk_CLKEN |= enabled; - } - } - } -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_GetDividerRegister -******************************************************************************** -* -* Summary: -* Gets the clock divider register value. -* -* Parameters: -* None -* -* Returns: -* Divide value of the clock minus 1. For example, if the clock is set to -* divide by 2, the return value will be 1. -* -*******************************************************************************/ -uint16 SD_Init_Clk_GetDividerRegister(void) -{ - return CY_GET_REG16(SD_Init_Clk_DIV_PTR); -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_SetModeRegister -******************************************************************************** -* -* Summary: -* Sets flags that control the operating mode of the clock. This function only -* changes flags from 0 to 1; flags that are already 1 will remain unchanged. -* To clear flags, use the ClearModeRegister function. The clock must be -* disabled before changing the mode. -* -* Parameters: -* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, -* clkMode should be a set of the following optional bits or'ed together. -* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will -* occur when the divider count reaches half of the divide -* value. -* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock -* is asserted for approximately half of its period. When -* disabled, the output clock is asserted for one period of the -* source clock. -* - CYCLK_SYNC Enable output synchronization to master clock. This should -* be enabled for all synchronous clocks. -* See the Technical Reference Manual for details about setting the mode of -* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) -{ - SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK; -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_ClearModeRegister -******************************************************************************** -* -* Summary: -* Clears flags that control the operating mode of the clock. This function -* only changes flags from 1 to 0; flags that are already 0 will remain -* unchanged. To set flags, use the SetModeRegister function. The clock must be -* disabled before changing the mode. -* -* Parameters: -* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, -* clkMode should be a set of the following optional bits or'ed together. -* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will -* occur when the divider count reaches half of the divide -* value. -* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock -* is asserted for approximately half of its period. When -* disabled, the output clock is asserted for one period of the -* source clock. -* - CYCLK_SYNC Enable output synchronization to master clock. This should -* be enabled for all synchronous clocks. -* See the Technical Reference Manual for details about setting the mode of -* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) -{ - SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK)); -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_GetModeRegister -******************************************************************************** -* -* Summary: -* Gets the clock mode register value. -* -* Parameters: -* None -* -* Returns: -* Bit mask representing the enabled mode bits. See the SetModeRegister and -* ClearModeRegister descriptions for details about the mode bits. -* -*******************************************************************************/ -uint8 SD_Init_Clk_GetModeRegister(void) -{ - return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK); -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_SetSourceRegister -******************************************************************************** -* -* Summary: -* Sets the input source of the clock. The clock must be disabled before -* changing the source. The old and new clock sources must be running. -* -* Parameters: -* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the -* following input sources: -* - CYCLK_SRC_SEL_SYNC_DIG -* - CYCLK_SRC_SEL_IMO -* - CYCLK_SRC_SEL_XTALM -* - CYCLK_SRC_SEL_ILO -* - CYCLK_SRC_SEL_PLL -* - CYCLK_SRC_SEL_XTALK -* - CYCLK_SRC_SEL_DSI_G -* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A -* See the Technical Reference Manual for details on clock sources. -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_SetSourceRegister(uint8 clkSource) -{ - uint16 currDiv = SD_Init_Clk_GetDividerRegister(); - uint8 oldSrc = SD_Init_Clk_GetSourceRegister(); - - if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && - (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) - { - /* Switching to Master and divider is 1, set SSS, which will output master, */ - /* then set the source so we are consistent. */ - SD_Init_Clk_MOD_SRC |= CYCLK_SSS; - SD_Init_Clk_MOD_SRC = - (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; - } - else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && - (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) - { - /* Switching from Master to not and divider is 1, set source, so we don't */ - /* lock when we clear SSS. */ - SD_Init_Clk_MOD_SRC = - (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; - SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); - } - else - { - SD_Init_Clk_MOD_SRC = - (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; - } -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_GetSourceRegister -******************************************************************************** -* -* Summary: -* Gets the input source of the clock. -* -* Parameters: -* None -* -* Returns: -* The input source of the clock. See SetSourceRegister for details. -* -*******************************************************************************/ -uint8 SD_Init_Clk_GetSourceRegister(void) -{ - return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK; -} - - -#if defined(SD_Init_Clk__CFG3) - - -/******************************************************************************* -* Function Name: SD_Init_Clk_SetPhaseRegister -******************************************************************************** -* -* Summary: -* Sets the phase delay of the analog clock. This function is only available -* for analog clocks. The clock must be disabled before changing the phase -* delay to avoid glitches. -* -* Parameters: -* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. -* clkPhase must be from 1 to 11 inclusive. Other values, including 0, -* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 -* produces a 10ns delay. -* -* Returns: -* None -* -*******************************************************************************/ -void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) -{ - SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK; -} - - -/******************************************************************************* -* Function Name: SD_Init_Clk_GetPhase -******************************************************************************** -* -* Summary: -* Gets the phase delay of the analog clock. This function is only available -* for analog clocks. -* -* Parameters: -* None -* -* Returns: -* Phase of the analog clock. See SetPhaseRegister for details. -* -*******************************************************************************/ -uint8 SD_Init_Clk_GetPhaseRegister(void) -{ - return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK; -} - -#endif /* SD_Init_Clk__CFG3 */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h deleted file mode 100755 index df7e48b..0000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h +++ /dev/null @@ -1,124 +0,0 @@ -/******************************************************************************* -* File Name: SD_Init_Clk.h -* Version 2.10 -* -* Description: -* Provides the function and constant definitions for the clock component. -* -* Note: -* -******************************************************************************** -* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. -* You may use this file only in accordance with the license, terms, conditions, -* disclaimers, and limitations in the end user license agreement accompanying -* the software package with which this file was provided. -*******************************************************************************/ - -#if !defined(CY_CLOCK_SD_Init_Clk_H) -#define CY_CLOCK_SD_Init_Clk_H - -#include -#include - - -/*************************************** -* Conditional Compilation Parameters -***************************************/ - -/* Check to see if required defines such as CY_PSOC5LP are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5LP) - #error Component cy_clock_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5LP) */ - - -/*************************************** -* Function Prototypes -***************************************/ - -void SD_Init_Clk_Start(void) ; -void SD_Init_Clk_Stop(void) ; - -#if(CY_PSOC3 || CY_PSOC5LP) -void SD_Init_Clk_StopBlock(void) ; -#endif /* (CY_PSOC3 || CY_PSOC5LP) */ - -void SD_Init_Clk_StandbyPower(uint8 state) ; -void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) - ; -uint16 SD_Init_Clk_GetDividerRegister(void) ; -void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ; -void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ; -uint8 SD_Init_Clk_GetModeRegister(void) ; -void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ; -uint8 SD_Init_Clk_GetSourceRegister(void) ; -#if defined(SD_Init_Clk__CFG3) -void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ; -uint8 SD_Init_Clk_GetPhaseRegister(void) ; -#endif /* defined(SD_Init_Clk__CFG3) */ - -#define SD_Init_Clk_Enable() SD_Init_Clk_Start() -#define SD_Init_Clk_Disable() SD_Init_Clk_Stop() -#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u) -#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u) -#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode) -#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource) -#if defined(SD_Init_Clk__CFG3) -#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase) -#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u) -#endif /* defined(SD_Init_Clk__CFG3) */ - - -/*************************************** -* Registers -***************************************/ - -/* Register to enable or disable the clock */ -#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG) -#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG) - -/* Register to enable or disable the clock */ -#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG) -#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG) - -/* Clock LSB divider configuration register. */ -#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0) -#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0) -#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0) - -/* Clock MSB divider configuration register. */ -#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1) -#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1) - -/* Mode and source configuration register */ -#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2) -#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2) - -#if defined(SD_Init_Clk__CFG3) -/* Analog clock phase configuration register */ -#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3) -#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3) -#endif /* defined(SD_Init_Clk__CFG3) */ - - -/************************************** -* Register Constants -**************************************/ - -/* Power manager register masks */ -#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK -#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK - -/* CFG2 field masks */ -#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK -#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK)) - -#if defined(SD_Init_Clk__CFG3) -/* CFG3 phase mask */ -#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK -#endif /* defined(SD_Init_Clk__CFG3) */ - -#endif /* CY_CLOCK_SD_Init_Clk_H */ - - -/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c new file mode 100644 index 0000000..2671e74 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SD_RX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SD_RX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SD_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */ + SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SD_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */ + SD_RX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SD_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SD_RX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SD_RX_DMA_COMPLETE_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SD_RX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SD_RX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start +* or SD_RX_DMA_COMPLETE_StartEx will override any effect this method +* would have had. This method should only be called after +* SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SD_RX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SD_RX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_SetPending(void) +{ + *SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_ClearPending(void) +{ + *SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h new file mode 100644 index 0000000..d1751d1 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SD_RX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H) +#define CY_ISR_SD_RX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SD_RX_DMA_COMPLETE_Start(void); +void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address); +void SD_RX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt); + +void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SD_RX_DMA_COMPLETE_GetVector(void); + +void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SD_RX_DMA_COMPLETE_GetPriority(void); + +void SD_RX_DMA_COMPLETE_Enable(void); +uint8 SD_RX_DMA_COMPLETE_GetState(void); +void SD_RX_DMA_COMPLETE_Disable(void); + +void SD_RX_DMA_COMPLETE_SetPending(void); +void SD_RX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */ +#define SD_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SD_RX_DMA_COMPLETE ISR priority. */ +#define SD_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */ +#define SD_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c new file mode 100644 index 0000000..b2b9bf1 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SD_RX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SD_RX_DMA__DRQ_CTL_REG +* +* +* SD_RX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SD_RX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SD_RX_DMA__PRIORITY +* +* True if SD_RX_DMA_TERMIN_SEL is used. +* SD_RX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SD_RX_DMA__TERMIN_SEL +* +* +* True if SD_RX_DMA_TERMOUT0_SEL is used. +* SD_RX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SD_RX_DMA__TERMOUT0_SEL +* +* +* True if SD_RX_DMA_TERMOUT1_SEL is used. +* SD_RX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SD_RX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SD_RX_DMA dma channel */ +uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SD_RX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SD_RX_DMA__TERMOUT0_SEL, + (uint8)SD_RX_DMA__TERMOUT1_SEL, + (uint8)SD_RX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY); + + return SD_RX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SD_RX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SD_RX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SD_RX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SD_RX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h new file mode 100644 index 0000000..c38d0da --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SD_RX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SD_RX_DMA_DMA_H__) +#define CY_DMA_SD_RX_DMA_DMA_H__ + + + +#include +#include + +#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SD_RX_DMA dma channel */ +extern uint8 SD_RX_DMA_DmaHandle; + + +uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SD_RX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SD_RX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c new file mode 100644 index 0000000..7998256 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SD_TX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SD_TX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SD_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */ + SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SD_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */ + SD_TX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SD_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SD_TX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SD_TX_DMA_COMPLETE_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SD_TX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SD_TX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start +* or SD_TX_DMA_COMPLETE_StartEx will override any effect this method +* would have had. This method should only be called after +* SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SD_TX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SD_TX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_SetPending(void) +{ + *SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_ClearPending(void) +{ + *SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h new file mode 100644 index 0000000..bbacac6 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SD_TX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H) +#define CY_ISR_SD_TX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SD_TX_DMA_COMPLETE_Start(void); +void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address); +void SD_TX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt); + +void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SD_TX_DMA_COMPLETE_GetVector(void); + +void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SD_TX_DMA_COMPLETE_GetPriority(void); + +void SD_TX_DMA_COMPLETE_Enable(void); +uint8 SD_TX_DMA_COMPLETE_GetState(void); +void SD_TX_DMA_COMPLETE_Disable(void); + +void SD_TX_DMA_COMPLETE_SetPending(void); +void SD_TX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */ +#define SD_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SD_TX_DMA_COMPLETE ISR priority. */ +#define SD_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */ +#define SD_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c new file mode 100644 index 0000000..4f605c2 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SD_TX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SD_TX_DMA__DRQ_CTL_REG +* +* +* SD_TX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SD_TX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SD_TX_DMA__PRIORITY +* +* True if SD_TX_DMA_TERMIN_SEL is used. +* SD_TX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SD_TX_DMA__TERMIN_SEL +* +* +* True if SD_TX_DMA_TERMOUT0_SEL is used. +* SD_TX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SD_TX_DMA__TERMOUT0_SEL +* +* +* True if SD_TX_DMA_TERMOUT1_SEL is used. +* SD_TX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SD_TX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SD_TX_DMA dma channel */ +uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SD_TX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SD_TX_DMA__TERMOUT0_SEL, + (uint8)SD_TX_DMA__TERMOUT1_SEL, + (uint8)SD_TX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY); + + return SD_TX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SD_TX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SD_TX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SD_TX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SD_TX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h new file mode 100644 index 0000000..64a7645 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SD_TX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SD_TX_DMA_DMA_H__) +#define CY_DMA_SD_TX_DMA_DMA_H__ + + + +#include +#include + +#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SD_TX_DMA dma channel */ +extern uint8 SD_TX_DMA_DmaHandle; + + +uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SD_TX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SD_TX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h old mode 100755 new mode 100644 index 8fdbe98..bd7996b --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -6,13 +6,33 @@ /* Debug_Timer_Interrupt */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define Debug_Timer_Interrupt__INTC_MASK 0x01u -#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_MASK 0x02u +#define Debug_Timer_Interrupt__INTC_NUMBER 1u #define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u -#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1 #define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_RX_DMA_COMPLETE */ +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA_COMPLETE */ +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + /* Debug_Timer_TimerHW */ #define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 #define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 @@ -31,6 +51,26 @@ #define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 #define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 +/* SD_RX_DMA_COMPLETE */ +#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SD_TX_DMA_COMPLETE */ +#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 @@ -44,41 +84,41 @@ /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL /* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u @@ -93,15 +133,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL /* USBFS_arb_int */ #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -126,24 +166,24 @@ /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -616,8 +656,8 @@ #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -625,13 +665,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -641,26 +681,30 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1 +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1 /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1104,6 +1148,30 @@ #define SCSI_In_DBx__DB7__SHIFT 1 #define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u + /* SD_Data_Clk */ #define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 #define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 @@ -1140,85 +1208,68 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u #define scsiTarget_StatusReg__3__POS 3 -#define scsiTarget_StatusReg__MASK 0x0Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_StatusReg__4__MASK 0x10u +#define scsiTarget_StatusReg__4__POS 4 +#define scsiTarget_StatusReg__MASK 0x1Fu +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ -#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u -#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__REMOVED 1u /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1233,43 +1284,67 @@ /* USBFS_ep_1 */ #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x02u -#define USBFS_ep_1__INTC_NUMBER 1u +#define USBFS_ep_1__INTC_MASK 0x20u +#define USBFS_ep_1__INTC_NUMBER 5u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x04u -#define USBFS_ep_2__INTC_NUMBER 2u +#define USBFS_ep_2__INTC_MASK 0x40u +#define USBFS_ep_2__INTC_NUMBER 6u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x08u -#define USBFS_ep_3__INTC_NUMBER 3u +#define USBFS_ep_3__INTC_MASK 0x80u +#define USBFS_ep_3__INTC_NUMBER 7u #define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ #define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x10u -#define USBFS_ep_4__INTC_NUMBER 4u +#define USBFS_ep_4__INTC_MASK 0x100u +#define USBFS_ep_4__INTC_NUMBER 8u #define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8 #define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SD_RX_DMA */ +#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SD_RX_DMA__DRQ_NUMBER 2u +#define SD_RX_DMA__NUMBEROF_TDS 0u +#define SD_RX_DMA__PRIORITY 1u +#define SD_RX_DMA__TERMIN_EN 0u +#define SD_RX_DMA__TERMIN_SEL 0u +#define SD_RX_DMA__TERMOUT0_EN 1u +#define SD_RX_DMA__TERMOUT0_SEL 2u +#define SD_RX_DMA__TERMOUT1_EN 0u +#define SD_RX_DMA__TERMOUT1_SEL 0u + +/* SD_TX_DMA */ +#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SD_TX_DMA__DRQ_NUMBER 3u +#define SD_TX_DMA__NUMBEROF_TDS 0u +#define SD_TX_DMA__PRIORITY 2u +#define SD_TX_DMA__TERMIN_EN 0u +#define SD_TX_DMA__TERMIN_SEL 0u +#define SD_TX_DMA__TERMOUT0_EN 1u +#define SD_TX_DMA__TERMOUT0_SEL 3u +#define SD_TX_DMA__TERMOUT1_EN 0u +#define SD_TX_DMA__TERMOUT1_SEL 0u + /* USBFS_USB */ #define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG #define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG @@ -2789,9 +2864,9 @@ #define CYDEV_CHIP_FAMILY_PSOC5 3u #define CYDEV_CHIP_DIE_PSOC5LP 4u #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP -#define BCLK__BUS_CLK__HZ 60000000U -#define BCLK__BUS_CLK__KHZ 60000U -#define BCLK__BUS_CLK__MHZ 60U +#define BCLK__BUS_CLK__HZ 50000000U +#define BCLK__BUS_CLK__KHZ 50000U +#define BCLK__BUS_CLK__MHZ 50U #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT #define CYDEV_CHIP_DIE_LEOPARD 1u #define CYDEV_CHIP_DIE_PANTHER 3u @@ -2852,7 +2927,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x00000001u +#define CYDEV_INTR_RISING 0x0000001Eu #define CYDEV_PROJ_TYPE 2 #define CYDEV_PROJ_TYPE_BOOTLOADER 1 #define CYDEV_PROJ_TYPE_LOADABLE 2 @@ -2883,7 +2958,7 @@ #define CYDEV_VIO2_MV 5000 #define CYDEV_VIO3 3.3 #define CYDEV_VIO3_MV 3300 -#define DMA_CHANNELS_USED__MASK0 0x00000000u +#define DMA_CHANNELS_USED__MASK0 0x0000000Fu #define CYDEV_BOOTLOADER_ENABLE 0 #endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c old mode 100755 new mode 100644 index 46963dc..f2497a0 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 35u +#define CY_CFG_BASE_ADDR_COUNT 37u CYPACKED typedef struct { uint8 offset; @@ -187,10 +187,10 @@ static void ClockSetup(void) /* Configure Digital Clocks based on settings from Clock DWR */ - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du); @@ -204,7 +204,7 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); /* Configure PLL based on settings from Clock DWR */ - CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); /* Wait up to 250us for the PLL to lock */ pllLock = 0u; @@ -230,7 +230,7 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Eu))); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu))); } @@ -351,6 +351,18 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Fu, 0x00u, 0x00u, 0x01u}; + /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = { + 0x00u, 0x01u, 0x00u, 0x00u}; + + /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = { + 0x00u, 0x02u, 0x00u, 0x00u}; + + /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = { + 0x00u, 0x03u, 0x00u, 0x00u}; + #ifdef CYGlobalIntDisable /* Disable interrupts by default. Let user enable if/when they want. */ CYGlobalIntDisable @@ -361,6 +373,8 @@ void cyfitter_cfg(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); /* Setup clocks based on selections from Clock DWR */ ClockSetup(); + /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u)); /* Enable/Disable Debug functionality based on settings from System DWR */ CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); @@ -368,1092 +382,1153 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004502u, /* Base address: 0x40004500 Count: 2 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x40005209u, /* Base address: 0x40005200 Count: 9 */ + 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x4001004Au, /* Base address: 0x40010000 Count: 74 */ - 0x40010134u, /* Base address: 0x40010100 Count: 52 */ - 0x40010252u, /* Base address: 0x40010200 Count: 82 */ - 0x40010355u, /* Base address: 0x40010300 Count: 85 */ - 0x40010449u, /* Base address: 0x40010400 Count: 73 */ - 0x40010555u, /* Base address: 0x40010500 Count: 85 */ - 0x4001060Eu, /* Base address: 0x40010600 Count: 14 */ - 0x40010747u, /* Base address: 0x40010700 Count: 71 */ - 0x40010903u, /* Base address: 0x40010900 Count: 3 */ - 0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */ - 0x40010C45u, /* Base address: 0x40010C00 Count: 69 */ - 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */ - 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */ - 0x40011501u, /* Base address: 0x40011500 Count: 1 */ - 0x40011657u, /* Base address: 0x40011600 Count: 87 */ - 0x40011753u, /* Base address: 0x40011700 Count: 83 */ - 0x40011903u, /* Base address: 0x40011900 Count: 3 */ - 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ - 0x40014012u, /* Base address: 0x40014000 Count: 18 */ - 0x40014110u, /* Base address: 0x40014100 Count: 16 */ - 0x40014215u, /* Base address: 0x40014200 Count: 21 */ - 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ - 0x40014410u, /* Base address: 0x40014400 Count: 16 */ - 0x40014517u, /* Base address: 0x40014500 Count: 23 */ - 0x40014607u, /* Base address: 0x40014600 Count: 7 */ - 0x4001470Au, /* Base address: 0x40014700 Count: 10 */ - 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */ - 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ - 0x4001500Bu, /* Base address: 0x40015000 Count: 11 */ - 0x40015102u, /* Base address: 0x40015100 Count: 2 */ + 0x40010052u, /* Base address: 0x40010000 Count: 82 */ + 0x40010139u, /* Base address: 0x40010100 Count: 57 */ + 0x40010241u, /* Base address: 0x40010200 Count: 65 */ + 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */ + 0x40010417u, /* Base address: 0x40010400 Count: 23 */ + 0x40010560u, /* Base address: 0x40010500 Count: 96 */ + 0x4001065Du, /* Base address: 0x40010600 Count: 93 */ + 0x40010754u, /* Base address: 0x40010700 Count: 84 */ + 0x40010804u, /* Base address: 0x40010800 Count: 4 */ + 0x4001090Eu, /* Base address: 0x40010900 Count: 14 */ + 0x40010B12u, /* Base address: 0x40010B00 Count: 18 */ + 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */ + 0x40010D45u, /* Base address: 0x40010D00 Count: 69 */ + 0x40010F05u, /* Base address: 0x40010F00 Count: 5 */ + 0x40011505u, /* Base address: 0x40011500 Count: 5 */ + 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */ + 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */ + 0x4001190Au, /* Base address: 0x40011900 Count: 10 */ + 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */ + 0x40014019u, /* Base address: 0x40014000 Count: 25 */ + 0x40014117u, /* Base address: 0x40014100 Count: 23 */ + 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ + 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ + 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ + 0x40014516u, /* Base address: 0x40014500 Count: 22 */ + 0x40014608u, /* Base address: 0x40014600 Count: 8 */ + 0x40014705u, /* Base address: 0x40014700 Count: 5 */ + 0x40014807u, /* Base address: 0x40014800 Count: 7 */ + 0x4001490Au, /* Base address: 0x40014900 Count: 10 */ + 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ + 0x40015005u, /* Base address: 0x40015000 Count: 5 */ + 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x36u, 0x02u}, {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x36u}, - {0x00u, 0x13u}, - {0x01u, 0x05u}, - {0x19u, 0x04u}, + {0x0Au, 0x1Bu}, + {0x00u, 0x14u}, + {0x01u, 0x01u}, + {0x18u, 0x0Cu}, + {0x19u, 0x08u}, {0x1Cu, 0x61u}, - {0x20u, 0xA8u}, - {0x21u, 0x60u}, - {0x30u, 0x09u}, - {0x31u, 0x0Au}, + {0x20u, 0x60u}, + {0x21u, 0xC0u}, + {0x30u, 0x06u}, + {0x31u, 0x0Cu}, {0x7Cu, 0x40u}, - {0x3Cu, 0x01u}, + {0x23u, 0x02u}, {0x86u, 0x0Fu}, - {0x05u, 0x08u}, - {0x06u, 0x40u}, - {0x07u, 0x44u}, - {0x0Au, 0x10u}, - {0x0Cu, 0x55u}, - {0x0Du, 0x04u}, - {0x0Eu, 0xAAu}, - {0x0Fu, 0x09u}, - {0x11u, 0x4Du}, - {0x12u, 0x04u}, - {0x13u, 0xB2u}, - {0x16u, 0x20u}, - {0x1Au, 0x02u}, - {0x1Du, 0x20u}, - {0x1Fu, 0x90u}, - {0x22u, 0x01u}, - {0x2Au, 0x80u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x08u}, - {0x2Fu, 0x22u}, - {0x30u, 0xC0u}, - {0x31u, 0xC0u}, - {0x32u, 0x0Cu}, - {0x33u, 0x03u}, - {0x34u, 0x30u}, - {0x35u, 0x3Cu}, - {0x36u, 0x03u}, - {0x3Eu, 0x55u}, - {0x3Fu, 0x15u}, + {0x00u, 0x03u}, + {0x01u, 0x09u}, + {0x02u, 0x0Cu}, + {0x03u, 0x24u}, + {0x04u, 0x09u}, + {0x06u, 0x06u}, + {0x07u, 0x09u}, + {0x08u, 0xFFu}, + {0x09u, 0x40u}, + {0x0Cu, 0x90u}, + {0x0Eu, 0x60u}, + {0x0Fu, 0x30u}, + {0x10u, 0xFFu}, + {0x11u, 0x09u}, + {0x13u, 0x12u}, + {0x14u, 0x05u}, + {0x15u, 0x40u}, + {0x16u, 0x0Au}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x0Fu}, + {0x1Eu, 0xF0u}, + {0x1Fu, 0x06u}, + {0x20u, 0x50u}, + {0x22u, 0xA0u}, + {0x23u, 0x08u}, + {0x25u, 0x80u}, + {0x26u, 0xFFu}, + {0x29u, 0x40u}, + {0x2Cu, 0x30u}, + {0x2Du, 0x40u}, + {0x2Eu, 0xC0u}, + {0x31u, 0x38u}, + {0x32u, 0xFFu}, + {0x33u, 0x40u}, + {0x35u, 0x80u}, + {0x37u, 0x07u}, + {0x39u, 0x08u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x14u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0x03u}, - {0x81u, 0x06u}, - {0x82u, 0x0Cu}, - {0x83u, 0x09u}, - {0x84u, 0x05u}, - {0x86u, 0x0Au}, - {0x87u, 0xFFu}, - {0x89u, 0x30u}, - {0x8Au, 0xFFu}, - {0x8Bu, 0xC0u}, - {0x8Cu, 0x0Fu}, - {0x8Du, 0x60u}, - {0x8Eu, 0xF0u}, - {0x8Fu, 0x90u}, - {0x90u, 0x90u}, - {0x91u, 0x0Fu}, - {0x92u, 0x60u}, - {0x93u, 0xF0u}, - {0x94u, 0xFFu}, - {0x95u, 0x50u}, - {0x97u, 0xA0u}, - {0x98u, 0xFFu}, - {0x99u, 0xFFu}, - {0xA1u, 0x03u}, - {0xA3u, 0x0Cu}, - {0xA4u, 0x50u}, - {0xA6u, 0xA0u}, - {0xA7u, 0xFFu}, - {0xA8u, 0x30u}, - {0xA9u, 0x05u}, - {0xAAu, 0xC0u}, - {0xABu, 0x0Au}, - {0xACu, 0x09u}, - {0xAEu, 0x06u}, - {0xB2u, 0xFFu}, - {0xB5u, 0xFFu}, - {0xBEu, 0x04u}, - {0xBFu, 0x10u}, + {0x81u, 0x10u}, + {0x83u, 0x20u}, + {0x85u, 0x43u}, + {0x86u, 0xC1u}, + {0x87u, 0x04u}, + {0x89u, 0x45u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x02u}, + {0x8Du, 0x08u}, + {0x8Eu, 0x02u}, + {0x90u, 0x24u}, + {0x91u, 0x41u}, + {0x92u, 0x90u}, + {0x93u, 0x06u}, + {0x95u, 0x04u}, + {0x96u, 0x24u}, + {0x97u, 0x03u}, + {0x9Au, 0x18u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x01u}, + {0xA2u, 0x02u}, + {0xA6u, 0x20u}, + {0xA8u, 0x24u}, + {0xAAu, 0x48u}, + {0xABu, 0x20u}, + {0xB1u, 0x08u}, + {0xB2u, 0xE0u}, + {0xB3u, 0x07u}, + {0xB4u, 0x1Cu}, + {0xB5u, 0x30u}, + {0xB6u, 0x03u}, + {0xB7u, 0x40u}, + {0xBBu, 0x08u}, + {0xBEu, 0x40u}, + {0xBFu, 0x51u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x10u}, - {0x03u, 0x01u}, - {0x05u, 0x02u}, - {0x06u, 0x28u}, - {0x07u, 0x03u}, - {0x08u, 0x01u}, - {0x0Au, 0x14u}, - {0x0Eu, 0x60u}, - {0x0Fu, 0x04u}, - {0x10u, 0x08u}, - {0x11u, 0x41u}, - {0x14u, 0x01u}, - {0x16u, 0x02u}, - {0x17u, 0x24u}, - {0x19u, 0x18u}, - {0x1Au, 0x80u}, - {0x1Bu, 0x80u}, - {0x1Du, 0x04u}, - {0x20u, 0x80u}, - {0x23u, 0x14u}, - {0x26u, 0x20u}, - {0x29u, 0x40u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x13u}, - {0x2Eu, 0x20u}, - {0x33u, 0x41u}, - {0x34u, 0x10u}, - {0x36u, 0x10u}, - {0x37u, 0x06u}, - {0x39u, 0x88u}, - {0x3Cu, 0x20u}, - {0x3Eu, 0x42u}, - {0x3Fu, 0x04u}, - {0x41u, 0xC0u}, - {0x68u, 0x10u}, - {0x69u, 0x40u}, - {0x6Au, 0x54u}, - {0x6Bu, 0x64u}, - {0x70u, 0x18u}, - {0x71u, 0x41u}, - {0x80u, 0x08u}, - {0x8Bu, 0x80u}, - {0x8Eu, 0x40u}, - {0xC0u, 0xF7u}, - {0xC2u, 0x7Eu}, - {0xC4u, 0xEBu}, - {0xCAu, 0xE8u}, - {0xCCu, 0xE9u}, - {0xCEu, 0xFAu}, - {0xE2u, 0x10u}, - {0xE6u, 0x05u}, - {0x01u, 0x03u}, - {0x03u, 0x0Cu}, - {0x04u, 0x30u}, - {0x06u, 0xC0u}, - {0x07u, 0xFFu}, - {0x0Au, 0xFFu}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0x06u}, - {0x0Du, 0x90u}, - {0x0Eu, 0x09u}, - {0x0Fu, 0x60u}, - {0x10u, 0x60u}, - {0x11u, 0x0Fu}, - {0x12u, 0x90u}, - {0x13u, 0xF0u}, - {0x15u, 0x50u}, - {0x16u, 0xFFu}, - {0x17u, 0xA0u}, - {0x18u, 0xFFu}, - {0x19u, 0x30u}, - {0x1Bu, 0xC0u}, - {0x1Cu, 0x03u}, - {0x1Eu, 0x0Cu}, - {0x20u, 0x0Fu}, - {0x21u, 0x09u}, - {0x22u, 0xF0u}, - {0x23u, 0x06u}, - {0x24u, 0x50u}, - {0x26u, 0xA0u}, - {0x27u, 0xFFu}, - {0x28u, 0x05u}, - {0x29u, 0x05u}, - {0x2Au, 0x0Au}, - {0x2Bu, 0x0Au}, - {0x34u, 0xFFu}, - {0x35u, 0xFFu}, - {0x3Eu, 0x10u}, + {0x00u, 0x80u}, + {0x02u, 0xA0u}, + {0x03u, 0x08u}, + {0x05u, 0x14u}, + {0x07u, 0x01u}, + {0x08u, 0x40u}, + {0x09u, 0x05u}, + {0x0Au, 0x01u}, + {0x0Du, 0x25u}, + {0x0Fu, 0x08u}, + {0x11u, 0x84u}, + {0x12u, 0x04u}, + {0x13u, 0x22u}, + {0x14u, 0x40u}, + {0x15u, 0x20u}, + {0x16u, 0x20u}, + {0x18u, 0x10u}, + {0x1Du, 0x24u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x80u}, + {0x20u, 0x20u}, + {0x22u, 0xD0u}, + {0x23u, 0xC0u}, + {0x24u, 0x40u}, + {0x25u, 0x80u}, + {0x26u, 0x04u}, + {0x27u, 0x28u}, + {0x28u, 0x08u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x22u}, + {0x2Cu, 0x04u}, + {0x31u, 0x01u}, + {0x32u, 0x44u}, + {0x33u, 0x10u}, + {0x36u, 0x06u}, + {0x37u, 0x80u}, + {0x38u, 0x10u}, + {0x39u, 0x0Au}, + {0x3Bu, 0x40u}, + {0x3Eu, 0x05u}, + {0x3Fu, 0x90u}, + {0x46u, 0x40u}, + {0x47u, 0x01u}, + {0x86u, 0x20u}, + {0x87u, 0x02u}, + {0x88u, 0x08u}, + {0x8Cu, 0x40u}, + {0x8Du, 0x01u}, + {0x8Fu, 0x08u}, + {0xC0u, 0xEFu}, + {0xC2u, 0x7Du}, + {0xC4u, 0x7Du}, + {0xCAu, 0x2Fu}, + {0xCCu, 0xDFu}, + {0xCEu, 0xFFu}, + {0xE2u, 0x08u}, + {0xE6u, 0x72u}, + {0x21u, 0x01u}, + {0x35u, 0x01u}, {0x3Fu, 0x10u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x0Du}, - {0x87u, 0x06u}, - {0x88u, 0x0Du}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x0Du}, - {0x92u, 0x10u}, - {0x94u, 0x80u}, - {0x95u, 0x09u}, - {0x97u, 0x52u}, - {0x98u, 0x02u}, - {0x9Au, 0x54u}, - {0x9Cu, 0x02u}, - {0x9Eu, 0x0Du}, - {0x9Fu, 0x30u}, - {0xA0u, 0x0Du}, - {0xA1u, 0x09u}, - {0xA3u, 0x24u}, - {0xA4u, 0x01u}, - {0xA6u, 0x32u}, - {0xA7u, 0x01u}, - {0xA8u, 0x62u}, - {0xAAu, 0x08u}, - {0xABu, 0x49u}, - {0xACu, 0x0Du}, - {0xB0u, 0x70u}, - {0xB3u, 0x07u}, + {0x80u, 0x80u}, + {0x81u, 0x40u}, + {0x84u, 0x02u}, + {0x85u, 0x01u}, + {0x8Au, 0x1Fu}, + {0x8Bu, 0x20u}, + {0x8Cu, 0x5Bu}, + {0x8Du, 0x80u}, + {0x8Eu, 0x24u}, + {0x94u, 0x03u}, + {0x95u, 0x08u}, + {0x96u, 0x0Cu}, + {0x97u, 0x12u}, + {0x98u, 0x58u}, + {0x99u, 0x0Bu}, + {0x9Au, 0x24u}, + {0x9Bu, 0x24u}, + {0xA0u, 0x0Cu}, + {0xA1u, 0x34u}, + {0xA2u, 0x40u}, + {0xA3u, 0x0Bu}, + {0xA6u, 0x01u}, + {0xA8u, 0x40u}, + {0xAAu, 0x37u}, + {0xABu, 0x3Fu}, + {0xB0u, 0x1Fu}, + {0xB1u, 0x80u}, + {0xB2u, 0x20u}, + {0xB3u, 0x38u}, {0xB4u, 0x80u}, - {0xB5u, 0x40u}, - {0xB6u, 0x0Fu}, - {0xB7u, 0x38u}, - {0xBAu, 0x80u}, - {0xBEu, 0x10u}, - {0xBFu, 0x10u}, - {0xD8u, 0x0Bu}, + {0xB5u, 0x07u}, + {0xB6u, 0x40u}, + {0xB7u, 0x40u}, + {0xBEu, 0x54u}, + {0xBFu, 0x41u}, + {0xC0u, 0x64u}, + {0xC1u, 0x02u}, + {0xC2u, 0x30u}, + {0xC5u, 0xCDu}, + {0xC6u, 0x2Eu}, + {0xC7u, 0x0Fu}, + {0xC8u, 0x1Fu}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCFu, 0x2Cu}, + {0xD6u, 0x01u}, + {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDAu, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x19u}, + {0xDCu, 0x11u}, + {0xDDu, 0x01u}, {0xDFu, 0x01u}, - {0x03u, 0x19u}, - {0x06u, 0x0Au}, - {0x07u, 0x20u}, - {0x08u, 0x04u}, + {0xE2u, 0xC0u}, + {0xE6u, 0x80u}, + {0xE8u, 0x40u}, + {0xE9u, 0x40u}, + {0xEEu, 0x08u}, + {0x00u, 0x02u}, + {0x01u, 0x08u}, + {0x03u, 0x0Au}, {0x09u, 0x20u}, - {0x0Au, 0x81u}, - {0x0Eu, 0x50u}, - {0x0Fu, 0x05u}, + {0x0Bu, 0x20u}, {0x10u, 0x80u}, - {0x11u, 0x40u}, - {0x13u, 0x18u}, - {0x14u, 0x40u}, - {0x15u, 0x10u}, - {0x17u, 0x06u}, - {0x19u, 0x20u}, - {0x1Au, 0x81u}, - {0x1Eu, 0x04u}, - {0x20u, 0x04u}, - {0x21u, 0x84u}, - {0x25u, 0x10u}, - {0x28u, 0x80u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x10u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x0Au}, - {0x31u, 0x80u}, - {0x32u, 0x04u}, - {0x37u, 0xE6u}, - {0x39u, 0x08u}, - {0x3Au, 0x20u}, - {0x3Du, 0x03u}, - {0x3Eu, 0x50u}, - {0x3Fu, 0x05u}, - {0x58u, 0x10u}, - {0x5Au, 0x10u}, - {0x5Fu, 0x80u}, - {0x61u, 0x01u}, - {0x62u, 0x02u}, - {0x64u, 0x02u}, - {0x6Bu, 0x02u}, - {0x6Cu, 0x02u}, - {0x78u, 0x02u}, - {0x82u, 0x02u}, - {0x83u, 0x10u}, - {0x84u, 0x80u}, - {0x86u, 0xA0u}, - {0x88u, 0x04u}, - {0x89u, 0x10u}, - {0x8Bu, 0x40u}, - {0x8Cu, 0x04u}, + {0x11u, 0x04u}, + {0x12u, 0x08u}, + {0x18u, 0x04u}, + {0x19u, 0x42u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x02u}, + {0x21u, 0x34u}, + {0x22u, 0x09u}, + {0x23u, 0x05u}, + {0x27u, 0x04u}, + {0x29u, 0x02u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x08u}, + {0x2Du, 0x20u}, + {0x2Fu, 0x80u}, + {0x31u, 0x20u}, + {0x32u, 0x08u}, + {0x38u, 0x20u}, + {0x39u, 0x85u}, + {0x41u, 0x11u}, + {0x42u, 0x10u}, + {0x43u, 0x02u}, + {0x48u, 0x90u}, + {0x49u, 0x08u}, + {0x4Au, 0x08u}, + {0x50u, 0x58u}, + {0x5Au, 0xA2u}, + {0x5Bu, 0x04u}, + {0x60u, 0x44u}, + {0x61u, 0x08u}, + {0x63u, 0x01u}, + {0x69u, 0x10u}, + {0x6Au, 0x40u}, + {0x6Bu, 0x50u}, + {0x6Du, 0x64u}, + {0x71u, 0x10u}, + {0x72u, 0x22u}, + {0x73u, 0x40u}, + {0x81u, 0x40u}, + {0x82u, 0x40u}, + {0x87u, 0x80u}, + {0x89u, 0x05u}, + {0x8Au, 0x80u}, + {0x8Bu, 0x80u}, + {0x8Cu, 0x08u}, {0x8Du, 0x40u}, - {0x90u, 0x20u}, + {0x8Fu, 0x08u}, + {0x90u, 0x40u}, + {0x92u, 0x20u}, + {0x93u, 0x20u}, + {0x94u, 0x80u}, + {0x95u, 0x2Eu}, + {0x96u, 0x0Du}, + {0x97u, 0x10u}, + {0x9Au, 0x44u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x11u}, + {0x9Eu, 0x22u}, + {0x9Fu, 0x12u}, + {0xA1u, 0x80u}, + {0xA2u, 0x90u}, + {0xA3u, 0x04u}, + {0xA4u, 0x48u}, + {0xA5u, 0x44u}, + {0xA6u, 0x02u}, + {0xA7u, 0x20u}, + {0xABu, 0x40u}, + {0xACu, 0x10u}, + {0xAFu, 0x91u}, + {0xB0u, 0x04u}, + {0xB7u, 0x08u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x06u}, + {0xC4u, 0x0Eu}, + {0xCAu, 0x85u}, + {0xCCu, 0x06u}, + {0xCEu, 0x0Fu}, + {0xD0u, 0x07u}, + {0xD2u, 0x04u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE2u, 0x20u}, + {0xE6u, 0x09u}, + {0xEAu, 0x06u}, + {0xEEu, 0x02u}, + {0x85u, 0x02u}, + {0x87u, 0x05u}, + {0x8Fu, 0x02u}, + {0x97u, 0x03u}, + {0x9Au, 0x01u}, + {0x9Fu, 0x0Cu}, + {0xA1u, 0x02u}, + {0xA2u, 0x04u}, + {0xA3u, 0x08u}, + {0xA4u, 0x05u}, + {0xA6u, 0x0Au}, + {0xAAu, 0x02u}, + {0xAEu, 0x08u}, + {0xB1u, 0x0Eu}, + {0xB4u, 0x0Cu}, + {0xB5u, 0x01u}, + {0xB6u, 0x03u}, + {0xBEu, 0x50u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x10u}, + {0xDFu, 0x01u}, + {0x01u, 0x41u}, + {0x03u, 0x18u}, + {0x04u, 0x80u}, + {0x05u, 0x80u}, + {0x08u, 0x48u}, + {0x0Au, 0x86u}, + {0x0Du, 0x80u}, + {0x0Fu, 0x0Au}, + {0x10u, 0x80u}, + {0x12u, 0x02u}, + {0x13u, 0x10u}, + {0x14u, 0x01u}, + {0x15u, 0x02u}, + {0x17u, 0x28u}, + {0x1Au, 0x82u}, + {0x1Bu, 0x10u}, + {0x1Fu, 0x90u}, + {0x20u, 0x40u}, + {0x22u, 0x10u}, + {0x27u, 0x84u}, + {0x29u, 0x02u}, + {0x2Du, 0x02u}, + {0x32u, 0x18u}, + {0x33u, 0x40u}, + {0x36u, 0x08u}, + {0x37u, 0x80u}, + {0x38u, 0x40u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Fu, 0x44u}, + {0x40u, 0x20u}, + {0x42u, 0x04u}, + {0x43u, 0x02u}, + {0x49u, 0x04u}, + {0x4Au, 0x02u}, + {0x4Bu, 0x11u}, + {0x50u, 0x08u}, + {0x51u, 0x60u}, + {0x53u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0xA0u}, + {0x5Au, 0x01u}, + {0x61u, 0x40u}, + {0x64u, 0x02u}, + {0x67u, 0x02u}, + {0x79u, 0x02u}, + {0x7Au, 0x80u}, + {0x7Du, 0x08u}, + {0x7Eu, 0x10u}, + {0x80u, 0x08u}, + {0x83u, 0x05u}, + {0x85u, 0x40u}, + {0x88u, 0x20u}, + {0x8Bu, 0x10u}, + {0x8Fu, 0x80u}, + {0x90u, 0x80u}, + {0x91u, 0x14u}, {0x92u, 0x40u}, - {0x93u, 0x04u}, - {0x95u, 0x19u}, - {0x98u, 0x08u}, - {0x99u, 0x05u}, - {0x9Bu, 0x24u}, - {0x9Cu, 0x10u}, - {0x9Eu, 0x0Au}, - {0x9Fu, 0x02u}, - {0xA0u, 0x08u}, - {0xA2u, 0x20u}, - {0xA4u, 0x24u}, - {0xA5u, 0x80u}, - {0xACu, 0x40u}, - {0xADu, 0x08u}, - {0xB3u, 0x10u}, + {0x93u, 0x44u}, + {0x96u, 0x0Cu}, + {0x97u, 0x10u}, + {0x98u, 0x04u}, + {0x99u, 0x62u}, + {0x9Au, 0x44u}, + {0x9Bu, 0x68u}, + {0xA0u, 0x10u}, + {0xA1u, 0x80u}, + {0xA2u, 0x98u}, + {0xA3u, 0x04u}, + {0xA4u, 0x40u}, + {0xA5u, 0x04u}, + {0xA6u, 0x02u}, + {0xA7u, 0x40u}, + {0xA9u, 0x29u}, + {0xABu, 0x20u}, + {0xACu, 0x84u}, + {0xADu, 0x40u}, + {0xB0u, 0x01u}, + {0xB2u, 0x01u}, + {0xB3u, 0x28u}, {0xB5u, 0x10u}, - {0xC0u, 0xE7u}, - {0xC2u, 0xFFu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0xE7u}, - {0xCCu, 0xEAu}, - {0xCEu, 0xF6u}, - {0xD6u, 0x10u}, - {0xD8u, 0x10u}, - {0xDEu, 0x01u}, - {0xE2u, 0x0Au}, - {0xE6u, 0x47u}, - {0xE8u, 0x02u}, - {0xEAu, 0x08u}, - {0xECu, 0x08u}, - {0xEEu, 0x80u}, - {0x01u, 0x44u}, - {0x05u, 0xE1u}, - {0x06u, 0x46u}, - {0x07u, 0x12u}, - {0x08u, 0x09u}, - {0x09u, 0x80u}, - {0x0Au, 0x12u}, - {0x0Bu, 0x5Fu}, - {0x0Du, 0x4Cu}, - {0x0Eu, 0x80u}, - {0x11u, 0x4Cu}, - {0x12u, 0x30u}, + {0xB7u, 0x42u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x4Fu}, + {0xC4u, 0xFBu}, + {0xCAu, 0x81u}, + {0xCCu, 0x5Eu}, + {0xCEu, 0x5Eu}, + {0xD0u, 0x07u}, + {0xD2u, 0x0Cu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, + {0xE0u, 0x80u}, + {0xE2u, 0x40u}, + {0xEAu, 0x03u}, + {0xEEu, 0x54u}, + {0x00u, 0x01u}, + {0x03u, 0x9Fu}, + {0x04u, 0x01u}, + {0x07u, 0xFFu}, + {0x08u, 0x04u}, + {0x09u, 0x7Fu}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x01u}, + {0x0Du, 0x90u}, + {0x0Fu, 0x40u}, + {0x11u, 0x1Fu}, + {0x12u, 0x40u}, + {0x13u, 0x20u}, + {0x14u, 0xA2u}, + {0x15u, 0x80u}, {0x16u, 0x08u}, - {0x17u, 0x4Cu}, - {0x19u, 0xB1u}, - {0x1Au, 0x09u}, - {0x1Bu, 0x0Eu}, - {0x1Cu, 0x09u}, - {0x1Du, 0x4Cu}, - {0x1Eu, 0x24u}, - {0x20u, 0x40u}, - {0x21u, 0x08u}, - {0x22u, 0x80u}, - {0x23u, 0x20u}, - {0x25u, 0x44u}, - {0x26u, 0x01u}, - {0x27u, 0x08u}, - {0x30u, 0x38u}, - {0x31u, 0x10u}, - {0x33u, 0x61u}, - {0x34u, 0x07u}, - {0x35u, 0x0Fu}, - {0x36u, 0xC0u}, - {0x37u, 0x80u}, - {0x3Bu, 0x0Cu}, + {0x18u, 0x08u}, + {0x1Au, 0x61u}, + {0x1Bu, 0x60u}, + {0x1Cu, 0x01u}, + {0x1Du, 0xC0u}, + {0x1Fu, 0x02u}, + {0x20u, 0x07u}, + {0x21u, 0xC0u}, + {0x22u, 0xD8u}, + {0x23u, 0x01u}, + {0x25u, 0xC0u}, + {0x27u, 0x04u}, + {0x28u, 0x01u}, + {0x29u, 0xC0u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x10u}, + {0x30u, 0xE0u}, + {0x36u, 0x3Fu}, + {0x37u, 0xFFu}, + {0x38u, 0x80u}, {0x3Eu, 0x40u}, - {0x3Fu, 0x41u}, - {0x54u, 0x09u}, + {0x3Fu, 0x40u}, {0x58u, 0x04u}, - {0x59u, 0x0Bu}, - {0x5Bu, 0x0Bu}, - {0x5Cu, 0x91u}, - {0x5Du, 0x90u}, + {0x59u, 0x04u}, {0x5Fu, 0x01u}, - {0x82u, 0x38u}, - {0x85u, 0x04u}, - {0x88u, 0x01u}, - {0x89u, 0x04u}, - {0x8Au, 0x14u}, - {0x90u, 0x3Eu}, - {0x94u, 0x22u}, - {0x95u, 0x04u}, - {0x96u, 0x01u}, - {0x99u, 0x04u}, - {0x9Fu, 0x01u}, - {0xA4u, 0x09u}, - {0xA6u, 0x02u}, - {0xABu, 0x02u}, - {0xADu, 0x01u}, - {0xAFu, 0x02u}, - {0xB0u, 0x07u}, - {0xB1u, 0x03u}, - {0xB4u, 0x38u}, - {0xB7u, 0x04u}, - {0xB8u, 0x02u}, - {0xB9u, 0x80u}, - {0xBEu, 0x10u}, - {0xBFu, 0x41u}, - {0xD8u, 0x0Bu}, + {0x80u, 0x56u}, + {0x81u, 0x64u}, + {0x84u, 0x52u}, + {0x85u, 0x83u}, + {0x86u, 0x04u}, + {0x87u, 0x70u}, + {0x88u, 0x50u}, + {0x8Au, 0x06u}, + {0x8Bu, 0xF5u}, + {0x8Cu, 0x17u}, + {0x8Du, 0x64u}, + {0x8Eu, 0x28u}, + {0x91u, 0x07u}, + {0x93u, 0x90u}, + {0x94u, 0x31u}, + {0x95u, 0x40u}, + {0x96u, 0x0Eu}, + {0x97u, 0x02u}, + {0x98u, 0x29u}, + {0x99u, 0x24u}, + {0x9Au, 0x16u}, + {0x9Bu, 0x40u}, + {0x9Du, 0x08u}, + {0xA0u, 0x56u}, + {0xA1u, 0x64u}, + {0xA4u, 0x22u}, + {0xA5u, 0x24u}, + {0xA6u, 0x10u}, + {0xA8u, 0x04u}, + {0xABu, 0x64u}, + {0xACu, 0x06u}, + {0xADu, 0x08u}, + {0xAEu, 0x50u}, + {0xB0u, 0x40u}, + {0xB1u, 0x71u}, + {0xB2u, 0x30u}, + {0xB3u, 0x07u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0x08u}, + {0xB7u, 0x80u}, + {0xB8u, 0x20u}, + {0xB9u, 0x20u}, + {0xBAu, 0x08u}, + {0xBBu, 0x0Cu}, + {0xBEu, 0x01u}, + {0xBFu, 0x40u}, + {0xD4u, 0x40u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x09u}, {0xDFu, 0x01u}, - {0x00u, 0x20u}, + {0x01u, 0x01u}, {0x02u, 0x02u}, - {0x03u, 0x20u}, - {0x04u, 0x02u}, - {0x05u, 0x10u}, - {0x08u, 0x80u}, - {0x09u, 0x01u}, - {0x0Au, 0xA0u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x80u}, + {0x03u, 0x18u}, + {0x05u, 0x08u}, + {0x07u, 0x49u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x10u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x84u}, {0x0Fu, 0x10u}, - {0x10u, 0x40u}, - {0x11u, 0x08u}, - {0x17u, 0x08u}, - {0x19u, 0x20u}, - {0x1Au, 0x82u}, - {0x1Bu, 0x20u}, + {0x10u, 0x98u}, + {0x11u, 0x40u}, + {0x15u, 0x82u}, + {0x17u, 0x10u}, + {0x18u, 0x08u}, + {0x19u, 0x09u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x02u}, + {0x1Du, 0x40u}, {0x1Eu, 0x80u}, - {0x1Fu, 0x10u}, - {0x20u, 0x04u}, - {0x21u, 0x84u}, - {0x23u, 0x98u}, - {0x25u, 0x40u}, - {0x27u, 0x40u}, - {0x2Au, 0x0Bu}, - {0x2Cu, 0x02u}, - {0x2Fu, 0x04u}, - {0x30u, 0x80u}, - {0x31u, 0x10u}, - {0x33u, 0x09u}, - {0x35u, 0x04u}, - {0x36u, 0xA0u}, - {0x38u, 0x04u}, - {0x39u, 0x41u}, + {0x21u, 0x01u}, + {0x22u, 0x62u}, + {0x23u, 0x18u}, + {0x25u, 0x80u}, + {0x28u, 0x10u}, + {0x29u, 0x48u}, + {0x2Bu, 0x88u}, + {0x2Cu, 0xA0u}, + {0x2Fu, 0x08u}, + {0x30u, 0x28u}, + {0x31u, 0x80u}, + {0x32u, 0x02u}, + {0x35u, 0x08u}, + {0x36u, 0x22u}, + {0x37u, 0x40u}, + {0x38u, 0x08u}, + {0x39u, 0x40u}, + {0x3Au, 0x02u}, {0x3Bu, 0x10u}, - {0x3Du, 0x20u}, + {0x3Du, 0x40u}, {0x3Eu, 0x04u}, - {0x58u, 0x20u}, - {0x59u, 0x09u}, - {0x5Bu, 0x80u}, - {0x61u, 0x80u}, - {0x65u, 0x08u}, - {0x66u, 0x14u}, - {0x67u, 0x04u}, - {0x6Cu, 0x20u}, - {0x6Fu, 0x06u}, - {0x78u, 0x02u}, - {0x7Cu, 0x02u}, - {0x82u, 0x80u}, - {0x85u, 0x40u}, - {0x86u, 0x01u}, - {0x87u, 0x02u}, - {0x90u, 0x20u}, - {0x91u, 0x80u}, - {0x92u, 0x24u}, - {0x93u, 0x40u}, - {0x95u, 0x40u}, - {0x96u, 0x18u}, - {0x97u, 0x10u}, - {0x98u, 0xCAu}, - {0x99u, 0x04u}, - {0x9Au, 0x80u}, - {0x9Eu, 0x10u}, - {0x9Fu, 0x59u}, - {0xA0u, 0x0Au}, - {0xA1u, 0x14u}, - {0xA2u, 0x22u}, - {0xA4u, 0xA4u}, - {0xA5u, 0x21u}, - {0xA7u, 0x08u}, - {0xA8u, 0x20u}, - {0xB1u, 0x20u}, - {0xB5u, 0x04u}, - {0xB6u, 0x50u}, - {0xC0u, 0x57u}, - {0xC2u, 0x3Fu}, - {0xC4u, 0x2Cu}, - {0xCAu, 0x33u}, - {0xCCu, 0x7Fu}, - {0xCEu, 0x6Fu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x08u}, - {0xDEu, 0x81u}, - {0xE2u, 0x01u}, - {0xEAu, 0x10u}, - {0x87u, 0x11u}, - {0x8Bu, 0x06u}, - {0x8Fu, 0x01u}, - {0x95u, 0x19u}, - {0x97u, 0x22u}, - {0x99u, 0x08u}, - {0xA1u, 0x21u}, - {0xA3u, 0x1Cu}, - {0xABu, 0x38u}, - {0xB3u, 0x38u}, - {0xB5u, 0x07u}, - {0xD9u, 0x04u}, - {0xDCu, 0x10u}, - {0xDFu, 0x01u}, - {0x04u, 0x04u}, - {0x05u, 0x10u}, - {0x07u, 0x42u}, - {0x0Eu, 0xA2u}, - {0x0Fu, 0x08u}, - {0x15u, 0x48u}, - {0x16u, 0x08u}, - {0x17u, 0x11u}, - {0x1Eu, 0xA0u}, - {0x20u, 0x28u}, - {0x21u, 0x10u}, - {0x22u, 0x04u}, - {0x27u, 0x02u}, - {0x28u, 0x88u}, - {0x2Fu, 0x1Au}, - {0x30u, 0x20u}, - {0x32u, 0x04u}, - {0x36u, 0x10u}, - {0x37u, 0x49u}, - {0x39u, 0x20u}, - {0x3Bu, 0x44u}, - {0x3Du, 0x41u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x18u}, - {0x45u, 0x22u}, - {0x46u, 0x20u}, - {0x47u, 0x08u}, - {0x4Du, 0x80u}, - {0x4Eu, 0x20u}, - {0x4Fu, 0x18u}, - {0x56u, 0x55u}, - {0x57u, 0x40u}, - {0x65u, 0x04u}, - {0x66u, 0x50u}, - {0x7Cu, 0x02u}, - {0x87u, 0x04u}, - {0x90u, 0x24u}, - {0x91u, 0x88u}, - {0x93u, 0x50u}, - {0x94u, 0x02u}, + {0x3Fu, 0x11u}, + {0x48u, 0x08u}, + {0x49u, 0x20u}, + {0x60u, 0x02u}, + {0x61u, 0x20u}, + {0x63u, 0xA0u}, + {0x86u, 0x40u}, + {0x88u, 0x01u}, + {0x91u, 0x84u}, + {0x92u, 0x60u}, + {0x93u, 0x05u}, {0x95u, 0x41u}, - {0x96u, 0x18u}, - {0x97u, 0x0Cu}, - {0x98u, 0xCAu}, - {0x99u, 0x20u}, - {0x9Au, 0x80u}, - {0x9Bu, 0x08u}, - {0x9Du, 0x11u}, - {0x9Eu, 0x0Du}, - {0x9Fu, 0x11u}, - {0xA0u, 0x28u}, - {0xA2u, 0x02u}, - {0xA4u, 0x94u}, - {0xA5u, 0x20u}, - {0xA7u, 0x08u}, - {0xA8u, 0x20u}, - {0xAAu, 0x02u}, - {0xAFu, 0x10u}, - {0xB7u, 0x04u}, - {0xC0u, 0xF0u}, - {0xC2u, 0xF0u}, - {0xC4u, 0xF0u}, - {0xCAu, 0x75u}, - {0xCCu, 0xF6u}, - {0xCEu, 0xFEu}, - {0xD0u, 0xE0u}, - {0xD2u, 0x30u}, - {0xD8u, 0x70u}, - {0xDEu, 0x80u}, - {0xEAu, 0x08u}, - {0xEEu, 0x10u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x08u}, - {0xEAu, 0x08u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x08u}, - {0xABu, 0x01u}, - {0xAFu, 0x40u}, - {0xB0u, 0x04u}, - {0xB3u, 0x40u}, - {0xB5u, 0x01u}, - {0xB6u, 0x04u}, - {0xE2u, 0x01u}, - {0xE8u, 0x20u}, - {0xEAu, 0x49u}, - {0xEEu, 0x40u}, - {0x00u, 0x12u}, - {0x02u, 0x24u}, - {0x05u, 0x02u}, - {0x06u, 0x12u}, - {0x0Au, 0x0Cu}, - {0x0Eu, 0x02u}, - {0x11u, 0x06u}, - {0x13u, 0x08u}, - {0x16u, 0x60u}, - {0x17u, 0x0Du}, - {0x1Bu, 0x07u}, - {0x1Cu, 0x12u}, - {0x1Du, 0x07u}, - {0x1Eu, 0x48u}, - {0x1Fu, 0x08u}, - {0x20u, 0x01u}, - {0x21u, 0x02u}, - {0x25u, 0x01u}, - {0x26u, 0x10u}, - {0x27u, 0x02u}, - {0x29u, 0x10u}, - {0x30u, 0x01u}, - {0x32u, 0x70u}, - {0x33u, 0x08u}, - {0x34u, 0x0Eu}, - {0x35u, 0x10u}, - {0x37u, 0x07u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x14u}, - {0x40u, 0x31u}, - {0x41u, 0x04u}, - {0x42u, 0x60u}, - {0x45u, 0xEFu}, - {0x46u, 0x20u}, - {0x47u, 0xDCu}, - {0x48u, 0x3Bu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Fu, 0x2Cu}, - {0x56u, 0x01u}, + {0x96u, 0x0Cu}, + {0x97u, 0x10u}, + {0x98u, 0x42u}, + {0x99u, 0x06u}, + {0x9Au, 0xC4u}, + {0x9Bu, 0xA0u}, + {0x9Cu, 0x01u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x08u}, + {0xA1u, 0x20u}, + {0xA2u, 0x98u}, + {0xA3u, 0x15u}, + {0xA4u, 0x80u}, + {0xA5u, 0x40u}, + {0xA6u, 0x02u}, + {0xA7u, 0x4Au}, + {0xAAu, 0x10u}, + {0xACu, 0x50u}, + {0xAEu, 0x81u}, + {0xB4u, 0x40u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xF6u}, + {0xC4u, 0xDFu}, + {0xCAu, 0xEFu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xFFu}, + {0xD8u, 0x0Fu}, + {0xE2u, 0x09u}, + {0xE6u, 0x08u}, + {0xEAu, 0x02u}, + {0xECu, 0x04u}, + {0x38u, 0x80u}, + {0x3Eu, 0x40u}, + {0x58u, 0x04u}, + {0x5Fu, 0x01u}, + {0x1Fu, 0x80u}, + {0x8Au, 0x04u}, + {0x92u, 0x0Cu}, + {0x97u, 0x01u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x20u}, + {0xA3u, 0x08u}, + {0xAAu, 0x04u}, + {0xADu, 0x40u}, + {0xB5u, 0x08u}, + {0xE2u, 0x09u}, + {0xE6u, 0x28u}, + {0xE8u, 0x40u}, + {0x92u, 0x0Cu}, + {0x97u, 0x01u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x28u}, + {0xA1u, 0x40u}, + {0xA3u, 0x08u}, + {0xA6u, 0x04u}, + {0xA8u, 0x40u}, + {0xA9u, 0x04u}, + {0xAEu, 0x04u}, + {0xB0u, 0x20u}, + {0xB1u, 0x01u}, + {0xB6u, 0x08u}, + {0xB7u, 0x08u}, + {0xE0u, 0x20u}, + {0xEAu, 0x94u}, + {0xEEu, 0xA4u}, + {0x01u, 0x0Fu}, + {0x03u, 0xF0u}, + {0x04u, 0x50u}, + {0x05u, 0x30u}, + {0x06u, 0xA0u}, + {0x07u, 0xC0u}, + {0x08u, 0x06u}, + {0x09u, 0x50u}, + {0x0Au, 0x09u}, + {0x0Bu, 0xA0u}, + {0x0Cu, 0x03u}, + {0x0Du, 0x60u}, + {0x0Eu, 0x0Cu}, + {0x0Fu, 0x90u}, + {0x11u, 0xFFu}, + {0x12u, 0xFFu}, + {0x14u, 0xFFu}, + {0x15u, 0x05u}, + {0x17u, 0x0Au}, + {0x18u, 0x05u}, + {0x19u, 0x06u}, + {0x1Au, 0x0Au}, + {0x1Bu, 0x09u}, + {0x1Cu, 0x0Fu}, + {0x1Eu, 0xF0u}, + {0x1Fu, 0xFFu}, + {0x21u, 0x03u}, + {0x22u, 0xFFu}, + {0x23u, 0x0Cu}, + {0x24u, 0x30u}, + {0x26u, 0xC0u}, + {0x27u, 0xFFu}, + {0x2Cu, 0x60u}, + {0x2Eu, 0x90u}, + {0x35u, 0xFFu}, + {0x36u, 0xFFu}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x01u}, {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x66u, 0x80u}, - {0x68u, 0x40u}, - {0x69u, 0x40u}, - {0x6Eu, 0x08u}, - {0x81u, 0x02u}, - {0x84u, 0x02u}, - {0x89u, 0x01u}, - {0x8Du, 0x04u}, - {0xACu, 0x01u}, - {0xB3u, 0x01u}, - {0xB4u, 0x02u}, - {0xB5u, 0x02u}, - {0xB6u, 0x01u}, - {0xB7u, 0x04u}, - {0xBEu, 0x50u}, - {0xBFu, 0x54u}, + {0x84u, 0x10u}, + {0x86u, 0x09u}, + {0x87u, 0x10u}, + {0x8Bu, 0x08u}, + {0x8Du, 0x0Au}, + {0x8Fu, 0x14u}, + {0x90u, 0x08u}, + {0x92u, 0x10u}, + {0x93u, 0x04u}, + {0x94u, 0x04u}, + {0x95u, 0x01u}, + {0x9Cu, 0x19u}, + {0x9Eu, 0x62u}, + {0xA0u, 0x40u}, + {0xA2u, 0x22u}, + {0xABu, 0x02u}, + {0xACu, 0x20u}, + {0xAEu, 0x40u}, + {0xB0u, 0x04u}, + {0xB1u, 0x06u}, + {0xB2u, 0x03u}, + {0xB3u, 0x18u}, + {0xB4u, 0x78u}, + {0xB5u, 0x01u}, + {0xBEu, 0x15u}, + {0xBFu, 0x15u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, {0xDFu, 0x01u}, {0x01u, 0x08u}, - {0x05u, 0x10u}, - {0x06u, 0x60u}, - {0x07u, 0x01u}, - {0x08u, 0x08u}, - {0x09u, 0x08u}, - {0x0Du, 0x80u}, - {0x0Eu, 0x20u}, - {0x10u, 0x10u}, - {0x12u, 0x22u}, + {0x04u, 0x08u}, + {0x05u, 0x20u}, + {0x06u, 0x02u}, + {0x09u, 0x06u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x01u}, + {0x0Du, 0x50u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x21u}, + {0x11u, 0x02u}, + {0x12u, 0x01u}, {0x14u, 0x80u}, - {0x17u, 0x04u}, - {0x19u, 0xA0u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x10u}, - {0x1Eu, 0x20u}, - {0x20u, 0x01u}, - {0x21u, 0x08u}, - {0x23u, 0x04u}, - {0x25u, 0x80u}, - {0x26u, 0xA8u}, - {0x2Cu, 0x04u}, - {0x2Du, 0x02u}, + {0x15u, 0x44u}, + {0x18u, 0xA0u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x30u}, + {0x1Fu, 0x80u}, + {0x22u, 0x2Au}, + {0x27u, 0x08u}, + {0x29u, 0x20u}, {0x2Eu, 0x02u}, - {0x2Fu, 0x10u}, - {0x34u, 0x20u}, - {0x36u, 0x80u}, - {0x37u, 0x0Au}, - {0x39u, 0x20u}, - {0x3Bu, 0x81u}, + {0x2Fu, 0x20u}, + {0x31u, 0x08u}, + {0x33u, 0x02u}, + {0x34u, 0x83u}, + {0x35u, 0x20u}, + {0x36u, 0x04u}, + {0x38u, 0x08u}, + {0x39u, 0xA0u}, + {0x3Du, 0x91u}, {0x3Eu, 0x04u}, - {0x3Fu, 0x08u}, - {0x45u, 0x80u}, - {0x46u, 0x60u}, - {0x47u, 0x0Au}, - {0x4Eu, 0x58u}, - {0x55u, 0x10u}, - {0x56u, 0x02u}, - {0x57u, 0x04u}, - {0x59u, 0x02u}, - {0x5Au, 0xA4u}, - {0x5Cu, 0x49u}, - {0x5Du, 0x20u}, - {0x64u, 0x10u}, - {0x65u, 0x80u}, - {0x67u, 0x44u}, - {0x6Eu, 0x08u}, - {0x6Fu, 0x45u}, - {0x74u, 0xA4u}, - {0x75u, 0x01u}, - {0x81u, 0x10u}, - {0x82u, 0x02u}, - {0x83u, 0x40u}, - {0x84u, 0xA0u}, - {0x85u, 0x80u}, - {0x88u, 0x04u}, - {0x89u, 0x10u}, - {0x8Au, 0x10u}, - {0x8Du, 0x18u}, - {0x93u, 0x20u}, - {0x98u, 0xA0u}, - {0xB0u, 0x80u}, - {0xC0u, 0xF4u}, - {0xC2u, 0xA0u}, - {0xC4u, 0x31u}, - {0xCAu, 0xE0u}, - {0xCCu, 0xF0u}, - {0xCEu, 0x4Du}, - {0xD0u, 0xD0u}, - {0xD2u, 0x20u}, - {0xD6u, 0xFFu}, - {0xD8u, 0xF0u}, - {0xE2u, 0xA1u}, - {0xE6u, 0x90u}, - {0xE8u, 0x42u}, - {0xEAu, 0x08u}, - {0xECu, 0x08u}, - {0x80u, 0x20u}, - {0x87u, 0x10u}, - {0xE0u, 0x80u}, - {0xE6u, 0x07u}, - {0xB4u, 0x04u}, - {0x00u, 0xD6u}, - {0x04u, 0xD2u}, - {0x05u, 0x40u}, - {0x06u, 0x04u}, - {0x07u, 0x30u}, - {0x08u, 0x29u}, - {0x09u, 0x58u}, - {0x0Au, 0x16u}, - {0x0Bu, 0x23u}, - {0x0Cu, 0x04u}, - {0x0Fu, 0x0Cu}, - {0x12u, 0x80u}, - {0x14u, 0x31u}, - {0x16u, 0x0Eu}, - {0x17u, 0x01u}, - {0x1Bu, 0x82u}, - {0x1Cu, 0x22u}, - {0x1Eu, 0x10u}, - {0x20u, 0xD6u}, - {0x24u, 0x17u}, - {0x25u, 0x34u}, - {0x26u, 0x28u}, - {0x27u, 0x43u}, - {0x28u, 0xD0u}, - {0x29u, 0x11u}, - {0x2Au, 0x06u}, - {0x2Bu, 0x62u}, - {0x2Cu, 0x06u}, - {0x2Eu, 0xD0u}, - {0x30u, 0x40u}, - {0x32u, 0x80u}, - {0x33u, 0x80u}, - {0x34u, 0x0Fu}, - {0x35u, 0x70u}, - {0x36u, 0x30u}, - {0x37u, 0x0Fu}, - {0x38u, 0x20u}, - {0x39u, 0x02u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x20u}, - {0x3Eu, 0x05u}, {0x3Fu, 0x01u}, + {0x6Cu, 0x04u}, + {0x6Du, 0xD6u}, + {0x6Eu, 0x04u}, + {0x6Fu, 0x0Au}, + {0x74u, 0x20u}, + {0x75u, 0x80u}, + {0x76u, 0x11u}, + {0x77u, 0x80u}, + {0x82u, 0x20u}, + {0x86u, 0x02u}, + {0x88u, 0x80u}, + {0x89u, 0x02u}, + {0x8Au, 0x02u}, + {0x8Cu, 0x10u}, + {0x8Fu, 0x80u}, + {0x9Cu, 0x02u}, + {0x9Du, 0xA0u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x08u}, + {0xA1u, 0x08u}, + {0xA7u, 0x10u}, + {0xAEu, 0x10u}, + {0xB1u, 0x80u}, + {0xB7u, 0x10u}, + {0xC0u, 0xE4u}, + {0xC2u, 0xFDu}, + {0xC4u, 0xB9u}, + {0xCAu, 0xC4u}, + {0xCCu, 0xF3u}, + {0xCEu, 0xFEu}, + {0xE0u, 0xA2u}, + {0xE2u, 0x50u}, + {0xE4u, 0x20u}, + {0xE6u, 0x98u}, + {0xEAu, 0x14u}, + {0xEEu, 0x82u}, + {0x85u, 0x20u}, + {0x87u, 0x08u}, + {0x8Cu, 0x02u}, + {0x8Du, 0x08u}, + {0xE2u, 0x10u}, + {0xAFu, 0x10u}, + {0xB2u, 0x20u}, + {0xB4u, 0x40u}, + {0xEAu, 0x40u}, + {0xECu, 0x02u}, + {0x00u, 0x03u}, + {0x02u, 0x0Cu}, + {0x04u, 0x60u}, + {0x05u, 0x01u}, + {0x06u, 0x90u}, + {0x07u, 0x02u}, + {0x0Bu, 0x10u}, + {0x0Cu, 0x0Fu}, + {0x0Eu, 0xF0u}, + {0x11u, 0x08u}, + {0x13u, 0x10u}, + {0x14u, 0x05u}, + {0x16u, 0x0Au}, + {0x17u, 0x01u}, + {0x18u, 0x06u}, + {0x1Au, 0x09u}, + {0x1Bu, 0x06u}, + {0x1Fu, 0x08u}, + {0x20u, 0x50u}, + {0x21u, 0x01u}, + {0x22u, 0xA0u}, + {0x23u, 0x04u}, + {0x24u, 0x30u}, + {0x26u, 0xC0u}, + {0x2Fu, 0x01u}, + {0x34u, 0xFFu}, + {0x35u, 0x07u}, + {0x37u, 0x18u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x40u}, {0x56u, 0x02u}, {0x57u, 0x28u}, - {0x58u, 0x0Bu}, - {0x59u, 0x0Bu}, - {0x5Bu, 0x0Bu}, - {0x5Cu, 0x99u}, - {0x5Du, 0x90u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x84u, 0x05u}, - {0x86u, 0x0Au}, - {0x87u, 0x70u}, - {0x88u, 0x03u}, - {0x8Au, 0x0Cu}, - {0x8Bu, 0x80u}, - {0x8Cu, 0x30u}, - {0x8Eu, 0xC0u}, - {0x8Fu, 0x04u}, - {0x95u, 0x09u}, - {0x97u, 0x14u}, - {0x98u, 0x06u}, - {0x99u, 0x01u}, - {0x9Au, 0x09u}, + {0x86u, 0xECu}, + {0x87u, 0xFFu}, + {0x8Bu, 0xFFu}, + {0x8Du, 0x0Fu}, + {0x8Eu, 0x01u}, + {0x8Fu, 0xF0u}, + {0x91u, 0x30u}, + {0x93u, 0xC0u}, + {0x98u, 0x04u}, + {0x99u, 0x05u}, + {0x9Au, 0x43u}, {0x9Bu, 0x0Au}, - {0x9Du, 0x40u}, - {0x9Fu, 0x80u}, - {0xA0u, 0x0Fu}, - {0xA1u, 0x0Eu}, - {0xA2u, 0xF0u}, - {0xA3u, 0x21u}, - {0xA4u, 0x60u}, - {0xA6u, 0x90u}, - {0xA8u, 0x50u}, - {0xAAu, 0xA0u}, - {0xABu, 0x07u}, - {0xAFu, 0x08u}, - {0xB1u, 0xC0u}, - {0xB2u, 0xFFu}, - {0xB3u, 0x38u}, - {0xB5u, 0x07u}, - {0xBEu, 0x04u}, - {0xBFu, 0x01u}, + {0x9Du, 0x03u}, + {0x9Eu, 0x12u}, + {0x9Fu, 0x0Cu}, + {0xA0u, 0xE0u}, + {0xA1u, 0x50u}, + {0xA3u, 0xA0u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x88u}, + {0xA9u, 0x09u}, + {0xAAu, 0x03u}, + {0xABu, 0x06u}, + {0xACu, 0x21u}, + {0xADu, 0x90u}, + {0xAEu, 0x02u}, + {0xAFu, 0x60u}, + {0xB0u, 0xE0u}, + {0xB3u, 0xFFu}, + {0xB4u, 0x0Fu}, + {0xB6u, 0x10u}, + {0xBEu, 0x01u}, + {0xBFu, 0x04u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x10u}, + {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x20u}, - {0x02u, 0x02u}, - {0x05u, 0x10u}, - {0x06u, 0x01u}, - {0x07u, 0x50u}, - {0x0Bu, 0x08u}, - {0x0Eu, 0x02u}, - {0x0Fu, 0x90u}, - {0x10u, 0x48u}, - {0x12u, 0x10u}, - {0x15u, 0x50u}, - {0x17u, 0x09u}, - {0x1Au, 0x10u}, - {0x1Du, 0x37u}, - {0x1Eu, 0x03u}, + {0x00u, 0x04u}, + {0x01u, 0x80u}, + {0x07u, 0xA2u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x01u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x08u}, + {0x10u, 0x40u}, + {0x12u, 0x02u}, + {0x13u, 0x10u}, + {0x16u, 0x60u}, + {0x18u, 0x44u}, + {0x19u, 0x80u}, {0x1Fu, 0x10u}, - {0x20u, 0x04u}, - {0x21u, 0x05u}, - {0x22u, 0x10u}, - {0x23u, 0x04u}, - {0x24u, 0x02u}, - {0x25u, 0x51u}, - {0x26u, 0x08u}, - {0x28u, 0x88u}, + {0x22u, 0x04u}, + {0x25u, 0x40u}, + {0x26u, 0x20u}, + {0x28u, 0xA0u}, + {0x29u, 0x10u}, {0x2Au, 0x80u}, - {0x2Eu, 0x20u}, - {0x2Fu, 0x10u}, - {0x30u, 0x40u}, - {0x32u, 0x14u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x40u}, + {0x30u, 0x01u}, + {0x32u, 0x90u}, + {0x35u, 0x10u}, {0x36u, 0x28u}, - {0x38u, 0x20u}, - {0x39u, 0x88u}, - {0x3Au, 0x10u}, - {0x3Bu, 0x08u}, - {0x3Du, 0x80u}, - {0x3Eu, 0x08u}, - {0x3Fu, 0x10u}, - {0x45u, 0x10u}, - {0x46u, 0x08u}, - {0x66u, 0x08u}, - {0x6Cu, 0x80u}, - {0x6Du, 0x50u}, - {0x6Fu, 0x58u}, - {0x77u, 0x01u}, - {0x7Cu, 0x02u}, - {0x83u, 0x12u}, - {0x8Du, 0x01u}, - {0x90u, 0x20u}, - {0x91u, 0x80u}, - {0x92u, 0x08u}, - {0x93u, 0x10u}, - {0x94u, 0x02u}, - {0x95u, 0x42u}, - {0x96u, 0x11u}, - {0x97u, 0x24u}, - {0x98u, 0xCAu}, - {0x99u, 0x20u}, - {0x9Au, 0xA1u}, - {0x9Bu, 0x08u}, - {0x9Du, 0x15u}, + {0x37u, 0x82u}, + {0x39u, 0x84u}, + {0x3Bu, 0x20u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x04u}, + {0x59u, 0x25u}, + {0x5Au, 0x80u}, + {0x63u, 0x82u}, + {0x66u, 0x04u}, + {0x69u, 0x80u}, + {0x6Bu, 0x02u}, + {0x6Cu, 0x20u}, + {0x6Du, 0x41u}, + {0x6Fu, 0xD9u}, + {0x74u, 0x80u}, + {0x76u, 0x02u}, + {0x81u, 0x40u}, + {0x8Fu, 0x40u}, + {0x91u, 0x04u}, + {0x92u, 0xE4u}, + {0x93u, 0x15u}, + {0x95u, 0x41u}, + {0x96u, 0x08u}, + {0x98u, 0xE1u}, + {0x99u, 0x27u}, + {0x9Au, 0xC4u}, + {0x9Bu, 0xA0u}, + {0x9Eu, 0x02u}, {0x9Fu, 0x51u}, - {0xA0u, 0x0Cu}, - {0xA2u, 0x22u}, - {0xA3u, 0x40u}, - {0xA4u, 0x80u}, - {0xA5u, 0x22u}, - {0xA6u, 0x01u}, - {0xA7u, 0x0Au}, - {0xB0u, 0x10u}, - {0xB1u, 0x01u}, - {0xB5u, 0x80u}, - {0xC0u, 0xF7u}, - {0xC2u, 0xB2u}, - {0xC4u, 0xFEu}, - {0xCAu, 0x6Du}, - {0xCCu, 0x6Eu}, - {0xCEu, 0x7Eu}, - {0xD8u, 0x40u}, - {0xDEu, 0x80u}, - {0xE2u, 0x10u}, - {0xEAu, 0x20u}, - {0xECu, 0x40u}, - {0x9Fu, 0x08u}, - {0xB2u, 0x40u}, - {0xECu, 0x80u}, - {0xB7u, 0x08u}, - {0xECu, 0x40u}, - {0x30u, 0x20u}, - {0x33u, 0x02u}, - {0x34u, 0x04u}, - {0x35u, 0x20u}, - {0x38u, 0x80u}, - {0x56u, 0x80u}, - {0x5Bu, 0x02u}, - {0x5Eu, 0x01u}, - {0x63u, 0x40u}, - {0x65u, 0x04u}, - {0x81u, 0x20u}, - {0x8Du, 0x04u}, - {0xCCu, 0xF0u}, - {0xCEu, 0x10u}, - {0xD4u, 0x40u}, + {0xA1u, 0x10u}, + {0xA2u, 0x9Au}, + {0xA3u, 0x05u}, + {0xA4u, 0xA0u}, + {0xA5u, 0x40u}, + {0xA7u, 0x88u}, + {0xB0u, 0xA0u}, + {0xB5u, 0x10u}, + {0xC0u, 0xB5u}, + {0xC2u, 0x63u}, + {0xC4u, 0x3Bu}, + {0xCAu, 0x9Fu}, + {0xCCu, 0xFDu}, + {0xCEu, 0x6Eu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x49u}, + {0xE0u, 0x01u}, + {0xE6u, 0x40u}, + {0xEEu, 0x06u}, + {0x83u, 0x01u}, + {0x97u, 0x01u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x20u}, + {0xABu, 0x80u}, + {0xB2u, 0x04u}, + {0xB3u, 0x08u}, + {0xB7u, 0x80u}, + {0xEAu, 0xA0u}, + {0xEEu, 0x12u}, + {0xACu, 0x02u}, + {0xB1u, 0x20u}, + {0xE8u, 0x20u}, + {0x12u, 0x08u}, + {0x15u, 0x80u}, + {0x17u, 0x01u}, + {0x33u, 0x01u}, + {0x36u, 0x88u}, + {0x38u, 0x01u}, + {0x39u, 0x80u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x80u}, + {0x43u, 0x10u}, + {0x50u, 0x80u}, + {0x5Au, 0x04u}, + {0x5Du, 0x02u}, + {0x61u, 0x20u}, + {0x64u, 0x08u}, + {0x89u, 0x40u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x20u}, + {0xC4u, 0xE0u}, + {0xCCu, 0xE0u}, + {0xCEu, 0xF0u}, + {0xD0u, 0x10u}, + {0xD4u, 0x20u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE6u, 0x80u}, - {0x51u, 0x02u}, - {0x56u, 0x20u}, - {0x5Eu, 0x01u}, - {0x5Fu, 0x20u}, - {0x8Eu, 0x20u}, - {0x94u, 0x80u}, - {0x97u, 0x40u}, - {0x9Cu, 0x04u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x02u}, - {0xA4u, 0x20u}, - {0xAFu, 0x02u}, - {0xB2u, 0x01u}, - {0xD4u, 0xC0u}, - {0xD6u, 0xA0u}, + {0x31u, 0x20u}, + {0x32u, 0x04u}, + {0x36u, 0x40u}, + {0x37u, 0x04u}, + {0x50u, 0x08u}, + {0x51u, 0x01u}, + {0x55u, 0x08u}, + {0x5Du, 0x02u}, + {0x81u, 0x02u}, + {0x89u, 0x01u}, + {0x94u, 0x04u}, + {0x96u, 0x04u}, + {0x9Cu, 0x08u}, + {0x9Fu, 0x10u}, + {0xA6u, 0x80u}, + {0xACu, 0x80u}, + {0xADu, 0x02u}, + {0xCCu, 0xF0u}, + {0xD4u, 0xE0u}, + {0xD6u, 0x80u}, + {0xE6u, 0x20u}, {0xEAu, 0x10u}, - {0x10u, 0x20u}, - {0x80u, 0x40u}, - {0x83u, 0x80u}, - {0x86u, 0x81u}, - {0x87u, 0x02u}, - {0x94u, 0x80u}, - {0x96u, 0x01u}, - {0x97u, 0x40u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x04u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x02u}, - {0xA4u, 0x20u}, - {0xA5u, 0x02u}, - {0xABu, 0x20u}, - {0xB7u, 0x40u}, + {0xEEu, 0x10u}, + {0x12u, 0x80u}, + {0x80u, 0x08u}, + {0x86u, 0x04u}, + {0x89u, 0x02u}, + {0x8Cu, 0x08u}, + {0x96u, 0x0Cu}, + {0x9Cu, 0x08u}, + {0x9Fu, 0x14u}, + {0xA4u, 0x08u}, + {0xA5u, 0x20u}, + {0xA6u, 0xC0u}, + {0xB4u, 0x04u}, + {0xB5u, 0x08u}, {0xC4u, 0x10u}, - {0xE2u, 0xD0u}, - {0xE4u, 0x20u}, - {0xE6u, 0x40u}, - {0xEAu, 0x80u}, - {0x86u, 0x80u}, - {0x97u, 0x40u}, - {0x9Bu, 0x40u}, - {0xA1u, 0x80u}, - {0xA7u, 0x80u}, - {0xACu, 0x04u}, - {0xADu, 0x80u}, - {0xB5u, 0x02u}, - {0xE4u, 0x10u}, - {0xEAu, 0x10u}, - {0xEEu, 0x40u}, - {0x0Bu, 0x02u}, - {0x0Fu, 0x40u}, - {0x10u, 0x10u}, - {0x52u, 0x80u}, - {0x54u, 0x40u}, - {0x58u, 0x20u}, - {0x5Eu, 0x20u}, - {0x80u, 0x02u}, - {0x83u, 0x01u}, - {0x87u, 0x40u}, - {0x88u, 0x20u}, + {0xE2u, 0xC0u}, + {0x63u, 0x08u}, + {0x83u, 0x04u}, + {0x85u, 0x20u}, + {0x86u, 0x04u}, + {0x87u, 0x08u}, + {0x96u, 0x08u}, + {0x9Du, 0x02u}, + {0x9Fu, 0x14u}, + {0xA5u, 0x20u}, + {0xA6u, 0x40u}, + {0xD8u, 0x40u}, + {0xE2u, 0x90u}, + {0xE6u, 0x50u}, + {0x09u, 0x80u}, + {0x0Eu, 0x80u}, + {0x13u, 0x01u}, + {0x50u, 0x80u}, + {0x51u, 0x02u}, + {0x54u, 0x04u}, + {0x56u, 0x01u}, + {0x8Fu, 0x01u}, {0xC2u, 0x06u}, {0xC4u, 0x08u}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0xE0u, 0x01u}, - {0x00u, 0x20u}, - {0x06u, 0x40u}, - {0x07u, 0x04u}, - {0x09u, 0x02u}, - {0x0Bu, 0x04u}, + {0xE6u, 0x08u}, + {0x02u, 0x08u}, + {0x05u, 0x40u}, + {0x06u, 0x20u}, + {0x08u, 0x24u}, + {0x0Du, 0x08u}, {0x0Eu, 0x08u}, - {0x0Fu, 0x10u}, - {0x81u, 0x02u}, - {0x8Au, 0x40u}, - {0x8Bu, 0x04u}, - {0x8Eu, 0x04u}, - {0x9Cu, 0x02u}, - {0xA4u, 0x02u}, - {0xACu, 0x42u}, - {0xAEu, 0x10u}, - {0xB0u, 0x10u}, - {0xB6u, 0x80u}, + {0x84u, 0x20u}, + {0x85u, 0x02u}, + {0x88u, 0x04u}, + {0x8Cu, 0x80u}, + {0x8Du, 0x88u}, + {0x9Eu, 0x21u}, + {0xA1u, 0x80u}, + {0xA4u, 0x84u}, + {0xA5u, 0x02u}, + {0xAAu, 0x20u}, + {0xAEu, 0x40u}, {0xC0u, 0x07u}, {0xC2u, 0x0Fu}, - {0xE2u, 0x02u}, - {0xE6u, 0x05u}, - {0xE8u, 0x02u}, - {0xEAu, 0x04u}, - {0x81u, 0x40u}, - {0x9Cu, 0x02u}, - {0xA4u, 0x02u}, - {0xABu, 0x04u}, - {0xAFu, 0x10u}, - {0xB0u, 0x10u}, - {0xEEu, 0x01u}, - {0x08u, 0x02u}, - {0x0Au, 0x01u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x40u}, - {0x95u, 0x80u}, - {0x96u, 0x01u}, - {0x9Cu, 0x02u}, - {0xA4u, 0x02u}, - {0xAEu, 0x01u}, + {0xE2u, 0x08u}, + {0xE4u, 0x02u}, + {0xE6u, 0x09u}, + {0x88u, 0x04u}, + {0xA4u, 0x04u}, + {0xAAu, 0x0Cu}, + {0xB1u, 0x40u}, + {0xB6u, 0x01u}, + {0xE0u, 0x04u}, + {0xEAu, 0x01u}, + {0xECu, 0x02u}, + {0x0Bu, 0x88u}, + {0x0Fu, 0x41u}, + {0x83u, 0x01u}, + {0x87u, 0x44u}, {0xC2u, 0x0Fu}, - {0x26u, 0x80u}, - {0x65u, 0x04u}, - {0x8Du, 0x04u}, - {0x9Bu, 0x40u}, + {0x8Fu, 0x10u}, + {0x9Du, 0x02u}, {0x9Fu, 0x10u}, - {0xA1u, 0x80u}, - {0xA6u, 0x80u}, - {0xA7u, 0x80u}, - {0xB3u, 0x40u}, - {0xB7u, 0x10u}, - {0xC8u, 0x20u}, - {0xD8u, 0x80u}, - {0x07u, 0x10u}, - {0x1Bu, 0x80u}, - {0x51u, 0x80u}, - {0x5Bu, 0x40u}, - {0x9Bu, 0x40u}, - {0x9Fu, 0x10u}, - {0xA1u, 0x80u}, - {0xA7u, 0x80u}, + {0xA3u, 0x08u}, + {0xABu, 0x04u}, + {0xAEu, 0x40u}, + {0xEEu, 0x60u}, + {0x05u, 0x02u}, + {0x57u, 0x08u}, + {0x5Du, 0x40u}, + {0x91u, 0x40u}, + {0x9Du, 0x02u}, + {0xA3u, 0x08u}, + {0xB5u, 0x40u}, {0xC0u, 0x20u}, - {0xC6u, 0x40u}, - {0xD4u, 0xA0u}, - {0x00u, 0x02u}, - {0x01u, 0x01u}, - {0x08u, 0x02u}, - {0x09u, 0x01u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x01u}, - {0x0Eu, 0x02u}, - {0x10u, 0x02u}, - {0x11u, 0x01u}, - {0x1Au, 0x02u}, - {0x1Bu, 0x01u}, - {0x00u, 0xABu}, - {0x01u, 0x02u}, + {0xD4u, 0x40u}, + {0xD6u, 0x20u}, + {0xAFu, 0x40u}, + {0x00u, 0x03u}, + {0x08u, 0x03u}, + {0x0Au, 0x03u}, + {0x10u, 0x03u}, + {0x1Au, 0x03u}, + {0x00u, 0xFDu}, + {0x01u, 0xABu}, + {0x02u, 0x02u}, + {0x10u, 0x55u}, }; @@ -1474,28 +1549,28 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, }; - /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = { - 0x01u, 0x80u, 0x00u, 0x00u, 0x07u, 0x00u, 0x18u, 0x9Fu, 0x08u, 0x7Fu, 0x21u, 0x80u, 0x40u, 0x90u, 0x00u, 0x40u, - 0x40u, 0xC0u, 0x00u, 0x01u, 0x04u, 0x1Fu, 0x00u, 0x20u, 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x02u, - 0x01u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x08u, 0xFFu, 0x01u, 0xC0u, 0x00u, 0x08u, 0x01u, 0xC0u, 0x00u, 0x04u, - 0x3Fu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x0Au, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, - 0x26u, 0x03u, 0x40u, 0x00u, 0x05u, 0x0Bu, 0xFDu, 0xCEu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x04u, 0x0Bu, 0x0Bu, 0x09u, 0x99u, 0x00u, 0x01u, + /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { + 0x8Du, 0x00u, 0x00u, 0x00u, 0x8Du, 0x09u, 0x00u, 0x12u, 0x8Du, 0x00u, 0x00u, 0x01u, 0x0Du, 0x00u, 0x80u, 0x30u, + 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x80u, 0x09u, 0x12u, 0x00u, 0x44u, 0x06u, 0x60u, 0x00u, 0x00u, 0x08u, + 0x8Du, 0x09u, 0x00u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x18u, 0x00u, 0x11u, 0x00u, 0x22u, 0x00u, + 0x0Fu, 0x38u, 0x00u, 0x00u, 0x80u, 0x07u, 0x70u, 0x00u, 0x80u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, + 0x26u, 0x05u, 0x40u, 0x00u, 0x03u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, }; uint8 CYDATA i; @@ -1519,6 +1594,12 @@ void cyfitter_cfg(void) cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + /* Perform normal device configuration. Order is not critical for these items. */ + CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u); + /* Enable digital routing */ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc old mode 100755 new mode 100644 index e2cddad..b4c3cb6 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -6,13 +6,33 @@ /* Debug_Timer_Interrupt */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set Debug_Timer_Interrupt__INTC_MASK, 0x01 -.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x02 +.set Debug_Timer_Interrupt__INTC_NUMBER, 1 .set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 -.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 .set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_RX_DMA_COMPLETE */ +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA_COMPLETE */ +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + /* Debug_Timer_TimerHW */ .set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 .set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 @@ -31,6 +51,26 @@ .set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 .set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 +/* SD_RX_DMA_COMPLETE */ +.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SD_TX_DMA_COMPLETE */ +.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 @@ -44,41 +84,41 @@ /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL /* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 @@ -93,15 +133,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL /* USBFS_arb_int */ .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -126,24 +166,24 @@ /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -616,8 +656,8 @@ .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -625,13 +665,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -641,26 +681,30 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1 +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1 /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1104,6 +1148,30 @@ .set SCSI_In_DBx__DB7__SHIFT, 1 .set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 + /* SD_Data_Clk */ .set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 .set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 @@ -1140,85 +1208,68 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 .set scsiTarget_StatusReg__3__POS, 3 -.set scsiTarget_StatusReg__MASK, 0x0F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_StatusReg__4__MASK, 0x10 +.set scsiTarget_StatusReg__4__POS, 4 +.set scsiTarget_StatusReg__MASK, 0x1F +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ -.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 -.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__REMOVED, 1 /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1233,43 +1284,67 @@ /* USBFS_ep_1 */ .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x02 -.set USBFS_ep_1__INTC_NUMBER, 1 +.set USBFS_ep_1__INTC_MASK, 0x20 +.set USBFS_ep_1__INTC_NUMBER, 5 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x04 -.set USBFS_ep_2__INTC_NUMBER, 2 +.set USBFS_ep_2__INTC_MASK, 0x40 +.set USBFS_ep_2__INTC_NUMBER, 6 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x08 -.set USBFS_ep_3__INTC_NUMBER, 3 +.set USBFS_ep_3__INTC_MASK, 0x80 +.set USBFS_ep_3__INTC_NUMBER, 7 .set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x10 -.set USBFS_ep_4__INTC_NUMBER, 4 +.set USBFS_ep_4__INTC_MASK, 0x100 +.set USBFS_ep_4__INTC_NUMBER, 8 .set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SD_RX_DMA */ +.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SD_RX_DMA__DRQ_NUMBER, 2 +.set SD_RX_DMA__NUMBEROF_TDS, 0 +.set SD_RX_DMA__PRIORITY, 1 +.set SD_RX_DMA__TERMIN_EN, 0 +.set SD_RX_DMA__TERMIN_SEL, 0 +.set SD_RX_DMA__TERMOUT0_EN, 1 +.set SD_RX_DMA__TERMOUT0_SEL, 2 +.set SD_RX_DMA__TERMOUT1_EN, 0 +.set SD_RX_DMA__TERMOUT1_SEL, 0 + +/* SD_TX_DMA */ +.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SD_TX_DMA__DRQ_NUMBER, 3 +.set SD_TX_DMA__NUMBEROF_TDS, 0 +.set SD_TX_DMA__PRIORITY, 2 +.set SD_TX_DMA__TERMIN_EN, 0 +.set SD_TX_DMA__TERMIN_SEL, 0 +.set SD_TX_DMA__TERMOUT0_EN, 1 +.set SD_TX_DMA__TERMOUT0_SEL, 3 +.set SD_TX_DMA__TERMOUT1_EN, 0 +.set SD_TX_DMA__TERMOUT1_SEL, 0 + /* USBFS_USB */ .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG @@ -2789,9 +2864,9 @@ .set CYDEV_CHIP_FAMILY_PSOC5, 3 .set CYDEV_CHIP_DIE_PSOC5LP, 4 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP -.set BCLK__BUS_CLK__HZ, 60000000 -.set BCLK__BUS_CLK__KHZ, 60000 -.set BCLK__BUS_CLK__MHZ, 60 +.set BCLK__BUS_CLK__HZ, 50000000 +.set BCLK__BUS_CLK__KHZ, 50000 +.set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT .set CYDEV_CHIP_DIE_LEOPARD, 1 .set CYDEV_CHIP_DIE_PANTHER, 3 @@ -2852,7 +2927,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x00000001 +.set CYDEV_INTR_RISING, 0x0000001E .set CYDEV_PROJ_TYPE, 2 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 .set CYDEV_PROJ_TYPE_LOADABLE, 2 @@ -2876,6 +2951,6 @@ .set CYDEV_VIO2, 5 .set CYDEV_VIO2_MV, 5000 .set CYDEV_VIO3_MV, 3300 -.set DMA_CHANNELS_USED__MASK0, 0x00000000 +.set DMA_CHANNELS_USED__MASK0, 0x0000000F .set CYDEV_BOOTLOADER_ENABLE, 0 .endif diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc old mode 100755 new mode 100644 index 93e3430..b9e9e28 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -6,13 +6,33 @@ /* Debug_Timer_Interrupt */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x01 -Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x02 +Debug_Timer_Interrupt__INTC_NUMBER EQU 1 Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_RX_DMA_COMPLETE */ +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA_COMPLETE */ +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + /* Debug_Timer_TimerHW */ Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 @@ -31,6 +51,26 @@ Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 +/* SD_RX_DMA_COMPLETE */ +SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SD_TX_DMA_COMPLETE */ +SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -44,41 +84,41 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL /* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -93,15 +133,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL /* USBFS_arb_int */ USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -126,24 +166,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -616,8 +656,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -625,13 +665,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -641,26 +681,30 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1104,6 +1148,30 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 1 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 + /* SD_Data_Clk */ SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 @@ -1140,85 +1208,68 @@ timer_clock__PM_STBY_MSK EQU 0x04 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 -scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_StatusReg__4__MASK EQU 0x10 +scsiTarget_StatusReg__4__POS EQU 4 +scsiTarget_StatusReg__MASK EQU 0x1F +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ -SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1 /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1233,43 +1284,67 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_1 */ USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x02 -USBFS_ep_1__INTC_NUMBER EQU 1 +USBFS_ep_1__INTC_MASK EQU 0x20 +USBFS_ep_1__INTC_NUMBER EQU 5 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x04 -USBFS_ep_2__INTC_NUMBER EQU 2 +USBFS_ep_2__INTC_MASK EQU 0x40 +USBFS_ep_2__INTC_NUMBER EQU 6 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x08 -USBFS_ep_3__INTC_NUMBER EQU 3 +USBFS_ep_3__INTC_MASK EQU 0x80 +USBFS_ep_3__INTC_NUMBER EQU 7 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x10 -USBFS_ep_4__INTC_NUMBER EQU 4 +USBFS_ep_4__INTC_MASK EQU 0x100 +USBFS_ep_4__INTC_NUMBER EQU 8 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SD_RX_DMA */ +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__NUMBEROF_TDS EQU 0 +SD_RX_DMA__PRIORITY EQU 1 +SD_RX_DMA__TERMIN_EN EQU 0 +SD_RX_DMA__TERMIN_SEL EQU 0 +SD_RX_DMA__TERMOUT0_EN EQU 1 +SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT1_EN EQU 0 +SD_RX_DMA__TERMOUT1_SEL EQU 0 + +/* SD_TX_DMA */ +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__NUMBEROF_TDS EQU 0 +SD_TX_DMA__PRIORITY EQU 2 +SD_TX_DMA__TERMIN_EN EQU 0 +SD_TX_DMA__TERMIN_SEL EQU 0 +SD_TX_DMA__TERMOUT0_EN EQU 1 +SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT1_EN EQU 0 +SD_TX_DMA__TERMOUT1_SEL EQU 0 + /* USBFS_USB */ USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG @@ -2789,9 +2864,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 CYDEV_CHIP_DIE_PSOC5LP EQU 4 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP -BCLK__BUS_CLK__HZ EQU 60000000 -BCLK__BUS_CLK__KHZ EQU 60000 -BCLK__BUS_CLK__MHZ EQU 60 +BCLK__BUS_CLK__HZ EQU 50000000 +BCLK__BUS_CLK__KHZ EQU 50000 +BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD EQU 1 CYDEV_CHIP_DIE_PANTHER EQU 3 @@ -2852,7 +2927,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000001 +CYDEV_INTR_RISING EQU 0x0000001E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 @@ -2876,7 +2951,7 @@ CYDEV_VIO1_MV EQU 5000 CYDEV_VIO2 EQU 5 CYDEV_VIO2_MV EQU 5000 CYDEV_VIO3_MV EQU 3300 -DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +DMA_CHANNELS_USED__MASK0 EQU 0x0000000F CYDEV_BOOTLOADER_ENABLE EQU 0 #endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc old mode 100755 new mode 100644 index 3768761..79c7a64 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -6,13 +6,33 @@ INCLUDED_CYFITTERRV_INC EQU 1 ; Debug_Timer_Interrupt Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -Debug_Timer_Interrupt__INTC_MASK EQU 0x01 -Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x02 +Debug_Timer_Interrupt__INTC_NUMBER EQU 1 Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 -Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_RX_DMA_COMPLETE +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA_COMPLETE +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + ; Debug_Timer_TimerHW Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 @@ -31,6 +51,26 @@ Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 +; SD_RX_DMA_COMPLETE +SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SD_TX_DMA_COMPLETE +SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -44,41 +84,41 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL ; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 @@ -93,15 +133,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL ; USBFS_arb_int USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -126,24 +166,24 @@ USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -616,8 +656,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -625,13 +665,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -641,26 +681,30 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1104,6 +1148,30 @@ SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS SCSI_In_DBx__DB7__SHIFT EQU 1 SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 + ; SD_Data_Clk SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 @@ -1140,85 +1208,68 @@ timer_clock__PM_STBY_MSK EQU 0x04 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 -scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_StatusReg__4__MASK EQU 0x10 +scsiTarget_StatusReg__4__POS EQU 4 +scsiTarget_StatusReg__MASK EQU 0x1F +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL ; SD_Clk_Ctl -SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1 ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1233,43 +1284,67 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_1 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x02 -USBFS_ep_1__INTC_NUMBER EQU 1 +USBFS_ep_1__INTC_MASK EQU 0x20 +USBFS_ep_1__INTC_NUMBER EQU 5 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_2 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x04 -USBFS_ep_2__INTC_NUMBER EQU 2 +USBFS_ep_2__INTC_MASK EQU 0x40 +USBFS_ep_2__INTC_NUMBER EQU 6 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_3 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x08 -USBFS_ep_3__INTC_NUMBER EQU 3 +USBFS_ep_3__INTC_MASK EQU 0x80 +USBFS_ep_3__INTC_NUMBER EQU 7 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_4 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x10 -USBFS_ep_4__INTC_NUMBER EQU 4 +USBFS_ep_4__INTC_MASK EQU 0x100 +USBFS_ep_4__INTC_NUMBER EQU 8 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SD_RX_DMA +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__NUMBEROF_TDS EQU 0 +SD_RX_DMA__PRIORITY EQU 1 +SD_RX_DMA__TERMIN_EN EQU 0 +SD_RX_DMA__TERMIN_SEL EQU 0 +SD_RX_DMA__TERMOUT0_EN EQU 1 +SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT1_EN EQU 0 +SD_RX_DMA__TERMOUT1_SEL EQU 0 + +; SD_TX_DMA +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__NUMBEROF_TDS EQU 0 +SD_TX_DMA__PRIORITY EQU 2 +SD_TX_DMA__TERMIN_EN EQU 0 +SD_TX_DMA__TERMIN_SEL EQU 0 +SD_TX_DMA__TERMOUT0_EN EQU 1 +SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT1_EN EQU 0 +SD_TX_DMA__TERMOUT1_SEL EQU 0 + ; USBFS_USB USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG @@ -2789,9 +2864,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 CYDEV_CHIP_DIE_PSOC5LP EQU 4 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP -BCLK__BUS_CLK__HZ EQU 60000000 -BCLK__BUS_CLK__KHZ EQU 60000 -BCLK__BUS_CLK__MHZ EQU 60 +BCLK__BUS_CLK__HZ EQU 50000000 +BCLK__BUS_CLK__KHZ EQU 50000 +BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD EQU 1 CYDEV_CHIP_DIE_PANTHER EQU 3 @@ -2852,7 +2927,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000001 +CYDEV_INTR_RISING EQU 0x0000001E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 @@ -2876,7 +2951,7 @@ CYDEV_VIO1_MV EQU 5000 CYDEV_VIO2 EQU 5 CYDEV_VIO2_MV EQU 5000 CYDEV_VIO3_MV EQU 3300 -DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +DMA_CHANNELS_USED__MASK0 EQU 0x0000000F CYDEV_BOOTLOADER_ENABLE EQU 0 ENDIF END diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h old mode 100755 new mode 100644 index 01afa7d..b47a204 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -64,6 +64,14 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include #include #include #include diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx old mode 100755 new mode 100644 index 265ed9e..4acdeea --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,8 +1,72 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - @@ -10,10 +74,6 @@ - - - - @@ -94,93 +154,39 @@ + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + - - - - - - - - + + + + - - + + + + + + - - - - - - - - - - - + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr index 96ace51..21c2248 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit old mode 100755 new mode 100644 index 02f02b0..1850b93 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj index b2cb899..df39035 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2666,6 +2666,276 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd old mode 100755 new mode 100644 index 66a63b4..f326a56 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd @@ -7,18 +7,39 @@ 32 - USBFS - USBFS - 0x40004394 + SCSI_Out_Bits + No description available + 0x4000647C 0 - 0x1D0A + 0x1 registers - USBFS_PM_USB_CR0 - USB Power Mode Control Register 0 + SCSI_Out_Bits_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + + + Debug_Timer + No description available + 0x400043A3 + + 0 + 0xB64 + registers + + + + Debug_Timer_GLOBAL_ENABLE + PM.ACT.CFG 0x0 8 read-write @@ -26,115 +47,157 @@ 0 - fsusbio_ref_en - No description available + en_timer + Enable timer/counters. + 0 + 3 + read-write + + + + + Debug_Timer_CONTROL + TMRx.CFG0 + 0xB5D + 8 + read-write + 0 + 0 + + + EN + Enables timer/comparator. 0 0 read-write - fsusbio_pd_n - No description available + MODE + Mode. (0 = Timer; 1 = Comparator) 1 1 read-write + + + Timer + Timer mode. CNT/CMP register holds timer count value. + 0 + + + Comparator + Comparator mode. CNT/CMP register holds comparator threshold value. + 1 + + - fsusbio_pd_pullup_n - No description available + ONESHOT + Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. 2 2 read-write - - - - USBFS_PM_ACT_CFG - Active Power Mode Configuration Register - 0x11 - 8 - read-write - 0 - 0 - - - USBFS_PM_STBY_CFG - Standby Power Mode Configuration Register - 0x21 - 8 - read-write - 0 - 0 - - - USBFS_PRT_PS - Port Pin State Register - 0xE5D - 8 - read-write - 0 - 0 - - PinState_DP - No description available - 6 - 6 - read-only + CMP_BUFF + Buffer compare register. Compare register updates only on timer terminal count. + 3 + 3 + read-write - PinState_DM - No description available - 7 - 7 - read-only + INV + Invert sense of TIMEREN signal + 4 + 4 + read-write - - - - USBFS_PRT_DM0 - Port Drive Mode Register - 0xE5E - 8 - read-write - 0 - 0 - - DriveMode_DP - No description available - 6 - 6 + DB + Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. + 5 + 5 read-write + + + Timer + CMP and TC are output. + 0 + + + Deadband + PHI1 (instead of CMP) and PHI2 (instead of TC) are output. + 1 + + - DriveMode_DM - No description available - 7 + DEADBAND_PERIOD + Deadband Period + 6 7 read-write - USBFS_PRT_DM1 - Port Drive Mode Register - 0xE5F + Debug_Timer_CONTROL2 + TMRx.CFG1 + 0xB5E 8 read-write 0 0 - PullUp_en_DP - No description available - 6 + IRQ_SEL + Irq selection. (0 = raw interrupts; 1 = status register interrupts) + 0 + 0 + read-write + + + FTC + First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + 1 + 1 + read-write + + + Disable_FTC + Disable the single cycle pulse, which signifies the timer is starting. + 0 + + + Enable_FTC + Enable the single cycle pulse, which signifies the timer is starting. + 1 + + + + + DCOR + Disable Clear on Read (DCOR) of Status Register SR0. + 2 + 2 + read-write + + + DBMODE + Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + 3 + 3 + read-write + + + CLK_BUS_EN_SEL + Digital Global Clock selection. + 4 6 read-write - PullUp_en_DM - No description available + BUS_CLK_SEL + Bus Clock selection. 7 7 read-write @@ -142,24 +205,94 @@ - USBFS_PRT_INP_DIS - Input buffer disable override - 0xE64 + Debug_Timer_CONTROL3_ + TMRx.CFG2 + 0xB5F 8 read-write 0 0 - seinput_dis_dp - No description available - 6 + TMR_CFG + Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ + 0 + 1 + read-write + + + Continuous + Timer runs while EN bit of CFG0 register is set to '1'. + 0 + + + Pulsewidth + Timer runs from positive to negative edge of TIMEREN. + 1 + + + Period + Timer runs from positive to positive edge of TIMEREN. + 2 + + + Irq + Timer runs until IRQ. + 3 + + + + + COD + Clear On Disable (COD). Clears or gates outputs to zero. + 2 + 2 + read-write + + + ROD + Reset On Disable (ROD). Resets internal state of output logic + 3 + 3 + read-write + + + CMP_CFG + Comparator configurations + 4 6 read-write + + + Equal + Compare Equal + 0 + + + Less_than + Compare Less Than + 1 + + + Less_than_or_equal + Compare Less Than or Equal . + 2 + + + Greater + Compare Greater Than . + 3 + + + Greater_than_or_equal + Compare Greater Than or Equal + 4 + + - seinput_dis_dm - No description available + HW_EN + When set Timer Enable controls counting. 7 7 read-write @@ -167,182 +300,174 @@ - USBFS_EP0_DR0 - bmRequestType - 0x1C6C - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR1 - bRequest - 0x1C6D - 8 - read-write - 0 - 0 - - - USBFS_EP0_DR2 - wValueLo - 0x1C6E - 8 + Debug_Timer_PERIOD + TMRx.PER0 - Assigned Period + 0xB61 + 16 read-write 0 0 - USBFS_EP0_DR3 - wValueHi - 0x1C6F - 8 + Debug_Timer_COUNTER + TMRx.CNT_CMP0 - Current Down Counter Value + 0xB63 + 16 read-write 0 0 + + + + SCSI_Out_Ctl + No description available + 0x40006577 + + 0 + 0x1 + registers + + - USBFS_EP0_DR4 - wIndexLo - 0x1C70 + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x0 8 read-write 0 0 + + + + USBFS + USBFS + 0x40004394 + + 0 + 0x1D0A + registers + + - USBFS_EP0_DR5 - wIndexHi - 0x1C71 + USBFS_PM_USB_CR0 + USB Power Mode Control Register 0 + 0x0 8 read-write 0 0 + + + fsusbio_ref_en + No description available + 0 + 0 + read-write + + + fsusbio_pd_n + No description available + 1 + 1 + read-write + + + fsusbio_pd_pullup_n + No description available + 2 + 2 + read-write + + - USBFS_EP0_DR6 - lengthLo - 0x1C72 + USBFS_PM_ACT_CFG + Active Power Mode Configuration Register + 0x11 8 read-write 0 0 - USBFS_EP0_DR7 - lengthHi - 0x1C73 + USBFS_PM_STBY_CFG + Standby Power Mode Configuration Register + 0x21 8 read-write 0 0 - USBFS_CR0 - USB Control Register 0 - 0x1C74 + USBFS_PRT_PS + Port Pin State Register + 0xE5D 8 read-write 0 0 - device_address + PinState_DP No description available 6 - 0 + 6 read-only - usb_enable + PinState_DM No description available 7 7 - read-write + read-only - USBFS_CR1 - USB Control Register 1 - 0x1C75 + USBFS_PRT_DM0 + Port Drive Mode Register + 0xE5E 8 read-write 0 0 - reg_enable - No description available - 0 - 0 - read-write - - - enable_lock - No description available - 1 - 1 - read-write - - - bus_activity + DriveMode_DP No description available - 2 - 2 + 6 + 6 read-write - trim_offset_msb + DriveMode_DM No description available - 3 - 3 + 7 + 7 read-write - - USBFS_SIE_EP1_CR0 - The Endpoint1 Control Register - 0x1C7A - 8 - read-write - 0 - 0 - - - USBFS_USBIO_CR0 - USBIO Control Register 0 - 0x1C7C - 8 - read-write - 0 - 0 - - - rd - No description available - 0 - 0 - read-only - - - td - No description available - 5 - 5 - read-write - + + USBFS_PRT_DM1 + Port Drive Mode Register + 0xE5F + 8 + read-write + 0 + 0 + - tse0 + PullUp_en_DP No description available 6 6 read-write - ten + PullUp_en_DM No description available 7 7 @@ -351,316 +476,208 @@ - USBFS_USBIO_CR1 - USBIO Control Register 1 - 0x1C7E + USBFS_PRT_INP_DIS + Input buffer disable override + 0xE64 8 read-write 0 0 - dmo - No description available - 0 - 0 - read-only - - - dpo - No description available - 1 - 1 - read-only - - - usbpuen + seinput_dis_dp No description available - 2 - 2 + 6 + 6 read-write - iomode + seinput_dis_dm No description available - 5 - 5 + 7 + 7 read-write - USBFS_SIE_EP2_CR0 - The Endpoint2 Control Register - 0x1C8A - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP3_CR0 - The Endpoint3 Control Register - 0x1C9A - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP4_CR0 - The Endpoint4 Control Register - 0x1CAA - 8 - read-write - 0 - 0 - - - USBFS_SIE_EP5_CR0 - The Endpoint5 Control Register - 0x1CBA + USBFS_EP0_DR0 + bmRequestType + 0x1C6C 8 read-write 0 0 - USBFS_SIE_EP6_CR0 - The Endpoint6 Control Register - 0x1CCA + USBFS_EP0_DR1 + bRequest + 0x1C6D 8 read-write 0 0 - USBFS_SIE_EP7_CR0 - The Endpoint7 Control Register - 0x1CDA + USBFS_EP0_DR2 + wValueLo + 0x1C6E 8 read-write 0 0 - USBFS_SIE_EP8_CR0 - The Endpoint8 Control Register - 0x1CEA + USBFS_EP0_DR3 + wValueHi + 0x1C6F 8 read-write 0 0 - USBFS_BUF_SIZE - Dedicated Endpoint Buffer Size Register - 0x1CF8 + USBFS_EP0_DR4 + wIndexLo + 0x1C70 8 read-write 0 0 - USBFS_EP_ACTIVE - Endpoint Active Indication Register - 0x1CFA + USBFS_EP0_DR5 + wIndexHi + 0x1C71 8 read-write 0 0 - USBFS_EP_TYPE - Endpoint Type (IN/OUT) Indication - 0x1CFB + USBFS_EP0_DR6 + lengthLo + 0x1C72 8 read-write 0 0 - USBFS_USB_CLK_EN - USB Block Clock Enable Register - 0x1D09 + USBFS_EP0_DR7 + lengthHi + 0x1C73 8 read-write 0 0 - - - - Debug_Timer - No description available - 0x400043A3 - - 0 - 0xB64 - registers - - - Debug_Timer_GLOBAL_ENABLE - PM.ACT.CFG - 0x0 + USBFS_CR0 + USB Control Register 0 + 0x1C74 8 read-write 0 0 - en_timer - Enable timer/counters. - 0 - 3 + device_address + No description available + 6 + 0 + read-only + + + usb_enable + No description available + 7 + 7 read-write - Debug_Timer_CONTROL - TMRx.CFG0 - 0xB5D + USBFS_CR1 + USB Control Register 1 + 0x1C75 8 read-write 0 0 - EN - Enables timer/comparator. + reg_enable + No description available 0 0 read-write - MODE - Mode. (0 = Timer; 1 = Comparator) + enable_lock + No description available 1 1 read-write - - - Timer - Timer mode. CNT/CMP register holds timer count value. - 0 - - - Comparator - Comparator mode. CNT/CMP register holds comparator threshold value. - 1 - - - ONESHOT - Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. + bus_activity + No description available 2 2 read-write - CMP_BUFF - Buffer compare register. Compare register updates only on timer terminal count. + trim_offset_msb + No description available 3 3 read-write - - INV - Invert sense of TIMEREN signal - 4 - 4 - read-write - - - DB - Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. - 5 - 5 - read-write - - - Timer - CMP and TC are output. - 0 - - - Deadband - PHI1 (instead of CMP) and PHI2 (instead of TC) are output. - 1 - - - - - DEADBAND_PERIOD - Deadband Period - 6 - 7 - read-write - - Debug_Timer_CONTROL2 - TMRx.CFG1 - 0xB5E + USBFS_SIE_EP1_CR0 + The Endpoint1 Control Register + 0x1C7A 8 - read-write - 0 - 0 - - - IRQ_SEL - Irq selection. (0 = raw interrupts; 1 = status register interrupts) - 0 - 0 - read-write - - - FTC - First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. - 1 - 1 - read-write - - - Disable_FTC - Disable the single cycle pulse, which signifies the timer is starting. - 0 - - - Enable_FTC - Enable the single cycle pulse, which signifies the timer is starting. - 1 - - - + read-write + 0 + 0 + + + USBFS_USBIO_CR0 + USBIO Control Register 0 + 0x1C7C + 8 + read-write + 0 + 0 + - DCOR - Disable Clear on Read (DCOR) of Status Register SR0. - 2 - 2 - read-write + rd + No description available + 0 + 0 + read-only - DBMODE - Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). - 3 - 3 + td + No description available + 5 + 5 read-write - CLK_BUS_EN_SEL - Digital Global Clock selection. - 4 + tse0 + No description available + 6 6 read-write - BUS_CLK_SEL - Bus Clock selection. + ten + No description available 7 7 read-write @@ -668,176 +685,138 @@ - Debug_Timer_CONTROL3_ - TMRx.CFG2 - 0xB5F + USBFS_USBIO_CR1 + USBIO Control Register 1 + 0x1C7E 8 read-write 0 0 - TMR_CFG - Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ + dmo + No description available 0 + 0 + read-only + + + dpo + No description available + 1 1 - read-write - - - Continuous - Timer runs while EN bit of CFG0 register is set to '1'. - 0 - - - Pulsewidth - Timer runs from positive to negative edge of TIMEREN. - 1 - - - Period - Timer runs from positive to positive edge of TIMEREN. - 2 - - - Irq - Timer runs until IRQ. - 3 - - + read-only - COD - Clear On Disable (COD). Clears or gates outputs to zero. + usbpuen + No description available 2 2 read-write - ROD - Reset On Disable (ROD). Resets internal state of output logic - 3 - 3 - read-write - - - CMP_CFG - Comparator configurations - 4 - 6 - read-write - - - Equal - Compare Equal - 0 - - - Less_than - Compare Less Than - 1 - - - Less_than_or_equal - Compare Less Than or Equal . - 2 - - - Greater - Compare Greater Than . - 3 - - - Greater_than_or_equal - Compare Greater Than or Equal - 4 - - - - - HW_EN - When set Timer Enable controls counting. - 7 - 7 + iomode + No description available + 5 + 5 read-write - Debug_Timer_PERIOD - TMRx.PER0 - Assigned Period - 0xB61 - 16 + USBFS_SIE_EP2_CR0 + The Endpoint2 Control Register + 0x1C8A + 8 read-write 0 0 - Debug_Timer_COUNTER - TMRx.CNT_CMP0 - Current Down Counter Value - 0xB63 - 16 + USBFS_SIE_EP3_CR0 + The Endpoint3 Control Register + 0x1C9A + 8 read-write 0 0 - - - - SCSI_Out_Ctl - No description available - 0x40006473 - - 0 - 0x1 - registers - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x0 + USBFS_SIE_EP4_CR0 + The Endpoint4 Control Register + 0x1CAA 8 read-write 0 0 - - - - SCSI_Out_Bits - No description available - 0x40006470 - - 0 - 0x1 - registers - - - SCSI_Out_Bits_CONTROL_REG - No description available - 0x0 + USBFS_SIE_EP5_CR0 + The Endpoint5 Control Register + 0x1CBA 8 read-write 0 0 - - - - SD_Clk_Ctl - No description available - 0x40006472 - - 0 - 0x1 - registers - - - SD_Clk_Ctl_CONTROL_REG - No description available - 0x0 + USBFS_SIE_EP6_CR0 + The Endpoint6 Control Register + 0x1CCA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP7_CR0 + The Endpoint7 Control Register + 0x1CDA + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP8_CR0 + The Endpoint8 Control Register + 0x1CEA + 8 + read-write + 0 + 0 + + + USBFS_BUF_SIZE + Dedicated Endpoint Buffer Size Register + 0x1CF8 + 8 + read-write + 0 + 0 + + + USBFS_EP_ACTIVE + Endpoint Active Indication Register + 0x1CFA + 8 + read-write + 0 + 0 + + + USBFS_EP_TYPE + Endpoint Type (IN/OUT) Indication + 0x1CFB + 8 + read-write + 0 + 0 + + + USBFS_USB_CLK_EN + USB Block Clock Enable Register + 0x1D09 8 read-write 0 @@ -848,7 +827,7 @@ SCSI_CTL_PHASE No description available - 0x40006475 + 0x40006472 0 0x1 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index afb8fbd..3602a0d 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym index 2671f59..1eeb6a0 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym and b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v index 91dbc27..5d46c5a 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -27,7 +27,9 @@ module scsiTarget ( input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus. input IO, // Active High, set by CPU via status register. input nRST, // Active LOW, connected directly to SCSI bus. - input clk + input clk, + output tx_intr, + output rx_intr ); @@ -47,28 +49,6 @@ cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync .clock_out(op_clk) ); -///////////////////////////////////////////////////////////////////////////// -// FIFO Status Register -///////////////////////////////////////////////////////////////////////////// -// Status Register: scsiTarget_StatusReg__STATUS_REG -// Bit 0: Tx FIFO not full -// Bit 1: Rx FIFO not empty -// Bit 2: Tx FIFO empty -// Bit 3: Rx FIFO full -// -// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG -// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG -// Use with CY_GET_REG8 and CY_SET_REG8 -wire f0_bus_stat; // Tx FIFO not full -wire f0_blk_stat; // Tx FIFO empty -wire f1_bus_stat; // Rx FIFO not empty -wire f1_blk_stat; // Rx FIFO full -cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg -( - /* input */ .clock(op_clk), - /* input [04:00] */ .status({4'b0, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat}) -); - ///////////////////////////////////////////////////////////////////////////// // CONSTANTS ///////////////////////////////////////////////////////////////////////////// @@ -80,7 +60,7 @@ localparam IO_READ = 1'b0; ///////////////////////////////////////////////////////////////////////////// // TX States: // IDLE -// Wait for an entry in the FIFO, and for the SCSI Initiator to be ready +// Wait for the SCSI Initiator to be ready // FIFOLOAD // Load F0 into A0. Feed (old) A0 into the ALU SRCA. // TX @@ -91,11 +71,12 @@ localparam IO_READ = 1'b0; // Load deskew clock count into A0 from D0 // DESKEW // DBx output signals will be output in this state -// Wait for the SCSI deskew time of 55ms. (DEC A0). +// Wait for the SCSI deskew time of 55ns. (DEC A0). // A1 must be fed into SRCA, so PO is now useless. // READY // REQ and DBx output signals will be output in this state -// Wait for acknowledgement from the SCSI initiator. +// Wait for acknowledgement from the SCSI initiator +// Wait for space in output fifo // RX // Dummy state for flow control. // REQ signal will be output in this state @@ -103,8 +84,8 @@ localparam IO_READ = 1'b0; // // RX States: // IDLE -// Wait for a dummy "enabling" entry in the input FIFO, and wait for space -// in output the FIFO, and for the SCSI Initiator to be ready +// Wait for a dummy "enabling" entry in the input FIFO, +// and for the SCSI Initiator to be ready // FIFOLOAD // Load F0 into A0. // The input FIFO is used to control the number of bytes we attempt to @@ -112,6 +93,7 @@ localparam IO_READ = 1'b0; // READY // REQ signal will be output in this state // Wait for the initiator to send a byte on the SCSI bus. +// Wait for space in output fifo // RX // REQ signal will be output in this state // PI enabled for input into ALU "PASS" operation, storing into F1. @@ -152,6 +134,38 @@ assign DBx_out[7:0] = data; assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0; + +///////////////////////////////////////////////////////////////////////////// +// FIFO Status Register +///////////////////////////////////////////////////////////////////////////// +// Status Register: scsiTarget_StatusReg__STATUS_REG +// Bit 0: Tx FIFO not full +// Bit 1: Rx FIFO not empty +// Bit 2: Tx FIFO empty +// Bit 3: Rx FIFO full +// Bit 4: TX Complete. Fifos empty and idle. +// +// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG +// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG +// Use with CY_GET_REG8 and CY_SET_REG8 +wire f0_bus_stat; // Tx FIFO not full +wire f0_blk_stat; // Tx FIFO empty +wire f1_bus_stat; // Rx FIFO not empty +wire f1_blk_stat; // Rx FIFO full +wire txComplete = f0_blk_stat && (state == STATE_IDLE); +cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg +( + /* input */ .clock(op_clk), + /* input [04:00] */ .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat}) +); + +// DMA outputs +assign tx_intr = f0_bus_stat; +assign rx_intr = f1_bus_stat; + +///////////////////////////////////////////////////////////////////////////// +// State machine +///////////////////////////////////////////////////////////////////////////// always @(posedge op_clk) begin case (state) STATE_IDLE: @@ -160,7 +174,7 @@ always @(posedge op_clk) begin // and output FIFO is not full. // Note that output FIFO is unused in TX mode. if (!nRST) state <= STATE_IDLE; - else if (nACK & !f0_blk_stat && !f1_blk_stat) + else if (nACK & !f0_blk_stat) state <= STATE_FIFOLOAD; else state <= STATE_IDLE; @@ -191,68 +205,74 @@ always @(posedge op_clk) begin STATE_READY: if (!nRST) state <= STATE_IDLE; - else if (~nACK) state <= STATE_RX; + else if (~nACK && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_RX; else state <= STATE_READY; - STATE_RX: state <= STATE_IDLE; + STATE_RX: // same code here as for the IDLE state, as we make + // a quick run back to the next byte if possible. + if (!nRST) state <= STATE_IDLE; + else if (nACK & !f0_blk_stat) + state <= STATE_FIFOLOAD; + else + state <= STATE_IDLE; default: state <= STATE_IDLE; endcase end -// D1 is used for the deskew count. +// D0 is used for the deskew count. // The data output is valid during the DESKEW_INIT phase as well, // so we subtract 1. -// D1 = [0.000000055 / (1 / clk)] - 1 -cy_psoc3_dp #(.d1_init(1), +// D0 = [0.000000055 / (1 / clk)] - 1 +cy_psoc3_dp #(.d0_init(2), .cy_dpconfig( { `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/ + `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/ + `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/ + `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/ + `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/ `CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/ + `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/ + `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/ + `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, - `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/ - 8'hFF, 8'h00, /*CFG9: */ - 8'hFF, 8'hFF, /*CFG11-10: */ + `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/ + 8'hFF, 8'h00, /*CFG9: */ + 8'hFF, 8'hFF, /*CFG11-10: */ `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH, `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI, - `SC_SI_A_DEFSI, /*CFG13-12: */ + `SC_SI_A_DEFSI, /*CFG13-12: */ `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN, 1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS, `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN, `SC_FB_NOCHN, `SC_CMP1_NOCHN, - `SC_CMP0_NOCHN, /*CFG15-14: */ + `SC_CMP0_NOCHN, /*CFG15-14: */ 10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX, `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL, - `SC_WRK16CAT_DSBL /*CFG17-16: */ + `SC_WRK16CAT_DSBL /*CFG17-16: */ } )) datapath( /* input */ .reset(1'b0), @@ -308,3 +328,4 @@ cy_psoc3_dp #(.d1_init(1), endmodule //`#start footer` -- edit after this line, do not edit this line //`#end` -- edit above this line, do not edit this line + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml index 75099ce..afcb84f 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml +++ b/software/SCSI2SD/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -18,7 +18,7 @@ - + USB_Bootloader.svd @@ -27,13 +27,13 @@ .\Generated_Source\PSoC5\Cm3Iar.icf - - + + .\main.c - - + + .\Generated_Source\PSoC5\cyfitter_cfg.h .\Generated_Source\PSoC5\cyfitter_cfg.c .\Generated_Source\PSoC5\cymetadata.c @@ -111,41 +111,41 @@ .\Generated_Source\PSoC5\libelf.dll - - + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a - - + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a - + - + - + - + - + - + - + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cycdx b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cycdx old mode 100755 new mode 100644 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit old mode 100755 new mode 100644 index 08bc6f0..e12d65d Binary files a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 index 60d50ee..962c2c5 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 @@ -1077,6 +1077,7 @@ + @@ -1110,7 +1111,7 @@ - + @@ -1663,14 +1664,14 @@ C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif - + - + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt old mode 100755 new mode 100644 index 3b14907..5aae516 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.481ms -Initializing data phase: Elapsed time ==> 3s.796ms +Loading plugins phase: Elapsed time ==> 1s.508ms +Initializing data phase: Elapsed time ==> 9s.403ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 7s.874ms +Elaboration phase: Elapsed time ==> 9s.079ms -HDL generation phase: Elapsed time ==> 0s.173ms +HDL generation phase: Elapsed time ==> 0s.906ms | | | | | | | @@ -25,23 +25,23 @@ HDL generation phase: Elapsed time ==> 0s.173ms ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : vlogfe -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Wed Apr 16 21:15:58 2014 +Tue May 20 21:24:38 2014 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Wed Apr 16 21:15:59 2014 +Tue May 20 21:24:39 2014 vpp: No errors. @@ -76,11 +76,11 @@ vlogfe: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : tovif -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Wed Apr 16 21:15:59 2014 +Tue May 20 21:24:41 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -91,8 +91,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. tovif: No errors. @@ -100,11 +100,11 @@ tovif: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : topld -Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Wed Apr 16 21:16:00 2014 +Tue May 20 21:24:44 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -115,8 +115,8 @@ Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\c Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. ---------------------------------------------------------- @@ -202,13 +202,13 @@ topld: No errors. CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe -Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 2s.967ms +Warp synthesis phase: Elapsed time ==> 9s.267ms -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Wednesday, 16 April 2014 21:16:01 -Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog +cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Tuesday, 20 May 2014 21:24:47 +Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog Design parsing phase: Elapsed time ==> 0s.046ms @@ -1314,8 +1314,8 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00% -Technology Mapping: Elapsed time ==> 0s.015ms -Tech mapping phase: Elapsed time ==> 0s.281ms +Technology Mapping: Elapsed time ==> 0s.437ms +Tech mapping phase: Elapsed time ==> 0s.672ms Initial Analog Placement Results: @@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.109ms +Analog Placement phase: Elapsed time ==> 0s.078ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 1s.031ms +Analog Code Generation phase: Elapsed time ==> 1s.828ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 1.6 sec. +I2076: Total run-time: 3.9 sec. @@ -2664,32 +2664,32 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection -Digital component placer commit/Report: Elapsed time ==> 0s.017ms -Digital Placement phase: Elapsed time ==> 2s.641ms +Digital component placer commit/Report: Elapsed time ==> 0s.375ms +Digital Placement phase: Elapsed time ==> 8s.689ms Routing successful. -Digital Routing phase: Elapsed time ==> 3s.404ms +Digital Routing phase: Elapsed time ==> 6s.563ms -Bitstream and API generation phase: Elapsed time ==> 0s.796ms +Bitstream and API generation phase: Elapsed time ==> 26s.707ms -Bitstream verification phase: Elapsed time ==> 0s.171ms +Bitstream verification phase: Elapsed time ==> 0s.140ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.812ms +Static timing analysis phase: Elapsed time ==> 7s.016ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.406ms +Design database save phase: Elapsed time ==> 0s.577ms -cydsfit: Elapsed time ==> 9s.781ms +cydsfit: Elapsed time ==> 52s.696ms -Fitter phase: Elapsed time ==> 9s.859ms -API generation phase: Elapsed time ==> 4s.706ms -Dependency generation phase: Elapsed time ==> 0s.028ms -Cleanup phase: Elapsed time ==> 0s.063ms +Fitter phase: Elapsed time ==> 52s.775ms +API generation phase: Elapsed time ==> 25s.205ms +Dependency generation phase: Elapsed time ==> 0s.796ms +Cleanup phase: Elapsed time ==> 0s.750ms diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.svd b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.svd old mode 100755 new mode 100644 diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html old mode 100755 new mode 100644 index 20322ae..4e0da6e --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 04/16/14 21:16:10 + 05/20/14 21:25:38 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/SCSI2SD/src/diagnostic.c b/software/SCSI2SD/src/diagnostic.c index f6899cd..17721c2 100755 --- a/software/SCSI2SD/src/diagnostic.c +++ b/software/SCSI2SD/src/diagnostic.c @@ -132,3 +132,28 @@ void scsiReceiveDiagnostic() } } +void scsiReadBuffer() +{ + // READ BUFFER + // Used for testing the speed of the SCSI interface. + uint8 mode = scsiDev.data[1] & 7; + + int allocLength = + (((uint32) scsiDev.cdb[6]) << 16) + + (((uint32) scsiDev.cdb[7]) << 8) + + scsiDev.cdb[8]; + + if (mode == 0) + { + uint32_t maxSize = MAX_SECTOR_SIZE - 4; + // 4 byte header + scsiDev.data[0] = 0; + scsiDev.data[1] = (maxSize >> 16) & 0xff; + scsiDev.data[2] = (maxSize >> 8) & 0xff; + scsiDev.data[3] = maxSize & 0xff; + + scsiDev.dataLen = + (allocLength > MAX_SECTOR_SIZE) ? MAX_SECTOR_SIZE : allocLength; + scsiDev.phase = DATA_IN; + } +} diff --git a/software/SCSI2SD/src/diagnostic.h b/software/SCSI2SD/src/diagnostic.h index e3f09be..4cba50c 100755 --- a/software/SCSI2SD/src/diagnostic.h +++ b/software/SCSI2SD/src/diagnostic.h @@ -19,5 +19,6 @@ void scsiSendDiagnostic(void); void scsiReceiveDiagnostic(void); +void scsiReadBuffer(void); #endif diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 6ae4d85..3974ccf 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -66,7 +66,7 @@ static void doFormatUnitPatternHeader(void) int defectLength = ((((uint16_t)scsiDev.data[2])) << 8) + scsiDev.data[3]; - + int patternLength = ((((uint16_t)scsiDev.data[4 + 2])) << 8) + scsiDev.data[4 + 3]; @@ -181,7 +181,7 @@ static void doWrite(uint32 lba, uint32 blocks) transfer.multiBlock = 1; if (blocks > 1) scsiDev.needReconnect = 1; - sdPrepareWrite(); + sdWriteMultiSectorPrep(); } } @@ -217,7 +217,7 @@ static void doRead(uint32 lba, uint32 blocks) { transfer.multiBlock = 1; scsiDev.needReconnect = 1; - sdPrepareRead(); + sdReadMultiSectorPrep(); } } } @@ -463,43 +463,106 @@ void scsiDiskPoll() if (scsiDev.phase == DATA_IN && transfer.currentBlock != transfer.blocks) { - if (scsiDev.dataLen == 0) + int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector(); + uint32_t sdLBA = SCSISector2SD(transfer.lba); + int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE; + int prep = 0; + int i = 0; + int scsiActive = 0; + int sdActive = 0; + while ((i < totalSDSectors) && + (scsiDev.phase == DATA_IN) && + !scsiDev.resetFlag) { - if (transfer.multiBlock) + if ((sdActive == 1) && sdReadSectorDMAPoll()) { - sdReadSectorMulti(); + sdActive = 0; + prep++; } - else + else if ((sdActive == 0) && (prep - i < buffers) && (prep < totalSDSectors)) { - sdReadSectorSingle(); + // Start an SD transfer if we have space. + if (transfer.multiBlock) + { + sdReadMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); + } + else + { + sdReadSingleSectorDMA(sdLBA + prep, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); + } + sdActive = 1; } - } - else if (scsiDev.dataPtr == scsiDev.dataLen) - { - scsiDev.dataLen = 0; - scsiDev.dataPtr = 0; - transfer.currentBlock++; - if (transfer.currentBlock >= transfer.blocks) + + if ((scsiActive == 1) && scsiWriteDMAPoll()) { - scsiDev.phase = STATUS; - scsiDiskReset(); + scsiActive = 0; + ++i; + } + else if ((scsiActive == 0) && ((prep - i) > 0)) + { + int dmaBytes = SD_SECTOR_SIZE; + if (i % SDSectorsPerSCSISector() == SDSectorsPerSCSISector() - 1) + { + dmaBytes = config->bytesPerSector % SD_SECTOR_SIZE; + if (dmaBytes == 0) dmaBytes = SD_SECTOR_SIZE; + } + scsiWriteDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)], dmaBytes); + scsiActive = 1; } } + if (scsiDev.phase == DATA_IN) + { + scsiDev.phase = STATUS; + } + scsiDiskReset(); } else if (scsiDev.phase == DATA_OUT && transfer.currentBlock != transfer.blocks) { - sdWriteSector(); - // TODO FIX scsiDiskPoll() scsiDev.dataPtr = 0; - transfer.currentBlock++; - if (transfer.currentBlock >= transfer.blocks) + int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector(); + int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE; + int prep = 0; + int i = 0; + int scsiActive = 0; + int sdActive = 0; + while ((i < totalSDSectors) && + (scsiDev.phase == DATA_OUT) && + !scsiDev.resetFlag) { - scsiDev.dataLen = 0; - scsiDev.dataPtr = 0; - scsiDev.phase = STATUS; + if ((sdActive == 1) && sdWriteSectorDMAPoll()) + { + sdActive = 0; + i++; + } + else if ((sdActive == 0) && ((prep - i) > 0)) + { + // Start an SD transfer if we have space. + sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]); + sdActive = 1; + } - scsiDiskReset(); + if ((scsiActive == 1) && scsiReadDMAPoll()) + { + scsiActive = 0; + ++prep; + } + else if ((scsiActive == 0) && ((prep - i) < buffers) && (prep < totalSDSectors)) + { + int dmaBytes = SD_SECTOR_SIZE; + if (prep % SDSectorsPerSCSISector() == SDSectorsPerSCSISector() - 1) + { + dmaBytes = config->bytesPerSector % SD_SECTOR_SIZE; + if (dmaBytes == 0) dmaBytes = SD_SECTOR_SIZE; + } + scsiReadDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)], dmaBytes); + scsiActive = 1; + } + } + if (scsiDev.phase == DATA_OUT) + { + scsiDev.phase = STATUS; } + scsiDiskReset(); } } diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index fb91c1d..bbf4f67 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -423,6 +423,10 @@ static void process_Command() { scsiSendDiagnostic(); } + else if (command == 0x3C) + { + scsiReadBuffer(); + } else if ( !scsiModeCommand() && !scsiDiskCommand()) diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index fc42b4f..45362a7 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -22,6 +22,41 @@ #define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG) +// DMA controller can't handle any more bytes. +#define MAX_DMA_BYTES 4095 + +// Private DMA variables. +static int dmaInProgress = 0; +// used when transferring > MAX_DMA_BYTES. +static uint8_t* dmaBuffer = NULL; +static uint32_t dmaSentCount = 0; +static uint32_t dmaTotalCount = 0; + +static uint8 scsiDmaRxChan = CY_DMA_INVALID_CHANNEL; +static uint8 scsiDmaTxChan = CY_DMA_INVALID_CHANNEL; + +// DMA descriptors +static uint8 scsiDmaRxTd[1] = { CY_DMA_INVALID_TD }; +static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD }; + +// Source of dummy bytes for DMA reads +static uint8 dummyBuffer = 0xFF; + +volatile static uint8 rxDMAComplete; +volatile static uint8 txDMAComplete; + +CY_ISR_PROTO(scsiRxCompleteISR); +CY_ISR(scsiRxCompleteISR) +{ + rxDMAComplete = 1; +} + +CY_ISR_PROTO(scsiTxCompleteISR); +CY_ISR(scsiTxCompleteISR) +{ + txDMAComplete = 1; +} + CY_ISR_PROTO(scsiResetISR); CY_ISR(scsiResetISR) { @@ -29,7 +64,8 @@ CY_ISR(scsiResetISR) SCSI_RST_ClearInterrupt(); } -uint8 scsiReadDBxPins() +uint8_t +scsiReadDBxPins() { return (SCSI_ReadPin(SCSI_In_DBx_DB7) << 7) | @@ -39,79 +75,259 @@ uint8 scsiReadDBxPins() (SCSI_ReadPin(SCSI_In_DBx_DB3) << 3) | (SCSI_ReadPin(SCSI_In_DBx_DB2) << 2) | (SCSI_ReadPin(SCSI_In_DBx_DB1) << 1) | - SCSI_ReadPin(SCSI_In_DBx_DB0); + SCSI_ReadPin(SCSI_In_DBx_DB0); } -uint8 scsiReadByte(void) +uint8_t +scsiReadByte(void) { - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) && - !scsiDev.resetFlag) {} - CY_SET_REG8(scsiTarget_datapath__F0_REG, 0); - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) && - !scsiDev.resetFlag) {} - + while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {} + scsiPhyTx(0); + + while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {} + uint8_t val = scsiPhyRx(); + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} - - return CY_GET_REG8(scsiTarget_datapath__F1_REG); + + return val; } -void scsiRead(uint8* data, uint32 count) +static void +scsiReadPIO(uint8* data, uint32 count) { int prep = 0; int i = 0; while (i < count && !scsiDev.resetFlag) { - if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) + uint8_t status = scsiPhyStatus(); + + if (prep < count && (status & SCSI_PHY_TX_FIFO_NOT_FULL)) { - CY_SET_REG8(scsiTarget_datapath__F0_REG, 0); + scsiPhyTx(0); ++prep; } - if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) + if (status & SCSI_PHY_RX_FIFO_NOT_EMPTY) { - data[i] = CY_GET_REG8(scsiTarget_datapath__F1_REG); + data[i] = scsiPhyRx(); ++i; } } while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} - } -void scsiWriteByte(uint8 value) +static void +doRxSingleDMA(uint8* data, uint32 count) { - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) && - !scsiDev.resetFlag) {} - CY_SET_REG8(scsiTarget_datapath__F0_REG, value); + // Prepare DMA transfer + dmaInProgress = 1; - // TODO maybe move this TX EMPTY check to scsiEnterPhase ? - //while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {} - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) && - !scsiDev.resetFlag) {} - value = CY_GET_REG8(scsiTarget_datapath__F1_REG); + CyDmaTdSetConfiguration( + scsiDmaTxTd[0], + count, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + CyDmaTdSetConfiguration( + scsiDmaRxTd[0], + count, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + TD_INC_DST_ADR | + SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + CyDmaTdSetAddress( + scsiDmaTxTd[0], + LO16((uint32)&dummyBuffer), + LO16((uint32)scsiTarget_datapath__F0_REG)); + CyDmaTdSetAddress( + scsiDmaRxTd[0], + LO16((uint32)scsiTarget_datapath__F1_REG), + LO16((uint32)data) + ); + + CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]); + CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]); + + // The DMA controller is a bit trigger-happy. It will retain + // a drq request that was triggered while the channel was + // disabled. + CyDmaClearPendingDrq(scsiDmaTxChan); + CyDmaClearPendingDrq(scsiDmaRxChan); + + txDMAComplete = 0; + rxDMAComplete = 0; + + CyDmaChEnable(scsiDmaRxChan, 1); + CyDmaChEnable(scsiDmaTxChan, 1); +} + +void +scsiReadDMA(uint8* data, uint32 count) +{ + dmaSentCount = 0; + dmaTotalCount = count; + dmaBuffer = data; + + uint32_t singleCount = (count > MAX_DMA_BYTES) ? MAX_DMA_BYTES : count; + doRxSingleDMA(data, singleCount); + dmaSentCount += count; +} + +int +scsiReadDMAPoll() +{ + if (txDMAComplete && rxDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) + { + if (dmaSentCount == dmaTotalCount) + { + dmaInProgress = 0; + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + return 1; + } + else + { + // Transfer was too large for a single DMA transfer. Continue + // to send remaining bytes. + uint32_t count = dmaTotalCount - dmaSentCount; + if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES; + doRxSingleDMA(dmaBuffer + dmaSentCount, count); + dmaSentCount += count; + return 0; + } + } + else + { + return 0; + } +} + +void +scsiRead(uint8_t* data, uint32_t count) +{ + if (count < 8) + { + scsiReadPIO(data, count); + } + else + { + scsiReadDMA(data, count); + while (!scsiReadDMAPoll() && !scsiDev.resetFlag) {}; + } +} + +void +scsiWriteByte(uint8 value) +{ + while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {} + scsiPhyTx(value); + + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} + scsiPhyRxFifoClear(); + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} } -void scsiWrite(uint8* data, uint32 count) +static void +scsiWritePIO(uint8_t* data, uint32_t count) { - int prep = 0; int i = 0; while (i < count && !scsiDev.resetFlag) { - if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) + if (!scsiPhyTxFifoFull()) { - CY_SET_REG8(scsiTarget_datapath__F0_REG, data[prep]); - ++prep; + scsiPhyTx(data[i]); + ++i; } - if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) + } + + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} + scsiPhyRxFifoClear(); +} + +static void +doTxSingleDMA(uint8* data, uint32 count) +{ + // Prepare DMA transfer + dmaInProgress = 1; + + CyDmaTdSetConfiguration( + scsiDmaTxTd[0], + count, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + TD_INC_SRC_ADR | + SCSI_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + CyDmaTdSetAddress( + scsiDmaTxTd[0], + LO16((uint32)data), + LO16((uint32)scsiTarget_datapath__F0_REG)); + CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]); + + // The DMA controller is a bit trigger-happy. It will retain + // a drq request that was triggered while the channel was + // disabled. + CyDmaClearPendingDrq(scsiDmaTxChan); + + txDMAComplete = 0; + + CyDmaChEnable(scsiDmaTxChan, 1); +} + +void +scsiWriteDMA(uint8* data, uint32 count) +{ + dmaSentCount = 0; + dmaTotalCount = count; + dmaBuffer = data; + + uint32_t singleCount = (count > MAX_DMA_BYTES) ? MAX_DMA_BYTES : count; + doTxSingleDMA(data, singleCount); + dmaSentCount += count; +} + +int +scsiWriteDMAPoll() +{ + if (txDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) + { + if (dmaSentCount == dmaTotalCount) { - CY_GET_REG8(scsiTarget_datapath__F1_REG); - ++i; + scsiPhyRxFifoClear(); + dmaInProgress = 0; + while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + return 1; + } + else + { + // Transfer was too large for a single DMA transfer. Continue + // to send remaining bytes. + uint32_t count = dmaTotalCount - dmaSentCount; + if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES; + doTxSingleDMA(dmaBuffer + dmaSentCount, count); + dmaSentCount += count; + return 0; } } - - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + else + { + return 0; + } +} + +void +scsiWrite(uint8_t* data, uint32_t count) +{ + if (count < 8) + { + scsiWritePIO(data, count); + } + else + { + scsiWriteDMA(data, count); + while (!scsiWriteDMAPoll() && !scsiDev.resetFlag) {}; + } } static void busSettleDelay(void) @@ -133,6 +349,20 @@ void scsiEnterPhase(int phase) void scsiPhyReset() { + if (dmaInProgress) + { + dmaInProgress = 0; + dmaBuffer = NULL; + dmaSentCount = 0; + dmaTotalCount = 0; + CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN); + CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN); + while (!(txDMAComplete && rxDMAComplete)) {} + + CyDmaChDisable(scsiDmaTxChan); + CyDmaChDisable(scsiDmaRxChan); + } + // Set the Clear bits for both SCSI device FIFOs scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03; @@ -155,8 +385,43 @@ void scsiPhyReset() scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03); } +static void scsiPhyInitDMA() +{ + // One-time init only. + if (scsiDmaTxChan == CY_DMA_INVALID_CHANNEL) + { + scsiDmaRxChan = + SCSI_RX_DMA_DmaInitialize( + 1, // Bytes per burst + 1, // request per burst + HI16(CYDEV_PERIPH_BASE), + HI16(CYDEV_SRAM_BASE) + ); + + scsiDmaTxChan = + SCSI_TX_DMA_DmaInitialize( + 1, // Bytes per burst + 1, // request per burst + HI16(CYDEV_SRAM_BASE), + HI16(CYDEV_PERIPH_BASE) + ); + + CyDmaChDisable(scsiDmaRxChan); + CyDmaChDisable(scsiDmaTxChan); + + scsiDmaRxTd[0] = CyDmaTdAllocate(); + scsiDmaTxTd[0] = CyDmaTdAllocate(); + + SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR); + SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR); + } +} + + void scsiPhyInit() { + scsiPhyInitDMA(); + SCSI_RST_ISR_StartEx(scsiResetISR); // Interrupts may have already been directed to the (empty) diff --git a/software/SCSI2SD/src/scsiPhy.h b/software/SCSI2SD/src/scsiPhy.h index 94c47e2..b6a1426 100755 --- a/software/SCSI2SD/src/scsiPhy.h +++ b/software/SCSI2SD/src/scsiPhy.h @@ -17,6 +17,26 @@ #ifndef SCSIPHY_H #define SCSIPHY_H +// Definitions to match the scsiTarget status register. +typedef enum +{ + SCSI_PHY_TX_FIFO_NOT_FULL = 0x01, + SCSI_PHY_RX_FIFO_NOT_EMPTY = 0x02, + + // The TX FIFO is empty and the state machine is in the idle state + SCSI_PHY_TX_COMPLETE = 0x10 +} SCSI_PHY_STATE; + +#define scsiPhyStatus() CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) +#define scsiPhyTxFifoFull() ((scsiPhyStatus() & SCSI_PHY_TX_FIFO_NOT_FULL) == 0) +#define scsiPhyRxFifoEmpty() ((scsiPhyStatus() & SCSI_PHY_RX_FIFO_NOT_EMPTY) == 0) + +// Clear 4 byte fifo +#define scsiPhyRxFifoClear() scsiPhyRx(); scsiPhyRx(); scsiPhyRx(); scsiPhyRx(); + +#define scsiPhyTx(val) CY_SET_REG8(scsiTarget_datapath__F0_REG, (val)) +#define scsiPhyRx() CY_GET_REG8(scsiTarget_datapath__F1_REG) + #define SCSI_SetPin(pin) \ CyPins_SetPin((pin)); @@ -28,16 +48,22 @@ (CyPins_ReadPin((pin)) == 0) // Contains the odd-parity flag for a given 8-bit value. -extern const uint8 Lookup_OddParity[256]; +extern const uint8_t Lookup_OddParity[256]; void scsiPhyReset(void); void scsiPhyInit(void); -uint8 scsiReadByte(void); -void scsiRead(uint8* data, uint32 count); -void scsiWriteByte(uint8 value); -void scsiWrite(uint8* data, uint32 count); -uint8 scsiReadDBxPins(void); +uint8_t scsiReadByte(void); +void scsiRead(uint8_t* data, uint32_t count); +void scsiReadDMA(uint8_t* data, uint32_t count); +int scsiReadDMAPoll(); + +void scsiWriteByte(uint8_t value); +void scsiWrite(uint8_t* data, uint32_t count); +void scsiWriteDMA(uint8_t* data, uint32_t count); +int scsiWriteDMAPoll(); + +uint8_t scsiReadDBxPins(void); void scsiEnterPhase(int phase); diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index f11d2e0..19e02fd 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -29,6 +29,35 @@ // Global SdDevice sdDev; +// Private DMA variables. +static int dmaInProgress = 0; +static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL; +static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL; + +// DMA descriptors +static uint8 sdDMARxTd[1] = { CY_DMA_INVALID_TD }; +static uint8 sdDMATxTd[1] = { CY_DMA_INVALID_TD }; + +// Dummy location for DMA to send unchecked CRC bytes to +static uint8 discardBuffer; + +// Source of dummy SPI bytes for DMA +static uint8 dummyBuffer = 0xFF; + +volatile static uint8 rxDMAComplete; +volatile static uint8 txDMAComplete; + +CY_ISR_PROTO(sdRxISR); +CY_ISR(sdRxISR) +{ + rxDMAComplete = 1; +} +CY_ISR_PROTO(sdTxISR); +CY_ISR(sdTxISR) +{ + txDMAComplete = 1; +} + static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc) { uint8 a; @@ -126,12 +155,13 @@ static void sdClearStatus() } -void sdPrepareRead() +void +sdReadMultiSectorPrep() { uint8 v; uint32 scsiLBA = (transfer.lba + transfer.currentBlock); uint32 sdLBA = SCSISector2SD(scsiLBA); - + if (!sdDev.ccs) { sdLBA = sdLBA * SD_SECTOR_SIZE; @@ -153,10 +183,9 @@ void sdPrepareRead() } } -static void doReadSector(uint32_t numBytes) +static void +dmaReadSector(uint8_t* outputBuffer) { - int prep, i, guard; - // Wait for a start-block token. // Don't wait more than 100ms, which is the timeout recommended // in the standard. @@ -183,93 +212,60 @@ static void doReadSector(uint32_t numBytes) return; } - scsiEnterPhase(DATA_IN); + CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, TD_INC_DST_ADR | SD_RX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer)); + CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR)); - // Quickly seed the FIFO - prep = 4; - CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO - CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO - CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO - CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO - - i = 0; - guard = 0; - - // This loop is critically important for performance. - // We stream data straight from the SDCard fifos into the SCSI component - // FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty, - // and performance will suffer. Every clock cycle counts. - while (i < numBytes && !scsiDev.resetFlag) - { - uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR); - uint8_t scsiStatus = CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG); - - // Read from the SPIM fifo if there is room to stream the byte to the - // SCSI fifos - if((sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) && - (scsiStatus & 1) // SCSI TX FIFO NOT FULL - ) - { - uint8_t val = CY_GET_REG8(SDCard_RXDATA_PTR); - CY_SET_REG8(scsiTarget_datapath__F0_REG, val); - guard++; + dmaInProgress = 1; + // The DMA controller is a bit trigger-happy. It will retain + // a drq request that was triggered while the channel was + // disabled. + CyDmaClearPendingDrq(sdDMATxChan); + CyDmaClearPendingDrq(sdDMARxChan); - // How many bytes are in a 4-byte FIFO ? 5. 4 FIFO bytes PLUS one byte - // being processed bit-by-bit. Artifically limit the number of bytes in the - // "combined" SPIM TX and RX FIFOS to the individual FIFO size. - // Unlike the SCSI component, SPIM doesn't check if there's room in - // the output FIFO before starting to transmit. + txDMAComplete = 0; + rxDMAComplete = 0; - if (prep < numBytes) - { - CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO - prep++; - } + // Re-loading the initial TD's here is very important, or else + // we'll be re-using the last-used TD, which would be the last + // in the chain (ie. CRC TD) + CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]); + CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]); - } - - // Byte has been sent out the SCSI interface. - if (scsiStatus & 2) // SCSI RX FIFO NOT EMPTY - { - CY_GET_REG8(scsiTarget_datapath__F1_REG); - ++i; - } - } + // There is no flow control, so we must ensure we can read the bytes + // before we start transmitting + CyDmaChEnable(sdDMARxChan, 1); + CyDmaChEnable(sdDMATxChan, 1); +} - // Read and discard remaining bytes. This applis for non-512 byte sectors, - // or if a SCSI reset was triggered. - while (guard < SD_SECTOR_SIZE) +int +sdReadSectorDMAPoll() +{ + if (rxDMAComplete && txDMAComplete) { - uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR); - if(sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) - { - CY_GET_REG8(SDCard_RXDATA_PTR); - guard++; - } + // DMA transfer is complete + dmaInProgress = 0; - if ((prep - guard < 4) && (prep < SD_SECTOR_SIZE)) - { - CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO - prep++; - } - } + sdSpiByte(0xFF); // CRC + sdSpiByte(0xFF); // CRC - sdSpiByte(0xFF); // CRC - sdSpiByte(0xFF); // CRC - scsiDev.dataLen = numBytes; - scsiDev.dataPtr = numBytes; - - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} + return 1; + } + else + { + return 0; + } } -static void doReadSectorSingle(uint32 sdBlock, int sdBytes) +void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer) { uint8 v; if (!sdDev.ccs) { - sdBlock = sdBlock * SD_SECTOR_SIZE; - } - v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, sdBlock); + lba = lba * SD_SECTOR_SIZE; + } + v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba); if (v) { scsiDiskReset(); @@ -282,52 +278,28 @@ static void doReadSectorSingle(uint32 sdBlock, int sdBytes) } else { - doReadSector(sdBytes); + dmaReadSector(outputBuffer); } } - -void sdReadSectorSingle() +void +sdReadMultiSectorDMA(uint8_t* outputBuffer) { - uint32 scsiLBA = (transfer.lba + transfer.currentBlock); - uint32 sdLBA = SCSISector2SD(scsiLBA); - - int sdSectors = SDSectorsPerSCSISector(); - int i; - for (i = 0; (i < sdSectors - 1) && (scsiDev.status != CHECK_CONDITION); ++i) - { - doReadSectorSingle(sdLBA + i, SD_SECTOR_SIZE); - } - - if (scsiDev.status != CHECK_CONDITION) - { - int remaining = config->bytesPerSector % SD_SECTOR_SIZE; - if (remaining == 0) remaining = SD_SECTOR_SIZE; // Full sector needed. - doReadSectorSingle(sdLBA + i, remaining); - } + // Pre: sdReadMultiSectorPrep called. + dmaReadSector(outputBuffer); } -void sdReadSectorMulti() -{ - // Pre: sdPrepareRead called. - int sdSectors = SDSectorsPerSCSISector(); - int i; - for (i = 0; (i < sdSectors - 1) && (scsiDev.status != CHECK_CONDITION); ++i) - { - doReadSector(SD_SECTOR_SIZE); - } - if (scsiDev.status != CHECK_CONDITION) +void sdCompleteRead() +{ + if (dmaInProgress) { - int remaining = config->bytesPerSector % SD_SECTOR_SIZE; - if (remaining == 0) remaining = SD_SECTOR_SIZE; // Full sector needed. - doReadSector(remaining); + // Not much choice but to wait until we've completed the transfer. + // Cancelling the transfer can't be done as we have no way to reset + // the SD card. + while (!sdReadSectorDMAPoll()) { /* spin */ } } -} - -void sdCompleteRead() -{ transfer.inProgress = 0; // We cannot send even a single "padding" byte, as we normally would when @@ -375,152 +347,110 @@ static void sdWaitWriteBusy() } while (val != 0xFF); } -static int doWriteSector(uint32_t numBytes) +void +sdWriteMultiSectorDMA(uint8_t* outputBuffer) { - int prep, i, guard; - int result, maxWait; - uint8 dataToken; - - scsiEnterPhase(DATA_OUT); - sdSpiByte(0xFC); // MULTIPLE byte start token - - prep = 0; - i = 0; - guard = 0; - - // This loop is critically important for performance. - // We stream data straight from the SCSI fifos into the SPIM component - // FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty, - // and performance will suffer. Every clock cycle counts. - while (i < numBytes && !scsiDev.resetFlag) - { - uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR); - uint8_t scsiStatus = CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG); - - // Read from the SCSI fifo if there is room to stream the byte to the - // SPIM fifos - // See sdReadSector for comment on guard (FIFO size is really 5) - if((guard - i < 4) && - (scsiDev.resetFlag || (scsiStatus & 2)) - ) // SCSI RX FIFO NOT EMPTY - { - uint8_t val = CY_GET_REG8(scsiTarget_datapath__F1_REG); - CY_SET_REG8(SDCard_TXDATA_PTR, val); - guard++; - } - - // Byte has been sent out the SPIM interface. - if (sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) - { - CY_GET_REG8(SDCard_RXDATA_PTR); - ++i; - } - if (prep < numBytes && - (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL - ) - { - // Trigger the SCSI component to read a byte - CY_SET_REG8(scsiTarget_datapath__F0_REG, 0xFF); - prep++; - } - } + CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, TD_INC_SRC_ADR | SD_TX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR)); + CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); - // Write remaining bytes as 0x00 - while (i < SD_SECTOR_SIZE) + dmaInProgress = 1; + // The DMA controller is a bit trigger-happy. It will retain + // a drq request that was triggered while the channel was + // disabled. + CyDmaClearPendingDrq(sdDMATxChan); + CyDmaClearPendingDrq(sdDMARxChan); + + txDMAComplete = 0; + rxDMAComplete = 0; + + // Re-loading the initial TD's here is very important, or else + // we'll be re-using the last-used TD, which would be the last + // in the chain (ie. CRC TD) + CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]); + CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]); + + // There is no flow control, so we must ensure we can read the bytes + // before we start transmitting + CyDmaChEnable(sdDMARxChan, 1); + CyDmaChEnable(sdDMATxChan, 1); +} + +int +sdWriteSectorDMAPoll() +{ + if (rxDMAComplete && txDMAComplete) { - uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR); + // DMA transfer is complete + dmaInProgress = 0; - if((guard - i < 4) && (guard < SD_SECTOR_SIZE)) - { - CY_SET_REG8(SDCard_TXDATA_PTR, 0x00); - guard++; - } + sdSpiByte(0x00); // CRC + sdSpiByte(0x00); // CRC - // Byte has been sent out the SPIM interface. - if (sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) + // Don't wait more than 1s. + // My 2g Kingston micro-sd card doesn't respond immediately. + // My 16Gb card does. + int maxWait = 1000000; + uint8_t dataToken = sdSpiByte(0xFF); // Response + while (dataToken == 0xFF && maxWait-- > 0) { - CY_GET_REG8(SDCard_RXDATA_PTR); - ++i; + CyDelayUs(1); + dataToken = sdSpiByte(0xFF); } - } - - sdSpiByte(0x00); // CRC - sdSpiByte(0x00); // CRC - - // Don't wait more than 1s. - // My 2g Kingston micro-sd card doesn't respond immediately. - // My 16Gb card does. - maxWait = 1000000; - dataToken = sdSpiByte(0xFF); // Response - while (dataToken == 0xFF && maxWait-- > 0) - { - CyDelayUs(1); - dataToken = sdSpiByte(0xFF); - } - if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted. - { - uint8 r1b, busy; + if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted. + { + uint8 r1b, busy; - sdWaitWriteBusy(); + sdWaitWriteBusy(); - r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0); - (void) r1b; - sdSpiByte(0xFF); + r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0); + (void) r1b; + sdSpiByte(0xFF); - // R1b has an optional trailing "busy" signal. - do - { - busy = sdSpiByte(0xFF); - } while (busy == 0); + // R1b has an optional trailing "busy" signal. + do + { + busy = sdSpiByte(0xFF); + } while (busy == 0); - // Wait for the card to come out of busy. - sdWaitWriteBusy(); + // Wait for the card to come out of busy. + sdWaitWriteBusy(); - transfer.inProgress = 0; - scsiDiskReset(); - sdClearStatus(); + transfer.inProgress = 0; + scsiDiskReset(); + sdClearStatus(); - scsiDev.status = CHECK_CONDITION; - scsiDev.sense.code = HARDWARE_ERROR; - scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; - scsiDev.phase = STATUS; - result = 0; + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = HARDWARE_ERROR; + scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.phase = STATUS; + } + else + { + sdWaitWriteBusy(); + } + + return 1; } else { - sdWaitWriteBusy(); - result = 1; + return 0; } - - while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {} - - return result; } -int sdWriteSector() +void sdCompleteWrite() { - int result = 1; - // Pre: sdPrepareWrite called. - int sdSectors = SDSectorsPerSCSISector(); - int i; - for (i = 0; result && (i < sdSectors - 1) && (scsiDev.status != CHECK_CONDITION); ++i) - { - result = doWriteSector(SD_SECTOR_SIZE); - } - - if (result && scsiDev.status != CHECK_CONDITION) + if (dmaInProgress) { - int remaining = config->bytesPerSector % SD_SECTOR_SIZE; - if (remaining == 0) remaining = SD_SECTOR_SIZE; // Full sector needed. - result = doWriteSector(remaining); + // Not much choice but to wait until we've completed the transfer. + // Cancelling the transfer can't be done as we have no way to reset + // the SD card. + while (!sdWriteSectorDMAPoll()) { /* spin */ } } - return result; -} - -void sdCompleteWrite() -{ + transfer.inProgress = 0; uint8 r1, r2; @@ -669,6 +599,38 @@ bad: return 0; } +static void sdInitDMA() +{ + // One-time init only. + if (sdDMATxChan == CY_DMA_INVALID_CHANNEL) + { + sdDMATxChan = + SD_TX_DMA_DmaInitialize( + 1, // Bytes per burst + 1, // request per burst + HI16(CYDEV_SRAM_BASE), + HI16(CYDEV_PERIPH_BASE) + ); + + sdDMARxChan = + SD_RX_DMA_DmaInitialize( + 1, // Bytes per burst + 1, // request per burst + HI16(CYDEV_PERIPH_BASE), + HI16(CYDEV_SRAM_BASE) + ); + + CyDmaChDisable(sdDMATxChan); + CyDmaChDisable(sdDMARxChan); + + sdDMARxTd[0] = CyDmaTdAllocate(); + sdDMATxTd[0] = CyDmaTdAllocate(); + + SD_RX_DMA_COMPLETE_StartEx(sdRxISR); + SD_TX_DMA_COMPLETE_StartEx(sdTxISR); + } +} + int sdInit() { int result = 0; @@ -679,9 +641,17 @@ int sdInit() sdDev.ccs = 0; sdDev.capacity = 0; + sdInitDMA(); + SD_CS_Write(1); // Set CS inactive (active low) - SD_Init_Clk_Start(); // Turn on the slow 400KHz clock - SD_Clk_Ctl_Write(0); // Select the 400KHz clock source. + + // Set the SPI clock for 400kHz transfers + // 25MHz / 400kHz approx factor of 63. + uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister(); + SD_Data_Clk_SetDivider(clkDiv25MHz * 63); + // Wait for the clock to settle. + CyDelayUs(1); + SDCard_Start(); // Enable SPI hardware // Power on sequence. 74 clock cycles of a "1" while CS unasserted. @@ -708,24 +678,16 @@ int sdInit() v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off if(v){goto bad;} - // now set the sd card up for full speed + // now set the sd card back to full speed. // The SD Card spec says we can run SPI @ 25MHz - // But the PSoC 5LP SPIM datasheet says the most we can do is 18MHz. - // I've confirmed that no data is ever put into the RX FIFO when run at - // 20MHz or 25MHz. - // ... and then we get timing analysis failures if the BUS_CLK is over 62MHz. - // So we run the MASTER_CLK and BUS_CLK at 60MHz, and run the SPI clock at 30MHz - // (15MHz SPI transfer clock). SDCard_Stop(); - + // We can't run at full-speed with the pullup resistors enabled. SD_MISO_SetDriveMode(SD_MISO_DM_DIG_HIZ); SD_MOSI_SetDriveMode(SD_MOSI_DM_STRONG); SD_SCK_SetDriveMode(SD_SCK_DM_STRONG); - - SD_Data_Clk_Start(); // Turn on the fast clock - SD_Clk_Ctl_Write(1); // Select the fast clock source. - SD_Init_Clk_Stop(); // Stop the slow clock. + + SD_Data_Clk_SetDivider(clkDiv25MHz); CyDelayUs(1); SDCard_Start(); @@ -750,7 +712,7 @@ out: } -void sdPrepareWrite() +void sdWriteMultiSectorPrep() { uint8 v; diff --git a/software/SCSI2SD/src/sd.h b/software/SCSI2SD/src/sd.h index 4f1e9db..ffa4dd0 100755 --- a/software/SCSI2SD/src/sd.h +++ b/software/SCSI2SD/src/sd.h @@ -58,13 +58,16 @@ typedef struct extern SdDevice sdDev; int sdInit(void); -void sdPrepareWrite(void); -int sdWriteSector(void); + +void sdWriteMultiSectorPrep(void); +void sdWriteMultiSectorDMA(uint8_t* outputBuffer); +int sdWriteSectorDMAPoll(); void sdCompleteWrite(void); -void sdPrepareRead(void); -void sdReadSectorMulti(void); -void sdReadSectorSingle(void); +void sdReadMultiSectorPrep(void); +void sdReadMultiSectorDMA(uint8_t* outputBuffer); +void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer); +int sdReadSectorDMAPoll(); void sdCompleteRead(void); #endif