From: Michael McMaster Date: Fri, 14 Feb 2014 20:58:27 +0000 (+1000) Subject: Many bug fixes, including selection fixes. X-Git-Tag: 3.2~1 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=6c8cbf54c6bd50fe5304d3616d8e8296d6968019;p=SCSI2SD.git Many bug fixes, including selection fixes. - Better selection support for SCSI1 initiators - Support select-with-atn --- diff --git a/CHANGELOG b/CHANGELOG index b74f36f..5a4eb9f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,13 @@ +20140214 3.2 + - Remove hacks around ATN handling, and implement proper select-with-atn + support. This fix is essential for communicating with some SCSI hosts. + All SCSI2SD users are urged to upgrade to this firmware version. + - More fixes to support Apple HD SC Setup (thanks to Doug Brown!) + - Fixes to support SCSI1 initiators + * Support non-arbitrating initiators. + * Support single-initiator option. + * Set CCS response format flag in INQUIRY response. + 20131227 3.1 - Fixes for better SCSI reset handling - Fix for reading the last sector of the SD card. diff --git a/readme.txt b/readme.txt index 0931201..9eea4c0 100644 --- a/readme.txt +++ b/readme.txt @@ -55,6 +55,13 @@ Tested with a 16GB class 10 SD card, via the commands: Compatibility -Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475 -hardware. +Tested with Linux (current), Apple Macintosh System 7.5.3 on LC-III, and LC-475 hardware. + +Users have reported success on these systems: + + Mac II running System 6.0.8 + Mac SE/30 + Roland JS-30 Sampler + Akai S3200 Sampler + EMU Emulator E4X with EOS 3.00b diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index bc90348..af7277c 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -33,16 +33,6 @@ #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 -/* SCSI_ATN_ISR */ -#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 -#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_ATN_ISR__INTC_MASK 0x800u -#define SCSI_ATN_ISR__INTC_NUMBER 11u -#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u -#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_11 -#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 -#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 - /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX @@ -488,34 +478,34 @@ #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -523,13 +513,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -539,28 +529,32 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -575,24 +569,24 @@ /* SCSI_CTL_IO */ #define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL #define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u -#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL /* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT12_AG @@ -1051,8 +1045,8 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1060,9 +1054,9 @@ #define scsiTarget_StatusReg__3__MASK 0x08u #define scsiTarget_StatusReg__3__POS 3 #define scsiTarget_StatusReg__MASK 0x0Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST #define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL #define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK @@ -1112,24 +1106,24 @@ /* SD_Clk_Ctl */ #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1301,7 +1295,6 @@ #define SCSI_ATN__DM2 CYREG_PRT12_DM2 #define SCSI_ATN__DR CYREG_PRT12_DR #define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS -#define SCSI_ATN__INTSTAT CYREG_PICU12_INTSTAT #define SCSI_ATN__INT__MASK 0x20u #define SCSI_ATN__INT__PC CYREG_PRT12_PC5 #define SCSI_ATN__INT__PORT 12u @@ -1322,7 +1315,6 @@ #define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN #define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ #define SCSI_ATN__SLW CYREG_PRT12_SLW -#define SCSI_ATN__SNAP CYREG_PICU12_SNAP /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT4_AG @@ -2671,9 +2663,9 @@ #define CYDEV_CHIP_FAMILY_PSOC5 3u #define CYDEV_CHIP_DIE_PSOC5LP 4u #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP -#define BCLK__BUS_CLK__HZ 64000000U -#define BCLK__BUS_CLK__KHZ 64000U -#define BCLK__BUS_CLK__MHZ 64U +#define BCLK__BUS_CLK__HZ 60000000U +#define BCLK__BUS_CLK__KHZ 60000U +#define BCLK__BUS_CLK__MHZ 60U #define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT #define CYDEV_CHIP_DIE_LEOPARD 1u #define CYDEV_CHIP_DIE_PANTHER 3u diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 6c7544e..fae8663 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -200,7 +200,7 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); /* Configure PLL based on settings from Clock DWR */ - CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0919u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); /* Wait up to 250us for the PLL to lock */ pllLock = 0u; @@ -362,37 +362,37 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { - 0x40004503u, /* Base address: 0x40004500 Count: 3 */ - 0x40005209u, /* Base address: 0x40005200 Count: 9 */ - 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40010044u, /* Base address: 0x40010000 Count: 68 */ - 0x40010135u, /* Base address: 0x40010100 Count: 53 */ - 0x4001023Eu, /* Base address: 0x40010200 Count: 62 */ - 0x40010350u, /* Base address: 0x40010300 Count: 80 */ - 0x4001044Bu, /* Base address: 0x40010400 Count: 75 */ - 0x40010554u, /* Base address: 0x40010500 Count: 84 */ - 0x40010605u, /* Base address: 0x40010600 Count: 5 */ - 0x4001074Bu, /* Base address: 0x40010700 Count: 75 */ - 0x40010911u, /* Base address: 0x40010900 Count: 17 */ - 0x40010A37u, /* Base address: 0x40010A00 Count: 55 */ - 0x40010B35u, /* Base address: 0x40010B00 Count: 53 */ - 0x40010D0Fu, /* Base address: 0x40010D00 Count: 15 */ - 0x40010F02u, /* Base address: 0x40010F00 Count: 2 */ - 0x40011504u, /* Base address: 0x40011500 Count: 4 */ - 0x40011642u, /* Base address: 0x40011600 Count: 66 */ - 0x40011747u, /* Base address: 0x40011700 Count: 71 */ - 0x40011908u, /* Base address: 0x40011900 Count: 8 */ - 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */ - 0x4001400Fu, /* Base address: 0x40014000 Count: 15 */ - 0x4001410Du, /* Base address: 0x40014100 Count: 13 */ - 0x40014206u, /* Base address: 0x40014200 Count: 6 */ + 0x40004502u, /* Base address: 0x40004500 Count: 2 */ + 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ + 0x40006401u, /* Base address: 0x40006400 Count: 1 */ + 0x40006501u, /* Base address: 0x40006500 Count: 1 */ + 0x40010043u, /* Base address: 0x40010000 Count: 67 */ + 0x40010130u, /* Base address: 0x40010100 Count: 48 */ + 0x4001023Au, /* Base address: 0x40010200 Count: 58 */ + 0x4001034Cu, /* Base address: 0x40010300 Count: 76 */ + 0x40010447u, /* Base address: 0x40010400 Count: 71 */ + 0x4001054Du, /* Base address: 0x40010500 Count: 77 */ + 0x40010649u, /* Base address: 0x40010600 Count: 73 */ + 0x40010746u, /* Base address: 0x40010700 Count: 70 */ + 0x4001090Du, /* Base address: 0x40010900 Count: 13 */ + 0x40010A33u, /* Base address: 0x40010A00 Count: 51 */ + 0x40010B38u, /* Base address: 0x40010B00 Count: 56 */ + 0x40010D06u, /* Base address: 0x40010D00 Count: 6 */ + 0x40010F03u, /* Base address: 0x40010F00 Count: 3 */ + 0x40011503u, /* Base address: 0x40011500 Count: 3 */ + 0x40011736u, /* Base address: 0x40011700 Count: 54 */ + 0x40011902u, /* Base address: 0x40011900 Count: 2 */ + 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ + 0x4001400Du, /* Base address: 0x40014000 Count: 13 */ + 0x4001410Fu, /* Base address: 0x40014100 Count: 15 */ + 0x4001420Au, /* Base address: 0x40014200 Count: 10 */ 0x40014308u, /* Base address: 0x40014300 Count: 8 */ - 0x4001440Au, /* Base address: 0x40014400 Count: 10 */ - 0x40014514u, /* Base address: 0x40014500 Count: 20 */ - 0x40014609u, /* Base address: 0x40014600 Count: 9 */ - 0x40014709u, /* Base address: 0x40014700 Count: 9 */ - 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */ - 0x40014907u, /* Base address: 0x40014900 Count: 7 */ + 0x4001440Bu, /* Base address: 0x40014400 Count: 11 */ + 0x40014512u, /* Base address: 0x40014500 Count: 18 */ + 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */ + 0x40014706u, /* Base address: 0x40014700 Count: 6 */ + 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ + 0x40014909u, /* Base address: 0x40014900 Count: 9 */ 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015101u, /* Base address: 0x40015100 Count: 1 */ @@ -400,185 +400,175 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x36u, 0x02u}, - {0x65u, 0x02u}, {0x7Eu, 0x02u}, + {0x00u, 0x01u}, {0x01u, 0x01u}, - {0x18u, 0x0Cu}, + {0x18u, 0x08u}, {0x19u, 0x04u}, {0x1Cu, 0x61u}, - {0x20u, 0x50u}, - {0x21u, 0x98u}, - {0x30u, 0x05u}, - {0x31u, 0x09u}, + {0x20u, 0x98u}, + {0x21u, 0x50u}, + {0x30u, 0x03u}, + {0x31u, 0x06u}, {0x7Cu, 0x40u}, {0x33u, 0x03u}, - {0x87u, 0x0Fu}, - {0x00u, 0x0Du}, - {0x03u, 0x04u}, - {0x04u, 0x01u}, - {0x06u, 0x32u}, - {0x07u, 0x24u}, - {0x08u, 0x02u}, - {0x09u, 0x24u}, - {0x0Au, 0x54u}, - {0x0Bu, 0x12u}, - {0x0Du, 0x24u}, - {0x0Eu, 0x10u}, - {0x0Fu, 0x09u}, - {0x14u, 0x62u}, - {0x16u, 0x08u}, - {0x1Bu, 0x03u}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x0Du}, - {0x1Fu, 0x18u}, - {0x20u, 0x0Du}, - {0x23u, 0x20u}, - {0x24u, 0x0Du}, - {0x28u, 0x0Du}, - {0x29u, 0x40u}, - {0x2Cu, 0x0Du}, - {0x30u, 0x70u}, - {0x33u, 0x40u}, - {0x35u, 0x07u}, - {0x36u, 0x0Fu}, - {0x37u, 0x38u}, - {0x3Au, 0x80u}, - {0x3Fu, 0x04u}, - {0x58u, 0x0Bu}, + {0x86u, 0x0Fu}, + {0x06u, 0x44u}, + {0x07u, 0x03u}, + {0x09u, 0x10u}, + {0x10u, 0x44u}, + {0x12u, 0x22u}, + {0x16u, 0x03u}, + {0x17u, 0x04u}, + {0x19u, 0x04u}, + {0x1Au, 0x30u}, + {0x1Bu, 0x01u}, + {0x1Du, 0x08u}, + {0x1Eu, 0x40u}, + {0x21u, 0x04u}, + {0x23u, 0x02u}, + {0x24u, 0x08u}, + {0x28u, 0x44u}, + {0x2Au, 0x11u}, + {0x2Bu, 0x04u}, + {0x2Eu, 0x04u}, + {0x31u, 0x10u}, + {0x32u, 0x07u}, + {0x33u, 0x07u}, + {0x34u, 0x70u}, + {0x35u, 0x08u}, + {0x36u, 0x08u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x11u}, + {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x99u}, {0x5Fu, 0x01u}, - {0x80u, 0x24u}, - {0x82u, 0x09u}, - {0x85u, 0x08u}, + {0x84u, 0x18u}, + {0x86u, 0x60u}, {0x87u, 0x04u}, - {0x8Au, 0x18u}, - {0x8Bu, 0x09u}, - {0x8Eu, 0x03u}, - {0x96u, 0x24u}, - {0x98u, 0x24u}, - {0x9Au, 0x12u}, - {0x9Eu, 0x20u}, - {0x9Fu, 0x06u}, - {0xA1u, 0x08u}, - {0xA2u, 0x80u}, - {0xA3u, 0x03u}, - {0xA6u, 0x04u}, - {0xAAu, 0x40u}, - {0xACu, 0x40u}, - {0xAEu, 0x80u}, - {0xAFu, 0x08u}, - {0xB0u, 0xC0u}, - {0xB1u, 0x0Eu}, - {0xB4u, 0x38u}, - {0xB5u, 0x01u}, - {0xB6u, 0x07u}, - {0xBEu, 0x01u}, - {0xBFu, 0x10u}, + {0x88u, 0x07u}, + {0x8Bu, 0x08u}, + {0x8Du, 0x08u}, + {0x8Fu, 0x10u}, + {0x90u, 0x28u}, + {0x92u, 0x50u}, + {0x93u, 0x03u}, + {0x98u, 0x04u}, + {0x9Bu, 0x04u}, + {0xA0u, 0x30u}, + {0xA2u, 0x48u}, + {0xA3u, 0x10u}, + {0xA5u, 0x04u}, + {0xA6u, 0x02u}, + {0xA7u, 0x01u}, + {0xA8u, 0x01u}, + {0xADu, 0x04u}, + {0xAEu, 0x07u}, + {0xAFu, 0x02u}, + {0xB1u, 0x18u}, + {0xB2u, 0x78u}, + {0xB4u, 0x07u}, + {0xB7u, 0x07u}, + {0xBEu, 0x14u}, + {0xBFu, 0x01u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x99u}, + {0xDCu, 0x90u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x60u}, - {0x03u, 0x60u}, - {0x05u, 0x50u}, - {0x06u, 0x40u}, - {0x07u, 0x04u}, - {0x0Au, 0x22u}, - {0x0Du, 0x14u}, - {0x0Eu, 0x01u}, - {0x11u, 0x14u}, - {0x13u, 0x41u}, - {0x15u, 0x40u}, - {0x16u, 0xA4u}, - {0x18u, 0x40u}, - {0x1Au, 0x02u}, - {0x1Du, 0x50u}, - {0x1Eu, 0x40u}, - {0x21u, 0x20u}, - {0x22u, 0x84u}, - {0x23u, 0x08u}, - {0x25u, 0x10u}, - {0x27u, 0x80u}, - {0x29u, 0x01u}, - {0x2Bu, 0x04u}, - {0x2Cu, 0x02u}, - {0x2Fu, 0x40u}, - {0x31u, 0x20u}, - {0x32u, 0x80u}, - {0x37u, 0x80u}, - {0x39u, 0x28u}, - {0x3Au, 0x42u}, - {0x3Bu, 0x80u}, - {0x3Cu, 0x10u}, + {0x00u, 0x04u}, + {0x05u, 0x08u}, + {0x06u, 0x08u}, + {0x09u, 0x80u}, + {0x0Au, 0x54u}, + {0x0Cu, 0x02u}, + {0x0Eu, 0x08u}, + {0x12u, 0x08u}, + {0x13u, 0x48u}, + {0x14u, 0x08u}, + {0x16u, 0x01u}, + {0x17u, 0x05u}, + {0x19u, 0x08u}, + {0x1Au, 0x16u}, + {0x1Bu, 0x10u}, + {0x1Du, 0x18u}, + {0x21u, 0x04u}, + {0x22u, 0x12u}, + {0x24u, 0x40u}, + {0x27u, 0x01u}, + {0x29u, 0x21u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x20u}, + {0x30u, 0x40u}, + {0x31u, 0x24u}, + {0x33u, 0x20u}, + {0x35u, 0x20u}, + {0x37u, 0x01u}, + {0x39u, 0x08u}, + {0x3Bu, 0x10u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, {0x3Fu, 0x04u}, - {0x58u, 0x84u}, - {0x59u, 0x02u}, - {0x5Bu, 0x10u}, - {0x6Du, 0x40u}, - {0x78u, 0x02u}, - {0x7Cu, 0x80u}, - {0x7Fu, 0x01u}, - {0x80u, 0x40u}, - {0x81u, 0x20u}, - {0x86u, 0x80u}, - {0xC0u, 0xDFu}, - {0xC2u, 0xE5u}, - {0xC4u, 0xFFu}, - {0xCAu, 0x95u}, - {0xCCu, 0x1Cu}, - {0xCEu, 0x6Fu}, - {0xD6u, 0x0Fu}, - {0xDEu, 0x01u}, - {0xE0u, 0x04u}, - {0xE4u, 0x08u}, - {0x0Cu, 0x01u}, - {0x14u, 0x01u}, - {0x18u, 0x02u}, - {0x2Eu, 0x01u}, - {0x36u, 0x03u}, - {0x3Au, 0xC0u}, - {0x58u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x09u}, - {0x5Fu, 0x01u}, - {0x84u, 0x96u}, + {0x5Cu, 0x40u}, + {0x67u, 0x02u}, + {0x69u, 0x80u}, + {0x82u, 0x10u}, + {0x83u, 0x01u}, + {0xC0u, 0x64u}, + {0xC2u, 0x5Fu}, + {0xC4u, 0xF7u}, + {0xCAu, 0xD5u}, + {0xCCu, 0xAEu}, + {0xCEu, 0x76u}, + {0xD6u, 0x10u}, + {0xD8u, 0x10u}, + {0xE4u, 0x04u}, + {0x82u, 0x40u}, + {0x83u, 0x06u}, + {0x84u, 0x16u}, {0x85u, 0x10u}, - {0x86u, 0x69u}, - {0x87u, 0x2Du}, - {0x89u, 0x67u}, - {0x8Au, 0xFFu}, - {0x8Bu, 0x18u}, - {0x8Cu, 0x33u}, - {0x8Du, 0x02u}, - {0x8Eu, 0xCCu}, - {0x94u, 0x55u}, - {0x96u, 0xAAu}, - {0x9Bu, 0x40u}, - {0xA0u, 0x0Fu}, - {0xA1u, 0x02u}, - {0xA2u, 0xF0u}, - {0xA4u, 0xFFu}, - {0xA5u, 0x01u}, - {0xA7u, 0x02u}, - {0xADu, 0x16u}, - {0xAEu, 0xFFu}, - {0xAFu, 0x48u}, - {0xB1u, 0x08u}, - {0xB3u, 0x70u}, - {0xB5u, 0x07u}, - {0xB6u, 0xFFu}, - {0xBEu, 0x40u}, - {0xBFu, 0x01u}, - {0xC0u, 0x32u}, - {0xC1u, 0x05u}, - {0xC2u, 0x40u}, - {0xC5u, 0xD2u}, - {0xC6u, 0x0Cu}, - {0xC7u, 0xEFu}, - {0xC8u, 0x37u}, + {0x86u, 0x48u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x02u}, + {0x8Fu, 0x20u}, + {0x90u, 0x67u}, + {0x92u, 0x18u}, + {0x94u, 0x01u}, + {0x96u, 0x02u}, + {0x98u, 0x10u}, + {0x99u, 0x28u}, + {0x9Au, 0x2Du}, + {0x9Bu, 0x02u}, + {0x9Du, 0x01u}, + {0xA0u, 0x80u}, + {0xA1u, 0x48u}, + {0xA3u, 0x04u}, + {0xA4u, 0x02u}, + {0xA9u, 0x20u}, + {0xABu, 0x08u}, + {0xB0u, 0x07u}, + {0xB1u, 0x0Eu}, + {0xB2u, 0x80u}, + {0xB3u, 0x10u}, + {0xB4u, 0x70u}, + {0xB5u, 0x60u}, + {0xB6u, 0x08u}, + {0xB7u, 0x01u}, + {0xBBu, 0x30u}, + {0xBEu, 0x44u}, + {0xBFu, 0x44u}, + {0xC0u, 0x24u}, + {0xC1u, 0x06u}, + {0xC2u, 0x50u}, + {0xC5u, 0xCFu}, + {0xC6u, 0xD2u}, + {0xC7u, 0x0Eu}, + {0xC8u, 0x1Fu}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, {0xCBu, 0xFFu}, @@ -588,7 +578,7 @@ void cyfitter_cfg(void) {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x90u}, + {0xDCu, 0x99u}, {0xDDu, 0x09u}, {0xDFu, 0x01u}, {0xE2u, 0xC0u}, @@ -596,729 +586,675 @@ void cyfitter_cfg(void) {0xE8u, 0x40u}, {0xE9u, 0x40u}, {0xEEu, 0x08u}, - {0x01u, 0x80u}, - {0x02u, 0x10u}, - {0x03u, 0x04u}, - {0x04u, 0x08u}, - {0x05u, 0x40u}, - {0x07u, 0x10u}, - {0x0Au, 0x10u}, - {0x0Fu, 0x14u}, - {0x11u, 0x40u}, - {0x13u, 0x0Au}, - {0x15u, 0x40u}, - {0x1Bu, 0x80u}, - {0x1Du, 0x40u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x40u}, - {0x20u, 0x50u}, - {0x21u, 0x14u}, - {0x23u, 0x14u}, - {0x29u, 0x42u}, - {0x2Au, 0x08u}, - {0x30u, 0x20u}, - {0x38u, 0x80u}, - {0x39u, 0x28u}, - {0x40u, 0x50u}, - {0x41u, 0x10u}, - {0x48u, 0x20u}, - {0x49u, 0x02u}, - {0x4Au, 0x01u}, - {0x50u, 0x44u}, - {0x52u, 0x40u}, - {0x53u, 0x01u}, - {0x58u, 0x50u}, - {0x5Au, 0x0Au}, - {0x60u, 0x08u}, - {0x61u, 0x08u}, - {0x63u, 0x82u}, - {0x68u, 0x06u}, - {0x6Au, 0x01u}, - {0x6Bu, 0x20u}, - {0x6Du, 0x40u}, - {0x71u, 0x21u}, - {0x72u, 0x22u}, - {0x81u, 0x40u}, - {0x82u, 0x80u}, - {0x83u, 0x42u}, - {0x86u, 0x08u}, - {0x89u, 0x08u}, - {0x8Au, 0x01u}, - {0x8Fu, 0x08u}, - {0x92u, 0x48u}, - {0x94u, 0x10u}, - {0x95u, 0x3Cu}, - {0x96u, 0x21u}, - {0x97u, 0xC7u}, - {0x9Bu, 0x8Cu}, - {0x9Cu, 0x06u}, - {0x9Du, 0x03u}, - {0x9Eu, 0xA6u}, - {0x9Fu, 0x50u}, - {0xA1u, 0x10u}, - {0xA4u, 0x12u}, - {0xA7u, 0x20u}, - {0xABu, 0x04u}, - {0xADu, 0x40u}, - {0xB5u, 0x10u}, - {0xC0u, 0x87u}, - {0xC2u, 0x64u}, - {0xC4u, 0x8Du}, - {0xCAu, 0x0Bu}, - {0xCCu, 0x04u}, - {0xCEu, 0x0Eu}, - {0xD0u, 0x07u}, - {0xD2u, 0x08u}, + {0x00u, 0x88u}, + {0x02u, 0x80u}, + {0x09u, 0x04u}, + {0x0Au, 0x44u}, + {0x11u, 0x02u}, + {0x12u, 0x10u}, + {0x18u, 0x14u}, + {0x19u, 0xA1u}, + {0x1Au, 0x44u}, + {0x1Bu, 0x02u}, + {0x20u, 0x08u}, + {0x21u, 0x21u}, + {0x22u, 0x04u}, + {0x23u, 0x01u}, + {0x29u, 0x21u}, + {0x31u, 0x20u}, + {0x33u, 0x40u}, + {0x39u, 0xA2u}, + {0x3Bu, 0x08u}, + {0x40u, 0x04u}, + {0x42u, 0x40u}, + {0x48u, 0x54u}, + {0x49u, 0x80u}, + {0x4Au, 0x08u}, + {0x52u, 0x94u}, + {0x53u, 0x10u}, + {0x58u, 0x80u}, + {0x5Au, 0x2Au}, + {0x60u, 0x10u}, + {0x62u, 0x02u}, + {0x63u, 0x09u}, + {0x68u, 0x80u}, + {0x69u, 0x24u}, + {0x6Au, 0x80u}, + {0x71u, 0x84u}, + {0x73u, 0x44u}, + {0x81u, 0x05u}, + {0x82u, 0x04u}, + {0x87u, 0x1Cu}, + {0x8Du, 0x10u}, + {0x91u, 0x80u}, + {0x92u, 0x22u}, + {0x93u, 0x02u}, + {0x94u, 0x04u}, + {0x96u, 0x40u}, + {0x97u, 0x54u}, + {0x99u, 0x10u}, + {0x9Cu, 0x48u}, + {0x9Du, 0x25u}, + {0x9Eu, 0x29u}, + {0x9Fu, 0x0Cu}, + {0xA1u, 0x08u}, + {0xA2u, 0x02u}, + {0xA3u, 0x10u}, + {0xA5u, 0xE0u}, + {0xA6u, 0x0Cu}, + {0xABu, 0x10u}, + {0xACu, 0x02u}, + {0xADu, 0x04u}, + {0xAFu, 0x01u}, + {0xB5u, 0x02u}, + {0xC0u, 0x0Du}, + {0xC2u, 0x0Eu}, + {0xC4u, 0x0Cu}, + {0xCAu, 0x05u}, + {0xCCu, 0x0Cu}, + {0xCEu, 0x0Fu}, + {0xD0u, 0x05u}, + {0xD2u, 0x0Cu}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE2u, 0x14u}, - {0xE4u, 0x01u}, - {0xE6u, 0x02u}, - {0xECu, 0x08u}, - {0xEEu, 0x04u}, - {0x00u, 0x40u}, - {0x03u, 0x04u}, - {0x06u, 0x04u}, - {0x07u, 0x30u}, - {0x09u, 0x41u}, - {0x0Eu, 0x03u}, - {0x0Fu, 0x41u}, - {0x11u, 0x23u}, - {0x12u, 0x18u}, - {0x13u, 0x0Cu}, - {0x14u, 0x40u}, - {0x15u, 0x02u}, - {0x17u, 0x01u}, - {0x19u, 0x41u}, - {0x1Au, 0x20u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x41u}, - {0x20u, 0x24u}, - {0x21u, 0x41u}, - {0x22u, 0x09u}, - {0x24u, 0x24u}, - {0x25u, 0x12u}, - {0x26u, 0x12u}, - {0x27u, 0x0Du}, - {0x29u, 0x05u}, - {0x2Au, 0x24u}, - {0x2Bu, 0x0Au}, - {0x2Cu, 0x40u}, - {0x2Fu, 0x08u}, - {0x30u, 0x38u}, - {0x31u, 0x40u}, - {0x32u, 0x40u}, - {0x33u, 0x03u}, - {0x35u, 0x3Cu}, - {0x36u, 0x07u}, - {0x38u, 0x08u}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, + {0xE0u, 0x01u}, + {0xE2u, 0x4Cu}, + {0xE4u, 0x02u}, + {0xE6u, 0x09u}, + {0xE8u, 0x40u}, + {0x04u, 0x24u}, + {0x06u, 0x49u}, + {0x0Cu, 0x24u}, + {0x0Eu, 0x12u}, + {0x0Fu, 0xFFu}, + {0x11u, 0xFFu}, + {0x12u, 0x04u}, + {0x15u, 0x96u}, + {0x16u, 0x03u}, + {0x17u, 0x69u}, + {0x19u, 0x55u}, + {0x1Au, 0x64u}, + {0x1Bu, 0xAAu}, + {0x1Du, 0x33u}, + {0x1Eu, 0x18u}, + {0x1Fu, 0xCCu}, + {0x21u, 0x0Fu}, + {0x22u, 0x20u}, + {0x23u, 0xF0u}, + {0x27u, 0xFFu}, + {0x32u, 0x07u}, + {0x34u, 0x40u}, + {0x35u, 0xFFu}, + {0x36u, 0x38u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x10u}, {0x58u, 0x04u}, - {0x59u, 0x0Bu}, + {0x59u, 0x04u}, + {0x5Cu, 0x09u}, + {0x5Fu, 0x01u}, + {0x82u, 0x20u}, + {0x84u, 0x11u}, + {0x85u, 0x06u}, + {0x86u, 0x22u}, + {0x89u, 0x20u}, + {0x8Au, 0x10u}, + {0x8Bu, 0x18u}, + {0x8Eu, 0xC0u}, + {0x90u, 0x02u}, + {0x92u, 0x0Du}, + {0x94u, 0x0Du}, + {0x95u, 0x49u}, + {0x97u, 0x32u}, + {0x98u, 0x82u}, + {0x99u, 0x59u}, + {0x9Au, 0x38u}, + {0x9Bu, 0x24u}, + {0x9Cu, 0x0Du}, + {0xA0u, 0x0Du}, + {0xA4u, 0x42u}, + {0xA5u, 0x6Au}, + {0xA6u, 0x34u}, + {0xA7u, 0x11u}, + {0xA8u, 0x0Du}, + {0xACu, 0x0Du}, + {0xB0u, 0x0Fu}, + {0xB3u, 0x07u}, + {0xB5u, 0x38u}, + {0xB6u, 0xF0u}, + {0xB7u, 0x40u}, + {0xB9u, 0x08u}, + {0xBAu, 0x02u}, + {0xBBu, 0x20u}, + {0xBFu, 0x40u}, + {0xD4u, 0x09u}, + {0xD8u, 0x08u}, + {0xD9u, 0x08u}, + {0xDBu, 0x08u}, + {0xDCu, 0x99u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x08u}, + {0x03u, 0x02u}, + {0x05u, 0x54u}, + {0x06u, 0x81u}, + {0x0Au, 0xA6u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x19u}, + {0x10u, 0x80u}, + {0x12u, 0x10u}, + {0x13u, 0x08u}, + {0x16u, 0x06u}, + {0x17u, 0x05u}, + {0x18u, 0x08u}, + {0x1Au, 0x22u}, + {0x1Du, 0x42u}, + {0x21u, 0x20u}, + {0x24u, 0x02u}, + {0x25u, 0x14u}, + {0x27u, 0x08u}, + {0x29u, 0x02u}, + {0x2Bu, 0x10u}, + {0x2Cu, 0x20u}, + {0x31u, 0x08u}, + {0x32u, 0x91u}, + {0x34u, 0x08u}, + {0x35u, 0x04u}, + {0x36u, 0x20u}, + {0x39u, 0x80u}, + {0x3Du, 0x28u}, + {0x3Eu, 0x08u}, + {0x4Cu, 0x01u}, + {0x4Du, 0x80u}, + {0x5Cu, 0x40u}, + {0x5Du, 0x08u}, + {0x5Eu, 0x02u}, + {0x5Fu, 0x20u}, + {0x65u, 0x80u}, + {0x6Du, 0x80u}, + {0x79u, 0x02u}, + {0x7Au, 0x80u}, + {0x7Fu, 0x01u}, + {0x81u, 0x62u}, + {0x88u, 0x41u}, + {0x89u, 0x01u}, + {0x8Eu, 0x30u}, + {0x8Fu, 0x10u}, + {0x91u, 0x86u}, + {0x92u, 0x84u}, + {0x93u, 0x02u}, + {0x9Cu, 0x88u}, + {0x9Eu, 0x29u}, + {0x9Fu, 0x04u}, + {0xA0u, 0xC4u}, + {0xA1u, 0x08u}, + {0xA3u, 0x12u}, + {0xA5u, 0x40u}, + {0xA6u, 0x04u}, + {0xA7u, 0x04u}, + {0xA9u, 0x40u}, + {0xABu, 0x40u}, + {0xACu, 0x40u}, + {0xAFu, 0x10u}, + {0xB0u, 0x10u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xFFu}, + {0xC4u, 0xF8u}, + {0xCAu, 0x43u}, + {0xCCu, 0x6Fu}, + {0xCEu, 0x68u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x10u}, + {0xDEu, 0x10u}, + {0xE0u, 0x05u}, + {0xE4u, 0x44u}, + {0xE6u, 0x02u}, + {0xEAu, 0x08u}, + {0xEEu, 0x09u}, + {0x00u, 0x01u}, + {0x01u, 0x86u}, + {0x04u, 0x07u}, + {0x05u, 0x04u}, + {0x06u, 0x18u}, + {0x07u, 0x40u}, + {0x08u, 0x01u}, + {0x0Bu, 0x86u}, + {0x0Cu, 0x04u}, + {0x0Du, 0x86u}, + {0x10u, 0x10u}, + {0x11u, 0x82u}, + {0x12u, 0x40u}, + {0x15u, 0x69u}, + {0x17u, 0x06u}, + {0x18u, 0x22u}, + {0x19u, 0x82u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x04u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x10u}, + {0x20u, 0x01u}, + {0x21u, 0x10u}, + {0x24u, 0x08u}, + {0x25u, 0x01u}, + {0x26u, 0x21u}, + {0x27u, 0xAEu}, + {0x29u, 0xE7u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x01u}, + {0x2Du, 0x86u}, + {0x30u, 0x08u}, + {0x31u, 0x10u}, + {0x33u, 0xE0u}, + {0x34u, 0x40u}, + {0x35u, 0x0Fu}, + {0x36u, 0x3Fu}, + {0x38u, 0x80u}, + {0x39u, 0x22u}, + {0x3Bu, 0x0Cu}, + {0x3Eu, 0x41u}, + {0x54u, 0x40u}, + {0x58u, 0x08u}, + {0x59u, 0x08u}, + {0x5Bu, 0x08u}, {0x5Cu, 0x99u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x82u, 0xFFu}, - {0x84u, 0x96u}, - {0x85u, 0xFFu}, - {0x86u, 0x69u}, - {0x88u, 0xFFu}, - {0x8Cu, 0x0Fu}, - {0x8Du, 0x33u}, - {0x8Eu, 0xF0u}, - {0x8Fu, 0xCCu}, - {0x90u, 0x33u}, - {0x91u, 0x0Fu}, - {0x92u, 0xCCu}, - {0x93u, 0xF0u}, - {0x95u, 0xFFu}, - {0x99u, 0x69u}, - {0x9Bu, 0x96u}, - {0x9Du, 0x55u}, - {0x9Fu, 0xAAu}, - {0xA6u, 0xFFu}, - {0xACu, 0x55u}, - {0xAEu, 0xAAu}, - {0xAFu, 0xFFu}, - {0xB6u, 0xFFu}, + {0x82u, 0x03u}, + {0x84u, 0x04u}, + {0x86u, 0x01u}, + {0x8Cu, 0x04u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0xFFu}, + {0x93u, 0xFFu}, + {0x95u, 0x69u}, + {0x97u, 0x96u}, + {0x99u, 0x55u}, + {0x9Au, 0x04u}, + {0x9Bu, 0xAAu}, + {0x9Du, 0x33u}, + {0x9Fu, 0xCCu}, + {0xA1u, 0x0Fu}, + {0xA3u, 0xF0u}, + {0xA6u, 0x04u}, + {0xA7u, 0xFFu}, + {0xB0u, 0x07u}, {0xB7u, 0xFFu}, - {0xBEu, 0x40u}, {0xBFu, 0x40u}, - {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDDu, 0x90u}, + {0xDCu, 0x09u}, {0xDFu, 0x01u}, {0x00u, 0x08u}, - {0x01u, 0x80u}, - {0x03u, 0x80u}, - {0x04u, 0x02u}, - {0x05u, 0x40u}, - {0x06u, 0x18u}, - {0x07u, 0x16u}, - {0x09u, 0x24u}, - {0x0Au, 0x81u}, + {0x01u, 0x02u}, + {0x03u, 0x02u}, + {0x04u, 0xA0u}, + {0x05u, 0x05u}, + {0x06u, 0x04u}, + {0x0Au, 0x04u}, + {0x0Cu, 0x20u}, + {0x0Eu, 0x09u}, {0x0Fu, 0x80u}, - {0x11u, 0x81u}, - {0x13u, 0x14u}, - {0x17u, 0x88u}, - {0x19u, 0x80u}, - {0x1Au, 0x80u}, - {0x1Bu, 0x48u}, - {0x1Eu, 0x01u}, - {0x20u, 0x04u}, - {0x22u, 0x0Bu}, - {0x25u, 0x40u}, - {0x28u, 0x20u}, - {0x29u, 0x10u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x02u}, - {0x2Du, 0x40u}, - {0x30u, 0x20u}, - {0x32u, 0x08u}, - {0x33u, 0x41u}, - {0x37u, 0x9Au}, - {0x38u, 0x04u}, - {0x39u, 0x92u}, - {0x3Bu, 0x40u}, - {0x3Eu, 0x08u}, - {0x3Fu, 0x80u}, - {0x4Eu, 0x08u}, - {0x4Fu, 0x20u}, - {0x5Du, 0x01u}, - {0x5Eu, 0x42u}, - {0x64u, 0x02u}, - {0x66u, 0x80u}, - {0x78u, 0x02u}, - {0x80u, 0x0Cu}, - {0x8Au, 0x80u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x40u}, - {0x8Eu, 0x40u}, - {0x91u, 0x68u}, - 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- {0x0Au, 0x44u}, - {0x0Bu, 0x12u}, - {0x0Du, 0x14u}, - {0x0Eu, 0x02u}, - {0x11u, 0x80u}, - {0x12u, 0x04u}, - {0x13u, 0x0Au}, - {0x19u, 0x18u}, - {0x1Au, 0x44u}, - {0x1Bu, 0x20u}, - {0x1Du, 0x40u}, - {0x20u, 0x30u}, - {0x21u, 0x20u}, - {0x22u, 0x90u}, - {0x23u, 0x94u}, - {0x29u, 0x20u}, - {0x2Au, 0x42u}, - {0x2Bu, 0x20u}, - {0x30u, 0x20u}, + {0x00u, 0x10u}, + {0x05u, 0x28u}, + {0x07u, 0x02u}, + {0x09u, 0x10u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x20u}, + {0x0Du, 0x20u}, + {0x0Eu, 0x21u}, + {0x10u, 0x08u}, + {0x11u, 0x40u}, + {0x12u, 0x80u}, + {0x14u, 0x40u}, + {0x16u, 0x20u}, + {0x1Au, 0x01u}, + {0x1Eu, 0xA0u}, + {0x20u, 0x40u}, + {0x22u, 0x20u}, + {0x25u, 0x20u}, + {0x28u, 0x80u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x08u}, {0x32u, 0x08u}, - {0x33u, 0x40u}, - {0x36u, 0x02u}, - {0x37u, 0x01u}, - {0x39u, 0x40u}, - {0x3Au, 0x04u}, - {0x3Bu, 0x14u}, - {0x58u, 0x20u}, - {0x59u, 0x04u}, - {0x5Au, 0x02u}, - {0x5Bu, 0x80u}, - {0x62u, 0x80u}, - {0x65u, 0x08u}, + {0x34u, 0x18u}, + {0x36u, 0x01u}, + {0x3Du, 0x20u}, + {0x3Fu, 0x08u}, + {0x5Cu, 0x02u}, + {0x5Fu, 0x94u}, + {0x7Fu, 0x80u}, + {0x81u, 0x50u}, + {0x82u, 0x20u}, + {0x83u, 0x04u}, + {0x86u, 0x40u}, + {0x88u, 0x50u}, + {0x8Au, 0x01u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x18u}, + {0x8Eu, 0x81u}, + {0x93u, 0x10u}, + {0x98u, 0x82u}, + {0x9Bu, 0x80u}, + {0xA3u, 0x80u}, + {0xB3u, 0x10u}, + {0xC0u, 0xE2u}, + {0xC2u, 0xE7u}, + {0xC4u, 0x3Bu}, + {0xCAu, 0x61u}, + {0xCCu, 0xE2u}, + {0xCEu, 0x60u}, + {0xD6u, 0xF0u}, + {0xDEu, 0x80u}, + {0xE0u, 0xF0u}, + {0xE4u, 0x24u}, + {0xEAu, 0x08u}, + {0xECu, 0x80u}, + {0xEEu, 0x09u}, + {0x83u, 0x80u}, + {0x84u, 0x02u}, + {0x98u, 0x80u}, + {0xA3u, 0x80u}, + {0xE2u, 0x0Cu}, + {0xE6u, 0x09u}, + {0x83u, 0x80u}, + {0x84u, 0x80u}, + {0xE6u, 0x02u}, + {0x80u, 0x01u}, + {0x94u, 0x02u}, + {0xB5u, 0x04u}, + {0x05u, 0x05u}, + {0x06u, 0x0Au}, + {0x0Eu, 0x99u}, + {0x15u, 0x01u}, + {0x17u, 0x14u}, + {0x1Du, 0x8Du}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x1Au}, + {0x27u, 0x40u}, + {0x2Eu, 0x02u}, + {0x2Fu, 0x0Au}, + {0x36u, 0x6Au}, + {0x3Eu, 0x15u}, + {0x3Fu, 0x80u}, + {0x45u, 0xA8u}, + {0x4Cu, 0x01u}, + {0x4Du, 0x09u}, + {0x4Eu, 0x08u}, + {0x4Fu, 0x01u}, + {0x56u, 0xA8u}, + {0x57u, 0x40u}, {0x66u, 0x10u}, - {0x67u, 0x02u}, - {0x78u, 0x02u}, - {0x7Cu, 0x02u}, - {0x89u, 0x40u}, - {0x91u, 0x6Cu}, - {0x92u, 0x02u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x80u}, + {0x6Eu, 0x95u}, + {0x6Fu, 0x11u}, + {0x75u, 0x80u}, + {0x76u, 0x02u}, + {0x7Fu, 0x01u}, {0x93u, 0x02u}, - {0x94u, 0x10u}, - {0x96u, 0x60u}, - {0x97u, 0x14u}, - {0x98u, 0x02u}, - {0x99u, 0x24u}, - {0x9Au, 0x52u}, - {0x9Bu, 0x6Au}, - {0x9Du, 0x50u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x20u}, - {0xA1u, 0x40u}, - {0xA2u, 0x09u}, - {0xA4u, 0x10u}, - {0xA5u, 0x20u}, - {0xA7u, 0x20u}, - {0xC0u, 0xAFu}, - {0xC2u, 0xEFu}, - {0xC4u, 0x0Fu}, - {0xCAu, 0x0Fu}, - {0xCCu, 0x0Eu}, - {0xCEu, 0x0Eu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x78u}, - {0xDEu, 0x81u}, - {0xEAu, 0x04u}, + {0x94u, 0x20u}, + {0x96u, 0x11u}, + {0x97u, 0x21u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x04u}, + {0x9Du, 0x8Du}, + {0x9Eu, 0xAAu}, + {0x9Fu, 0x51u}, + {0xA1u, 0x20u}, + {0xA2u, 0x2Eu}, + {0xA5u, 0x40u}, + {0xA6u, 0x01u}, + {0xA7u, 0x48u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xF0u}, + {0xC4u, 0x70u}, + {0xCAu, 0xB0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0xF0u}, + {0xD0u, 0x70u}, + {0xD2u, 0x30u}, + {0xD8u, 0x20u}, + {0xDEu, 0x10u}, {0xEEu, 0x0Au}, - {0x88u, 0x40u}, - {0x96u, 0x04u}, - {0x97u, 0x80u}, - {0x9Cu, 0x40u}, - {0x9Du, 0x08u}, - {0xA8u, 0x10u}, - {0xE0u, 0x80u}, + {0x9Du, 0x20u}, {0xEEu, 0x0Au}, - {0xB2u, 0x04u}, - {0xB3u, 0x40u}, - {0xB5u, 0x08u}, - {0xE8u, 0x40u}, - {0xECu, 0xA0u}, + {0xB5u, 0x20u}, + {0xE8u, 0x10u}, {0x33u, 0x80u}, {0x36u, 0x40u}, - {0x5Au, 0x80u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, {0x5Eu, 0x02u}, - {0x62u, 0x01u}, - {0x63u, 0x02u}, - {0x67u, 0x08u}, - {0x82u, 0x03u}, - {0x87u, 0x04u}, + {0x62u, 0x02u}, + {0x66u, 0x04u}, + {0x82u, 0x04u}, {0xCCu, 0x30u}, - {0xD4u, 0x80u}, + {0xD4u, 0x40u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x20u}, - {0xE6u, 0x30u}, - {0x51u, 0x08u}, - {0x53u, 0x01u}, - {0x83u, 0x05u}, - {0x8Eu, 0x40u}, - {0x96u, 0x80u}, - {0x9Au, 0x02u}, - {0xA6u, 0x41u}, + {0xE2u, 0x80u}, + {0x52u, 0x20u}, + {0x5Fu, 0x20u}, + {0x8Fu, 0x04u}, + {0x94u, 0x02u}, + {0x9Eu, 0x08u}, + {0xA6u, 0x40u}, {0xA7u, 0x80u}, - {0xAFu, 0x01u}, - {0xD4u, 0xA0u}, - {0xE0u, 0x80u}, - {0xE6u, 0x20u}, - {0xEEu, 0x10u}, - {0x8Eu, 0x01u}, - {0x9Au, 0x02u}, - {0x9Fu, 0x04u}, - {0xA6u, 0x41u}, + {0xAAu, 0x01u}, + {0xACu, 0x04u}, + {0xAEu, 0x02u}, + {0xB4u, 0x01u}, + {0xD4u, 0x20u}, + {0xD6u, 0x20u}, + {0xEAu, 0x50u}, + {0xEEu, 0x80u}, + {0x86u, 0x08u}, + {0x8Eu, 0x08u}, + {0x94u, 0x02u}, + {0x9Eu, 0x08u}, + {0xA3u, 0x04u}, + {0xA6u, 0x60u}, {0xA7u, 0x80u}, - {0xB5u, 0x08u}, - {0x81u, 0x04u}, - {0x9Au, 0x02u}, - {0x9Fu, 0x84u}, - {0xA6u, 0x40u}, + {0xABu, 0x20u}, + {0xE6u, 0x40u}, + {0xEAu, 0x80u}, + {0x94u, 0x02u}, + {0x98u, 0x20u}, + {0xA3u, 0x04u}, + {0xA6u, 0x48u}, {0xA7u, 0x80u}, - {0xABu, 0x80u}, - {0xE4u, 0x80u}, - {0xE8u, 0x80u}, - {0x0Eu, 0x80u}, - {0x10u, 0x80u}, - {0x50u, 0x04u}, - {0x54u, 0x10u}, - {0x5Au, 0x10u}, + {0xAAu, 0x20u}, + {0xB0u, 0x20u}, + {0xEEu, 0x80u}, + {0x0Cu, 0x02u}, + {0x12u, 0x20u}, + {0x53u, 0x80u}, + {0x55u, 0x80u}, + {0x58u, 0x80u}, {0x5Cu, 0x40u}, + {0x86u, 0x20u}, {0xC2u, 0x04u}, {0xC4u, 0x08u}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x03u, 0x01u}, - {0x04u, 0x80u}, - {0x06u, 0x80u}, - {0x08u, 0x20u}, - {0x09u, 0x04u}, - {0x0Eu, 0x02u}, - {0x0Fu, 0x40u}, - {0x80u, 0x04u}, - {0x86u, 0x40u}, - {0x94u, 0x08u}, - {0x96u, 0x10u}, - {0x9Cu, 0x20u}, - {0xA2u, 0x40u}, - {0xA4u, 0x10u}, - {0xA8u, 0x20u}, - {0xB4u, 0xC0u}, + {0x01u, 0x20u}, + {0x06u, 0x40u}, + {0x07u, 0x08u}, + {0x08u, 0x02u}, + {0x0Bu, 0x08u}, + {0x0Du, 0x04u}, + {0x0Fu, 0x02u}, + {0x80u, 0x02u}, + {0x81u, 0x20u}, + {0x85u, 0x04u}, + {0x87u, 0x04u}, + {0x94u, 0x40u}, + {0x9Cu, 0x80u}, + {0xA0u, 0x02u}, + {0xA5u, 0x80u}, + {0xA7u, 0x80u}, {0xC0u, 0x07u}, {0xC2u, 0x0Fu}, - {0xE8u, 0x02u}, - {0xEEu, 0x02u}, - {0x90u, 0x80u}, - {0x93u, 0x40u}, - {0x9Bu, 0x01u}, - {0xA2u, 0x01u}, - {0xA4u, 0x10u}, - {0xAAu, 0x10u}, - {0xB2u, 0x80u}, - {0xB5u, 0x04u}, - {0xEEu, 0x06u}, + {0x80u, 0x40u}, + {0x88u, 0x80u}, + {0x8Fu, 0x80u}, + {0x94u, 0x40u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x80u}, + {0xA5u, 0x80u}, + {0xA7u, 0x80u}, + {0xA8u, 0x02u}, + {0xAEu, 0x40u}, + {0xAFu, 0x01u}, + {0xE0u, 0x06u}, {0x08u, 0x08u}, {0x0Fu, 0x40u}, - {0xA8u, 0x40u}, - {0xACu, 0x10u}, - {0xAFu, 0x01u}, - {0xB3u, 0x40u}, - {0xB6u, 0x01u}, + {0xAFu, 0x08u}, + {0xB1u, 0x80u}, {0xC2u, 0x0Cu}, - {0xEAu, 0x0Cu}, - {0x23u, 0x80u}, - {0x27u, 0x04u}, - {0x9Au, 0x22u}, - {0x9Du, 0x04u}, - {0x9Fu, 0x84u}, - {0xAAu, 0x20u}, + {0xE8u, 0x04u}, + {0x22u, 0x08u}, + {0x24u, 0x02u}, + {0x94u, 0x02u}, + {0x98u, 0x20u}, + {0xA3u, 0x04u}, + {0xA6u, 0x08u}, {0xAEu, 0x40u}, {0xAFu, 0x80u}, {0xC8u, 0x60u}, - {0xEAu, 0x20u}, {0xEEu, 0x50u}, - {0x05u, 0x04u}, - {0x56u, 0x22u}, - {0x9Au, 0x22u}, - {0x9Du, 0x04u}, + {0x05u, 0x02u}, + {0x57u, 0x04u}, + {0x58u, 0x20u}, + {0x81u, 0x02u}, + {0x98u, 0x20u}, + {0xA3u, 0x04u}, {0xC0u, 0x20u}, - {0xD4u, 0x40u}, - {0xD6u, 0x20u}, + {0xD4u, 0xC0u}, + {0xE4u, 0x20u}, {0xACu, 0x08u}, {0xAFu, 0x40u}, {0x01u, 0x01u}, @@ -1347,28 +1283,28 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, }; - /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = { - 0xC0u, 0x01u, 0x02u, 0x00u, 0x1Fu, 0x22u, 0x20u, 0x08u, 0xC0u, 0x08u, 0x08u, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, - 0x00u, 0x10u, 0x60u, 0x80u, 0x00u, 0x40u, 0xFFu, 0x00u, 0x7Fu, 0x01u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, - 0xC0u, 0x40u, 0x01u, 0x00u, 0xC0u, 0x01u, 0x04u, 0x00u, 0x80u, 0x07u, 0x00u, 0x18u, 0x00u, 0x04u, 0x9Fu, 0x00u, - 0xFFu, 0x80u, 0x00u, 0x3Fu, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x88u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x04u, - 0x32u, 0x06u, 0x50u, 0x00u, 0x04u, 0xDEu, 0xFCu, 0xB0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, + /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = { + 0x24u, 0xC0u, 0x10u, 0x02u, 0x11u, 0xC0u, 0x22u, 0x04u, 0x08u, 0xC0u, 0x00u, 0x08u, 0xDCu, 0x00u, 0x00u, 0x9Fu, + 0x0Cu, 0x00u, 0xD0u, 0x60u, 0xD0u, 0x7Fu, 0x0Cu, 0x80u, 0x30u, 0x00u, 0x0Fu, 0xFFu, 0xDCu, 0x90u, 0x00u, 0x40u, + 0x00u, 0xC0u, 0x80u, 0x01u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0xD4u, 0x1Fu, 0x08u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, + 0x30u, 0xFFu, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, + 0x26u, 0x03u, 0x10u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x08u, 0x04u, 0x08u, 0x08u, 0x09u, 0x99u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u}, }; uint8 CYDATA i; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 1cdc92f..099248a 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -33,16 +33,6 @@ .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 -/* SCSI_ATN_ISR */ -.set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 -.set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_ATN_ISR__INTC_MASK, 0x800 -.set SCSI_ATN_ISR__INTC_NUMBER, 11 -.set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_11 -.set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 -.set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 - /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX @@ -488,34 +478,34 @@ .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -523,13 +513,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -539,28 +529,32 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -575,24 +569,24 @@ /* SCSI_CTL_IO */ .set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL .set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL /* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG @@ -1051,8 +1045,8 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1060,9 +1054,9 @@ .set scsiTarget_StatusReg__3__MASK, 0x08 .set scsiTarget_StatusReg__3__POS, 3 .set scsiTarget_StatusReg__MASK, 0x0F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST .set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL .set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK @@ -1112,24 +1106,24 @@ /* SD_Clk_Ctl */ .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1301,7 +1295,6 @@ .set SCSI_ATN__DM2, CYREG_PRT12_DM2 .set SCSI_ATN__DR, CYREG_PRT12_DR .set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS -.set SCSI_ATN__INTSTAT, CYREG_PICU12_INTSTAT .set SCSI_ATN__INT__MASK, 0x20 .set SCSI_ATN__INT__PC, CYREG_PRT12_PC5 .set SCSI_ATN__INT__PORT, 12 @@ -1322,7 +1315,6 @@ .set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN .set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ .set SCSI_ATN__SLW, CYREG_PRT12_SLW -.set SCSI_ATN__SNAP, CYREG_PICU12_SNAP /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT4_AG @@ -2671,9 +2663,9 @@ .set CYDEV_CHIP_FAMILY_PSOC5, 3 .set CYDEV_CHIP_DIE_PSOC5LP, 4 .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP -.set BCLK__BUS_CLK__HZ, 64000000 -.set BCLK__BUS_CLK__KHZ, 64000 -.set BCLK__BUS_CLK__MHZ, 64 +.set BCLK__BUS_CLK__HZ, 60000000 +.set BCLK__BUS_CLK__KHZ, 60000 +.set BCLK__BUS_CLK__MHZ, 60 .set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT .set CYDEV_CHIP_DIE_LEOPARD, 1 .set CYDEV_CHIP_DIE_PANTHER, 3 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index e4afa13..962465c 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -33,16 +33,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -/* SCSI_ATN_ISR */ -SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_ATN_ISR__INTC_MASK EQU 0x800 -SCSI_ATN_ISR__INTC_NUMBER EQU 11 -SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11 -SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX @@ -488,34 +478,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -523,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -539,28 +529,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -575,24 +569,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_IO */ SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL /* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1051,8 +1045,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1060,9 +1054,9 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK @@ -1112,24 +1106,24 @@ scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1301,7 +1295,6 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2 SCSI_ATN__DR EQU CYREG_PRT12_DR SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT SCSI_ATN__INT__MASK EQU 0x20 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5 SCSI_ATN__INT__PORT EQU 12 @@ -1322,7 +1315,6 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ SCSI_ATN__SLW EQU CYREG_PRT12_SLW -SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT4_AG @@ -2671,9 +2663,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 CYDEV_CHIP_DIE_PSOC5LP EQU 4 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP -BCLK__BUS_CLK__HZ EQU 64000000 -BCLK__BUS_CLK__KHZ EQU 64000 -BCLK__BUS_CLK__MHZ EQU 64 +BCLK__BUS_CLK__HZ EQU 60000000 +BCLK__BUS_CLK__KHZ EQU 60000 +BCLK__BUS_CLK__MHZ EQU 60 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD EQU 1 CYDEV_CHIP_DIE_PANTHER EQU 3 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index bb7ab3a..05b91a0 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -33,16 +33,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 -; SCSI_ATN_ISR -SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 -SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_ATN_ISR__INTC_MASK EQU 0x800 -SCSI_ATN_ISR__INTC_NUMBER EQU 11 -SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11 -SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 -SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 - ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX @@ -488,34 +478,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -523,13 +513,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -539,28 +529,32 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -575,24 +569,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_IO SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL ; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1051,8 +1045,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1060,9 +1054,9 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK @@ -1112,24 +1106,24 @@ scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL ; SD_Clk_Ctl SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1301,7 +1295,6 @@ SCSI_ATN__DM1 EQU CYREG_PRT12_DM1 SCSI_ATN__DM2 EQU CYREG_PRT12_DM2 SCSI_ATN__DR EQU CYREG_PRT12_DR SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS -SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT SCSI_ATN__INT__MASK EQU 0x20 SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5 SCSI_ATN__INT__PORT EQU 12 @@ -1322,7 +1315,6 @@ SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ SCSI_ATN__SLW EQU CYREG_PRT12_SLW -SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT4_AG @@ -2671,9 +2663,9 @@ CYDEV_CHIP_MEMBER_5B EQU 4 CYDEV_CHIP_FAMILY_PSOC5 EQU 3 CYDEV_CHIP_DIE_PSOC5LP EQU 4 CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP -BCLK__BUS_CLK__HZ EQU 64000000 -BCLK__BUS_CLK__KHZ EQU 64000 -BCLK__BUS_CLK__MHZ EQU 64 +BCLK__BUS_CLK__HZ EQU 60000000 +BCLK__BUS_CLK__KHZ EQU 60000 +BCLK__BUS_CLK__MHZ EQU 60 CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_LEOPARD EQU 1 CYDEV_CHIP_DIE_PANTHER EQU 3 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 3b9f84b..92a14ac 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -45,7 +45,6 @@ #include #include #include -#include #include #include #include diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx index 658cb56..b9aff61 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,12 +1,12 @@ + - - + @@ -87,6 +87,8 @@ + + @@ -94,25 +96,22 @@ - - - + + - - - + + + - - - + \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr index 7e702d8..821b57b 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cydwr differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index c6d5f47..3c24266 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj index 9bcf221..63786d6 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -26,13 +26,6 @@ - - - - - - - @@ -190,13 +183,6 @@ - - - - - - - @@ -1513,14 +1499,14 @@ - + - + @@ -1529,7 +1515,7 @@ - + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd index 9b19422..3770159 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd @@ -493,7 +493,7 @@ SD_Clk_Ctl No description available - 0x40006471 + 0x40006475 0 0x1 @@ -514,7 +514,7 @@ SCSI_CTL_IO No description available - 0x40006472 + 0x40006470 0 0x1 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 5eb78a5..430cf96 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/blinky.c b/software/SCSI2SD/SCSI2SD.cydsn/blinky.c deleted file mode 100755 index 4d9d7ae..0000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/blinky.c +++ /dev/null @@ -1,31 +0,0 @@ -// Copyright (C) 2013 Michael McMaster -// -// This file is part of SCSI2SD. -// -// SCSI2SD is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// SCSI2SD is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with SCSI2SD. If not, see . - -#include "blinky.h" -#include "device.h" - -void scsi2sd_test_blink(void) -{ - // Toggle LED. - while (1) - { - LED1_Write(0); - CyDelay(1000); // ms - LED1_Write(1); - CyDelay(250); // ms - } -} diff --git a/software/SCSI2SD/SCSI2SD.cydsn/blinky.h b/software/SCSI2SD/SCSI2SD.cydsn/blinky.h deleted file mode 100755 index a8fde4b..0000000 --- a/software/SCSI2SD/SCSI2SD.cydsn/blinky.h +++ /dev/null @@ -1,25 +0,0 @@ -// Copyright (C) 2013 Michael McMaster -// -// This file is part of SCSI2SD. -// -// SCSI2SD is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// SCSI2SD is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with SCSI2SD. If not, see . - -#ifndef SCSI2SD_BLINKY_H -#define SCSI2SD_BLINKY_H - -// Helloworld LED blink test. -void scsi2sd_test_blink(void); - - -#endif // SCSI2SD_POST_H diff --git a/software/SCSI2SD/SCSI2SD.cydsn/config.c b/software/SCSI2SD/SCSI2SD.cydsn/config.c index 674d752..98578f9 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/config.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/config.c @@ -1,4 +1,4 @@ -// Copyright (C) 2013 Michael McMaster +// Copyright (C) 2014 Michael McMaster // // This file is part of SCSI2SD. // @@ -20,6 +20,9 @@ #include "USBFS.h" #include "led.h" +#include "scsi.h" +#include "scsiPhy.h" + #include // CYDEV_EEPROM_ROW_SIZE == 16. @@ -31,7 +34,7 @@ static Config shadow = 0, // SCSI ID " codesrc", // vendor (68k Apple Drive Setup: Set to " SEAGATE") " SCSI2SD", //prodId (68k Apple Drive Setup: Set to " ST225N") - "2.0a", // revision (68k Apple Drive Setup: Set to "1.0 ") + " 3.2", // revision (68k Apple Drive Setup: Set to "1.0 ") 1, // enable parity 0, // disable unit attention, 0 // Max blocks (0 == disabled) @@ -94,7 +97,7 @@ void configInit() { int shadowRows, shadowBytes; uint8* eeprom = (uint8*)CYDEV_EE_BASE; - + // We could map cfgPtr directly into the EEPROM memory, // but that would waste power. Copy it to RAM then turn off // the EEPROM. @@ -137,21 +140,21 @@ void configPoll() { return; } - + if (reset) { USBFS_EnableOutEP(USB_EP_OUT); usbInEpState = USB_IDLE; - } + } if(USBFS_GetEPState(USB_EP_OUT) == USBFS_OUT_BUFFER_FULL) { int byteCount; - + ledOn(); - + // The host sent us some data! - byteCount = USBFS_GetEPCount(USB_EP_OUT); + byteCount = USBFS_GetEPCount(USB_EP_OUT); // Assume that byteCount <= sizeof(shadow). // shadow should be padded out to 64bytes, which is the largest @@ -162,20 +165,38 @@ void configPoll() CFG_EEPROM_Start(); saveConfig(); // write to eeprom CFG_EEPROM_Stop(); - + // Send the updated data. usbInEpState = USB_IDLE; // Allow the host to send us another updated config. USBFS_EnableOutEP(USB_EP_OUT); - ledOff(); + ledOff(); } switch (usbInEpState) { case USB_IDLE: shadow.maxBlocks = htonl(shadow.maxBlocks); + + #ifdef MM_DEBUG + memcpy(&shadow.reserved, &scsiDev.cdb, 12); + shadow.reserved[12] = scsiDev.msgIn; + shadow.reserved[13] = scsiDev.msgOut; + shadow.reserved[14] = scsiDev.lastStatus; + shadow.reserved[15] = scsiDev.lastSense; + shadow.reserved[16] = scsiDev.phase; + shadow.reserved[17] = SCSI_ReadPin(SCSI_In_BSY); + shadow.reserved[18] = SCSI_ReadPin(SCSI_In_SEL); + shadow.reserved[19] = SCSI_ReadPin(SCSI_ATN_INT); + shadow.reserved[20] = SCSI_ReadPin(SCSI_RST_INT); + shadow.reserved[21] = scsiDev.rstCount; + shadow.reserved[22] = scsiDev.selCount; + shadow.reserved[23] = scsiDev.msgCount; + shadow.reserved[24] = scsiDev.watchdogTick++; + #endif + USBFS_LoadInEP(USB_EP_IN, (uint8 *)&shadow, sizeof(shadow)); shadow.maxBlocks = ntohl(shadow.maxBlocks); usbInEpState = USB_DATA_SENT; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.c b/software/SCSI2SD/SCSI2SD.cydsn/disk.c index c94aaa8..cfd5b9a 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/disk.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/disk.c @@ -1,4 +1,5 @@ // Copyright (C) 2013 Michael McMaster +// Copyright (C) 2014 Doug Brown // // This file is part of SCSI2SD. // @@ -118,7 +119,7 @@ static void doWrite(uint32 lba, uint32 blocks) scsiDev.phase = DATA_OUT; scsiDev.dataLen = SCSI_BLOCK_SIZE; scsiDev.dataPtr = SCSI_BLOCK_SIZE; // TODO FIX scsiDiskPoll() - + // No need for single-block reads atm. Overhead of the // multi-block read is minimal. transfer.multiBlock = 1; @@ -144,20 +145,20 @@ static void doRead(uint32 lba, uint32 blocks) transfer.currentBlock = 0; scsiDev.phase = DATA_IN; scsiDev.dataLen = 0; // No data yet - + if ((blocks == 1) || (((uint64) lba) + blocks == blockDev.capacity) ) { // We get errors on reading the last sector using a multi-sector // read :-( - transfer.multiBlock = 0; + transfer.multiBlock = 0; } else { transfer.multiBlock = 1; sdPrepareRead(); - } + } } } @@ -354,6 +355,26 @@ int scsiDiskCommand() // SYNCHRONIZE CACHE // We don't have a cache. do nothing. } + else if (command == 0x2F) + { + // VERIFY + // TODO: When they supply data to verify, we should read the data and + // verify it. If they don't supply any data, just say success. + if ((scsiDev.cdb[1] & 0x02) == 0) + { + // They are asking us to do a medium verification with no data + // comparison. Assume success, do nothing. + } + else + { + // TODO. This means they are supplying data to verify against. + // Technically we should probably grab the data and compare it. + scsiDev.status = CHECK_CONDITION; + scsiDev.sense.code = ILLEGAL_REQUEST; + scsiDev.sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } + } else { commandHandled = 0; @@ -406,7 +427,7 @@ void scsiDiskPoll() scsiDev.dataLen = 0; scsiDev.dataPtr = 0; scsiDev.phase = STATUS; - + scsiDiskReset(); if (writeOk) diff --git a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c index 9cc0f23..9cc8f8b 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c @@ -27,8 +27,8 @@ static uint8 StandardResponse[] = 0x00, // "Direct-access device". AKA standard hard disk 0x00, // device type qualifier 0x02, // Complies with ANSI SCSI-2. -0x02, // SCSI-2 Inquiry response -31, // standard length +0x01, // Response format is compatible with the old CCS format. +0x1f, // standard length. 0, 0, //Reserved 0 // We don't support anything at all }; @@ -36,6 +36,19 @@ static uint8 StandardResponse[] = // prodId set by config'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ', // Revision set by config'2','.','0','a' +/* For reference, here's a dump from an Apple branded 500Mb drive from 1994. +$ sudo sg_inq -H /dev/sdd --len 255 +standard INQUIRY: + 00 00 00 02 01 31 00 00 18 51 55 41 4e 54 55 4d 20 ....1...QUANTUM + 10 4c 50 53 32 37 30 20 20 20 20 20 20 20 20 20 20 LPS270 + 20 30 39 30 30 00 00 00 d9 b0 27 34 01 04 b3 01 1b 0900.....'4..... + 30 07 00 a0 00 00 ff ...... + Vendor identification: QUANTUM + Product identification: LPS270 + Product revision level: 0900 +*/ + + static const uint8 SupportedVitalPages[] = { 0x00, // "Direct-access device". AKA standard hard disk @@ -85,7 +98,7 @@ void scsiInquiry() uint8 lun = scsiDev.cdb[1] >> 5; uint32 allocationLength = scsiDev.cdb[4]; if (allocationLength == 0) allocationLength = 256; - + if (!evpd) { if (pageCode) @@ -98,16 +111,14 @@ void scsiInquiry() } else { - uint8* out; memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse)); - out = scsiDev.data + sizeof(StandardResponse); - memcpy(out, config->vendor, sizeof(config->vendor)); - out += sizeof(config->vendor); - memcpy(out, config->prodId, sizeof(config->prodId)); - out += sizeof(config->prodId); - memcpy(out, config->revision, sizeof(config->revision)); - out += sizeof(config->revision); - scsiDev.dataLen = out - scsiDev.data; + memcpy(&scsiDev.data[8], config->vendor, sizeof(config->vendor)); + memcpy(&scsiDev.data[16], config->prodId, sizeof(config->prodId)); + memcpy(&scsiDev.data[32], config->revision, sizeof(config->revision)); + scsiDev.dataLen = sizeof(StandardResponse) + + sizeof(config->vendor) + + sizeof(config->prodId) + + sizeof(config->revision); scsiDev.phase = DATA_IN; if (!lun) scsiDev.unitAttention = 0; @@ -153,13 +164,23 @@ void scsiInquiry() } - if (scsiDev.phase == DATA_IN && scsiDev.dataLen > allocationLength) + if (scsiDev.phase == DATA_IN) { - // Spec 8.2.5 requires us to simply truncate the response. + // "real" hard drives send back exactly allocationLenth bytes, padded + // with zeroes. This only seems to happen for Inquiry responses, and not + // other commands that also supply an allocation length such as Mode Sense or + // Request Sense. + if (scsiDev.dataLen < allocationLength) + { + memset( + &scsiDev.data[scsiDev.dataLen], + 0, + allocationLength - scsiDev.dataLen); + } + // Spec 8.2.5 requires us to simply truncate the response if it's too big. scsiDev.dataLen = allocationLength; } - // Set the first byte to indicate LUN presence. if (lun) // We only support lun 0 { diff --git a/software/SCSI2SD/SCSI2SD.cydsn/main.c b/software/SCSI2SD/SCSI2SD.cydsn/main.c index 4ae3d96..c738428 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/main.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/main.c @@ -1,4 +1,4 @@ -// Copyright (C) 2013 Michael McMaster +// Copyright (C) 2014 Michael McMaster // // This file is part of SCSI2SD. // @@ -16,18 +16,16 @@ // along with SCSI2SD. If not, see . #include "device.h" -#include "blinky.h" #include "scsi.h" #include "scsiPhy.h" #include "config.h" #include "disk.h" #include "led.h" -const char* Notice = "Copyright (C) 2013 Michael McMaster "; +const char* Notice = "Copyright (C) 2014 Michael McMaster "; int main() { - // scsi2sd_test_blink(); // Initial test. Will not return. ledOff(); // Enable global interrupts. @@ -36,19 +34,17 @@ int main() // Set interrupt handlers. scsiPhyInit(); - + configInit(); - + scsiInit(); scsiDiskInit(); - // Reading jumpers - // Is SD card detect asserted ? - - // TODO POST ? - while (1) { +#ifdef MM_DEBUG + scsiDev.watchdogTick++; +#endif scsiPoll(); scsiDiskPoll(); configPoll(); diff --git a/software/SCSI2SD/SCSI2SD.cydsn/mode.c b/software/SCSI2SD/SCSI2SD.cydsn/mode.c index 99e89b1..0f5b38c 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/mode.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/mode.c @@ -1,4 +1,5 @@ // Copyright (C) 2013 Michael McMaster +// Copyright (C) 2014 Doug Brown // // This file is part of SCSI2SD. // @@ -22,6 +23,21 @@ #include +static const uint8 ReadWriteErrorRecoveryPage[] = +{ +0x01, // Page code +0x0A, // Page length +0x00, // No error recovery options for now +0x00, // Don't try recovery algorithm during reads +0x00, // Correction span 0 +0x00, // Head offset count 0, +0x00, // Data strobe offset count 0, +0x00, // Reserved +0x00, // Don't try recovery algorithm during writes +0x00, // Reserved +0x00, 0x00 // Recovery time limit 0 (use default)*/ +}; + static const uint8 DisconnectReconnectPage[] = { 0x02, // Page code @@ -117,13 +133,6 @@ static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen) static void doModeSense( int sixByteCmd, int dbd, int pc, int pageCode, int allocLength) { - // TODO Apple HD SC Drive Setup requests Page 3 (FormatDevicePage) with an - // allocLength of 0x20. We need 0x24 if we include a block descriptor, and - // thus return CHECK CONDITION. A block descriptor is optional, so we - // chose to ignore it. - // TODO make configurable - dbd = 1; - if (pc == 0x03) // Saved Values not supported. { scsiDev.status = CHECK_CONDITION; @@ -202,6 +211,11 @@ static void doModeSense( case 0x3F: // EVERYTHING + case 0x01: + pageIn(pc, idx, ReadWriteErrorRecoveryPage, sizeof(ReadWriteErrorRecoveryPage)); + idx += sizeof(ReadWriteErrorRecoveryPage); + if (pageCode != 0x3f) break; + case 0x02: pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage)); idx += sizeof(DisconnectReconnectPage); @@ -250,7 +264,7 @@ static void doModeSense( pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage)); idx += sizeof(AppleVendorPage); break; - + default: // Unknown Page Code pageFound = 0; @@ -263,13 +277,11 @@ static void doModeSense( if (idx > allocLength) { - // Initiator may not have space to receive results. - scsiDev.status = CHECK_CONDITION; - scsiDev.sense.code = ILLEGAL_REQUEST; - scsiDev.sense.asc = INVALID_FIELD_IN_CDB; - scsiDev.phase = STATUS; + // Chop the reply off early if shorter length is requested + idx = allocLength; } - else if (pageFound) + + if (pageFound) { // Go back and fill out the mode data length if (sixByteCmd) @@ -288,7 +300,7 @@ static void doModeSense( } else { - // Initiator may not have space to receive results. + // Page not found scsiDev.status = CHECK_CONDITION; scsiDev.sense.code = ILLEGAL_REQUEST; scsiDev.sense.asc = INVALID_FIELD_IN_CDB; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c index 245bf1d..59d9688 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c @@ -1,4 +1,4 @@ -// Copyright (C) 2013 Michael McMaster +// Copyright (C) 2014 Michael McMaster // // This file is part of SCSI2SD. // @@ -95,6 +95,11 @@ static void process_Status() { scsiEnterPhase(STATUS); scsiWriteByte(scsiDev.status); + + #ifdef MM_DEBUG + scsiDev.lastStatus = scsiDev.status; + scsiDev.lastSense = scsiDev.sense.code; + #endif // Command Complete occurs AFTER a valid status has been // sent. then we go bus-free. @@ -323,6 +328,9 @@ static void doReserveRelease() static void scsiReset() { +#ifdef MM_DEBUG + scsiDev.rstCount++; +#endif ledOff(); // done in verilog SCSI_Out_DBx_Write(0); SCSI_CTL_IO_Write(0); @@ -364,7 +372,7 @@ static void enter_SelectionPhase() { // Ignore stale versions of this flag, but ensure we know the // current value if the flag is still set. - scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT); + scsiDev.atnFlag = 0; scsiDev.parityError = 0; scsiDev.dataPtr = 0; scsiDev.savedDataPtr = 0; @@ -378,15 +386,24 @@ static void enter_SelectionPhase() static void process_SelectionPhase() { + int sel = SCSI_ReadPin(SCSI_In_SEL); + int bsy = SCSI_ReadPin(SCSI_In_BSY); + + // Only read these pins AFTER SEL and BSY - we don't want to catch them + // during a transition period. uint8 mask = scsiReadDBxPins(); + int maskBitCount = countBits(mask); int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP)); - int sel = SCSI_ReadPin(SCSI_In_SEL); - int bsy = SCSI_ReadPin(SCSI_In_BSY); if (!bsy && sel && (mask & scsiDev.scsiIdMask) && - (goodParity || !config->enableParity) && (countBits(mask) == 2)) + (goodParity || !config->enableParity) && (maskBitCount <= 2)) { + // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says + // move to MESSAGE OUT if ATN is true before we release BSY. + // The initiate should assert ATN with SEL. + scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT); + // We've been selected! // Assert BSY - Selection success! // must happen within 200us (Selection abort time) of seeing our @@ -396,18 +413,29 @@ static void process_SelectionPhase() SCSI_SetPin(SCSI_Out_BSY); ledOn(); + #ifdef MM_DEBUG + scsiDev.selCount++; + #endif + // Wait until the end of the selection phase. while (!scsiDev.resetFlag) { - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); if (!SCSI_ReadPin(SCSI_In_SEL)) { break; } } + // Last chance for the ATN signal! The initiator should have set this + // previously, but we try and be a little tolerant. This is required + // for the LCIII to work. I assume ATN is being set before the + // initiator releases SEL. + scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT); + // Save our initiator now that we're no longer in a time-critical // section. + // SCSI1/SASI initiators may not set their own ID. + if (maskBitCount == 2) { int i; uint8 initiatorMask = mask ^ scsiDev.scsiIdMask; @@ -421,11 +449,12 @@ static void process_SelectionPhase() } } } + else + { + scsiDev.initiatorId = -1; + } scsiDev.phase = COMMAND; - - CyDelayUs(2); // DODGY HACK - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); } else if (!sel) { @@ -440,6 +469,9 @@ static void process_MessageOut() scsiDev.atnFlag = 0; scsiDev.parityError = 0; scsiDev.msgOut = scsiReadByte(); +#ifdef MM_DEBUG + scsiDev.msgCount++; +#endif if (scsiDev.parityError) { @@ -531,7 +563,7 @@ static void process_MessageOut() else if (scsiDev.msgOut == 0x01) { int i; - + // Extended message. int msgLen = scsiReadByte(); if (msgLen == 0) msgLen = 256; @@ -554,31 +586,9 @@ static void process_MessageOut() { messageReject(); } - - // Re-check the ATN flag. We won't get another interrupt if - // it stays asserted. - CyDelayUs(2); // DODGY HACK - scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); -} - -// TODO remove. -// This is a hack until I work out why the ATN ISR isn't -// running when it should. -static int atnErrCount = 0; -static int atnHitCount = 0; -static void checkATN() -{ - int atn = SCSI_ReadPin(SCSI_ATN_INT); - if (atn && !scsiDev.atnFlag) - { - atnErrCount++; - scsiDev.atnFlag = 1; - } - else if (atn && scsiDev.atnFlag) - { - atnHitCount++; - } + // Re-check the ATN flag in case it stays asserted. + scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); } void scsiPoll(void) @@ -595,6 +605,14 @@ void scsiPoll(void) { scsiDev.phase = BUS_BUSY; } + // The Arbitration phase is optional for SCSI1/SASI hosts if there is only + // one initiator in the chain. Support this by moving + // straight to selection if SEL is asserted. + // ie. the initiator won't assert BSY and it's own ID before moving to selection. + else if (SCSI_ReadPin(SCSI_In_SEL)) + { + enter_SelectionPhase(); + } break; case BUS_BUSY: @@ -623,7 +641,9 @@ void scsiPoll(void) break; case COMMAND: - checkATN(); + // Do not check ATN here. SCSI 1 & 2 initiators must set ATN + // and SEL together upon entering the selection phase if they + // want to send a message (IDENTIFY) immediately. if (scsiDev.atnFlag) { process_MessageOut(); @@ -635,7 +655,7 @@ void scsiPoll(void) break; case DATA_IN: - checkATN(); + scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); if (scsiDev.atnFlag) { process_MessageOut(); @@ -647,7 +667,7 @@ void scsiPoll(void) break; case DATA_OUT: - checkATN(); + scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); if (scsiDev.atnFlag) { process_MessageOut(); @@ -659,7 +679,7 @@ void scsiPoll(void) break; case STATUS: - checkATN(); + scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); if (scsiDev.atnFlag) { process_MessageOut(); @@ -671,7 +691,7 @@ void scsiPoll(void) break; case MESSAGE_IN: - checkATN(); + scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT); if (scsiDev.atnFlag) { process_MessageOut(); diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h index 68ec8bd..fe16954 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h @@ -25,6 +25,11 @@ // Fixed 512 byte sector size. // 2TB limit, based on 32bit LBA (read16/write16 not supported) +// Set this to true to log SCSI commands and status information via +// USB HID packets. The can be captured and viewed in wireshark. +// For windows users, capture using USBPcap http://desowin.org/usbpcap/ +#define MM_DEBUG 0 + #include "geometry.h" #include "sense.h" @@ -97,11 +102,20 @@ typedef struct uint8 status; ScsiSense sense; - + uint16 unitAttention; // Set to the sense qualifier key to be returned. uint8 msgIn; uint8 msgOut; + +#ifdef MM_DEBUG + uint8 selCount; + uint8 rstCount; + uint8 msgCount; + uint8 watchdogTick; + uint8 lastStatus; + uint8 lastSense; +#endif } ScsiDevice; extern ScsiDevice scsiDev; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c index d6d1a91..f67f5f8 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c @@ -27,13 +27,6 @@ CY_ISR(scsiResetISR) SCSI_RST_ClearInterrupt(); } -CY_ISR_PROTO(scsiAttentionISR); -CY_ISR(scsiAttentionISR) -{ - scsiDev.atnFlag = 1; - SCSI_ATN_ClearInterrupt(); -} - uint8 scsiReadDBxPins() { return @@ -149,10 +142,8 @@ void scsiEnterPhase(int phase) void scsiPhyInit() { SCSI_RST_ISR_StartEx(scsiResetISR); - SCSI_ATN_ISR_StartEx(scsiAttentionISR); // Interrupts may have already been directed to the (empty) // standard ISR generated by PSoC Creator. SCSI_RST_ClearInterrupt(); - SCSI_ATN_ClearInterrupt(); } diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v index 20f9cc6..e820cd3 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -133,7 +133,6 @@ reg[2:0] state; reg[7:0] data; // Set by the datapath zero detector (z1). High when A1 counts down to zero. -// D1 set to constant by .d1_init_a(4) (55ns at 66MHz) wire deskewComplete; // Parallel input to the datapath SRCA. @@ -185,8 +184,6 @@ always @(posedge op_clk) begin else state <= STATE_DESKEW; STATE_READY: - //if ((IO == IO_WRITE) & ~nACK) state <= STATE_IDLE; - //else if ((IO == IO_READ) & ~nACK) state <= STATE_RX; if (~nACK) state <= STATE_RX; else state <= STATE_READY; @@ -196,6 +193,10 @@ always @(posedge op_clk) begin endcase end +// D1 is used for the deskew count. +// The data output is valid during the DESKEW_INIT phase as well, +// so we subtract 1. +// D1 = [0.000000055 / (1 / clk)] - 1 cy_psoc3_dp #(.d1_init(3), .cy_dpconfig( { @@ -300,23 +301,3 @@ cy_psoc3_dp #(.d1_init(3), endmodule //`#start footer` -- edit after this line, do not edit this line //`#end` -- edit above this line, do not edit this line - - - - - - - - - - - - - - - - - - - -