From: Michael McMaster <michael@codesrc.com>
Date: Thu, 22 Jan 2015 01:01:59 +0000 (+1000)
Subject: SD card interface rewrite to improve compatibility with some SD cards.
X-Git-Tag: v4.01.00~1
X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=70257ca8677f4602359cfbb37a422222691b23bd;p=SCSI2SD-V6.git

SD card interface rewrite to improve compatibility with some SD cards.

- Fixed write problems with Samsung SD card controllers
- Added workaround to prevent timeouts on slow writes.
- Upgrade to PSoC Creator 3.1 and gcc 4.8.4
---

diff --git a/CHANGELOG b/CHANGELOG
index d9d299cd..d0652afc 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,11 @@
+20150201		4.1
+	- Rewrite of the SD card interface to fix compatibility problems.
+		This fixes write issues with Samsung SD cards.
+	- Workaround for SCSI hosts that set 250ms timeouts. Some NCR53C80/53C9X
+	drivers (openbsd, netbsd, and others) set a byte-to-byte timeout which
+	can be exceeded by SD card latency.
+	- Upgrade to PSoC Creator 3.1 and gcc 4.8.4.
+
 20150108		4.0
 	- Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
 	- Handle glitches of the scsi signals to improve stability and operate with
diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c
index 4b009c8b..74c554ee 100755
--- a/software/SCSI2SD/src/config.c
+++ b/software/SCSI2SD/src/config.c
@@ -17,6 +17,7 @@
 
 #include "device.h"
 #include "config.h"
+#include "debug.h"
 #include "USBFS.h"
 #include "led.h"
 
@@ -29,7 +30,7 @@
 
 #include <string.h>
 
-static const uint16_t FIRMWARE_VERSION = 0x0403;
+static const uint16_t FIRMWARE_VERSION = 0x0410;
 
 enum USB_ENDPOINTS
 {
@@ -99,12 +100,8 @@ writeFlashCommand(const uint8_t* cmd, size_t cmdSize)
 	}
 	else
 	{
-		uint8_t spcBuffer[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE];
-		CyFlash_Start();
-		CySetFlashEEBuffer(spcBuffer);
 		CySetTemp();
 		int status = CyWriteRowData(flashArray, flashRow, cmd + 1);
-		CyFlash_Stop();
 
 		uint8_t response[] =
 		{
@@ -124,6 +121,15 @@ pingCommand()
 	hidPacket_send(response, sizeof(response));
 }
 
+static void
+sdInfoCommand()
+{
+	uint8_t response[sizeof(sdDev.csd) + sizeof(sdDev.cid)];
+	memcpy(response, sdDev.csd, sizeof(sdDev.csd));
+	memcpy(response + sizeof(sdDev.csd), sdDev.cid, sizeof(sdDev.cid));
+
+	hidPacket_send(response, sizeof(response));
+}
 static void
 processCommand(const uint8_t* cmd, size_t cmdSize)
 {
@@ -145,6 +151,10 @@ processCommand(const uint8_t* cmd, size_t cmdSize)
 		Bootloadable_1_Load();
 		break;
 
+	case CONFIG_SDINFO:
+		sdInfoCommand();
+		break;
+
 	case CONFIG_NONE: // invalid
 	default:
 		break;
@@ -262,7 +272,10 @@ void debugPoll()
 		hidBuffer[24] = scsiDev.cmdCount;
 		hidBuffer[25] = scsiDev.watchdogTick;
 		hidBuffer[26] = blockDev.state;
-		
+		hidBuffer[27] = scsiDev.lastSenseASC >> 8;
+		hidBuffer[28] = scsiDev.lastSenseASC;
+
+
 		hidBuffer[58] = sdDev.capacity >> 24;
 		hidBuffer[59] = sdDev.capacity >> 16;
 		hidBuffer[60] = sdDev.capacity >> 8;
@@ -300,6 +313,16 @@ void debugInit()
 	Debug_Timer_Start();
 }
 
+void debugPause()
+{
+	Debug_Timer_Stop();
+}
+
+void debugResume()
+{
+	Debug_Timer_Start();
+}
+
 // Public method for storing MODE SELECT results.
 void configSave(int scsiId, uint16_t bytesPerSector)
 {
@@ -317,16 +340,11 @@ void configSave(int scsiId, uint16_t bytesPerSector)
 			memcpy(rowCfgData, tgt, sizeof(rowData));
 			rowCfgData->bytesPerSector = bytesPerSector;
 
-
-			uint8_t spcBuffer[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE];
-			CyFlash_Start();
-			CySetFlashEEBuffer(spcBuffer);
 			CySetTemp();
 			CyWriteRowData(
 				SCSI_CONFIG_ARRAY,
 				SCSI_CONFIG_0_ROW + (cfgIdx * SCSI_CONFIG_ROWS),
 				(uint8_t*)rowCfgData);
-			CyFlash_Stop();
 			return;
 		}
 	}
diff --git a/software/SCSI2SD/src/debug.h b/software/SCSI2SD/src/debug.h
new file mode 100755
index 00000000..cece6bcf
--- /dev/null
+++ b/software/SCSI2SD/src/debug.h
@@ -0,0 +1,25 @@
+//	Copyright (C) 2015 Michael McMaster <michael@codesrc.com>
+//
+//	This file is part of SCSI2SD.
+//
+//	SCSI2SD is free software: you can redistribute it and/or modify
+//	it under the terms of the GNU General Public License as published by
+//	the Free Software Foundation, either version 3 of the License, or
+//	(at your option) any later version.
+//
+//	SCSI2SD is distributed in the hope that it will be useful,
+//	but WITHOUT ANY WARRANTY; without even the implied warranty of
+//	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//	GNU General Public License for more details.
+//
+//	You should have received a copy of the GNU General Public License
+//	along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#ifndef Debug_H
+#define Debug_H
+
+void debugInit(void);
+void debugPause(void);
+void debugResume(void);
+
+#endif
+
diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c
index 0329e99c..003f5f39 100755
--- a/software/SCSI2SD/src/disk.c
+++ b/software/SCSI2SD/src/disk.c
@@ -20,6 +20,8 @@
 #include "scsi.h"
 #include "scsiPhy.h"
 #include "config.h"
+#include "debug.h"
+#include "debug.h"
 #include "disk.h"
 #include "sd.h"
 #include "time.h"
@@ -486,6 +488,8 @@ int scsiDiskCommand()
 
 void scsiDiskPoll()
 {
+	debugPause(); // TODO comment re. timeouts.
+
 	if (scsiDev.phase == DATA_IN &&
 		transfer.currentBlock != transfer.blocks)
 	{
@@ -565,15 +569,17 @@ void scsiDiskPoll()
 		int prep = 0;
 		int i = 0;
 		int scsiDisconnected = 0;
-		volatile uint32_t lastActivityTime = getTime_ms();
+		int scsiComplete = 0;
+		uint32_t lastActivityTime = getTime_ms();
 		int scsiActive = 0;
 		int sdActive = 0;
-		
+
 		while ((i < totalSDSectors) &&
-			(scsiDev.phase == DATA_OUT) && // scsiDisconnect keeps our phase.
+			((scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.
+				scsiComplete) &&
 			!scsiDev.resetFlag)
 		{
-			if ((sdActive == 1) && sdWriteSectorDMAPoll())
+			if ((sdActive == 1) && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))
 			{
 				sdActive = 0;
 				i++;
@@ -585,11 +591,13 @@ void scsiDiskPoll()
 				sdActive = 1;
 			}
 
+			uint32_t now = getTime_ms();
+
 			if ((scsiActive == 1) && scsiReadDMAPoll())
 			{
 				scsiActive = 0;
 				++prep;
-				lastActivityTime = getTime_ms();
+				lastActivityTime = now;
 			}
 			else if ((scsiActive == 0) &&
 				((prep - i) < buffers) &&
@@ -609,7 +617,7 @@ void scsiDiskPoll()
 				(scsiActive == 0) &&
 				!scsiDisconnected &&
 				scsiDev.discPriv &&
-				(diffTime_ms(lastActivityTime, getTime_ms()) >= 20) &&
+				(diffTime_ms(lastActivityTime, now) >= 20) &&
 				(scsiDev.phase == DATA_OUT))
 			{
 				// We're transferring over the SCSI bus faster than the SD card
@@ -628,7 +636,7 @@ void scsiDiskPoll()
 					(prep == i) || // Buffers empty.
 					// Send some messages every 100ms so we don't timeout.
 					// At a minimum, a reselection involves an IDENTIFY message.
-					(diffTime_ms(lastActivityTime, getTime_ms()) >= 100)
+					(diffTime_ms(lastActivityTime, now) >= 100)
 				))
 			{
 				int reconnected = scsiReconnect();
@@ -643,8 +651,38 @@ void scsiDiskPoll()
 					scsiDev.resetFlag = 1;
 				}
 			}
+			else if (
+				!scsiComplete &&
+				(sdActive == 1) &&
+				(prep == totalSDSectors) && // All scsi data read and buffered
+				!scsiDev.discPriv && // Prefer disconnect where possible.
+				(diffTime_ms(lastActivityTime, now) >= 150) &&
+
+				(scsiDev.phase == DATA_OUT) &&
+				!(scsiDev.cdb[scsiDev.cdbLen - 1] & 0x01) // Not linked command
+				)
+			{
+				// We're transferring over the SCSI bus faster than the SD card
+				// can write.  All data is buffered, and we're just waiting for
+				// the SD card to complete. The host won't let us disconnect.
+				// Some drivers set a 250ms timeout on transfers to complete.
+				// SD card writes are supposed to complete
+				// within 200ms, but sometimes they don'to.
+				// Just pretend we're finished.
+				scsiComplete = 1;
+
+				process_Status();
+				process_MessageIn(); // Will go to BUS_FREE state
+
+				// Try and prevent anyone else using the SCSI bus while we're not ready.
+				SCSI_SetPin(SCSI_Out_BSY); 
+			}
 		}
 
+		if (scsiComplete)
+		{
+			SCSI_ClearPin(SCSI_Out_BSY);
+		}
 		while (
 			!scsiDev.resetFlag &&
 			scsiDisconnected &&
@@ -672,6 +710,7 @@ void scsiDiskPoll()
 		}
 		scsiDiskReset();
 	}
+	debugResume(); // TODO comment re. timeouts.
 }
 
 void scsiDiskReset()
@@ -697,6 +736,8 @@ void scsiDiskReset()
 	}
 	transfer.inProgress = 0;
 	transfer.multiBlock = 0;
+		//		SD_CS_Write(1);
+
 }
 
 void scsiDiskInit()
diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c
index 2f9180be..00f9f831 100755
--- a/software/SCSI2SD/src/main.c
+++ b/software/SCSI2SD/src/main.c
@@ -25,6 +25,8 @@
 
 const char* Notice = "Copyright (C) 2014 Michael McMaster <michael@codesrc.com>";
 
+uint8_t testData[512];
+
 int main()
 {
 	timeInit();
@@ -42,10 +44,13 @@ int main()
 
 	scsiInit();
 	scsiDiskInit();
-	
+
 	uint32_t lastSDPoll = getTime_ms();
 	sdPoll();
-	
+
+
+
+
 	while (1)
 	{
 		scsiDev.watchdogTick++;
@@ -53,7 +58,7 @@ int main()
 		scsiPoll();
 		scsiDiskPoll();
 		configPoll();
-		
+
 		uint32_t now = getTime_ms();
 		if (diffTime_ms(lastSDPoll, now) > 200)
 		{
diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c
index b507bd3d..63739e0c 100755
--- a/software/SCSI2SD/src/scsi.c
+++ b/software/SCSI2SD/src/scsi.c
@@ -38,9 +38,7 @@ static void enter_SelectionPhase(void);
 static void process_SelectionPhase(void);
 static void enter_BusFree(void);
 static void enter_MessageIn(uint8 message);
-static void process_MessageIn(void);
 static void enter_Status(uint8 status);
-static void process_Status(void);
 static void enter_DataIn(int len);
 static void process_DataIn(void);
 static void process_DataOut(void);
@@ -72,7 +70,7 @@ static void enter_MessageIn(uint8 message)
 	scsiDev.phase = MESSAGE_IN;
 }
 
-static void process_MessageIn()
+void process_MessageIn()
 {
 	scsiEnterPhase(MESSAGE_IN);
 	scsiWriteByte(scsiDev.msgIn);
@@ -115,9 +113,10 @@ static void enter_Status(uint8 status)
 
 	scsiDev.lastStatus = scsiDev.status;
 	scsiDev.lastSense = scsiDev.target->sense.code;
+	scsiDev.lastSenseASC = scsiDev.target->sense.asc;
 }
 
-static void process_Status()
+void process_Status()
 {
 	scsiEnterPhase(STATUS);
 
@@ -145,6 +144,8 @@ static void process_Status()
 
 	scsiDev.lastStatus = scsiDev.status;
 	scsiDev.lastSense = scsiDev.target->sense.code;
+	scsiDev.lastSenseASC = scsiDev.target->sense.asc;
+
 
 	// Command Complete occurs AFTER a valid status has been
 	// sent. then we go bus-free.
@@ -460,8 +461,9 @@ static void scsiReset()
 	// There is no guarantee that the RST line will be negated by then.
 	// NOTE: We could be connected and powered by USB for configuration,
 	// in which case TERMPWR cannot be supplied, and reset will ALWAYS
-	// be true.
-	CyDelay(10); // 10ms.
+	// be true. Therefore, the sleep here must be slow to avoid slowing
+	// USB comms
+	CyDelay(1); // 1ms.
 }
 
 static void enter_SelectionPhase()
diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h
index 828a496c..d7e24041 100755
--- a/software/SCSI2SD/src/scsi.h
+++ b/software/SCSI2SD/src/scsi.h
@@ -103,7 +103,7 @@ typedef struct
 
 	int phase;
 
-	uint8 data[MAX_SECTOR_SIZE];
+	uint8 data[MAX_SECTOR_SIZE * 2];
 	int dataPtr; // Index into data, reset on [re]selection to savedDataPtr
 	int savedDataPtr; // Index into data, initially 0.
 	int dataLen;
@@ -134,10 +134,14 @@ typedef struct
 	uint8 watchdogTick;
 	uint8 lastStatus;
 	uint8 lastSense;
+	uint16_t lastSenseASC;
 } ScsiDevice;
 
 extern ScsiDevice scsiDev;
 
+void process_Status(void);
+void process_MessageIn(void);
+
 void scsiInit(void);
 void scsiPoll(void);
 void scsiDisconnect(void);
diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c
index f20ef306..e0649bd5 100755
--- a/software/SCSI2SD/src/sd.c
+++ b/software/SCSI2SD/src/sd.c
@@ -30,18 +30,26 @@
 // Global
 SdDevice sdDev;
 
+enum SD_IO_STATE { SD_DMA, SD_ACCEPTED, SD_BUSY, SD_IDLE };
+static int sdIOState = SD_IDLE;
+
 // Private DMA variables.
-static int dmaInProgress = 0;
 static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;
 static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;
 
 // DMA descriptors
 static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
-static uint8 sdDMATxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
+static uint8 sdDMATxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
 
 // Dummy location for DMA to send unchecked CRC bytes to
 static uint8 discardBuffer;
 
+// 2 bytes CRC, response, 8bits to close the clock..
+// "NCR" time is up to 8 bytes.
+static uint8_t writeResponseBuffer[8];
+
+static uint8_t writeStartToken = 0xFC;
+
 // Source of dummy SPI bytes for DMA
 static uint8 dummyBuffer = 0xFF;
 
@@ -77,85 +85,108 @@ static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)
 }
 
 // Read and write 1 byte.
-static uint8 sdSpiByte(uint8 value)
+static uint8_t sdSpiByte(uint8_t value)
 {
 	SDCard_WriteTxData(value);
 	while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}
 	return SDCard_ReadRxData();
 }
 
-static void sdSendCRCCommand(uint8 cmd, uint32 param)
+static uint16_t sdDoCommand(
+	uint8_t cmd,
+	uint32_t param,
+	int useCRC,
+	int use2byteResponse)
 {
-	uint8 send[6];
+	uint8_t send[7];
 
 	send[0] = cmd | 0x40;
 	send[1] = param >> 24;
 	send[2] = param >> 16;
 	send[3] = param >> 8;
 	send[4] = param;
-	send[5] = (sdCrc7(send, 5, 0) << 1) | 1;
-
-	for(cmd = 0; cmd < sizeof(send); cmd++)
+	if (useCRC)
 	{
-		sdSpiByte(send[cmd]);
+		send[5] = (sdCrc7(send, 5, 0) << 1) | 1;
 	}
-	// Allow command to process before reading result code.
-	sdSpiByte(0xFF);
-}
+	else
+	{
+		send[5] = 1; // stop bit
+	}
+	send[6] = 0xFF; // Result code or stuff byte.
 
-static void sdSendCommand(uint8 cmd, uint32 param)
-{
-	uint8 send[6];
+	CyDmaTdSetConfiguration(sdDMATxTd[0], sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);
+	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));
+	CyDmaTdSetConfiguration(sdDMARxTd[0], sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
+	CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	// The DMA controller is a bit trigger-happy. It will retain
+	// a drq request that was triggered while the channel was
+	// disabled.
+	CyDmaClearPendingDrq(sdDMATxChan);
+	CyDmaClearPendingDrq(sdDMARxChan);
 
-	send[0] = cmd | 0x40;
-	send[1] = param >> 24;
-	send[2] = param >> 16;
-	send[3] = param >> 8;
-	send[4] = param;
-	send[5] = 1; // 7:1 CRC, 0: Stop bit.
+	txDMAComplete = 0;
+	rxDMAComplete = 0;
 
-	for(cmd = 0; cmd < sizeof(send); cmd++)
+	CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);
+	CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);
+
+	// There is no flow control, so we must ensure we can read the bytes
+	// before we start transmitting
+	CyDmaChEnable(sdDMARxChan, 1);
+	CyDmaChEnable(sdDMATxChan, 1);
+
+	while (!(txDMAComplete && rxDMAComplete)) {}
+
+	uint16_t response = discardBuffer;
+	if (cmd == SD_STOP_TRANSMISSION)
 	{
-		sdSpiByte(send[cmd]);
+		// Stuff byte is required for this command only.
+		// Part 1 Simplified standard 3.01
+		// "The stop command has an execution delay due to the serial command
+		// transmission."
+		response = sdSpiByte(0xFF);
 	}
-	// Allow command to process before reading result code.
-	sdSpiByte(0xFF);
-}
 
-static uint8 sdReadResp()
-{
-	uint8 v;
-	uint8 i = 128;
-	do
+	uint32_t start = getTime_ms();
+	while ((response & 0x80) && (diffTime_ms(start, getTime_ms()) <= 200))
+	{
+		response = sdSpiByte(0xFF);
+	}
+	if (use2byteResponse)
 	{
-		v = sdSpiByte(0xFF);
-	} while(i-- && (v & 0x80));
-	return v;
+		response = (response << 8) | sdSpiByte(0xFF);
+	}
+	return response;
 }
 
-static uint8 sdCommandAndResponse(uint8 cmd, uint32 param)
+
+static uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)
 {
-	sdSpiByte(0xFF);
-	sdSendCommand(cmd, param);
-	return sdReadResp();
+	// Some Samsung cards enter a busy-state after single-sector reads.
+	// But we also need to wait for R1B to complete from the multi-sector
+	// reads.
+	while (sdSpiByte(0xFF) == 0x00) {}
+	return sdDoCommand(cmd, param, 0, 0);
 }
 
-static uint8 sdCRCCommandAndResponse(uint8 cmd, uint32 param)
+static uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)
 {
-	sdSpiByte(0xFF);
-	sdSendCRCCommand(cmd, param);
-	return sdReadResp();
+	// Some Samsung cards enter a busy-state after single-sector reads.
+	// But we also need to wait for R1B to complete from the multi-sector
+	// reads.
+	while (sdSpiByte(0xFF) == 0x00) {}
+	return sdDoCommand(cmd, param, 1, 0);
 }
 
 // Clear the sticky status bits on error.
 static void sdClearStatus()
 {
-	uint8 r2hi = sdCRCCommandAndResponse(SD_SEND_STATUS, 0);
-	uint8 r2lo = sdSpiByte(0xFF);
-	(void) r2hi; (void) r2lo;
+	sdSpiByte(0xFF);
+	uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 1, 1);
+	(void) r2;
 }
 
-
 void
 sdReadMultiSectorPrep()
 {
@@ -179,7 +210,7 @@ sdReadMultiSectorPrep()
 
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
+		scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;
 		scsiDev.phase = STATUS;
 	}
 	else
@@ -192,12 +223,16 @@ static void
 dmaReadSector(uint8_t* outputBuffer)
 {
 	// Wait for a start-block token.
-	// Don't wait more than 200ms.
-	// The standard recommends 100ms.
+	// Don't wait more than 200ms.  The standard recommends 100ms.
 	uint32_t start = getTime_ms();
-	uint8 token = sdSpiByte(0xFF);
+	uint8_t token = sdSpiByte(0xFF);
 	while (token != 0xFE && (diffTime_ms(start, getTime_ms()) <= 200))
 	{
+		if (token && ((token & 0xE0) == 0))
+		{
+			// Error token!
+			break;
+		}
 		token = sdSpiByte(0xFF);
 	}
 	if (token != 0xFE)
@@ -210,9 +245,10 @@ dmaReadSector(uint8_t* outputBuffer)
 		{
 			scsiDev.status = CHECK_CONDITION;
 			scsiDev.target->sense.code = HARDWARE_ERROR;
-			scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
+			scsiDev.target->sense.asc = 0x4400 | token;
 			scsiDev.phase = STATUS;
 		}
+		sdClearStatus();
 		return;
 	}
 
@@ -225,13 +261,7 @@ dmaReadSector(uint8_t* outputBuffer)
 	CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
 	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
-	dmaInProgress = 1;
-	// The DMA controller is a bit trigger-happy. It will retain
-	// a drq request that was triggered while the channel was
-	// disabled.
-	CyDmaClearPendingDrq(sdDMATxChan);
-	CyDmaClearPendingDrq(sdDMARxChan);
-
+	sdIOState = SD_DMA;
 	txDMAComplete = 0;
 	rxDMAComplete = 0;
 
@@ -241,6 +271,12 @@ dmaReadSector(uint8_t* outputBuffer)
 	CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);
 	CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);
 
+	// The DMA controller is a bit trigger-happy. It will retain
+	// a drq request that was triggered while the channel was
+	// disabled.
+	CyDmaClearPendingDrq(sdDMATxChan);
+	CyDmaClearPendingDrq(sdDMARxChan);
+
 	// There is no flow control, so we must ensure we can read the bytes
 	// before we start transmitting
 	CyDmaChEnable(sdDMARxChan, 1);
@@ -253,7 +289,7 @@ sdReadSectorDMAPoll()
 	if (rxDMAComplete && txDMAComplete)
 	{
 		// DMA transfer is complete
-		dmaInProgress = 0;
+		sdIOState = SD_IDLE;
 		return 1;
 	}
 	else
@@ -277,7 +313,7 @@ void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer)
 
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
+		scsiDev.target->sense.asc = LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION;
 		scsiDev.phase = STATUS;
 	}
 	else
@@ -296,14 +332,13 @@ sdReadMultiSectorDMA(uint8_t* outputBuffer)
 
 void sdCompleteRead()
 {
-	if (dmaInProgress)
+	if (sdIOState != SD_IDLE)
 	{
 		// Not much choice but to wait until we've completed the transfer.
 		// Cancelling the transfer can't be done as we have no way to reset
 		// the SD card.
 		while (!sdReadSectorDMAPoll()) { /* spin */ }
 	}
-
 	transfer.inProgress = 0;
 
 	// We cannot send even a single "padding" byte, as we normally would when
@@ -312,34 +347,19 @@ void sdCompleteRead()
 	// an error condition as we're trying to read past-the-end of the storage
 	// device.
 	// ie. do not use sdCommandAndResponse here.
-	uint8 r1b;
-	sdSendCommand(SD_STOP_TRANSMISSION, 0);
-	r1b = sdReadResp();
+	uint8 r1b = sdDoCommand(SD_STOP_TRANSMISSION, 0, 0, 0);
 
 	if (r1b)
 	{
-		// Try very hard to make sure the transmission stops
-		int retries = 255;
-		while (r1b && retries)
-		{
-			r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);
-			retries--;
-		}
-
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;
+		scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR | r1b;
 		scsiDev.phase = STATUS;
 	}
 
-	// R1b has an optional trailing "busy" signal.
-	{
-		uint8 busy;
-		do
-		{
-			busy = sdSpiByte(0xFF);
-		} while (busy == 0);
-	}
+	// R1b has an optional trailing "busy" signal, but we defer waiting on this.
+	// The next call so sdCommandAndResponse will wait for the busy state to
+	// clear.
 }
 
 static void sdWaitWriteBusy()
@@ -354,19 +374,23 @@ static void sdWaitWriteBusy()
 void
 sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 {
-	sdSpiByte(0xFC); // MULTIPLE byte start token
+	// Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte
+	// We need to do this without stopping the clock
+	CyDmaTdSetConfiguration(sdDMATxTd[0], 1, sdDMATxTd[1], TD_INC_SRC_ADR);
+	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));
 
-	// Transmit 512 bytes of data and then 2 bytes CRC.
-	CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, sdDMATxTd[1], TD_INC_SRC_ADR);
-	CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
-	CyDmaTdSetConfiguration(sdDMATxTd[1], 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
+	CyDmaTdSetConfiguration(sdDMATxTd[1], SD_SECTOR_SIZE, sdDMATxTd[2], TD_INC_SRC_ADR);
+	CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
-	CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);
-	CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	CyDmaTdSetConfiguration(sdDMATxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);
+	CyDmaTdSetAddress(sdDMATxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));
 
+	CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 3, sdDMARxTd[1], 0);
+	CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));
+	CyDmaTdSetConfiguration(sdDMARxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);
+	CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));
 	
-	dmaInProgress = 1;
+	sdIOState = SD_DMA;
 	// The DMA controller is a bit trigger-happy. It will retain
 	// a drq request that was triggered while the channel was
 	// disabled.
@@ -389,51 +413,76 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer)
 }
 
 int
-sdWriteSectorDMAPoll()
+sdWriteSectorDMAPoll(int sendStopToken)
 {
 	if (rxDMAComplete && txDMAComplete)
 	{
-		uint8_t dataToken = sdSpiByte(0xFF); // Response
-		if (dataToken == 0x0FF)
+		if (sdIOState == SD_DMA)
 		{
-			return 0; // Write has not completed.
-		}
-		else if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.
-		{
-			uint8 r1b, busy;
-		
-			sdWaitWriteBusy();
-
-			r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);
-			(void) r1b;
-			sdSpiByte(0xFF);
-
-			// R1b has an optional trailing "busy" signal.
+			// Retry a few times. The data token format is:
+			// XXX0AAA1
+			int i = 0;
+			uint8_t dataToken;
 			do
 			{
-				busy = sdSpiByte(0xFF);
-			} while (busy == 0);
+				dataToken = writeResponseBuffer[i]; // Response
+				++i;
+			} while (((dataToken & 0x0101) != 1) && (i < sizeof(writeResponseBuffer)));
+
+			// At this point we should either have an accepted token, or we'll
+			// timeout and proceed into the error case below.
+			if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.
+			{
+				sdIOState = SD_IDLE;
 
-			// Wait for the card to come out of busy.
-			sdWaitWriteBusy();
+				sdWaitWriteBusy();
+				sdSpiByte(0xFD); // STOP TOKEN
+				sdWaitWriteBusy();
 
-			transfer.inProgress = 0;
-			scsiDiskReset();
-			sdClearStatus();
+				transfer.inProgress = 0;
+				scsiDiskReset();
+				sdClearStatus();
 
-			scsiDev.status = CHECK_CONDITION;
-			scsiDev.target->sense.code = HARDWARE_ERROR;
-			scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
-			scsiDev.phase = STATUS;
+				scsiDev.status = CHECK_CONDITION;
+				scsiDev.target->sense.code = HARDWARE_ERROR;
+				scsiDev.target->sense.asc = 0x6900 | dataToken;
+				scsiDev.phase = STATUS;
+			}
+			else
+			{
+				sdIOState = SD_ACCEPTED;
+			}
 		}
-		else
+
+		if (sdIOState == SD_ACCEPTED)
 		{
-			sdWaitWriteBusy();
+			// Wait while the SD card is busy
+			if (sdSpiByte(0xFF) == 0xFF)
+			{
+				if (sendStopToken)
+				{
+					sdIOState = SD_BUSY;
+					transfer.inProgress = 0;
+
+					sdSpiByte(0xFD); // STOP TOKEN
+				}
+				else
+				{
+					sdIOState = SD_IDLE;
+				}
+			}
 		}
-		// DMA transfer is complete and the SD card has accepted the write.
-		dmaInProgress = 0;
 
-		return 1;
+		if (sdIOState == SD_BUSY)
+		{
+			// Wait while the SD card is busy
+			if (sdSpiByte(0xFF) == 0xFF)
+			{
+				sdIOState = SD_IDLE;
+			}
+		}
+
+		return sdIOState == SD_IDLE;
 	}
 	else
 	{
@@ -443,31 +492,28 @@ sdWriteSectorDMAPoll()
 
 void sdCompleteWrite()
 {
-	if (dmaInProgress)
+	if (sdIOState != SD_IDLE)
 	{
 		// Not much choice but to wait until we've completed the transfer.
 		// Cancelling the transfer can't be done as we have no way to reset
 		// the SD card.
-		while (!sdWriteSectorDMAPoll()) { /* spin */ }
+		while (!sdWriteSectorDMAPoll(1)) { /* spin */ }
 	}
-	
-	transfer.inProgress = 0;
 
-	uint8 r1, r2;
-
-	sdSpiByte(0xFD); // STOP TOKEN
-	// Wait for the card to come out of busy.
-	sdWaitWriteBusy();
+	transfer.inProgress = 0;
 
-	r1 = sdCommandAndResponse(13, 0); // send status
-	r2 = sdSpiByte(0xFF);
-	if (r1 || r2)
+	if (scsiDev.phase == DATA_OUT)
 	{
-		sdClearStatus();
-		scsiDev.status = CHECK_CONDITION;
-		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;
-		scsiDev.phase = STATUS;
+		sdSpiByte(0xFF);
+		uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);
+		if (r2)
+		{
+			sdClearStatus();
+			scsiDev.status = CHECK_CONDITION;
+			scsiDev.target->sense.code = HARDWARE_ERROR;
+			scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;
+			scsiDev.phase = STATUS;
+		}
 	}
 }
 
@@ -533,7 +579,7 @@ static int sdReadOCR()
 	uint32_t start = getTime_ms();
 	int complete;
 	uint8 status;
-	
+
 	do
 	{
 		uint8 buf[4];
@@ -557,11 +603,33 @@ static int sdReadOCR()
 	return (status == 0) && complete;
 }
 
+static void sdReadCID()
+{
+	uint8 startToken;
+	int maxWait, i;
+
+	uint8 status = sdCRCCommandAndResponse(SD_SEND_CID, 0);
+	if(status){return;}
+
+	maxWait = 1023;
+	do
+	{
+		startToken = sdSpiByte(0xFF);
+	} while(maxWait-- && (startToken != 0xFE));
+	if (startToken != 0xFE) { return; }
+
+	for (i = 0; i < 16; ++i)
+	{
+		sdDev.cid[i] = sdSpiByte(0xFF);
+	}
+	sdSpiByte(0xFF); // CRC
+	sdSpiByte(0xFF); // CRC
+}
+
 static int sdReadCSD()
 {
 	uint8 startToken;
 	int maxWait, i;
-	uint8 buf[16];
 
 	uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);
 	if(status){goto bad;}
@@ -575,29 +643,29 @@ static int sdReadCSD()
 
 	for (i = 0; i < 16; ++i)
 	{
-		buf[i] = sdSpiByte(0xFF);
+		sdDev.csd[i] = sdSpiByte(0xFF);
 	}
 	sdSpiByte(0xFF); // CRC
 	sdSpiByte(0xFF); // CRC
 
-	if ((buf[0] >> 6) == 0x00)
+	if ((sdDev.csd[0] >> 6) == 0x00)
 	{
 		// CSD version 1
 		// C_SIZE in bits [73:62]
-		uint32 c_size = (((((uint32)buf[6]) & 0x3) << 16) | (((uint32)buf[7]) << 8) | buf[8]) >> 6;
-		uint32 c_mult = (((((uint32)buf[9]) & 0x3) << 8) | ((uint32)buf[0xa])) >> 7;
-		uint32 sectorSize = buf[5] & 0x0F;
+		uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6;
+		uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7;
+		uint32 sectorSize = sdDev.csd[5] & 0x0F;
 		sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;
 	}
-	else if ((buf[0] >> 6) == 0x01)
+	else if ((sdDev.csd[0] >> 6) == 0x01)
 	{
 		// CSD version 2
 		// C_SIZE in bits [69:48]
 
 		uint32 c_size =
-			((((uint32)buf[7]) & 0x3F) << 16) |
-			(((uint32)buf[8]) << 8) |
-			((uint32)buf[7]);
+			((((uint32)sdDev.csd[7]) & 0x3F) << 16) |
+			(((uint32)sdDev.csd[8]) << 8) |
+			((uint32)sdDev.csd[7]);
 		sdDev.capacity = (c_size + 1) * 1024;
 	}
 	else
@@ -638,6 +706,7 @@ static void sdInitDMA()
 		sdDMARxTd[1] = CyDmaTdAllocate();
 		sdDMATxTd[0] = CyDmaTdAllocate();
 		sdDMATxTd[1] = CyDmaTdAllocate();
+		sdDMATxTd[2] = CyDmaTdAllocate();
 
 		SD_RX_DMA_COMPLETE_StartEx(sdRxISR);
 		SD_TX_DMA_COMPLETE_StartEx(sdTxISR);
@@ -653,6 +722,8 @@ int sdInit()
 	sdDev.version = 0;
 	sdDev.ccs = 0;
 	sdDev.capacity = 0;
+	memset(sdDev.csd, 0, sizeof(sdDev.csd));
+	memset(sdDev.cid, 0, sizeof(sdDev.cid));
 
 	sdInitDMA();
 
@@ -678,7 +749,8 @@ int sdInit()
 	SD_CS_Write(0); // Set CS active (active low)
 	CyDelayUs(1);
 
-	v = sdCRCCommandAndResponse(SD_GO_IDLE_STATE, 0);
+	sdSpiByte(0xFF);
+	v = sdDoCommand(SD_GO_IDLE_STATE, 0, 1, 0);
 	if(v != 1){goto bad;}
 
 	ledOn();
@@ -713,6 +785,7 @@ int sdInit()
 	SDCard_ClearFIFO();
 
 	if (!sdReadCSD()) goto bad;
+	sdReadCID();
 
 	result = 1;
 	goto out;
@@ -730,7 +803,7 @@ out:
 void sdWriteMultiSectorPrep()
 {
 	uint8 v;
-	
+
 	// Set the number of blocks to pre-erase by the multiple block write command
 	// We don't care about the response - if the command is not accepted, writes
 	// will just be a bit slower.
@@ -752,14 +825,14 @@ void sdWriteMultiSectorPrep()
 	{
 		sdLBA = sdLBA * SD_SECTOR_SIZE;
 	}
-	v = sdCommandAndResponse(25, sdLBA);
+	v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);
 	if (v)
 	{
 		scsiDiskReset();
 		sdClearStatus();
 		scsiDev.status = CHECK_CONDITION;
 		scsiDev.target->sense.code = HARDWARE_ERROR;
-		scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;
+		scsiDev.target->sense.asc = 0x8800 | v;
 		scsiDev.phase = STATUS;
 	}
 	else
@@ -772,7 +845,7 @@ void sdPoll()
 {
 	// Check if there's an SD card present.
 	if ((scsiDev.phase == BUS_FREE) &&
-		!dmaInProgress)
+		(sdIOState == SD_IDLE))
 	{
 		// The CS line is pulled high by the SD card.
 		// De-assert the line, and check if it's high.
diff --git a/software/SCSI2SD/src/sd.h b/software/SCSI2SD/src/sd.h
index 7fec4819..abb45078 100755
--- a/software/SCSI2SD/src/sd.h
+++ b/software/SCSI2SD/src/sd.h
@@ -25,12 +25,14 @@ typedef enum
 	SD_SEND_OP_COND = 1,
 	SD_SEND_IF_COND = 8, // SD V2
 	SD_SEND_CSD = 9,
+	SD_SEND_CID = 10,
 	SD_STOP_TRANSMISSION = 12,
 	SD_SEND_STATUS = 13,
 	SD_SET_BLOCKLEN = 16,
 	SD_READ_SINGLE_BLOCK = 17,
 	SD_READ_MULTIPLE_BLOCK = 18,
 	SD_APP_SET_WR_BLK_ERASE_COUNT = 23,
+	SD_WRITE_MULTIPLE_BLOCK = 25,
 	SD_APP_SEND_OP_COND = 41,
 	SD_APP_CMD = 55,
 	SD_READ_OCR = 58,
@@ -53,6 +55,9 @@ typedef struct
 	int version; // SDHC = version 2.
 	int ccs; // Card Capacity Status. 1 = SDHC or SDXC
 	uint32 capacity; // in 512 byte blocks
+
+	uint8_t csd[16]; // Unparsed CSD
+	uint8_t cid[16]; // Unparsed CID
 } SdDevice;
 
 extern SdDevice sdDev;
@@ -61,7 +66,7 @@ int sdInit(void);
 
 void sdWriteMultiSectorPrep(void);
 void sdWriteMultiSectorDMA(uint8_t* outputBuffer);
-int sdWriteSectorDMAPoll();
+int sdWriteSectorDMAPoll(int sendStopToken);
 void sdCompleteWrite(void);
 
 void sdReadMultiSectorPrep(void);
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
old mode 100755
new mode 100644
index 529413cc..6c7c3fd4
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
@@ -1,13 +1,13 @@
 /*******************************************************************************
 * File Name: Bootloadable_1.c
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloadable application. The API includes a
-*   single function for starting bootloader.
+*   single function for starting the bootloader.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,7 +20,7 @@
 * Function Name: Bootloadable_1_Load
 ********************************************************************************
 * Summary:
-*  Begins the bootloading algorithm, downloading a new ACD image from the host.
+*  Begins the bootloading algorithm downloading a new ACD image from the host.
 *
 * Parameters:
 *  None
@@ -40,28 +40,23 @@ void Bootloadable_1_Load(void)
 
 
 /*******************************************************************************
-* Function Name: Bootloadable_1_SetFlashByte
-********************************************************************************
-* Summary:
-*  Sets byte at specified address in Flash.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
+* The following code is OBSOLETE and must not be used.
 *******************************************************************************/
 void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) 
 {
     uint32 flsAddr = address - CYDEV_FLASH_BASE;
-    uint8 rowData[CYDEV_FLS_ROW_SIZE];
+    uint8  rowData[CYDEV_FLS_ROW_SIZE];
 
     #if !(CY_PSOC4)
-        uint8 arrayId = (uint8)(flsAddr / CYDEV_FLS_SECTOR_SIZE);
+        uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
     #endif  /* !(CY_PSOC4) */
 
-    uint16 rowNum = (uint16)((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
     uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
     uint16 idx;
 
@@ -72,12 +67,21 @@ void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType)
     }
     rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
 
-
     #if(CY_PSOC4)
-        (void) CySysFlashWriteRow((uint32)rowNum, rowData);
+        (void) CySysFlashWriteRow((uint32) rowNum, rowData);
     #else
         (void) CyWriteRowData(arrayId, rowNum, rowData);
     #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing Flash, data in the instruction cache can become stale.
+        * Therefore, the cache data does not correlate to the data just written to
+        * Flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from Flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
 }
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
old mode 100755
new mode 100644
index d760f96e..20358afb
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
@@ -1,13 +1,13 @@
 /*******************************************************************************
 * File Name: Bootloadable_1.h
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloadable application. The API includes a
 *   single function for starting bootloader.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -24,7 +24,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component Bootloadable_v1_20 requires cy_boot v3.0 or later
+    #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later
 #endif /* !defined (CY_PSOC5LP) */
 
 
@@ -89,13 +89,13 @@ extern void Bootloadable_1_Load(void) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.10
+* The following code is OBSOLETE and must not be used starting from version 1.10
 *******************************************************************************/
 #define CYBTDLR_SET_RUN_TYPE(x)     Bootloadable_1_SET_RUN_TYPE(x)
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.20
+* The following code is OBSOLETE and must not be used starting from version 1.20
 *******************************************************************************/
 #define Bootloadable_1_START_APP                      (0x80u)
 #define Bootloadable_1_START_BTLDR                    (0x40u)
@@ -136,12 +136,26 @@ extern void Bootloadable_1_Load(void) ;
 #define Bootloadable_1_SetFlashRunType(runType)           \
                         Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
 
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
 
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
 #if(CY_PSOC4)
-    #define Bootloadable_1_SOFTWARE_RESET         CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u)
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
 #else
-    #define Bootloadable_1_SOFTWARE_RESET         CY_SET_REG8(CYREG_RESET_CR2, 0x01u)
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
 #endif  /* (CY_PSOC4) */
 
 #if(CY_PSOC4)
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
old mode 100755
new mode 100644
index 124d8370..239de620
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
@@ -9,7 +9,7 @@ define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
 define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
 define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;
 /*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
 define symbol __ICFEDIT_size_heap__   = 0x0400;
 /**** End of ICF editor section. ###ICF###*/
 
@@ -40,7 +40,10 @@ define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   {
 define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
 define block HSTACK      {block HEAP, last block CSTACK};
 
+if (CY_APPL_LOADABLE)
+{
 define block LOADER     { readonly section .cybootloader };
+}
 define block APPL       with fixed order {readonly section .romvectors, readonly};
 
 /* The address of Flash row next after Bootloader image */
@@ -83,7 +86,11 @@ do not initialize  { section .noinit };
 do not initialize  { readwrite section .ramvectors };
 
 /******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
 ".cybootloader"    : place at start of ROM_region {block LOADER};
+}
+
 "APPL"             : place at start of APPL_region {block APPL};
 
 "RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
@@ -101,7 +108,10 @@ keep {  section .cybootloader,
         section .cymeta };
 
 ".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
 ".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
 ".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
 ".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
 ".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
old mode 100755
new mode 100644
index c44d04e6..0c25bb27
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
@@ -4,7 +4,7 @@
 
 ;********************************************************************************
 ;* File Name: Cm3RealView.scat
-;* Version 4.0
+;* Version 4.20
 ;*
 ;*  Description:
 ;*  This Linker Descriptor file describes the memory layout of the PSoC5
@@ -14,7 +14,7 @@
 ;*
 ;*  Note:
 ;*
-;*  romvectors: Cypress default Interrupt sevice routine vector table.
+;*  romvectors: Cypress default Interrupt service routine vector table.
 ;*
 ;*      This is the ISR vector table at bootup. Used only for the reset vector.
 ;*
@@ -25,7 +25,7 @@
 ;*
 ;*
 ;********************************************************************************
-;* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+;* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ;* You may use this file only in accordance with the license, terms, conditions,
 ;* disclaimers, and limitations in the end user license agreement accompanying
 ;* the software package with which this file was provided.
@@ -112,11 +112,11 @@ APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
         .ANY (+RW, +ZI)
     }
 
-    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x2000) EMPTY 0x0400
+    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
     {
     }
 
-    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000
+    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
     {
     }
 }
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
old mode 100755
new mode 100644
index f4d6607e..dd1cc0bc
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: Cm3Start.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  Startup code for the ARM CM3.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -52,6 +52,12 @@ CY_ISR(IntDefaultHandler);
     extern void __iar_data_init3 (void);
 #endif  /* (__ARMCC_VERSION) */
 
+#if defined(__GNUC__)
+    #include <errno.h>
+    extern int  errno;
+    extern int  end;
+#endif  /* defined(__GNUC__) */
+
 /* Global variables */
 #if !defined (__ICCARM__)
     CY_NOINIT static uint32 cySysNoInitDataValid;
@@ -76,7 +82,7 @@ cyisraddress CyRamVectors[CY_NUM_VECTORS];
 ********************************************************************************
 *
 * Summary:
-*  This function is called for all interrupts, other than reset, that get
+*  This function is called for all interrupts, other than a reset that gets
 *  called before the system is setup.
 *
 * Parameters:
@@ -95,7 +101,7 @@ CY_ISR(IntDefaultHandler)
     while(1)
     {
         /***********************************************************************
-        * We should never get here. If we do, a serious problem occured, so go
+        * We must not get here. If we do, a serious problem occurs, so go
         * into an infinite loop.
         ***********************************************************************/
     }
@@ -104,7 +110,7 @@ CY_ISR(IntDefaultHandler)
 
 #if defined(__ARMCC_VERSION)
 
-/* Local function for the device reset. */
+/* Local function for device reset. */
 extern void Reset(void);
 
 /* Application entry point. */
@@ -161,7 +167,7 @@ void Reset(void)
 ********************************************************************************
 *
 * Summary:
-*  This function is called imediatly before the users main
+*  This function is called immediately before the users main
 *
 * Parameters:
 *  None
@@ -179,7 +185,7 @@ void $Sub$$main(void)
 
     while (1)
     {
-        /* If main returns it is undefined what we should do. */
+        /* If main returns, it is undefined what we should do. */
     }
 }
 
@@ -193,7 +199,7 @@ extern void __cy_stack(void);
 /* Application entry point. */
 extern int main(void);
 
-/* The static objects constructors initializer */
+/* Static objects constructors initializer */
 extern void __libc_init_array(void);
 
 typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
@@ -211,6 +217,84 @@ extern const char __cy_region_num __attribute__((weak));
 #define __cy_region_num ((size_t)&__cy_region_num)
 
 
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+*  Exit a program without cleaning up files. If your system doesn't provide
+*  this, it is best to avoid linking with subroutines that require it (exit,
+*  system).
+*
+* Parameters:
+*  status: Status caused program exit.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+    /* Cause divide by 0 exception */
+    int x = status / (int) INT_MAX;
+    x = 4 / x;
+
+    while(1)
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+*  Increase program data space. As malloc and related functions depend on this,
+*  it is useful to have a working implementation. The following suffices for a
+*  standalone system; it exploits the symbol end automatically defined by the
+*  GNU linker.
+*
+* Parameters:
+*  nbytes: The number of bytes requested (if the parameter value is positive)
+*  from the heap or returned back to the heap (if the parameter value is
+*  negative).
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
+    void *      returnValue;
+
+    /* The statically held previous end of the heap, with its initialization. */
+    static void *heapPointer = (void *) &end;                 /* Previous end */
+
+    if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+    {
+        returnValue  = heapPointer;
+        heapPointer += nbytes;
+    }
+    else
+    {
+        errno = ENOMEM;
+        returnValue = (void *) -1;
+    }
+
+    return (returnValue);
+}
+
+
 /*******************************************************************************
 * Function Name: Reset
 ********************************************************************************
@@ -249,17 +333,6 @@ void Reset(void)
     Start_c();
 }
 
-__attribute__((weak))
-void _exit(int status)
-{
-    /* Cause a divide by 0 exception */
-    int x = status / INT_MAX;
-    x = 4 / x;
-
-    while(1)
-    {
-    }
-}
 
 /*******************************************************************************
 * Function Name: Start_c
@@ -267,7 +340,7 @@ void _exit(int status)
 *
 * Summary:
 *  This function handles initializing the .data and .bss sections in
-*  preperation for running standard C code.  Once initialization is complete
+*  preparation for running the standard C code.  Once initialization is complete
 *  it will call main(). This function will never return.
 *
 * Parameters:
@@ -284,7 +357,7 @@ void Start_c(void)
     const struct __cy_region *rptr = __cy_regions;
 
     /* Initialize memory */
-    for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+    for (regions = __cy_region_num; regions != 0u; regions--)
     {
         uint32 *src = (uint32 *)rptr->init;
         uint32 *dst = (uint32 *)rptr->data;
@@ -293,13 +366,18 @@ void Start_c(void)
 
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = *src++;
+            *dst = *src;
+            dst++;
+            src++;
         }
         limit = rptr->zero_size;
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = 0u;
+            *dst = 0u;
+            dst++;
         }
+
+        rptr++;
     }
 
     /* Invoke static objects constructors */
@@ -320,8 +398,8 @@ void Start_c(void)
 ********************************************************************************
 *
 * Summary:
-*  This function perform early initializations for the IAR Embedded
-*  Workbench IDE. It is executed in the context of reset interrupt handler
+*  This function performs early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of a reset interrupt handler
 *  before the data sections are initialized.
 *
 * Parameters:
@@ -383,14 +461,14 @@ int __low_level_init(void)
     const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
 #endif  /* defined (__ICCARM__) */
 {
-    INITIAL_STACK_POINTER,   /* The initial stack pointer  0 */
-    #if defined (__ICCARM__) /* The reset handler          1 */
+    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
+    #if defined (__ICCARM__) /* Reset handler          1 */
         __iar_program_start,
     #else
         (cyisraddress)&Reset,
     #endif  /* defined (__ICCARM__) */
-    &IntDefaultHandler,      /* The NMI handler            2 */
-    &IntDefaultHandler,      /* The hard fault handler     3 */
+    &IntDefaultHandler,      /* NMI handler            2 */
+    &IntDefaultHandler,      /* Hard fault handler     3 */
 };
 
 #if defined(__ARMCC_VERSION)
@@ -438,7 +516,7 @@ void initialize_psoc(void)
     /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
     CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
 
-    /* Point NVIC at the RAM vector table. */
+    /* Point NVIC at RAM vector table. */
     *CYINT_VECT_TABLE = CyRamVectors;
 
     /* Initialize the configuration registers. */
@@ -446,7 +524,7 @@ void initialize_psoc(void)
 
     #if(0u != DMA_CHANNELS_USED__MASK0)
 
-        /* Setup DMA - only necessary if the design contains a DMA component. */
+        /* Setup DMA - only necessary if design contains DMA component. */
         CyDmacConfigure();
 
     #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
old mode 100755
new mode 100644
index a8797f7e..e8c87a4a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: CyBootAsmGnu.s
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Assembly routines for GNU as.
 *
 ********************************************************************************
-* Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
old mode 100755
new mode 100644
index 166ba871..330202c8
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmIar.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for IAR Embedded Workbench IDE.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2013-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -30,7 +30,7 @@
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic. Therefore, to avoid corrupting processor state, it must be the policy 
+;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
 ;  that all interrupt routines restore the interrupt enable bits as they were 
 ;  found on entry.
 ;
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
old mode 100755
new mode 100644
index 6c40635e..8b1cc20a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmRv.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for RealView.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -110,7 +110,7 @@ byte_4 DCB 0x09
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
 ;  corrupting processor state, it must be the policy that all interrupt routines
 ;  restore the interrupt enable bits as they were found on entry.
 ;
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
old mode 100755
new mode 100644
index f4983c39..2a1ef96a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the DMAC component. The API includes functions for the
@@ -18,10 +18,10 @@
 *  not being used.
 *
 *  This code uses the first byte of each TD to manage the free list of TD's.
-*  The user can over write this once the TD is allocated.
+*  The user can overwrite this once the TD is allocated.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,8 +37,8 @@
 * are initialized. To avoid zeroing, these variables should be initialized
 * properly during segments initialization as well.
 *******************************************************************************/
-static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements in the list */
-static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
 static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
 
 
@@ -48,7 +48,7 @@ static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map
 *
 * Summary:
 *  Creates a linked list of all the TDs to be allocated. This function is called
-*  by the startup code; you do not normally need to call it. You could call this
+*  by the startup code; you do not normally need to call it. You can call this
 *  function if all of the DMA channels are inactive.
 *
 * Parameters:
@@ -72,7 +72,7 @@ void CyDmacConfigure(void)
         CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
     }
 
-    /* Make the last one point to zero. */
+    /* Make last one point to zero. */
     CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
 }
 
@@ -102,8 +102,8 @@ void CyDmacConfigure(void)
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 uint8 CyDmacError(void) 
@@ -131,15 +131,15 @@ uint8 CyDmacError(void)
 *   Set to 1 when an access is attempted to an invalid address.
 *
 *  DMAC_BUS_TIMEOUT:
-*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Return:
 *  None
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 void CyDmacClearError(uint8 error) 
@@ -153,7 +153,7 @@ void CyDmacClearError(uint8 error)
 ********************************************************************************
 *
 * Summary:
-*  When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the
+*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
 *  address of the error is written to the error address register and can be read
 *  with this function.
 *
@@ -198,12 +198,12 @@ uint8 CyDmaChAlloc(void)
     /* Enter critical section! */
     interruptState = CyEnterCriticalSection();
 
-    /* Look for a free channel. */
+    /* Look for free channel. */
     for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
     {
         if(0uL == (CyDmaChannels & channel))
         {
-            /* Mark the channel as used. */
+            /* Mark channel as used. */
             CyDmaChannels |= channel;
             break;
         }
@@ -249,7 +249,7 @@ cystatus CyDmaChFree(uint8 chHandle)
         /* Enter critical section */
         interruptState = CyEnterCriticalSection();
 
-        /* Clear the bit mask that keeps track of ownership. */
+        /* Clear bit mask that keeps track of ownership. */
         CyDmaChannels &= ~(((uint32) 1u) << chHandle);
 
         /* Exit critical section */
@@ -277,10 +277,10 @@ cystatus CyDmaChFree(uint8 chHandle)
 *   Preserves the original TD state when the TD has completed. This parameter
 *   applies to all TDs in the channel.
 *
-*   0 - When a TD is completed, the DMAC leaves the TD configuration values in
+*   0 - When TD is completed, the DMAC leaves the TD configuration values in
 *   their current state, and does not restore them to their original state.
 *
-*   1 - When a TD is completed, the DMAC restores the original configuration
+*   1 - When TD is completed, the DMAC restores the original configuration
 *   values of the TD.
 *
 *  When preserveTds is set, the TD slot that equals the channel number becomes
@@ -309,14 +309,14 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds)
     {
         if (0u != preserveTds)
         {
-            /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
-            *  preserve the original TD chain
+            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve original TD chain
             */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
         }
         else
         {
-            /* Store the intermediate and final TD states on top of the original TD chain */
+            /* Store intermediate and final TD states on top of original TD chain */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
         }
 
@@ -365,7 +365,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
         /* Disable channel */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
 
-        /* Store the intermediate and final TD states on top of the original TD chain */
+        /* Store intermediate and final TD states on top of original TD chain */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
         status = CYRET_SUCCESS;
     }
@@ -379,7 +379,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
 ********************************************************************************
 *
 * Summary:
-*  Clears pending DMA data request.
+*  Clears pending the DMA data request.
 *
 * Parameters:
 *  uint8 chHandle:
@@ -518,7 +518,7 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
 *   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
 *
 *  uint8 startTd:
-*   The index of TD to set as the first TD associated with the channel. Zero is
+*   Set the TD index as the first TD associated with the channel. Zero is
 *   a valid TD index.
 *
 * Return:
@@ -759,13 +759,13 @@ uint8 CyDmaTdAllocate(void)
 
     if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
     {
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         element = CyDmaTdFreeIndex;
 
         /* Decrement the count. */
         CyDmaTdCurrentNumber--;
 
-        /* Update the next available pointer. */
+        /* Update next available pointer. */
         CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
     }
 
@@ -798,7 +798,7 @@ void CyDmaTdFree(uint8 tdHandle)
         /* Enter critical section! */
         uint8 interruptState = CyEnterCriticalSection();
 
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
 
         /* Set new Next Available. */
@@ -942,9 +942,9 @@ cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nex
 *  CYRET_BAD_PARAM if tdHandle is invalid.
 *
 * Side Effects:
-*  If a TD has a transfer count of N and is executed, the transfer count becomes
+*  If TD has a transfer count of N and is executed, the transfer count becomes
 *  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-*  request for indefinite transfer. Be careful when requesting a TD with a
+*  request for indefinite transfer. Be careful when requesting TD with a
 *  transfer count of zero.
 *
 *******************************************************************************/
@@ -955,25 +955,25 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 *
 
     if(tdHandle < CY_DMA_NUMBEROF_TDS)
     {
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != transferCount)
         {
-            /* Get the 12 bits of the transfer count */
+            /* Get 12 bits of transfer count */
             reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
             *transferCount = 0x0FFFu & CY_GET_REG16(convert);
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != nextTd)
         {
-            /* Get the Next TD pointer */
+            /* Get Next TD pointer */
             *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != configuration)
         {
-            /* Get the configuration the TD */
+            /* Get configuration TD */
             *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
         }
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
old mode 100755
new mode 100644
index 6a3ee851..8bbb4a7d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the DMA Controller.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -116,7 +116,7 @@ typedef struct dmac_tdmem2_struct
 
 #define CY_DMA_TD_SIZE              0x08u
 
-/* The "u" was removed as workaround for Keil compiler bug */
+/* "u" was removed as workaround for Keil compiler bug */
 #define CY_DMA_TD_SWAP_EN           0x80
 #define CY_DMA_TD_SWAP_SIZE4        0x40
 #define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
@@ -178,7 +178,18 @@ typedef struct dmac_tdmem2_struct
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
 #define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
old mode 100755
new mode 100644
index e692e661..38ffe998
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the FLASH/EEPROM.
@@ -13,7 +13,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,9 +21,12 @@
 
 #include "CyFlash.h"
 
+/*  The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
+
 
 /*******************************************************************************
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
 * The first byte is the sign of the temperature (0 = negative, 1 = positive).
 * The second byte is the magnitude.
 *******************************************************************************/
@@ -35,6 +38,7 @@ uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 
 
 static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
 
 
 /*******************************************************************************
@@ -53,13 +57,48 @@ static cystatus CySetTempInt(void);
 *******************************************************************************/
 void CyFlash_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or eeprom to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable flash. Active flash macros consume current, but re-enabling a
+    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+    * macro during that time, it will be stalled. This bit allows the flash to
+    * be enabled even if the CPU is disabled, which allows a quicker return to
+    * code execution.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
 
-    CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -83,11 +122,14 @@ void CyFlash_Start(void)
 *******************************************************************************/
 void CyFlash_Stop(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -97,7 +139,7 @@ void CyFlash_Stop(void)
 *
 * Summary:
 *  Sends a command to the SPC to read the die temperature. Sets a global value
-*  used by the Write functions. This function must be called once before
+*  used by the Write function. This function must be called once before
 *  executing a series of Flash writing functions.
 *
 * Parameters:
@@ -153,13 +195,65 @@ static cystatus CySetTempInt(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        status = CySpcGetAlgorithm();
+
+        if(CYRET_STARTED == status)
+        {
+            while(CY_SPC_BUSY)
+            {
+                /* Spin until idle. */
+                CyDelayUs(1u);
+            }
+
+            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySetTemp
 ********************************************************************************
 *
 * Summary:
-*  This is a wraparound for CySetTempInt(). It is used to return second
-*  successful read of temperature value.
+*  This is a wraparound for CySetTempInt(). It is used to return the second
+*  successful read of the temperature value.
 *
 * Parameters:
 *  None
@@ -171,14 +265,14 @@ static cystatus CySetTempInt(void)
 *   CYRET_UNKNOWN if there was an SPC error.
 *
 *  uint8 dieTemperature[2]:
-*   Holds die temperature for the flash writting algorithm. The first byte is
+*   Holds the die temperature for the flash writing algorithm. The first byte is
 *   the sign of the temperature (0 = negative, 1 = positive). The second byte is
 *   the magnitude.
 *
 *******************************************************************************/
 cystatus CySetTemp(void) 
 {
-    cystatus status = CySetTempInt();
+    cystatus status = CyFlashGetSpcAlgorithm();
 
     if(status == CYRET_SUCCESS)
     {
@@ -195,12 +289,12 @@ cystatus CySetTemp(void)
 *
 * Summary:
 *  Sets the user supplied temporary buffer to store SPC data while performing
-*  flash and EEPROM commands. This buffer is only necessary when Flash ECC is
+*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
 *  disabled.
 *
 * Parameters:
 *  buffer:
-*   Address of block of memory to store temporary memory. The size of the block
+*   The address of a block of memory to store temporary memory. The size of the block
 *   of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
 *
 * Return:
@@ -219,10 +313,12 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
         if(NULL == buffer)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_BAD_PARAM;
         }
         else if(CySpcLock() != CYRET_SUCCESS)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_LOCKED;
         }
         else
@@ -233,7 +329,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
     #else
 
-        /* To supress the warning */
+        /* To suppress warning */
         buffer = buffer;
 
     #endif  /* (CYDEV_ECC_ENABLE == 0u) */
@@ -242,120 +338,48 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 }
 
 
-#if(CYDEV_ECC_ENABLE == 1)
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sends a command to the SPC to load and program a row of data in
-    *  Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID:    ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress: rowAddress of flash row to program.
-    *  rowData:    Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint16 rowSize;
-        cystatus status;
-
-        rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
-        status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
-        return(status);
-    }
-
-#else
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *   Sends a command to the SPC to load and program a row of data in
-    *   Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID      : ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress   : rowAddress of flash row to program.
-    *  rowData      : Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint8 i;
-        uint32 offset;
-        uint16 rowSize;
-        cystatus status;
-
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
-            {
-                rowSize = CYDEV_EEPROM_ROW_SIZE;
-            }
-            else
-            {
-                rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
-
-                /* Save the ECC area. */
-                offset = CYDEV_ECC_BASE +
-                        ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
-                        ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
-
-                for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
-                {
-                    *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-                }
-            }
-
-            /* Copy the rowdata to the temporary buffer. */
-        #if(CY_PSOC3)
-            (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
-        #else
-            (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
-        #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to load and program a row of data in
+*  Flash or EEPROM.
+*
+* Parameters:
+*  arrayID:    ID of the array to write.
+*   The type of write, Flash or EEPROM, is determined from the array ID.
+*   The arrays in the part are sequential starting at the first ID for the
+*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+*  rowAddress: rowAddress of flash row to program.
+*  rowData:    Array of bytes to write.
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED if the SPC is already in use.
+*   CYRET_CANCELED if command not accepted
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
+{
+    uint16 rowSize;
+    cystatus status;
 
-        return(status);
-    }
+    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
 
-#endif /* (CYDEV_ECC_ENABLE == 0u) */
+    return(status);
+}
 
 
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
 #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
 
     /*******************************************************************************
@@ -363,7 +387,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a command to the SPC to load and program a row of config data in flash.
+    *  Sends a command to the SPC to load and program a row of config data in the Flash.
     *  This function is only valid for Flash array IDs (not for EEPROM).
     *
     * Parameters:
@@ -371,8 +395,8 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     *   The arrays in the part are sequential starting at the first ID for the
     *   specific memory type. The array ID for the Flash memory lasts
     *   from 0x00 to 0x3F.
-    *  rowAddress:   Address of the sector to erase.
-    *  rowECC:       Array of bytes to write.
+    *  rowAddress:   The address of the sector to erase.
+    *  rowECC:       The array of bytes to write.
     *
     * Return:
     *  status:
@@ -385,42 +409,9 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
     
     {
-        uint32 offset;
-        uint16 i;
         cystatus status;
 
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            /* Read the existing flash data. */
-            offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
-                     ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
-
-            #if (CYDEV_FLS_BASE != 0u)
-                offset += CYDEV_FLS_BASE;
-            #endif  /* (CYDEV_FLS_BASE != 0u) */
-
-            for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
-            {
-                rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-            }
-
-            #if(CY_PSOC3)
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (void *)(uint32)rowECC,
-                              (int16)CYDEV_ECC_ROW_SIZE);
-            #else
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (const void *)rowECC,
-                              CYDEV_ECC_ROW_SIZE);
-            #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
 
         return (status);
     }
@@ -433,7 +424,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 * Function Name: CyWriteRowFull
 ********************************************************************************
 * Summary:
-*  Sends a command to the SPC to load and program a row of data in flash.
+*  Sends a command to the SPC to load and program a row of data in the Flash.
 *  rowData array is expected to contain Flash and ECC data if needed.
 *
 * Parameters:
@@ -452,63 +443,107 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
         
 {
-    cystatus status;
+    cystatus status = CYRET_SUCCESS;
 
-    if(CySpcLock() == CYRET_SUCCESS)
+    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
     {
-        /* Load row data into SPC internal latch */
-        status = CySpcLoadRow(arrayId, rowData, rowSize);
+        status = CYRET_BAD_PARAM;
+    }
 
-        if(CYRET_STARTED == status)
+    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
+    {
+        /* Flash */
+        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
         {
-            while(CY_SPC_BUSY)
-            {
-                /* Wait for SPC to finish and get SPC status */
-                CyDelayUs(1u);
-            }
+            status = CYRET_BAD_PARAM;
+        }
+    }
+    else
+    {
+        /* EEPROM */
+        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
 
-            /* Hide SPC status */
-            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-            {
-                status = CYRET_SUCCESS;
-            }
-            else
-            {
-                status = CYRET_UNKNOWN;
-            }
+        if(CY_EEPROM_SIZEOF_ROW != rowSize)
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
 
-            if(CYRET_SUCCESS == status)
+    if(rowData == NULL)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    if(status == CYRET_SUCCESS)
+    {
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Load row data into SPC internal latch */
+            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+            if(CYRET_STARTED == status)
             {
-                /* Erase and program flash with the data from SPC interval latch */
-                status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait for SPC to finish and get SPC status */
+                    CyDelayUs(1u);
+                }
 
-                if(CYRET_STARTED == status)
+                /* Hide SPC status */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
                 {
-                    while(CY_SPC_BUSY)
-                    {
-                        /* Wait for SPC to finish and get SPC status */
-                        CyDelayUs(1u);
-                    }
+                    status = CYRET_SUCCESS;
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
 
-                    /* Hide SPC status */
-                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                    {
-                        status = CYRET_SUCCESS;
-                    }
-                    else
+                if(CYRET_SUCCESS == status)
+                {
+                    /* Erase and program flash with data from SPC interval latch */
+                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+                    if(CYRET_STARTED == status)
                     {
-                        status = CYRET_UNKNOWN;
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait for SPC to finish and get SPC status */
+                            CyDelayUs(1u);
+                        }
+
+                        /* Hide SPC status */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                        else
+                        {
+                            status = CYRET_UNKNOWN;
+                        }
                     }
                 }
             }
-
+            CySpcUnlock();
+        }   /* if(CySpcLock() == CYRET_SUCCESS) */
+        else
+        {
+            status = CYRET_LOCKED;
         }
-
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_LOCKED;
     }
 
     return(status);
@@ -521,9 +556,9 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, u
 *
 * Summary:
 *  Sets the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash. This function must be called before increasing CPU
-*  clock frequency. It can optionally be called after lowering CPU clock
-*  frequency in order to improve CPU performance.
+*  coming back from the Flash. This function must be called before increasing the CPU
+*  clock frequency. It can optionally be called after lowering the CPU clock
+*  frequency in order to improve the CPU performance.
 *
 * Parameters:
 *  uint8 freq:
@@ -542,55 +577,42 @@ void CyFlash_SetWaitCycles(uint8 freq)
 
     /***************************************************************************
     * The number of clock cycles the cache will wait before it samples data
-    * coming back from Flash must be equal or greater to to the CPU frequency
+    * coming back from the Flash must be equal or greater to to the CPU frequency
     * outlined in clock cycles.
     ***************************************************************************/
 
-    #if (CY_PSOC3)
-
-        if (freq <= 22u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 44u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC3) */
-
-
-    #if (CY_PSOC5)
-
-        if (freq <= 16u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 33u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 50u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC5) */
+    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
+    }
+#if (CY_PSOC5)
+    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
+    }
+    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
+    }
+#endif  /* (CY_PSOC5) */
+    else
+    {
+        /* Halt CPU in debug mode if frequency is invalid */
+        CYASSERT(0u != 0u);
+    }
 
     /* Restore global interrupt enable state */
     CyExitCriticalSection(interruptState);
@@ -613,11 +635,45 @@ void CyFlash_SetWaitCycles(uint8 freq)
 *******************************************************************************/
 void CyEEPROM_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or EEPROM to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+    * the EE will not acknowledge a PHUB request.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -637,11 +693,14 @@ void CyEEPROM_Start(void)
 *******************************************************************************/
 void CyEEPROM_Stop (void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    uint8 interruptState;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -661,12 +720,12 @@ void CyEEPROM_Stop (void)
 *******************************************************************************/
 void CyEEPROM_ReadReserve(void) 
 {
-    /* Make a request for PHUB to have access */
-    *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+    /* Make request for PHUB to have access */
+    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
 
-    while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
+    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
     {
-        /* Wait for acknowledgement from PHUB */
+        /* Wait for acknowledgment from PHUB */
     }
 }
 
@@ -687,7 +746,7 @@ void CyEEPROM_ReadReserve(void)
 *******************************************************************************/
 void CyEEPROM_ReadRelease(void) 
 {
-    *CY_FLASH_EE_SCR_PTR |= 0x00u;
+    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
 }
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
old mode 100755
new mode 100644
index 69f8c88c..119d7fc6
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the FLASH/EEPROM.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,13 +41,19 @@ extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 #define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
 #define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
 
+#if(CYDEV_ECC_ENABLE == 0)
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
 #define CY_EEPROM_BASE              (CYDEV_EE_BASE)
 #define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
 #define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EEPROM_SECTOR_SIZE)
 #define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS       (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
 #define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-
+#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
 
 #if !defined(CYDEV_FLS_BASE)
     #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
@@ -85,13 +91,29 @@ void CyEEPROM_ReadRelease(void) ;
 /***************************************
 *     Registers
 ***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
+
 /* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
 
 /* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
 
 
 /* Cache Control Register */
@@ -119,35 +141,64 @@ void CyEEPROM_ReadRelease(void) ;
 ***************************************/
 
 /* Power Mode Masks */
-#define CY_FLASH_PM_EE_MASK                 (0x10u)
-#define CY_FLASH_PM_FLASH_MASK              (0x01u)
 
-/* Frequency Constants */
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
+
+/* Enable Flash */
 #if (CY_PSOC3)
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
+#else
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
+#endif  /* (CY_PSOC3) */
+
 
-    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
-    #define CY_FLASH_GREATER_44MHz              (0x03u)
 
+/* Frequency Constants */
+#if (CY_PSOC3)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
 #endif  /* (CY_PSOC3) */
 
 #if (CY_PSOC5)
-
-    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
-    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
-    #define CY_FLASH_GREATER_51MHz              (0x00u)
-
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
+    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
+    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
+    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
 #endif  /* (CY_PSOC5) */
 
 #define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
 #define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-#define CY_FLASH_EE_STARTUP_DELAY               (5u)
 
 #define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
 #define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
 
 
+#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
 
 /* Default values for getting temperature. */
 
@@ -167,7 +218,42 @@ void CyEEPROM_ReadRelease(void) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
+    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
+    #define CY_FLASH_GREATER_51MHz              (0x00u)
+#endif  /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
+    #define CY_FLASH_GREATER_44MHz              (0x03u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
 *******************************************************************************/
 #define FLASH_SIZE                  (CY_FLASH_SIZE)
 #define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
@@ -177,12 +263,10 @@ void CyEEPROM_ReadRelease(void) ;
 #define EEPROM_SIZEOF_SECTOR        (CY_EEPROM_SIZEOF_ARRAY)
 #define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
 #define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_NUMBER_SECTORS    (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_SIZEOF_SECTOR     (CY_EEPROM_SIZEOF_ARRAY)
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
 *******************************************************************************/
 #define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
old mode 100755
new mode 100644
index 206c6cb1..a36bee0d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
@@ -1,16 +1,16 @@
 /*******************************************************************************
 * File Name: CyLib.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   Provides system API for the clocking, interrupts and watchdog timer.
+*   Provides a system API for the clocking, interrupts and watchdog timer.
 *
 *  Note:
 *   Documentation of the API's in this file is located in the
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -49,6 +49,12 @@ static uint8 CyUSB_PowerOnCheck(void)  ;
 static void CyIMO_SetTrimValue(uint8 freq) ;
 static void CyBusClk_Internal_SetDivider(uint16 divider);
 
+#if(CY_PSOC5)
+	static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+    static void CySysTickServiceCallbacks(void);
+    uint32 CySysTickInitVar = 0u;
+#endif  /* (CY_PSOC5) */
+
 
 /*******************************************************************************
 * Function Name: CyPLL_OUT_Start
@@ -72,7 +78,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider);
 *     clock can still be used.
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -95,7 +101,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
     uint8 pmTwCfg2State;
 
 
-    /* Enables the PLL circuit  */
+    /* Enables PLL circuit  */
     CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
 
     if(wait != 0u)
@@ -111,7 +117,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
 
         while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
             if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
             {
                 if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
@@ -180,11 +186,11 @@ void CyPLL_OUT_Stop(void)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -235,11 +241,11 @@ void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -279,7 +285,7 @@ void CyPLL_OUT_SetSource(uint8 source)
 *  None
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -305,7 +311,7 @@ void CyIMO_Start(uint8 wait)
 
     if(0u != wait)
     {
-        /* Need to turn on the 100KHz ILO if it happens to not already be running.*/
+        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
         ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
         pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
         pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
@@ -314,7 +320,7 @@ void CyIMO_Start(uint8 wait)
 
         while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
         }
 
         if(0u == ilo100KhzEnable)
@@ -442,7 +448,7 @@ static void CyIMO_SetTrimValue(uint8 freq)
         /* If USB is powered */
         if(usbPowerOn == 1u)
         {
-            /* Lock the USB Oscillator */
+            /* Lock USB Oscillator */
             CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
         }
         break;
@@ -477,11 +483,11 @@ static void CyIMO_SetTrimValue(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When the USB setting is chosen, the USB clock locking circuit is enabled.
@@ -495,15 +501,15 @@ void CyIMO_SetFreq(uint8 freq)
     uint8 nextFreq;
 
     /***************************************************************************
-    * When changing the IMO frequency the Trim values must also be set
+    * If the IMO frequency is changed,the Trim values must also be set
     * accordingly.This requires reading the current frequency. If the new
-    * frequency is faster, then set the new trim and then change the frequency,
-    * otherwise change the frequency and then set the new trim values.
+    * frequency is faster, then set a new trim and then change the frequency,
+    * otherwise change the frequency and then set new trim values.
     ***************************************************************************/
 
     currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
 
-    /* Check if the requested frequency is USB. */
+    /* Check if requested frequency is USB. */
     nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
 
     switch (currentFreq)
@@ -545,11 +551,11 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq >= currentFreq)
     {
-        /* Set the new trim first */
+        /* Set new trim first */
         CyIMO_SetTrimValue(freq);
     }
 
-    /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
     switch(freq)
     {
     case CY_IMO_FREQ_3MHZ:
@@ -599,7 +605,7 @@ void CyIMO_SetFreq(uint8 freq)
         break;
     }
 
-    /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */
+    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
     if (freq == CY_IMO_FREQ_USB)
     {
         CyIMO_EnableDoubler();
@@ -611,7 +617,7 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq < currentFreq)
     {
-        /* Set the new trim after setting the frequency */
+        /* Set the trim after setting frequency */
         CyIMO_SetTrimValue(freq);
     }
 }
@@ -625,7 +631,7 @@ void CyIMO_SetFreq(uint8 freq)
 *  Sets the source of the clock output from the IMO block.
 *
 *  The output from the IMO is by default the IMO itself. Optionally the MHz
-*  Crystal or a DSI input can be the source of the IMO output instead.
+*  Crystal or DSI input can be the source of the IMO output instead.
 *
 * Parameters:
 *   source: CY_IMO_SOURCE_DSI to set the DSI as source.
@@ -636,11 +642,11 @@ void CyIMO_SetFreq(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -687,7 +693,7 @@ void CyIMO_SetSource(uint8 source)
 *******************************************************************************/
 void CyIMO_EnableDoubler(void) 
 {
-    /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */
+    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
     CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
 }
 
@@ -733,11 +739,11 @@ void CyIMO_DisableDoubler(void)
 *  The current source and the new source must both be running and stable before
 *  calling this function.
 *
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -757,18 +763,18 @@ void CyMasterClk_SetSource(uint8 source)
 *
 * Parameters:
 *  uint8 divider:
-*   Valid range [0-255]. The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   The valid range is [0-255]. The clock will be divided by this value + 1.
+*   For example to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When changing the Master or Bus clock divider value from div-by-n to div-by-1
@@ -787,12 +793,12 @@ void CyMasterClk_SetDivider(uint8 divider)
 ********************************************************************************
 *
 * Summary:
-*  Function used by CyBusClk_SetDivider(). For internal use only.
+*  The function used by CyBusClk_SetDivider(). For internal use only.
 *
 * Parameters:
 *   divider: Valid range [0-65535].
 *   The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
@@ -807,7 +813,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
     /* Enable mask bits to enable shadow loads */
     CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
 
-    /* Update Shadow Divider Value Register with the new divider */
+    /* Update Shadow Divider Value Register with new divider */
     CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
     CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
 
@@ -827,21 +833,21 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
 ********************************************************************************
 *
 * Summary:
-*  Sets the divider value used to generate Bus Clock.
+*  Sets the divider value used to generate the Bus Clock.
 *
 * Parameters:
 *  divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-*  For example to divide by 2 this parameter should be set to 1.
+*  For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -853,13 +859,13 @@ void CyBusClk_SetDivider(uint16 divider)
 
     interruptState = CyEnterCriticalSection();
 
-    /* Work around to set the bus clock divider value */
+    /* Work around to set bus clock divider value */
     busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
     busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
 
     if ((divider == 0u) || (busClkDiv == 0u))
     {
-        /* Save away the master clock divider value */
+        /* Save away master clock divider value */
         masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
 
         if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
@@ -870,7 +876,7 @@ void CyBusClk_SetDivider(uint16 divider)
 
         if (divider == 0u)
         {
-            /* Set the SSS bit and the divider register desired value */
+            /* Set SSS bit and divider register desired value */
             CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
             CyBusClk_Internal_SetDivider(divider);
         }
@@ -880,7 +886,7 @@ void CyBusClk_SetDivider(uint16 divider)
             CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
         }
 
-        /* Restore the master clock */
+        /* Restore master clock */
         CyMasterClk_SetDivider(masterClkDiv);
     }
     else
@@ -904,17 +910,17 @@ void CyBusClk_SetDivider(uint16 divider)
     *
     * Parameters:
     *  divider: Valid range [0-15]. The clock will be divided by this value + 1.
-    *  For example to divide by 2 this parameter should be set to 1.
+    *  For example, to divide this parameter by two should be set to 1.
     *
     * Return:
     *  None
     *
     * Side Effects:
-    *  If as result of this function execution the CPU clock frequency is increased
-    *  then the number of clock cycles the cache will wait before it samples data
-    *  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-    *  with appropriate parameter. It can be optionally called if CPU clock
-    *  frequency is lowered in order to improve CPU performance.
+    *  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
     *  See CyFlash_SetWaitCycles() description for more information.
     *
     *******************************************************************************/
@@ -972,7 +978,7 @@ void CyUsbClk_SetSource(uint8 source)
 *******************************************************************************/
 void CyILO_Start1K(void) 
 {
-    /* Set the bit 1 of ILO RS */
+    /* Set bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
 }
 
@@ -984,7 +990,7 @@ void CyILO_Start1K(void)
 * Summary:
 *  Disables the ILO 1 KHz oscillator.
 *
-*  Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power
+*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
 *  mode APIs are expected to be used. For more information, refer to the Power
 *  Management section of this document.
 *
@@ -1000,7 +1006,7 @@ void CyILO_Start1K(void)
 *******************************************************************************/
 void CyILO_Stop1K(void) 
 {
-    /* Clear the bit 1 of ILO RS */
+    /* Clear bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
 }
 
@@ -1064,7 +1070,7 @@ void CyILO_Stop100K(void)
 *******************************************************************************/
 void CyILO_Enable33K(void) 
 {
-    /* Set the bit 5 of ILO RS */
+    /* Set bit 5 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
 }
 
@@ -1141,7 +1147,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
     /* Get current state. */
     state = CY_LIB_SLOWCLK_ILO_CR0_REG;
 
-    /* Set the the oscillator power mode. */
+    /* Set the oscillator power mode. */
     if(mode != CY_ILO_FAST_START)
     {
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
@@ -1151,7 +1157,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
     }
 
-    /* Return the old mode. */
+    /* Return old mode. */
     return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
 }
 
@@ -1183,14 +1189,14 @@ void CyXTAL_32KHZ_Start(void)
         CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
     #endif  /* (CY_PSOC3) */
 
-    /* Enable operation of the 32K Crystal Oscillator */
+    /* Enable operation of 32K Crystal Oscillator */
     CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
 
     for (i = 1000u; i > 0u; i--)
     {
         if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
         {
-            /* Ready - switch to the hign power mode */
+            /* Ready - switch to high power mode */
             (void) CyXTAL_32KHZ_SetPowerMode(0u);
 
             break;
@@ -1256,9 +1262,9 @@ uint8 CyXTAL_32KHZ_ReadStatus(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the power mode for the 32 KHz oscillator used during sleep mode.
+*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
 *  Allows for lower power during sleep when there are fewer sources of noise.
-*  During active mode the oscillator is always run in high power mode.
+*  During the active mode the oscillator is always run in the high power mode.
 *
 * Parameters:
 *  uint8 mode
@@ -1345,7 +1351,7 @@ cystatus CyXTAL_Start(uint8 wait)
     uint8 pmTwCfg2Tmp;
 
 
-    /* Enables the MHz crystal oscillator circuit  */
+    /* Enables MHz crystal oscillator circuit  */
     CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
 
 
@@ -1366,19 +1372,19 @@ cystatus CyXTAL_Start(uint8 wait)
             /* Read XERR bit to clear it */
             (void) CY_CLK_XMHZ_CSR_REG;
 
-            /* Wait for a millisecond - 4 x 250 us */
+            /* Wait for 1 millisecond - 4 x 250 us */
             for(count = 4u; count > 0u; count--)
             {
                 while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
                 {
-                    /* Wait for the FTW interrupt event */
+                    /* Wait for FTW interrupt event */
                 }
             }
 
 
             /*******************************************************************
-            * High output indicates oscillator failure.
-            * Only can be used after start-up interval (1 ms) is completed.
+            * High output indicates an oscillator failure.
+            * Only can be used after a start-up interval (1 ms) is completed.
             *******************************************************************/
             if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
             {
@@ -1417,7 +1423,7 @@ cystatus CyXTAL_Start(uint8 wait)
 *******************************************************************************/
 void CyXTAL_Stop(void) 
 {
-    /* Disable the the oscillator. */
+    /* Disable oscillator. */
     FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
 }
 
@@ -1472,7 +1478,7 @@ void CyXTAL_DisableErrStatus(void)
 *
 * Summary:
 *  Reads the XERR status bit for the megahertz crystal. This status bit is a
-*  sticky clear on read value. This function is not available for PSoC5.
+*  sticky, clear on read. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1486,8 +1492,8 @@ void CyXTAL_DisableErrStatus(void)
 uint8 CyXTAL_ReadStatus(void) 
 {
     /***************************************************************************
-    * High output indicates oscillator failure. Only use this after start-up
-    * interval is completed. This can be used for status and failure recovery.
+    * High output indicates an oscillator failure. Only use this after a start-up
+    * interval is completed. This can be used for the status and failure recovery.
     ***************************************************************************/
     return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
 }
@@ -1501,7 +1507,7 @@ uint8 CyXTAL_ReadStatus(void)
 *  Enables the fault recovery circuit which will switch to the IMO in the case
 *  of a fault in the megahertz crystal circuit. The crystal must be up and
 *  running with the XERR bit at 0, before calling this function to prevent
-*  immediate fault switchover. This function is not available for PSoC5.
+*  an immediate fault switchover. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1543,7 +1549,7 @@ void CyXTAL_DisableFaultRecovery(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the startup settings for the crystal. Logic model outputs a frequency
+*  Sets the startup settings for the crystal. The logic model outputs a frequency
 *  (setting + 4) MHz when enabled.
 *
 *  This is artificial as the actual frequency is determined by an attached
@@ -1551,7 +1557,7 @@ void CyXTAL_DisableFaultRecovery(void)
 *
 * Parameters:
 *  setting: Valid range [0-31].
-*   Value is dependent on the frequency and quality of the crystal being used.
+*   The value is dependent on the frequency and quality of the crystal being used.
 *   Refer to the device TRM and datasheet for more information.
 *
 * Return:
@@ -1648,7 +1654,7 @@ void CyHalt(uint8 reason) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Forces a software reset of the device.
+*  Forces a device software reset.
 *
 * Parameters:
 *  None
@@ -1672,9 +1678,9 @@ void CySoftwareReset(void)
 *
 *  Note:
 *  CyDelay has been implemented with the instruction cache assumed enabled. When
-*  instruction cache is disabled on PSoC5, CyDelay will be two times larger. For
-*  example, with instruction cache disabled CyDelay(100) would result in about
-*  200 ms delay instead of 100 ms.
+*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+*  For example, with instruction cache disabled CyDelay(100) would result in
+*  about 200 ms delay instead of 100 ms.
 *
 * Parameters:
 *  milliseconds: number of milliseconds to delay.
@@ -1724,8 +1730,8 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
     *
     * Side Effects:
     *  CyDelayUS has been implemented with the instruction cache assumed enabled.
-    *  When instruction cache is disabled on PSoC 5, CyDelayUs will be two times
-    *  larger. For example, with instruction cache disabled CyDelayUs(100) would
+    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
     *  result in about 200 us delay instead of 100 us.
     *
     *  If the bus clock frequency is a small non-integer number, the actual delay
@@ -1745,10 +1751,10 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Sets clock frequency for CyDelay.
+*  Sets the clock frequency for CyDelay.
 *
 * Parameters:
-*  freq: Frequency of bus clock in Hertz.
+*  freq: The frequency of the bus clock in Hertz.
 *
 * Return:
 *  None
@@ -1779,7 +1785,7 @@ void CyDelayFreq(uint32 freq) CYREENTRANT
 *  Enables the watchdog timer.
 *
 *  The timer is configured for the specified count interval, the central
-*  timewheel is cleared, the setting for low power mode is configured and the
+*  timewheel is cleared, the setting for the low power mode is configured and the
 *  watchdog timer is enabled.
 *
 *  Once enabled the watchdog cannot be disabled. The watchdog counts each time
@@ -1826,11 +1832,11 @@ void CyWdtStart(uint8 ticks, uint8 lpMode)
     CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
     CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
 
-    /* Setting the low power mode */
+    /* Setting low power mode */
     CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
                        (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
 
-    /* Enables the watchdog reset */
+    /* Enables watchdog reset */
     CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
 }
 
@@ -1862,16 +1868,16 @@ void CyWdtClear(void)
 *
 * Summary:
 *  Enables the digital low voltage monitors to generate interrupt on Vddd
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vddd threshold:
+*  reset: The option to reset the device at a specified Vddd threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
 *  threshold: Sets the trip level for the voltage monitor.
-*  Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-*  interval.
+*  Values from 1.70 V to 5.45 V are accepted with an interval  of approximately
+*  250 mV.
 *
 * Return:
 *  None
@@ -1887,7 +1893,7 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
                             (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -1912,10 +1918,10 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
 *
 * Summary:
 *  Enables the analog low voltage monitors to generate interrupt on Vdda
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vdda threshold:
+*  reset: The option to reset the device at a specified Vdda threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
@@ -1936,7 +1942,7 @@ void CyVdLvAnalogEnable(uint8 reset, uint8 threshold)
     CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -2258,31 +2264,14 @@ void CyEnableInts(uint32 mask)
         CY_NOP;
         CY_NOP;
 
-        /* All entries in the cache are invalidated on the next clock cycle. */
+        /* All entries in cache are invalidated on next clock cycle. */
         CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
 
+        /* Once this is executed it's guaranteed the cache has been flushed */
+        (void) CY_CACHE_CONTROL_REG;
 
-        /***********************************************************************
-        * The prefetch unit could/would be filled with the instructions that
-        * succeed the flush. Since a flush is desired then theoretically those
-        * instructions might be considered stale/invalid.
-        ***********************************************************************/
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
+        /* Flush the pipeline */
+        CY_SYS_ISB;
 
         /* Restore global interrupt enable state */
         CyExitCriticalSection(interruptState);
@@ -2298,8 +2287,18 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *  number: Interrupt number, valid range [0-15].
-       address: Pointer to an interrupt service routine.
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    *  address: Pointer to an interrupt service routine.
     *
     * Return:
     *   The old ISR vector at this location.
@@ -2332,7 +2331,16 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *   number: The interrupt number, valid range [0-15].
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
     *
     * Return:
     *   Address of the ISR in the interrupt vector table.
@@ -2390,7 +2398,7 @@ void CyEnableInts(uint32 mask)
     *  number: Valid range [0-31].  Interrupt number
     *
     * Return:
-    *  Address of the ISR in the interrupt vector table.
+    *  The address of the ISR in the interrupt vector table.
     *
     *******************************************************************************/
     cyisraddress CyIntGetVector(uint8 number)
@@ -2471,10 +2479,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR;
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
     }
 
@@ -2609,10 +2617,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
     }
 
@@ -2630,20 +2638,20 @@ void CyEnableInts(uint32 mask)
     *  If 1 is passed as a parameter:
     *   - if any of the SC blocks are used - enable pumps for the SC blocks and
     *     start boost clock.
-    *   - For the each enabled SC block set boost clock index and enable boost
+    *   - For each enabled SC block set a boost clock index and enable the boost
     *     clock.
     *
     *  If non-1 value is passed as a parameter:
     *   - If all SC blocks are not used - disable pumps for the SC blocks and
-    *     stop boost clock.
-    *   - For the each enabled SC block clear boost clock index and disable boost
+    *     stop the boost clock.
+    *   - For each enabled SC block clear the boost clock index and disable the  boost
     *     clock.
     *
-    *  The global variable CyScPumpEnabled is updated to be equal to passed
+    *  The global variable CyScPumpEnabled is updated to be equal to passed the
     *  parameter.
     *
     * Parameters:
-    *   uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.
+    *   uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
     *                 1 - Enable
     *                 0 - Disable
     *
@@ -2707,4 +2715,391 @@ void CyEnableInts(uint32 mask)
 #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
+#if(CY_PSOC5)
+    /*******************************************************************************
+    * Function Name: CySysTickStart
+    ********************************************************************************
+    *
+    * Summary:
+    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
+    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
+    *  Refer to the corresponding function description for the details.
+
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStart(void)
+    {
+        if (0u == CySysTickInitVar)
+        {
+            CySysTickInit();
+            CySysTickInitVar = 1u;
+        }
+
+        CySysTickEnable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickInit
+    ********************************************************************************
+    *
+    * Summary:
+    *  Initializes the callback addresses with pointers to NULL, associates the
+    *  SysTick system vector with the function that is responsible for calling
+    *  registered callback functions, configures SysTick timer to generate interrupt
+    * every 1 ms.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set.
+    *
+    *  The 1 ms interrupt interval is configured based on the frequency determined
+    *  by PSoC Creator at build time. If System clock frequency is changed in
+    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
+    *
+    *******************************************************************************/
+    void CySysTickInit(void)
+    {
+        uint32 i;
+
+        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+        {
+            CySysTickCallbacks[i] = (void *) 0;
+        }
+
+    	(void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+        CySysTickSetReload(cydelay_freq_hz/1000u);
+        CySysTickClear();
+        CyIntEnable(CY_INT_SYSTICK_IRQN);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick timer and its interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnable(void)
+    {
+        CySysTickEnableInterrupt();
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickStop
+    ********************************************************************************
+    *
+    * Summary:
+    *  Stops the system timer (SysTick).
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStop(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickDisableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickDisableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero. This
+    *  function do not change or reset current sysTick counter value, so it should
+    *  be cleared using CySysTickClear() API.
+    *
+    * Parameters:
+    *  value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickSetReload(uint32 value)
+    {
+        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Counter reset value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetReload(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetValue
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets current SysTick counter value.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Current SysTick counter value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetValue(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetClockSource
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the clock source for the SysTick counter.
+    *
+    * Parameters:
+    *  clockSource: Clock source for SysTick counter
+    *         Define                     Clock Source
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                              clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set. If clock source is not ready this
+    *  function call will have no effect. After changing clock source to the low frequency
+    *  clock the counter and reload register values will remain unchanged so time to
+    *  the interrupt will be significantly bigger and vice versa.
+    *
+    *******************************************************************************/
+    void CySysTickSetClockSource(uint32 clockSource)
+    {
+        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+        {
+            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+        }
+        else
+        {
+            CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCountFlag
+    ********************************************************************************
+    *
+    * Summary:
+    *  The count flag is set once SysTick counter reaches zero.
+    *   The flag cleared on read.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Returns non-zero value if counter is set, otherwise zero is returned.
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetCountFlag(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickClear
+    ********************************************************************************
+    *
+    * Summary:
+    *  Clears the SysTick counter for well-defined startup.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickClear(void)
+    {
+        CY_SYS_SYST_CVR_REG = 0u;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function set the pointers to the functions that will be called on
+    *  SysTick interrupt.
+    *
+    * Parameters:
+    *  number:  The number of callback function address to be set.
+    *           The valid range is from 0 to 4.
+    *  CallbackFunction: Function address.
+    *
+    * Return:
+    *  Returns the address of the previous callback function.
+    *  The NULL is returned if the specified address in not set.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+    {
+        cySysTickCallback retVal;
+
+        retVal = CySysTickCallbacks[number];
+        CySysTickCallbacks[number] = function;
+        return (retVal);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function get the specified callback pointer.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickGetCallback(uint32 number)
+    {
+        return ((cySysTickCallback) CySysTickCallbacks[number]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickServiceCallbacks
+    ********************************************************************************
+    *
+    * Summary:
+    *  System Tick timer interrupt routine
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    static void CySysTickServiceCallbacks(void)
+    {
+        uint32 i;
+
+        /* Verify that tick timer flag was set */
+        if (1u == CySysTickGetCountFlag())
+        {
+            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+            {
+                if (CySysTickCallbacks[i] != (void *) 0)
+                {
+                    (void)(CySysTickCallbacks[i])();
+                }
+            }
+        }
+    }
+#endif /* (CY_PSOC5) */
+
+
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
old mode 100755
new mode 100644
index 8a69921b..a718ffad
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyLib.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the system, clocking, interrupts and
@@ -11,7 +11,7 @@
 *  Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -163,6 +163,30 @@ uint8 CyVdRealTimeStatus(void) ;
 
 void CySetScPumps(uint8 enable) ;
 
+#if(CY_PSOC5)
+    /* Default interrupt handler */
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif  /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+    /* System tick timer APIs */
+    typedef void (*cySysTickCallback)(void);
+
+    void CySysTickStart(void);
+    void CySysTickInit(void);
+    void CySysTickEnable(void);
+    void CySysTickStop(void);
+    void CySysTickEnableInterrupt(void);
+    void CySysTickDisableInterrupt(void);
+    void CySysTickSetReload(uint32 value);
+    uint32 CySysTickGetReload(void);
+    uint32 CySysTickGetValue(void);
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+    cySysTickCallback CySysTickGetCallback(uint32 number);
+    void CySysTickSetClockSource(uint32 clockSource);
+    uint32 CySysTickGetCountFlag(void);
+    void CySysTickClear(void);
+#endif  /* (CY_PSOC5) */
 
 /***************************************
 * API Constants
@@ -400,6 +424,23 @@ void CySetScPumps(uint8 enable) ;
 #define CY_ALT_ACT_USB_ENABLED          (0x01u)
 
 
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * Instruction Synchronization Barrier flushes the pipeline in the processor,
+    * so that all instructions following the ISB are fetched from cache or
+    * memory, after the instruction has been completed.
+    ***************************************************************************/
+
+    #if defined(__ARMCC_VERSION)
+        #define CY_SYS_ISB       __isb(0x0f)
+    #else   /* ASM for GCC & IAR */
+        #define CY_SYS_ISB       asm volatile ("isb \n")
+    #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
 /***************************************
 * Registers
 ***************************************/
@@ -689,16 +730,29 @@ void CySetScPumps(uint8 enable) ;
     #define CY_CACHE_CONTROL_REG        (* (reg16 *) CYREG_CACHE_CC_CTL )
     #define CY_CACHE_CONTROL_PTR        (  (reg16 *) CYREG_CACHE_CC_CTL )
 
+    /* System tick registers */
+    #define CY_SYS_SYST_CSR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+    #define CY_SYS_SYST_CSR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+    #define CY_SYS_SYST_RVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+    #define CY_SYS_SYST_RVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+    #define CY_SYS_SYST_CVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+    #define CY_SYS_SYST_CVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+    #define CY_SYS_SYST_CALIB_REG       (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+    #define CY_SYS_SYST_CALIB_PTR       ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
 #elif (CY_PSOC3)
 
     /* Interrupt Address Vector registers */
     #define CY_INT_VECT_TABLE           ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
 
-    /* Interrrupt Controller Priority Registers */
+    /* Interrupt Controller Priority Registers */
     #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_INTC_PRIOR0)
     #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_INTC_PRIOR0)
 
-    /* Interrrupt Controller Set Enable Registers */
+    /* Interrupt Controller Set Enable Registers */
     #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
     #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
 
@@ -714,7 +768,7 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
     #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
 
-    /* Interrrupt Controller Clear Enable Registers */
+    /* Interrupt Controller Clear Enable Registers */
     #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
     #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
 
@@ -731,11 +785,11 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
 
 
-    /* Interrrupt Controller Set Pend Registers */
+    /* Interrupt Controller Set Pend Registers */
     #define CY_INT_SET_PEND_REG         (* (reg8 *) CYREG_INTC_SET_PD0)
     #define CY_INT_SET_PEND_PTR         (  (reg8 *) CYREG_INTC_SET_PD0)
 
-    /* Interrrupt Controller Clear Pend Registers */
+    /* Interrupt Controller Clear Pend Registers */
     #define CY_INT_CLR_PEND_REG         (* (reg8 *) CYREG_INTC_CLR_PD0)
     #define CY_INT_CLR_PEND_PTR         (  (reg8 *) CYREG_INTC_CLR_PD0)
 
@@ -753,8 +807,8 @@ void CySetScPumps(uint8 enable) ;
 * Macro Name: CyAssert
 ********************************************************************************
 * Summary:
-*  Macro that evaluates the expression and if it is false (evaluates to 0) then
-*  the processor is halted.
+*  The macro that evaluates the expression and if it is false (evaluates to 0)
+*  then the processor is halted.
 *
 *  This macro is evaluated unless NDEBUG is defined.
 *
@@ -791,7 +845,7 @@ void CySetScPumps(uint8 enable) ;
 #define CY_RESET_GPIO1              (0x80u)
 
 
-/* Interrrupt Controller Configuration and Status Register */
+/* Interrupt Controller Configuration and Status Register */
 #if(CY_PSOC3)
     #define INTERRUPT_CSR               ((reg8 *) CYREG_INTC_CSR_EN)
     #define DISABLE_IRQ_SET             ((uint8)(0x01u << 1u))    /* INTC_CSR_EN */
@@ -844,6 +898,19 @@ void CySetScPumps(uint8 enable) ;
 #define CY_CACHE_CONTROL_FLUSH          (0x0004u)
 #define CY_LIB_RESET_CR2_RESET          (0x01u)
 
+#if(CY_PSOC5)
+    /* System tick API constants */
+    #define CY_SYS_SYST_CSR_ENABLE              ((uint32) (0x01u))
+    #define CY_SYS_SYST_CSR_ENABLE_INT          ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT    ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT     ((uint32) (16u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK      ((uint32) (1u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK       ((uint32) (0u))
+    #define CY_SYS_SYST_RVR_CNT_MASK            ((uint32) (0x00FFFFFFu))
+    #define CY_SYS_SYST_NUM_OF_CALLBACKS        ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
 
 /*******************************************************************************
 * Interrupt API constants
@@ -876,6 +943,20 @@ void CySetScPumps(uint8 enable) ;
 /* Mask to get valid range of system interrupt 0-15 */
 #define CY_INT_SYS_NUMBER_MASK          (0xFu)
 
+#if(CY_PSOC5)
+
+    /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+    #define CY_INT_NMI_IRQN                  ( 2u)      /* Non Maskable Interrupt      */
+    #define CY_INT_HARD_FAULT_IRQN           ( 3u)      /* Hard Fault Interrupt        */
+    #define CY_INT_MEM_MANAGE_IRQN           ( 4u)      /* Memory Management Interrupt */
+    #define CY_INT_BUS_FAULT_IRQN            ( 5u)      /* Bus Fault Interrupt         */
+    #define CY_INT_USAGE_FAULT_IRQN          ( 6u)      /* Usage Fault Interrupt       */
+    #define CY_INT_SVCALL_IRQN               (11u)      /* SV Call Interrupt           */
+    #define CY_INT_DEBUG_MONITOR_IRQN        (12u)      /* Debug Monitor Interrupt     */
+    #define CY_INT_PEND_SV_IRQN              (14u)      /* Pend SV Interrupt           */
+    #define CY_INT_SYSTICK_IRQN              (15u)      /* System Tick Interrupt       */
+
+#endif  /* (CY_PSOC5) */
 
 /*******************************************************************************
 * Interrupt Macros
@@ -1027,18 +1108,26 @@ void CySetScPumps(uint8 enable) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used.
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+
 #define CYGlobalIntEnable       CyGlobalIntEnable
 #define CYGlobalIntDisable      CyGlobalIntDisable
 
 #define cymemset(s,c,n)         memset((s),(c),(n))
 #define cymemcpy(d,s,n)         memcpy((d),(s),(n))
 
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
-*******************************************************************************/
 #define MFGCFG_X32_TR_PTR               (CY_CLK_XTAL32_TR_PTR)
 #define MFGCFG_X32_TR                   (CY_CLK_XTAL32_TR_REG)
 #define SLOWCLK_X32_TST_PTR             (CY_CLK_XTAL32_TST_PTR)
@@ -1123,10 +1212,6 @@ void CySetScPumps(uint8 enable) ;
 #define CY_VD_PRESISTENT_STATUS_PTR    (CY_VD_PERSISTENT_STATUS_PTR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20
-*******************************************************************************/
-
 #if(CY_PSOC5)
 
     #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
@@ -1153,9 +1238,7 @@ void CySetScPumps(uint8 enable) ;
 #endif  /* (CY_PSOC5) */
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
-*******************************************************************************/
+
 #define BUS_AMASK_CLEAR                 (0xF0u)
 #define BUS_DMASK_CLEAR                 (0x00u)
 #define CLKDIST_LD_LOAD_SET             (0x01u)
@@ -1190,9 +1273,6 @@ void CySetScPumps(uint8 enable) ;
 #define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
-*******************************************************************************/
 #define IMO_PM_ENABLE                   (0x10u)
 #define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
 #define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
old mode 100755
new mode 100644
index 0d2b9302..21811611
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the System Performance Component.
@@ -8,7 +8,7 @@
 *   application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -231,6 +231,11 @@ cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], u
 * Summary:
 *  Loads a row of data into the row latch of a Flash/EEPROM array.
 *
+*  The buffer pointer should point to the data that should be written to the
+*  flash row directly (no data in ECC/flash will be preserved). It is Flash API
+*  responsibility to prepare data: the preserved data are copied from flash into
+*  array with the modified data.
+*
 * Parameters:
 *  uint8 array:
 *   Id of the array.
@@ -286,6 +291,149 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+*  Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+*  The only data that are going to be changed should be passed. The function
+*  will handle unmodified data preservation based on DWR settings and input
+*  parameters.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 row:
+*   Flash row number to be loaded.
+*
+*  uint8* buffer:
+*   Data to be loaded to the row latch
+*
+*  uint8 size:
+*   The number of data bytes that the SPC expects to be written. Depends on the
+*   type of the array and, if the array is Flash, whether ECC is being enabled
+*   or not. There are following values: flash row latch size with ECC enabled,
+*   flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+    cystatus status = CYRET_STARTED;
+    uint16 i;
+
+    #if (CYDEV_ECC_ENABLE == 0)
+        uint32 offset;
+    #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+            * Data in ECC" DWR options are disabled, ECC section is available
+            * for user data.
+            *******************************************************************/
+            #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+                /*******************************************************************
+                * If size parameter equals size of the ECC row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the ECC section.
+                * In this case flash data must be preserved. The flash data copied
+                * from flash data section to the SPC data register.
+                *******************************************************************/
+                if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_FLS_BASE +
+                             ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+                             ((uint32)   row * CYDEV_FLS_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+            for(i = 0u; i < size; i++)
+            {
+                CY_SPC_CPU_DATA_REG = buffer[i];
+            }
+
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+            * ECC section can be used for storing device configuration data
+            * ("Store Configuration Data in ECC" DWR option is enabled) or for
+            * storing user data in the ECC section ("Store Configuration Data in
+            * ECC" DWR option is enabled). In both cases, the data in the ECC
+            * section must be preserved if flash data is written.
+            *******************************************************************/
+            #if (CYDEV_ECC_ENABLE == 0)
+
+
+                /*******************************************************************
+                * If size parameter equals size of the flash row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the flash data
+                * section. In this case, ECC section data must be preserved.
+                * The ECC section data copied from ECC section to the SPC data
+                * register.
+                *******************************************************************/
+                if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_ECC_BASE +
+                            ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+                            ((uint32) row   * CYDEV_ECC_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #else
+
+                if(0u != row)
+                {
+                    /* To remove unreferenced local variable warning */
+                }
+
+            #endif /* (CYDEV_ECC_ENABLE == 0) */
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySpcWriteRow
 ********************************************************************************
@@ -551,4 +699,38 @@ void CySpcUnlock(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+*  Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
 /* [] END OF FILE */
+
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
old mode 100755
new mode 100644
index 6a5828c5..36f764ef
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides definitions for the System Performance Component API.
@@ -8,7 +8,7 @@
 *  application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,10 +37,13 @@ uint8    CySpcReadData(uint8 buffer[], uint8 size);
 cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
 ;
 cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
 cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
 ;
 cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
 cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
 cystatus CySpcLock(void);
 void     CySpcUnlock(void);
 
@@ -69,7 +72,7 @@ void     CySpcUnlock(void);
 #define CY_SPC_STATUS_CODE_MASK             (0xFCu)
 #define CY_SPC_STATUS_CODE_SHIFT            (0x02u)
 
-/* Status codes for the SPC. */
+/* Status codes for SPC. */
 #define CY_SPC_STATUS_SUCCESS               (0x00u)   /* Operation Successful */
 #define CY_SPC_STATUS_INVALID_ARRAY_ID      (0x01u)   /* Invalid Array ID for given command */
 #define CY_SPC_STATUS_INVALID_2BYTEKEY      (0x02u)   /* Invalid 2-byte key */
@@ -137,7 +140,18 @@ void     CySpcUnlock(void);
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define FIRST_FLASH_ARRAYID         (CY_SPC_FIRST_FLASH_ARRAYID)
 #define LAST_FLASH_ARRAYID          (CY_SPC_LAST_FLASH_ARRAYID)
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c
index 2d991148..ba36af7a 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Debug_Timer.c
-* Version 2.50
+* Version 2.70
 *
 * Description:
 *  The Timer component consists of a 8, 16, 24 or 32-bit timer with
@@ -15,7 +15,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -129,10 +129,12 @@ void Debug_Timer_Init(void)
         #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
 
         #if (Debug_Timer_SoftwareTriggerMode)
-            if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
-            {
-                Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
-            }
+            #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+                if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
+                {
+                    Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
+                }
+            #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
         #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
 
         /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
@@ -148,12 +150,11 @@ void Debug_Timer_Init(void)
         #if (Debug_Timer_EnableTriggerMode)
             Debug_Timer_EnableTrigger();
         #endif /* Set Trigger enable bit for UDB implementation in the control register*/
-
-        #if (Debug_Timer_InterruptOnCaptureCount)
-             #if (!Debug_Timer_ControlRegRemoved)
-                Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
-            #endif /* Set interrupt count in control register if control register is not removed */
-        #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+		
+		
+        #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
+            Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
+        #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
 
         Debug_Timer_ClearFIFO();
     #endif /* Configure additional features of UDB implementation */
@@ -185,7 +186,7 @@ void Debug_Timer_Enable(void)
     #endif /* Set Enable bit for enabling Fixed function timer*/
 
     /* Remove assignment if control register is removed */
-    #if (!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
         Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
     #endif /* Remove assignment if control register is removed */
 }
@@ -246,7 +247,7 @@ void Debug_Timer_Start(void)
 void Debug_Timer_Stop(void) 
 {
     /* Disable Timer */
-    #if(!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
         Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
     #endif /* Remove assignment if control register is removed */
 
@@ -301,7 +302,11 @@ void Debug_Timer_SetInterruptMode(uint8 interruptMode)
 void Debug_Timer_SoftwareCapture(void) 
 {
     /* Generate a software capture by reading the counter register */
-    (void)Debug_Timer_COUNTER_LSB;
+    #if(Debug_Timer_UsingFixedFunction)
+        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+    #else
+        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+    #endif/* (Debug_Timer_UsingFixedFunction) */
     /* Capture Data is now in the FIFO */
 }
 
@@ -331,7 +336,7 @@ uint8   Debug_Timer_ReadStatusRegister(void)
 }
 
 
-#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
+#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
 
 
 /*******************************************************************************
@@ -350,7 +355,11 @@ uint8   Debug_Timer_ReadStatusRegister(void)
 *******************************************************************************/
 uint8 Debug_Timer_ReadControlRegister(void) 
 {
-    return ((uint8)Debug_Timer_CONTROL);
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
+        return ((uint8)Debug_Timer_CONTROL);
+    #else
+        return (0);
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
 
 
@@ -369,9 +378,14 @@ uint8 Debug_Timer_ReadControlRegister(void)
 *******************************************************************************/
 void Debug_Timer_WriteControlRegister(uint8 control) 
 {
-    Debug_Timer_CONTROL = control;
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
+        Debug_Timer_CONTROL = control;
+    #else
+        control = 0u;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
-#endif /* Remove API if control register is removed */
+
+#endif /* Remove API if control register is unused */
 
 
 /*******************************************************************************
@@ -463,8 +477,7 @@ uint16 Debug_Timer_ReadCapture(void)
 *  void
 *
 *******************************************************************************/
-void Debug_Timer_WriteCounter(uint16 counter) \
-                                   
+void Debug_Timer_WriteCounter(uint16 counter) 
 {
    #if(Debug_Timer_UsingFixedFunction)
         /* This functionality is removed until a FixedFunction HW update to
@@ -494,11 +507,14 @@ void Debug_Timer_WriteCounter(uint16 counter) \
 *******************************************************************************/
 uint16 Debug_Timer_ReadCounter(void) 
 {
-
     /* Force capture by reading Accumulator */
     /* Must first do a software capture to be able to read the counter */
     /* It is up to the user code to make sure there isn't already captured data in the FIFO */
-    (void)Debug_Timer_COUNTER_LSB;
+    #if(Debug_Timer_UsingFixedFunction)
+        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+    #else
+        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+    #endif/* (Debug_Timer_UsingFixedFunction) */
 
     /* Read the data from the FIFO (or capture register for Fixed Function)*/
     #if(Debug_Timer_UsingFixedFunction)
@@ -511,6 +527,7 @@ uint16 Debug_Timer_ReadCounter(void)
 
 #if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
 
+    
 /*******************************************************************************
  * The functions below this point are only available using the UDB
  * implementation.  If a feature is selected, then the API is enabled.
@@ -552,11 +569,13 @@ void Debug_Timer_SetCaptureMode(uint8 captureMode)
     captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
     captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
 
-    /* Clear the Current Setting */
-    Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
 
-    /* Write The New Setting */
-    Debug_Timer_CONTROL |= captureMode;
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= captureMode;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
 #endif /* Remove API if Capture Mode is not Software Controlled */
 
@@ -588,12 +607,14 @@ void Debug_Timer_SetTriggerMode(uint8 triggerMode)
     /* This must only set to two bits of the control register associated */
     triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
 
-    /* Clear the Current Setting */
-    Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
-
-    /* Write The New Setting */
-    Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
+    
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
 
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+    #endif /* Remove code section if control register is not used */
 }
 #endif /* Remove API if Trigger Mode is not Software Controlled */
 
@@ -616,7 +637,7 @@ void Debug_Timer_SetTriggerMode(uint8 triggerMode)
 *******************************************************************************/
 void Debug_Timer_EnableTrigger(void) 
 {
-    #if (!Debug_Timer_ControlRegRemoved)   /* Remove assignment if control register is removed */
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
         Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
     #endif /* Remove code section if control register is not used */
 }
@@ -638,15 +659,13 @@ void Debug_Timer_EnableTrigger(void)
 *******************************************************************************/
 void Debug_Timer_DisableTrigger(void) 
 {
-    #if (!Debug_Timer_ControlRegRemoved)   /* Remove assignment if control register is removed */
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED )   /* Remove assignment if control register is removed */
         Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
     #endif /* Remove code section if control register is not used */
 }
 #endif /* Remove API is Trigger Mode is set to None */
 
-
 #if(Debug_Timer_InterruptOnCaptureCount)
-#if (!Debug_Timer_ControlRegRemoved)   /* Remove API if control register is removed */
 
 
 /*******************************************************************************
@@ -671,12 +690,13 @@ void Debug_Timer_SetInterruptCount(uint8 interruptCount)
     /* This must only set to two bits of the control register associated */
     interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
 
-    /* Clear the Current Setting */
-    Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
-    /* Write The New Setting */
-    Debug_Timer_CONTROL |= interruptCount;
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= interruptCount;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
-#endif /* Remove API if control register is removed */
 #endif /* Debug_Timer_InterruptOnCaptureCount */
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h
index 2170009e..2a8742cb 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Debug_Timer.h
-* Version 2.50
+* Version 2.70
 *
 *  Description:
 *     Contains the function prototypes and constants available to the timer
@@ -10,14 +10,14 @@
 *     None
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
 ********************************************************************************/
 
-#if !defined(CY_Timer_v2_30_Debug_Timer_H)
-#define CY_Timer_v2_30_Debug_Timer_H
+#if !defined(CY_Timer_v2_60_Debug_Timer_H)
+#define CY_Timer_v2_60_Debug_Timer_H
 
 #include "cytypes.h"
 #include "cyfitter.h"
@@ -28,7 +28,7 @@ extern uint8 Debug_Timer_initVar;
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component Timer_v2_50 requires cy_boot v3.0 or later
+    #error Component Timer_v2_70 requires cy_boot v3.0 or later
 #endif /* (CY_ PSOC5LP) */
 
 
@@ -47,6 +47,14 @@ extern uint8 Debug_Timer_initVar;
 #define Debug_Timer_RunModeUsed                0u
 #define Debug_Timer_ControlRegRemoved          0u
 
+#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
+#elif  (Debug_Timer_UsingFixedFunction)
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
+#else 
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (1u)
+#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
+
 
 /***************************************
 *       Type defines
@@ -60,27 +68,18 @@ typedef struct
 {
     uint8 TimerEnableState;
     #if(!Debug_Timer_UsingFixedFunction)
-        #if (CY_UDB_V0)
-            uint16 TimerUdb;                 /* Timer internal counter value */
-            uint16 TimerPeriod;              /* Timer Period value       */
-            uint8 InterruptMaskValue;       /* Timer Compare Value */
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                uint8 TimerCaptureCounter;  /* Timer Capture Counter Value */
-            #endif /* variable declaration for backing up Capture Counter value*/
-        #endif /* variables for non retention registers in CY_UDB_V0 */
-
-        #if (CY_UDB_V1)
-            uint16 TimerUdb;
-            uint8 InterruptMaskValue;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                uint8 TimerCaptureCounter;
-            #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
-        #endif /* (CY_UDB_V1) */
-
-        #if (!Debug_Timer_ControlRegRemoved)
+
+        uint16 TimerUdb;
+        uint8 InterruptMaskValue;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            uint8 TimerCaptureCounter;
+        #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+
+        #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
             uint8 TimerControlRegister;
         #endif /* variable declaration for backing up enable state of the Timer */
     #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+
 }Debug_Timer_backupStruct;
 
 
@@ -96,22 +95,18 @@ uint8   Debug_Timer_ReadStatusRegister(void) ;
 /* Deprecated function. Do not use this in future. Retained for backward compatibility */
 #define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
 
-#if(!Debug_Timer_ControlRegRemoved)
+#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
     uint8   Debug_Timer_ReadControlRegister(void) ;
-    void    Debug_Timer_WriteControlRegister(uint8 control) \
-        ;
-#endif /* (!Debug_Timer_ControlRegRemoved) */
+    void    Debug_Timer_WriteControlRegister(uint8 control) ;
+#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 
 uint16  Debug_Timer_ReadPeriod(void) ;
-void    Debug_Timer_WritePeriod(uint16 period) \
-    ;
+void    Debug_Timer_WritePeriod(uint16 period) ;
 uint16  Debug_Timer_ReadCounter(void) ;
-void    Debug_Timer_WriteCounter(uint16 counter) \
-    ;
+void    Debug_Timer_WriteCounter(uint16 counter) ;
 uint16  Debug_Timer_ReadCapture(void) ;
 void    Debug_Timer_SoftwareCapture(void) ;
 
-
 #if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
     #if (Debug_Timer_SoftwareCaptureMode)
         void    Debug_Timer_SetCaptureMode(uint8 captureMode) ;
@@ -120,21 +115,19 @@ void    Debug_Timer_SoftwareCapture(void) ;
     #if (Debug_Timer_SoftwareTriggerMode)
         void    Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
     #endif /* (Debug_Timer_SoftwareTriggerMode) */
+
     #if (Debug_Timer_EnableTriggerMode)
         void    Debug_Timer_EnableTrigger(void) ;
         void    Debug_Timer_DisableTrigger(void) ;
     #endif /* (Debug_Timer_EnableTriggerMode) */
 
+
     #if(Debug_Timer_InterruptOnCaptureCount)
-        #if(!Debug_Timer_ControlRegRemoved)
-            void    Debug_Timer_SetInterruptCount(uint8 interruptCount) \
-                ;
-        #endif /* (!Debug_Timer_ControlRegRemoved) */
+        void    Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
     #endif /* (Debug_Timer_InterruptOnCaptureCount) */
 
     #if (Debug_Timer_UsingHWCaptureCounter)
-        void    Debug_Timer_SetCaptureCount(uint8 captureCount) \
-            ;
+        void    Debug_Timer_SetCaptureCount(uint8 captureCount) ;
         uint8   Debug_Timer_ReadCaptureCount(void) ;
     #endif /* (Debug_Timer_UsingHWCaptureCounter) */
 
@@ -256,8 +249,8 @@ void Debug_Timer_Wakeup(void)        ;
     #if (CY_PSOC5A)
         /* Use CFG1 Mode bits to set run mode */
         /* As defined by Verilog Implementation */
-        #define Debug_Timer_CTRL_MODE_SHIFT                     0x01u
-        #define Debug_Timer_CTRL_MODE_MASK                     ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
+        #define Debug_Timer_CTRL_MODE_SHIFT                 0x01u
+        #define Debug_Timer_CTRL_MODE_MASK                 ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
     #endif /* (CY_PSOC5A) */
     #if (CY_PSOC3 || CY_PSOC5LP)
         /* Control3 Register Bit Locations */
@@ -367,6 +360,8 @@ void Debug_Timer_Wakeup(void)        ;
         #endif /* CY_PSOC3 || CY_PSOC5 */ 
     #endif
 
+    #define Debug_Timer_COUNTER_LSB_PTR_8BIT       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+    
     #if (Debug_Timer_UsingHWCaptureCounter)
         #define Debug_Timer_CAP_COUNT              (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
         #define Debug_Timer_CAP_COUNT_PTR          ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c
index 97f2d96d..c9c443b9 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Debug_Timer_PM.c
-* Version 2.50
+* Version 2.70
 *
 *  Description:
 *     This file provides the power management source code to API for the
@@ -10,13 +10,14 @@
 *     None
 *
 *******************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
 ********************************************************************************/
 
 #include "Debug_Timer.h"
+
 static Debug_Timer_backupStruct Debug_Timer_backup;
 
 
@@ -42,25 +43,13 @@ static Debug_Timer_backupStruct Debug_Timer_backup;
 void Debug_Timer_SaveConfig(void) 
 {
     #if (!Debug_Timer_UsingFixedFunction)
-        /* Backup the UDB non-rentention registers for CY_UDB_V0 */
-        #if (CY_UDB_V0)
-            Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
-            Debug_Timer_backup.TimerPeriod = Debug_Timer_ReadPeriod();
-            Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
-            #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
-        #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
-
-        #if (CY_UDB_V1)
-            Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
-            Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
-            #endif /* Back Up capture counter register  */
-        #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+        Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+        Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
+        #endif /* Back Up capture counter register  */
 
-        #if(!Debug_Timer_ControlRegRemoved)
+        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
             Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
         #endif /* Backup the enable state of the Timer component */
     #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
@@ -88,35 +77,14 @@ void Debug_Timer_SaveConfig(void)
 void Debug_Timer_RestoreConfig(void) 
 {   
     #if (!Debug_Timer_UsingFixedFunction)
-        /* Restore the UDB non-rentention registers for CY_UDB_V0 */
-        #if (CY_UDB_V0)
-            /* Interrupt State Backup for Critical Region*/
-            uint8 Debug_Timer_interruptState;
-
-            Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
-            Debug_Timer_WritePeriod(Debug_Timer_backup.TimerPeriod);
-            /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
-            /* Enter Critical Region*/
-            Debug_Timer_interruptState = CyEnterCriticalSection();
-            /* Use the interrupt output of the status register for IRQ output */
-            Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
-            /* Exit Critical Region*/
-            CyExitCriticalSection(Debug_Timer_interruptState);
-            Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
-            #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
-        #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
 
-        #if (CY_UDB_V1)
-            Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
-            Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
-            #endif /* Restore Capture counter register*/
-        #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+        Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+        Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
+        #endif /* Restore Capture counter register*/
 
-        #if(!Debug_Timer_ControlRegRemoved)
+        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
             Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
         #endif /* Restore the enable state of the Timer component */
     #endif /* Restore non retention registers in the UDB implementation only */
@@ -143,7 +111,7 @@ void Debug_Timer_RestoreConfig(void)
 *******************************************************************************/
 void Debug_Timer_Sleep(void) 
 {
-    #if(!Debug_Timer_ControlRegRemoved)
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
         /* Save Counter's enable state */
         if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
         {
@@ -182,7 +150,7 @@ void Debug_Timer_Sleep(void)
 void Debug_Timer_Wakeup(void) 
 {
     Debug_Timer_RestoreConfig();
-    #if(!Debug_Timer_ControlRegRemoved)
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
         if(Debug_Timer_backup.TimerEnableState == 1u)
         {     /* Enable Timer's operation */
                 Debug_Timer_Enable();
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c
old mode 100755
new mode 100644
index a70ea8ea..b0b3ba73
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED1.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void LED1_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  LED1_DM_STRONG     Strong Drive 
+*  LED1_DM_OD_HI      Open Drain, Drives High 
+*  LED1_DM_OD_LO      Open Drain, Drives Low 
+*  LED1_DM_RES_UP     Resistive Pull Up 
+*  LED1_DM_RES_DWN    Resistive Pull Down 
+*  LED1_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  LED1_DM_DIG_HIZ    High Impedance Digital 
+*  LED1_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h
old mode 100755
new mode 100644
index 7eb7d8dd..21cf5037
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED1.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h
old mode 100755
new mode 100644
index 040612f4..3e5d1131
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED1.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define LED1_0		LED1__0__PC
+#define LED1_0		(LED1__0__PC)
 
 #endif /* End Pins LED1_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
index 16a02412..6e8f8085 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_CLK.c
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
index 5c915030..e4c3e105 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_CLK.h
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
old mode 100755
new mode 100644
index 0f4eb676..8b2dbe8c
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_In_DBx.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,23 +25,23 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_In_DBx_0		SCSI_In_DBx__0__PC
-#define SCSI_In_DBx_1		SCSI_In_DBx__1__PC
-#define SCSI_In_DBx_2		SCSI_In_DBx__2__PC
-#define SCSI_In_DBx_3		SCSI_In_DBx__3__PC
-#define SCSI_In_DBx_4		SCSI_In_DBx__4__PC
-#define SCSI_In_DBx_5		SCSI_In_DBx__5__PC
-#define SCSI_In_DBx_6		SCSI_In_DBx__6__PC
-#define SCSI_In_DBx_7		SCSI_In_DBx__7__PC
-
-#define SCSI_In_DBx_DB0		SCSI_In_DBx__DB0__PC
-#define SCSI_In_DBx_DB1		SCSI_In_DBx__DB1__PC
-#define SCSI_In_DBx_DB2		SCSI_In_DBx__DB2__PC
-#define SCSI_In_DBx_DB3		SCSI_In_DBx__DB3__PC
-#define SCSI_In_DBx_DB4		SCSI_In_DBx__DB4__PC
-#define SCSI_In_DBx_DB5		SCSI_In_DBx__DB5__PC
-#define SCSI_In_DBx_DB6		SCSI_In_DBx__DB6__PC
-#define SCSI_In_DBx_DB7		SCSI_In_DBx__DB7__PC
+#define SCSI_In_DBx_0		(SCSI_In_DBx__0__PC)
+#define SCSI_In_DBx_1		(SCSI_In_DBx__1__PC)
+#define SCSI_In_DBx_2		(SCSI_In_DBx__2__PC)
+#define SCSI_In_DBx_3		(SCSI_In_DBx__3__PC)
+#define SCSI_In_DBx_4		(SCSI_In_DBx__4__PC)
+#define SCSI_In_DBx_5		(SCSI_In_DBx__5__PC)
+#define SCSI_In_DBx_6		(SCSI_In_DBx__6__PC)
+#define SCSI_In_DBx_7		(SCSI_In_DBx__7__PC)
+
+#define SCSI_In_DBx_DB0		(SCSI_In_DBx__DB0__PC)
+#define SCSI_In_DBx_DB1		(SCSI_In_DBx__DB1__PC)
+#define SCSI_In_DBx_DB2		(SCSI_In_DBx__DB2__PC)
+#define SCSI_In_DBx_DB3		(SCSI_In_DBx__DB3__PC)
+#define SCSI_In_DBx_DB4		(SCSI_In_DBx__DB4__PC)
+#define SCSI_In_DBx_DB5		(SCSI_In_DBx__DB5__PC)
+#define SCSI_In_DBx_DB6		(SCSI_In_DBx__DB6__PC)
+#define SCSI_In_DBx_DB7		(SCSI_In_DBx__DB7__PC)
 
 #endif /* End Pins SCSI_In_DBx_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
index ca519511..7f4d0f73 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_In.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,17 +25,17 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_In_0		SCSI_In__0__PC
-#define SCSI_In_1		SCSI_In__1__PC
-#define SCSI_In_2		SCSI_In__2__PC
-#define SCSI_In_3		SCSI_In__3__PC
-#define SCSI_In_4		SCSI_In__4__PC
-
-#define SCSI_In_DBP		SCSI_In__DBP__PC
-#define SCSI_In_MSG		SCSI_In__MSG__PC
-#define SCSI_In_CD		SCSI_In__CD__PC
-#define SCSI_In_REQ		SCSI_In__REQ__PC
-#define SCSI_In_IO		SCSI_In__IO__PC
+#define SCSI_In_0		(SCSI_In__0__PC)
+#define SCSI_In_1		(SCSI_In__1__PC)
+#define SCSI_In_2		(SCSI_In__2__PC)
+#define SCSI_In_3		(SCSI_In__3__PC)
+#define SCSI_In_4		(SCSI_In__4__PC)
+
+#define SCSI_In_DBP		(SCSI_In__DBP__PC)
+#define SCSI_In_MSG		(SCSI_In__MSG__PC)
+#define SCSI_In_CD		(SCSI_In__CD__PC)
+#define SCSI_In_REQ		(SCSI_In__REQ__PC)
+#define SCSI_In_IO		(SCSI_In__IO__PC)
 
 #endif /* End Pins SCSI_In_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
index ffd841d4..2bf11476 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Noise.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,17 +25,17 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Noise_0		SCSI_Noise__0__PC
-#define SCSI_Noise_1		SCSI_Noise__1__PC
-#define SCSI_Noise_2		SCSI_Noise__2__PC
-#define SCSI_Noise_3		SCSI_Noise__3__PC
-#define SCSI_Noise_4		SCSI_Noise__4__PC
-
-#define SCSI_Noise_ATN		SCSI_Noise__ATN__PC
-#define SCSI_Noise_BSY		SCSI_Noise__BSY__PC
-#define SCSI_Noise_SEL		SCSI_Noise__SEL__PC
-#define SCSI_Noise_RST		SCSI_Noise__RST__PC
-#define SCSI_Noise_ACK		SCSI_Noise__ACK__PC
+#define SCSI_Noise_0		(SCSI_Noise__0__PC)
+#define SCSI_Noise_1		(SCSI_Noise__1__PC)
+#define SCSI_Noise_2		(SCSI_Noise__2__PC)
+#define SCSI_Noise_3		(SCSI_Noise__3__PC)
+#define SCSI_Noise_4		(SCSI_Noise__4__PC)
+
+#define SCSI_Noise_ATN		(SCSI_Noise__ATN__PC)
+#define SCSI_Noise_BSY		(SCSI_Noise__BSY__PC)
+#define SCSI_Noise_SEL		(SCSI_Noise__SEL__PC)
+#define SCSI_Noise_RST		(SCSI_Noise__RST__PC)
+#define SCSI_Noise_ACK		(SCSI_Noise__ACK__PC)
 
 #endif /* End Pins SCSI_Noise_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
old mode 100755
new mode 100644
index 740ea099..7b232529
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_DBx.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,23 +25,23 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_DBx_0		SCSI_Out_DBx__0__PC
-#define SCSI_Out_DBx_1		SCSI_Out_DBx__1__PC
-#define SCSI_Out_DBx_2		SCSI_Out_DBx__2__PC
-#define SCSI_Out_DBx_3		SCSI_Out_DBx__3__PC
-#define SCSI_Out_DBx_4		SCSI_Out_DBx__4__PC
-#define SCSI_Out_DBx_5		SCSI_Out_DBx__5__PC
-#define SCSI_Out_DBx_6		SCSI_Out_DBx__6__PC
-#define SCSI_Out_DBx_7		SCSI_Out_DBx__7__PC
-
-#define SCSI_Out_DBx_DB0		SCSI_Out_DBx__DB0__PC
-#define SCSI_Out_DBx_DB1		SCSI_Out_DBx__DB1__PC
-#define SCSI_Out_DBx_DB2		SCSI_Out_DBx__DB2__PC
-#define SCSI_Out_DBx_DB3		SCSI_Out_DBx__DB3__PC
-#define SCSI_Out_DBx_DB4		SCSI_Out_DBx__DB4__PC
-#define SCSI_Out_DBx_DB5		SCSI_Out_DBx__DB5__PC
-#define SCSI_Out_DBx_DB6		SCSI_Out_DBx__DB6__PC
-#define SCSI_Out_DBx_DB7		SCSI_Out_DBx__DB7__PC
+#define SCSI_Out_DBx_0		(SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1		(SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2		(SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3		(SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4		(SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5		(SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6		(SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7		(SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0		(SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1		(SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2		(SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3		(SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4		(SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5		(SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6		(SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7		(SCSI_Out_DBx__DB7__PC)
 
 #endif /* End Pins SCSI_Out_DBx_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
old mode 100755
new mode 100644
index 7b32a93c..f711499d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,27 +25,27 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_0		SCSI_Out__0__PC
-#define SCSI_Out_1		SCSI_Out__1__PC
-#define SCSI_Out_2		SCSI_Out__2__PC
-#define SCSI_Out_3		SCSI_Out__3__PC
-#define SCSI_Out_4		SCSI_Out__4__PC
-#define SCSI_Out_5		SCSI_Out__5__PC
-#define SCSI_Out_6		SCSI_Out__6__PC
-#define SCSI_Out_7		SCSI_Out__7__PC
-#define SCSI_Out_8		SCSI_Out__8__PC
-#define SCSI_Out_9		SCSI_Out__9__PC
-
-#define SCSI_Out_DBP_raw		SCSI_Out__DBP_raw__PC
-#define SCSI_Out_ATN		SCSI_Out__ATN__PC
-#define SCSI_Out_BSY		SCSI_Out__BSY__PC
-#define SCSI_Out_ACK		SCSI_Out__ACK__PC
-#define SCSI_Out_RST		SCSI_Out__RST__PC
-#define SCSI_Out_MSG_raw		SCSI_Out__MSG_raw__PC
-#define SCSI_Out_SEL		SCSI_Out__SEL__PC
-#define SCSI_Out_CD_raw		SCSI_Out__CD_raw__PC
-#define SCSI_Out_REQ		SCSI_Out__REQ__PC
-#define SCSI_Out_IO_raw		SCSI_Out__IO_raw__PC
+#define SCSI_Out_0		(SCSI_Out__0__PC)
+#define SCSI_Out_1		(SCSI_Out__1__PC)
+#define SCSI_Out_2		(SCSI_Out__2__PC)
+#define SCSI_Out_3		(SCSI_Out__3__PC)
+#define SCSI_Out_4		(SCSI_Out__4__PC)
+#define SCSI_Out_5		(SCSI_Out__5__PC)
+#define SCSI_Out_6		(SCSI_Out__6__PC)
+#define SCSI_Out_7		(SCSI_Out__7__PC)
+#define SCSI_Out_8		(SCSI_Out__8__PC)
+#define SCSI_Out_9		(SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw		(SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN		(SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY		(SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK		(SCSI_Out__ACK__PC)
+#define SCSI_Out_RST		(SCSI_Out__RST__PC)
+#define SCSI_Out_MSG_raw		(SCSI_Out__MSG_raw__PC)
+#define SCSI_Out_SEL		(SCSI_Out__SEL__PC)
+#define SCSI_Out_CD_raw		(SCSI_Out__CD_raw__PC)
+#define SCSI_Out_REQ		(SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw		(SCSI_Out__IO_raw__PC)
 
 #endif /* End Pins SCSI_Out_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c
old mode 100755
new mode 100644
index 1824609c..c721ce6c
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CD.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_CD_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_CD_DM_STRONG     Strong Drive 
+*  SD_CD_DM_OD_HI      Open Drain, Drives High 
+*  SD_CD_DM_OD_LO      Open Drain, Drives Low 
+*  SD_CD_DM_RES_UP     Resistive Pull Up 
+*  SD_CD_DM_RES_DWN    Resistive Pull Down 
+*  SD_CD_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_CD_DM_DIG_HIZ    High Impedance Digital 
+*  SD_CD_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h
old mode 100755
new mode 100644
index fca729ea..3ad98a31
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CD.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h
old mode 100755
new mode 100644
index 782cb816..8237c485
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CD.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_CD_0		SD_CD__0__PC
+#define SD_CD_0		(SD_CD__0__PC)
 
 #endif /* End Pins SD_CD_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c
old mode 100755
new mode 100644
index 37a69196..c2189d9f
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CS.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_CS_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_CS_DM_STRONG     Strong Drive 
+*  SD_CS_DM_OD_HI      Open Drain, Drives High 
+*  SD_CS_DM_OD_LO      Open Drain, Drives Low 
+*  SD_CS_DM_RES_UP     Resistive Pull Up 
+*  SD_CS_DM_RES_DWN    Resistive Pull Down 
+*  SD_CS_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_CS_DM_DIG_HIZ    High Impedance Digital 
+*  SD_CS_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h
old mode 100755
new mode 100644
index aa66de1c..e4a4cc76
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CS.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h
old mode 100755
new mode 100644
index d6c29cca..d63225a7
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CS.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_CS_0		SD_CS__0__PC
+#define SD_CS_0		(SD_CS__0__PC)
 
 #endif /* End Pins SD_CS_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c
old mode 100755
new mode 100644
index 534aa575..bc671760
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_DAT1.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_DAT1_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_DAT1_DM_STRONG     Strong Drive 
+*  SD_DAT1_DM_OD_HI      Open Drain, Drives High 
+*  SD_DAT1_DM_OD_LO      Open Drain, Drives Low 
+*  SD_DAT1_DM_RES_UP     Resistive Pull Up 
+*  SD_DAT1_DM_RES_DWN    Resistive Pull Down 
+*  SD_DAT1_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_DAT1_DM_DIG_HIZ    High Impedance Digital 
+*  SD_DAT1_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h
old mode 100755
new mode 100644
index d7e22533..1c5c9409
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_DAT1.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h
old mode 100755
new mode 100644
index a26e0de3..0a708f80
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT1_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_DAT1.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_DAT1_0		SD_DAT1__0__PC
+#define SD_DAT1_0		(SD_DAT1__0__PC)
 
 #endif /* End Pins SD_DAT1_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c
old mode 100755
new mode 100644
index 8dfc6ae7..ea86b323
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_DAT2.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_DAT2_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_DAT2_DM_STRONG     Strong Drive 
+*  SD_DAT2_DM_OD_HI      Open Drain, Drives High 
+*  SD_DAT2_DM_OD_LO      Open Drain, Drives Low 
+*  SD_DAT2_DM_RES_UP     Resistive Pull Up 
+*  SD_DAT2_DM_RES_DWN    Resistive Pull Down 
+*  SD_DAT2_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_DAT2_DM_DIG_HIZ    High Impedance Digital 
+*  SD_DAT2_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h
old mode 100755
new mode 100644
index bfb30172..6f4fd8ce
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_DAT2.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h
old mode 100755
new mode 100644
index 5f262144..5767bc02
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_DAT2_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_DAT2.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_DAT2_0		SD_DAT2__0__PC
+#define SD_DAT2_0		(SD_DAT2__0__PC)
 
 #endif /* End Pins SD_DAT2_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
old mode 100755
new mode 100644
index f10eb3a8..cf5e5ff5
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Data_Clk.c
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
old mode 100755
new mode 100644
index 1d1e0987..478a20d7
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Data_Clk.h
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c
old mode 100755
new mode 100644
index 5a3ec620..50dcabfa
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MISO.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_MISO_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_MISO_DM_STRONG     Strong Drive 
+*  SD_MISO_DM_OD_HI      Open Drain, Drives High 
+*  SD_MISO_DM_OD_LO      Open Drain, Drives Low 
+*  SD_MISO_DM_RES_UP     Resistive Pull Up 
+*  SD_MISO_DM_RES_DWN    Resistive Pull Down 
+*  SD_MISO_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_MISO_DM_DIG_HIZ    High Impedance Digital 
+*  SD_MISO_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h
old mode 100755
new mode 100644
index e36fa070..7b91202a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MISO.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h
old mode 100755
new mode 100644
index 78313afb..a8f41caa
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MISO.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_MISO_0		SD_MISO__0__PC
+#define SD_MISO_0		(SD_MISO__0__PC)
 
 #endif /* End Pins SD_MISO_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c
old mode 100755
new mode 100644
index 7986406a..f980ba1f
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MOSI.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_MOSI_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_MOSI_DM_STRONG     Strong Drive 
+*  SD_MOSI_DM_OD_HI      Open Drain, Drives High 
+*  SD_MOSI_DM_OD_LO      Open Drain, Drives Low 
+*  SD_MOSI_DM_RES_UP     Resistive Pull Up 
+*  SD_MOSI_DM_RES_DWN    Resistive Pull Down 
+*  SD_MOSI_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_MOSI_DM_DIG_HIZ    High Impedance Digital 
+*  SD_MOSI_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h
old mode 100755
new mode 100644
index 54a0ded0..895fe9e4
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MOSI.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h
old mode 100755
new mode 100644
index 1cf2c44d..5f1a08ff
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MOSI.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_MOSI_0		SD_MOSI__0__PC
+#define SD_MOSI_0		(SD_MOSI__0__PC)
 
 #endif /* End Pins SD_MOSI_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c
old mode 100755
new mode 100644
index d5922364..fc984f3d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_SCK.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_SCK_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_SCK_DM_STRONG     Strong Drive 
+*  SD_SCK_DM_OD_HI      Open Drain, Drives High 
+*  SD_SCK_DM_OD_LO      Open Drain, Drives Low 
+*  SD_SCK_DM_RES_UP     Resistive Pull Up 
+*  SD_SCK_DM_RES_DWN    Resistive Pull Down 
+*  SD_SCK_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_SCK_DM_DIG_HIZ    High Impedance Digital 
+*  SD_SCK_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h
old mode 100755
new mode 100644
index a4a93510..8fc2dc53
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_SCK.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h
old mode 100755
new mode 100644
index 93890ac3..0a09ffdc
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_SCK.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_SCK_0		SD_SCK__0__PC
+#define SD_SCK_0		(SD_SCK__0__PC)
 
 #endif /* End Pins SD_SCK_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c
old mode 100755
new mode 100644
index 081e687e..7ebd294a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  API for USBFS Component.
@@ -11,7 +11,7 @@
 *  registers are indexed by variations of epNumber - 1.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -23,28 +23,33 @@
 #include "USBFS_hid.h"
 #if(USBFS_DMA1_REMOVE == 0u)
     #include "USBFS_ep1_dma.h"
-#endif   /* End USBFS_DMA1_REMOVE */
+#endif   /*  USBFS_DMA1_REMOVE */
 #if(USBFS_DMA2_REMOVE == 0u)
     #include "USBFS_ep2_dma.h"
-#endif   /* End USBFS_DMA2_REMOVE */
+#endif   /*  USBFS_DMA2_REMOVE */
 #if(USBFS_DMA3_REMOVE == 0u)
     #include "USBFS_ep3_dma.h"
-#endif   /* End USBFS_DMA3_REMOVE */
+#endif   /*  USBFS_DMA3_REMOVE */
 #if(USBFS_DMA4_REMOVE == 0u)
     #include "USBFS_ep4_dma.h"
-#endif   /* End USBFS_DMA4_REMOVE */
+#endif   /*  USBFS_DMA4_REMOVE */
 #if(USBFS_DMA5_REMOVE == 0u)
     #include "USBFS_ep5_dma.h"
-#endif   /* End USBFS_DMA5_REMOVE */
+#endif   /*  USBFS_DMA5_REMOVE */
 #if(USBFS_DMA6_REMOVE == 0u)
     #include "USBFS_ep6_dma.h"
-#endif   /* End USBFS_DMA6_REMOVE */
+#endif   /*  USBFS_DMA6_REMOVE */
 #if(USBFS_DMA7_REMOVE == 0u)
     #include "USBFS_ep7_dma.h"
-#endif   /* End USBFS_DMA7_REMOVE */
+#endif   /*  USBFS_DMA7_REMOVE */
 #if(USBFS_DMA8_REMOVE == 0u)
     #include "USBFS_ep8_dma.h"
-#endif   /* End USBFS_DMA8_REMOVE */
+#endif   /*  USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP_DMA_Done_isr.h"
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /***************************************
@@ -55,7 +60,25 @@ uint8 USBFS_initVar = 0u;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     uint8 USBFS_DmaChan[USBFS_MAX_EP];
     uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+    uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+    {   0u,
+        USBFS_ep1_TD_TERMOUT_EN,
+        USBFS_ep2_TD_TERMOUT_EN,
+        USBFS_ep3_TD_TERMOUT_EN,
+        USBFS_ep4_TD_TERMOUT_EN,
+        USBFS_ep5_TD_TERMOUT_EN,
+        USBFS_ep6_TD_TERMOUT_EN,
+        USBFS_ep7_TD_TERMOUT_EN,
+        USBFS_ep8_TD_TERMOUT_EN
+    };
+    volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -137,7 +160,7 @@ void USBFS_Init(void)
     uint8 enableInterrupts;
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         uint16 i;
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     enableInterrupts = CyEnterCriticalSection();
 
@@ -190,8 +213,11 @@ void USBFS_Init(void)
         for (i = 0u; i < USBFS_MAX_EP; i++)
         {
             USBFS_DmaTd[i] = DMA_INVALID_TD;
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
         }
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     CyExitCriticalSection(enableInterrupts);
 
@@ -204,7 +230,7 @@ void USBFS_Init(void)
     #if(USBFS_SOF_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_SOF_VECT_NUM,   &USBFS_SOF_ISR);
         CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
-    #endif   /* End USBFS_SOF_ISR_REMOVE */
+    #endif   /*  USBFS_SOF_ISR_REMOVE */
 
     /* Set the Control Endpoint Interrupt. */
     (void) CyIntSetVector(USBFS_EP_0_VECT_NUM,   &USBFS_EP_0_ISR);
@@ -214,55 +240,55 @@ void USBFS_Init(void)
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_1_VECT_NUM,   &USBFS_EP_1_ISR);
         CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
 
     /* Set the Data Endpoint 2 Interrupt. */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_2_VECT_NUM,   &USBFS_EP_2_ISR);
         CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
 
     /* Set the Data Endpoint 3 Interrupt. */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_3_VECT_NUM,   &USBFS_EP_3_ISR);
         CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
 
     /* Set the Data Endpoint 4 Interrupt. */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_4_VECT_NUM,   &USBFS_EP_4_ISR);
         CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
 
     /* Set the Data Endpoint 5 Interrupt. */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_5_VECT_NUM,   &USBFS_EP_5_ISR);
         CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
 
     /* Set the Data Endpoint 6 Interrupt. */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_6_VECT_NUM,   &USBFS_EP_6_ISR);
         CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
 
      /* Set the Data Endpoint 7 Interrupt. */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_7_VECT_NUM,   &USBFS_EP_7_ISR);
         CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
 
     /* Set the Data Endpoint 8 Interrupt. */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_8_VECT_NUM,   &USBFS_EP_8_ISR);
         CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* Set the ARB Interrupt. */
         (void) CyIntSetVector(USBFS_ARB_VECT_NUM,   &USBFS_ARB_ISR);
         CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
 }
 
@@ -339,45 +365,50 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
     CyIntEnable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* usb arb interrupt enable */
         USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
         CyIntEnable(USBFS_ARB_VECT_NUM);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Arbiter configuration for DMA transfers */
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /*Set cfg cmplt this rises DMA request when the full configuration is done */
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+                /* Init interrupt which handles verification of the successful DMA transaction */
+                USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+                USBFS_EP17_DMA_Done_SR_InterruptEnable();
+                USBFS_EP8_DMA_Done_SR_InterruptEnable();
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     USBFS_transferState = USBFS_TRANS_STATE_IDLE;
 
@@ -395,7 +426,7 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
             #else
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
-            #endif /* End USBFS_VDDD_MV < USBFS_3500MV */
+            #endif /*  USBFS_VDDD_MV < USBFS_3500MV */
             break;
     }
 
@@ -535,7 +566,7 @@ void USBFS_Stop(void)
 
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Disable the SIE */
     USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
@@ -551,28 +582,28 @@ void USBFS_Stop(void)
     CyIntDisable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     /* Clear all of the component data */
     USBFS_configuration = 0u;
@@ -768,7 +799,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
     *  No.
     *
     *******************************************************************************/
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                                     
     {
         uint16 src;
@@ -788,56 +819,56 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 src = HI16(CYDEV_PERIPH_BASE);
                 dst = HI16(pData);
             }
-        #endif  /* End C51 */
+        #endif  /*  C51 */
         switch(epNumber)
         {
             case USBFS_EP1:
                 #if(USBFS_DMA1_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA1_REMOVE */
+                #endif   /*  USBFS_DMA1_REMOVE */
                 break;
             case USBFS_EP2:
                 #if(USBFS_DMA2_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA2_REMOVE */
+                #endif   /*  USBFS_DMA2_REMOVE */
                 break;
             case USBFS_EP3:
                 #if(USBFS_DMA3_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA3_REMOVE */
+                #endif   /*  USBFS_DMA3_REMOVE */
                 break;
             case USBFS_EP4:
                 #if(USBFS_DMA4_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA4_REMOVE */
+                #endif   /*  USBFS_DMA4_REMOVE */
                 break;
             case USBFS_EP5:
                 #if(USBFS_DMA5_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA5_REMOVE */
+                #endif   /*  USBFS_DMA5_REMOVE */
                 break;
             case USBFS_EP6:
                 #if(USBFS_DMA6_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA6_REMOVE */
+                #endif   /*  USBFS_DMA6_REMOVE */
                 break;
             case USBFS_EP7:
                 #if(USBFS_DMA7_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA7_REMOVE */
+                #endif   /*  USBFS_DMA7_REMOVE */
                 break;
             case USBFS_EP8:
                 #if(USBFS_DMA8_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA8_REMOVE */
+                #endif   /*  USBFS_DMA8_REMOVE */
                 break;
             default:
                 /* Do not support EP0 DMA transfers */
@@ -846,6 +877,10 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
         if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
         {
             USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+            #endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
         }
     }
 
@@ -879,11 +914,74 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 CyDmaTdFree(USBFS_DmaTd[i]);
                 USBFS_DmaTd[i] = DMA_INVALID_TD;
             }
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+                {
+                    CyDmaTdFree(USBFS_DmaNextTd[i]);
+                    USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+                }
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
             i++;
         }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
     }
 
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_LoadNextInEP
+    ********************************************************************************
+    *
+    * Summary:
+    *  This internal function is used for IN endpoint DMA reconfiguration in
+    *  Auto DMA mode.
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number.
+    *  mode:   0 - Configure DMA to send the the rest of data.
+    *          1 - Configure DMA to repeat 2 last bytes of the first burst.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) 
+    {
+        reg16 *convert;
+
+        if(mode == 0u)
+        {
+            /* Configure DMA to send the the rest of data */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                            USBFS_DMA_BYTES_PER_BURST));
+            USBFS_inBufFull[epNumber] = 1u;
+        }
+        else
+        {
+            /* Configure DMA to repeat 2 last bytes of the first burst. */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert,  LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                   USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+        }
+
+        /* CyDmaChSetInitialTd API is optimised to init TD */
+        CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -891,8 +989,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
 ********************************************************************************
 *
 * Summary:
-*  Loads and enables the specified USB data endpoint for an IN interrupt or bulk
-*  transfer.
+*  Loads and enables the specified USB data endpoint for an IN transfer.
 *
 * Parameters:
 *  epNumber: Contains the data endpoint number.
@@ -916,7 +1013,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
     {
@@ -929,7 +1026,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             {
                 length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Set the count and data toggle */
         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
@@ -950,15 +1047,15 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
         #else
             /* Init DMA if it was not initialized */
-            if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+            if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-            if((pData != NULL) && (length > 0u))
+            if ((pData != NULL) && (length > 0u))
             {
                 /* Enable DMA in mode2 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
@@ -978,16 +1075,37 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 /* When zero-length packet - write the Mode register directly */
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            if(pData != NULL)
+            if (pData != NULL)
             {
                 /* Enable DMA in mode3 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                USBFS_inLength[epNumber] = length;
+                USBFS_inDataPointer[epNumber] = pData;
+                /* Configure DMA to send the data only for the first burst */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+                    (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+                    USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+                /* The second TD will be executed only when the first one fails.
+                *  The intention of this TD is to generate NRQ interrupt
+                *  and repeat 2 last bytes of the first burst.
+                */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+                                               USBFS_DmaNextTd[epNumber],
+                                               USBFS_epX_TD_TERMOUT_EN[epNumber]);
+                /* Configure DmaNextTd to clear Data ready status */
+                (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber],  LO16((uint32)&clearInDataRdyStatus),
+                                                                LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+            #else /* Configure DMA to send all data*/
                 (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
                                                USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
                 (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
                 /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
                 (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
                 /* Enable the DMA */
@@ -999,8 +1117,28 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
                 if(length > 0u)
                 {
+                #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                    USBFS_inLength[epNumber] = length;
+                    USBFS_inBufFull[epNumber] = 0u;
+                    (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+                    /* Configure DMA to send the data only for the first burst */
+                    (void) CyDmaTdSetConfiguration(
+                        USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+                        USBFS_DMA_BYTES_PER_BURST : length,
+                        USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+                    (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+                                             LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+                    /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+                    (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+                    /* Enable the DMA */
+                    (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                    (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+                #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
                     /* Set Data ready status, This will generate DMA request */
-                    * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #ifndef USBFS_MANUAL_IN_EP_ARM
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #endif  /* USBFS_MANUAL_IN_EP_ARM */
                     /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
                 }
                 else
@@ -1009,8 +1147,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                     CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
                 }
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
     }
 }
 
@@ -1047,10 +1184,10 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 xferCount;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
     {
@@ -1064,7 +1201,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 length = xferCount;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         #if(USBFS_EP_MM == USBFS__EP_MANUAL)
             /* Copy the data using the arbiter data register */
@@ -1081,7 +1218,8 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             /* Enable DMA in mode2 for transferring data */
@@ -1097,7 +1235,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /* Enable DMA in mode3 for transferring data */
@@ -1112,7 +1250,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
             (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     }
     else
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h
index e178fc2a..08a00eac 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: USBFS.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,6 +20,11 @@
 #include "cyfitter.h"
 #include "CyLib.h"
 
+/*  User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
 
 /***************************************
 * Conditional Compilation Parameters
@@ -28,7 +33,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component USBFS_v2_60 requires cy_boot v3.0 or later
+    #error Component USBFS_v2_80 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -47,7 +52,7 @@
 #else
     #define USBFS_DATA
     #define USBFS_XDATA
-#endif /* End __C51__ */
+#endif /*  __C51__ */
 #define USBFS_NULL       NULL
 
 
@@ -105,6 +110,7 @@
 #define USBFS_EP8_ISR_REMOVE                 (1u)
 #define USBFS_EP_MM                          (0u)
 #define USBFS_EP_MA                          (0u)
+#define USBFS_EP_DMA_AUTO_OPT                (0u)
 #define USBFS_DMA1_REMOVE                    (1u)
 #define USBFS_DMA2_REMOVE                    (1u)
 #define USBFS_DMA3_REMOVE                    (1u)
@@ -226,7 +232,7 @@ void   USBFS_Resume(void) ;
 #endif  /* USBFS_ENABLE_FWSN_STRING */
 #if (USBFS_MON_VBUS == 1u)
     uint8  USBFS_VBusPresent(void) ;
-#endif /* End USBFS_MON_VBUS */
+#endif /*  USBFS_MON_VBUS */
 
 #if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
@@ -234,19 +240,24 @@ void   USBFS_Resume(void) ;
     void USBFS_CyBtldrCommStart(void) ;
     void USBFS_CyBtldrCommStop(void) ;
     void USBFS_CyBtldrCommReset(void) ;
-    cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
-    cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommRead       (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
 
-    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER      (64u)    /* EP 1 OUT */
-    #define USBFS_BTLDR_SIZEOF_READ_BUFFER       (64u)    /* EP 2 IN */
-    #define USBFS_BTLDR_MAX_PACKET_SIZE          USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+    #define USBFS_BTLDR_OUT_EP      (0x01u)
+    #define USBFS_BTLDR_IN_EP       (0x02u)
+
+    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER  (64u)   /* EP 1 OUT */
+    #define USBFS_BTLDR_SIZEOF_READ_BUFFER   (64u)   /* EP 2 IN  */
+    #define USBFS_BTLDR_MAX_PACKET_SIZE      USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+    #define USBFS_BTLDR_WAIT_1_MS            (1u)    /* Time Out quantity equal 1mS */
 
     /* These defines active if used USBFS interface as an
     *  IO Component for bootloading. When Custom_Interface selected
     *  in Bootloder configuration as the IO Component, user must
-    *  provide these functions
+    *  provide these functions.
     */
     #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
         #define CyBtldrCommStart        USBFS_CyBtldrCommStart
@@ -256,13 +267,13 @@ void   USBFS_Resume(void) ;
         #define CyBtldrCommRead         USBFS_CyBtldrCommRead
     #endif  /*End   CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP  */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP  */
 
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                     ;
     void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL) */
 
 #if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
     void USBFS_MIDI_EP_Init(void) ;
@@ -277,7 +288,7 @@ void   USBFS_Resume(void) ;
         void USBFS_MIDI_OUT_EP_Service(void) ;
     #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
 
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */
+#endif /*  USBFS_ENABLE_MIDI_API != 0u */
 
 /* Renamed Functions for backward compatibility.
 *  Should not be used in new designs.
@@ -490,10 +501,10 @@ void   USBFS_Resume(void) ;
 #define USBFS_EP_USAGE_TYPE_RESERVED         (0x30u)
 #define USBFS_EP_USAGE_TYPE_MASK             (0x30u)
 
-/* Endpoint Status defines */
+/* point Status defines */
 #define USBFS_EP_STATUS_LENGTH               (0x02u)
 
-/* Endpoint Device defines */
+/* point Device defines */
 #define USBFS_DEVICE_STATUS_LENGTH           (0x02u)
 
 #define USBFS_STATUS_LENGTH_MAX \
@@ -520,14 +531,60 @@ void   USBFS_Resume(void) ;
     /* DMA manual mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (0u)
     #define USBFS_DMA_REQUEST_PER_BURST      (0u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
     /* DMA automatic mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (32u)
+    #define USBFS_DMA_BYTES_REPEAT           (2u)
     /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes  44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
     #define USBFS_DMA_BUF_SIZE               (0x55u)
     #define USBFS_DMA_REQUEST_PER_BURST      (1u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+    #if(USBFS_DMA1_REMOVE == 0u)
+        #define USBFS_ep1_TD_TERMOUT_EN      USBFS_ep1__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep1_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA1_REMOVE == 0u */
+    #if(USBFS_DMA2_REMOVE == 0u)
+        #define USBFS_ep2_TD_TERMOUT_EN      USBFS_ep2__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep2_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA2_REMOVE == 0u */
+    #if(USBFS_DMA3_REMOVE == 0u)
+        #define USBFS_ep3_TD_TERMOUT_EN      USBFS_ep3__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep3_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA3_REMOVE == 0u */
+    #if(USBFS_DMA4_REMOVE == 0u)
+        #define USBFS_ep4_TD_TERMOUT_EN      USBFS_ep4__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep4_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA4_REMOVE == 0u */
+    #if(USBFS_DMA5_REMOVE == 0u)
+        #define USBFS_ep5_TD_TERMOUT_EN      USBFS_ep5__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep5_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA5_REMOVE == 0u */
+    #if(USBFS_DMA6_REMOVE == 0u)
+        #define USBFS_ep6_TD_TERMOUT_EN      USBFS_ep6__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep6_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA6_REMOVE == 0u */
+    #if(USBFS_DMA7_REMOVE == 0u)
+        #define USBFS_ep7_TD_TERMOUT_EN      USBFS_ep7__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep7_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA7_REMOVE == 0u */
+    #if(USBFS_DMA8_REMOVE == 0u)
+        #define USBFS_ep8_TD_TERMOUT_EN      USBFS_ep8__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep8_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA8_REMOVE == 0u */
+
+    #define     USBFS_EP17_SR_MASK           (0x7fu)
+    #define     USBFS_EP8_SR_MASK            (0x03u)
+
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
 /* DIE ID string descriptor defines */
 #if defined(USBFS_ENABLE_IDSN_STRING)
@@ -812,7 +869,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #if(!CY_PSOC5LP)
     #define USBFS_USBIO_CR2_PTR      (  (reg8 *) USBFS_USB__USBIO_CR2)
     #define USBFS_USBIO_CR2_REG      (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /* End CY_PSOC5LP */
+#endif /*  CY_PSOC5LP */
 
 #define USBFS_DIE_ID             CYDEV_FLSHID_CUST_TABLES_BASE
 
@@ -838,8 +895,8 @@ extern volatile uint8 USBFS_deviceStatus;
     #else
         #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
         #define USBFS_VBUS_MASK          (0x01u)
-    #endif /* End USBFS_EXTERN_VBUS == 0u */
-#endif /* End USBFS_MON_VBUS */
+    #endif /*  USBFS_EXTERN_VBUS == 0u */
+#endif /*  USBFS_MON_VBUS */
 
 /* Renamed Registers for backward compatibility.
 *  Should not be used in new designs.
@@ -1017,7 +1074,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
     #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
     #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /* End CYDEV_CHIP_DIE_EXPECT */
+#endif /*  CYDEV_CHIP_DIE_EXPECT */
 
 
 /***************************************
@@ -1138,6 +1195,8 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_ARB_EPX_CFG_CRC_BYPASS     (0x04u)
 #define USBFS_ARB_EPX_CFG_DMA_REQ        (0x02u)
 #define USBFS_ARB_EPX_CFG_IN_DATA_RDY    (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT        (USBFS_ARB_EPX_CFG_RESET | \
+                                                     USBFS_ARB_EPX_CFG_CRC_BYPASS)
 
 #define USBFS_ARB_EPX_SR_IN_BUF_FULL     (0x01u)
 #define USBFS_ARB_EPX_SR_DMA_GNT         (0x02u)
@@ -1153,7 +1212,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_ARB_EPX_INT_MASK           (0x1Du)
 #else
     #define USBFS_ARB_EPX_INT_MASK           (0x1Fu)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 #define USBFS_ARB_INT_MASK       (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
                                             (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
                                             (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
@@ -1190,7 +1249,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_DYN_RECONFIG_RDY_STS       (0x10u)
 
 
-#endif /* End CY_USBFS_USBFS_H */
+#endif /*  CY_USBFS_USBFS_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
old mode 100755
new mode 100644
index afae8fad..6bb45afa
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dm_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dm_DM_STRONG     Strong Drive 
+*  USBFS_Dm_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dm_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dm_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dm_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dm_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dm_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dm_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
old mode 100755
new mode 100644
index c1aa9b99..5166935a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
old mode 100755
new mode 100644
index bc4f686d..faf08704
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dm_0		USBFS_Dm__0__PC
+#define USBFS_Dm_0		(USBFS_Dm__0__PC)
 
 #endif /* End Pins USBFS_Dm_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
old mode 100755
new mode 100644
index 304d5d61..7121119d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dp_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dp_DM_STRONG     Strong Drive 
+*  USBFS_Dp_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dp_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dp_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dp_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dp_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dp_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dp_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
old mode 100755
new mode 100644
index 2d03ad93..fb0a19c0
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
old mode 100755
new mode 100644
index b77c3b9a..5268950d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dp_0		USBFS_Dp__0__PC
+#define USBFS_Dp_0		(USBFS_Dp__0__PC)
 
 #endif /* End Pins USBFS_Dp_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c
old mode 100755
new mode 100644
index cec388be..2cd1304a
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB AUDIO Class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,9 +21,9 @@
 
 #include "USBFS_audio.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -52,7 +53,7 @@
                                                                                   USBFS_VOL_MAX_MSB};
     volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,
                                                                                      USBFS_VOL_RES_MSB};
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+#endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
 
 /*******************************************************************************
@@ -93,17 +94,18 @@
 uint8 USBFS_DispatchAUDIOClassRqst(void) 
 {
     uint8 requestHandled = USBFS_FALSE;
+    uint8 bmRequestType  = CY_GET_REG8(USBFS_bmRequestType);
 
     #if defined(USBFS_ENABLE_AUDIO_STREAMING)
         uint8 epNumber;
         epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;
-    #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+    #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
-    if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
+
+    if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
     {
         /* Control Read */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
             /* Endpoint */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -112,12 +114,12 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlRead();
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_READ_REQUESTS` Place other request handler here */
 
@@ -127,8 +129,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -140,7 +141,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */
 
                         /* `#END` */
-                        
+
                          /* Entity ID Control Selector is MUTE */
                         USBFS_currentTD.wCount = 1u;
                         USBFS_currentTD.pData  = &USBFS_currentMute;
@@ -199,7 +200,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         USBFS_currentTD.wCount = 0u;
                         requestHandled   = USBFS_InitControlWrite();
 
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
 
@@ -213,27 +214,25 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
         {   /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \
-                                                                                    USBFS_RQST_DIR_H2D)
+    else
     {
         /* Control Write */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
-            /* Endpoint */
+            /* point */
             switch (CY_GET_REG8(USBFS_bRequest))
             {
                 case USBFS_SET_CUR:
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlWrite();
                         USBFS_frequencyChanged = epNumber;
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
 
@@ -243,8 +242,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -279,7 +277,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
                         /* `#END` */
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
 
@@ -290,17 +288,14 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
             }
         }
         else
-        {   /* USBFS_RQST_RCPT_OTHER */
+        {
+            /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else
-    {   /* requestHandled is initialized as FALSE by default */
-    }
 
     return(requestHandled);
 }
 
-
 #endif /* USER_SUPPLIED_AUDIO_HANDLER */
 
 
@@ -312,7 +307,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_AUDIO_CLASS*/
+#endif  /*  USBFS_ENABLE_AUDIO_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h
old mode 100755
new mode 100644
index 1e6186bf..0cae2dc9
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -45,7 +48,7 @@
 #define USBFS_GET_MEM                    (0x85u)
 #define USBFS_GET_STAT                   (0xFFu)
 
-/* Endpoint Control Selectors (AUDIO Table A-19) */
+/* point Control Selectors (AUDIO Table A-19) */
 #define USBFS_EP_CONTROL_UNDEFINED       (0x00u)
 #define USBFS_SAMPLING_FREQ_CONTROL      (0x01u)
 #define USBFS_PITCH_CONTROL              (0x02u)
@@ -89,7 +92,7 @@ extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];
 
-#endif /* End CY_USBFS_USBFS_audio_H */
+#endif /*  CY_USBFS_USBFS_audio_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c
old mode 100755
new mode 100644
index 28430575..75b91270
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_boot.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Boot loader API for USBFS Component.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,23 +20,11 @@
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
 
 
-/***************************************
-*    Bootloader defines
-***************************************/
-
-#define USBFS_CyBtLdrStarttimer(X, T)         {USBFS_universalTime = T * 10; X = 0u;}
-#define USBFS_CyBtLdrChecktimer(X)            ((X++ < USBFS_universalTime) ? 1u : 0u)
-
-#define USBFS_BTLDR_OUT_EP      (0x01u)
-#define USBFS_BTLDR_IN_EP       (0x02u)
-
-
 /***************************************
 *    Bootloader Variables
 ***************************************/
 
-static uint16 USBFS_universalTime;
-static uint8 USBFS_started = 0u;
+static uint8  USBFS_started = 0u;
 
 
 /*******************************************************************************
@@ -68,7 +56,6 @@ void USBFS_CyBtldrCommStart(void)
 
     /* USB component started, the correct enumeration will be checked in first Read operation */
     USBFS_started = 1u;
-
 }
 
 
@@ -100,13 +87,13 @@ void USBFS_CyBtldrCommStop(void)
 *  Resets the receive and transmit communication Buffers.
 *
 * Parameters:
-*  None.
+*  None
 *
 * Return:
-*  None.
+*  None
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
 void USBFS_CyBtldrCommReset(void) 
@@ -135,39 +122,39 @@ void USBFS_CyBtldrCommReset(void)
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    uint16 time;
-    cystatus status;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
     /* Enable IN transfer */
     USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);
 
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
-
     /* Wait for the master to read it. */
-    while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+    while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&
+           (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)
     {
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
     else
     {
         *count = size;
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
 
-    return(status);
+    return(retCode);
 }
 
 
@@ -193,70 +180,77 @@ cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    cystatus status;
-    uint16 time;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
-    if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
+    if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
     {
         size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;
     }
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
 
     /* Wait on enumeration in first time */
-    if(USBFS_started)
+    if (0u != USBFS_started)
     {
         /* Wait for Device to enumerate */
-        while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))
+        while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))
         {
-            CyDelay(1u); /* 1ms delay */
+            CyDelay(USBFS_BTLDR_WAIT_1_MS);
+            timeoutMs--;
         }
+
         /* Enable first OUT, if enumeration complete */
-        if(USBFS_GetConfiguration())
+        if (0u != USBFS_GetConfiguration())
         {
-            USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
+            (void) USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
             USBFS_CyBtldrCommReset();
             USBFS_started = 0u;
         }
     }
     else /* Check for configuration changes, has been done by Host */
     {
-        if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */
+        if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */
         {
-            if(USBFS_GetConfiguration() != 0u)   /* Init OUT endpoints when device reconfigured */
+            if (0u != USBFS_GetConfiguration())   /* Init OUT endpoints when device reconfigured */
             {
                 USBFS_CyBtldrCommReset();
             }
         }
     }
+
+    timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */
+
     /* Wait on next packet */
     while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+          (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     /* OUT EP has completed */
     if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)
     {
         *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
     else
     {
         *count = 0u;
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
-    return(status);
+
+    return(retCode);
 }
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
old mode 100755
new mode 100644
index 82951c8a..63ebf120
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  USB HID Class request handler.
+*  USB CDC class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
 *
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -26,7 +27,13 @@
 *    CDC Variables
 ***************************************/
 
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =
+{
+    0x00u, 0xC2u, 0x01u, 0x00u,     /* Data terminal rate 115200 */
+    0x00u,                          /* 1 Stop bit */
+    0x00u,                          /* None parity */
+    0x08u                           /* 8 data bits */
+};
 volatile uint8 USBFS_lineChanged;
 volatile uint16 USBFS_lineControlBitmap;
 volatile uint8 USBFS_cdc_data_in_ep;
@@ -36,7 +43,9 @@ volatile uint8 USBFS_cdc_data_out_ep;
 /***************************************
 *     Static Function Prototypes
 ***************************************/
-static uint16 USBFS_StrLen(const char8 string[]) ;
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
+    static uint16 USBFS_StrLen(const char8 string[]) ;
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */
 
 
 /***************************************
@@ -138,7 +147,6 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 ***************************************/
 #if (USBFS_ENABLE_CDC_CLASS_API != 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_CDC_Init
     ********************************************************************************
@@ -173,14 +181,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a specified number of bytes from the location specified by a
-    *  pointer to the PC.
+    *  This function sends a specified number of bytes from the location specified
+    *  by a pointer to the PC. The USBFS_CDCIsReady() function should be
+    *  called before sending new data, to be sure that the previous data has
+    *  finished sending.
+    *  If the last sent packet is less than maximum packet size the USB transfer
+    *  of this short packet will identify the end of the segment. If the last sent
+    *  packet is exactly maximum packet size, it shall be followed by a zero-length
+    *  packet (which is a short packet) to assure the end of segment is properly
+    *  identified. To send zero-length packet, use USBFS_PutData() API
+    *  with length parameter set to zero.
     *
     * Parameters:
     *  pData: pointer to the buffer containing data to be sent.
     *  length: Specifies the number of bytes to send from the pData
     *  buffer. Maximum length will be limited by the maximum packet
-    *  size for the endpoint.
+    *  size for the endpoint. Data will be lost if length is greater than Max
+    *  Packet Size.
     *
     * Return:
     *  None.
@@ -239,10 +256,15 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a null terminated string to the PC.
+    *  This function sends a null terminated string to the PC. This function will
+    *  block if there is not enough memory to place the whole string. It will block
+    *  until the entire string has been written to the transmit buffer.
+    *  The USBUART_CDCIsReady() function should be called before sending data with
+    *  a new call to USBFS_PutString(), to be sure that the previous data
+    *  has finished sending.
     *
     * Parameters:
-    *  string: pointer to the string to be sent to the PC
+    *  string: pointer to the string to be sent to the PC.
     *
     * Return:
     *  None.
@@ -254,41 +276,44 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     * Reentrant:
     *  No.
     *
-    * Theory:
-    *  This function will block if there is not enough memory to place the whole
-    *  string, it will block until the entire string has been written to the
-    *  transmit buffer.
-    *
     *******************************************************************************/
     void USBFS_PutString(const char8 string[]) 
     {
-        uint16 str_length;
-        uint16 send_length;
-        uint16 buf_index = 0u;
+        uint16 strLength;
+        uint16 sendLength;
+        uint16 bufIndex = 0u;
 
         /* Get length of the null terminated string */
-        str_length = USBFS_StrLen(string);
+        strLength = USBFS_StrLen(string);
         do
         {
             /* Limits length to maximum packet size for the EP */
-            send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
-                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;
+            sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
+                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;
              /* Enable IN transfer */
-            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);
-            str_length -= send_length;
+            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);
+            strLength -= sendLength;
 
-            /* If more data are present to send */
-            if(str_length > 0u)
+            /* If more data are present to send or full packet was sent */
+            if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))
             {
-                buf_index += send_length;
+                bufIndex += sendLength;
                 /* Wait for the Host to read it. */
                 while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==
                                           USBFS_IN_BUFFER_FULL)
                 {
                     ;
                 }
+                /* If the last sent packet is exactly maximum packet size,
+                *  it shall be followed by a zero-length packet to assure the
+                *  end of segment is properly identified by the terminal.
+                */
+                if(strLength == 0u)
+                {
+                    USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);
+                }
             }
-        }while(str_length > 0u);
+        }while(strLength > 0u);
     }
 
 
@@ -357,12 +382,17 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  This function returns the number of bytes that were received from the PC.
+    *  The returned length value should be passed to USBFS_GetData() as
+    *  a parameter to read all received data. If all of the received data is not
+    *  read at one time by the USBFS_GetData() API, the unread data will
+    *  be lost.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  Returns the number of received bytes.
+    *  Returns the number of received bytes. The maximum amount of received data at
+    *  a time is limited by the maximum packet size for the endpoint.
     *
     * Global variables:
     *   USBFS_cdc_data_out_ep: CDC OUT endpoint number used.
@@ -370,12 +400,16 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *******************************************************************************/
     uint16 USBFS_GetCount(void) 
     {
-        uint16 bytesCount = 0u;
+        uint16 bytesCount;
 
         if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)
         {
             bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);
         }
+        else
+        {
+            bytesCount = 0u;
+        }
 
         return(bytesCount);
     }
@@ -387,9 +421,9 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  Returns a nonzero value if the component received data or received
-    *  zero-length packet. The GetAll() or GetData() API should be called to read
-    *  data from the buffer and re-init OUT endpoint even when zero-length packet
-    *  received.
+    *  zero-length packet. The USBFS_GetAll() or
+    *  USBFS_GetData() API should be called to read data from the buffer
+    *  and re-init OUT endpoint even when zero-length packet received.
     *
     * Parameters:
     *  None.
@@ -413,17 +447,19 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Returns a nonzero value if the component is ready to send more data to the
-    *  PC. Otherwise returns zero. Should be called before sending new data to
-    *  ensure the previous data has finished sending.This function returns the
-    *  number of bytes that were received from the PC.
+    *  This function returns a nonzero value if the component is ready to send more
+    *  data to the PC; otherwise, it returns zero. The function should be called
+    *  before sending new data when using any of the following APIs:
+    *  USBFS_PutData(),USBFS_PutString(),
+    *  USBFS_PutChar or USBFS_PutCRLF(),
+    *  to be sure that the previous data has finished sending.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If the buffer can accept new data then this function returns a nonzero value.
-    *  Otherwise zero is returned.
+    *  If the buffer can accept new data, this function returns a nonzero value.
+    *  Otherwise, it returns zero.
     *
     * Global variables:
     *   USBFS_cdc_data_in_ep: CDC IN endpoint number used.
@@ -440,10 +476,12 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Gets a specified number of bytes from the input buffer and places it in a
-    *  data array specified by the passed pointer.
-    *  USBFS_DataIsReady() API should be called before, to be sure
-    *  that data is received from the Host.
+    *  This function gets a specified number of bytes from the input buffer and
+    *  places them in a data array specified by the passed pointer.
+    *  The USBFS_DataIsReady() API should be called first, to be sure
+    *  that data is received from the host. If all received data will not be read at
+    *  once, the unread data will be lost. The USBFS_GetData() API should
+    *  be called to get the number of bytes that were received.
     *
     * Parameters:
     *  pData: Pointer to the data array where data will be placed.
@@ -502,7 +540,8 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Reads one byte of received data from the buffer.
+    *  This function reads one byte of received data from the buffer. If more than
+    *  one byte has been received from the host, the rest of the data will be lost.
     *
     * Parameters:
     *  None.
@@ -531,17 +570,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  This function returns clear on read status of the line.
+    *  This function returns clear on read status of the line. It returns not zero
+    *  value when the host sends updated coding or control information to the
+    *  device. The USBFS_GetDTERate(), USBFS_GetCharFormat()
+    *  or USBFS_GetParityType() or USBFS_GetDataBits() API
+    *  should be called to read data coding information.
+    *  The USBFS_GetLineControl() API should be called to read line
+    *  control information.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not
-    *  zero value returned. Otherwise zero is returned.
+    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it
+    *  returns a nonzero value. Otherwise, it returns zero.
     *
     * Global variables:
-    *  USBFS_transferState - it is checked to be sure then OUT data
+    *  USBFS_transferState: it is checked to be sure then OUT data
     *    phase has been complete, and data written to the lineCoding or Control
     *    Bitmap buffer.
     *  USBFS_lineChanged: used as a flag to be aware that Host has been
@@ -689,7 +734,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
         return(USBFS_lineControlBitmap);
     }
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API*/
 
 
 /*******************************************************************************
@@ -700,7 +745,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS*/
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
old mode 100755
new mode 100644
index 334bc589..11c94d05
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
@@ -1,13 +1,16 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component.
+*  Header File for the USBFS component.
 *  Contains CDC class prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,7 +44,7 @@
     uint8 USBFS_GetParityType(void) ;
     uint8 USBFS_GetDataBits(void) ;
     uint16 USBFS_GetLineControl(void) ;
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API */
 
 
 /***************************************
@@ -86,7 +89,7 @@ extern volatile uint16 USBFS_lineControlBitmap;
 extern volatile uint8 USBFS_cdc_data_in_ep;
 extern volatile uint8 USBFS_cdc_data_out_ep;
 
-#endif /* End CY_USBFS_USBFS_cdc_H */
+#endif /*  CY_USBFS_USBFS_cdc_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
old mode 100755
new mode 100644
index c3477c28..9bbefb9b
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
@@ -1,12 +1,12 @@
 ;******************************************************************************
 ; File Name: USBFS_cdc.inf
-; Version 2.60
+; Version 2.80
 ;
 ; Description:
 ;  Windows USB CDC setup file for USBUART Device.
 ;
 ;******************************************************************************
-; Copyright 2007-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2007-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c
old mode 100755
new mode 100644
index 7bbd8d11..a9801ead
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_cls.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Class request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -57,8 +57,8 @@ uint8 USBFS_DispatchClassRqst(void)
             break;
         case USBFS_RQST_RCPT_EP:         /* Class-specific request directed to the endpoint */
             /* Find related interface to the endpoint, wIndexLo contain EP number */
-            interfaceNumber =
-                USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;
+            interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &
+                              USBFS_DIR_UNUSED].interface;
             break;
         default:    /* RequestHandled is initialized as FALSE by default */
             break;
@@ -74,7 +74,7 @@ uint8 USBFS_DispatchClassRqst(void)
         case USBFS_CLASS_AUDIO:
             #if defined(USBFS_ENABLE_AUDIO_CLASS)
                 requestHandled = USBFS_DispatchAUDIOClassRqst();
-            #endif /* USBFS_ENABLE_HID_CLASS */
+            #endif /* USBFS_CLASS_AUDIO */
             break;
         case USBFS_CLASS_CDC:
             #if defined(USBFS_ENABLE_CDC_CLASS)
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
index 00c65059..3144a039 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_descr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB descriptors and storage.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,7 @@
 
 /*****************************************************************************
 *  User supplied descriptors.  If you want to specify your own descriptors,
-*  remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and
-*  add your descriptors.
+*  define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.
 *****************************************************************************/
 /* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c
old mode 100755
new mode 100644
index e78a41b2..282c938d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_drv.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Endpoint 0 Driver for the USBFS Component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c
old mode 100755
new mode 100644
index cd88e929..b3cd8e33
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_episr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Data endpoint Interrupt Service Routines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -16,9 +16,13 @@
 
 #include "USBFS.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 
 /***************************************
@@ -48,7 +52,8 @@
     ******************************************************************************/
     CY_ISR(USBFS_EP_1_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT)  && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -56,7 +61,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -72,23 +78,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &
                                                                     (uint8)~USBFS_SIE_EP_INT_EP1_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP1)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP1_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP1_ISR_REMOVE */
+#endif   /*  USBFS_EP1_ISR_REMOVE */
 
 
 #if(USBFS_EP2_ISR_REMOVE == 0u)
@@ -109,7 +117,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_2_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -117,7 +126,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -133,23 +143,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP2_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP2)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP2_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP2_ISR_REMOVE */
+#endif   /*  USBFS_EP2_ISR_REMOVE */
 
 
 #if(USBFS_EP3_ISR_REMOVE == 0u)
@@ -170,7 +182,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_3_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -178,7 +191,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -194,23 +208,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP3_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP3)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP3_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP3_ISR_REMOVE */
+#endif   /*  USBFS_EP3_ISR_REMOVE */
 
 
 #if(USBFS_EP4_ISR_REMOVE == 0u)
@@ -231,7 +247,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_4_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -239,7 +256,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -255,23 +273,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP4_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP4)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP4_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP4_ISR_REMOVE */
+#endif   /*  USBFS_EP4_ISR_REMOVE */
 
 
 #if(USBFS_EP5_ISR_REMOVE == 0u)
@@ -292,7 +312,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_5_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -300,7 +321,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -316,22 +338,24 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP5_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP5)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP5_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
-#endif   /* End USBFS_EP5_ISR_REMOVE */
+#endif   /*  USBFS_EP5_ISR_REMOVE */
 
 
 #if(USBFS_EP6_ISR_REMOVE == 0u)
@@ -352,7 +376,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_6_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -360,7 +385,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -376,23 +402,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP6_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP6)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP6_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP6_ISR_REMOVE */
+#endif   /*  USBFS_EP6_ISR_REMOVE */
 
 
 #if(USBFS_EP7_ISR_REMOVE == 0u)
@@ -413,7 +441,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_7_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -421,7 +450,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -437,23 +467,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP7_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP7)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP7_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP7_ISR_REMOVE */
+#endif   /*  USBFS_EP7_ISR_REMOVE */
 
 
 #if(USBFS_EP8_ISR_REMOVE == 0u)
@@ -474,7 +506,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_8_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -482,7 +515,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -498,23 +532,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP8_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP8)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP8_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP8_ISR_REMOVE */
+#endif   /*  USBFS_EP8_ISR_REMOVE */
 
 
 /*******************************************************************************
@@ -611,6 +647,17 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                         /* Clear Data ready status */
                         *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=
                                                                     (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                        #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                            /* Setup common area DMA with rest of the data */
+                            if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)
+                            {
+                                USBFS_LoadNextInEP(ep, 0u);
+                            }
+                            else
+                            {
+                                USBFS_inBufFull[ep] = 1u;
+                            }
+                        #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
                         /* Write the Mode register */
                         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);
                         #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)
@@ -618,7 +665,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                             {   /* Clear MIDI input pointer */
                                 USBFS_midiInPointer = 0u;
                             }
-                        #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                 }
                 /* (re)arm Out EP only for mode2 */
@@ -634,7 +681,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                                                                                     USBFS_EP[ep].epMode);
                         }
                     }
-                #endif /* End USBFS_EP_MM */
+                #endif /*  USBFS_EP_MM */
 
                 /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */
 
@@ -652,7 +699,82 @@ CY_ISR(USBFS_BUS_RESET_ISR)
         /* `#END` */
     }
 
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    /******************************************************************************
+    * Function Name: USBFS_EP_DMA_DONE_ISR
+    *******************************************************************************
+    *
+    * Summary:
+    *  Endpoint 1 DMA Done Interrupt Service Routine
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  None.
+    *
+    ******************************************************************************/
+    CY_ISR(USBFS_EP_DMA_DONE_ISR)
+    {
+        uint8 int8Status;
+        uint8 int17Status;
+        uint8 ep_status;
+        uint8 ep = USBFS_EP1;
+        uint8 ptr = 0u;
+
+        /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
+
+        /* `#END` */
+
+        /* Read clear on read status register with the EP source of interrupt */
+        int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;
+        int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;
+
+        while(int8Status != 0u)
+        {
+            while(int17Status != 0u)
+            {
+                if((int17Status & 1u) != 0u)  /* If EpX interrupt present */
+                {
+                    /* Read Endpoint Status Register */
+                    ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));
+                    if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&
+                        (USBFS_inBufFull[ep] == 0u))
+                    {
+                        /* `#START EP_DMA_DONE_USER_CODE` Place your code here */
+
+                        /* `#END` */
+
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
+                        /* repeat 2 last bytes to prefetch endpoint area */
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
+                                    USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);
+                        USBFS_LoadNextInEP(ep, 1);
+                        /* Set Data ready status, This will generate DMA request */
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    }
+                }
+                ptr += USBFS_EPX_CNTX_ADDR_OFFSET;               /* prepare pointer for next EP */
+                ep++;
+                int17Status >>= 1u;
+            }
+            int8Status >>= 1u;
+            if(int8Status != 0u)
+            {
+                /* Prepare pointer for EP8 */
+                ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+                ep = USBFS_EP8;
+                int17Status = int8Status & 0x01u;
+            }
+        }
+
+        /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
+
+        /* `#END` */
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c
old mode 100755
new mode 100644
index ba9fdf5b..fedf8b0b
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c
@@ -1,14 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_hid.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB HID Class request handler.
 *
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
+*
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -416,7 +419,7 @@ void USBFS_FindReport(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_HID_CLASS */
+#endif  /*  USBFS_ENABLE_HID_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h
old mode 100755
new mode 100644
index 9a6201c1..e802023f
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_hid.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -58,7 +61,7 @@ uint8 USBFS_GetProtocol(uint8 interface) ;
 #define USBFS_HID_GET_REPORT_OUTPUT      (0x02u)
 #define USBFS_HID_GET_REPORT_FEATURE     (0x03u)
 
-#endif /* End CY_USBFS_USBFS_hid_H */
+#endif /*  CY_USBFS_USBFS_hid_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c
old mode 100755
new mode 100644
index 1f0ce51a..be7060bf
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c
@@ -1,14 +1,18 @@
 /*******************************************************************************
 * File Name: USBFS_midi.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  MIDI Streaming request handler.
 *  This file contains routines for sending and receiving MIDI
 *  messages, and handles running status in both directions.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -60,15 +64,15 @@
         volatile uint16 USBFS_midiInPointer;                            /* Input endpoint buffer pointer */
     #else
         volatile uint8 USBFS_midiInPointer;                             /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */
     volatile uint8 USBFS_midi_in_ep;                                    /* Input endpoint number */
     uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];       /* Input endpoint buffer */
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
     volatile uint8 USBFS_midi_out_ep;                                   /* Output endpoint number */
     uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE];     /* Output endpoint buffer */
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event;            /* MIDI RX status structure */
@@ -79,8 +83,8 @@
         static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event;        /* MIDI RX status structure */
         static volatile uint8 USBFS_MIDI2_TxRunStat;                     /* MIDI Output running status */
         volatile uint8 USBFS_MIDI2_InqFlags;                             /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
 
 /***************************************
@@ -134,30 +138,30 @@ void USBFS_MIDI_EP_Init(void)
 {
     #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
        USBFS_midiInPointer = 0u;
-    #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
         #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
             /* Init DMA configurations for IN EP*/
             USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,
                                                                                 USBFS_MIDI_IN_BUFF_SIZE);
-                                                                                
-        #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+        #endif  /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
         #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
             /* Init DMA configurations for OUT EP*/
             (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,
                                                                                 USBFS_MIDI_OUT_BUFF_SIZE);
-        #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-    #endif  /* End USBFS__EP_DMAAUTO */
+        #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
+    #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
 
     #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
         USBFS_EnableOutEP(USBFS_midi_out_ep);
-    #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
     /* Initialize the MIDI port(s) */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
         USBFS_MIDI_Init();
-    #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 }
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
@@ -199,37 +203,43 @@ void USBFS_MIDI_EP_Init(void)
         #else
             uint8 outLength;
             uint8 outPointer;
-        #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */
+        #endif /*  USBFS_MIDI_OUT_BUFF_SIZE >=256 */
 
         uint8 dmaState = 0u;
 
         /* Service the USB MIDI output endpoint */
         if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)
         {
-            #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+            #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                 outLength = USBFS_GetEPCount(USBFS_midi_out_ep);
             #else
                 outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);
-            #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+            #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
             #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-                #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+                #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                     outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, outLength);
                 #else
                     outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, (uint16)outLength);
-                #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+                #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
                 #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                     do  /* wait for DMA transfer complete */
                     {
-                        (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
-                    }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-            #endif  /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+                        (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
+                    }
+                    while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
+                #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */
+
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
+
             if(dmaState != 0u)
             {
                 /* Suppress compiler warning */
             }
+
             if (outLength >= USBFS_EVENT_LENGTH)
             {
                 outPointer = 0u;
@@ -252,7 +262,7 @@ void USBFS_MIDI_EP_Init(void)
                         {
                             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                                 USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);
-                            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+                            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
                         }
                         else
                         {
@@ -260,7 +270,7 @@ void USBFS_MIDI_EP_Init(void)
 
                             /* `#END` */
                         }
-                    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+                    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
                     /* Process any local MIDI output functions */
                     USBFS_callbackLocalMidiEvent(
@@ -272,7 +282,7 @@ void USBFS_MIDI_EP_Init(void)
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /* Enable Out EP*/
                 USBFS_EnableOutEP(USBFS_midi_out_ep);
-            #endif  /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif  /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
         }
     }
 
@@ -322,12 +332,12 @@ void USBFS_MIDI_EP_Init(void)
             #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
                 /* rearm IN EP */
                 USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);
-            #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
 
             /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */
             #if(USBFS_EP_MM == USBFS__EP_MANUAL)
                 USBFS_midiInPointer = 0u;
-            #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
+            #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */
             }
         }
     }
@@ -370,7 +380,8 @@ void USBFS_MIDI_EP_Init(void)
             uint8 m2 = 0u;
             do
             {
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI1 input port for a complete event */
                     m1 = USBFS_MIDI1_GetEvent();
@@ -382,7 +393,8 @@ void USBFS_MIDI_EP_Init(void)
                 }
 
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI2 input port for a complete event */
                     m2 = USBFS_MIDI2_GetEvent();
@@ -392,11 +404,12 @@ void USBFS_MIDI_EP_Init(void)
                                                     USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);
                     }
                 }
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 
-            }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
-                   && ((m1 != 0u) || (m2 != 0u)) );
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            }while( (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&
+                    ((m1 != 0u) || (m2 != 0u)) );
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         /* Service the USB MIDI input endpoint */
         USBFS_MIDI_IN_EP_Service();
@@ -453,8 +466,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_DisableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_DisableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         if (USBFS_midiInPointer >
                     (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
@@ -481,15 +494,16 @@ void USBFS_MIDI_EP_Init(void)
                         (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                     {
                         USBFS_MIDI_IN_EP_Service();
-                        if (USBFS_midiInPointer >
-                            (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
+                        if(USBFS_midiInPointer >
+                          (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                         {
                             /* Error condition. HOST is not ready to receive this packet. */
                             retError = USBFS_TRUE;
                             break;
                         }
                     }
-                }while(ic > USBFS_EVENT_BYTE3);
+                }
+                while(ic > USBFS_EVENT_BYTE3);
 
                 if(retError == USBFS_FALSE)
                 {
@@ -507,8 +521,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_EnableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_EnableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         return (retError);
     }
@@ -712,7 +726,7 @@ void USBFS_MIDI_EP_Init(void)
             /* Change the priority of the UART TX interrupt */
             CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);
             CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
+        #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
 
         /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */
 
@@ -915,12 +929,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI1_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;
@@ -930,12 +945,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI1_UART_rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI1_UART_rxBufferWrite;
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary buffer pointer
@@ -948,7 +963,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /*  ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI1_UART_rxBuffer[rxBufferRead];
                     /* Increment pointer with a wrap */
@@ -965,11 +980,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI1_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                         MIDI1_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -984,11 +999,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI1_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1105,6 +1120,7 @@ void USBFS_MIDI_EP_Init(void)
         /* `#END` */
     }
 
+
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
 
 
@@ -1137,12 +1153,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI2_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;
@@ -1152,12 +1169,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI2_UART_rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI2_UART_rxBufferWrite;
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary output pointer to
@@ -1170,7 +1187,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI2_UART_rxBuffer[rxBufferRead];
                     rxBufferRead++;
@@ -1186,11 +1203,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI2_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                         MIDI2_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -1205,11 +1222,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI2_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1325,17 +1342,17 @@ void USBFS_MIDI_EP_Init(void)
 
         /* `#END` */
     }
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
-#endif  /* End (USBFS_ENABLE_MIDI_API != 0u) */
+#endif  /*  (USBFS_ENABLE_MIDI_API != 0u) */
 
 
 /* `#START MIDI_FUNCTIONS` Place any additional functions here */
 
 /* `#END` */
 
-#endif  /* End defined(USBFS_ENABLE_MIDI_STREAMING) */
+#endif  /*  defined(USBFS_ENABLE_MIDI_STREAMING) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h
old mode 100755
new mode 100644
index 5a720340..ad6e5d7b
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h
@@ -1,13 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_midi.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Header File for the USBFS MIDI module.
 *  Contains prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,7 +25,7 @@
 
 
 /***************************************
-*    Data Struct Definition
+*    Data Structure Definition
 ***************************************/
 
 /* The following structure is used to hold status information for
@@ -112,12 +116,13 @@ typedef struct
 #define USBFS_CUSTOM_UART_TX_PRIOR_NUM   (0x04u)
 #define USBFS_CUSTOM_UART_RX_PRIOR_NUM   (0x02u)
 
-#define USBFS_ISR_SERVICE_MIDI_OUT     \
+#define USBFS_ISR_SERVICE_MIDI_OUT         \
         ( (USBFS_ENABLE_MIDI_API != 0u) && \
-          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )
+          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))
 #define USBFS_ISR_SERVICE_MIDI_IN     \
         ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )
 
+
 /***************************************
 * External function references
 ***************************************/
@@ -132,13 +137,13 @@ void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     #include "MIDI1_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
     #include "MIDI2_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     #include <CyDmac.h>
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 
 
 /***************************************
@@ -159,8 +164,8 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         uint8 USBFS_MIDI2_GetEvent(void) ;
         void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])
                                                     ;
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 
 /***************************************
@@ -174,7 +179,7 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         extern volatile uint16 USBFS_midiInPointer;                       /* Input endpoint buffer pointer */
     #else
         extern volatile uint8 USBFS_midiInPointer;                        /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /*  USBFS_MIDI_IN_BUFF_SIZE >=256 */
     extern volatile uint8 USBFS_midi_in_ep;                               /* Input endpoint number */
     extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];  /* Input endpoint buffer */
 #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
@@ -188,13 +193,13 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
     extern volatile uint8 USBFS_MIDI1_InqFlags;                              /* Device inquiry flag */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
         extern volatile uint8 USBFS_MIDI2_InqFlags;                          /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
 
 
-#endif /* End CY_USBFS_USBFS_midi_H */
+#endif /*  CY_USBFS_USBFS_midi_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c
old mode 100755
new mode 100644
index 00c88f64..3540214e
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_pm.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This file provides Suspend/Resume APIs functionality.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -36,7 +36,6 @@ static USBFS_BACKUP_STRUCT  USBFS_backup;
 
 #if(USBFS_DP_ISR_REMOVE == 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_DP_Interrupt
     ********************************************************************************
@@ -119,7 +118,7 @@ void USBFS_RestoreConfig(void)
 ********************************************************************************
 *
 * Summary:
-*  This function disables the USBFS block and prepares for power donwn mode.
+*  This function disables the USBFS block and prepares for power down mode.
 *
 * Parameters:
 *  None.
@@ -145,7 +144,7 @@ void USBFS_Suspend(void)
 
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
         USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;
@@ -158,7 +157,7 @@ void USBFS_Suspend(void)
         /* Disable the SIE */
         USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;
 
-        CyDelayUs(0u);  /*~50ns delay */
+        CyDelayUs(0u);  /* ~50ns delay */
         /* Store mode and Disable VRegulator*/
         USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;
         USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;
@@ -181,16 +180,16 @@ void USBFS_Suspend(void)
     {
         USBFS_backup.enableState = 0u;
     }
+
     CyExitCriticalSection(enableInterrupts);
 
     /* Set the DP Interrupt for wake-up from sleep mode. */
     #if(USBFS_DP_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM,   &USBFS_DP_ISR);
+        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
         CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);
         CyIntClearPending(USBFS_DP_INTC_VECT_NUM);
         CyIntEnable(USBFS_DP_INTC_VECT_NUM);
     #endif /* (USBFS_DP_ISR_REMOVE == 0u) */
-
 }
 
 
@@ -223,7 +222,7 @@ void USBFS_Resume(void)
     {
         #if(USBFS_DP_ISR_REMOVE == 0u)
             CyIntDisable(USBFS_DP_INTC_VECT_NUM);
-        #endif /* End USBFS_DP_ISR_REMOVE */
+        #endif /*  USBFS_DP_ISR_REMOVE */
 
         /* Enable USB block */
         USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
@@ -245,18 +244,18 @@ void USBFS_Resume(void)
         /* Set the USBIO pull-up enable */
         USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
 
-        /* Reinit Arbiter configuration for DMA transfers */
+        /* Re-init Arbiter configuration for DMA transfers */
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-            /* usb arb interrupt enable */
+            /* Usb arb interrupt enable */
             USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
             #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /*Set cfg cmplt this rises DMA request when the full configuration is done */
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* STALL_IN_OUT */
         CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
@@ -268,8 +267,8 @@ void USBFS_Resume(void)
 
         /* Restore USB register settings */
         USBFS_RestoreConfig();
-
     }
+
     CyExitCriticalSection(enableInterrupts);
 }
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
index db14e05d..08bf742a 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: .h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This private file provides constants and parameter values for the
@@ -10,7 +10,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -77,7 +77,14 @@ extern volatile T_USBFS_TD USBFS_currentTD;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     extern uint8 USBFS_DmaChan[USBFS_MAX_EP];
     extern uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];
+    extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 extern volatile uint8 USBFS_ep0Toggle;
 extern volatile uint8 USBFS_lastPacketSize;
@@ -117,7 +124,7 @@ void USBFS_Config(uint8 clearAltSetting) ;
 void USBFS_ConfigAltChanged(void) ;
 void USBFS_ConfigReg(void) ;
 
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                             ;
 const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)
                                                             ;
@@ -130,56 +137,62 @@ uint8 USBFS_ValidateAlternateSetting(void) ;
 void USBFS_SaveConfig(void) ;
 void USBFS_RestoreConfig(void) ;
 
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
 #if defined(USBFS_ENABLE_IDSN_STRING)
     void USBFS_ReadDieID(uint8 descr[]) ;
 #endif /* USBFS_ENABLE_IDSN_STRING */
 
 #if defined(USBFS_ENABLE_HID_CLASS)
     uint8 USBFS_DispatchHIDClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_AUDIO_CLASS)
     uint8 USBFS_DispatchAUDIOClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_CDC_CLASS)
     uint8 USBFS_DispatchCDCClassRqst(void);
-#endif /* End USBFS_ENABLE_CDC_CLASS */
+#endif /*  USBFS_ENABLE_CDC_CLASS */
 
 CY_ISR_PROTO(USBFS_EP_0_ISR);
 #if(USBFS_EP1_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_1_ISR);
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /*  USBFS_EP1_ISR_REMOVE */
 #if(USBFS_EP2_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_2_ISR);
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /*  USBFS_EP2_ISR_REMOVE */
 #if(USBFS_EP3_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_3_ISR);
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /*  USBFS_EP3_ISR_REMOVE */
 #if(USBFS_EP4_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_4_ISR);
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /*  USBFS_EP4_ISR_REMOVE */
 #if(USBFS_EP5_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_5_ISR);
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /*  USBFS_EP5_ISR_REMOVE */
 #if(USBFS_EP6_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_6_ISR);
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /*  USBFS_EP6_ISR_REMOVE */
 #if(USBFS_EP7_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_7_ISR);
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /*  USBFS_EP7_ISR_REMOVE */
 #if(USBFS_EP8_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_8_ISR);
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /*  USBFS_EP8_ISR_REMOVE */
 CY_ISR_PROTO(USBFS_BUS_RESET_ISR);
 #if(USBFS_SOF_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_SOF_ISR);
-#endif /* End USBFS_SOF_ISR_REMOVE */
+#endif /*  USBFS_SOF_ISR_REMOVE */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     CY_ISR_PROTO(USBFS_ARB_ISR);
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 #if(USBFS_DP_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_DP_ISR);
-#endif /* End USBFS_DP_ISR_REMOVE */
-
+#endif /*  USBFS_DP_ISR_REMOVE */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 /***************************************
 * Request Handlers
@@ -193,6 +206,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    HID Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_HID_CLASS)
     void USBFS_FindReport(void) ;
     void USBFS_FindReportDescriptor(void) ;
@@ -203,6 +217,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    MIDI Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_MIDI_STREAMING)
     void USBFS_MIDI_IN_EP_Service(void) ;
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c
old mode 100755
new mode 100644
index 18f0364a..b047b37d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_std.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Standard request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -17,9 +17,9 @@
 #include "USBFS.h"
 #include "USBFS_cdc.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -33,7 +33,6 @@
 
 #if defined(USBFS_ENABLE_FWSN_STRING)
 
-
     /*******************************************************************************
     * Function Name: USBFS_SerialNumString
     ********************************************************************************
@@ -57,10 +56,10 @@
         USBFS_snStringConfirm = USBFS_FALSE;
         if(snString != NULL)
         {
-            USBFS_fwSerialNumberStringDescriptor = snString;
             /* Check descriptor validation */
             if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )
             {
+                USBFS_fwSerialNumberStringDescriptor = snString;
                 USBFS_snStringConfirm = USBFS_TRUE;
             }
         }
@@ -90,6 +89,7 @@ uint8 USBFS_HandleStandardRqst(void)
 {
     uint8 requestHandled = USBFS_FALSE;
     uint8 interfaceNumber;
+    uint8 configurationN;
     #if defined(USBFS_ENABLE_STRINGS)
         volatile uint8 *pStr = 0u;
         #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)
@@ -117,11 +117,14 @@ uint8 USBFS_HandleStandardRqst(void)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)
                 {
                     pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));
-                    USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
-                    USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
-                                      USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
-                                     (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
-                    requestHandled  = USBFS_InitControlRead();
+                    if( pTmp != NULL )  /* Verify that requested descriptor exists */
+                    {
+                        USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
+                        USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
+                                          USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
+                                         (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
+                        requestHandled  = USBFS_InitControlRead();
+                    }
                 }
                 #if defined(USBFS_ENABLE_STRINGS)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)
@@ -138,34 +141,39 @@ uint8 USBFS_HandleStandardRqst(void)
                             pStr = &pStr[descrLength];
                             nStr++;
                         }
-                    #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */
+                    #endif /*  USBFS_ENABLE_DESCRIPTOR_STRINGS */
                     /* Microsoft OS String*/
                     #if defined(USBFS_ENABLE_MSOS_STRING)
                         if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )
                         {
                             pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];
                         }
-                    #endif /* End USBFS_ENABLE_MSOS_STRING*/
+                    #endif /*  USBFS_ENABLE_MSOS_STRING*/
                     /* SN string */
                     #if defined(USBFS_ENABLE_SN_STRING)
                         if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&
                             (CY_GET_REG8(USBFS_wValueLo) ==
                             USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )
                         {
-                            pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
-                            #if defined(USBFS_ENABLE_FWSN_STRING)
-                                if(USBFS_snStringConfirm != USBFS_FALSE)
-                                {
-                                    pStr = USBFS_fwSerialNumberStringDescriptor;
-                                }
-                            #endif  /* USBFS_ENABLE_FWSN_STRING */
+
                             #if defined(USBFS_ENABLE_IDSN_STRING)
                                 /* Read DIE ID and generate string descriptor in RAM */
                                 USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);
                                 pStr = USBFS_idSerialNumberStringDescriptor;
-                            #endif    /* End USBFS_ENABLE_IDSN_STRING */
+                            #elif defined(USBFS_ENABLE_FWSN_STRING)
+                                if(USBFS_snStringConfirm != USBFS_FALSE)
+                                {
+                                    pStr = USBFS_fwSerialNumberStringDescriptor;
+                                }
+                                else
+                                {
+                                    pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                                }
+                            #else
+                                pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                            #endif  /* defined(USBFS_ENABLE_IDSN_STRING) */
                         }
-                    #endif    /* End USBFS_ENABLE_SN_STRING */
+                    #endif    /*  USBFS_ENABLE_SN_STRING */
                     if (*pStr != 0u)
                     {
                         USBFS_currentTD.count = *pStr;
@@ -173,7 +181,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         requestHandled  = USBFS_InitControlRead();
                     }
                 }
-                #endif /* End USBFS_ENABLE_STRINGS */
+                #endif /*  USBFS_ENABLE_STRINGS */
                 else
                 {
                     requestHandled = USBFS_DispatchClassRqst();
@@ -225,10 +233,23 @@ uint8 USBFS_HandleStandardRqst(void)
                 requestHandled = USBFS_InitNoDataControlTransfer();
                 break;
             case USBFS_SET_CONFIGURATION:
-                USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);
-                USBFS_configurationChanged = USBFS_TRUE;
-                USBFS_Config(USBFS_TRUE);
-                requestHandled = USBFS_InitNoDataControlTransfer();
+                configurationN = CY_GET_REG8(USBFS_wValueLo);
+                if(configurationN > 0u)
+                {   /* Verify that configuration descriptor exists */
+                    pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);
+                }
+                /* Responds with a Request Error when configuration number is invalid */
+                if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))
+                {
+                    /* Set new configuration if it has been changed */
+                    if(configurationN != USBFS_configuration)
+                    {
+                        USBFS_configuration = configurationN;
+                        USBFS_configurationChanged = USBFS_TRUE;
+                        USBFS_Config(USBFS_TRUE);
+                    }
+                    requestHandled = USBFS_InitNoDataControlTransfer();
+                }
                 break;
             case USBFS_SET_INTERFACE:
                 if (USBFS_ValidateAlternateSetting() != 0u)
@@ -241,7 +262,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         USBFS_Config(USBFS_FALSE);
                     #else
                         USBFS_ConfigAltChanged();
-                    #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+                    #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
                     /* Update handled Alt setting changes status */
                     USBFS_interfaceSetting_last[interfaceNumber] =
                          USBFS_interfaceSetting[interfaceNumber];
@@ -342,7 +363,6 @@ uint8 USBFS_HandleStandardRqst(void)
         uint8 value;
         const char8 CYCODE hex[16u] = "0123456789ABCDEF";
 
-
         /* Check descriptor validation */
         if( descr != NULL)
         {
@@ -360,7 +380,7 @@ uint8 USBFS_HandleStandardRqst(void)
         }
     }
 
-#endif /* End USBFS_ENABLE_IDSN_STRING */
+#endif /*  USBFS_ENABLE_IDSN_STRING */
 
 
 /*******************************************************************************
@@ -384,20 +404,18 @@ void USBFS_ConfigReg(void)
     uint8 ep;
     uint8 i;
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-        uint8 ep_type = 0u;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        uint8 epType = 0u;
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     /* Set the endpoint buffer addresses */
     ep = USBFS_EP1;
     for (i = 0u; i < 0x80u; i+= 0x10u)
     {
-        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |
-                                                          USBFS_ARB_EPX_CFG_RESET);
-
+        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */
             CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)
         {
@@ -410,8 +428,8 @@ void USBFS_ConfigReg(void)
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);
                 /* Prepare EP type mask for automatic memory allocation */
                 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-                    ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                    epType |= (uint8)(0x01u << (ep - USBFS_EP1));
+                #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
         }
         else
@@ -427,7 +445,7 @@ void USBFS_ConfigReg(void)
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i),     USBFS_EP[ep].buffOffset & 0xFFu);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         ep++;
     }
@@ -438,13 +456,13 @@ void USBFS_ConfigReg(void)
         USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST;   /* DMA burst threshold */
         USBFS_DMA_THRES_MSB_REG = 0u;
         USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;
-        USBFS_EP_TYPE_REG = ep_type;
+        USBFS_EP_TYPE_REG = epType;
         /* Cfg_cmp bit set to 1 once configuration is complete. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |
                                        USBFS_ARB_CFG_CFG_CPM;
         /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);
 }
@@ -477,11 +495,11 @@ void USBFS_Config(uint8 clearAltSetting)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     const uint8 *pDescr;
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 buffCount = 0u;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     const T_USBFS_LUT CYCODE *pTmp;
     const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;
@@ -534,56 +552,56 @@ void USBFS_Config(uint8 clearAltSetting)
             pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;
             for (i = 0u; i < ep; i++)
             {
-                /* Compare current Alternate setting with EP Alt*/
+                /* Compare current Alternate setting with EP Alt */
                 if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                 {
                     cur_ep = pEP->addr & USBFS_DIR_UNUSED;
-                    ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                    epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                     if (pEP->addr & USBFS_DIR_IN)
                     {
                         /* IN Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     else
                     {
                         /* OUT Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                      (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;
                     USBFS_EP[cur_ep].addr = pEP->addr;
@@ -591,7 +609,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 }
                 pEP = &pEP[1u];
             }
-        #else /* Config for static EP memory allocation  */
+        #else /* Configure for static EP memory allocation  */
             for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)
             {
                 /* p_list points the endpoint setting table. */
@@ -610,67 +628,67 @@ void USBFS_Config(uint8 clearAltSetting)
                         /* Compare current Alternate setting with EP Alt*/
                         if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                         {
-                            ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                            epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                             if ((pEP->addr & USBFS_DIR_IN) != 0u)
                             {
                                 /* IN Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             else
                             {
                                 /* OUT Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             USBFS_EP[i].addr = pEP->addr;
                             USBFS_EP[i].attrib = pEP->attributes;
 
                             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                                 break;      /* use first EP setting in Auto memory managment */
-                            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
                         }
                     }
                     pEP = &pEP[1u];
                 }
             }
-        #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+        #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
 
         /* Init class array for each interface and interface number for each EP.
         *  It is used for handling Class specific requests directed to either an
@@ -694,7 +712,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 USBFS_EP[ep].buffOffset = buffCount;
                  buffCount += USBFS_EP[ep].bufferSize;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Configure hardware registers */
         USBFS_ConfigReg();
@@ -725,7 +743,7 @@ void USBFS_ConfigAltChanged(void)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     uint8 ri;
 
     const T_USBFS_LUT CYCODE *pTmp;
@@ -753,19 +771,19 @@ void USBFS_ConfigAltChanged(void)
             {
                 cur_ep = pEP->addr & USBFS_DIR_UNUSED;
                 ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-                ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                 if ((pEP->addr & USBFS_DIR_IN) != 0u)
                 {
                     /* IN Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                 }
                 else
                 {
                     /* OUT Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                 }
                  /* Change the SIE mode for the selected EP to NAK ALL */
@@ -823,7 +841,7 @@ void USBFS_ConfigAltChanged(void)
                                                                 USBFS_EP[cur_ep].buffOffset & 0xFFu);
                 CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),
                                                                 USBFS_EP[cur_ep].buffOffset >> 8u);
-            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
             /* Get next EP element */
             pEP = &pEP[1u];
@@ -840,13 +858,13 @@ void USBFS_ConfigAltChanged(void)
 *  This routine returns a pointer a configuration table entry
 *
 * Parameters:
-*  c:  Configuration Index
+*  confIndex:  Configuration Index
 *
 * Return:
-*  Device Descriptor pointer.
+*  Device Descriptor pointer or NULL when descriptor isn't exists.
 *
 *******************************************************************************/
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                         
 {
     /* Device Table */
@@ -856,8 +874,20 @@ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
 
     /* The first entry points to the Device Descriptor,
     *  the rest configuration entries.
-	*/
-    return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );
+    *  Set pointer to the first Configuration Descriptor
+    */
+    pTmp = &pTmp[1u];
+    /* For this table, c is the number of configuration descriptors  */
+    if(confIndex >= pTmp->c)   /* Verify that required configuration descriptor exists */
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) NULL;
+    }
+    else
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;
+    }
+
+    return( pTmp );
 }
 
 
@@ -902,14 +932,24 @@ const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void)
                                                         
 {
     const T_USBFS_LUT CYCODE *pTmp;
+    const uint8 CYCODE *pInterfaceClass;
     uint8 currentInterfacesNum;
 
     pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
-    currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
-    /* Third entry in the LUT starts the Interface Table pointers */
-    /* The INTERFACE_CLASS table is located after all interfaces */
-    pTmp = &pTmp[currentInterfacesNum + 2u];
-    return( (const uint8 CYCODE *) pTmp->p_list );
+    if( pTmp != NULL )
+    {
+        currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
+        /* Third entry in the LUT starts the Interface Table pointers */
+        /* The INTERFACE_CLASS table is located after all interfaces */
+        pTmp = &pTmp[currentInterfacesNum + 2u];
+        pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;
+    }
+    else
+    {
+        pInterfaceClass = (const uint8 CYCODE *) NULL;
+    }
+
+    return( pInterfaceClass );
 }
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
old mode 100755
new mode 100644
index 15b68a55..ef4d5f14
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_vnd.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB vendor request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -34,7 +34,7 @@
 ********************************************************************************
 *
 * Summary:
-*  This routine provide users with a method to implement vendor specifc
+*  This routine provide users with a method to implement vendor specific
 *  requests.
 *
 *  To implement vendor specific requests, add your code in this function to
@@ -66,7 +66,7 @@ uint8 USBFS_HandleVendorRqst(void)
                     USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     requestHandled  = USBFS_InitControlRead();
-                #endif /* End USBFS_ENABLE_MSOS_STRING */
+                #endif /*  USBFS_ENABLE_MSOS_STRING */
                 break;
             default:
                 break;
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
old mode 100755
new mode 100644
index e959beb7..3504994b
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
@@ -45,10 +45,10 @@ CY_METADATA_SIZE    = 64;
  */
 EXTERN(Reset)
 
-/* Bring in the interrupt routines & vector */
+/* Bring in interrupt routines & vector */
 EXTERN(main)
 
-/* Bring in the meta data */
+/* Bring in meta data */
 EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
 EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 
@@ -56,7 +56,7 @@ EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 PROVIDE(__cy_heap_start = _end);
 PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);
 PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));
-PROVIDE(__cy_heap_end = __cy_stack - 0x2000);
+PROVIDE(__cy_heap_end = __cy_stack - 0x1000);
 
 
 SECTIONS
@@ -90,7 +90,7 @@ SECTIONS
     /* Make sure we pulled in some reset code.  */
     ASSERT (. != __cy_reset, "No reset code");
 
-	/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
+	/* Place DMA initialization before text to ensure it gets placed in first 64K of flash */
     *(.dma_init)
     ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
 		
@@ -221,10 +221,10 @@ SECTIONS
     __cy_heap_limit = .;
   } >ram
 
-  .stack (__cy_stack - 0x2000) (NOLOAD) :
+  .stack (__cy_stack - 0x1000) (NOLOAD) :
   {
     __cy_stack_limit = .;
-    . += 0x2000;
+    . += 0x1000;
   } >ram
   
   /* Check if data + heap + stack exceeds RAM limit */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
old mode 100755
new mode 100644
index a7c7be7c..959fde97
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: core_cm3_psoc5.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides important type information for the PSoC5.  This includes types
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
old mode 100755
new mode 100644
index 01f07941..33ecdf44
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the power management.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,8 @@
 
 
 /*******************************************************************
-* Place your includes, defines and code here. Do not use merge
-* region below unless any component datasheet suggest to do so.
+* Place your includes, defines, and code here. Do not use the merge
+* region below unless any component datasheet suggests doing so.
 *******************************************************************/
 /* `#START CY_PM_HEADER_INCLUDE` */
 
@@ -51,8 +51,8 @@ static void CyPmHviLviRestore(void) ;
 *
 * Summary:
 *  This function is called in preparation for entering sleep or hibernate low
-*  power modes. Saves all state of the clocking system that does not persist
-*  during sleep/hibernate or that needs to be altered in preparation for
+*  power modes. Saves all the states of the clocking system that do not persist
+*  during sleep/hibernate or that need to be altered in preparation for
 *  sleep/hibernate. Shutdowns all the digital and analog clock dividers for the
 *  active power mode configuration.
 *
@@ -105,6 +105,45 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imo2x = CY_PM_DISABLED;
     }
 
+    /* Master clock - save source */
+    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+
+    /* Switch Master clock's source from PLL's output to PLL's source */
+    if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)
+    {
+        switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)
+        {
+        case CY_PM_CLKDIST_PLL_SRC_IMO:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_XTAL:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_DSI:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);
+            break;
+
+        default:
+            CYASSERT(0u != 0u);
+            break;
+        }
+    }
+
+    /* PLL - check enable state, disable if needed */
+    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
+    {
+        /* PLL is enabled - save state and disable */
+        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
+        CyPLL_OUT_Stop();
+    }
+    else
+    {
+        /* PLL is disabled - save state */
+        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
+    }
+
     /* IMO - set appropriate frequency for LPM */
     CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);
 
@@ -119,8 +158,11 @@ void CyPmSaveClocks(void)
         /* IMO - save disabled state */
         cyPmClockBackup.imoEnable = CY_PM_DISABLED;
 
-        /* IMO - enable */
+        /* Enable the IMO. Use software delay instead of the FTW-based inside */
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
+
+        /* Settling time of the IMO is of the order of less than 6us */
+        CyDelayUs(6u);
     }
 
     /* IMO - save the current IMOCLK source and set to IMO if not yet */
@@ -130,7 +172,7 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imoClkSrc =
             (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;
 
-        /* IMO -  set IMOCLK source to MHz OSC */
+        /* IMO -  set IMOCLK source to IMO */
         CyIMO_SetSource(CY_IMO_SOURCE_IMO);
     }
     else
@@ -161,16 +203,13 @@ void CyPmSaveClocks(void)
     if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)
     {
         CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);
-    }    /* Need to change nothing if master clock divider is 1 */
-
-    /* Master clock - save current source */
-    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+    }    /* No change if master clock divider is 1 */
 
     /* Master clock source - set it to IMO if not yet. */
     if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)
     {
         CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
-    }    /* Need to change nothing if master clock source is IMO */
+    }    /* No change if master clock source is IMO */
 
     /* Bus clock - save divider and set it, if needed, to divide-by-one */
     cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
@@ -180,22 +219,9 @@ void CyPmSaveClocks(void)
         CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);
     }    /* Do nothing if saved and actual values are equal */
 
-    /* Set number of wait cycles for the flash according CPU frequency in MHz */
+    /* Set number of wait cycles for flash according to CPU frequency in MHz */
     CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);
 
-    /* PLL - check enable state, disable if needed */
-    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
-    {
-        /* PLL is enabled - save state and disable */
-        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
-        CyPLL_OUT_Stop();
-    }
-    else
-    {
-        /* PLL is disabled - save state */
-        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
-    }
-
     /* MHz ECO - check enable state and disable if needed */
     if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))
     {
@@ -211,8 +237,8 @@ void CyPmSaveClocks(void)
 
 
     /***************************************************************************
-    * Save enable state of delay between the system bus clock and each of the
-    * 4 individual analog clocks. This bit non-retention and it's value should
+    * Save the enable state of delay between the system bus clock and each of the
+    * 4 individual analog clocks. This bit non-retention and its value should
     * be restored on wakeup.
     ***************************************************************************/
     if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))
@@ -240,11 +266,11 @@ void CyPmSaveClocks(void)
 *
 *  PSoC 3 and PSoC 5LP:
 *  The merge region could be used to process state when the megahertz crystal is
-*  not ready after the hold-off timeout.
+*  not ready after a hold-off timeout.
 *
 *  PSoC 5:
-*  The 130 ms is given for the megahertz crystal to stabilize. It's readiness is
-*  not verified after the hold-off timeout.
+*  The 130 ms is given for the megahertz crystal to stabilize. Its readiness is
+*  not verified after a hold-off timeout.
 *
 * Parameters:
 *  None
@@ -265,10 +291,10 @@ void CyPmRestoreClocks(void)
         CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ,  CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,
         CY_IMO_FREQ_48MHZ, 5u, 6u};
 
-    /* Restore enable state of delay between the system bus clock and ACLKs. */
+    /* Restore enable state of delay between system bus clock and ACLKs. */
     if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)
     {
-        /* Delay for both the bandgap and the delay line to settle out */
+        /* Delay for both bandgap and delay line to settle out */
         CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *
                         CY_PM_GET_CPU_FREQ_MHZ);
 
@@ -279,7 +305,7 @@ void CyPmRestoreClocks(void)
     if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)
     {
         /***********************************************************************
-        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait
+        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait
         * period uses FTW for period measurement. This could cause a problem
         * if CTW/FTW is used as a wake up time in the low power modes APIs.
         * So, the XTAL wait procedure is implemented with a software delay.
@@ -309,7 +335,7 @@ void CyPmRestoreClocks(void)
         {
             /*******************************************************************
             * Process the situation when megahertz crystal is not ready.
-            * Time to stabialize value is crystal specific.
+            * Time to stabilize the value is crystal specific.
             *******************************************************************/
            /* `#START_MHZ_ECO_TIMEOUT` */
 
@@ -318,10 +344,10 @@ void CyPmRestoreClocks(void)
     }   /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */
 
 
-    /* Temprorary set the maximum flash wait cycles */
+    /* Temprorary set maximum flash wait cycles */
     CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);
 
-    /* The XTAL and DSI clocks are ready to be source for Master clock. */
+    /* XTAL and DSI clocks are ready to be source for Master clock. */
     if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||
        (CY_PM_MASTER_CLK_SRC_DSI  == cyPmClockBackup.masterClkSrc))
     {
@@ -366,13 +392,6 @@ void CyPmRestoreClocks(void)
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
     }
 
-    /* IMO - restore disable state if needed */
-    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
-       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
-    {
-        CyIMO_Stop();
-    }
-
     /* IMO - restore IMOCLK source */
     CyIMO_SetSource(cyPmClockBackup.imoClkSrc);
 
@@ -389,6 +408,7 @@ void CyPmRestoreClocks(void)
                                 cyPmClockBackup.clkImoSrc;
     }
 
+
     /* PLL restore state */
     if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)
     {
@@ -398,12 +418,38 @@ void CyPmRestoreClocks(void)
         * as a wakeup time in the low power modes APIs. To omit this issue PLL
         * wait procedure is implemented with a software delay.
         ***********************************************************************/
+        status = CYRET_TIMEOUT;
 
         /* Enable PLL */
         (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);
 
-        /* Make a 250 us delay */
-        CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);
+        /* Read to clear lock status after delay */
+        CyDelayUs((uint32)80u);
+        (void) CY_PM_FASTCLK_PLL_SR_REG;
+
+        /* It should take 250 us lock: 251-80 = 171 */
+        for(i = 171u; i > 0u; i--)
+        {
+            CyDelayUs((uint32)1u);
+
+            /* Accept PLL is OK after two consecutive polls indicate PLL lock */
+            if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&
+               (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))
+            {
+                status = CYRET_SUCCESS;
+                break;
+            }
+        }
+
+        if(CYRET_TIMEOUT == status)
+        {
+            /*******************************************************************
+            * Process the situation when PLL is not ready.
+            *******************************************************************/
+           /* `#START_PLL_TIMEOUT` */
+
+           /* `#END` */
+        }
     }   /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */
 
 
@@ -421,6 +467,13 @@ void CyPmRestoreClocks(void)
         CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);
     }
 
+    /* IMO - disable if it was originally disabled */
+    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
+       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
+    {
+        CyIMO_Stop();
+    }
+
     /* Bus clock - restore divider, if needed */
     clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
     clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;
@@ -490,7 +543,7 @@ void CyPmRestoreClocks(void)
 *  Sleep Timer component and one second interval should be configured with the
 *  RTC component.
 *
-*  The wakeup behavior depends on wakeupSource parameter in the following
+*  The wakeup behavior depends on the wakeupSource parameter in the following
 *  manner: upon function execution the device will be switched from Active to
 *  Alternate Active mode and then the CPU will be halted. When an enabled wakeup
 *  event occurs the device will return to Active mode.  Similarly when an
@@ -534,7 +587,7 @@ void CyPmRestoreClocks(void)
             For PSoC 3 silicon the valid range of  values is 1 to 256.
 *
 *  wakeUpSource:    Specifies a bitwise mask of wakeup sources. In addition, if
-*                   a wakeupTime has been specified the associated timer will be
+*                   a wakeupTime has been specified, the associated timer will be
 *                   included as a wakeup source.
 *
 *           Define                      Source
@@ -556,13 +609,13 @@ void CyPmRestoreClocks(void)
 *  *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.
 *  **Note: CTW and One PPS wakeup signals are in the same mask bit.
 *
-*  When specifying a Comparator as the wakeupSource an instance specific define
-*  should be used that will track with the specific comparator that the instance
-*  is placed into. As an example, for a Comparator instance named MyComp the
+*  When specifying a Comparator as the wakeupSource, an instance specific define
+*  that will track with the specific comparator that the instance
+*  is placed into should be used. As an example, for a Comparator instance named MyComp the
 *  value to OR into the mask is: MyComp_ctComp__CMP_MASK.
 *
 *  When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()
-*  function must be called upon wakeup with corresponding parameter. Please
+*  function must be called upon wakeup with a corresponding parameter. Please
 *  refer to the CyPmReadStatus() API in the System Reference Guide for more
 *  information.
 *
@@ -576,7 +629,7 @@ void CyPmRestoreClocks(void)
 *  If a wakeupTime other than NONE is specified, then upon exit the state of the
 *  specified timer will be left as specified by wakeupTime with the timer
 *  enabled and the interrupt disabled.  Also, the ILO 1 KHz (if CTW timer is
-*  used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)
+*  used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)
 *  will be left started.
 *
 *******************************************************************************/
@@ -602,7 +655,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
         {
             CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_FTW;
         }
 
@@ -612,7 +665,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current CTW configuration and set new one */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_CTW;
         }
 
@@ -622,7 +675,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current 1PPS configuration and set new one */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;
         }
 
@@ -674,7 +727,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  Puts the part into the Sleep state.
 *
 *  Note Before calling this function, you must manually configure the power
-*  mode of the source clocks for the timer that is used as wakeup timer.
+*  mode of the source clocks for the timer that is used as the wakeup timer.
 *
 *  Note Before calling this function, you must prepare clock tree configuration
 *  for the low power mode by calling CyPmSaveClocks(). And restore clock
@@ -685,7 +738,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  PSoC 3:
 *  Before switching to Sleep, if a wakeupTime other than NONE is specified,
 *  then the appropriate timer state is configured as specified with the
-*  interrupt for that timer disabled.  The wakeup source will be the combination
+*  interrupt for that timer disabled.  The wakeup source will be a combination
 *  of the values specified in the wakeupSource and any timer specified in the
 *  wakeupTime argument.  Once the wakeup condition is satisfied, then all saved
 *  state is restored and the function returns in the Active state.
@@ -706,7 +759,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  The wakeupTime parameter is not used and the only NONE can be specified.
 *  The wakeup time must be configured with the component, SleepTimer for CTW
 *  intervals and RTC for 1PPS interval. The component must be configured to
-*  generate an interrrupt.
+*  generate interrupt.
 *
 * Parameters:
 *  wakeupTime:      Specifies a timer wakeup source and the frequency of that
@@ -780,7 +833,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  detect (power supply supervising capabilities) are required in a design
 *  during sleep, use the Central Time Wheel (CTW) to periodically wake the
 *  device, perform software buzz, and refresh the supervisory services. If LVI,
-*  HVI, or Brown Out is not required, then use of the CTW is not required.
+*  HVI, or Brown Out is not required, then CTW is not required.
 *  Refer to the device errata for more information.
 *
 *******************************************************************************/
@@ -816,13 +869,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
     /***********************************************************************
     * PSoC3 < TO6:
-    * - Hardware buzz must be disabled before sleep mode entry.
+    * - Hardware buzz must be disabled before the sleep mode entry.
     * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must
-    *   be aslo disabled.
+    *   be also disabled.
     *
     * PSoC3 >= TO6:
-    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be
-    *   enabled before sleep mode entry and restored on wakeup.
+    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware
+    *   buzz must be enabled before the sleep mode entry and restored on
+    *   the wakeup.
     ***********************************************************************/
     #if(CY_PSOC3)
 
@@ -860,9 +914,9 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************************
-    * For ARM-based devices, an interrupt is required for the CPU to wake up. The
+    * For ARM-based devices,interrupt is required for the CPU to wake up. The
     * Power Management implementation assumes that wakeup time is configured with a
-    * separate component (component-based wakeup time configuration) for an
+    * separate component (component-based wakeup time configuration) for
     * interrupt to be issued on terminal count. For more information, refer to the
     * Wakeup Time Configuration section of System Reference Guide.
     *******************************************************************************/
@@ -887,10 +941,10 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         /* CTW - save current and set new configuration */
         if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))
         {
-            /* Save current and set new configuration of the CTW */
+            /* Save current and set new configuration of CTW */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_CTW;
         }
 
@@ -900,7 +954,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
             /* Save current and set new configuration of the 1PPS */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_ONE_PPS;
         }
 
@@ -923,8 +977,8 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************
-    * Do not use merge region below unless any component datasheet
-    * suggest to do so.
+    * Do not use the merge region below unless any component datasheet
+    * suggests doing so.
     *******************************************************************/
     /* `#START CY_PM_JUST_BEFORE_SLEEP` */
 
@@ -949,13 +1003,13 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));
     }
 
-    /* Switch to the Sleep mode */
+    /* Switch to Sleep mode */
     CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);
 
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1023,7 +1077,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  PSoC 3 and PSoC 5LP:
 *  Before switching to Hibernate, the current status of the PICU wakeup source
 *  bit is saved and then set. This configures the device to wake up from the
-*  PICU. Make sure you have at least one pin configured to generate a PICU
+*  PICU. Make sure you have at least one pin configured to generate PICU
 *  interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls
 *  the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."
 *  In the Pins component datasheet, this register is referred to as the IRQ
@@ -1046,14 +1100,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  requirement begins when the device wakes up. There is no hardware check that
 *  this requirement is met. The specified delay should be done on ISR entry.
 *
-*  After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
+*  After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
 *  instance name of the Pins component) function must be called to clear the
-*  latched pin events to allow proper Hibernate mode entry andd to enable
+*  latched pin events to allow the proper Hibernate mode entry and to enable
 *  detection of future events.
 *
 *  The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to
 *  measure Hibernate/Sleep regulator settling time after a reset. The holdoff
-*  delay is measured using rising edges of the 1 kHz ILO.
+*  delay is measured using the rising edges of the 1 kHz ILO.
 *
 *******************************************************************************/
 void CyPmHibernate(void) 
@@ -1065,8 +1119,8 @@ void CyPmHibernate(void)
 
         /***********************************************************************
         * The Hibernate/Sleep regulator has a settling time after a reset.
-        * During this time, the system ignores requests to enter Sleep and
-        * Hibernate modes. The holdoff delay is measured using rising edges of
+        * During this time, the system ignores requests to enter the Sleep and
+        * Hibernate modes. The holdoff delay is measured using the rising edges of
         * the 1 kHz ILO.
         ***********************************************************************/
         if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))
@@ -1123,7 +1177,7 @@ void CyPmHibernate(void)
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1193,7 +1247,7 @@ uint8 CyPmReadStatus(uint8 mask)
     /* Enter critical section */
     interruptState = CyEnterCriticalSection();
 
-    /* Save value of the register, copy it and clear desired bit */
+    /* Save value of register, copy it and clear desired bit */
     interruptStatus |= CY_PM_INT_SR_REG;
     tmpStatus = interruptStatus;
     interruptStatus &= ((uint8)(~mask));
@@ -1234,11 +1288,11 @@ static void CyPmHibSaveSet(void)
     if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))
     {
         /***********************************************************************
-        * If I2C backup regulator is enabled, all the fixed-function registers
-        * store their values while device is in low power mode, otherwise their
+        * If the I2C backup regulator is enabled, all the fixed-function registers
+        * store their values while the device is in the low power mode, otherwise their
         * configuration is lost. The I2C API makes a decision to restore or not
         * to restore I2C registers based on this. If this regulator will be
-        * disabled and then enabled, I2C API will suppose that I2C block
+        * disabled and then enabled, I2C API will suppose that the I2C block
         * registers preserved their values, while this is not true. So, the
         * backup regulator is disabled. The I2C sleep APIs is responsible for
         * restoration.
@@ -1289,7 +1343,7 @@ static void CyPmHibSaveSet(void)
 
 
     /***************************************************************************
-    * Save and set power mode wakeup trim registers
+    * Save and set the power mode wakeup trim registers
     ***************************************************************************/
     cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;
     cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;
@@ -1304,12 +1358,12 @@ static void CyPmHibSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Restore device for proper Hibernate mode exit:
-*  - Restore LVI/HVI configuration - call CyPmHviLviRestore()
+*  Restores the device for the proper Hibernate mode exit:
+*  - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()
 *  - CyPmHibSlpSaveRestore() function is called
-*  - Restores ILO power down mode state and enable it
-*  - Restores state of 1 kHz and 100 kHz ILO and disable them
-*  - Restores sleep regulator settings
+*  - Restores ILO power down mode state and enables it
+*  - Restores the state of 1 kHz and 100 kHz ILO and disables them
+*  - Restores the sleep regulator settings
 *
 * Parameters:
 *  None
@@ -1352,7 +1406,7 @@ static void CyPmHibRestore(void)
 
 
     /***************************************************************************
-    * Restore power mode wakeup trim registers
+    * Restore the power mode wakeup trim registers
     ***************************************************************************/
     CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;
     CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;
@@ -1364,10 +1418,10 @@ static void CyPmHibRestore(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs CTW configuration:
-*  - Disables CTW interrupt
+*  Performs the CTW configuration:
+*  - Disables the CTW interrupt
 *  - Enables 1 kHz ILO
-*  - Sets new CTW interval
+*  - Sets a new CTW interval
 *
 * Parameters:
 *  ctwInterval: the CTW interval to be set.
@@ -1404,11 +1458,11 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
         /* Set CTW interval if needed */
         if(CY_PM_TW_CFG1_REG != ctwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG1_REG = ctwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the CTW */
+        /* Enable CTW */
         CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;
     }
 }
@@ -1421,7 +1475,7 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
 * Summary:
 *  Performs 1PPS configuration:
 *  - Starts 32 KHz XTAL
-*  - Disables 1PPS interupts
+*  - Disables 1PPS interrupts
 *  - Enables 1PPS
 *
 * Parameters:
@@ -1453,10 +1507,10 @@ void CyPmOppsSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs FTW configuration:
-*  - Disables FTW interrupt
+*  Performs the FTW configuration:
+*  - Disables the FTW interrupt
 *  - Enables 100 kHz ILO
-*  - Sets new FTW interval.
+*  - Sets a new FTW interval.
 *
 * Parameters:
 *  ftwInterval - FTW counter interval.
@@ -1465,7 +1519,7 @@ void CyPmOppsSet(void)
 *  None
 *
 * Side Effects:
-*  Enables ILO 100 KHz clock and leaves it enabled.
+*  Enables the ILO 100 KHz clock and leaves it enabled.
 *
 *******************************************************************************/
 void CyPmFtwSetInterval(uint8 ftwInterval) 
@@ -1476,13 +1530,13 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
     /* Enable 100kHz ILO */
     CyILO_Start100K();
 
-    /* Iterval could be set only while FTW is disabled */
+    /* Interval could be set only while FTW is disabled */
     if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))
     {
         /* Disable FTW, set new FTW interval if needed and enable it again */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Disable the CTW, set new CTW interval and enable it again */
+            /* Disable CTW, set new CTW interval and enable it again */
             CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));
             CY_PM_TW_CFG0_REG = ftwInterval;
             CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
@@ -1493,11 +1547,11 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
         /* Set new FTW counter interval if needed. FTW is disabled. */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG0_REG = ftwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the FTW */
+        /* Enable FTW */
         CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
     }
 }
@@ -1508,12 +1562,12 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for preparing device for Sleep and Hibernate low power
+*  This API is used for preparing the device for the Sleep and Hibernate low power
 *  modes entry:
-*  - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)
-*  - Saves SC/CT routing connections (PSoC 3/5/5LP)
-*  - Disables Serial Wire Viewer (SWV) (PSoC 3)
-*  - Save boost reference selection and set it to internal
+*  - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)
+*  - Saves the SC/CT routing connections (PSoC 3/5/5LP)
+*  - Disables the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Saves the boost reference selection and sets it to internal
 *
 * Parameters:
 *  None
@@ -1643,11 +1697,11 @@ static void CyPmHibSlpSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for restoring device configurations after wakeup from Sleep
+*  This API is used for restoring the device configurations after wakeup from the Sleep
 *  and Hibernate low power modes:
-*  - Restores SC/CT routing connections
-*  - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)
-*  - Restore boost reference selection
+*  - Restores the SC/CT routing connections
+*  - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Restores the  boost reference selection
 *
 * Parameters:
 *  None
@@ -1740,7 +1794,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lvidEn = CY_PM_ENABLED;
         cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;
 
-        /* Save state of reset device at a specified Vddd threshold */
+        /* Save state of reset device at specified Vddd threshold */
         cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1756,7 +1810,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lviaEn = CY_PM_ENABLED;
         cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;
 
-        /* Save state of reset device at a specified Vdda threshold */
+        /* Save state of reset device at specified Vdda threshold */
         cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1784,7 +1838,7 @@ static void CyPmHviLviSaveDisable(void)
 ********************************************************************************
 *
 * Summary:
-*  Restores analog and digital LVI and HVI configuration.
+*  Restores the analog and digital LVI and HVI configuration.
 *
 * Parameters:
 *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
old mode 100755
new mode 100644
index bfa22143..0110c377
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the power management API.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -54,7 +54,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC3)
 
-    /* Wake up time for the Sleep mode */
+    /* Wake up time for Sleep mode */
     #define PM_SLEEP_TIME_ONE_PPS           (0x01u)
     #define PM_SLEEP_TIME_CTW_2MS           (0x02u)
     #define PM_SLEEP_TIME_CTW_4MS           (0x03u)
@@ -72,7 +72,7 @@ void CyPmOppsSet(void) ;
     /* Difference between parameter's value and register's one */
     #define CY_PM_FTW_INTERVAL_SHIFT        (0x000Eu)
 
-    /* Wake up time for the Alternate Active mode */
+    /* Wake up time for Alternate Active mode */
     #define PM_ALT_ACT_TIME_ONE_PPS         (0x0001u)
     #define PM_ALT_ACT_TIME_CTW_2MS         (0x0002u)
     #define PM_ALT_ACT_TIME_CTW_4MS         (0x0003u)
@@ -91,7 +91,7 @@ void CyPmOppsSet(void) ;
 #endif  /* (CY_PSOC3) */
 
 
-/* Wake up sources for the Sleep mode */
+/* Wake up sources for Sleep mode */
 #define PM_SLEEP_SRC_COMPARATOR0        (0x0001u)
 #define PM_SLEEP_SRC_COMPARATOR1        (0x0002u)
 #define PM_SLEEP_SRC_COMPARATOR2        (0x0004u)
@@ -104,7 +104,7 @@ void CyPmOppsSet(void) ;
 #define PM_SLEEP_SRC_ONE_PPS            (0x0800u)
 #define PM_SLEEP_SRC_LCD                (0x1000u)
 
-/* Wake up sources for the Alternate Active mode */
+/* Wake up sources for Alternate Active mode */
 #define PM_ALT_ACT_SRC_COMPARATOR0      (0x0001u)
 #define PM_ALT_ACT_SRC_COMPARATOR1      (0x0002u)
 #define PM_ALT_ACT_SRC_COMPARATOR2      (0x0004u)
@@ -145,7 +145,7 @@ void CyPmOppsSet(void) ;
 #define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (5u)
 
 
-/* Delay line bandgap current settling time starting from a wakeup event */
+/* Delay line bandgap current settling time starting from wakeup event */
 #define     CY_PM_CLK_DELAY_BANDGAP_SETTLE_US       (50u)
 
 /* Delay line internal bias settling */
@@ -177,7 +177,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC5)
 
-    /* The CPU clock is directly derived from bus clock */
+    /* CPU clock is directly derived from bus clock */
     #define     CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])
 
 #endif  /* (CY_PSOC5) */
@@ -186,7 +186,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low
 * power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI
 * instruction into the instruction stream generated by the compiler. The GCC
 * compiler has to execute assembly language instruction.
 *******************************************************************************/
@@ -219,7 +219,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * This macro defines the IMO frequency that will be set by CyPmSaveClocks()
 * function based on Enable Fast IMO during Startup option from the DWR file.
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the
 * low power mode and restore IMO back to the value set by CyPmSaveClocks()
 * immediately on wakeup.
 *******************************************************************************/
@@ -243,7 +243,7 @@ typedef struct cyPmClockBackupStruct
     /* CyPmSaveClocks()/CyPmRestoreClocks() */
     uint8  enClkA;              /* Analog clocks enable         */
     uint8  enClkD;              /* Digital clocks enable        */
-    uint8  masterClkSrc;        /* The Master clock source      */
+    uint8  masterClkSrc;        /* Master clock source          */
     uint8  imoFreq;             /* IMO frequency (reg's value)  */
     uint8  imoUsbClk;           /* IMO USB CLK (reg's value)    */
     uint8  flashWaitCycles;     /* Flash wait cycles            */
@@ -252,7 +252,7 @@ typedef struct cyPmClockBackupStruct
     uint8  clkImoSrc;
     uint8  imo2x;               /* IMO doubler enable state     */
     uint8  clkSyncDiv;          /* Master clk divider           */
-    uint16 clkBusDiv;           /* The clk_bus divider          */
+    uint16 clkBusDiv;           /* clk_bus divider              */
     uint8  pllEnableState;      /* PLL enable state             */
     uint8  xmhzEnableState;     /* XM HZ enable state           */
     uint8  clkDistDelay;        /* Delay for clk_bus and ACLKs  */
@@ -472,6 +472,14 @@ typedef struct cyPmBackupStruct
 #define CY_PM_BOOST_CR2_REG           (* (reg8 *) CYREG_BOOST_CR2 )
 #define CY_PM_BOOST_CR2_PTR           (  (reg8 *) CYREG_BOOST_CR2 )
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_REG           (* (reg8 *) CYREG_INTC_CSR_EN )
+    #define CY_PM_INTC_CSR_EN_PTR           (  (reg8 *) CYREG_INTC_CSR_EN )
+
+#endif  /* (CY_PSOC3) */
+
 
 /***************************************
 * Register Constants
@@ -521,7 +529,12 @@ typedef struct cyPmBackupStruct
 #define CY_PM_CLKDIST_IMO_OUT_IMO       (0x00u)
 #define CY_PM_CLKDIST_IMO2X_SRC         (0x40u)
 
-/* Waiting for the hibernate/sleep regulator to stabilize */
+#define CY_PM_CLKDIST_PLL_SRC_MASK      (0x03u)
+#define CY_PM_CLKDIST_PLL_SRC_IMO       (0x00u)
+#define CY_PM_CLKDIST_PLL_SRC_XTAL      (0x01u)
+#define CY_PM_CLKDIST_PLL_SRC_DSI       (0x02u)
+
+/* Waiting for hibernate/sleep regulator to stabilize */
 #define CY_PM_MODE_CSR_PWRUP_PULSE_Q    (0x08u)
 
 #define CY_PM_MODE_CSR_ACTIVE           (0x00u)     /* Active power mode      */
@@ -533,10 +546,10 @@ typedef struct cyPmBackupStruct
 /* I2C regulator backup enable */
 #define CY_PM_PWRSYS_CR1_I2CREG_BACKUP  (0x04u)
 
-/* When set, prepares the system to disable the LDO-A */
+/* When set, prepares system to disable LDO-A */
 #define CY_PM_PWRSYS_CR1_LDOA_ISO       (0x01u)
 
-/* When set, disables the analog LDO regulator */
+/* When set, disables analog LDO regulator */
 #define CY_PM_PWRSYS_CR1_LDOA_DIS       (0x02u)
 
 #define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET  (0x04u)
@@ -554,19 +567,19 @@ typedef struct cyPmBackupStruct
 /* Bus Clock divider to divide-by-one */
 #define CY_PM_BUS_CLK_DIV_BY_ONE        (0x00u)
 
-/* HVI/LVI feature on the external analog and digital supply mask */
+/* HVI/LVI feature on external analog and digital supply mask */
 #define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)
 
-/* The high-voltage-interrupt feature on the external analog supply */
+/* High-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_HVIA_EN         (0x04u)
 
-/* The low-voltage-interrupt feature on the external analog supply */
+/* Low-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_LVIA_EN         (0x02u)
 
-/* The low-voltage-interrupt feature on the external digital supply */
+/* Low-voltage-interrupt feature on external digital supply */
 #define CY_PM_RESET_CR1_LVID_EN         (0x01u)
 
-/* Allows the system to program delays on clk_sync_d */
+/* Allows system to program delays on clk_sync_d */
 #define CY_PM_CLKDIST_DELAY_EN          (0x04u)
 
 
@@ -595,7 +608,7 @@ typedef struct cyPmBackupStruct
 #endif  /* (CY_PSOC3) */
 
 
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+/* Disables sleep regulator and shorts vccd to vpwrsleep */
 #define CY_PM_PWRSYS_SLP_TR_BYPASS          (0x10u)
 
 /* Boost Control 2: Select external precision reference */
@@ -615,9 +628,37 @@ typedef struct cyPmBackupStruct
 
 #endif  /* (CY_PSOC5) */
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_CLK       (0x01u)
+
+#endif  /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of
+* whether lock is subsequently lost) until it is read. Upon reading it will
+* clear. If lock is still true then the bit will simply set again. If lock
+* happens to be false when the clear on read occurs then the bit will stay
+* cleared until the next lock event.
+*******************************************************************************/
+#define CY_PM_FASTCLK_PLL_LOCKED       (0x01u)
+
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #if(CY_PSOC3)
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
index 32543d5e..d4fece0f 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
@@ -29,1031 +29,1054 @@ __attribute__ ((__section__(".cybootloader"), used))
 #endif
 const uint8 cy_bootloader[] = {
     0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u,
-    0x61u, 0x01u, 0x00u, 0x00u, 0x61u, 0x01u, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u,
-    0x02u, 0x60u, 0x00u, 0xF0u, 0x7Bu, 0xFCu, 0x00u, 0xF0u,
-    0xA1u, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,
-    0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
-    0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u,
-    0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u,
-    0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x20u, 0x00u, 0x00u,
+    0x5Du, 0x01u, 0x00u, 0x00u, 0x5Du, 0x01u, 0x00u, 0x00u,
+    0x08u, 0xB5u, 0x05u, 0x4Bu, 0x1Au, 0x68u, 0x03u, 0xF5u,
+    0x3Fu, 0x53u, 0x02u, 0x33u, 0x1Au, 0x60u, 0x00u, 0xF0u,
+    0x43u, 0xFAu, 0x00u, 0xF0u, 0x9Du, 0xF8u, 0x00u, 0xBFu,
+    0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
+    0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x4Bu, 0x13u, 0xB1u,
+    0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x23u,
+    0x23u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xC4u, 0x20u, 0x00u, 0x00u,
     0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u,
     0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u,
-    0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u,
-    0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x0Cu, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
+    0x03u, 0x68u, 0x13u, 0xB1u, 0x05u, 0x4Bu, 0x03u, 0xB1u,
+    0x98u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xC4u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
     0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x36u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x22u, 0x10u,
-    0x01u, 0xF0u, 0xFEu, 0x02u, 0x83u, 0xF8u, 0x22u, 0x20u,
-    0x07u, 0x33u, 0x18u, 0x78u, 0x00u, 0xF0u, 0xFEu, 0x01u,
-    0x19u, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x03u, 0xF8u, 0x01u, 0x0Cu, 0x13u, 0xF8u,
-    0x02u, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
-    0x02u, 0x2Cu, 0x13u, 0xF8u, 0x04u, 0x0Cu, 0x00u, 0xF0u,
-    0xFEu, 0x01u, 0x03u, 0xF8u, 0x04u, 0x1Cu, 0x13u, 0xF8u,
-    0x06u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u,
-    0x06u, 0x0Cu, 0x13u, 0xF8u, 0x03u, 0x1Cu, 0x01u, 0xF0u,
-    0xFEu, 0x02u, 0x03u, 0xF8u, 0x03u, 0x2Cu, 0x13u, 0xF8u,
-    0x05u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u,
-    0x05u, 0x1Cu, 0x93u, 0xF8u, 0x2Cu, 0x20u, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x83u, 0xF8u, 0x2Cu, 0x00u, 0x2Bu, 0x33u,
-    0x19u, 0x78u, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u,
-    0x13u, 0xF8u, 0x01u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u,
-    0x03u, 0xF8u, 0x01u, 0x1Cu, 0x13u, 0xF8u, 0x02u, 0x2Cu,
-    0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u, 0x02u, 0x0Cu,
-    0x13u, 0xF8u, 0x0Bu, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u,
-    0x03u, 0xF8u, 0x0Bu, 0x2Cu, 0x13u, 0xF8u, 0x0Cu, 0x0Cu,
-    0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u, 0x0Cu, 0x1Cu,
-    0x13u, 0xF8u, 0x0Du, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u,
-    0x03u, 0xF8u, 0x0Du, 0x0Cu, 0x13u, 0xF8u, 0x0Eu, 0x1Cu,
-    0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Eu, 0x2Cu,
-    0x13u, 0xF8u, 0x0Fu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u,
-    0x03u, 0xF8u, 0x0Fu, 0x1Cu, 0x00u, 0xF0u, 0x9Eu, 0xFBu,
-    0xFEu, 0xE7u, 0x00u, 0xBFu, 0x00u, 0x50u, 0x00u, 0x40u,
-    0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u,
-    0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u,
-    0x10u, 0x6Cu, 0x53u, 0xF8u, 0x0Cu, 0x0Cu, 0x53u, 0xF8u,
-    0x08u, 0x5Cu, 0x00u, 0x22u, 0xAAu, 0x42u, 0x00u, 0xEBu,
-    0x02u, 0x04u, 0x03u, 0xD0u, 0xB4u, 0x58u, 0x84u, 0x50u,
-    0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu,
-    0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u,
-    0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u,
-    0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xF6u, 0xFEu,
-    0xFFu, 0xF7u, 0x6Au, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x22u, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u,
-    0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,
-    0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au,
-    0x0Du, 0x49u, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Du, 0x4Au,
-    0x42u, 0xF8u, 0x23u, 0x10u, 0x01u, 0x33u, 0x30u, 0x2Bu,
-    0xF3u, 0xD1u, 0x0Bu, 0x49u, 0x0Bu, 0x4Bu, 0x08u, 0x78u,
-    0x0Bu, 0x49u, 0x18u, 0x70u, 0x0Au, 0x60u, 0x00u, 0xF0u,
-    0x17u, 0xF8u, 0x0Au, 0x48u, 0x00u, 0x22u, 0x02u, 0x60u,
+    0x08u, 0xB5u, 0x35u, 0x4Bu, 0x1Au, 0x78u, 0x07u, 0x33u,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x07u, 0x2Cu,
+    0xDAu, 0x7Eu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0xDAu, 0x76u,
+    0x1Au, 0x78u, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u,
+    0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x03u, 0xF8u, 0x01u, 0x2Cu, 0x13u, 0xF8u, 0x02u, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x02u, 0x2Cu,
+    0x13u, 0xF8u, 0x04u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x03u, 0xF8u, 0x04u, 0x2Cu, 0x13u, 0xF8u, 0x06u, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x06u, 0x2Cu,
+    0x13u, 0xF8u, 0x03u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x03u, 0xF8u, 0x03u, 0x2Cu, 0x13u, 0xF8u, 0x05u, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x05u, 0x2Cu,
+    0x93u, 0xF8u, 0x2Cu, 0x20u, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x83u, 0xF8u, 0x2Cu, 0x20u, 0x2Bu, 0x33u, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u, 0x13u, 0xF8u,
+    0x01u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+    0x01u, 0x2Cu, 0x13u, 0xF8u, 0x02u, 0x2Cu, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x03u, 0xF8u, 0x02u, 0x2Cu, 0x13u, 0xF8u,
+    0x0Bu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+    0x0Bu, 0x2Cu, 0x13u, 0xF8u, 0x0Cu, 0x2Cu, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Cu, 0x2Cu, 0x13u, 0xF8u,
+    0x0Du, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+    0x0Du, 0x2Cu, 0x13u, 0xF8u, 0x0Eu, 0x2Cu, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Eu, 0x2Cu, 0x13u, 0xF8u,
+    0x0Fu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+    0x0Fu, 0x2Cu, 0x00u, 0xF0u, 0xE1u, 0xFBu, 0xFEu, 0xE7u,
+    0x00u, 0x50u, 0x00u, 0x40u, 0xFEu, 0xE7u, 0x00u, 0x00u,
+    0x08u, 0xB5u, 0x12u, 0x49u, 0x12u, 0x4Bu, 0x4Au, 0x1Cu,
+    0x1Au, 0xD0u, 0x53u, 0xF8u, 0x10u, 0x6Cu, 0x53u, 0xF8u,
+    0x0Cu, 0x0Cu, 0x53u, 0xF8u, 0x08u, 0x5Cu, 0x00u, 0x22u,
+    0xAAu, 0x42u, 0x00u, 0xEBu, 0x02u, 0x04u, 0x03u, 0xD0u,
+    0xB4u, 0x58u, 0x84u, 0x50u, 0x04u, 0x32u, 0xF7u, 0xE7u,
+    0x53u, 0xF8u, 0x04u, 0x0Cu, 0x00u, 0x22u, 0x82u, 0x42u,
+    0x03u, 0xD0u, 0x00u, 0x25u, 0xA5u, 0x50u, 0x04u, 0x32u,
+    0xF9u, 0xE7u, 0x10u, 0x33u, 0x01u, 0x39u, 0xE2u, 0xE7u,
+    0x01u, 0xF0u, 0x54u, 0xFFu, 0xFFu, 0xF7u, 0x6Cu, 0xFFu,
+    0xFEu, 0xE7u, 0x00u, 0xBFu, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x14u, 0x23u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x11u, 0x4Au,
+    0x11u, 0x4Bu, 0x1Au, 0x60u, 0x9Au, 0x68u, 0x42u, 0xF4u,
+    0x00u, 0x72u, 0x9Au, 0x60u, 0x00u, 0x23u, 0x03u, 0x2Bu,
+    0x98u, 0xBFu, 0x0Eu, 0x4Au, 0x4Fu, 0xEAu, 0x83u, 0x00u,
+    0x94u, 0xBFu, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Cu, 0x49u,
+    0x0Cu, 0x4Au, 0x01u, 0x33u, 0x30u, 0x2Bu, 0x11u, 0x50u,
+    0xF1u, 0xD1u, 0x0Bu, 0x4Bu, 0x19u, 0x78u, 0x0Bu, 0x4Bu,
+    0x19u, 0x70u, 0x0Bu, 0x4Bu, 0x1Au, 0x60u, 0x00u, 0xF0u,
+    0x17u, 0xF8u, 0x0Au, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x60u,
     0x08u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x04u, 0xFAu, 0x05u,
     0x0Cu, 0xEDu, 0x00u, 0xE0u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x61u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,
+    0x5Du, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,
     0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu,
     0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu,
-    0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Fu, 0x4Bu, 0x01u, 0x22u,
-    0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u,
-    0x06u, 0x20u, 0x52u, 0x24u, 0x5Cu, 0x4Eu, 0x1Au, 0x70u,
-    0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x5Bu, 0x4Bu,
-    0x5Bu, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u,
-    0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u,
-    0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x57u, 0x4Eu,
-    0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u,
-    0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,
-    0x6Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
-    0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x50u, 0x48u,
-    0x50u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,
-    0x4Fu, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,
-    0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u,
-    0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu,
-    0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u,
-    0x00u, 0xE0u, 0xFEu, 0xE7u, 0x47u, 0x4Fu, 0x06u, 0x21u,
-    0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u,
-    0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x9Du, 0xFEu,
-    0x08u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u,
-    0x41u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,
-    0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu,
-    0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u,
-    0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u,
-    0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u,
-    0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u,
-    0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x35u, 0x4Cu,
-    0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u,
-    0x21u, 0x7Cu, 0x33u, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u,
-    0x32u, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u,
-    0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x30u, 0x4Au,
-    0x43u, 0xF0u, 0x10u, 0x04u, 0x2Fu, 0x4Bu, 0x04u, 0x70u,
-    0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x54u, 0x60u,
-    0x1Au, 0x46u, 0x2Du, 0x48u, 0x52u, 0xF8u, 0x08u, 0x4Fu,
-    0x04u, 0x60u, 0x54u, 0x68u, 0x12u, 0x89u, 0x44u, 0x60u,
-    0x02u, 0x81u, 0x1Au, 0x46u, 0x52u, 0xF8u, 0x12u, 0x4Fu,
-    0x40u, 0xF8u, 0xC0u, 0x4Cu, 0x54u, 0x68u, 0x12u, 0x89u,
-    0x40u, 0xF8u, 0xBCu, 0x4Cu, 0x20u, 0xF8u, 0xB8u, 0x2Cu,
-    0x1Au, 0x46u, 0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u,
-    0x40u, 0xF8u, 0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu,
-    0x53u, 0xF8u, 0x24u, 0x0Fu, 0x1Fu, 0x4Au, 0x5Bu, 0x68u,
-    0x10u, 0x60u, 0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u,
-    0x42u, 0xF0u, 0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u,
-    0x1Du, 0x4Au, 0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u,
-    0x1Bu, 0x09u, 0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au,
-    0x44u, 0x20u, 0x10u, 0x70u, 0x1Au, 0x4Au, 0x0Bu, 0x46u,
-    0x0Cu, 0x31u, 0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u,
-    0x42u, 0xF8u, 0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u,
-    0x11u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0x48u, 0x00u, 0x40u,
-    0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u,
-    0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u,
-    0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u,
-    0xE8u, 0x46u, 0x00u, 0x40u, 0x10u, 0x20u, 0x00u, 0x00u,
-    0x40u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,
-    0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u,
-    0x02u, 0x51u, 0x00u, 0x40u, 0x9Eu, 0x20u, 0x00u, 0x00u,
-    0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u,
-    0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u,
-    0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u,
-    0xB0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x00u,
-    0x43u, 0x1Eu, 0x10u, 0xB5u, 0x02u, 0x46u, 0x06u, 0x2Bu,
-    0x0Du, 0xD8u, 0xDFu, 0xE8u, 0x03u, 0xF0u, 0x06u, 0x0Eu,
-    0x23u, 0x04u, 0x08u, 0x0Au, 0x21u, 0x00u, 0x16u, 0x48u,
-    0x08u, 0xE0u, 0x16u, 0x4Bu, 0x1Bu, 0xE0u, 0x16u, 0x48u,
-    0x04u, 0xE0u, 0x16u, 0x48u, 0x02u, 0xE0u, 0x00u, 0x20u,
-    0x00u, 0xE0u, 0x15u, 0x48u, 0x41u, 0x78u, 0x00u, 0x78u,
-    0x41u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x2Au, 0x04u, 0xD0u,
-    0x03u, 0x2Au, 0x07u, 0xD0u, 0x01u, 0x2Au, 0x15u, 0xD1u,
-    0x04u, 0xE0u, 0x02u, 0x02u, 0x42u, 0xEAu, 0x10u, 0x23u,
-    0x98u, 0xB2u, 0x10u, 0xBDu, 0x00u, 0xBAu, 0x10u, 0xBDu,
-    0x0Cu, 0x4Bu, 0x00u, 0xE0u, 0x0Cu, 0x4Bu, 0xD8u, 0x78u,
-    0x9Cu, 0x78u, 0x59u, 0x78u, 0x1Bu, 0x78u, 0x40u, 0xEAu,
-    0x03u, 0x60u, 0x40u, 0xEAu, 0x04u, 0x23u, 0x43u, 0xEAu,
-    0x01u, 0x40u, 0xE3u, 0xE7u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0xD2u, 0xFFu, 0x01u, 0x00u, 0xC1u, 0xFFu, 0x01u, 0x00u,
-    0xD6u, 0xFFu, 0x01u, 0x00u, 0xD4u, 0xFFu, 0x01u, 0x00u,
-    0xC5u, 0xFFu, 0x01u, 0x00u, 0xD8u, 0xFFu, 0x01u, 0x00u,
-    0xC9u, 0xFFu, 0x01u, 0x00u, 0x70u, 0xB5u, 0x02u, 0x20u,
-    0xFFu, 0xF7u, 0xB6u, 0xFFu, 0x06u, 0x46u, 0x03u, 0x20u,
-    0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x71u, 0x1Cu, 0x00u, 0xEBu,
-    0x01u, 0x26u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xACu, 0xFFu,
-    0x00u, 0x24u, 0x01u, 0x30u, 0x01u, 0x02u, 0x25u, 0x46u,
-    0xB1u, 0x42u, 0x09u, 0xD2u, 0x11u, 0xF8u, 0x01u, 0x0Bu,
-    0x42u, 0x1Eu, 0xD3u, 0xB2u, 0x04u, 0x19u, 0xFDu, 0x2Bu,
-    0x98u, 0xBFu, 0x01u, 0x25u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,
-    0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x0Fu, 0x49u,
-    0x42u, 0x1Cu, 0x13u, 0x02u, 0xDBu, 0x08u, 0x8Eu, 0x42u,
-    0x01u, 0xD0u, 0xF6u, 0x08u, 0x01u, 0xE0u, 0x4Fu, 0xF4u,
-    0x80u, 0x46u, 0xB3u, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,
-    0x90u, 0x41u, 0x08u, 0x78u, 0x01u, 0x33u, 0x02u, 0x19u,
-    0xD4u, 0xB2u, 0xF6u, 0xE7u, 0x05u, 0x48u, 0x64u, 0x42u,
-    0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u,
-    0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u,
-    0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u,
-    0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du,
-    0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u,
-    0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u,
-    0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u,
-    0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u,
-    0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u,
-    0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,
-    0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u,
-    0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u,
-    0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u,
-    0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u,
-    0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu,
-    0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u,
-    0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu,
-    0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u,
-    0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u,
-    0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u,
-    0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,
-    0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu,
-    0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,
-    0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u,
-    0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u,
-    0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du,
-    0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u,
-    0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u,
-    0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u,
-    0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u,
-    0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u,
-    0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u,
-    0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u,
-    0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u,
-    0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu,
-    0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u,
-    0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u,
-    0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u,
-    0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u,
-    0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u,
-    0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u,
-    0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
-    0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u,
-    0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u,
-    0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u,
-    0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u,
-    0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu,
-    0x9Du, 0x06u, 0x00u, 0x00u, 0xC1u, 0x05u, 0x00u, 0x00u,
-    0x57u, 0x08u, 0x00u, 0x00u, 0xBBu, 0x06u, 0x00u, 0x00u,
-    0x6Du, 0x07u, 0x00u, 0x00u, 0x57u, 0x08u, 0x00u, 0x00u,
-    0x73u, 0x07u, 0x00u, 0x00u, 0x91u, 0x07u, 0x00u, 0x00u,
-    0xBBu, 0x06u, 0x00u, 0x00u, 0xABu, 0x07u, 0x00u, 0x00u,
-    0x37u, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
-    0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u,
-    0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u,
-    0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u,
-    0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,
-    0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u,
-    0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu,
-    0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u,
-    0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u,
-    0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
-    0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u,
-    0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u,
-    0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu,
-    0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u,
-    0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u,
-    0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u,
-    0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,
-    0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u,
-    0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u,
-    0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u,
-    0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u,
-    0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu,
-    0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u,
-    0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u,
-    0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u,
-    0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u,
-    0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,
-    0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u,
-    0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u,
-    0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u,
-    0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u,
-    0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu,
-    0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u,
-    0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u,
-    0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du,
-    0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u,
-    0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au,
-    0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u,
-    0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u,
-    0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u,
-    0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u,
-    0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u,
-    0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u,
-    0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu,
-    0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu,
-    0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u,
-    0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u,
-    0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du,
-    0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u,
-    0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u,
-    0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u,
-    0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u,
-    0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u,
-    0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u,
-    0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u,
-    0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u,
-    0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u,
-    0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u,
-    0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u,
-    0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u,
-    0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,
-    0xCCu, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,
-    0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,
-    0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u,
-    0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u,
-    0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u,
-    0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,
-    0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,
-    0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u,
-    0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u,
-    0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u,
-    0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,
-    0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu,
-    0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,
-    0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,
-    0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,
-    0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,
-    0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
-    0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u,
-    0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,
-    0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Bu, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x70u, 0x06u, 0x22u, 0xA3u, 0xF5u, 0xA0u, 0x63u,
+    0x1Au, 0x70u, 0x52u, 0x22u, 0xA3u, 0xF5u, 0x80u, 0x73u,
+    0x1Au, 0x70u, 0x57u, 0x4Bu, 0x19u, 0x25u, 0x1Au, 0x78u,
+    0x56u, 0x4Bu, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x40u, 0xF6u,
+    0x18u, 0x02u, 0xA3u, 0xF2u, 0x7Fu, 0x43u, 0x1Au, 0x80u,
+    0x41u, 0xF2u, 0x51u, 0x22u, 0x23u, 0xF8u, 0x02u, 0x2Cu,
+    0x00u, 0x24u, 0x51u, 0x4Bu, 0x4Fu, 0xF4u, 0xF0u, 0x70u,
+    0x1Bu, 0x78u, 0x03u, 0xF0u, 0x01u, 0x03u, 0x43u, 0xEAu,
+    0x44u, 0x04u, 0x00u, 0xF0u, 0x89u, 0xFBu, 0x01u, 0x3Du,
+    0x04u, 0xF0u, 0x03u, 0x04u, 0x18u, 0xD0u, 0x03u, 0x2Cu,
+    0xEFu, 0xD1u, 0x4Au, 0x4Bu, 0x4Fu, 0xF4u, 0x80u, 0x72u,
+    0x1Au, 0x80u, 0x07u, 0x22u, 0x1Au, 0x70u, 0x48u, 0x4Au,
+    0x00u, 0x24u, 0x48u, 0x21u, 0x14u, 0x70u, 0x91u, 0x70u,
+    0x02u, 0x22u, 0x1Cu, 0x70u, 0x5Cu, 0x71u, 0x03u, 0xF8u,
+    0x03u, 0x2Cu, 0x93u, 0xF8u, 0xE4u, 0x26u, 0x42u, 0xF0u,
+    0x04u, 0x02u, 0x83u, 0xF8u, 0xE4u, 0x26u, 0x00u, 0xE0u,
+    0xFEu, 0xE7u, 0x40u, 0x4Bu, 0x00u, 0x21u, 0x23u, 0x44u,
+    0x18u, 0x68u, 0x9Au, 0x88u, 0x06u, 0x34u, 0x01u, 0xF0u,
+    0xF8u, 0xFEu, 0x30u, 0x2Cu, 0xF5u, 0xD1u, 0x00u, 0x23u,
+    0x19u, 0x46u, 0x3Bu, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u,
+    0x30u, 0x34u, 0x20u, 0xF0u, 0xFFu, 0x06u, 0xC0u, 0xB2u,
+    0x45u, 0x00u, 0x04u, 0xEBu, 0x41u, 0x04u, 0xAAu, 0x42u,
+    0x08u, 0xD0u, 0x04u, 0xEBu, 0x02u, 0x0Cu, 0xA7u, 0x5Cu,
+    0x9Cu, 0xF8u, 0x01u, 0xC0u, 0x02u, 0x32u, 0x07u, 0xF8u,
+    0x06u, 0xC0u, 0xF4u, 0xE7u, 0x04u, 0x33u, 0x30u, 0x2Bu,
+    0x01u, 0x44u, 0xE6u, 0xD1u, 0x2Fu, 0x4Bu, 0x30u, 0x48u,
+    0x1Au, 0x78u, 0x30u, 0x4Cu, 0x42u, 0xF0u, 0x02u, 0x02u,
+    0x1Au, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u, 0x02u, 0x02u,
+    0x1Au, 0x74u, 0xA3u, 0xF5u, 0x86u, 0x33u, 0x63u, 0x3Bu,
+    0x1Au, 0x78u, 0x42u, 0xF0u, 0x40u, 0x02u, 0x1Au, 0x70u,
+    0x29u, 0x4Au, 0x11u, 0x78u, 0x41u, 0xF0u, 0x10u, 0x01u,
+    0x11u, 0x70u, 0x28u, 0x4Au, 0x11u, 0x68u, 0x15u, 0x46u,
+    0x01u, 0x60u, 0x51u, 0x68u, 0x41u, 0x60u, 0x55u, 0xF8u,
+    0x08u, 0x0Fu, 0x69u, 0x68u, 0x03u, 0xC4u, 0x29u, 0x89u,
+    0x15u, 0x46u, 0x55u, 0xF8u, 0x12u, 0x0Fu, 0x21u, 0x80u,
+    0x69u, 0x68u, 0xC8u, 0x3Cu, 0x03u, 0xC4u, 0x29u, 0x89u,
+    0x10u, 0x46u, 0x21u, 0x80u, 0x50u, 0xF8u, 0x1Cu, 0x1Fu,
+    0xA4u, 0xF6u, 0x88u, 0x54u, 0xC4u, 0xF8u, 0x92u, 0x1Du,
+    0x41u, 0x68u, 0x1Bu, 0x48u, 0xC4u, 0xF8u, 0x96u, 0x1Du,
+    0x52u, 0xF8u, 0x24u, 0x1Fu, 0x01u, 0x60u, 0x51u, 0x68u,
+    0x18u, 0x4Au, 0x41u, 0x60u, 0x11u, 0x78u, 0x41u, 0xF0u,
+    0x08u, 0x01u, 0x11u, 0x70u, 0x16u, 0x4Au, 0x17u, 0x49u,
+    0x12u, 0x78u, 0xD2u, 0xB2u, 0x02u, 0xF0u, 0x07u, 0x00u,
+    0x12u, 0x09u, 0x08u, 0x70u, 0x4Au, 0x70u, 0x14u, 0x4Au,
+    0x44u, 0x21u, 0x11u, 0x70u, 0x0Fu, 0xCBu, 0x07u, 0xC4u,
+    0x23u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0x48u, 0x00u, 0x40u,
+    0x0Fu, 0x01u, 0x00u, 0x49u, 0xA1u, 0x46u, 0x00u, 0x40u,
+    0x25u, 0x42u, 0x00u, 0x40u, 0x04u, 0x40u, 0x00u, 0x40u,
+    0x06u, 0x40u, 0x00u, 0x40u, 0xC8u, 0x20u, 0x00u, 0x00u,
+    0xF8u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,
+    0x02u, 0x51u, 0x00u, 0x40u, 0xF0u, 0x51u, 0x00u, 0x40u,
+    0xC2u, 0x43u, 0x00u, 0x40u, 0x56u, 0x21u, 0x00u, 0x00u,
+    0x62u, 0x51u, 0x00u, 0x40u, 0x22u, 0x43u, 0x00u, 0x40u,
+    0xCFu, 0x01u, 0x00u, 0x49u, 0x6Eu, 0x58u, 0x00u, 0x40u,
+    0x76u, 0x58u, 0x00u, 0x40u, 0x00u, 0x47u, 0x10u, 0xB5u,
+    0x00u, 0x23u, 0x2Au, 0xB1u, 0x01u, 0x3Au, 0x44u, 0x18u,
+    0xA4u, 0x5Cu, 0x23u, 0x44u, 0xDBu, 0xB2u, 0xF8u, 0xE7u,
+    0x18u, 0x46u, 0x10u, 0xBDu, 0x01u, 0x38u, 0x09u, 0x28u,
+    0x42u, 0xD8u, 0xDFu, 0xE8u, 0x00u, 0xF0u, 0x05u, 0x0Bu,
+    0x11u, 0x17u, 0x1Du, 0x23u, 0x2Fu, 0x29u, 0x35u, 0x3Bu,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+    0xE0u, 0x71u, 0x3Bu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF2u, 0xC1u, 0x11u, 0x38u, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+    0xC5u, 0x11u, 0x2Au, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF2u, 0xC9u, 0x11u, 0x2Cu, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+    0xE8u, 0x71u, 0x23u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF2u, 0xD1u, 0x11u, 0x1Du, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+    0xEBu, 0x71u, 0x12u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF5u, 0xE9u, 0x71u, 0x0Cu, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+    0xEAu, 0x71u, 0x06u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF5u, 0xECu, 0x71u, 0x08u, 0xE0u,
+    0x00u, 0x21u, 0x0Bu, 0x78u, 0x48u, 0x78u, 0x43u, 0xEAu,
+    0x00u, 0x20u, 0x70u, 0x47u, 0x08u, 0x78u, 0xC0u, 0xB2u,
+    0x70u, 0x47u, 0x0Bu, 0x78u, 0x4Au, 0x78u, 0x88u, 0x78u,
+    0x00u, 0x04u, 0x40u, 0xEAu, 0x02u, 0x20u, 0x18u, 0x43u,
+    0xCBu, 0x78u, 0x40u, 0xEAu, 0x03u, 0x60u, 0x70u, 0x47u,
+    0x10u, 0xB5u, 0x0Bu, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,
+    0xC0u, 0x02u, 0x80u, 0x2Au, 0x0Eu, 0xD1u, 0x00u, 0x24u,
+    0x1Cu, 0x70u, 0x02u, 0x20u, 0x21u, 0x46u, 0xFFu, 0xF7u,
+    0x99u, 0xFFu, 0x38u, 0xB1u, 0x21u, 0x46u, 0x02u, 0x20u,
+    0xFFu, 0xF7u, 0x94u, 0xFFu, 0xBDu, 0xE8u, 0x10u, 0x40u,
+    0xFFu, 0xF7u, 0x84u, 0xBFu, 0x10u, 0xBDu, 0x00u, 0xBFu,
+    0xFAu, 0x46u, 0x00u, 0x40u, 0xF8u, 0xB5u, 0x05u, 0x46u,
+    0x29u, 0x46u, 0x03u, 0x20u, 0xFFu, 0xF7u, 0x86u, 0xFFu,
+    0x29u, 0x46u, 0x07u, 0x46u, 0x04u, 0x20u, 0xFFu, 0xF7u,
+    0x81u, 0xFFu, 0x01u, 0x37u, 0x00u, 0xEBu, 0x07u, 0x27u,
+    0x29u, 0x46u, 0x03u, 0x20u, 0xFFu, 0xF7u, 0x7Au, 0xFFu,
+    0x00u, 0x24u, 0x01u, 0x30u, 0x00u, 0x02u, 0x26u, 0x46u,
+    0xB8u, 0x42u, 0x09u, 0xD2u, 0x10u, 0xF8u, 0x01u, 0x3Bu,
+    0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0xFDu, 0x2Au, 0x1Cu, 0x44u,
+    0x98u, 0xBFu, 0x01u, 0x26u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,
+    0x03u, 0x20u, 0x29u, 0x46u, 0xFFu, 0xF7u, 0x66u, 0xFFu,
+    0x11u, 0x4Au, 0x01u, 0x30u, 0x97u, 0x42u, 0x4Fu, 0xEAu,
+    0x00u, 0x23u, 0x4Fu, 0xEAu, 0xD3u, 0x03u, 0x14u, 0xBFu,
+    0xFFu, 0x08u, 0x4Fu, 0xF4u, 0x80u, 0x47u, 0xBBu, 0x42u,
+    0x06u, 0xD2u, 0x03u, 0xF1u, 0x90u, 0x42u, 0x12u, 0x78u,
+    0x01u, 0x33u, 0x14u, 0x44u, 0xE4u, 0xB2u, 0xF6u, 0xE7u,
+    0x01u, 0x20u, 0x29u, 0x46u, 0xFFu, 0xF7u, 0x4Eu, 0xFFu,
+    0x64u, 0x42u, 0xE4u, 0xB2u, 0x84u, 0x42u, 0x04u, 0xD1u,
+    0x00u, 0x2Eu, 0x14u, 0xBFu, 0x00u, 0x20u, 0x06u, 0x20u,
+    0xF8u, 0xBDu, 0x06u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu,
+    0xC0u, 0xFFu, 0x01u, 0x00u, 0x2Du, 0xE9u, 0xF0u, 0x4Fu,
+    0xADu, 0xF5u, 0x1Bu, 0x7Du, 0x80u, 0x46u, 0x00u, 0xF0u,
+    0x13u, 0xFAu, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,
+    0xDFu, 0xFAu, 0x00u, 0xF0u, 0x39u, 0xFCu, 0x62u, 0xB6u,
+    0x00u, 0x26u, 0x4Fu, 0xF0u, 0x0Au, 0x09u, 0x35u, 0x46u,
+    0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x14u, 0xBFu, 0x43u, 0x46u,
+    0xFFu, 0x23u, 0x04u, 0xA8u, 0x4Fu, 0xF4u, 0x96u, 0x71u,
+    0x01u, 0xAAu, 0x00u, 0xF0u, 0x59u, 0xFCu, 0xB8u, 0xF1u,
+    0x00u, 0x0Fu, 0x03u, 0xD0u, 0x09u, 0xF1u, 0xFFu, 0x39u,
+    0x5Fu, 0xFAu, 0x89u, 0xF9u, 0xB9u, 0xF1u, 0x00u, 0x0Fu,
+    0x02u, 0xD0u, 0x00u, 0x28u, 0xE8u, 0xD1u, 0x01u, 0xE0u,
+    0x00u, 0x28u, 0x78u, 0xD1u, 0xBDu, 0xF8u, 0x04u, 0x20u,
+    0x06u, 0x2Au, 0x40u, 0xF2u, 0x89u, 0x81u, 0x9Du, 0xF8u,
+    0x10u, 0x30u, 0x01u, 0x2Bu, 0x40u, 0xF0u, 0x84u, 0x81u,
+    0x9Du, 0xF8u, 0x12u, 0x30u, 0x9Du, 0xF8u, 0x13u, 0x40u,
+    0x43u, 0xEAu, 0x04u, 0x24u, 0xE7u, 0x1Du, 0x04u, 0xABu,
+    0x23u, 0x44u, 0x97u, 0x42u, 0x58u, 0x79u, 0x19u, 0x79u,
+    0x00u, 0xF2u, 0x74u, 0x81u, 0x9Bu, 0x79u, 0x17u, 0x2Bu,
+    0x40u, 0xF0u, 0x72u, 0x81u, 0x23u, 0x1Du, 0x9Bu, 0xB2u,
+    0x00u, 0x22u, 0x3Bu, 0xB1u, 0x0Du, 0xF1u, 0x0Fu, 0x07u,
+    0xFFu, 0x5Cu, 0x01u, 0x3Bu, 0x3Au, 0x44u, 0x92u, 0xB2u,
+    0x9Bu, 0xB2u, 0xF6u, 0xE7u, 0x52u, 0x42u, 0x41u, 0xEAu,
+    0x00u, 0x23u, 0x92u, 0xB2u, 0x93u, 0x42u, 0x40u, 0xF0u,
+    0x61u, 0x81u, 0x51u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
+    0x5Bu, 0x81u, 0x01u, 0x2Cu, 0x40u, 0xF0u, 0x58u, 0x81u,
+    0x01u, 0x2Fu, 0x00u, 0xF2u, 0x55u, 0x81u, 0xB2u, 0x4Bu,
+    0x1Bu, 0x68u, 0x1Bu, 0x68u, 0xC3u, 0xF3u, 0x07u, 0x42u,
+    0x97u, 0x42u, 0x73u, 0xD1u, 0xC3u, 0xF3u, 0x07u, 0x23u,
+    0x8Du, 0xF8u, 0x14u, 0x30u, 0x1Bu, 0x0Au, 0x8Du, 0xF8u,
+    0x15u, 0x30u, 0x00u, 0x24u, 0xFFu, 0x23u, 0x8Du, 0xF8u,
+    0x16u, 0x30u, 0x8Du, 0xF8u, 0x17u, 0x40u, 0x04u, 0x21u,
+    0x01u, 0x23u, 0x8Du, 0xF8u, 0x10u, 0x30u, 0x00u, 0x22u,
+    0x0Bu, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x10u, 0x8Du, 0xF8u,
+    0x11u, 0x40u, 0x8Du, 0xF8u, 0x12u, 0x10u, 0x8Du, 0xF8u,
+    0x13u, 0x20u, 0x9Bu, 0xB2u, 0x0Du, 0xF1u, 0x0Fu, 0x00u,
+    0xC0u, 0x5Cu, 0x01u, 0x3Bu, 0x02u, 0x44u, 0x9Bu, 0xB2u,
+    0x92u, 0xB2u, 0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x52u, 0x42u,
+    0x92u, 0xB2u, 0x05u, 0xABu, 0x5Au, 0x54u, 0x12u, 0x0Au,
+    0x0Du, 0xF1u, 0x15u, 0x03u, 0x5Au, 0x54u, 0x17u, 0x22u,
+    0x0Du, 0xF1u, 0x16u, 0x03u, 0x5Au, 0x54u, 0x07u, 0x31u,
+    0x04u, 0xA8u, 0x89u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u,
+    0x96u, 0x23u, 0x00u, 0xF0u, 0xB0u, 0xFBu, 0xB8u, 0xF1u,
+    0x00u, 0x0Fu, 0x3Fu, 0xF4u, 0x69u, 0xAFu, 0x00u, 0x2Eu,
+    0x00u, 0xF0u, 0x19u, 0x81u, 0x01u, 0x26u, 0x63u, 0xE7u,
+    0x9Du, 0xF8u, 0x11u, 0x20u, 0x9Du, 0xF8u, 0x14u, 0x70u,
+    0xA2u, 0xF1u, 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u,
+    0xFEu, 0x80u, 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u,
+    0x15u, 0x07u, 0x00u, 0x00u, 0x2Du, 0x06u, 0x00u, 0x00u,
+    0xDFu, 0x08u, 0x00u, 0x00u, 0x3Fu, 0x07u, 0x00u, 0x00u,
+    0xEFu, 0x07u, 0x00u, 0x00u, 0xDFu, 0x08u, 0x00u, 0x00u,
+    0xF5u, 0x07u, 0x00u, 0x00u, 0x13u, 0x08u, 0x00u, 0x00u,
+    0x3Fu, 0x07u, 0x00u, 0x00u, 0x2Fu, 0x08u, 0x00u, 0x00u,
+    0xBDu, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
+    0xE7u, 0x80u, 0x00u, 0x2Cu, 0x40u, 0xF0u, 0xE4u, 0x80u,
+    0x20u, 0x46u, 0xFFu, 0xF7u, 0xDBu, 0xFEu, 0xD0u, 0xF1u,
+    0x01u, 0x00u, 0x38u, 0xBFu, 0x00u, 0x20u, 0x8Du, 0xF8u,
+    0x14u, 0x00u, 0xC1u, 0xE0u, 0x8Cu, 0xBFu, 0x00u, 0x23u,
+    0x4Fu, 0xF4u, 0x80u, 0x73u, 0x88u, 0xE7u, 0x34u, 0x2Au,
+    0x12u, 0xD1u, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xD0u, 0x80u,
+    0x03u, 0x2Cu, 0x40u, 0xF0u, 0xCDu, 0x80u, 0xA7u, 0xF1u,
+    0x40u, 0x03u, 0x3Fu, 0x2Bu, 0x8Cu, 0xBFu, 0x4Fu, 0xF4u,
+    0x90u, 0x75u, 0x10u, 0x25u, 0x4Fu, 0xA8u, 0x00u, 0x21u,
+    0x2Au, 0x46u, 0x01u, 0xF0u, 0xA2u, 0xFCu, 0x05u, 0xE0u,
+    0x00u, 0x2Eu, 0x00u, 0xF0u, 0xBDu, 0x80u, 0x02u, 0x2Cu,
+    0x40u, 0xF2u, 0xBAu, 0x80u, 0x03u, 0x3Cu, 0x4Fu, 0xA8u,
+    0x28u, 0x44u, 0x0Du, 0xF1u, 0x17u, 0x01u, 0x22u, 0x46u,
+    0x01u, 0xF0u, 0x8Au, 0xFCu, 0xA7u, 0xF1u, 0x40u, 0x03u,
+    0x25u, 0x44u, 0x3Fu, 0x2Bu, 0xADu, 0xB2u, 0x03u, 0xD8u,
+    0x00u, 0xF0u, 0xB4u, 0xF9u, 0x10u, 0x23u, 0x01u, 0xE0u,
+    0x4Fu, 0xF4u, 0x90u, 0x73u, 0x9Du, 0x42u, 0x40u, 0xF0u,
+    0x97u, 0x80u, 0x9Du, 0xF8u, 0x16u, 0x10u, 0x9Du, 0xF8u,
+    0x15u, 0x30u, 0x3Fu, 0x2Fu, 0x43u, 0xEAu, 0x01u, 0x21u,
+    0x0Fu, 0xD8u, 0x55u, 0x4Bu, 0x01u, 0xEBu, 0x07u, 0x22u,
+    0x1Bu, 0x68u, 0x92u, 0xB2u, 0x1Bu, 0x68u, 0xC3u, 0xF3u,
+    0x0Fu, 0x20u, 0x13u, 0xF0u, 0xFFu, 0x0Fu, 0x1Cu, 0xBFu,
+    0x01u, 0x30u, 0x80u, 0xB2u, 0x82u, 0x42u, 0xC0u, 0xF0u,
+    0x82u, 0x80u, 0x2Bu, 0x46u, 0x4Fu, 0xAAu, 0x38u, 0x46u,
+    0x00u, 0xF0u, 0x2Eu, 0xF9u, 0x00u, 0x28u, 0x0Cu, 0xBFu,
+    0x00u, 0x24u, 0x0Au, 0x24u, 0x01u, 0x26u, 0x00u, 0xF0u,
+    0xD5u, 0xF9u, 0x00u, 0x25u, 0x78u, 0xE0u, 0x00u, 0x2Eu,
+    0x7Au, 0xD0u, 0x7Du, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,
+    0x2Fu, 0x19u, 0xB7u, 0xF5u, 0x96u, 0x7Fu, 0x71u, 0xD8u,
+    0x4Fu, 0xA8u, 0x28u, 0x44u, 0x22u, 0x46u, 0x05u, 0xA9u,
+    0x01u, 0xF0u, 0x46u, 0xFCu, 0xBDu, 0xB2u, 0x00u, 0x24u,
+    0x66u, 0xE0u, 0x00u, 0x2Cu, 0x68u, 0xD1u, 0x3Du, 0x4Au,
+    0x02u, 0xABu, 0x92u, 0xE8u, 0x03u, 0x00u, 0x05u, 0xAAu,
+    0x83u, 0xE8u, 0x03u, 0x00u, 0x82u, 0xE8u, 0x03u, 0x00u,
+    0x01u, 0x26u, 0x08u, 0x21u, 0x1Cu, 0xE7u, 0x00u, 0x2Eu,
+    0x5Au, 0xD0u, 0x03u, 0x2Cu, 0x58u, 0xD1u, 0x9Du, 0xF8u,
+    0x15u, 0x30u, 0x9Du, 0xF8u, 0x16u, 0xA0u, 0x43u, 0xEAu,
+    0x0Au, 0x2Au, 0xA7u, 0xF1u, 0x40u, 0x03u, 0x3Fu, 0x2Bu,
+    0x07u, 0xD8u, 0x31u, 0x48u, 0x4Fu, 0xEAu, 0x0Au, 0x11u,
+    0x10u, 0x22u, 0xFFu, 0xF7u, 0xC4u, 0xFDu, 0x04u, 0x46u,
+    0x2Au, 0xE0u, 0x4Fu, 0xEAu, 0x07u, 0x2Bu, 0x0Au, 0xEBu,
+    0x0Bu, 0x01u, 0x00u, 0x20u, 0x09u, 0x02u, 0x4Fu, 0xF4u,
+    0x80u, 0x72u, 0xFFu, 0xF7u, 0xB8u, 0xFDu, 0x3Fu, 0x2Fu,
+    0x04u, 0x46u, 0x1Du, 0xD8u, 0x0Bu, 0xF1u, 0x10u, 0x7Bu,
+    0xD3u, 0x44u, 0x4Fu, 0xEAu, 0x4Bu, 0x1Bu, 0x00u, 0x23u,
+    0x13u, 0xF8u, 0x0Bu, 0x20u, 0x01u, 0x33u, 0x14u, 0x44u,
+    0x20u, 0x2Bu, 0xE4u, 0xB2u, 0xF8u, 0xD1u, 0x01u, 0x2Fu,
+    0x0Eu, 0xD1u, 0xBAu, 0xF1u, 0xFFu, 0x0Fu, 0x0Bu, 0xD1u,
+    0x00u, 0x21u, 0x05u, 0x20u, 0xFFu, 0xF7u, 0xAAu, 0xFDu,
+    0x20u, 0x1Au, 0xC4u, 0xB2u, 0x00u, 0x21u, 0x06u, 0x20u,
+    0xFFu, 0xF7u, 0xA4u, 0xFDu, 0x20u, 0x1Au, 0xC4u, 0xB2u,
+    0x64u, 0x42u, 0x8Du, 0xF8u, 0x14u, 0x40u, 0x00u, 0x24u,
+    0x01u, 0x21u, 0xD5u, 0xE6u, 0x00u, 0x20u, 0xFFu, 0xF7u,
+    0x0Du, 0xFEu, 0x10u, 0xB9u, 0x13u, 0x4Bu, 0x80u, 0x22u,
+    0x1Au, 0x70u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x0Bu, 0xE0u,
+    0x01u, 0x26u, 0x00u, 0x25u, 0x06u, 0xE0u, 0x01u, 0x26u,
+    0x00u, 0x25u, 0x0Au, 0x24u, 0x00u, 0xE0u, 0x05u, 0x24u,
+    0x00u, 0x21u, 0xC1u, 0xE6u, 0x03u, 0x24u, 0xFBu, 0xE7u,
+    0x04u, 0x24u, 0xF9u, 0xE7u, 0x08u, 0x24u, 0xF7u, 0xE7u,
+    0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x45u, 0x46u,
+    0x4Eu, 0xE6u, 0x00u, 0x25u, 0xE6u, 0xE6u, 0x0Du, 0xF5u,
+    0x1Bu, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,
+    0x0Cu, 0xC1u, 0xFFu, 0x1Fu, 0x84u, 0x21u, 0x00u, 0x00u,
+    0x00u, 0x80u, 0x00u, 0x40u, 0xFAu, 0x46u, 0x00u, 0x40u,
+    0x70u, 0xB5u, 0x00u, 0x20u, 0xFFu, 0xF7u, 0xDEu, 0xFDu,
+    0x15u, 0x4Du, 0x00u, 0x28u, 0x2Bu, 0x68u, 0x4Fu, 0xF0u,
+    0x00u, 0x00u, 0x1Cu, 0x68u, 0x01u, 0x46u, 0x22u, 0x46u,
+    0x0Cu, 0xBFu, 0x00u, 0x26u, 0x06u, 0x26u, 0xFFu, 0xF7u,
+    0x52u, 0xFDu, 0x6Bu, 0x68u, 0x1Bu, 0x78u, 0x18u, 0x1Au,
+    0x00u, 0xF0u, 0xFFu, 0x00u, 0x98u, 0x42u, 0x00u, 0xD1u,
+    0x14u, 0xB9u, 0x00u, 0x20u, 0x00u, 0xF0u, 0xFCu, 0xF8u,
+    0x0Au, 0x4Cu, 0x23u, 0x78u, 0x03u, 0xF0u, 0xC0u, 0x03u,
+    0x40u, 0x2Bu, 0x00u, 0xD0u, 0x1Eu, 0xB1u, 0x00u, 0x20u,
+    0x20u, 0x70u, 0xFFu, 0xF7u, 0x07u, 0xFEu, 0x14u, 0x20u,
+    0xFFu, 0xF7u, 0x04u, 0xFEu, 0x80u, 0x23u, 0x23u, 0x70u,
+    0xBDu, 0xE8u, 0x70u, 0x40u, 0x00u, 0xF0u, 0xEAu, 0xB8u,
+    0x0Cu, 0xC1u, 0xFFu, 0x1Fu, 0xFAu, 0x46u, 0x00u, 0x40u,
     0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u,
     0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u,
     0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u,
     0x72u, 0xB6u, 0x70u, 0x47u, 0x80u, 0xF3u, 0x10u, 0x88u,
     0x70u, 0x47u, 0x00u, 0xBFu, 0xAFu, 0xF3u, 0x00u, 0x80u,
-    0x01u, 0x20u, 0x10u, 0xB5u, 0x00u, 0xF0u, 0x60u, 0xF9u,
-    0x07u, 0x28u, 0x09u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
-    0x17u, 0xE0u, 0x0Eu, 0x4Bu, 0x18u, 0x78u, 0x00u, 0xF0u,
-    0x02u, 0x01u, 0xCAu, 0xB2u, 0x00u, 0x2Au, 0xF5u, 0xD1u,
-    0x02u, 0x21u, 0x0Bu, 0x48u, 0x00u, 0xF0u, 0xECu, 0xF8u,
-    0x02u, 0x28u, 0xF2u, 0xD1u, 0x07u, 0x4Cu, 0x23u, 0x78u,
-    0x03u, 0xF0u, 0x02u, 0x00u, 0xC1u, 0xB2u, 0x19u, 0xB9u,
-    0x01u, 0x20u, 0x00u, 0xF0u, 0xAFu, 0xF8u, 0xF5u, 0xE7u,
-    0x00u, 0x24u, 0x00u, 0xF0u, 0x7Fu, 0xF9u, 0x20u, 0x46u,
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
-    0x57u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x00u, 0xF0u,
-    0xC1u, 0xF8u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x58u, 0xB9u,
-    0xFFu, 0xF7u, 0xCEu, 0xFFu, 0x48u, 0xB9u, 0x00u, 0xF0u,
-    0xB9u, 0xF8u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x18u, 0xB9u,
-    0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xC4u, 0xBFu,
-    0x04u, 0x20u, 0x08u, 0xBDu, 0x38u, 0xB5u, 0x04u, 0x46u,
-    0x00u, 0xF0u, 0xACu, 0xF8u, 0x4Cu, 0xB1u, 0x00u, 0xF0u,
-    0x3Du, 0xF9u, 0x05u, 0x46u, 0x38u, 0xB9u, 0x05u, 0x4Bu,
-    0x1Cu, 0x60u, 0x00u, 0xF0u, 0x57u, 0xF9u, 0x28u, 0x46u,
-    0x38u, 0xBDu, 0x01u, 0x20u, 0x38u, 0xBDu, 0x04u, 0x20u,
-    0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,
-    0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u, 0x17u, 0x46u,
-    0x1Cu, 0x46u, 0x00u, 0xF0u, 0x27u, 0xF9u, 0xF0u, 0xB9u,
-    0x22u, 0x46u, 0x28u, 0x46u, 0x39u, 0x46u, 0x00u, 0xF0u,
-    0xB9u, 0xF8u, 0x07u, 0x28u, 0x04u, 0x46u, 0x13u, 0xD1u,
-    0x1Du, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u,
-    0xC1u, 0xB2u, 0x19u, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u,
-    0x61u, 0xF8u, 0xF5u, 0xE7u, 0x1Cu, 0x78u, 0x04u, 0xF0u,
-    0x02u, 0x02u, 0xD0u, 0xB2u, 0x10u, 0xB1u, 0x1Bu, 0x78u,
-    0x9Bu, 0x08u, 0x06u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
-    0x00u, 0xF0u, 0x28u, 0xF9u, 0x22u, 0xE0u, 0x04u, 0x24u,
-    0x20u, 0xE0u, 0x12u, 0x4Cu, 0x28u, 0x46u, 0x22u, 0x78u,
-    0x63u, 0x78u, 0x31u, 0x46u, 0x00u, 0xF0u, 0xBCu, 0xF8u,
-    0x07u, 0x28u, 0x04u, 0x46u, 0xF0u, 0xD1u, 0x0Cu, 0x49u,
-    0x0Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u, 0xC3u, 0xB2u,
-    0x1Bu, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF8u,
-    0xF5u, 0xE7u, 0x0Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x02u,
-    0xD0u, 0xB2u, 0x00u, 0x28u, 0xDEu, 0xD0u, 0x09u, 0x78u,
-    0x8Bu, 0x08u, 0x14u, 0xBFu, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
-    0x00u, 0x24u, 0xD9u, 0xE7u, 0x20u, 0x46u, 0xF8u, 0xBDu,
-    0x22u, 0x47u, 0x00u, 0x40u, 0x57u, 0xC1u, 0xFFu, 0x1Fu,
-    0x04u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u, 0x10u, 0x00u,
-    0x18u, 0x70u, 0x19u, 0x7Cu, 0x41u, 0xF0u, 0x10u, 0x02u,
-    0x1Au, 0x74u, 0x70u, 0x47u, 0xACu, 0x43u, 0x00u, 0x40u,
+    0x38u, 0xB5u, 0x00u, 0xF0u, 0x2Du, 0xF9u, 0x00u, 0xF0u,
+    0xD9u, 0xF9u, 0x00u, 0x28u, 0x38u, 0xD1u, 0x00u, 0xF0u,
+    0x0Fu, 0xFAu, 0x07u, 0x28u, 0x04u, 0x46u, 0x0Fu, 0xD1u,
+    0x1Bu, 0x4Bu, 0x1Au, 0x78u, 0x90u, 0x07u, 0x03u, 0xD4u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0xDBu, 0xF8u, 0xF7u, 0xE7u,
+    0x1Au, 0x78u, 0x91u, 0x07u, 0x04u, 0xD5u, 0x1Bu, 0x78u,
+    0x9Bu, 0x08u, 0x14u, 0xBFu, 0x07u, 0x24u, 0x00u, 0x24u,
+    0x00u, 0xF0u, 0xE0u, 0xF9u, 0x0Cu, 0xBBu, 0x00u, 0xF0u,
+    0x0Fu, 0xF9u, 0x00u, 0xF0u, 0xBBu, 0xF9u, 0xD8u, 0xB9u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0x9Du, 0xF9u, 0x07u, 0x28u,
+    0x05u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u, 0x10u, 0xE0u,
+    0x2Bu, 0x78u, 0x9Bu, 0x07u, 0xF9u, 0xD4u, 0x0Bu, 0x48u,
+    0x02u, 0x21u, 0x00u, 0xF0u, 0x0Fu, 0xF9u, 0x02u, 0x28u,
+    0x07u, 0x4Du, 0xF5u, 0xD1u, 0x2Bu, 0x78u, 0x9Au, 0x07u,
+    0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0xB2u, 0xF8u,
+    0xF8u, 0xE7u, 0x00u, 0xF0u, 0xBFu, 0xF9u, 0x00u, 0xE0u,
+    0x04u, 0x24u, 0x20u, 0x46u, 0x38u, 0xBDu, 0x00u, 0xBFu,
+    0x22u, 0x47u, 0x00u, 0x40u, 0x50u, 0xC1u, 0xFFu, 0x1Fu,
+    0x41u, 0x28u, 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u,
+    0x17u, 0x46u, 0x1Cu, 0x46u, 0x0Au, 0xD8u, 0xC1u, 0x1Eu,
+    0x3Cu, 0x29u, 0x8Cu, 0xBFu, 0x00u, 0x21u, 0x01u, 0x21u,
+    0x3Fu, 0x28u, 0x04u, 0xD8u, 0xB6u, 0xF5u, 0x80u, 0x7Fu,
+    0x29u, 0xD8u, 0x05u, 0xE0u, 0x01u, 0x21u, 0x81u, 0x2Eu,
+    0x28u, 0xBFu, 0x01u, 0x21u, 0x10u, 0x2Cu, 0x22u, 0xD1u,
+    0x0Fu, 0xB3u, 0x01u, 0xBBu, 0x00u, 0xF0u, 0x7Au, 0xF9u,
+    0xF8u, 0xB9u, 0x23u, 0x46u, 0x28u, 0x46u, 0x31u, 0x46u,
+    0x3Au, 0x46u, 0x00u, 0xF0u, 0xF1u, 0xF8u, 0x07u, 0x28u,
+    0x04u, 0x46u, 0x11u, 0xD1u, 0x1Bu, 0x4Bu, 0x1Au, 0x78u,
+    0x1Fu, 0x46u, 0x12u, 0xF0u, 0x02u, 0x0Fu, 0x03u, 0xD1u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0x77u, 0xF8u, 0xF5u, 0xE7u,
+    0x1Au, 0x78u, 0x90u, 0x07u, 0x02u, 0xD5u, 0x1Bu, 0x78u,
+    0x9Bu, 0x08u, 0x08u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
+    0x00u, 0xF0u, 0x7Cu, 0xF9u, 0x1Fu, 0xE0u, 0x01u, 0x24u,
+    0x1Du, 0xE0u, 0x04u, 0x24u, 0x1Bu, 0xE0u, 0x10u, 0x4Bu,
+    0x28u, 0x46u, 0x1Au, 0x78u, 0x31u, 0x46u, 0x5Bu, 0x78u,
+    0x00u, 0xF0u, 0x16u, 0xF9u, 0x07u, 0x28u, 0x04u, 0x46u,
+    0xEEu, 0xD1u, 0x3Au, 0x78u, 0x09u, 0x4Bu, 0x91u, 0x07u,
+    0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x56u, 0xF8u,
+    0xF7u, 0xE7u, 0x1Au, 0x78u, 0x92u, 0x07u, 0xE1u, 0xD5u,
+    0x1Bu, 0x78u, 0x9Bu, 0x08u, 0x0Cu, 0xBFu, 0x00u, 0x24u,
+    0x6Fu, 0xF0u, 0x00u, 0x04u, 0xDCu, 0xE7u, 0x20u, 0x46u,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
+    0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,
+    0x49u, 0xFFu, 0x0Fu, 0x4Bu, 0x1Au, 0x78u, 0x0Cu, 0x33u,
+    0x42u, 0xF0u, 0x08u, 0x02u, 0x03u, 0xF8u, 0x0Cu, 0x2Cu,
+    0x1Au, 0x79u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x71u,
+    0xC8u, 0x22u, 0x83u, 0xF8u, 0x55u, 0x23u, 0x1Au, 0x78u,
+    0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x70u, 0x1Au, 0x7Cu,
+    0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x74u, 0x05u, 0x4Bu,
+    0x1Bu, 0x78u, 0x9Bu, 0x06u, 0xFBu, 0xD5u, 0xBDu, 0xE8u,
+    0x08u, 0x40u, 0xFFu, 0xF7u, 0x2Fu, 0xBFu, 0x00u, 0xBFu,
+    0xA0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x40u,
     0x01u, 0xBEu, 0x70u, 0x47u, 0x02u, 0x4Bu, 0x1Au, 0x78u,
-    0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u, 0x70u, 0x47u,
+    0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,
     0xF6u, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x04u, 0x46u,
     0xB4u, 0xF5u, 0x00u, 0x4Fu, 0x06u, 0x4Bu, 0x05u, 0xD9u,
-    0x18u, 0x68u, 0xFFu, 0xF7u, 0x29u, 0xFFu, 0xA4u, 0xF5u,
+    0x18u, 0x68u, 0xFFu, 0xF7u, 0x09u, 0xFFu, 0xA4u, 0xF5u,
     0x00u, 0x44u, 0xF5u, 0xE7u, 0x58u, 0x68u, 0x60u, 0x43u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x20u, 0xBFu,
-    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x19u, 0x7Au,
-    0x48u, 0x43u, 0xFFu, 0xF7u, 0x19u, 0xBFu, 0x00u, 0xBFu,
-    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x00u, 0xF0u,
-    0x1Fu, 0x00u, 0x1Bu, 0x68u, 0x00u, 0xF1u, 0x10u, 0x02u,
-    0x53u, 0xF8u, 0x22u, 0x00u, 0x43u, 0xF8u, 0x22u, 0x10u,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x08u, 0xEDu, 0x00u, 0xE0u,
-    0x00u, 0xF0u, 0x1Fu, 0x00u, 0x00u, 0xF1u, 0x60u, 0x43u,
-    0x49u, 0x01u, 0x03u, 0xF5u, 0x64u, 0x42u, 0xC8u, 0xB2u,
-    0x10u, 0x70u, 0x70u, 0x47u, 0x08u, 0xB5u, 0xFFu, 0xF7u,
-    0x05u, 0xFFu, 0x06u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,
-    0x08u, 0x01u, 0x19u, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u,
-    0x08u, 0x01u, 0x19u, 0x74u, 0xBDu, 0xE8u, 0x08u, 0x40u,
-    0xFFu, 0xF7u, 0xFCu, 0xBEu, 0xA0u, 0x43u, 0x00u, 0x40u,
-    0x70u, 0xB5u, 0x06u, 0x46u, 0x0Du, 0x46u, 0x00u, 0x24u,
-    0xE3u, 0xB2u, 0xABu, 0x42u, 0x0Cu, 0xD2u, 0x07u, 0x48u,
-    0x01u, 0x78u, 0xCBu, 0x07u, 0x03u, 0xD4u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0xC0u, 0xFFu, 0xF7u, 0xE7u, 0x04u, 0x4Au,
-    0x13u, 0x78u, 0x33u, 0x55u, 0x01u, 0x34u, 0xEFu, 0xE7u,
-    0x28u, 0x46u, 0x70u, 0xBDu, 0x22u, 0x47u, 0x00u, 0x40u,
-    0x20u, 0x47u, 0x00u, 0x40u, 0x30u, 0xB5u, 0x10u, 0x4Bu,
-    0x1Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x04u, 0xE4u, 0xB2u,
-    0xACu, 0xB1u, 0x0Eu, 0x4Cu, 0xB6u, 0x25u, 0x25u, 0x70u,
-    0xD5u, 0x25u, 0x25u, 0x70u, 0x02u, 0x25u, 0x25u, 0x70u,
-    0x1Bu, 0x78u, 0x2Bu, 0x40u, 0xDBu, 0xB2u, 0x63u, 0xB9u,
-    0x20u, 0x70u, 0x98u, 0xB2u, 0x90u, 0x42u, 0x04u, 0xD2u,
-    0xCCu, 0x5Cu, 0x06u, 0x48u, 0x01u, 0x33u, 0x04u, 0x70u,
-    0xF7u, 0xE7u, 0x07u, 0x20u, 0x30u, 0xBDu, 0x04u, 0x20u,
-    0x30u, 0xBDu, 0x09u, 0x20u, 0x30u, 0xBDu, 0x00u, 0xBFu,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x00u, 0xBFu,
+    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x1Bu, 0x7Au,
+    0x58u, 0x43u, 0xFFu, 0xF7u, 0xF9u, 0xBEu, 0x00u, 0xBFu,
+    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,
+    0xFDu, 0xFEu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x06u, 0x4Bu, 0x1Au, 0x88u, 0x92u, 0xB2u,
+    0x42u, 0xF0u, 0x04u, 0x02u, 0x1Au, 0x80u, 0x1Bu, 0x88u,
+    0xBFu, 0xF3u, 0x6Fu, 0x8Fu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+    0xFFu, 0xF7u, 0xE4u, 0xBEu, 0x00u, 0x48u, 0x00u, 0x40u,
+    0x05u, 0x4Bu, 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x1Bu, 0x68u,
+    0x00u, 0xF1u, 0x10u, 0x02u, 0x53u, 0xF8u, 0x22u, 0x00u,
+    0x43u, 0xF8u, 0x22u, 0x10u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xF0u, 0x1Fu, 0x00u,
+    0x00u, 0xF1u, 0x60u, 0x40u, 0x49u, 0x01u, 0x00u, 0xF5u,
+    0x64u, 0x40u, 0xC9u, 0xB2u, 0x01u, 0x70u, 0x70u, 0x47u,
+    0x08u, 0xB5u, 0xFFu, 0xF7u, 0xC3u, 0xFEu, 0x06u, 0x4Bu,
+    0x1Au, 0x78u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x70u,
+    0x1Au, 0x7Cu, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x74u,
+    0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xBAu, 0xBEu,
+    0xA0u, 0x43u, 0x00u, 0x40u, 0x70u, 0xB5u, 0x06u, 0x46u,
+    0x0Du, 0x46u, 0x00u, 0x24u, 0xE3u, 0xB2u, 0xABu, 0x42u,
+    0x0Cu, 0xD2u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0x07u,
+    0x03u, 0xD4u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x9Eu, 0xFFu,
+    0xF7u, 0xE7u, 0x04u, 0x4Bu, 0x1Bu, 0x78u, 0x33u, 0x55u,
+    0x01u, 0x34u, 0xEFu, 0xE7u, 0x28u, 0x46u, 0x70u, 0xBDu,
+    0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
+    0xF0u, 0xB5u, 0x21u, 0x4Du, 0x2Cu, 0x78u, 0xA4u, 0x07u,
+    0x39u, 0xD5u, 0x20u, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,
+    0xD5u, 0x26u, 0x26u, 0x70u, 0x02u, 0x26u, 0x26u, 0x70u,
+    0x2Eu, 0x78u, 0x06u, 0xF0u, 0x02u, 0x06u, 0x06u, 0xF0u,
+    0xFFu, 0x05u, 0x76u, 0xBBu, 0x20u, 0x2Bu, 0x20u, 0x70u,
+    0x01u, 0xD0u, 0x00u, 0x25u, 0x0Cu, 0xE0u, 0x3Fu, 0x28u,
+    0xFBu, 0xD8u, 0x01u, 0xEBu, 0x00u, 0x27u, 0x3Fu, 0x02u,
+    0xEEu, 0x5Du, 0x01u, 0x35u, 0xF6u, 0xB2u, 0xB5u, 0xF5u,
+    0x80u, 0x7Fu, 0x26u, 0x70u, 0xF8u, 0xD1u, 0xF0u, 0xE7u,
+    0xAEu, 0xB2u, 0x9Eu, 0x42u, 0x03u, 0xD2u, 0x56u, 0x5Du,
+    0x01u, 0x35u, 0x26u, 0x70u, 0xF8u, 0xE7u, 0xB3u, 0xF5u,
+    0x80u, 0x7Fu, 0x01u, 0xD0u, 0x07u, 0x20u, 0xF0u, 0xBDu,
+    0x3Fu, 0x28u, 0xFBu, 0xD8u, 0x00u, 0xF5u, 0x10u, 0x30u,
+    0x01u, 0xEBu, 0x00u, 0x21u, 0x49u, 0x01u, 0x00u, 0x23u,
+    0x5Au, 0x5Cu, 0x01u, 0x33u, 0xD2u, 0xB2u, 0x20u, 0x2Bu,
+    0x22u, 0x70u, 0xF9u, 0xD1u, 0xEEu, 0xE7u, 0x04u, 0x20u,
+    0xF0u, 0xBDu, 0x09u, 0x20u, 0xF0u, 0xBDu, 0x00u, 0xBFu,
     0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
-    0x70u, 0xB5u, 0x0Fu, 0x4Du, 0x2Cu, 0x78u, 0x04u, 0xF0u,
-    0x02u, 0x04u, 0xE4u, 0xB2u, 0xA4u, 0xB1u, 0x0Du, 0x4Cu,
-    0xB6u, 0x26u, 0x26u, 0x70u, 0xD8u, 0x26u, 0x26u, 0x70u,
-    0x05u, 0x26u, 0x26u, 0x70u, 0x2Du, 0x78u, 0x05u, 0xF0u,
-    0x02u, 0x05u, 0xEDu, 0xB2u, 0x55u, 0xB9u, 0x20u, 0x70u,
+    0x70u, 0xB5u, 0x0Du, 0x4Du, 0x2Cu, 0x78u, 0xA6u, 0x07u,
+    0x12u, 0xD5u, 0x0Cu, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,
+    0xD8u, 0x26u, 0x26u, 0x70u, 0x05u, 0x26u, 0x26u, 0x70u,
+    0x2Du, 0x78u, 0xADu, 0x07u, 0x0Au, 0xD4u, 0x20u, 0x70u,
     0x08u, 0x0Au, 0xC9u, 0xB2u, 0x20u, 0x70u, 0x21u, 0x70u,
-    0x07u, 0x20u, 0x22u, 0x70u, 0x23u, 0x70u, 0x70u, 0xBDu,
+    0x22u, 0x70u, 0x23u, 0x70u, 0x07u, 0x20u, 0x70u, 0xBDu,
     0x04u, 0x20u, 0x70u, 0xBDu, 0x09u, 0x20u, 0x70u, 0xBDu,
     0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
-    0x0Cu, 0x4Au, 0x13u, 0x78u, 0x03u, 0xF0u, 0x02u, 0x01u,
-    0xCBu, 0xB2u, 0x73u, 0xB1u, 0x0Au, 0x4Bu, 0xB6u, 0x21u,
-    0x19u, 0x70u, 0xE1u, 0x21u, 0x19u, 0x70u, 0x0Eu, 0x21u,
-    0x19u, 0x70u, 0x12u, 0x78u, 0x02u, 0xF0u, 0x02u, 0x01u,
-    0xCAu, 0xB2u, 0x22u, 0xB9u, 0x18u, 0x70u, 0x07u, 0x20u,
+    0x0Au, 0x4Au, 0x13u, 0x78u, 0x99u, 0x07u, 0x0Cu, 0xD5u,
+    0x09u, 0x4Bu, 0xB6u, 0x21u, 0x19u, 0x70u, 0xE1u, 0x21u,
+    0x19u, 0x70u, 0x0Eu, 0x21u, 0x19u, 0x70u, 0x12u, 0x78u,
+    0x92u, 0x07u, 0x04u, 0xD4u, 0x18u, 0x70u, 0x07u, 0x20u,
     0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x09u, 0x20u,
     0x70u, 0x47u, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
     0x20u, 0x47u, 0x00u, 0x40u, 0x38u, 0xB5u, 0xFFu, 0xF7u,
-    0x71u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,
+    0x15u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,
     0x01u, 0x25u, 0x0Bu, 0x4Au, 0x1Du, 0x70u, 0x14u, 0x68u,
     0x2Cu, 0x40u, 0x0Au, 0xD0u, 0x14u, 0x68u, 0x24u, 0xF0u,
     0x01u, 0x04u, 0x14u, 0x60u, 0x00u, 0xBFu, 0x00u, 0xBFu,
     0x00u, 0xBFu, 0x5Du, 0x60u, 0x0Cu, 0x46u, 0x00u, 0xE0u,
-    0x04u, 0x24u, 0xFFu, 0xF7u, 0x5Fu, 0xFEu, 0x20u, 0x46u,
-    0x38u, 0xBDu, 0x00u, 0xBFu, 0x48u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x24u, 0xFFu, 0xF7u, 0x03u, 0xFEu, 0x20u, 0x46u,
+    0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,
     0x04u, 0x00u, 0x08u, 0x40u, 0x10u, 0xB5u, 0xFFu, 0xF7u,
-    0x51u, 0xFEu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,
+    0xF5u, 0xFDu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,
     0x1Au, 0x70u, 0x01u, 0x29u, 0x08u, 0xD1u, 0x07u, 0x49u,
     0x0Cu, 0x68u, 0x44u, 0xF0u, 0x01u, 0x04u, 0x0Cu, 0x60u,
     0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x5Au, 0x60u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x42u, 0xBEu,
-    0x48u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xE6u, 0xBDu,
+    0x44u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,
+    0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x9Bu, 0x07u, 0x08u, 0xD5u,
+    0x06u, 0x4Bu, 0xB6u, 0x22u, 0x1Au, 0x70u, 0xE0u, 0x22u,
+    0x1Au, 0x70u, 0x0Du, 0x22u, 0x1Au, 0x70u, 0x07u, 0x20u,
+    0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
     0x08u, 0xB5u, 0x62u, 0xB6u, 0x00u, 0x20u, 0x02u, 0x21u,
-    0x00u, 0xF0u, 0x62u, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,
-    0x1Au, 0x70u, 0x08u, 0xBDu, 0x50u, 0xC1u, 0xFFu, 0x1Fu,
-    0x01u, 0x20u, 0x00u, 0xF0u, 0x03u, 0xBAu, 0x00u, 0x00u,
-    0xF8u, 0xB5u, 0x07u, 0x46u, 0x0Eu, 0x46u, 0x02u, 0x20u,
-    0x15u, 0x46u, 0x39u, 0x46u, 0x40u, 0x22u, 0x1Cu, 0x46u,
-    0x00u, 0xF0u, 0xBAu, 0xF9u, 0x0Au, 0x23u, 0x5Cu, 0x43u,
-    0x0Du, 0x48u, 0x44u, 0x80u, 0x00u, 0x24u, 0x02u, 0x20u,
-    0x00u, 0xF0u, 0x94u, 0xF9u, 0x50u, 0xB9u, 0x0Au, 0x49u,
-    0x67u, 0x1Cu, 0x4Au, 0x88u, 0xBFu, 0xB2u, 0xA2u, 0x42u,
-    0x04u, 0xD9u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0xD2u, 0xFEu,
-    0x3Cu, 0x46u, 0xF0u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,
-    0x85u, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,
-    0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu,
-    0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x2Du, 0xE9u, 0xF0u, 0x41u,
-    0x15u, 0x46u, 0x0Au, 0x22u, 0x53u, 0x43u, 0x28u, 0x4Cu,
-    0x80u, 0x46u, 0x63u, 0x80u, 0x24u, 0x78u, 0x0Fu, 0x46u,
-    0xD4u, 0xB1u, 0x00u, 0x24u, 0x00u, 0xF0u, 0x5Eu, 0xF9u,
-    0x58u, 0xB9u, 0x23u, 0x4Bu, 0x66u, 0x1Cu, 0x58u, 0x88u,
-    0xB6u, 0xB2u, 0xA0u, 0x42u, 0x04u, 0xD9u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0xACu, 0xFEu, 0x34u, 0x46u, 0xF1u, 0xE7u,
-    0x34u, 0x46u, 0x00u, 0xF0u, 0x4Fu, 0xF9u, 0xE0u, 0xB1u,
-    0x00u, 0xF0u, 0x52u, 0xF9u, 0xFFu, 0xF7u, 0xB0u, 0xFFu,
-    0x19u, 0x4Au, 0x00u, 0x21u, 0x11u, 0x70u, 0x14u, 0xE0u,
-    0x00u, 0xF0u, 0x4Au, 0xF9u, 0x08u, 0xB9u, 0x00u, 0x24u,
-    0x0Fu, 0xE0u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x00u, 0x28u,
-    0xF9u, 0xD0u, 0xFFu, 0xF7u, 0xA1u, 0xFFu, 0x08u, 0xE0u,
-    0x11u, 0x4Bu, 0x66u, 0x1Cu, 0x59u, 0x88u, 0xB6u, 0xB2u,
-    0xA1u, 0x42u, 0x09u, 0xD9u, 0xFFu, 0xF7u, 0x8Au, 0xFEu,
-    0x34u, 0x46u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF9u,
-    0x01u, 0x28u, 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xEFu, 0xD1u,
-    0x00u, 0xF0u, 0x38u, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u,
-    0x41u, 0x46u, 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u,
-    0x40u, 0x22u, 0x00u, 0xF0u, 0x9Fu, 0xF9u, 0x28u, 0x80u,
-    0x00u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u, 0x00u, 0x20u,
-    0x28u, 0x80u, 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u,
-    0x50u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,
-    0xA5u, 0xFDu, 0x38u, 0x4Bu, 0x07u, 0x46u, 0x1Au, 0x78u,
-    0x01u, 0x25u, 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u,
-    0x19u, 0x7Cu, 0x02u, 0x26u, 0x41u, 0xF0u, 0x01u, 0x04u,
-    0x1Cu, 0x74u, 0x33u, 0x4Bu, 0x33u, 0x4Cu, 0x1Du, 0x70u,
-    0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u, 0x8Du, 0x2Cu,
-    0x02u, 0xF0u, 0x7Fu, 0x00u, 0x03u, 0xF8u, 0x8Du, 0x0Cu,
-    0x00u, 0x20u, 0xFFu, 0xF7u, 0x63u, 0xFEu, 0x21u, 0x78u,
-    0x2Du, 0x48u, 0x01u, 0xF0u, 0xF9u, 0x03u, 0x23u, 0x70u,
-    0x02u, 0x78u, 0x02u, 0xF0u, 0xDFu, 0x01u, 0x01u, 0x70u,
-    0x23u, 0x78u, 0x28u, 0x46u, 0x2Bu, 0x43u, 0x23u, 0x70u,
-    0xFFu, 0xF7u, 0x54u, 0xFEu, 0x28u, 0x20u, 0xFFu, 0xF7u,
-    0x51u, 0xFEu, 0x26u, 0x48u, 0x02u, 0x78u, 0x02u, 0xF0u,
-    0x7Fu, 0x01u, 0x01u, 0x70u, 0x03u, 0x78u, 0x03u, 0xF0u,
-    0xBFu, 0x02u, 0x02u, 0x70u, 0x20u, 0x78u, 0x30u, 0x43u,
-    0x20u, 0x70u, 0x30u, 0x46u, 0xFFu, 0xF7u, 0x42u, 0xFEu,
-    0x21u, 0x78u, 0x1Fu, 0x4Au, 0x41u, 0xF0u, 0x04u, 0x03u,
-    0x23u, 0x70u, 0x00u, 0x24u, 0x14u, 0x70u, 0x38u, 0x46u,
-    0x54u, 0x70u, 0xFFu, 0xF7u, 0x63u, 0xFDu, 0x17u, 0x20u,
-    0x1Au, 0x49u, 0xFFu, 0xF7u, 0x3Bu, 0xFEu, 0x17u, 0x20u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x45u, 0xFEu, 0x15u, 0x20u,
-    0x17u, 0x49u, 0xFFu, 0xF7u, 0x33u, 0xFEu, 0x15u, 0x20u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x3Du, 0xFEu, 0x18u, 0x20u,
-    0x14u, 0x49u, 0xFFu, 0xF7u, 0x2Bu, 0xFEu, 0x18u, 0x20u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x35u, 0xFEu, 0x20u, 0x46u,
-    0x11u, 0x49u, 0xFFu, 0xF7u, 0x23u, 0xFEu, 0x20u, 0x46u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x2Du, 0xFEu, 0x28u, 0x46u,
-    0x0Eu, 0x49u, 0xFFu, 0xF7u, 0x1Bu, 0xFEu, 0x28u, 0x46u,
-    0x07u, 0x21u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,
-    0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u,
-    0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
+    0x00u, 0xF0u, 0x4Eu, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x70u, 0x08u, 0xBDu, 0x4Cu, 0xC1u, 0xFFu, 0x1Fu,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0xF1u, 0xB9u, 0xF8u, 0xB5u,
+    0x07u, 0x46u, 0x0Eu, 0x46u, 0x15u, 0x46u, 0x03u, 0xEBu,
+    0x83u, 0x03u, 0x02u, 0x20u, 0x39u, 0x46u, 0x40u, 0x22u,
+    0x5Cu, 0x00u, 0x00u, 0xF0u, 0xA7u, 0xF9u, 0x02u, 0x20u,
+    0x00u, 0xF0u, 0x86u, 0xF9u, 0x30u, 0xB9u, 0x2Cu, 0xB1u,
+    0x01u, 0x20u, 0x01u, 0x3Cu, 0xFFu, 0xF7u, 0x8Au, 0xFEu,
+    0xA4u, 0xB2u, 0xF4u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,
+    0x7Bu, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,
+    0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0x00u,
+    0x2Du, 0xE9u, 0xF8u, 0x43u, 0x03u, 0xEBu, 0x83u, 0x03u,
+    0x5Cu, 0x00u, 0x23u, 0x4Bu, 0x16u, 0x46u, 0x1Au, 0x78u,
+    0x80u, 0x46u, 0x0Fu, 0x46u, 0x99u, 0x46u, 0xAAu, 0xB1u,
+    0x25u, 0x46u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x30u, 0xB9u,
+    0x2Du, 0xB1u, 0x01u, 0x20u, 0x01u, 0x3Du, 0xFFu, 0xF7u,
+    0x69u, 0xFEu, 0xADu, 0xB2u, 0xF5u, 0xE7u, 0x00u, 0xF0u,
+    0x49u, 0xF9u, 0xA8u, 0xB1u, 0x00u, 0xF0u, 0x4Cu, 0xF9u,
+    0xFFu, 0xF7u, 0xBEu, 0xFFu, 0x00u, 0x23u, 0x89u, 0xF8u,
+    0x00u, 0x30u, 0x0Du, 0xE0u, 0x00u, 0xF0u, 0x44u, 0xF9u,
+    0x50u, 0xB1u, 0x00u, 0xF0u, 0x3Bu, 0xF9u, 0x38u, 0xB1u,
+    0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x04u, 0xE0u, 0x54u, 0xB1u,
+    0xFFu, 0xF7u, 0x50u, 0xFEu, 0x01u, 0x3Cu, 0xA4u, 0xB2u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0x41u, 0xF9u, 0x01u, 0x28u,
+    0x4Fu, 0xF0u, 0x01u, 0x00u, 0xF3u, 0xD1u, 0x00u, 0xF0u,
+    0x3Bu, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u, 0x41u, 0x46u,
+    0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u, 0x40u, 0x22u,
+    0x00u, 0xF0u, 0xA4u, 0xF9u, 0x30u, 0x80u, 0x00u, 0x20u,
+    0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0x23u, 0x33u, 0x80u,
+    0x10u, 0x20u, 0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0xBFu,
+    0x4Cu, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,
+    0x49u, 0xFDu, 0x39u, 0x4Bu, 0x01u, 0x25u, 0x1Au, 0x78u,
+    0x02u, 0x26u, 0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u,
+    0x1Au, 0x7Cu, 0x36u, 0x4Cu, 0x42u, 0xF0u, 0x01u, 0x02u,
+    0x1Au, 0x74u, 0x03u, 0xF5u, 0xE7u, 0x53u, 0x18u, 0x33u,
+    0x1Du, 0x70u, 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u,
+    0x8Du, 0x2Cu, 0x07u, 0x46u, 0x02u, 0xF0u, 0x7Fu, 0x02u,
+    0x03u, 0xF8u, 0x8Du, 0x2Cu, 0x00u, 0x20u, 0xFFu, 0xF7u,
+    0x25u, 0xFEu, 0x23u, 0x78u, 0x28u, 0x46u, 0x03u, 0xF0u,
+    0xF9u, 0x03u, 0x23u, 0x70u, 0x2Au, 0x4Bu, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xDFu, 0x02u, 0x1Au, 0x70u, 0x23u, 0x78u,
+    0x2Bu, 0x43u, 0x23u, 0x70u, 0xFFu, 0xF7u, 0x16u, 0xFEu,
+    0x28u, 0x20u, 0xFFu, 0xF7u, 0x13u, 0xFEu, 0x25u, 0x4Bu,
+    0x30u, 0x46u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x7Fu, 0x02u,
+    0x1Au, 0x70u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xBFu, 0x02u,
+    0x1Au, 0x70u, 0x23u, 0x78u, 0x33u, 0x43u, 0x23u, 0x70u,
+    0xFFu, 0xF7u, 0x04u, 0xFEu, 0x23u, 0x78u, 0x38u, 0x46u,
+    0x43u, 0xF0u, 0x04u, 0x03u, 0x23u, 0x70u, 0x1Cu, 0x4Bu,
+    0x00u, 0x24u, 0x1Cu, 0x70u, 0x5Cu, 0x70u, 0xFFu, 0xF7u,
+    0x05u, 0xFDu, 0x1Au, 0x49u, 0x17u, 0x20u, 0xFFu, 0xF7u,
+    0x1Fu, 0xFEu, 0x17u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x29u, 0xFEu, 0x17u, 0x49u, 0x15u, 0x20u, 0xFFu, 0xF7u,
+    0x17u, 0xFEu, 0x15u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x21u, 0xFEu, 0x14u, 0x49u, 0x18u, 0x20u, 0xFFu, 0xF7u,
+    0x0Fu, 0xFEu, 0x18u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x19u, 0xFEu, 0x20u, 0x46u, 0x10u, 0x49u, 0xFFu, 0xF7u,
+    0x07u, 0xFEu, 0x20u, 0x46u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x11u, 0xFEu, 0x28u, 0x46u, 0x0Du, 0x49u, 0xFFu, 0xF7u,
+    0xFFu, 0xFDu, 0x28u, 0x46u, 0x07u, 0x21u, 0xBDu, 0xE8u,
+    0xF8u, 0x40u, 0xFFu, 0xF7u, 0x07u, 0xBEu, 0x00u, 0xBFu,
+    0xA5u, 0x43u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
     0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u,
-    0x84u, 0x60u, 0x00u, 0x40u, 0x0Bu, 0x16u, 0x00u, 0x00u,
-    0x09u, 0x16u, 0x00u, 0x00u, 0x49u, 0x14u, 0x00u, 0x00u,
-    0xA1u, 0x15u, 0x00u, 0x00u, 0xD5u, 0x15u, 0x00u, 0x00u,
+    0x84u, 0x60u, 0x00u, 0x40u, 0xF3u, 0x16u, 0x00u, 0x00u,
+    0xF1u, 0x16u, 0x00u, 0x00u, 0x45u, 0x15u, 0x00u, 0x00u,
+    0x89u, 0x16u, 0x00u, 0x00u, 0xBDu, 0x16u, 0x00u, 0x00u,
     0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u,
     0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u,
     0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u,
     0x02u, 0x22u, 0x1Au, 0x60u, 0x13u, 0x4Bu, 0x00u, 0x24u,
     0x1Cu, 0x70u, 0x13u, 0x4Bu, 0x01u, 0xB1u, 0x03u, 0x22u,
-    0x12u, 0x49u, 0x1Au, 0x70u, 0x12u, 0x4Bu, 0x08u, 0x70u,
-    0x12u, 0x4Au, 0x00u, 0x20u, 0x12u, 0x49u, 0x18u, 0x70u,
-    0x12u, 0x4Bu, 0x10u, 0x70u, 0x08u, 0x70u, 0x12u, 0x4Au,
-    0x12u, 0x49u, 0x18u, 0x70u, 0x12u, 0x4Bu, 0x10u, 0x70u,
-    0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,
-    0x01u, 0x20u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,
-    0xE7u, 0xFCu, 0x0Eu, 0x48u, 0x04u, 0x21u, 0x01u, 0x70u,
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0xECu, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0xE1u, 0x00u, 0xE0u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x09u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
+    0x1Au, 0x70u, 0x12u, 0x4Bu, 0x12u, 0x4Au, 0x18u, 0x70u,
+    0x00u, 0x23u, 0x13u, 0x70u, 0x11u, 0x4Au, 0x01u, 0x20u,
+    0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,
+    0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,
+    0x13u, 0x70u, 0x11u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+    0x80u, 0x22u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,
+    0x8Bu, 0xFCu, 0x0Eu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0xE1u, 0x00u, 0xE0u, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x09u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+    0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+    0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
     0x28u, 0x60u, 0x00u, 0x40u, 0x12u, 0x60u, 0x00u, 0x40u,
     0x70u, 0xB5u, 0x07u, 0x4Cu, 0x06u, 0x46u, 0x23u, 0x78u,
     0x0Du, 0x46u, 0x1Bu, 0xB9u, 0xFFu, 0xF7u, 0x22u, 0xFFu,
-    0x01u, 0x20u, 0x20u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,
+    0x01u, 0x23u, 0x23u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,
     0xBDu, 0xE8u, 0x70u, 0x40u, 0xFFu, 0xF7u, 0xA4u, 0xBFu,
-    0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,
-    0x0Cu, 0x49u, 0x1Au, 0x70u, 0x00u, 0x20u, 0x0Cu, 0x4Au,
-    0x0Cu, 0x4Bu, 0x08u, 0x70u, 0x0Cu, 0x49u, 0x10u, 0x70u,
-    0x18u, 0x70u, 0x0Cu, 0x4Au, 0x0Cu, 0x4Bu, 0x08u, 0x70u,
-    0x0Cu, 0x49u, 0x10u, 0x70u, 0x18u, 0x70u, 0x0Cu, 0x4Bu,
-    0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,
+    0x4Du, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x70u, 0x0Cu, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,
+    0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+    0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+    0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+    0x0Bu, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x80u, 0x22u,
     0x03u, 0xF8u, 0x20u, 0x2Cu, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
+    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+    0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+    0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
     0x28u, 0x60u, 0x00u, 0x40u, 0x01u, 0x4Bu, 0x18u, 0x78u,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
-    0x03u, 0x4Bu, 0x18u, 0x78u, 0x10u, 0xB1u, 0x00u, 0x22u,
-    0x18u, 0x78u, 0x1Au, 0x70u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x0Cu, 0x22u,
-    0x02u, 0xFBu, 0x00u, 0x30u, 0x40u, 0x78u, 0x70u, 0x47u,
-    0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x38u, 0xC3u, 0xB2u,
-    0x07u, 0x2Bu, 0x0Cu, 0xD8u, 0x19u, 0x01u, 0x07u, 0x4Au,
-    0xCBu, 0xB2u, 0x98u, 0x5Cu, 0x51u, 0x1Cu, 0x5Bu, 0x5Cu,
-    0x00u, 0xF0u, 0x0Fu, 0x02u, 0x43u, 0xEAu, 0x02u, 0x20u,
-    0x81u, 0x1Eu, 0x88u, 0xB2u, 0x70u, 0x47u, 0x00u, 0x20u,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0xF0u, 0xB5u,
-    0x2Fu, 0xD8u, 0x18u, 0x4Eu, 0x1Cu, 0x01u, 0x0Cu, 0x27u,
-    0xE3u, 0xB2u, 0x07u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,
-    0x15u, 0x4Du, 0xBFu, 0xB2u, 0xC7u, 0xF5u, 0x00u, 0x77u,
-    0xBAu, 0x42u, 0x1Du, 0x44u, 0x03u, 0xD9u, 0xE2u, 0x88u,
-    0xC2u, 0xF5u, 0x00u, 0x74u, 0xA2u, 0xB2u, 0x0Cu, 0x24u,
-    0x04u, 0xFBu, 0x00u, 0x66u, 0xF4u, 0x78u, 0x44u, 0xEAu,
-    0x12u, 0x26u, 0x0Eu, 0x4Cu, 0x1Eu, 0x55u, 0xD6u, 0xB2u,
-    0x01u, 0x34u, 0x1Eu, 0x55u, 0x49u, 0xB9u, 0x09u, 0x4Au,
-    0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u,
-    0x41u, 0x70u, 0x40u, 0x79u, 0x08u, 0x4Au, 0x98u, 0x54u,
-    0xF0u, 0xBDu, 0x00u, 0x24u, 0xA6u, 0xB2u, 0x96u, 0x42u,
-    0xF1u, 0xD2u, 0x0Eu, 0x5Du, 0x01u, 0x34u, 0x2Eu, 0x70u,
-    0xF8u, 0xE7u, 0xF0u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x88u, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,
-    0x07u, 0x2Bu, 0x0Au, 0xD8u, 0x05u, 0x4Au, 0x0Cu, 0x21u,
-    0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u, 0x41u, 0x70u,
-    0x1Bu, 0x01u, 0x40u, 0x79u, 0x02u, 0x4Au, 0xDBu, 0xB2u,
-    0x98u, 0x54u, 0x70u, 0x47u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFFu, 0x00u,
+    0x1Au, 0xB1u, 0x18u, 0x78u, 0x00u, 0x22u, 0xC0u, 0xB2u,
+    0x1Au, 0x70u, 0x70u, 0x47u, 0x68u, 0xC1u, 0xFFu, 0x1Fu,
+    0x02u, 0x4Bu, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x30u,
+    0x40u, 0x78u, 0x70u, 0x47u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x01u, 0x38u, 0xC3u, 0xB2u, 0x07u, 0x2Bu, 0x0Cu, 0xD8u,
+    0x07u, 0x4Au, 0x1Bu, 0x01u, 0xDBu, 0xB2u, 0x98u, 0x5Cu,
+    0x01u, 0x32u, 0x9Bu, 0x5Cu, 0x00u, 0xF0u, 0x0Fu, 0x00u,
+    0x43u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x38u, 0x80u, 0xB2u,
+    0x70u, 0x47u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0x0Cu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,
+    0x07u, 0x2Bu, 0xF0u, 0xB5u, 0x2Fu, 0xD8u, 0x18u, 0x4Eu,
+    0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,
+    0x1Bu, 0x01u, 0xBFu, 0xB2u, 0x15u, 0x4Du, 0xC7u, 0xF5u,
+    0x00u, 0x77u, 0xDBu, 0xB2u, 0xBAu, 0x42u, 0x1Du, 0x44u,
+    0x03u, 0xD9u, 0xE2u, 0x88u, 0xC2u, 0xF5u, 0x00u, 0x72u,
+    0x92u, 0xB2u, 0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u,
+    0xE7u, 0x78u, 0x0Fu, 0x4Cu, 0x47u, 0xEAu, 0x12u, 0x27u,
+    0x1Fu, 0x55u, 0xD7u, 0xB2u, 0x01u, 0x34u, 0x1Fu, 0x55u,
+    0x49u, 0xB9u, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x60u,
+    0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x09u, 0x4Au,
+    0xC9u, 0xB2u, 0x99u, 0x54u, 0xF0u, 0xBDu, 0x00u, 0x24u,
+    0xA7u, 0xB2u, 0x97u, 0x42u, 0xF1u, 0xD2u, 0x0Fu, 0x5Du,
+    0x01u, 0x34u, 0x2Fu, 0x70u, 0xF8u, 0xE7u, 0xF0u, 0xBDu,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x88u, 0x60u, 0x00u, 0x40u,
+    0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,
+    0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x0Bu, 0xD8u,
+    0x06u, 0x4Au, 0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u,
+    0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x1Bu, 0x01u,
+    0x03u, 0x4Au, 0xDBu, 0xB2u, 0xC9u, 0xB2u, 0x99u, 0x54u,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
     0x0Eu, 0x60u, 0x00u, 0x40u, 0xF8u, 0xB5u, 0x43u, 0x1Eu,
-    0x0Du, 0x46u, 0xD9u, 0xB2u, 0x07u, 0x29u, 0x07u, 0x46u,
-    0x14u, 0x46u, 0x16u, 0xD8u, 0xBDu, 0xB1u, 0x0Au, 0x01u,
-    0x0Cu, 0x4Eu, 0xD3u, 0xB2u, 0x9Eu, 0x19u, 0xFFu, 0xF7u,
-    0x89u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,
-    0x84u, 0xB2u, 0x00u, 0x22u, 0x90u, 0xB2u, 0xA0u, 0x42u,
-    0x03u, 0xD2u, 0x31u, 0x78u, 0xA9u, 0x54u, 0x01u, 0x32u,
-    0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCEu, 0xFFu,
-    0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x2Cu, 0x46u,
+    0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x07u, 0x46u, 0x0Du, 0x46u,
+    0x14u, 0x46u, 0x16u, 0xD8u, 0xB9u, 0xB1u, 0x1Bu, 0x01u,
+    0x0Cu, 0x4Eu, 0xDBu, 0xB2u, 0x1Eu, 0x44u, 0xFFu, 0xF7u,
+    0x87u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,
+    0x84u, 0xB2u, 0x00u, 0x23u, 0x9Au, 0xB2u, 0xA2u, 0x42u,
+    0x03u, 0xD2u, 0x32u, 0x78u, 0xEAu, 0x54u, 0x01u, 0x33u,
+    0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCCu, 0xFFu,
+    0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x0Cu, 0x46u,
     0x20u, 0x46u, 0xF8u, 0xBDu, 0x88u, 0x60u, 0x00u, 0x40u,
-    0x1Bu, 0x4Bu, 0x1Cu, 0x49u, 0x1Au, 0x88u, 0x08u, 0x78u,
-    0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u, 0x1Au, 0x49u,
-    0x1Au, 0x4Bu, 0xCAu, 0xB2u, 0x18u, 0x88u, 0x80u, 0xB2u,
-    0x78u, 0xB1u, 0x19u, 0x4Au, 0x91u, 0x42u, 0x0Bu, 0xD0u,
-    0x5Au, 0x68u, 0x10u, 0x78u, 0x01u, 0xF8u, 0x01u, 0x0Bu,
-    0x5Au, 0x68u, 0x50u, 0x1Cu, 0x58u, 0x60u, 0x1Au, 0x88u,
-    0x50u, 0x1Eu, 0x82u, 0xB2u, 0x1Au, 0x80u, 0xEBu, 0xE7u,
-    0x08u, 0x22u, 0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x08u, 0x2Bu,
-    0x00u, 0xD0u, 0x5Au, 0xB1u, 0x0Fu, 0x48u, 0x01u, 0x78u,
-    0x81u, 0xF0u, 0x80u, 0x03u, 0x0Eu, 0x49u, 0x03u, 0x70u,
-    0x0Fu, 0x20u, 0x0Eu, 0x4Bu, 0x08u, 0x70u, 0x02u, 0x20u,
-    0x18u, 0x70u, 0x04u, 0xE0u, 0x0Au, 0x49u, 0x0Bu, 0x4Bu,
-    0x02u, 0x20u, 0x08u, 0x70u, 0x18u, 0x70u, 0x03u, 0x49u,
-    0x09u, 0x48u, 0x0Au, 0x70u, 0x02u, 0x70u, 0x70u, 0x47u,
-    0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0x60u, 0x00u, 0x40u, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x02u, 0x22u,
-    0x1Au, 0x70u, 0x07u, 0x49u, 0x07u, 0x4Bu, 0x80u, 0x20u,
-    0x0Fu, 0x22u, 0x08u, 0x70u, 0x1Au, 0x70u, 0x06u, 0x49u,
-    0x06u, 0x4Au, 0x00u, 0x20u, 0x08u, 0x70u, 0x10u, 0x70u,
-    0x01u, 0x20u, 0x70u, 0x47u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
-    0xE5u, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
-    0x10u, 0xB5u, 0x15u, 0x4Bu, 0x1Au, 0x78u, 0x15u, 0x4Bu,
-    0x02u, 0xF0u, 0x0Fu, 0x00u, 0x81u, 0x1Eu, 0x18u, 0x88u,
-    0xCAu, 0xB2u, 0x11u, 0x18u, 0x88u, 0xB2u, 0x12u, 0x49u,
-    0x18u, 0x80u, 0x12u, 0x4Bu, 0x18u, 0x88u, 0x80u, 0xB2u,
-    0x70u, 0xB1u, 0x6Au, 0xB1u, 0x58u, 0x68u, 0x11u, 0xF8u,
-    0x01u, 0x4Bu, 0x01u, 0x3Au, 0x04u, 0x70u, 0x58u, 0x68u,
-    0xD2u, 0xB2u, 0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u,
-    0x01u, 0x38u, 0x80u, 0xB2u, 0x18u, 0x80u, 0xECu, 0xE7u,
-    0x09u, 0x49u, 0x0Au, 0x4Bu, 0x0Au, 0x70u, 0x1Au, 0x78u,
-    0x0Bu, 0x21u, 0x82u, 0xF0u, 0x80u, 0x00u, 0x18u, 0x70u,
-    0x07u, 0x4Bu, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0x29u, 0x60u, 0x00u, 0x40u, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x06u, 0x4Au, 0x07u, 0x48u,
-    0x06u, 0x23u, 0x13u, 0x70u, 0x03u, 0x70u, 0x06u, 0x4Bu,
-    0x06u, 0x48u, 0x80u, 0x21u, 0x00u, 0x22u, 0x19u, 0x70u,
-    0x02u, 0x70u, 0x01u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
-    0x05u, 0x4Bu, 0x9Au, 0x68u, 0x3Au, 0xB1u, 0x99u, 0x68u,
-    0x04u, 0x4Au, 0x08u, 0x70u, 0x98u, 0x68u, 0x11u, 0x88u,
-    0x41u, 0x80u, 0x00u, 0x20u, 0x98u, 0x60u, 0x70u, 0x47u,
-    0x60u, 0xC1u, 0xFFu, 0x1Fu, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x32u, 0xB1u,
-    0x19u, 0x78u, 0x09u, 0x4Au, 0x41u, 0xF0u, 0x80u, 0x00u,
-    0x00u, 0x21u, 0x10u, 0x70u, 0x19u, 0x70u, 0x07u, 0x4Bu,
-    0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u, 0xFFu, 0xF7u,
-    0xDFu, 0xFFu, 0x05u, 0x49u, 0x03u, 0x22u, 0x0Au, 0x70u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0x60u, 0x00u, 0x40u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,
+    0x30u, 0xB5u, 0x1Au, 0x4Bu, 0x1Au, 0x48u, 0x1Au, 0x88u,
+    0x01u, 0x78u, 0x0Au, 0x44u, 0x92u, 0xB2u, 0x19u, 0x49u,
+    0x1Au, 0x80u, 0x19u, 0x4Bu, 0xCAu, 0xB2u, 0x1Cu, 0x88u,
+    0xA4u, 0xB2u, 0x84u, 0xB1u, 0x17u, 0x4Au, 0x91u, 0x42u,
+    0x0Cu, 0xD0u, 0x5Au, 0x68u, 0x12u, 0x78u, 0xD2u, 0xB2u,
+    0x01u, 0xF8u, 0x01u, 0x2Bu, 0x5Au, 0x68u, 0x01u, 0x32u,
+    0x5Au, 0x60u, 0x1Au, 0x88u, 0x01u, 0x3Au, 0x92u, 0xB2u,
+    0x1Au, 0x80u, 0xEAu, 0xE7u, 0x08u, 0x22u, 0x03u, 0x78u,
+    0x0Fu, 0x4Cu, 0x08u, 0x2Bu, 0x0Fu, 0x4Bu, 0x00u, 0xD0u,
+    0x42u, 0xB1u, 0x0Fu, 0x49u, 0x0Du, 0x78u, 0x85u, 0xF0u,
+    0x80u, 0x05u, 0x0Du, 0x70u, 0x0Fu, 0x21u, 0x21u, 0x70u,
+    0x02u, 0x21u, 0x01u, 0xE0u, 0x02u, 0x21u, 0x21u, 0x70u,
+    0x19u, 0x70u, 0x0Au, 0x4Bu, 0x02u, 0x70u, 0x1Au, 0x70u,
+    0x30u, 0xBDu, 0x00u, 0xBFu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,
+    0x07u, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x07u, 0x4Bu,
+    0x80u, 0x22u, 0x1Au, 0x70u, 0x06u, 0x4Bu, 0x0Fu, 0x22u,
+    0x1Au, 0x70u, 0x06u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,
+    0x05u, 0x4Au, 0x01u, 0x20u, 0x13u, 0x70u, 0x70u, 0x47u,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
+    0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x15u, 0x4Bu,
+    0x1Au, 0x78u, 0x15u, 0x4Bu, 0x02u, 0xF0u, 0x0Fu, 0x02u,
+    0x19u, 0x88u, 0x02u, 0x3Au, 0xD2u, 0xB2u, 0x11u, 0x44u,
+    0x89u, 0xB2u, 0x19u, 0x80u, 0x11u, 0x49u, 0x12u, 0x4Bu,
+    0x18u, 0x88u, 0x80u, 0xB2u, 0x78u, 0xB1u, 0x72u, 0xB1u,
+    0x58u, 0x68u, 0x11u, 0xF8u, 0x01u, 0x4Bu, 0x01u, 0x3Au,
+    0xE4u, 0xB2u, 0x04u, 0x70u, 0x58u, 0x68u, 0xD2u, 0xB2u,
+    0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u, 0x01u, 0x38u,
+    0x80u, 0xB2u, 0x18u, 0x80u, 0xEBu, 0xE7u, 0x09u, 0x4Bu,
+    0x1Au, 0x70u, 0x09u, 0x4Bu, 0x1Au, 0x78u, 0x82u, 0xF0u,
+    0x80u, 0x02u, 0x1Au, 0x70u, 0x07u, 0x4Bu, 0x0Bu, 0x22u,
+    0x1Au, 0x70u, 0x10u, 0xBDu, 0x29u, 0x60u, 0x00u, 0x40u,
+    0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x06u, 0x4Au, 0x06u, 0x23u, 0x13u, 0x70u, 0x06u, 0x4Au,
+    0x01u, 0x20u, 0x13u, 0x70u, 0x05u, 0x4Bu, 0x80u, 0x22u,
+    0x1Au, 0x70u, 0x05u, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x70u,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x9Au, 0x68u,
+    0x3Au, 0xB1u, 0x9Au, 0x68u, 0x04u, 0x49u, 0x10u, 0x70u,
+    0x9Au, 0x68u, 0x09u, 0x88u, 0x51u, 0x80u, 0x00u, 0x22u,
+    0x9Au, 0x60u, 0x70u, 0x47u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x12u, 0x4Bu,
+    0x1Au, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x1Bu, 0x78u,
+    0xDBu, 0xB2u, 0x1Au, 0x06u, 0x02u, 0xD5u, 0x0Fu, 0x4Au,
+    0x13u, 0x70u, 0x08u, 0xBDu, 0x02u, 0x20u, 0xFFu, 0xF7u,
+    0xE1u, 0xFFu, 0x0Du, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+    0x60u, 0x03u, 0x20u, 0x2Bu, 0x05u, 0xD0u, 0x40u, 0x2Bu,
+    0x06u, 0xD0u, 0x43u, 0xB9u, 0x00u, 0xF0u, 0x94u, 0xFCu,
+    0x04u, 0xE0u, 0x00u, 0xF0u, 0xE1u, 0xFDu, 0x01u, 0xE0u,
+    0x00u, 0xF0u, 0xD2u, 0xFDu, 0x10u, 0xB9u, 0x03u, 0x4Bu,
+    0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+    0x28u, 0x60u, 0x00u, 0x40u, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x08u, 0x49u,
+    0x08u, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x88u, 0x09u, 0x78u,
+    0x0Au, 0x44u, 0x92u, 0xB2u, 0x1Au, 0x80u, 0x06u, 0x4Bu,
+    0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xB6u, 0xFFu,
+    0x04u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu,
+    0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u,
+    0x04u, 0x2Bu, 0x07u, 0xD0u, 0x06u, 0x2Bu, 0x09u, 0xD0u,
+    0x02u, 0x2Bu, 0x0Du, 0xD1u, 0xBDu, 0xE8u, 0x08u, 0x40u,
+    0xFFu, 0xF7u, 0xD8u, 0xBFu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+    0xFFu, 0xF7u, 0x48u, 0xBFu, 0x03u, 0x20u, 0xFFu, 0xF7u,
+    0x95u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+    0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,
     0x00u, 0x22u, 0x01u, 0x20u, 0x1Au, 0x70u, 0xFFu, 0xF7u,
-    0xCBu, 0xFFu, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x18u, 0x78u,
-    0x04u, 0x28u, 0x05u, 0xD0u, 0x06u, 0x28u, 0x05u, 0xD0u,
-    0x02u, 0x28u, 0x05u, 0xD1u, 0xFFu, 0xF7u, 0x04u, 0xBFu,
-    0xFFu, 0xF7u, 0xE4u, 0xBFu, 0xFFu, 0xF7u, 0xC4u, 0xBFu,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x08u, 0x49u, 0x08u, 0x4Bu, 0x1Au, 0x88u,
-    0x08u, 0x78u, 0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u,
-    0x06u, 0x4Bu, 0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0xA2u, 0xFFu, 0x04u, 0x49u, 0x03u, 0x22u,
-    0x0Au, 0x70u, 0x08u, 0xBDu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
-    0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Bu, 0x4Bu,
-    0x18u, 0x78u, 0x04u, 0x28u, 0x07u, 0xD0u, 0x06u, 0x28u,
-    0x09u, 0xD0u, 0x02u, 0x28u, 0x0Du, 0xD1u, 0xBDu, 0xE8u,
-    0x08u, 0x40u, 0xFFu, 0xF7u, 0xD9u, 0xBFu, 0xBDu, 0xE8u,
-    0x08u, 0x40u, 0xFFu, 0xF7u, 0x35u, 0xBFu, 0x03u, 0x20u,
-    0xFFu, 0xF7u, 0x82u, 0xFFu, 0x02u, 0x49u, 0x03u, 0x22u,
-    0x0Au, 0x70u, 0x08u, 0xBDu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x11u, 0x4Bu,
-    0x1Au, 0x78u, 0x1Au, 0x70u, 0x18u, 0x78u, 0x02u, 0x06u,
-    0x02u, 0xD5u, 0x0Fu, 0x4Bu, 0x18u, 0x70u, 0x08u, 0xBDu,
-    0x02u, 0x20u, 0xFFu, 0xF7u, 0x6Du, 0xFFu, 0x0Du, 0x49u,
-    0x0Bu, 0x78u, 0x03u, 0xF0u, 0x60u, 0x02u, 0x20u, 0x2Au,
-    0x05u, 0xD0u, 0x40u, 0x2Au, 0x06u, 0xD0u, 0x42u, 0xB9u,
-    0x00u, 0xF0u, 0x4Au, 0xFCu, 0x04u, 0xE0u, 0x00u, 0xF0u,
-    0x8Du, 0xFDu, 0x01u, 0xE0u, 0x00u, 0xF0u, 0x7Eu, 0xFDu,
-    0x10u, 0xB9u, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x08u, 0xB5u, 0x22u, 0x4Bu, 0x1Au, 0x78u, 0xD0u, 0xB2u,
-    0x00u, 0xF0u, 0x10u, 0x01u, 0xCBu, 0xB2u, 0x00u, 0x2Bu,
-    0x3Bu, 0xD0u, 0x52u, 0xB2u, 0x00u, 0x2Au, 0x0Au, 0xDAu,
-    0x00u, 0xF0u, 0x0Fu, 0x01u, 0x01u, 0x29u, 0x34u, 0xD1u,
-    0xFFu, 0xF7u, 0xC4u, 0xFFu, 0x1Au, 0x4Bu, 0x18u, 0x78u,
-    0x00u, 0x06u, 0x0Du, 0xD5u, 0x08u, 0xBDu, 0x00u, 0xF0u,
-    0x40u, 0x01u, 0xCBu, 0xB2u, 0x13u, 0xB1u, 0xFFu, 0xF7u,
-    0x71u, 0xFFu, 0x05u, 0xE0u, 0x00u, 0xF0u, 0x20u, 0x00u,
-    0xC2u, 0xB2u, 0x12u, 0xB3u, 0xFFu, 0xF7u, 0x96u, 0xFFu,
-    0x10u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x06u, 0x1Cu, 0xD4u,
-    0x10u, 0x4Bu, 0x11u, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u,
-    0x41u, 0xEAu, 0x00u, 0x03u, 0x0Fu, 0x48u, 0x03u, 0x70u,
-    0x02u, 0x78u, 0x93u, 0x42u, 0x11u, 0xD1u, 0x0Au, 0x49u,
-    0x08u, 0x4Bu, 0x0Au, 0x78u, 0x18u, 0x78u, 0x00u, 0xF0u,
-    0x80u, 0x00u, 0xC0u, 0xB2u, 0x20u, 0xB9u, 0x0Au, 0x78u,
-    0x1Au, 0x70u, 0x19u, 0x78u, 0x01u, 0xF0u, 0x0Fu, 0x02u,
-    0x03u, 0x4Bu, 0x18u, 0x78u, 0x82u, 0x42u, 0xEEu, 0xD1u,
-    0x08u, 0xBDu, 0x08u, 0xBDu, 0x28u, 0x60u, 0x00u, 0x40u,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,
+    0x85u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+    0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
+    0x1Au, 0x78u, 0x32u, 0xB1u, 0x19u, 0x78u, 0x09u, 0x4Au,
+    0x41u, 0xF0u, 0x80u, 0x01u, 0x11u, 0x70u, 0x00u, 0x22u,
+    0x1Au, 0x70u, 0x07u, 0x4Bu, 0x00u, 0x22u, 0x01u, 0x20u,
+    0x1Au, 0x70u, 0xFFu, 0xF7u, 0x6Bu, 0xFFu, 0x05u, 0x4Bu,
+    0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+    0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x04u, 0x2Bu,
+    0x05u, 0xD0u, 0x06u, 0x2Bu, 0x05u, 0xD0u, 0x02u, 0x2Bu,
+    0x05u, 0xD1u, 0xFFu, 0xF7u, 0xA1u, 0xBEu, 0xFFu, 0xF7u,
+    0xC5u, 0xBFu, 0xFFu, 0xF7u, 0xD3u, 0xBFu, 0x70u, 0x47u,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x1Du, 0x4Cu,
+    0x23u, 0x78u, 0xDBu, 0xB2u, 0xDAu, 0x06u, 0x33u, 0xD5u,
+    0x18u, 0x06u, 0x0Au, 0xD5u, 0x03u, 0xF0u, 0x0Fu, 0x03u,
+    0x01u, 0x2Bu, 0x2Du, 0xD1u, 0xFFu, 0xF7u, 0x4Eu, 0xFFu,
+    0x17u, 0x4Bu, 0x1Bu, 0x78u, 0x19u, 0x06u, 0x09u, 0xD5u,
+    0x10u, 0xBDu, 0x5Au, 0x06u, 0x02u, 0xD5u, 0xFFu, 0xF7u,
+    0xD7u, 0xFFu, 0x03u, 0xE0u, 0x9Bu, 0x06u, 0x1Fu, 0xD5u,
+    0xFFu, 0xF7u, 0x86u, 0xFFu, 0x23u, 0x78u, 0x1Bu, 0x06u,
+    0x1Au, 0xD4u, 0x10u, 0x4Bu, 0x10u, 0x4Au, 0x1Bu, 0x78u,
+    0x12u, 0x78u, 0x13u, 0x43u, 0x0Fu, 0x4Au, 0x13u, 0x70u,
+    0x12u, 0x78u, 0x93u, 0x42u, 0x10u, 0xD1u, 0x0Au, 0x4Bu,
+    0x08u, 0x49u, 0x1Au, 0x78u, 0x20u, 0x78u, 0xD2u, 0xB2u,
+    0x00u, 0x06u, 0x05u, 0xD4u, 0x1Au, 0x78u, 0xD2u, 0xB2u,
+    0x0Au, 0x70u, 0x0Au, 0x78u, 0x02u, 0xF0u, 0x0Fu, 0x02u,
+    0x1Bu, 0x78u, 0x9Au, 0x42u, 0xEFu, 0xD1u, 0x10u, 0xBDu,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,
     0x05u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x80u, 0x05u, 0x4Au,
     0x91u, 0x68u, 0x19u, 0xB1u, 0x91u, 0x68u, 0x0Bu, 0x70u,
-    0x90u, 0x68u, 0x43u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x0Cu, 0x49u, 0x0Cu, 0x4Bu, 0x04u, 0x22u,
-    0x80u, 0x20u, 0x1Au, 0x70u, 0x08u, 0x70u, 0xFFu, 0xF7u,
-    0xE7u, 0xFFu, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x58u, 0x1Eu,
-    0x09u, 0x4Bu, 0x01u, 0x78u, 0x18u, 0x88u, 0x41u, 0xEAu,
-    0x02u, 0x22u, 0x81u, 0xB2u, 0x91u, 0x42u, 0x88u, 0xBFu,
-    0x1Au, 0x80u, 0x06u, 0x4Bu, 0x0Bu, 0x22u, 0x1Au, 0x70u,
-    0x01u, 0x20u, 0x08u, 0xBDu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
-    0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x98u, 0xB2u,
-    0x10u, 0xB9u, 0xFFu, 0xF7u, 0x5Bu, 0xFEu, 0x14u, 0xE0u,
-    0x0Cu, 0x49u, 0x0Du, 0x4Bu, 0x02u, 0x22u, 0x00u, 0x20u,
-    0x0Au, 0x70u, 0x18u, 0x70u, 0xFFu, 0xF7u, 0xBCu, 0xFFu,
-    0x0Au, 0x49u, 0x48u, 0x1Eu, 0x0Au, 0x78u, 0x03u, 0x78u,
-    0x43u, 0xEAu, 0x02u, 0x21u, 0x22u, 0x88u, 0x90u, 0xB2u,
-    0x88u, 0x42u, 0x88u, 0xBFu, 0x21u, 0x80u, 0xFFu, 0xF7u,
-    0xFBu, 0xFDu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
-    0x09u, 0x4Bu, 0x0Au, 0x48u, 0x1Bu, 0x78u, 0x02u, 0x7Bu,
-    0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x03u, 0xD0u,
-    0xC3u, 0x7Bu, 0x83u, 0xF0u, 0x80u, 0x02u, 0xC2u, 0x73u,
-    0x01u, 0x21u, 0x41u, 0x73u, 0x04u, 0x48u, 0x03u, 0x78u,
-    0x03u, 0xF0u, 0xFEu, 0x02u, 0x02u, 0x70u, 0x70u, 0x47u,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x0Au, 0x48u,
-    0x1Bu, 0x78u, 0x02u, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x01u,
-    0x01u, 0x29u, 0x03u, 0xD0u, 0xC3u, 0x7Eu, 0x83u, 0xF0u,
-    0x80u, 0x02u, 0xC2u, 0x76u, 0x01u, 0x21u, 0x41u, 0x76u,
-    0x04u, 0x48u, 0x03u, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x02u,
-    0x02u, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,
-    0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,
-    0x70u, 0x47u, 0xFFu, 0xF7u, 0xE7u, 0xBCu, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x0Bu, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,
-    0xC8u, 0xB2u, 0x00u, 0xF0u, 0x59u, 0xF9u, 0x09u, 0x4Au,
-    0x09u, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x68u, 0x06u, 0x4Bu, 0x50u, 0x6Au, 0x01u, 0x78u,
-    0x19u, 0x80u, 0x58u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x0Du, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,
-    0xC8u, 0xB2u, 0x00u, 0xF0u, 0x39u, 0xF9u, 0x0Bu, 0x4Au,
-    0x0Bu, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x68u, 0xD3u, 0x69u, 0x07u, 0x4Au, 0x59u, 0x78u,
-    0x13u, 0xF8u, 0x02u, 0x0Bu, 0x40u, 0xEAu, 0x01u, 0x21u,
-    0x11u, 0x80u, 0x53u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x10u, 0xB5u, 0x16u, 0x4Cu, 0x00u, 0x23u, 0x16u, 0x48u,
-    0x23u, 0x80u, 0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,
-    0x00u, 0xF0u, 0x12u, 0xF9u, 0x13u, 0x49u, 0x14u, 0x4Bu,
-    0x1Bu, 0x78u, 0x0Au, 0x78u, 0x00u, 0xEBu, 0xC2u, 0x00u,
-    0x41u, 0x69u, 0xD2u, 0xB9u, 0x11u, 0x4Au, 0x01u, 0x3Bu,
-    0x10u, 0x78u, 0xDAu, 0xB2u, 0x01u, 0xEBu, 0xC0u, 0x01u,
-    0x02u, 0x2Au, 0x49u, 0x68u, 0x11u, 0xD8u, 0x0Eu, 0x4Au,
-    0x01u, 0xEBu, 0xC3u, 0x00u, 0x12u, 0x78u, 0x11u, 0xF8u,
-    0x33u, 0x10u, 0x91u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u,
-    0x5Au, 0x43u, 0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u,
-    0x8Au, 0x5Au, 0x99u, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u,
-    0xA1u, 0x60u, 0x10u, 0xBDu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x03u, 0x60u, 0x00u, 0x40u, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Au, 0x4Bu,
-    0x3Au, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u, 0x09u, 0x06u,
-    0x34u, 0xD5u, 0x51u, 0x1Cu, 0x0Bu, 0x78u, 0x5Au, 0x1Eu,
-    0x05u, 0x2Au, 0x67u, 0xD8u, 0xDFu, 0xE8u, 0x02u, 0xF0u,
-    0x10u, 0x18u, 0x27u, 0x66u, 0x66u, 0x03u, 0x34u, 0x48u,
-    0x01u, 0x78u, 0x21u, 0x29u, 0x02u, 0xD1u, 0xFFu, 0xF7u,
-    0x6Bu, 0xFFu, 0x07u, 0xE0u, 0x03u, 0x78u, 0x22u, 0x2Bu,
-    0x58u, 0xD1u, 0xFFu, 0xF7u, 0x85u, 0xFFu, 0x01u, 0xE0u,
-    0xFFu, 0xF7u, 0xA6u, 0xFFu, 0x2Du, 0x49u, 0x0Bu, 0x88u,
-    0x98u, 0xB2u, 0x00u, 0x28u, 0x4Eu, 0xD0u, 0x0Au, 0xE0u,
-    0x00u, 0x28u, 0x4Bu, 0xD1u, 0x2Au, 0x4Bu, 0x18u, 0x78u,
-    0x00u, 0x28u, 0x47u, 0xD1u, 0x27u, 0x48u, 0x01u, 0x22u,
-    0x28u, 0x49u, 0x02u, 0x80u, 0x41u, 0x60u, 0xBDu, 0xE8u,
-    0x10u, 0x40u, 0xFFu, 0xF7u, 0xEDu, 0xBEu, 0x00u, 0x28u,
-    0x3Cu, 0xD1u, 0x22u, 0x48u, 0x01u, 0x22u, 0x02u, 0x80u,
-    0x23u, 0x49u, 0xF3u, 0xE7u, 0x13u, 0x78u, 0x1Au, 0x06u,
-    0x34u, 0xD4u, 0x22u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x29u,
-    0x05u, 0xD0u, 0x2Fu, 0xD3u, 0x0Au, 0x29u, 0x0Du, 0xD0u,
-    0x0Bu, 0x29u, 0x2Bu, 0xD1u, 0x22u, 0xE0u, 0xFFu, 0xF7u,
-    0x7Bu, 0xFFu, 0x18u, 0x4Bu, 0x1Au, 0x88u, 0x90u, 0xB2u,
-    0x00u, 0x28u, 0x23u, 0xD0u, 0xBDu, 0xE8u, 0x10u, 0x40u,
-    0xFFu, 0xF7u, 0xAAu, 0xBEu, 0xF0u, 0xB9u, 0x14u, 0x48u,
-    0x01u, 0x78u, 0xD9u, 0xB9u, 0x44u, 0x1Cu, 0x23u, 0x78u,
-    0x12u, 0x4Au, 0x13u, 0x70u, 0x14u, 0x4Bu, 0x14u, 0x78u,
-    0x18u, 0x78u, 0x84u, 0x42u, 0x01u, 0xD2u, 0x19u, 0x70u,
-    0x04u, 0xE0u, 0x19u, 0x78u, 0x01u, 0x29u, 0x01u, 0xD9u,
-    0x12u, 0x78u, 0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u,
-    0xFFu, 0xF7u, 0x6Cu, 0xBDu, 0x30u, 0xB9u, 0x08u, 0x48u,
-    0x03u, 0x78u, 0x01u, 0x2Bu, 0x02u, 0xD8u, 0x02u, 0x78u,
-    0x07u, 0x4Bu, 0xF2u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,
+    0x92u, 0x68u, 0x53u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x9Bu, 0xB2u,
+    0x13u, 0xB9u, 0xFFu, 0xF7u, 0x85u, 0xFEu, 0x14u, 0xE0u,
+    0x0Cu, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x0Cu, 0x4Bu,
+    0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xE0u, 0xFFu,
+    0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x3Bu, 0x1Bu, 0x78u,
+    0x43u, 0xEAu, 0x02u, 0x23u, 0x22u, 0x88u, 0x92u, 0xB2u,
+    0x9Au, 0x42u, 0x88u, 0xBFu, 0x23u, 0x80u, 0xFFu, 0xF7u,
+    0x27u, 0xFEu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
+    0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,
+    0x0Bu, 0x4Bu, 0x80u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u,
+    0xBFu, 0xFFu, 0x0Au, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x78u,
+    0x01u, 0x3Bu, 0x1Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x22u,
+    0x07u, 0x4Bu, 0x19u, 0x88u, 0x89u, 0xB2u, 0x91u, 0x42u,
+    0x88u, 0xBFu, 0x1Au, 0x80u, 0x05u, 0x4Bu, 0x0Bu, 0x22u,
+    0x1Au, 0x70u, 0x08u, 0xBDu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x09u, 0x4Bu, 0x1Bu, 0x78u, 0x09u, 0x4Bu, 0x1Au, 0x7Bu,
+    0x02u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au, 0x03u, 0xD0u,
+    0xDAu, 0x7Bu, 0x82u, 0xF0u, 0x80u, 0x02u, 0xDAu, 0x73u,
+    0x01u, 0x22u, 0x5Au, 0x73u, 0x04u, 0x4Bu, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,
+    0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x1Bu, 0x78u,
+    0x09u, 0x4Bu, 0x1Au, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x02u,
+    0x01u, 0x2Au, 0x03u, 0xD0u, 0xDAu, 0x7Eu, 0x82u, 0xF0u,
+    0x80u, 0x02u, 0xDAu, 0x76u, 0x01u, 0x22u, 0x5Au, 0x76u,
+    0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFDu, 0x02u,
+    0x1Au, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,
+    0x70u, 0x47u, 0xFFu, 0xF7u, 0xEBu, 0xBCu, 0x00u, 0x00u,
+    0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,
+    0xC0u, 0xB2u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x0Au, 0x4Bu,
+    0x0Au, 0x49u, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xEBu,
+    0xC3u, 0x00u, 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu,
+    0xC3u, 0x03u, 0x5Bu, 0x68u, 0x5Au, 0x6Au, 0x06u, 0x4Bu,
+    0x11u, 0x78u, 0xC9u, 0xB2u, 0x19u, 0x80u, 0x5Au, 0x60u,
+    0x08u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Du, 0x4Bu,
+    0x18u, 0x78u, 0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u,
+    0x29u, 0xF9u, 0x0Bu, 0x4Bu, 0x0Bu, 0x49u, 0x1Bu, 0x78u,
+    0xDBu, 0xB2u, 0x00u, 0xEBu, 0xC3u, 0x00u, 0x42u, 0x69u,
+    0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x03u, 0x5Bu, 0x68u,
+    0xDBu, 0x69u, 0x59u, 0x78u, 0x13u, 0xF8u, 0x02u, 0x2Bu,
+    0x42u, 0xEAu, 0x01u, 0x21u, 0x04u, 0x4Au, 0x11u, 0x80u,
+    0x53u, 0x60u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x19u, 0x4Cu,
+    0x00u, 0x23u, 0x23u, 0x80u, 0x18u, 0x4Bu, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u, 0x02u, 0xF9u,
+    0x16u, 0x4Bu, 0x17u, 0x4Au, 0x1Bu, 0x78u, 0x12u, 0x78u,
+    0xDBu, 0xB2u, 0xD2u, 0xB2u, 0x00u, 0xEBu, 0xC2u, 0x00u,
+    0x41u, 0x69u, 0xEAu, 0xB9u, 0x13u, 0x4Au, 0x12u, 0x78u,
+    0x01u, 0xEBu, 0xC2u, 0x02u, 0x51u, 0x68u, 0x5Au, 0x1Eu,
+    0x02u, 0x2Au, 0x15u, 0xD8u, 0x10u, 0x4Au, 0x03u, 0xF1u,
+    0x00u, 0x53u, 0x01u, 0x3Bu, 0x12u, 0x78u, 0x01u, 0xEBu,
+    0xC3u, 0x00u, 0x11u, 0xF8u, 0x33u, 0x30u, 0xD2u, 0xB2u,
+    0x93u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u, 0x5Au, 0x43u,
+    0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u, 0x8Au, 0x5Au,
+    0x9Bu, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u, 0xA3u, 0x60u,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x03u, 0x60u, 0x00u, 0x40u,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Cu, 0x4Bu,
+    0x3Cu, 0x4Au, 0x1Bu, 0x78u, 0x11u, 0x78u, 0xDBu, 0xB2u,
+    0x09u, 0x06u, 0x34u, 0xD5u, 0x01u, 0x32u, 0x12u, 0x78u,
+    0x01u, 0x3Au, 0x05u, 0x2Au, 0x6Au, 0xD8u, 0xDFu, 0xE8u,
+    0x02u, 0xF0u, 0x10u, 0x18u, 0x27u, 0x69u, 0x69u, 0x03u,
+    0x35u, 0x4Bu, 0x1Au, 0x78u, 0x21u, 0x2Au, 0x02u, 0xD1u,
+    0xFFu, 0xF7u, 0x62u, 0xFFu, 0x07u, 0xE0u, 0x1Bu, 0x78u,
+    0x22u, 0x2Bu, 0x5Bu, 0xD1u, 0xFFu, 0xF7u, 0x7Eu, 0xFFu,
+    0x01u, 0xE0u, 0xFFu, 0xF7u, 0x9Fu, 0xFFu, 0x2Fu, 0x4Bu,
+    0x1Bu, 0x88u, 0x9Bu, 0xB2u, 0x00u, 0x2Bu, 0x51u, 0xD0u,
+    0x0Au, 0xE0u, 0x00u, 0x2Bu, 0x4Eu, 0xD1u, 0x2Cu, 0x4Bu,
+    0x1Bu, 0x78u, 0x00u, 0x2Bu, 0x4Au, 0xD1u, 0x29u, 0x4Bu,
+    0x01u, 0x22u, 0x1Au, 0x80u, 0x29u, 0x4Au, 0x5Au, 0x60u,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xC0u, 0xBEu,
+    0x00u, 0x2Bu, 0x3Fu, 0xD1u, 0x23u, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x80u, 0x25u, 0x4Au, 0xF3u, 0xE7u, 0x12u, 0x78u,
+    0x12u, 0x06u, 0x37u, 0xD4u, 0x23u, 0x4Au, 0x12u, 0x78u,
+    0xD2u, 0xB2u, 0x0Au, 0x2Au, 0x0Du, 0xD0u, 0x0Bu, 0x2Au,
+    0x27u, 0xD0u, 0x09u, 0x2Au, 0x2Eu, 0xD1u, 0xFFu, 0xF7u,
+    0x75u, 0xFFu, 0x1Au, 0x4Bu, 0x1Bu, 0x88u, 0x9Bu, 0xB2u,
+    0x43u, 0xB3u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
+    0xCBu, 0xBEu, 0x1Bu, 0xBBu, 0x16u, 0x4Bu, 0x1Bu, 0x78u,
+    0x03u, 0xF0u, 0xFFu, 0x01u, 0xF3u, 0xB9u, 0x12u, 0x4Bu,
+    0x14u, 0x4Au, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x13u, 0x70u,
+    0x15u, 0x4Bu, 0x14u, 0x78u, 0x18u, 0x78u, 0x84u, 0x42u,
+    0x01u, 0xD2u, 0x19u, 0x70u, 0x05u, 0xE0u, 0x19u, 0x78u,
+    0x01u, 0x29u, 0x02u, 0xD9u, 0x12u, 0x78u, 0xD2u, 0xB2u,
+    0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
+    0x67u, 0xBDu, 0x3Bu, 0xB9u, 0x08u, 0x4Bu, 0x1Au, 0x78u,
+    0x01u, 0x2Au, 0x03u, 0xD8u, 0x1Au, 0x78u, 0x08u, 0x4Bu,
+    0xD2u, 0xB2u, 0xF1u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,
     0x04u, 0x60u, 0x00u, 0x40u, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x03u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x02u, 0x60u, 0x00u, 0x40u, 0xEAu, 0xC1u, 0xFFu, 0x1Fu,
-    0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,
-    0xEBu, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x01u, 0x22u,
-    0x02u, 0xF1u, 0x0Fu, 0x03u, 0x18u, 0x01u, 0x09u, 0x2Au,
-    0xC3u, 0xB2u, 0x3Bu, 0xD0u, 0x1Fu, 0x49u, 0x03u, 0xF1u,
-    0x80u, 0x44u, 0x0Cu, 0x20u, 0x04u, 0xF5u, 0xC1u, 0x45u,
-    0x00u, 0xFBu, 0x02u, 0x14u, 0x28u, 0x70u, 0x1Cu, 0x49u,
-    0x65u, 0x79u, 0x59u, 0x18u, 0x25u, 0xB1u, 0x24u, 0x79u,
-    0x24u, 0x06u, 0x58u, 0xBFu, 0x08u, 0x20u, 0x00u, 0xE0u,
-    0x80u, 0x20u, 0x08u, 0x70u, 0x17u, 0x49u, 0x0Cu, 0x24u,
-    0x58u, 0x18u, 0x14u, 0x49u, 0x04u, 0xFBu, 0x02u, 0x11u,
-    0x0Cu, 0x89u, 0x01u, 0x32u, 0xC4u, 0xF3u, 0x07u, 0x24u,
-    0x04u, 0x70u, 0x0Cu, 0x89u, 0x12u, 0x48u, 0xE4u, 0xB2u,
-    0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u, 0x11u, 0x48u,
-    0xE4u, 0xB2u, 0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u,
-    0x0Fu, 0x48u, 0xC4u, 0xF3u, 0x07u, 0x24u, 0x18u, 0x18u,
-    0x04u, 0x70u, 0xCCu, 0x88u, 0x0Du, 0x48u, 0xE4u, 0xB2u,
-    0x18u, 0x18u, 0x04u, 0x70u, 0x0Cu, 0x48u, 0xD2u, 0xB2u,
-    0x18u, 0x18u, 0xCBu, 0x88u, 0xC3u, 0xF3u, 0x07u, 0x21u,
-    0x01u, 0x70u, 0xBDu, 0xE7u, 0x09u, 0x49u, 0xFFu, 0x22u,
-    0x0Au, 0x70u, 0x30u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
+    0x03u, 0x60u, 0x00u, 0x40u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x02u, 0x60u, 0x00u, 0x40u, 0xE2u, 0xC1u, 0xFFu, 0x1Fu,
+    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,
+    0xE3u, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x1Cu, 0x4Bu,
+    0x01u, 0x21u, 0x1Cu, 0x4Au, 0x0Cu, 0x20u, 0x00u, 0xFBu,
+    0x01u, 0x24u, 0x83u, 0xF8u, 0x72u, 0x00u, 0x65u, 0x79u,
+    0x25u, 0xB1u, 0x24u, 0x79u, 0x24u, 0x06u, 0x58u, 0xBFu,
+    0x08u, 0x20u, 0x00u, 0xE0u, 0x80u, 0x20u, 0x18u, 0x70u,
+    0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x22u, 0x10u, 0x89u,
+    0x01u, 0x31u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x03u, 0xF8u,
+    0x02u, 0x0Cu, 0x10u, 0x89u, 0x09u, 0x29u, 0xC0u, 0xB2u,
+    0x03u, 0xF8u, 0x01u, 0x0Cu, 0xD0u, 0x88u, 0x03u, 0xF1u,
+    0x10u, 0x03u, 0xC0u, 0xB2u, 0x83u, 0xF8u, 0x68u, 0x00u,
+    0xD0u, 0x88u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x83u, 0xF8u,
+    0x69u, 0x00u, 0xD0u, 0x88u, 0xC0u, 0xB2u, 0x83u, 0xF8u,
+    0x66u, 0x00u, 0xD2u, 0x88u, 0xC2u, 0xF3u, 0x07u, 0x22u,
+    0x83u, 0xF8u, 0x67u, 0x20u, 0xCDu, 0xD1u, 0x04u, 0x4Bu,
+    0xFFu, 0x22u, 0x1Au, 0x70u, 0x30u, 0xBDu, 0x00u, 0xBFu,
+    0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x0Au, 0x60u, 0x00u, 0x40u, 0x07u, 0x4Bu, 0x1Au, 0x78u,
+    0x07u, 0x4Bu, 0x03u, 0xEBu, 0xC2u, 0x03u, 0x5Bu, 0x68u,
+    0x03u, 0xF1u, 0x08u, 0x02u, 0x1Bu, 0x7Au, 0x83u, 0x42u,
+    0x86u, 0xBFu, 0x02u, 0xEBu, 0xC0u, 0x00u, 0x40u, 0x68u,
+    0x00u, 0x20u, 0x70u, 0x47u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+    0x8Cu, 0x21u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x39u, 0x4Bu,
+    0x1Au, 0x78u, 0x00u, 0x2Au, 0x6Cu, 0xD0u, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0xE2u, 0xFFu,
+    0xC3u, 0x68u, 0x04u, 0x7Au, 0x08u, 0x33u, 0x03u, 0xEBu,
+    0xC4u, 0x04u, 0xA3u, 0x42u, 0x60u, 0xD0u, 0x13u, 0xF8u,
+    0x08u, 0x2Cu, 0x31u, 0x49u, 0x31u, 0x48u, 0x8Du, 0x5Cu,
+    0x80u, 0x5Cu, 0x85u, 0x42u, 0x56u, 0xD0u, 0x89u, 0x5Cu,
+    0x13u, 0xF8u, 0x07u, 0x0Cu, 0x88u, 0x42u, 0x51u, 0xD1u,
+    0x2Du, 0x49u, 0x09u, 0x78u, 0x8Au, 0x42u, 0x4Du, 0xD1u,
+    0x13u, 0xF8u, 0x06u, 0x0Cu, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+    0x00u, 0xF0u, 0x7Fu, 0x02u, 0x51u, 0x1Eu, 0x10u, 0xF0u,
+    0x80u, 0x0Fu, 0x28u, 0x48u, 0x4Fu, 0xEAu, 0x01u, 0x11u,
+    0x4Fu, 0xF0u, 0x0Cu, 0x05u, 0xC9u, 0xB2u, 0x06u, 0xF0u,
+    0x03u, 0x06u, 0x05u, 0xFBu, 0x02u, 0x05u, 0x06u, 0xD0u,
+    0x01u, 0x27u, 0xBEu, 0x42u, 0x6Fu, 0x70u, 0x14u, 0xBFu,
+    0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u, 0x00u, 0x27u,
+    0x01u, 0x2Eu, 0x6Fu, 0x70u, 0x14u, 0xBFu, 0x09u, 0x26u,
+    0x05u, 0x26u, 0x6Eu, 0x71u, 0x1Cu, 0x4Du, 0x01u, 0x26u,
+    0x6Eu, 0x54u, 0x0Cu, 0x25u, 0x55u, 0x43u, 0x33u, 0xF8u,
+    0x04u, 0x6Cu, 0x42u, 0x19u, 0x16u, 0x81u, 0x13u, 0xF8u,
+    0x06u, 0x6Cu, 0x16u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+    0x46u, 0x55u, 0x00u, 0x20u, 0xD0u, 0x70u, 0x15u, 0x89u,
+    0x14u, 0x48u, 0xC5u, 0xF3u, 0x07u, 0x25u, 0x45u, 0x54u,
+    0x15u, 0x89u, 0x01u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,
+    0xD5u, 0x88u, 0x79u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,
+    0xD5u, 0x88u, 0x01u, 0x30u, 0xC5u, 0xF3u, 0x07u, 0x25u,
+    0x45u, 0x54u, 0xD5u, 0x88u, 0x03u, 0x38u, 0xEDu, 0xB2u,
+    0x45u, 0x54u, 0xD2u, 0x88u, 0x01u, 0x30u, 0xC2u, 0xF3u,
+    0x07u, 0x22u, 0x42u, 0x54u, 0x08u, 0x33u, 0x9Cu, 0xE7u,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
     0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,
-    0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,
-    0x85u, 0x60u, 0x00u, 0x40u, 0x0Au, 0x60u, 0x00u, 0x40u,
-    0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu,
-    0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u,
-    0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0xD4u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,
-    0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u,
-    0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu,
-    0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u,
-    0xA8u, 0x42u, 0x69u, 0xD0u, 0x13u, 0xF8u, 0x08u, 0x2Cu,
-    0x35u, 0x49u, 0x36u, 0x4Cu, 0x8Eu, 0x5Cu, 0xA4u, 0x5Cu,
-    0xA6u, 0x42u, 0x5Du, 0xD0u, 0x89u, 0x5Cu, 0x13u, 0xF8u,
-    0x07u, 0x4Cu, 0x8Cu, 0x42u, 0x58u, 0xD1u, 0x32u, 0x49u,
-    0x09u, 0x78u, 0x8Au, 0x42u, 0x54u, 0xD1u, 0x13u, 0xF8u,
-    0x06u, 0x7Cu, 0x07u, 0xF0u, 0x7Fu, 0x02u, 0x56u, 0x1Eu,
-    0x34u, 0x01u, 0xE1u, 0xB2u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
-    0x2Cu, 0x4Cu, 0x17u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,
-    0x0Cu, 0x07u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu,
-    0x02u, 0x44u, 0x06u, 0xD0u, 0x01u, 0x27u, 0x67u, 0x70u,
-    0xBEu, 0x42u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,
-    0x05u, 0xE0u, 0x00u, 0x27u, 0x67u, 0x70u, 0x01u, 0x2Eu,
-    0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x66u, 0x71u,
-    0x21u, 0x4Cu, 0x01u, 0x26u, 0x0Fu, 0x19u, 0x0Cu, 0x24u,
-    0x54u, 0x43u, 0x3Eu, 0x70u, 0x1Du, 0x4Eu, 0x33u, 0xF8u,
-    0x04u, 0x7Cu, 0x32u, 0x19u, 0x17u, 0x81u, 0x13u, 0xF8u,
-    0x06u, 0x7Cu, 0x17u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x7Cu,
-    0x37u, 0x55u, 0x00u, 0x26u, 0xD6u, 0x70u, 0x16u, 0x89u,
-    0x18u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,
-    0x26u, 0x70u, 0x16u, 0x89u, 0x16u, 0x4Cu, 0xF6u, 0xB2u,
-    0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u, 0x15u, 0x4Cu,
-    0xF6u, 0xB2u, 0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u,
-    0x13u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,
-    0x26u, 0x70u, 0xD6u, 0x88u, 0x11u, 0x4Cu, 0xF6u, 0xB2u,
-    0x0Cu, 0x19u, 0x26u, 0x70u, 0x10u, 0x4Cu, 0x0Cu, 0x19u,
-    0xD1u, 0x88u, 0xC1u, 0xF3u, 0x07u, 0x22u, 0x22u, 0x70u,
-    0x01u, 0x30u, 0xC0u, 0xB2u, 0x08u, 0x33u, 0x93u, 0xE7u,
-    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,
-    0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,
-    0x85u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x06u, 0x4Bu,
-    0x18u, 0x78u, 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u,
-    0x57u, 0xFFu, 0x42u, 0x68u, 0x13u, 0x79u, 0x00u, 0xEBu,
-    0xC3u, 0x00u, 0x40u, 0x69u, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0x00u, 0x21u,
-    0x0Cu, 0x24u, 0x4Cu, 0x43u, 0x51u, 0x4Du, 0x01u, 0x31u,
-    0x00u, 0x23u, 0x2Au, 0x19u, 0x09u, 0x29u, 0x2Bu, 0x55u,
-    0x93u, 0x70u, 0x02u, 0xF1u, 0x08u, 0x04u, 0x53u, 0x70u,
+    0x08u, 0xB5u, 0x06u, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,
+    0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x63u, 0xFFu, 0x20u, 0xB1u,
+    0x43u, 0x68u, 0x1Bu, 0x79u, 0x00u, 0xEBu, 0xC3u, 0x00u,
+    0x40u, 0x69u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0xF8u, 0xB5u, 0x00u, 0x21u, 0x0Cu, 0x25u, 0x4Du, 0x43u,
+    0x4Cu, 0x4Cu, 0x01u, 0x31u, 0x00u, 0x23u, 0x62u, 0x19u,
+    0x09u, 0x29u, 0x63u, 0x55u, 0x93u, 0x70u, 0x53u, 0x70u,
     0xD3u, 0x70u, 0x53u, 0x71u, 0x13u, 0x81u, 0x93u, 0x72u,
-    0xEEu, 0xD1u, 0x18u, 0xB1u, 0x4Au, 0x48u, 0x4Bu, 0x4Au,
-    0x03u, 0x70u, 0x13u, 0x70u, 0x4Au, 0x4Bu, 0x19u, 0x78u,
-    0x00u, 0x29u, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x1Cu, 0x78u,
-    0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x2Cu, 0xFFu,
-    0x42u, 0x68u, 0xD3u, 0x79u, 0x03u, 0xF0u, 0x40u, 0x01u,
-    0xCCu, 0xB2u, 0x44u, 0x4Bu, 0x1Cu, 0xB1u, 0x1Cu, 0x78u,
-    0x44u, 0xF0u, 0x01u, 0x01u, 0x02u, 0xE0u, 0x1Au, 0x78u,
-    0x02u, 0xF0u, 0xFEu, 0x01u, 0x04u, 0x7Au, 0x19u, 0x70u,
-    0x01u, 0x22u, 0xC3u, 0x68u, 0x00u, 0x21u, 0x08u, 0x33u,
-    0xA1u, 0x42u, 0x43u, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,
-    0x05u, 0xF0u, 0x7Fu, 0x06u, 0xB2u, 0x42u, 0x39u, 0xD1u,
-    0x34u, 0x4Eu, 0x0Cu, 0x27u, 0x07u, 0xFBu, 0x02u, 0x66u,
-    0xB6u, 0xF8u, 0x08u, 0xE0u, 0x33u, 0xF8u, 0x04u, 0x7Cu,
-    0x1Fu, 0xFAu, 0x8Eu, 0xFCu, 0xBCu, 0x45u, 0x38u, 0xBFu,
-    0x37u, 0x81u, 0x13u, 0xF8u, 0x08u, 0x6Cu, 0x2Eu, 0x4Fu,
-    0xBEu, 0x5Du, 0x13u, 0xF8u, 0x07u, 0x7Cu, 0xB7u, 0x42u,
-    0x24u, 0xD1u, 0x13u, 0xF8u, 0x05u, 0x6Cu, 0x15u, 0xF0u,
-    0x80u, 0x0Fu, 0x28u, 0x4Du, 0x4Fu, 0xF0u, 0x0Cu, 0x07u,
-    0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu, 0x02u, 0x55u,
-    0x06u, 0xD0u, 0x01u, 0x27u, 0x6Fu, 0x70u, 0xBEu, 0x42u,
-    0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u,
-    0x00u, 0x27u, 0x6Fu, 0x70u, 0x01u, 0x2Eu, 0x14u, 0xBFu,
-    0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u, 0x0Cu, 0x25u,
-    0x55u, 0x43u, 0x1Cu, 0x4Eu, 0x13u, 0xF8u, 0x06u, 0xECu,
-    0x77u, 0x19u, 0x87u, 0xF8u, 0x04u, 0xE0u, 0x13u, 0xF8u,
-    0x05u, 0x7Cu, 0x77u, 0x55u, 0x01u, 0x31u, 0xC9u, 0xB2u,
-    0x08u, 0x33u, 0xB9u, 0xE7u, 0x01u, 0x32u, 0x09u, 0x2Au,
-    0xB3u, 0xD1u, 0xC3u, 0x68u, 0x00u, 0x22u, 0x08u, 0x33u,
-    0xA2u, 0x42u, 0x0Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,
-    0x0Cu, 0x26u, 0x05u, 0xF0u, 0x7Fu, 0x01u, 0x0Fu, 0x4Du,
-    0x13u, 0xF8u, 0x08u, 0x0Cu, 0x06u, 0xFBu, 0x01u, 0x51u,
-    0x01u, 0x32u, 0x88u, 0x72u, 0xD2u, 0xB2u, 0xEEu, 0xE7u,
-    0xFFu, 0xF7u, 0x5Cu, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,
-    0x18u, 0x60u, 0x01u, 0x23u, 0x07u, 0x49u, 0x0Cu, 0x20u,
-    0x00u, 0xFBu, 0x03u, 0x10u, 0xC2u, 0x80u, 0x01u, 0x89u,
-    0x01u, 0x33u, 0x52u, 0x18u, 0x09u, 0x2Bu, 0x92u, 0xB2u,
-    0xF4u, 0xD1u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,
-    0x4Du, 0xBEu, 0xF8u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Fu, 0xC1u, 0xFFu, 0x1Fu,
-    0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x12u, 0x4Bu, 0x19u, 0x78u,
-    0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,
-    0x07u, 0x28u, 0x1Au, 0xD8u, 0x03u, 0x01u, 0xDAu, 0xB2u,
-    0x0Eu, 0x4Bu, 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x30u,
-    0x81u, 0x78u, 0x41u, 0xF0u, 0x01u, 0x03u, 0x00u, 0x21u,
-    0x83u, 0x70u, 0xC1u, 0x70u, 0x43u, 0x78u, 0x43u, 0xF0u,
-    0x02u, 0x01u, 0x41u, 0x70u, 0x00u, 0x79u, 0x08u, 0x4Bu,
-    0x10u, 0xF0u, 0x80u, 0x0Fu, 0x01u, 0xD0u, 0x8Du, 0x21u,
-    0x00u, 0xE0u, 0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u,
-    0x6Du, 0xBBu, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x1Au, 0x4Bu,
-    0x18u, 0x78u, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x5Au, 0x1Eu,
-    0xD2u, 0xB2u, 0x07u, 0x2Au, 0x2Au, 0xD8u, 0x17u, 0x49u,
-    0x0Cu, 0x20u, 0x00u, 0xFBu, 0x03u, 0x13u, 0x9Cu, 0x78u,
-    0x12u, 0x01u, 0x04u, 0xF0u, 0xFEu, 0x01u, 0x99u, 0x70u,
-    0x00u, 0x24u, 0x13u, 0x49u, 0xDCu, 0x70u, 0xD2u, 0xB2u,
-    0x54u, 0x5Cu, 0x04u, 0xF0u, 0x7Fu, 0x04u, 0x54u, 0x54u,
-    0x59u, 0x78u, 0x01u, 0xF0u, 0xFDu, 0x01u, 0x59u, 0x70u,
-    0x19u, 0x79u, 0x5Bu, 0x78u, 0x11u, 0xF0u, 0x80u, 0x0Fu,
-    0x0Cu, 0x49u, 0x05u, 0xD0u, 0x01u, 0x2Bu, 0x01u, 0xD1u,
-    0x50u, 0x54u, 0x07u, 0xE0u, 0x0Du, 0x20u, 0x04u, 0xE0u,
-    0x01u, 0x2Bu, 0x01u, 0xD1u, 0x08u, 0x20u, 0x00u, 0xE0u,
-    0x09u, 0x20u, 0x50u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u,
-    0xFFu, 0xF7u, 0x30u, 0xBBu, 0x00u, 0x20u, 0x10u, 0xBDu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,
-    0x10u, 0xB5u, 0x0Cu, 0x4Bu, 0x0Cu, 0x48u, 0x1Cu, 0x78u,
-    0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u, 0xFFu, 0xF7u,
-    0x27u, 0xFEu, 0x43u, 0x68u, 0x18u, 0x79u, 0xA0u, 0x42u,
-    0x09u, 0xD9u, 0x44u, 0xB9u, 0x07u, 0x4Bu, 0x08u, 0x4Au,
-    0x19u, 0x78u, 0x08u, 0x48u, 0x11u, 0x70u, 0x01u, 0x78u,
-    0x01u, 0x20u, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0x20u,
+    0xF0u, 0xD1u, 0x18u, 0xB1u, 0x46u, 0x4Au, 0x13u, 0x70u,
+    0x46u, 0x4Au, 0x13u, 0x70u, 0x46u, 0x4Bu, 0x1Au, 0x78u,
+    0x00u, 0x2Au, 0x00u, 0xF0u, 0x81u, 0x80u, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Au, 0xFFu,
+    0x43u, 0x68u, 0x01u, 0x7Au, 0xDBu, 0x79u, 0xC9u, 0x00u,
+    0x13u, 0xF0u, 0x40u, 0x0Fu, 0x3Fu, 0x4Bu, 0x1Au, 0x78u,
+    0x14u, 0xBFu, 0x42u, 0xF0u, 0x01u, 0x02u, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x1Au, 0x70u, 0x01u, 0x22u, 0xC3u, 0x68u,
+    0x08u, 0x33u, 0x03u, 0xEBu, 0x01u, 0x0Eu, 0x73u, 0x45u,
+    0x3Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu, 0x05u, 0xF0u,
+    0x7Fu, 0x06u, 0xB2u, 0x42u, 0x35u, 0xD1u, 0x0Cu, 0x26u,
+    0x06u, 0xFBu, 0x02u, 0x46u, 0xB6u, 0xF8u, 0x08u, 0xC0u,
+    0x33u, 0xF8u, 0x04u, 0x7Cu, 0x1Fu, 0xFAu, 0x8Cu, 0xFCu,
+    0xBCu, 0x45u, 0x38u, 0xBFu, 0x37u, 0x81u, 0x13u, 0xF8u,
+    0x08u, 0x6Cu, 0x2Bu, 0x4Fu, 0xBEu, 0x5Du, 0x13u, 0xF8u,
+    0x07u, 0x7Cu, 0xB7u, 0x42u, 0x21u, 0xD1u, 0x13u, 0xF8u,
+    0x05u, 0x6Cu, 0x15u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,
+    0x0Cu, 0x05u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x05u, 0xFBu,
+    0x02u, 0x45u, 0x06u, 0xD0u, 0x01u, 0x27u, 0xBEu, 0x42u,
+    0x6Fu, 0x70u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,
+    0x05u, 0xE0u, 0x00u, 0x27u, 0x01u, 0x2Eu, 0x6Fu, 0x70u,
+    0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u,
+    0x0Cu, 0x25u, 0x55u, 0x43u, 0x13u, 0xF8u, 0x06u, 0x7Cu,
+    0x66u, 0x19u, 0x37u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+    0x66u, 0x55u, 0x08u, 0x33u, 0xBFu, 0xE7u, 0x01u, 0x32u,
+    0x09u, 0x2Au, 0xB8u, 0xD1u, 0xC3u, 0x68u, 0x03u, 0xF1u,
+    0x08u, 0x02u, 0x11u, 0x44u, 0x08u, 0x33u, 0x8Bu, 0x42u,
+    0x0Au, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x2Cu, 0x0Cu, 0x25u,
+    0x02u, 0xF0u, 0x7Fu, 0x02u, 0x05u, 0xFBu, 0x02u, 0x42u,
+    0x13u, 0xF8u, 0x08u, 0x0Cu, 0x90u, 0x72u, 0xF1u, 0xE7u,
+    0xFFu, 0xF7u, 0x66u, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,
+    0x18u, 0x60u, 0x01u, 0x23u, 0x0Cu, 0x21u, 0x01u, 0xFBu,
+    0x03u, 0x41u, 0xCAu, 0x80u, 0x09u, 0x89u, 0x01u, 0x33u,
+    0x0Au, 0x44u, 0x09u, 0x2Bu, 0x92u, 0xB2u, 0xF5u, 0xD1u,
+    0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u, 0x7Eu, 0xBEu,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x67u, 0xC1u, 0xFFu, 0x1Fu,
+    0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x11u, 0x4Bu, 0x19u, 0x78u,
+    0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD2u, 0xB2u,
+    0x07u, 0x2Au, 0x19u, 0xD8u, 0x0Eu, 0x4Bu, 0x0Cu, 0x20u,
+    0x00u, 0xFBu, 0x01u, 0x33u, 0x99u, 0x78u, 0x12u, 0x01u,
+    0x41u, 0xF0u, 0x01u, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u,
+    0xD9u, 0x70u, 0x59u, 0x78u, 0xD2u, 0xB2u, 0x41u, 0xF0u,
+    0x02u, 0x01u, 0x59u, 0x70u, 0x1Bu, 0x79u, 0x13u, 0xF0u,
+    0x80u, 0x0Fu, 0x06u, 0x4Bu, 0x14u, 0xBFu, 0x8Du, 0x21u,
+    0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u, 0x98u, 0xBBu,
+    0x00u, 0x20u, 0x70u, 0x47u, 0x04u, 0x60u, 0x00u, 0x40u,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Eu, 0x60u, 0x00u, 0x40u,
+    0x10u, 0xB5u, 0x1Au, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+    0x7Fu, 0x03u, 0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0x07u, 0x2Au,
+    0x29u, 0xD8u, 0x17u, 0x49u, 0x0Cu, 0x20u, 0x00u, 0xFBu,
+    0x03u, 0x13u, 0x99u, 0x78u, 0x12u, 0x01u, 0x01u, 0xF0u,
+    0xFEu, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u, 0xD9u, 0x70u,
+    0x12u, 0x49u, 0xD2u, 0xB2u, 0x54u, 0x5Cu, 0x04u, 0xF0u,
+    0x7Fu, 0x04u, 0x54u, 0x54u, 0x59u, 0x78u, 0x01u, 0xF0u,
+    0xFDu, 0x01u, 0x59u, 0x70u, 0x19u, 0x79u, 0x5Bu, 0x78u,
+    0x11u, 0xF0u, 0x80u, 0x0Fu, 0x0Cu, 0x49u, 0x05u, 0xD0u,
+    0x01u, 0x2Bu, 0x01u, 0xD1u, 0x50u, 0x54u, 0x06u, 0xE0u,
+    0x0Du, 0x23u, 0x03u, 0xE0u, 0x01u, 0x2Bu, 0x0Cu, 0xBFu,
+    0x08u, 0x23u, 0x09u, 0x23u, 0x53u, 0x54u, 0xBDu, 0xE8u,
+    0x10u, 0x40u, 0xFFu, 0xF7u, 0x5Du, 0xBBu, 0x00u, 0x20u,
     0x10u, 0xBDu, 0x00u, 0xBFu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,
-    0x10u, 0xB5u, 0x7Cu, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x80u,
-    0x7Bu, 0x4Au, 0x7Cu, 0x48u, 0x11u, 0x78u, 0x11u, 0xF0u,
-    0x80u, 0x0Fu, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x01u, 0x78u,
-    0x0Au, 0x29u, 0x00u, 0xF2u, 0x22u, 0x81u, 0xDFu, 0xE8u,
-    0x11u, 0xF0u, 0x58u, 0x00u, 0x20u, 0x01u, 0x20u, 0x01u,
-    0x20u, 0x01u, 0x20u, 0x01u, 0x20u, 0x01u, 0x0Bu, 0x00u,
-    0x20u, 0x01u, 0x78u, 0x00u, 0x20u, 0x01u, 0x7Cu, 0x00u,
-    0x71u, 0x4Bu, 0x19u, 0x78u, 0x01u, 0x29u, 0x0Au, 0xD1u,
-    0x70u, 0x48u, 0x71u, 0x49u, 0x02u, 0x78u, 0x01u, 0xEBu,
-    0xC2u, 0x03u, 0x58u, 0x68u, 0x12u, 0x23u, 0x42u, 0x68u,
-    0x68u, 0x48u, 0x42u, 0x60u, 0x0Fu, 0xE0u, 0x18u, 0x78u,
-    0x02u, 0x28u, 0x11u, 0xD1u, 0x6Bu, 0x4Bu, 0x18u, 0x78u,
-    0xFFu, 0xF7u, 0xDAu, 0xFDu, 0x42u, 0x68u, 0x63u, 0x48u,
-    0x42u, 0x60u, 0x41u, 0x68u, 0xCBu, 0x78u, 0x42u, 0x68u,
-    0x91u, 0x78u, 0x41u, 0xEAu, 0x03u, 0x23u, 0x03u, 0x80u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x0Cu, 0xBCu,
-    0x1Au, 0x78u, 0x03u, 0x2Au, 0x21u, 0xD1u, 0x62u, 0x4Bu,
-    0x00u, 0x22u, 0x60u, 0x49u, 0x08u, 0x78u, 0x90u, 0x42u,
-    0x0Au, 0xD8u, 0x0Au, 0x78u, 0x82u, 0xB1u, 0x5Du, 0x49u,
-    0x5Eu, 0x48u, 0x09u, 0x78u, 0x5Eu, 0x4Au, 0x00u, 0x7Cu,
-    0x88u, 0x42u, 0x08u, 0xBFu, 0x13u, 0x46u, 0x07u, 0xE0u,
-    0x18u, 0x78u, 0x00u, 0x28u, 0xF1u, 0xD0u, 0x19u, 0x78u,
-    0x50u, 0x1Cu, 0x5Bu, 0x18u, 0xC2u, 0xB2u, 0xE8u, 0xE7u,
-    0x19u, 0x78u, 0x00u, 0x29u, 0x00u, 0xF0u, 0xD1u, 0x80u,
-    0x18u, 0x78u, 0x4Cu, 0x4Au, 0x10u, 0x80u, 0x53u, 0x60u,
-    0xD6u, 0xE7u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0x00u, 0xF0u,
-    0xDDu, 0xB8u, 0x11u, 0x78u, 0x11u, 0xF0u, 0x03u, 0x02u,
-    0x11u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xC1u, 0x80u,
-    0x44u, 0x49u, 0x4Eu, 0x4Bu, 0x0Au, 0x80u, 0x18u, 0x78u,
-    0x4Du, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x20u,
-    0x00u, 0xFBu, 0x03u, 0x23u, 0x98u, 0x78u, 0x4Bu, 0x4Bu,
-    0x00u, 0x22u, 0x18u, 0x70u, 0x06u, 0xE0u, 0x3Du, 0x49u,
-    0x02u, 0x23u, 0x49u, 0x48u, 0x0Bu, 0x80u, 0x00u, 0x78u,
-    0x46u, 0x4Bu, 0x18u, 0x70u, 0x5Au, 0x70u, 0x4Bu, 0x60u,
-    0xB2u, 0xE7u, 0x01u, 0x22u, 0x1Au, 0x80u, 0x45u, 0x48u,
-    0x05u, 0xE0u, 0x01u, 0x22u, 0x3Fu, 0x48u, 0x1Au, 0x80u,
-    0x02u, 0x78u, 0x43u, 0x49u, 0x88u, 0x18u, 0x58u, 0x60u,
-    0xA6u, 0xE7u, 0x03u, 0x78u, 0x58u, 0x1Eu, 0x0Au, 0x28u,
-    0x00u, 0xF2u, 0x97u, 0x80u, 0xDFu, 0xE8u, 0x10u, 0xF0u,
-    0x2Bu, 0x00u, 0x95u, 0x00u, 0x44u, 0x00u, 0x95u, 0x00u,
-    0x0Bu, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u,
-    0x0Fu, 0x00u, 0x95u, 0x00u, 0x19u, 0x00u, 0x2Fu, 0x4Bu,
-    0x38u, 0x49u, 0x18u, 0x78u, 0x4Cu, 0xE0u, 0x2Du, 0x4Bu,
-    0x34u, 0x4Au, 0x18u, 0x78u, 0x36u, 0x49u, 0x10u, 0x70u,
-    0x01u, 0x20u, 0x08u, 0x70u, 0xFFu, 0xF7u, 0x0Au, 0xFEu,
-    0x77u, 0xE0u, 0xFFu, 0xF7u, 0x25u, 0xFFu, 0x00u, 0x28u,
-    0x77u, 0xD0u, 0x2Au, 0x4Cu, 0x31u, 0x4Au, 0x24u, 0x78u,
-    0x2Fu, 0x4Bu, 0x01u, 0x21u, 0x14u, 0x70u, 0x19u, 0x70u,
-    0xFFu, 0xF7u, 0x58u, 0xFDu, 0x2Au, 0x48u, 0x2Eu, 0x49u,
-    0x02u, 0x5Du, 0x0Au, 0x55u, 0x65u, 0xE0u, 0x12u, 0x78u,
-    0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x55u, 0xD0u,
-    0x09u, 0xD3u, 0x02u, 0x29u, 0x61u, 0xD1u, 0x1Bu, 0x4Bu,
-    0x18u, 0x78u, 0x00u, 0x28u, 0x5Du, 0xD1u, 0xBDu, 0xE8u,
-    0x10u, 0x40u, 0xFFu, 0xF7u, 0xC7u, 0xBEu, 0x17u, 0x4Au,
-    0x11u, 0x78u, 0x01u, 0x29u, 0x55u, 0xD1u, 0x1Cu, 0x49u,
-    0x0Bu, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x00u, 0x17u, 0xE0u,
-    0x10u, 0x78u, 0x00u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au,
-    0x3Cu, 0xD0u, 0x09u, 0xD3u, 0x02u, 0x2Au, 0x48u, 0xD1u,
-    0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x00u, 0x2Bu, 0x44u, 0xD1u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x82u, 0xBEu,
-    0x0Au, 0x48u, 0x02u, 0x78u, 0x01u, 0x2Au, 0x3Cu, 0xD1u,
-    0x0Fu, 0x49u, 0x0Bu, 0x78u, 0x43u, 0xF0u, 0x02u, 0x00u,
-    0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x60u, 0x00u, 0x40u,
+    0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x0Du, 0x4Bu,
+    0x1Cu, 0x78u, 0x0Du, 0x4Bu, 0xE4u, 0xB2u, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Eu, 0xFEu,
+    0x43u, 0x68u, 0x1Bu, 0x79u, 0xA3u, 0x42u, 0x0Bu, 0xD9u,
+    0x54u, 0xB9u, 0x08u, 0x4Bu, 0x08u, 0x4Au, 0x19u, 0x78u,
+    0x01u, 0x20u, 0xC9u, 0xB2u, 0x11u, 0x70u, 0x07u, 0x4Au,
+    0x12u, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x10u, 0xBDu,
+    0x00u, 0x20u, 0x10u, 0xBDu, 0x04u, 0x60u, 0x00u, 0x40u,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,
+    0x38u, 0xB5u, 0x8Cu, 0x4Cu, 0x00u, 0x23u, 0x23u, 0x80u,
+    0x8Bu, 0x4Bu, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x80u, 0x0Fu,
+    0x8Au, 0x4Au, 0x12u, 0x78u, 0x00u, 0xF0u, 0x88u, 0x80u,
+    0x0Au, 0x2Au, 0x00u, 0xF2u, 0x08u, 0x81u, 0xDFu, 0xE8u,
+    0x12u, 0xF0u, 0x58u, 0x00u, 0x06u, 0x01u, 0x06u, 0x01u,
+    0x06u, 0x01u, 0x06u, 0x01u, 0x06u, 0x01u, 0x0Bu, 0x00u,
+    0x06u, 0x01u, 0x78u, 0x00u, 0x06u, 0x01u, 0x7Cu, 0x00u,
+    0x81u, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x2Au, 0x09u, 0xD1u,
+    0x80u, 0x4Bu, 0x1Au, 0x78u, 0x80u, 0x4Bu, 0x03u, 0xEBu,
+    0xC2u, 0x03u, 0x5Bu, 0x68u, 0x5Bu, 0x68u, 0x63u, 0x60u,
+    0x12u, 0x23u, 0x11u, 0xE0u, 0x1Au, 0x78u, 0x02u, 0x2Au,
+    0x13u, 0xD1u, 0x7Cu, 0x4Bu, 0x18u, 0x78u, 0xFFu, 0xF7u,
+    0xF1u, 0xFDu, 0x00u, 0x28u, 0x00u, 0xF0u, 0xE3u, 0x80u,
+    0x43u, 0x68u, 0x63u, 0x60u, 0x63u, 0x68u, 0xDAu, 0x78u,
+    0x63u, 0x68u, 0x9Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x23u,
+    0x23u, 0x80u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,
+    0x0Bu, 0xBCu, 0x1Bu, 0x78u, 0x03u, 0x2Bu, 0x20u, 0xD1u,
+    0x71u, 0x4Bu, 0x00u, 0x22u, 0x6Fu, 0x49u, 0xD0u, 0xB2u,
+    0x0Du, 0x78u, 0x85u, 0x42u, 0x0Au, 0xD8u, 0x0Au, 0x78u,
+    0x7Au, 0xB1u, 0x6Cu, 0x4Au, 0x6Du, 0x48u, 0x11u, 0x78u,
+    0x00u, 0x7Cu, 0x6Du, 0x4Au, 0x88u, 0x42u, 0x08u, 0xBFu,
+    0x13u, 0x46u, 0x06u, 0xE0u, 0x18u, 0x78u, 0x01u, 0x32u,
+    0x00u, 0x28u, 0xF0u, 0xD0u, 0x19u, 0x78u, 0x0Bu, 0x44u,
+    0xE8u, 0xE7u, 0x1Au, 0x78u, 0x00u, 0x2Au, 0x00u, 0xF0u,
+    0xB6u, 0x80u, 0x1Au, 0x78u, 0xD2u, 0xB2u, 0x22u, 0x80u,
+    0x19u, 0xE0u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0x00u, 0xF0u,
+    0xE7u, 0xB8u, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x03u, 0x02u,
+    0x13u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xA7u, 0x80u,
+    0x5Eu, 0x4Bu, 0x22u, 0x80u, 0x1Bu, 0x78u, 0x5Eu, 0x4Au,
+    0x03u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x21u, 0x01u, 0xFBu,
+    0x03u, 0x23u, 0x9Au, 0x78u, 0x5Bu, 0x4Bu, 0xD2u, 0xB2u,
+    0x1Au, 0x70u, 0x00u, 0x22u, 0x5Au, 0x70u, 0x63u, 0x60u,
+    0xBBu, 0xE7u, 0x02u, 0x23u, 0x23u, 0x80u, 0x58u, 0x4Bu,
+    0x19u, 0x78u, 0x56u, 0x4Bu, 0xC9u, 0xB2u, 0x19u, 0x70u,
+    0xF4u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x55u, 0x4Bu,
+    0xF1u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x4Fu, 0x4Bu,
+    0x53u, 0x4Au, 0x1Bu, 0x78u, 0x13u, 0x44u, 0xEAu, 0xE7u,
+    0x01u, 0x3Au, 0x0Au, 0x2Au, 0x7Fu, 0xD8u, 0xDFu, 0xE8u,
+    0x02u, 0xF0u, 0x36u, 0x7Eu, 0x52u, 0x7Eu, 0x06u, 0x7Eu,
+    0x7Eu, 0x7Eu, 0x0Bu, 0x7Eu, 0x22u, 0x00u, 0x43u, 0x4Bu,
+    0x1Au, 0x78u, 0x4Cu, 0x4Bu, 0xD2u, 0xB2u, 0x60u, 0xE0u,
+    0x40u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0xFFu, 0x04u,
+    0x53u, 0xB9u, 0x46u, 0x4Bu, 0x1Au, 0x78u, 0x94u, 0x42u,
+    0x65u, 0xD0u, 0x1Cu, 0x70u, 0x46u, 0x4Bu, 0x01u, 0x20u,
+    0x18u, 0x70u, 0xFFu, 0xF7u, 0x15u, 0xFEu, 0x5Eu, 0xE0u,
+    0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x6Au, 0xFDu,
+    0x00u, 0x28u, 0xEEu, 0xD1u, 0x5Bu, 0xE0u, 0xFFu, 0xF7u,
+    0x1Du, 0xFFu, 0x00u, 0x28u, 0x57u, 0xD0u, 0x37u, 0x4Bu,
+    0x01u, 0x22u, 0x1Cu, 0x78u, 0x3Du, 0x4Bu, 0xE4u, 0xB2u,
+    0x1Cu, 0x70u, 0x3Bu, 0x4Bu, 0x1Au, 0x70u, 0xFFu, 0xF7u,
+    0x6Du, 0xFDu, 0x37u, 0x4Bu, 0x1Au, 0x5Du, 0x3Au, 0x4Bu,
+    0xD2u, 0xB2u, 0x1Au, 0x55u, 0x43u, 0xE0u, 0x1Bu, 0x78u,
+    0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x32u, 0xD0u,
+    0x0Cu, 0xD3u, 0x02u, 0x2Bu, 0x3Fu, 0xD1u, 0x03u, 0xF1u,
+    0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,
+    0x00u, 0x2Bu, 0x38u, 0xD1u, 0xBDu, 0xE8u, 0x38u, 0x40u,
+    0xFFu, 0xF7u, 0xBAu, 0xBEu, 0x21u, 0x4Bu, 0x1Bu, 0x78u,
+    0x01u, 0x2Bu, 0x30u, 0xD1u, 0x26u, 0x4Bu, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xFDu, 0x02u, 0x19u, 0xE0u, 0x1Bu, 0x78u,
+    0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x16u, 0xD0u,
+    0x0Bu, 0xD3u, 0x02u, 0x2Bu, 0x23u, 0xD1u, 0x03u, 0xF1u,
+    0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,
+    0xEBu, 0xB9u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,
+    0x75u, 0xBEu, 0x14u, 0x4Bu, 0x1Bu, 0x78u, 0x01u, 0x2Bu,
+    0x15u, 0xD1u, 0x19u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,
+    0x02u, 0x02u, 0x1Au, 0x70u, 0x0Bu, 0xE0u, 0x13u, 0x4Bu,
+    0x1Au, 0x78u, 0x62u, 0xB9u, 0x1Bu, 0x78u, 0x1Bu, 0x4Au,
+    0x0Cu, 0x48u, 0xDBu, 0xB2u, 0xD1u, 0x5Cu, 0x00u, 0x78u,
+    0x21u, 0xEAu, 0x00u, 0x01u, 0xD1u, 0x54u, 0xBDu, 0xE8u,
+    0x38u, 0x40u, 0xFFu, 0xF7u, 0x15u, 0xBAu, 0x00u, 0x20u,
+    0x38u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
     0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
-    0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0xD4u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
-    0x9Au, 0x21u, 0x00u, 0x00u, 0x16u, 0x22u, 0x00u, 0x00u,
-    0x90u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
-    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x48u, 0x02u, 0x78u,
-    0x5Au, 0xB9u, 0x03u, 0x78u, 0x07u, 0x4Au, 0x08u, 0x48u,
-    0xD1u, 0x5Cu, 0x00u, 0x78u, 0x21u, 0xEAu, 0x00u, 0x01u,
-    0xD1u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
-    0xD1u, 0xB9u, 0x00u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x73u, 0xC1u, 0xFFu, 0x1Fu,
-    0x02u, 0x60u, 0x00u, 0x40u, 0x03u, 0x4Bu, 0x18u, 0x78u,
-    0x01u, 0x06u, 0x44u, 0xBFu, 0x02u, 0x49u, 0x09u, 0x78u,
-    0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x01u, 0x60u, 0x00u, 0x40u, 0x0Fu, 0x4Bu, 0x18u, 0x78u,
-    0x00u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x0Cu, 0xD0u,
-    0x02u, 0x29u, 0x0Du, 0xD1u, 0x0Cu, 0x4Au, 0x0Cu, 0x21u,
-    0x10u, 0x78u, 0x0Cu, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u,
-    0x01u, 0xFBu, 0x03u, 0x20u, 0x08u, 0x30u, 0x83u, 0x78u,
-    0x03u, 0xE0u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x00u, 0xE0u,
-    0x00u, 0x23u, 0x07u, 0x49u, 0x0Au, 0x68u, 0xD0u, 0x5Cu,
-    0x03u, 0x28u, 0x01u, 0xD1u, 0xFFu, 0xF7u, 0xC6u, 0xBBu,
-    0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x38u, 0xB5u, 0x0Eu, 0x4Du,
-    0x0Eu, 0x4Bu, 0x00u, 0x24u, 0xE8u, 0x1Au, 0x85u, 0x10u,
-    0xACu, 0x42u, 0x05u, 0xD0u, 0x0Bu, 0x49u, 0x51u, 0xF8u,
-    0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u,
-    0x00u, 0xF0u, 0x3Au, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au,
-    0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u,
-    0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u,
-    0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu,
-    0x34u, 0x22u, 0x00u, 0x00u, 0x34u, 0x22u, 0x00u, 0x00u,
-    0x34u, 0x22u, 0x00u, 0x00u, 0x3Cu, 0x22u, 0x00u, 0x00u,
+    0x03u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+    0x8Cu, 0x21u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
+    0x52u, 0x22u, 0x00u, 0x00u, 0xCEu, 0x22u, 0x00u, 0x00u,
+    0x48u, 0x22u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x4Eu, 0xC1u, 0xFFu, 0x1Fu,
+    0x67u, 0xC1u, 0xFFu, 0x1Fu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x56u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+    0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x6Bu, 0xC1u, 0xFFu, 0x1Fu,
+    0x03u, 0x4Bu, 0x00u, 0x20u, 0x1Bu, 0x78u, 0x1Bu, 0x06u,
+    0x44u, 0xBFu, 0x02u, 0x4Bu, 0x1Bu, 0x78u, 0x70u, 0x47u,
+    0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
+    0x10u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0x03u, 0x03u,
+    0x01u, 0x2Bu, 0x0Cu, 0xD0u, 0x02u, 0x2Bu, 0x0Eu, 0xD1u,
+    0x0Du, 0x4Bu, 0x0Eu, 0x4Au, 0x1Bu, 0x78u, 0x0Cu, 0x21u,
+    0x03u, 0xF0u, 0x7Fu, 0x03u, 0x01u, 0xFBu, 0x03u, 0x23u,
+    0x08u, 0x33u, 0x9Bu, 0x78u, 0x01u, 0xE0u, 0x08u, 0x4Bu,
+    0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xE0u, 0x00u, 0x23u,
+    0x07u, 0x4Au, 0x12u, 0x68u, 0xD3u, 0x5Cu, 0x03u, 0x2Bu,
+    0x01u, 0xD1u, 0xFFu, 0xF7u, 0xE7u, 0xBBu, 0x00u, 0x20u,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x00u, 0x60u, 0x00u, 0x40u,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x70u, 0xB5u, 0x0Eu, 0x4Bu,
+    0x0Eu, 0x4Du, 0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u,
+    0x1Eu, 0x46u, 0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u,
+    0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u,
+    0x00u, 0xF0u, 0x3Au, 0xF9u, 0x08u, 0x4Du, 0x09u, 0x4Bu,
+    0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u, 0x1Eu, 0x46u,
+    0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u, 0x24u, 0x20u,
+    0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u, 0x70u, 0xBDu,
+    0xECu, 0x22u, 0x00u, 0x00u, 0xECu, 0x22u, 0x00u, 0x00u,
+    0xF4u, 0x22u, 0x00u, 0x00u, 0xECu, 0x22u, 0x00u, 0x00u,
     0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u,
     0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u,
-    0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,
+    0x10u, 0xBDu, 0x02u, 0x44u, 0x03u, 0x46u, 0x93u, 0x42u,
     0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
-    0x70u, 0x47u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,
-    0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x70u, 0x47u, 0x00u, 0x00u, 0x38u, 0x23u, 0x00u, 0x00u,
+    0xF2u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x10u, 0x51u, 0x00u, 0x40u, 0x20u, 0x00u, 0x50u, 0x51u,
     0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x00u, 0x40u,
     0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x10u,
@@ -1078,25 +1101,25 @@ const uint8 cy_bootloader[] = {
     0x00u, 0x00u, 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x69u, 0x30u, 0x13u, 0x2Eu,
-    0x00u, 0x14u, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0xDCu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0x16u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0xECu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0xEDu, 0x21u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u,
-    0x0Eu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0x20u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x0Cu, 0x21u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x1Eu, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u,
+    0x94u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xCEu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xA4u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xA5u, 0x22u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u,
+    0xC6u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xD8u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xC4u, 0x21u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,
     0x01u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,
     0x82u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x28u, 0x21u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x21u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x21u, 0x00u, 0x00u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xE0u, 0x21u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x14u, 0x22u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x22u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x68u, 0x21u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x21u, 0x00u, 0x00u,
-    0x41u, 0x00u, 0x00u, 0x00u, 0x33u, 0xC2u, 0xFFu, 0x1Fu,
-    0x74u, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u,
-    0xF2u, 0xC1u, 0xFFu, 0x1Fu, 0xEEu, 0xC1u, 0xFFu, 0x1Fu,
+    0x01u, 0x00u, 0x00u, 0x00u, 0x20u, 0x22u, 0x00u, 0x00u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xB7u, 0x22u, 0x00u, 0x00u,
+    0x41u, 0x00u, 0x00u, 0x00u, 0x2Bu, 0xC2u, 0xFFu, 0x1Fu,
+    0x6Cu, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u,
+    0xEAu, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
     0x24u, 0x00u, 0x05u, 0x01u, 0x09u, 0x00u, 0xA1u, 0x00u,
     0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0x15u, 0x00u,
     0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x91u, 0x02u,
@@ -1123,13 +1146,13 @@ const uint8 cy_bootloader[] = {
     0x1Du, 0xB7u, 0x01u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u,
     0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,
     0x9Eu, 0x46u, 0x70u, 0x47u, 0x51u, 0x00u, 0x00u, 0x00u,
-    0xB9u, 0x01u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu,
+    0xB5u, 0x01u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu,
     0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u,
-    0x2Du, 0x00u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u,
+    0x2Du, 0x00u, 0x00u, 0x00u, 0x18u, 0x23u, 0x00u, 0x00u,
     0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x20u, 0x00u, 0x00u, 0x00u,
-    0x50u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x20u, 0x00u, 0x00u,
-    0x08u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
+    0x48u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xBCu, 0x20u, 0x00u, 0x00u,
+    0xC0u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
     0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
@@ -1147,6 +1170,15 @@ const uint8 cy_bootloader[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
 
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
@@ -1158,7 +1190,7 @@ __attribute__ ((__section__(".cymeta"), used))
 #endif
 const uint8 cy_metadata[] = {
     0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,
-    0x2Eu, 0x1Fu, 0x8Cu, 0x6Bu};
+    0x2Eu, 0x20u, 0x2Bu, 0x6Bu};
 
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
 __attribute__ ((__section__(".cycustnvl"), used))
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf
old mode 100755
new mode 100644
index 7d8b8c27..6eded1c3
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf
@@ -1,3 +1,3 @@
 /* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */
 
-define symbol CYDEV_BTLDR_SIZE = 0x00002300;
+define symbol CYDEV_BTLDR_SIZE = 0x00002400;
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
old mode 100755
new mode 100644
index 5f1b198d..d5394a10
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
old mode 100755
new mode 100644
index e2c0687f..023cea0d
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
old mode 100755
new mode 100644
index 1776ef90..b5460484
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
old mode 100755
new mode 100644
index 3c24869c..dfe5fca5
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
old mode 100755
new mode 100644
index e4f1a443..8c2cb7d6
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
old mode 100755
new mode 100644
index ebd1b1dc..6481aaf0
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
old mode 100755
new mode 100644
index 4ed74edd..189d0303
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
old mode 100755
new mode 100644
index d4d800c6..7c853db5
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index d9cdcac0..a110bfa0 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -3,83 +3,110 @@
 #include <cydevice.h>
 #include <cydevice_trm.h>
 
-/* Debug_Timer_Interrupt */
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+/* LED1 */
+#define LED1__0__MASK 0x08u
+#define LED1__0__PC CYREG_PRT12_PC3
+#define LED1__0__PORT 12u
+#define LED1__0__SHIFT 3
+#define LED1__AG CYREG_PRT12_AG
+#define LED1__BIE CYREG_PRT12_BIE
+#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK
+#define LED1__BYP CYREG_PRT12_BYP
+#define LED1__DM0 CYREG_PRT12_DM0
+#define LED1__DM1 CYREG_PRT12_DM1
+#define LED1__DM2 CYREG_PRT12_DM2
+#define LED1__DR CYREG_PRT12_DR
+#define LED1__INP_DIS CYREG_PRT12_INP_DIS
+#define LED1__MASK 0x08u
+#define LED1__PORT 12u
+#define LED1__PRT CYREG_PRT12_PRT
+#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define LED1__PS CYREG_PRT12_PS
+#define LED1__SHIFT 3
+#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG
+#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define LED1__SLW CYREG_PRT12_SLW
 
-/* SD_RX_DMA_COMPLETE */
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SD_CD */
+#define SD_CD__0__MASK 0x40u
+#define SD_CD__0__PC CYREG_PRT3_PC6
+#define SD_CD__0__PORT 3u
+#define SD_CD__0__SHIFT 6
+#define SD_CD__AG CYREG_PRT3_AG
+#define SD_CD__AMUX CYREG_PRT3_AMUX
+#define SD_CD__BIE CYREG_PRT3_BIE
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CD__BYP CYREG_PRT3_BYP
+#define SD_CD__CTL CYREG_PRT3_CTL
+#define SD_CD__DM0 CYREG_PRT3_DM0
+#define SD_CD__DM1 CYREG_PRT3_DM1
+#define SD_CD__DM2 CYREG_PRT3_DM2
+#define SD_CD__DR CYREG_PRT3_DR
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CD__MASK 0x40u
+#define SD_CD__PORT 3u
+#define SD_CD__PRT CYREG_PRT3_PRT
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CD__PS CYREG_PRT3_PS
+#define SD_CD__SHIFT 6
+#define SD_CD__SLW CYREG_PRT3_SLW
 
-/* SD_TX_DMA_COMPLETE */
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SD_CS */
+#define SD_CS__0__MASK 0x10u
+#define SD_CS__0__PC CYREG_PRT3_PC4
+#define SD_CS__0__PORT 3u
+#define SD_CS__0__SHIFT 4
+#define SD_CS__AG CYREG_PRT3_AG
+#define SD_CS__AMUX CYREG_PRT3_AMUX
+#define SD_CS__BIE CYREG_PRT3_BIE
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CS__BYP CYREG_PRT3_BYP
+#define SD_CS__CTL CYREG_PRT3_CTL
+#define SD_CS__DM0 CYREG_PRT3_DM0
+#define SD_CS__DM1 CYREG_PRT3_DM1
+#define SD_CS__DM2 CYREG_PRT3_DM2
+#define SD_CS__DR CYREG_PRT3_DR
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CS__MASK 0x10u
+#define SD_CS__PORT 3u
+#define SD_CS__PRT CYREG_PRT3_PRT
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CS__PS CYREG_PRT3_PS
+#define SD_CS__SHIFT 4
+#define SD_CS__SLW CYREG_PRT3_SLW
 
-/* SCSI_Parity_Error */
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST
+/* USBFS_arb_int */
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_arb_int__INTC_MASK 0x400000u
+#define USBFS_arb_int__INTC_NUMBER 22u
+#define USBFS_arb_int__INTC_PRIOR_NUM 7u
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* USBFS_bus_reset */
 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -91,99 +118,131 @@
 #define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_PHASE */
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
-
-/* SCSI_Filtered */
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Filtered_sts_sts_reg__0__POS 0
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
-#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
-#define SCSI_Filtered_sts_sts_reg__2__POS 2
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
-#define SCSI_Filtered_sts_sts_reg__3__POS 3
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
-#define SCSI_Filtered_sts_sts_reg__4__POS 4
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB14_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB14_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB14_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB14_ST
-
-/* SCSI_Out_Bits */
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-
-/* USBFS_arb_int */
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_arb_int__INTC_MASK 0x400000u
-#define USBFS_arb_int__INTC_NUMBER 22u
-#define USBFS_arb_int__INTC_PRIOR_NUM 7u
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* USBFS_Dm */
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x40u
+#define USBFS_ep_1__INTC_NUMBER 6u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x80u
+#define USBFS_ep_2__INTC_NUMBER 7u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_3__INTC_MASK 0x100u
+#define USBFS_ep_3__INTC_NUMBER 8u
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_4__INTC_MASK 0x200u
+#define USBFS_ep_4__INTC_NUMBER 9u
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 #define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -195,2186 +254,236 @@
 #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_Ctl */
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+/* USBFS_USB */
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
+#define USBFS_USB__CR0 CYREG_USB_CR0
+#define USBFS_USB__CR1 CYREG_USB_CR1
+#define USBFS_USB__CWA CYREG_USB_CWA
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
+#define USBFS_USB__PM_ACT_MSK 0x01u
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
+#define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
+#define USBFS_USB__SOF0 CYREG_USB_SOF0
+#define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
 
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x08u
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3
-#define SCSI_Out_DBx__0__PORT 6u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__0__SHIFT 3
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x04u
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2
-#define SCSI_Out_DBx__1__PORT 6u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__1__SHIFT 2
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__2__MASK 0x02u
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1
-#define SCSI_Out_DBx__2__PORT 6u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__2__SHIFT 1
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x01u
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0
-#define SCSI_Out_DBx__3__PORT 6u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__3__SHIFT 0
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x80u
-#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7
-#define SCSI_Out_DBx__4__PORT 4u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__4__SHIFT 7
-#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x40u
-#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6
-#define SCSI_Out_DBx__5__PORT 4u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__5__SHIFT 6
-#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x20u
-#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5
-#define SCSI_Out_DBx__6__PORT 4u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__6__SHIFT 5
-#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x10u
-#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4
-#define SCSI_Out_DBx__7__PORT 4u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__7__SHIFT 4
-#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x08u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3
-#define SCSI_Out_DBx__DB0__PORT 6u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB0__SHIFT 3
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x04u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2
-#define SCSI_Out_DBx__DB1__PORT 6u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB1__SHIFT 2
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB2__MASK 0x02u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1
-#define SCSI_Out_DBx__DB2__PORT 6u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB2__SHIFT 1
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x01u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0
-#define SCSI_Out_DBx__DB3__PORT 6u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB3__SHIFT 0
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x80u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7
-#define SCSI_Out_DBx__DB4__PORT 4u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB4__SHIFT 7
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x40u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6
-#define SCSI_Out_DBx__DB5__PORT 4u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB5__SHIFT 6
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x20u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5
-#define SCSI_Out_DBx__DB6__PORT 4u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB6__SHIFT 5
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x10u
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4
-#define SCSI_Out_DBx__DB7__PORT 4u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB7__SHIFT 4
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW
-
-/* SCSI_RST_ISR */
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x04u
-#define SCSI_RST_ISR__INTC_NUMBER 2u
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_RxStsReg__4__POS 4
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
-#define SDCard_BSPIM_RxStsReg__5__POS 5
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
-#define SDCard_BSPIM_RxStsReg__6__POS 6
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
-#define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
-#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
-#define SDCard_BSPIM_TxStsReg__2__POS 2
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
-#define SDCard_BSPIM_TxStsReg__3__POS 3
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_TxStsReg__4__POS 4
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-#define SCSI_In_DBx__0__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__0__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__0__MASK 0x10u
-#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__0__PORT 12u
-#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__0__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__0__SHIFT 4
-#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__1__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__1__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__1__MASK 0x80u
-#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7
-#define SCSI_In_DBx__1__PORT 2u
-#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__1__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__1__SHIFT 7
-#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__2__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__2__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__2__MASK 0x40u
-#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6
-#define SCSI_In_DBx__2__PORT 2u
-#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__2__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__2__SHIFT 6
-#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__3__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__3__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__3__MASK 0x20u
-#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__3__PORT 2u
-#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__3__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__3__SHIFT 5
-#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__4__MASK 0x10u
-#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__4__PORT 2u
-#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__4__SHIFT 4
-#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__5__MASK 0x08u
-#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3
-#define SCSI_In_DBx__5__PORT 2u
-#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__5__SHIFT 3
-#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__6__MASK 0x04u
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2
-#define SCSI_In_DBx__6__PORT 2u
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__6__SHIFT 2
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__7__MASK 0x02u
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1
-#define SCSI_In_DBx__7__PORT 2u
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__7__SHIFT 1
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__DB0__MASK 0x10u
-#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__DB0__PORT 12u
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__DB0__SHIFT 4
-#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB1__MASK 0x80u
-#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7
-#define SCSI_In_DBx__DB1__PORT 2u
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB1__SHIFT 7
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB2__MASK 0x40u
-#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6
-#define SCSI_In_DBx__DB2__PORT 2u
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB2__SHIFT 6
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB3__MASK 0x20u
-#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__DB3__PORT 2u
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB3__SHIFT 5
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB4__MASK 0x10u
-#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__DB4__PORT 2u
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB4__SHIFT 4
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB5__MASK 0x08u
-#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3
-#define SCSI_In_DBx__DB5__PORT 2u
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB5__SHIFT 3
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB6__MASK 0x04u
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2
-#define SCSI_In_DBx__DB6__PORT 2u
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB6__SHIFT 2
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB7__MASK 0x02u
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1
-#define SCSI_In_DBx__DB7__PORT 2u
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB7__SHIFT 1
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_RX_DMA__DRQ_NUMBER 0u
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u
-#define SCSI_RX_DMA__PRIORITY 2u
-#define SCSI_RX_DMA__TERMIN_EN 0u
-#define SCSI_RX_DMA__TERMIN_SEL 0u
-#define SCSI_RX_DMA__TERMOUT0_EN 1u
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u
-#define SCSI_RX_DMA__TERMOUT1_EN 0u
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u
-
-/* SCSI_TX_DMA */
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_TX_DMA__DRQ_NUMBER 1u
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u
-#define SCSI_TX_DMA__PRIORITY 2u
-#define SCSI_TX_DMA__TERMIN_EN 0u
-#define SCSI_TX_DMA__TERMIN_SEL 0u
-#define SCSI_TX_DMA__TERMOUT0_EN 1u
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u
-#define SCSI_TX_DMA__TERMOUT1_EN 0u
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u
-
-/* SD_Data_Clk */
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
-#define SD_Data_Clk__INDEX 0x00u
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SD_Data_Clk__PM_ACT_MSK 0x01u
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SD_Data_Clk__PM_STBY_MSK 0x01u
-
-/* timer_clock */
-#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
-#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
-#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
-#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
-#define timer_clock__INDEX 0x02u
-#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define timer_clock__PM_ACT_MSK 0x04u
-#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define timer_clock__PM_STBY_MSK 0x04u
-
-/* SCSI_Noise */
-#define SCSI_Noise__0__AG CYREG_PRT12_AG
-#define SCSI_Noise__0__BIE CYREG_PRT12_BIE
-#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_Noise__0__BYP CYREG_PRT12_BYP
-#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0
-#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1
-#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2
-#define SCSI_Noise__0__DR CYREG_PRT12_DR
-#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_Noise__0__MASK 0x20u
-#define SCSI_Noise__0__PC CYREG_PRT12_PC5
-#define SCSI_Noise__0__PORT 12u
-#define SCSI_Noise__0__PRT CYREG_PRT12_PRT
-#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_Noise__0__PS CYREG_PRT12_PS
-#define SCSI_Noise__0__SHIFT 5
-#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_Noise__0__SLW CYREG_PRT12_SLW
-#define SCSI_Noise__1__AG CYREG_PRT6_AG
-#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__1__DR CYREG_PRT6_DR
-#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__1__MASK 0x10u
-#define SCSI_Noise__1__PC CYREG_PRT6_PC4
-#define SCSI_Noise__1__PORT 6u
-#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__1__PS CYREG_PRT6_PS
-#define SCSI_Noise__1__SHIFT 4
-#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__2__AG CYREG_PRT5_AG
-#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX
-#define SCSI_Noise__2__BIE CYREG_PRT5_BIE
-#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Noise__2__BYP CYREG_PRT5_BYP
-#define SCSI_Noise__2__CTL CYREG_PRT5_CTL
-#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0
-#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1
-#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2
-#define SCSI_Noise__2__DR CYREG_PRT5_DR
-#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Noise__2__MASK 0x01u
-#define SCSI_Noise__2__PC CYREG_PRT5_PC0
-#define SCSI_Noise__2__PORT 5u
-#define SCSI_Noise__2__PRT CYREG_PRT5_PRT
-#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Noise__2__PS CYREG_PRT5_PS
-#define SCSI_Noise__2__SHIFT 0
-#define SCSI_Noise__2__SLW CYREG_PRT5_SLW
-#define SCSI_Noise__3__AG CYREG_PRT6_AG
-#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__3__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__3__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__3__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__3__DR CYREG_PRT6_DR
-#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__3__MASK 0x40u
-#define SCSI_Noise__3__PC CYREG_PRT6_PC6
-#define SCSI_Noise__3__PORT 6u
-#define SCSI_Noise__3__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__3__PS CYREG_PRT6_PS
-#define SCSI_Noise__3__SHIFT 6
-#define SCSI_Noise__3__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__4__AG CYREG_PRT6_AG
-#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__4__DR CYREG_PRT6_DR
-#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__4__MASK 0x20u
-#define SCSI_Noise__4__PC CYREG_PRT6_PC5
-#define SCSI_Noise__4__PORT 6u
-#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__4__PS CYREG_PRT6_PS
-#define SCSI_Noise__4__SHIFT 5
-#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
-#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
-#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__ACK__MASK 0x20u
-#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5
-#define SCSI_Noise__ACK__PORT 6u
-#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
-#define SCSI_Noise__ACK__SHIFT 5
-#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__ATN__AG CYREG_PRT12_AG
-#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE
-#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP
-#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0
-#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1
-#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2
-#define SCSI_Noise__ATN__DR CYREG_PRT12_DR
-#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_Noise__ATN__MASK 0x20u
-#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5
-#define SCSI_Noise__ATN__PORT 12u
-#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT
-#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_Noise__ATN__PS CYREG_PRT12_PS
-#define SCSI_Noise__ATN__SHIFT 5
-#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW
-#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
-#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
-#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__BSY__MASK 0x10u
-#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4
-#define SCSI_Noise__BSY__PORT 6u
-#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
-#define SCSI_Noise__BSY__SHIFT 4
-#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__RST__AG CYREG_PRT6_AG
-#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__RST__DR CYREG_PRT6_DR
-#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__RST__MASK 0x40u
-#define SCSI_Noise__RST__PC CYREG_PRT6_PC6
-#define SCSI_Noise__RST__PORT 6u
-#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__RST__PS CYREG_PRT6_PS
-#define SCSI_Noise__RST__SHIFT 6
-#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__SEL__AG CYREG_PRT5_AG
-#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX
-#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE
-#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP
-#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL
-#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0
-#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1
-#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2
-#define SCSI_Noise__SEL__DR CYREG_PRT5_DR
-#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Noise__SEL__MASK 0x01u
-#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0
-#define SCSI_Noise__SEL__PORT 5u
-#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT
-#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Noise__SEL__PS CYREG_PRT5_PS
-#define SCSI_Noise__SEL__SHIFT 0
-#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW
-
-/* scsiTarget */
-#define scsiTarget_StatusReg__0__MASK 0x01u
-#define scsiTarget_StatusReg__0__POS 0
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
-#define scsiTarget_StatusReg__1__MASK 0x02u
-#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__2__MASK 0x04u
-#define scsiTarget_StatusReg__2__POS 2
-#define scsiTarget_StatusReg__3__MASK 0x08u
-#define scsiTarget_StatusReg__3__POS 3
-#define scsiTarget_StatusReg__4__MASK 0x10u
-#define scsiTarget_StatusReg__4__POS 4
-#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB05_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB05_ST
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB01_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB01_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB01_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB01_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB01_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB01_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB01_MSK
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB01_02_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB01_02_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB01_02_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB01_02_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB01_02_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB01_02_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB01_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB01_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB01_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB01_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB01_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB01_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB01_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB01_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB01_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x40u
-#define USBFS_ep_1__INTC_NUMBER 6u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x80u
-#define USBFS_ep_2__INTC_NUMBER 7u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x100u
-#define USBFS_ep_3__INTC_NUMBER 8u
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x200u
-#define USBFS_ep_4__INTC_NUMBER 9u
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_RX_DMA__DRQ_NUMBER 2u
-#define SD_RX_DMA__NUMBEROF_TDS 0u
-#define SD_RX_DMA__PRIORITY 1u
-#define SD_RX_DMA__TERMIN_EN 0u
-#define SD_RX_DMA__TERMIN_SEL 0u
-#define SD_RX_DMA__TERMOUT0_EN 1u
-#define SD_RX_DMA__TERMOUT0_SEL 2u
-#define SD_RX_DMA__TERMOUT1_EN 0u
-#define SD_RX_DMA__TERMOUT1_SEL 0u
-
-/* SD_TX_DMA */
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_TX_DMA__DRQ_NUMBER 3u
-#define SD_TX_DMA__NUMBEROF_TDS 0u
-#define SD_TX_DMA__PRIORITY 2u
-#define SD_TX_DMA__TERMIN_EN 0u
-#define SD_TX_DMA__TERMIN_SEL 0u
-#define SD_TX_DMA__TERMOUT0_EN 1u
-#define SD_TX_DMA__TERMOUT0_SEL 3u
-#define SD_TX_DMA__TERMOUT1_EN 0u
-#define SD_TX_DMA__TERMOUT1_SEL 0u
-
-/* USBFS_USB */
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
-#define USBFS_USB__CR0 CYREG_USB_CR0
-#define USBFS_USB__CR1 CYREG_USB_CR1
-#define USBFS_USB__CWA CYREG_USB_CWA
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
-#define USBFS_USB__PM_ACT_MSK 0x01u
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
-#define USBFS_USB__PM_STBY_MSK 0x01u
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
-#define USBFS_USB__SOF0 CYREG_USB_SOF0
-#define USBFS_USB__SOF1 CYREG_USB_SOF1
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
-#define SCSI_CLK__INDEX 0x01u
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SCSI_CLK__PM_ACT_MSK 0x02u
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SCSI_CLK__PM_STBY_MSK 0x02u
-
-/* SCSI_Out */
-#define SCSI_Out__0__AG CYREG_PRT4_AG
-#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__0__BIE CYREG_PRT4_BIE
-#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__0__BYP CYREG_PRT4_BYP
-#define SCSI_Out__0__CTL CYREG_PRT4_CTL
-#define SCSI_Out__0__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__0__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__0__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__0__DR CYREG_PRT4_DR
-#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__0__MASK 0x08u
-#define SCSI_Out__0__PC CYREG_PRT4_PC3
-#define SCSI_Out__0__PORT 4u
-#define SCSI_Out__0__PRT CYREG_PRT4_PRT
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__0__PS CYREG_PRT4_PS
-#define SCSI_Out__0__SHIFT 3
-#define SCSI_Out__0__SLW CYREG_PRT4_SLW
-#define SCSI_Out__1__AG CYREG_PRT4_AG
-#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__1__BIE CYREG_PRT4_BIE
-#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__1__BYP CYREG_PRT4_BYP
-#define SCSI_Out__1__CTL CYREG_PRT4_CTL
-#define SCSI_Out__1__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__1__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__1__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__1__DR CYREG_PRT4_DR
-#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__1__MASK 0x04u
-#define SCSI_Out__1__PC CYREG_PRT4_PC2
-#define SCSI_Out__1__PORT 4u
-#define SCSI_Out__1__PRT CYREG_PRT4_PRT
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__1__PS CYREG_PRT4_PS
-#define SCSI_Out__1__SHIFT 2
-#define SCSI_Out__1__SLW CYREG_PRT4_SLW
-#define SCSI_Out__2__AG CYREG_PRT0_AG
-#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__2__BIE CYREG_PRT0_BIE
-#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__2__BYP CYREG_PRT0_BYP
-#define SCSI_Out__2__CTL CYREG_PRT0_CTL
-#define SCSI_Out__2__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__2__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__2__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__2__DR CYREG_PRT0_DR
-#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__2__MASK 0x80u
-#define SCSI_Out__2__PC CYREG_PRT0_PC7
-#define SCSI_Out__2__PORT 0u
-#define SCSI_Out__2__PRT CYREG_PRT0_PRT
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__2__PS CYREG_PRT0_PS
-#define SCSI_Out__2__SHIFT 7
-#define SCSI_Out__2__SLW CYREG_PRT0_SLW
-#define SCSI_Out__3__AG CYREG_PRT0_AG
-#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__3__BIE CYREG_PRT0_BIE
-#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__3__BYP CYREG_PRT0_BYP
-#define SCSI_Out__3__CTL CYREG_PRT0_CTL
-#define SCSI_Out__3__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__3__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__3__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__3__DR CYREG_PRT0_DR
-#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__3__MASK 0x40u
-#define SCSI_Out__3__PC CYREG_PRT0_PC6
-#define SCSI_Out__3__PORT 0u
-#define SCSI_Out__3__PRT CYREG_PRT0_PRT
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__3__PS CYREG_PRT0_PS
-#define SCSI_Out__3__SHIFT 6
-#define SCSI_Out__3__SLW CYREG_PRT0_SLW
-#define SCSI_Out__4__AG CYREG_PRT0_AG
-#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__4__BIE CYREG_PRT0_BIE
-#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__4__BYP CYREG_PRT0_BYP
-#define SCSI_Out__4__CTL CYREG_PRT0_CTL
-#define SCSI_Out__4__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__4__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__4__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__4__DR CYREG_PRT0_DR
-#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__4__MASK 0x20u
-#define SCSI_Out__4__PC CYREG_PRT0_PC5
-#define SCSI_Out__4__PORT 0u
-#define SCSI_Out__4__PRT CYREG_PRT0_PRT
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__4__PS CYREG_PRT0_PS
-#define SCSI_Out__4__SHIFT 5
-#define SCSI_Out__4__SLW CYREG_PRT0_SLW
-#define SCSI_Out__5__AG CYREG_PRT0_AG
-#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__5__BIE CYREG_PRT0_BIE
-#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__5__BYP CYREG_PRT0_BYP
-#define SCSI_Out__5__CTL CYREG_PRT0_CTL
-#define SCSI_Out__5__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__5__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__5__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__5__DR CYREG_PRT0_DR
-#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__5__MASK 0x10u
-#define SCSI_Out__5__PC CYREG_PRT0_PC4
-#define SCSI_Out__5__PORT 0u
-#define SCSI_Out__5__PRT CYREG_PRT0_PRT
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__5__PS CYREG_PRT0_PS
-#define SCSI_Out__5__SHIFT 4
-#define SCSI_Out__5__SLW CYREG_PRT0_SLW
-#define SCSI_Out__6__AG CYREG_PRT0_AG
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__6__DR CYREG_PRT0_DR
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__6__MASK 0x08u
-#define SCSI_Out__6__PC CYREG_PRT0_PC3
-#define SCSI_Out__6__PORT 0u
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__6__PS CYREG_PRT0_PS
-#define SCSI_Out__6__SHIFT 3
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW
-#define SCSI_Out__7__AG CYREG_PRT0_AG
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__7__DR CYREG_PRT0_DR
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__7__MASK 0x04u
-#define SCSI_Out__7__PC CYREG_PRT0_PC2
-#define SCSI_Out__7__PORT 0u
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__7__PS CYREG_PRT0_PS
-#define SCSI_Out__7__SHIFT 2
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW
-#define SCSI_Out__8__AG CYREG_PRT0_AG
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__8__DR CYREG_PRT0_DR
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__8__MASK 0x02u
-#define SCSI_Out__8__PC CYREG_PRT0_PC1
-#define SCSI_Out__8__PORT 0u
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__8__PS CYREG_PRT0_PS
-#define SCSI_Out__8__SHIFT 1
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW
-#define SCSI_Out__9__AG CYREG_PRT0_AG
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__9__DR CYREG_PRT0_DR
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__9__MASK 0x01u
-#define SCSI_Out__9__PC CYREG_PRT0_PC0
-#define SCSI_Out__9__PORT 0u
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__9__PS CYREG_PRT0_PS
-#define SCSI_Out__9__SHIFT 0
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW
-#define SCSI_Out__ACK__AG CYREG_PRT0_AG
-#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP
-#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL
-#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__ACK__DR CYREG_PRT0_DR
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__ACK__MASK 0x40u
-#define SCSI_Out__ACK__PC CYREG_PRT0_PC6
-#define SCSI_Out__ACK__PORT 0u
-#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__ACK__PS CYREG_PRT0_PS
-#define SCSI_Out__ACK__SHIFT 6
-#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW
-#define SCSI_Out__ATN__AG CYREG_PRT4_AG
-#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP
-#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL
-#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__ATN__DR CYREG_PRT4_DR
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__ATN__MASK 0x04u
-#define SCSI_Out__ATN__PC CYREG_PRT4_PC2
-#define SCSI_Out__ATN__PORT 4u
-#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__ATN__PS CYREG_PRT4_PS
-#define SCSI_Out__ATN__SHIFT 2
-#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW
-#define SCSI_Out__BSY__AG CYREG_PRT0_AG
-#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP
-#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL
-#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__BSY__DR CYREG_PRT0_DR
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__BSY__MASK 0x80u
-#define SCSI_Out__BSY__PC CYREG_PRT0_PC7
-#define SCSI_Out__BSY__PORT 0u
-#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__BSY__PS CYREG_PRT0_PS
-#define SCSI_Out__BSY__SHIFT 7
-#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__CD_raw__MASK 0x04u
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2
-#define SCSI_Out__CD_raw__PORT 0u
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__CD_raw__SHIFT 2
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__DBP_raw__MASK 0x08u
-#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3
-#define SCSI_Out__DBP_raw__PORT 4u
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS
-#define SCSI_Out__DBP_raw__SHIFT 3
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__IO_raw__MASK 0x01u
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0
-#define SCSI_Out__IO_raw__PORT 0u
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__IO_raw__SHIFT 0
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__MSG_raw__MASK 0x10u
-#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4
-#define SCSI_Out__MSG_raw__PORT 0u
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__MSG_raw__SHIFT 4
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__REQ__MASK 0x02u
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC1
-#define SCSI_Out__REQ__PORT 0u
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS
-#define SCSI_Out__REQ__SHIFT 1
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
-#define SCSI_Out__RST__AG CYREG_PRT0_AG
-#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__RST__BIE CYREG_PRT0_BIE
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__RST__BYP CYREG_PRT0_BYP
-#define SCSI_Out__RST__CTL CYREG_PRT0_CTL
-#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__RST__DR CYREG_PRT0_DR
-#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__RST__MASK 0x20u
-#define SCSI_Out__RST__PC CYREG_PRT0_PC5
-#define SCSI_Out__RST__PORT 0u
-#define SCSI_Out__RST__PRT CYREG_PRT0_PRT
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__RST__PS CYREG_PRT0_PS
-#define SCSI_Out__RST__SHIFT 5
-#define SCSI_Out__RST__SLW CYREG_PRT0_SLW
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__SEL__MASK 0x08u
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC3
-#define SCSI_Out__SEL__PORT 0u
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS
-#define SCSI_Out__SEL__SHIFT 3
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
-
-/* USBFS_Dm */
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_RxStsReg__4__POS 4
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
+#define SDCard_BSPIM_RxStsReg__5__POS 5
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
+#define SDCard_BSPIM_RxStsReg__6__POS 6
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
+#define SDCard_BSPIM_TxStsReg__0__POS 0
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
+#define SDCard_BSPIM_TxStsReg__1__POS 1
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
+#define SDCard_BSPIM_TxStsReg__2__POS 2
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
+#define SDCard_BSPIM_TxStsReg__3__POS 3
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_TxStsReg__4__POS 4
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB04_ST
 
-/* USBFS_Dp */
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+#define SD_SCK__0__MASK 0x04u
+#define SD_SCK__0__PC CYREG_PRT3_PC2
+#define SD_SCK__0__PORT 3u
+#define SD_SCK__0__SHIFT 2
+#define SD_SCK__AG CYREG_PRT3_AG
+#define SD_SCK__AMUX CYREG_PRT3_AMUX
+#define SD_SCK__BIE CYREG_PRT3_BIE
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_SCK__BYP CYREG_PRT3_BYP
+#define SD_SCK__CTL CYREG_PRT3_CTL
+#define SD_SCK__DM0 CYREG_PRT3_DM0
+#define SD_SCK__DM1 CYREG_PRT3_DM1
+#define SD_SCK__DM2 CYREG_PRT3_DM2
+#define SD_SCK__DR CYREG_PRT3_DR
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_SCK__MASK 0x04u
+#define SD_SCK__PORT 3u
+#define SD_SCK__PRT CYREG_PRT3_PRT
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_SCK__PS CYREG_PRT3_PS
+#define SD_SCK__SHIFT 2
+#define SD_SCK__SLW CYREG_PRT3_SLW
 
 /* SCSI_In */
 #define SCSI_In__0__AG CYREG_PRT2_AG
@@ -2648,332 +757,2229 @@
 #define SCSI_In__REQ__SHIFT 2
 #define SCSI_In__REQ__SLW CYREG_PRT5_SLW
 
-/* SD_DAT1 */
-#define SD_DAT1__0__MASK 0x01u
-#define SD_DAT1__0__PC CYREG_PRT3_PC0
-#define SD_DAT1__0__PORT 3u
-#define SD_DAT1__0__SHIFT 0
-#define SD_DAT1__AG CYREG_PRT3_AG
-#define SD_DAT1__AMUX CYREG_PRT3_AMUX
-#define SD_DAT1__BIE CYREG_PRT3_BIE
-#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_DAT1__BYP CYREG_PRT3_BYP
-#define SD_DAT1__CTL CYREG_PRT3_CTL
-#define SD_DAT1__DM0 CYREG_PRT3_DM0
-#define SD_DAT1__DM1 CYREG_PRT3_DM1
-#define SD_DAT1__DM2 CYREG_PRT3_DM2
-#define SD_DAT1__DR CYREG_PRT3_DR
-#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_DAT1__MASK 0x01u
-#define SD_DAT1__PORT 3u
-#define SD_DAT1__PRT CYREG_PRT3_PRT
-#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_DAT1__PS CYREG_PRT3_PS
-#define SD_DAT1__SHIFT 0
-#define SD_DAT1__SLW CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+#define SCSI_In_DBx__0__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__0__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__0__MASK 0x10u
+#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__0__PORT 12u
+#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__0__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__0__SHIFT 4
+#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__1__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__1__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__1__MASK 0x80u
+#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7
+#define SCSI_In_DBx__1__PORT 2u
+#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__1__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__1__SHIFT 7
+#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__2__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__2__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__2__MASK 0x40u
+#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6
+#define SCSI_In_DBx__2__PORT 2u
+#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__2__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__2__SHIFT 6
+#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__3__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__3__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__3__MASK 0x20u
+#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__3__PORT 2u
+#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__3__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__3__SHIFT 5
+#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__4__MASK 0x10u
+#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__4__PORT 2u
+#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__4__SHIFT 4
+#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__5__MASK 0x08u
+#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3
+#define SCSI_In_DBx__5__PORT 2u
+#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__5__SHIFT 3
+#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__6__MASK 0x04u
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2
+#define SCSI_In_DBx__6__PORT 2u
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__6__SHIFT 2
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__7__MASK 0x02u
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1
+#define SCSI_In_DBx__7__PORT 2u
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__7__SHIFT 1
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__DB0__MASK 0x10u
+#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__DB0__PORT 12u
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__DB0__SHIFT 4
+#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB1__MASK 0x80u
+#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7
+#define SCSI_In_DBx__DB1__PORT 2u
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB1__SHIFT 7
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB2__MASK 0x40u
+#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6
+#define SCSI_In_DBx__DB2__PORT 2u
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB2__SHIFT 6
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB3__MASK 0x20u
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__DB3__PORT 2u
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB3__SHIFT 5
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB4__MASK 0x10u
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__DB4__PORT 2u
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB4__SHIFT 4
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB5__MASK 0x08u
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3
+#define SCSI_In_DBx__DB5__PORT 2u
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB5__SHIFT 3
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB6__MASK 0x04u
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2
+#define SCSI_In_DBx__DB6__PORT 2u
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB6__SHIFT 2
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB7__MASK 0x02u
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1
+#define SCSI_In_DBx__DB7__PORT 2u
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB7__SHIFT 1
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
+
+/* SD_DAT1 */
+#define SD_DAT1__0__MASK 0x01u
+#define SD_DAT1__0__PC CYREG_PRT3_PC0
+#define SD_DAT1__0__PORT 3u
+#define SD_DAT1__0__SHIFT 0
+#define SD_DAT1__AG CYREG_PRT3_AG
+#define SD_DAT1__AMUX CYREG_PRT3_AMUX
+#define SD_DAT1__BIE CYREG_PRT3_BIE
+#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_DAT1__BYP CYREG_PRT3_BYP
+#define SD_DAT1__CTL CYREG_PRT3_CTL
+#define SD_DAT1__DM0 CYREG_PRT3_DM0
+#define SD_DAT1__DM1 CYREG_PRT3_DM1
+#define SD_DAT1__DM2 CYREG_PRT3_DM2
+#define SD_DAT1__DR CYREG_PRT3_DR
+#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_DAT1__MASK 0x01u
+#define SD_DAT1__PORT 3u
+#define SD_DAT1__PRT CYREG_PRT3_PRT
+#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_DAT1__PS CYREG_PRT3_PS
+#define SD_DAT1__SHIFT 0
+#define SD_DAT1__SLW CYREG_PRT3_SLW
+
+/* SD_DAT2 */
+#define SD_DAT2__0__MASK 0x20u
+#define SD_DAT2__0__PC CYREG_PRT3_PC5
+#define SD_DAT2__0__PORT 3u
+#define SD_DAT2__0__SHIFT 5
+#define SD_DAT2__AG CYREG_PRT3_AG
+#define SD_DAT2__AMUX CYREG_PRT3_AMUX
+#define SD_DAT2__BIE CYREG_PRT3_BIE
+#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_DAT2__BYP CYREG_PRT3_BYP
+#define SD_DAT2__CTL CYREG_PRT3_CTL
+#define SD_DAT2__DM0 CYREG_PRT3_DM0
+#define SD_DAT2__DM1 CYREG_PRT3_DM1
+#define SD_DAT2__DM2 CYREG_PRT3_DM2
+#define SD_DAT2__DR CYREG_PRT3_DR
+#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_DAT2__MASK 0x20u
+#define SD_DAT2__PORT 3u
+#define SD_DAT2__PRT CYREG_PRT3_PRT
+#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_DAT2__PS CYREG_PRT3_PS
+#define SD_DAT2__SHIFT 5
+#define SD_DAT2__SLW CYREG_PRT3_SLW
+
+/* SD_MISO */
+#define SD_MISO__0__MASK 0x02u
+#define SD_MISO__0__PC CYREG_PRT3_PC1
+#define SD_MISO__0__PORT 3u
+#define SD_MISO__0__SHIFT 1
+#define SD_MISO__AG CYREG_PRT3_AG
+#define SD_MISO__AMUX CYREG_PRT3_AMUX
+#define SD_MISO__BIE CYREG_PRT3_BIE
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MISO__BYP CYREG_PRT3_BYP
+#define SD_MISO__CTL CYREG_PRT3_CTL
+#define SD_MISO__DM0 CYREG_PRT3_DM0
+#define SD_MISO__DM1 CYREG_PRT3_DM1
+#define SD_MISO__DM2 CYREG_PRT3_DM2
+#define SD_MISO__DR CYREG_PRT3_DR
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MISO__MASK 0x02u
+#define SD_MISO__PORT 3u
+#define SD_MISO__PRT CYREG_PRT3_PRT
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MISO__PS CYREG_PRT3_PS
+#define SD_MISO__SHIFT 1
+#define SD_MISO__SLW CYREG_PRT3_SLW
+
+/* SD_MOSI */
+#define SD_MOSI__0__MASK 0x08u
+#define SD_MOSI__0__PC CYREG_PRT3_PC3
+#define SD_MOSI__0__PORT 3u
+#define SD_MOSI__0__SHIFT 3
+#define SD_MOSI__AG CYREG_PRT3_AG
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX
+#define SD_MOSI__BIE CYREG_PRT3_BIE
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MOSI__BYP CYREG_PRT3_BYP
+#define SD_MOSI__CTL CYREG_PRT3_CTL
+#define SD_MOSI__DM0 CYREG_PRT3_DM0
+#define SD_MOSI__DM1 CYREG_PRT3_DM1
+#define SD_MOSI__DM2 CYREG_PRT3_DM2
+#define SD_MOSI__DR CYREG_PRT3_DR
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MOSI__MASK 0x08u
+#define SD_MOSI__PORT 3u
+#define SD_MOSI__PRT CYREG_PRT3_PRT
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MOSI__PS CYREG_PRT3_PS
+#define SD_MOSI__SHIFT 3
+#define SD_MOSI__SLW CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
+#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SCSI_CLK__PM_STBY_MSK 0x02u
+
+/* SCSI_Out */
+#define SCSI_Out__0__AG CYREG_PRT4_AG
+#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__0__BIE CYREG_PRT4_BIE
+#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__0__BYP CYREG_PRT4_BYP
+#define SCSI_Out__0__CTL CYREG_PRT4_CTL
+#define SCSI_Out__0__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__0__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__0__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__0__DR CYREG_PRT4_DR
+#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__0__MASK 0x08u
+#define SCSI_Out__0__PC CYREG_PRT4_PC3
+#define SCSI_Out__0__PORT 4u
+#define SCSI_Out__0__PRT CYREG_PRT4_PRT
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__0__PS CYREG_PRT4_PS
+#define SCSI_Out__0__SHIFT 3
+#define SCSI_Out__0__SLW CYREG_PRT4_SLW
+#define SCSI_Out__1__AG CYREG_PRT4_AG
+#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__1__BIE CYREG_PRT4_BIE
+#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__1__BYP CYREG_PRT4_BYP
+#define SCSI_Out__1__CTL CYREG_PRT4_CTL
+#define SCSI_Out__1__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__1__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__1__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__1__DR CYREG_PRT4_DR
+#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__1__MASK 0x04u
+#define SCSI_Out__1__PC CYREG_PRT4_PC2
+#define SCSI_Out__1__PORT 4u
+#define SCSI_Out__1__PRT CYREG_PRT4_PRT
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__1__PS CYREG_PRT4_PS
+#define SCSI_Out__1__SHIFT 2
+#define SCSI_Out__1__SLW CYREG_PRT4_SLW
+#define SCSI_Out__2__AG CYREG_PRT0_AG
+#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__2__BIE CYREG_PRT0_BIE
+#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__2__BYP CYREG_PRT0_BYP
+#define SCSI_Out__2__CTL CYREG_PRT0_CTL
+#define SCSI_Out__2__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__2__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__2__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__2__DR CYREG_PRT0_DR
+#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__2__MASK 0x80u
+#define SCSI_Out__2__PC CYREG_PRT0_PC7
+#define SCSI_Out__2__PORT 0u
+#define SCSI_Out__2__PRT CYREG_PRT0_PRT
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__2__PS CYREG_PRT0_PS
+#define SCSI_Out__2__SHIFT 7
+#define SCSI_Out__2__SLW CYREG_PRT0_SLW
+#define SCSI_Out__3__AG CYREG_PRT0_AG
+#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__3__BIE CYREG_PRT0_BIE
+#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__3__BYP CYREG_PRT0_BYP
+#define SCSI_Out__3__CTL CYREG_PRT0_CTL
+#define SCSI_Out__3__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__3__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__3__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__3__DR CYREG_PRT0_DR
+#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__3__MASK 0x40u
+#define SCSI_Out__3__PC CYREG_PRT0_PC6
+#define SCSI_Out__3__PORT 0u
+#define SCSI_Out__3__PRT CYREG_PRT0_PRT
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__3__PS CYREG_PRT0_PS
+#define SCSI_Out__3__SHIFT 6
+#define SCSI_Out__3__SLW CYREG_PRT0_SLW
+#define SCSI_Out__4__AG CYREG_PRT0_AG
+#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__4__BIE CYREG_PRT0_BIE
+#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__4__BYP CYREG_PRT0_BYP
+#define SCSI_Out__4__CTL CYREG_PRT0_CTL
+#define SCSI_Out__4__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__4__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__4__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__4__DR CYREG_PRT0_DR
+#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__4__MASK 0x20u
+#define SCSI_Out__4__PC CYREG_PRT0_PC5
+#define SCSI_Out__4__PORT 0u
+#define SCSI_Out__4__PRT CYREG_PRT0_PRT
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__4__PS CYREG_PRT0_PS
+#define SCSI_Out__4__SHIFT 5
+#define SCSI_Out__4__SLW CYREG_PRT0_SLW
+#define SCSI_Out__5__AG CYREG_PRT0_AG
+#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__5__BIE CYREG_PRT0_BIE
+#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__5__BYP CYREG_PRT0_BYP
+#define SCSI_Out__5__CTL CYREG_PRT0_CTL
+#define SCSI_Out__5__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__5__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__5__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__5__DR CYREG_PRT0_DR
+#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__5__MASK 0x10u
+#define SCSI_Out__5__PC CYREG_PRT0_PC4
+#define SCSI_Out__5__PORT 0u
+#define SCSI_Out__5__PRT CYREG_PRT0_PRT
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__5__PS CYREG_PRT0_PS
+#define SCSI_Out__5__SHIFT 4
+#define SCSI_Out__5__SLW CYREG_PRT0_SLW
+#define SCSI_Out__6__AG CYREG_PRT0_AG
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__6__DR CYREG_PRT0_DR
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__6__MASK 0x08u
+#define SCSI_Out__6__PC CYREG_PRT0_PC3
+#define SCSI_Out__6__PORT 0u
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__6__PS CYREG_PRT0_PS
+#define SCSI_Out__6__SHIFT 3
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW
+#define SCSI_Out__7__AG CYREG_PRT0_AG
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__7__DR CYREG_PRT0_DR
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__7__MASK 0x04u
+#define SCSI_Out__7__PC CYREG_PRT0_PC2
+#define SCSI_Out__7__PORT 0u
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__7__PS CYREG_PRT0_PS
+#define SCSI_Out__7__SHIFT 2
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW
+#define SCSI_Out__8__AG CYREG_PRT0_AG
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__8__DR CYREG_PRT0_DR
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__8__MASK 0x02u
+#define SCSI_Out__8__PC CYREG_PRT0_PC1
+#define SCSI_Out__8__PORT 0u
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__8__PS CYREG_PRT0_PS
+#define SCSI_Out__8__SHIFT 1
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW
+#define SCSI_Out__9__AG CYREG_PRT0_AG
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__9__DR CYREG_PRT0_DR
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__9__MASK 0x01u
+#define SCSI_Out__9__PC CYREG_PRT0_PC0
+#define SCSI_Out__9__PORT 0u
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__9__PS CYREG_PRT0_PS
+#define SCSI_Out__9__SHIFT 0
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW
+#define SCSI_Out__ACK__AG CYREG_PRT0_AG
+#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP
+#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL
+#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__ACK__DR CYREG_PRT0_DR
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__ACK__MASK 0x40u
+#define SCSI_Out__ACK__PC CYREG_PRT0_PC6
+#define SCSI_Out__ACK__PORT 0u
+#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__ACK__PS CYREG_PRT0_PS
+#define SCSI_Out__ACK__SHIFT 6
+#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW
+#define SCSI_Out__ATN__AG CYREG_PRT4_AG
+#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP
+#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL
+#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__ATN__DR CYREG_PRT4_DR
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__ATN__MASK 0x04u
+#define SCSI_Out__ATN__PC CYREG_PRT4_PC2
+#define SCSI_Out__ATN__PORT 4u
+#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__ATN__PS CYREG_PRT4_PS
+#define SCSI_Out__ATN__SHIFT 2
+#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW
+#define SCSI_Out__BSY__AG CYREG_PRT0_AG
+#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP
+#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL
+#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__BSY__DR CYREG_PRT0_DR
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__BSY__MASK 0x80u
+#define SCSI_Out__BSY__PC CYREG_PRT0_PC7
+#define SCSI_Out__BSY__PORT 0u
+#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__BSY__PS CYREG_PRT0_PS
+#define SCSI_Out__BSY__SHIFT 7
+#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__CD_raw__MASK 0x04u
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2
+#define SCSI_Out__CD_raw__PORT 0u
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__CD_raw__SHIFT 2
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__DBP_raw__MASK 0x08u
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3
+#define SCSI_Out__DBP_raw__PORT 4u
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS
+#define SCSI_Out__DBP_raw__SHIFT 3
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__IO_raw__MASK 0x01u
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0
+#define SCSI_Out__IO_raw__PORT 0u
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__IO_raw__SHIFT 0
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__MSG_raw__MASK 0x10u
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4
+#define SCSI_Out__MSG_raw__PORT 0u
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__MSG_raw__SHIFT 4
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__REQ__MASK 0x02u
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC1
+#define SCSI_Out__REQ__PORT 0u
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS
+#define SCSI_Out__REQ__SHIFT 1
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
+#define SCSI_Out__RST__AG CYREG_PRT0_AG
+#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__RST__BIE CYREG_PRT0_BIE
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__RST__BYP CYREG_PRT0_BYP
+#define SCSI_Out__RST__CTL CYREG_PRT0_CTL
+#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__RST__DR CYREG_PRT0_DR
+#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__RST__MASK 0x20u
+#define SCSI_Out__RST__PC CYREG_PRT0_PC5
+#define SCSI_Out__RST__PORT 0u
+#define SCSI_Out__RST__PRT CYREG_PRT0_PRT
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__RST__PS CYREG_PRT0_PS
+#define SCSI_Out__RST__SHIFT 5
+#define SCSI_Out__RST__SLW CYREG_PRT0_SLW
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__SEL__MASK 0x08u
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC3
+#define SCSI_Out__SEL__PORT 0u
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS
+#define SCSI_Out__SEL__SHIFT 3
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+
+/* SCSI_Out_Ctl */
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
+
+/* SCSI_Out_DBx */
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x08u
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3
+#define SCSI_Out_DBx__0__PORT 6u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__0__SHIFT 3
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x04u
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2
+#define SCSI_Out_DBx__1__PORT 6u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__1__SHIFT 2
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__2__MASK 0x02u
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1
+#define SCSI_Out_DBx__2__PORT 6u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__2__SHIFT 1
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x01u
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0
+#define SCSI_Out_DBx__3__PORT 6u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__3__SHIFT 0
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x80u
+#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7
+#define SCSI_Out_DBx__4__PORT 4u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__4__SHIFT 7
+#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x40u
+#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6
+#define SCSI_Out_DBx__5__PORT 4u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__5__SHIFT 6
+#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x20u
+#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5
+#define SCSI_Out_DBx__6__PORT 4u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__6__SHIFT 5
+#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x10u
+#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4
+#define SCSI_Out_DBx__7__PORT 4u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__7__SHIFT 4
+#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x08u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3
+#define SCSI_Out_DBx__DB0__PORT 6u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB0__SHIFT 3
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x04u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2
+#define SCSI_Out_DBx__DB1__PORT 6u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB1__SHIFT 2
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB2__MASK 0x02u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1
+#define SCSI_Out_DBx__DB2__PORT 6u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB2__SHIFT 1
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x01u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0
+#define SCSI_Out_DBx__DB3__PORT 6u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB3__SHIFT 0
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x80u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7
+#define SCSI_Out_DBx__DB4__PORT 4u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB4__SHIFT 7
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x40u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6
+#define SCSI_Out_DBx__DB5__PORT 4u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB5__SHIFT 6
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x20u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5
+#define SCSI_Out_DBx__DB6__PORT 4u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB6__SHIFT 5
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x10u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4
+#define SCSI_Out_DBx__DB7__PORT 4u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB7__SHIFT 4
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW
+
+/* SD_RX_DMA */
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_RX_DMA__DRQ_NUMBER 2u
+#define SD_RX_DMA__NUMBEROF_TDS 0u
+#define SD_RX_DMA__PRIORITY 2u
+#define SD_RX_DMA__TERMIN_EN 0u
+#define SD_RX_DMA__TERMIN_SEL 0u
+#define SD_RX_DMA__TERMOUT0_EN 1u
+#define SD_RX_DMA__TERMOUT0_SEL 2u
+#define SD_RX_DMA__TERMOUT1_EN 0u
+#define SD_RX_DMA__TERMOUT1_SEL 0u
+
+/* SD_RX_DMA_COMPLETE */
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_TX_DMA__DRQ_NUMBER 3u
+#define SD_TX_DMA__NUMBEROF_TDS 0u
+#define SD_TX_DMA__PRIORITY 2u
+#define SD_TX_DMA__TERMIN_EN 0u
+#define SD_TX_DMA__TERMIN_SEL 0u
+#define SD_TX_DMA__TERMOUT0_EN 1u
+#define SD_TX_DMA__TERMOUT0_SEL 3u
+#define SD_TX_DMA__TERMOUT1_EN 0u
+#define SD_TX_DMA__TERMOUT1_SEL 0u
+
+/* SD_TX_DMA_COMPLETE */
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+#define SCSI_Noise__0__AG CYREG_PRT12_AG
+#define SCSI_Noise__0__BIE CYREG_PRT12_BIE
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_Noise__0__BYP CYREG_PRT12_BYP
+#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0
+#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1
+#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2
+#define SCSI_Noise__0__DR CYREG_PRT12_DR
+#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_Noise__0__MASK 0x20u
+#define SCSI_Noise__0__PC CYREG_PRT12_PC5
+#define SCSI_Noise__0__PORT 12u
+#define SCSI_Noise__0__PRT CYREG_PRT12_PRT
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_Noise__0__PS CYREG_PRT12_PS
+#define SCSI_Noise__0__SHIFT 5
+#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_Noise__0__SLW CYREG_PRT12_SLW
+#define SCSI_Noise__1__AG CYREG_PRT6_AG
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__1__DR CYREG_PRT6_DR
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__1__MASK 0x10u
+#define SCSI_Noise__1__PC CYREG_PRT6_PC4
+#define SCSI_Noise__1__PORT 6u
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__1__PS CYREG_PRT6_PS
+#define SCSI_Noise__1__SHIFT 4
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__2__AG CYREG_PRT5_AG
+#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX
+#define SCSI_Noise__2__BIE CYREG_PRT5_BIE
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Noise__2__BYP CYREG_PRT5_BYP
+#define SCSI_Noise__2__CTL CYREG_PRT5_CTL
+#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0
+#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1
+#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2
+#define SCSI_Noise__2__DR CYREG_PRT5_DR
+#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Noise__2__MASK 0x01u
+#define SCSI_Noise__2__PC CYREG_PRT5_PC0
+#define SCSI_Noise__2__PORT 5u
+#define SCSI_Noise__2__PRT CYREG_PRT5_PRT
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Noise__2__PS CYREG_PRT5_PS
+#define SCSI_Noise__2__SHIFT 0
+#define SCSI_Noise__2__SLW CYREG_PRT5_SLW
+#define SCSI_Noise__3__AG CYREG_PRT6_AG
+#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__3__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__3__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__3__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__3__DR CYREG_PRT6_DR
+#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__3__MASK 0x40u
+#define SCSI_Noise__3__PC CYREG_PRT6_PC6
+#define SCSI_Noise__3__PORT 6u
+#define SCSI_Noise__3__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__3__PS CYREG_PRT6_PS
+#define SCSI_Noise__3__SHIFT 6
+#define SCSI_Noise__3__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__4__AG CYREG_PRT6_AG
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__4__DR CYREG_PRT6_DR
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__4__MASK 0x20u
+#define SCSI_Noise__4__PC CYREG_PRT6_PC5
+#define SCSI_Noise__4__PORT 6u
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__4__PS CYREG_PRT6_PS
+#define SCSI_Noise__4__SHIFT 5
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__ACK__MASK 0x20u
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5
+#define SCSI_Noise__ACK__PORT 6u
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
+#define SCSI_Noise__ACK__SHIFT 5
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ATN__AG CYREG_PRT12_AG
+#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP
+#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0
+#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1
+#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2
+#define SCSI_Noise__ATN__DR CYREG_PRT12_DR
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_Noise__ATN__MASK 0x20u
+#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5
+#define SCSI_Noise__ATN__PORT 12u
+#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_Noise__ATN__PS CYREG_PRT12_PS
+#define SCSI_Noise__ATN__SHIFT 5
+#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__BSY__MASK 0x10u
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4
+#define SCSI_Noise__BSY__PORT 6u
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
+#define SCSI_Noise__BSY__SHIFT 4
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__RST__AG CYREG_PRT6_AG
+#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__RST__DR CYREG_PRT6_DR
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__RST__MASK 0x40u
+#define SCSI_Noise__RST__PC CYREG_PRT6_PC6
+#define SCSI_Noise__RST__PORT 6u
+#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__RST__PS CYREG_PRT6_PS
+#define SCSI_Noise__RST__SHIFT 6
+#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__SEL__AG CYREG_PRT5_AG
+#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX
+#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP
+#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL
+#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0
+#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1
+#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2
+#define SCSI_Noise__SEL__DR CYREG_PRT5_DR
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Noise__SEL__MASK 0x01u
+#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0
+#define SCSI_Noise__SEL__PORT 5u
+#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Noise__SEL__PS CYREG_PRT5_PS
+#define SCSI_Noise__SEL__SHIFT 0
+#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW
+
+/* scsiTarget */
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB05_06_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB05_06_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB05_06_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB05_06_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB05_06_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB05_06_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB05_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB05_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB05_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB05_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB05_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB05_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB05_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB05_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB05_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB05_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB05_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB05_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB05_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB05_MSK
+#define scsiTarget_StatusReg__0__MASK 0x01u
+#define scsiTarget_StatusReg__0__POS 0
+#define scsiTarget_StatusReg__1__MASK 0x02u
+#define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define scsiTarget_StatusReg__2__MASK 0x04u
+#define scsiTarget_StatusReg__2__POS 2
+#define scsiTarget_StatusReg__3__MASK 0x08u
+#define scsiTarget_StatusReg__3__POS 3
+#define scsiTarget_StatusReg__4__MASK 0x10u
+#define scsiTarget_StatusReg__4__POS 4
+#define scsiTarget_StatusReg__MASK 0x1Fu
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
 
-/* SD_DAT2 */
-#define SD_DAT2__0__MASK 0x20u
-#define SD_DAT2__0__PC CYREG_PRT3_PC5
-#define SD_DAT2__0__PORT 3u
-#define SD_DAT2__0__SHIFT 5
-#define SD_DAT2__AG CYREG_PRT3_AG
-#define SD_DAT2__AMUX CYREG_PRT3_AMUX
-#define SD_DAT2__BIE CYREG_PRT3_BIE
-#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_DAT2__BYP CYREG_PRT3_BYP
-#define SD_DAT2__CTL CYREG_PRT3_CTL
-#define SD_DAT2__DM0 CYREG_PRT3_DM0
-#define SD_DAT2__DM1 CYREG_PRT3_DM1
-#define SD_DAT2__DM2 CYREG_PRT3_DM2
-#define SD_DAT2__DR CYREG_PRT3_DR
-#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_DAT2__MASK 0x20u
-#define SD_DAT2__PORT 3u
-#define SD_DAT2__PRT CYREG_PRT3_PRT
-#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_DAT2__PS CYREG_PRT3_PS
-#define SD_DAT2__SHIFT 5
-#define SD_DAT2__SLW CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define Debug_Timer_Interrupt__INTC_MASK 0x02u
+#define Debug_Timer_Interrupt__INTC_NUMBER 1u
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SD_MISO */
-#define SD_MISO__0__MASK 0x02u
-#define SD_MISO__0__PC CYREG_PRT3_PC1
-#define SD_MISO__0__PORT 3u
-#define SD_MISO__0__SHIFT 1
-#define SD_MISO__AG CYREG_PRT3_AG
-#define SD_MISO__AMUX CYREG_PRT3_AMUX
-#define SD_MISO__BIE CYREG_PRT3_BIE
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MISO__BYP CYREG_PRT3_BYP
-#define SD_MISO__CTL CYREG_PRT3_CTL
-#define SD_MISO__DM0 CYREG_PRT3_DM0
-#define SD_MISO__DM1 CYREG_PRT3_DM1
-#define SD_MISO__DM2 CYREG_PRT3_DM2
-#define SD_MISO__DR CYREG_PRT3_DR
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MISO__MASK 0x02u
-#define SD_MISO__PORT 3u
-#define SD_MISO__PRT CYREG_PRT3_PRT
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MISO__PS CYREG_PRT3_PS
-#define SD_MISO__SHIFT 1
-#define SD_MISO__SLW CYREG_PRT3_SLW
+/* Debug_Timer_TimerHW */
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_RX_DMA__DRQ_NUMBER 0u
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u
+#define SCSI_RX_DMA__PRIORITY 2u
+#define SCSI_RX_DMA__TERMIN_EN 0u
+#define SCSI_RX_DMA__TERMIN_SEL 0u
+#define SCSI_RX_DMA__TERMOUT0_EN 1u
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u
+#define SCSI_RX_DMA__TERMOUT1_EN 0u
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u
+
+/* SCSI_RX_DMA_COMPLETE */
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_TX_DMA__DRQ_NUMBER 1u
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u
+#define SCSI_TX_DMA__PRIORITY 2u
+#define SCSI_TX_DMA__TERMIN_EN 0u
+#define SCSI_TX_DMA__TERMIN_SEL 0u
+#define SCSI_TX_DMA__TERMOUT0_EN 1u
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u
+#define SCSI_TX_DMA__TERMOUT1_EN 0u
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u
+
+/* SCSI_TX_DMA_COMPLETE */
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
+#define SD_Data_Clk__INDEX 0x00u
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SD_Data_Clk__PM_ACT_MSK 0x01u
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SD_Data_Clk__PM_STBY_MSK 0x01u
 
-/* SD_MOSI */
-#define SD_MOSI__0__MASK 0x08u
-#define SD_MOSI__0__PC CYREG_PRT3_PC3
-#define SD_MOSI__0__PORT 3u
-#define SD_MOSI__0__SHIFT 3
-#define SD_MOSI__AG CYREG_PRT3_AG
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX
-#define SD_MOSI__BIE CYREG_PRT3_BIE
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MOSI__BYP CYREG_PRT3_BYP
-#define SD_MOSI__CTL CYREG_PRT3_CTL
-#define SD_MOSI__DM0 CYREG_PRT3_DM0
-#define SD_MOSI__DM1 CYREG_PRT3_DM1
-#define SD_MOSI__DM2 CYREG_PRT3_DM2
-#define SD_MOSI__DR CYREG_PRT3_DR
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MOSI__MASK 0x08u
-#define SD_MOSI__PORT 3u
-#define SD_MOSI__PRT CYREG_PRT3_PRT
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MOSI__PS CYREG_PRT3_PS
-#define SD_MOSI__SHIFT 3
-#define SD_MOSI__SLW CYREG_PRT3_SLW
+/* timer_clock */
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
+#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
+#define timer_clock__INDEX 0x02u
+#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define timer_clock__PM_ACT_MSK 0x04u
+#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define timer_clock__PM_STBY_MSK 0x04u
 
-/* SD_SCK */
-#define SD_SCK__0__MASK 0x04u
-#define SD_SCK__0__PC CYREG_PRT3_PC2
-#define SD_SCK__0__PORT 3u
-#define SD_SCK__0__SHIFT 2
-#define SD_SCK__AG CYREG_PRT3_AG
-#define SD_SCK__AMUX CYREG_PRT3_AMUX
-#define SD_SCK__BIE CYREG_PRT3_BIE
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_SCK__BYP CYREG_PRT3_BYP
-#define SD_SCK__CTL CYREG_PRT3_CTL
-#define SD_SCK__DM0 CYREG_PRT3_DM0
-#define SD_SCK__DM1 CYREG_PRT3_DM1
-#define SD_SCK__DM2 CYREG_PRT3_DM2
-#define SD_SCK__DR CYREG_PRT3_DR
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_SCK__MASK 0x04u
-#define SD_SCK__PORT 3u
-#define SD_SCK__PRT CYREG_PRT3_PRT
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_SCK__PS CYREG_PRT3_PS
-#define SD_SCK__SHIFT 2
-#define SD_SCK__SLW CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RST_ISR__INTC_MASK 0x04u
+#define SCSI_RST_ISR__INTC_NUMBER 2u
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SD_CD */
-#define SD_CD__0__MASK 0x40u
-#define SD_CD__0__PC CYREG_PRT3_PC6
-#define SD_CD__0__PORT 3u
-#define SD_CD__0__SHIFT 6
-#define SD_CD__AG CYREG_PRT3_AG
-#define SD_CD__AMUX CYREG_PRT3_AMUX
-#define SD_CD__BIE CYREG_PRT3_BIE
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CD__BYP CYREG_PRT3_BYP
-#define SD_CD__CTL CYREG_PRT3_CTL
-#define SD_CD__DM0 CYREG_PRT3_DM0
-#define SD_CD__DM1 CYREG_PRT3_DM1
-#define SD_CD__DM2 CYREG_PRT3_DM2
-#define SD_CD__DR CYREG_PRT3_DR
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CD__MASK 0x40u
-#define SD_CD__PORT 3u
-#define SD_CD__PRT CYREG_PRT3_PRT
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CD__PS CYREG_PRT3_PS
-#define SD_CD__SHIFT 6
-#define SD_CD__SLW CYREG_PRT3_SLW
+/* SCSI_Filtered */
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Filtered_sts_sts_reg__0__POS 0
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
+#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
+#define SCSI_Filtered_sts_sts_reg__2__POS 2
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
+#define SCSI_Filtered_sts_sts_reg__3__POS 3
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
+#define SCSI_Filtered_sts_sts_reg__4__POS 4
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST
 
-/* SD_CS */
-#define SD_CS__0__MASK 0x10u
-#define SD_CS__0__PC CYREG_PRT3_PC4
-#define SD_CS__0__PORT 3u
-#define SD_CS__0__SHIFT 4
-#define SD_CS__AG CYREG_PRT3_AG
-#define SD_CS__AMUX CYREG_PRT3_AMUX
-#define SD_CS__BIE CYREG_PRT3_BIE
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CS__BYP CYREG_PRT3_BYP
-#define SD_CS__CTL CYREG_PRT3_CTL
-#define SD_CS__DM0 CYREG_PRT3_DM0
-#define SD_CS__DM1 CYREG_PRT3_DM1
-#define SD_CS__DM2 CYREG_PRT3_DM2
-#define SD_CS__DR CYREG_PRT3_DR
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CS__MASK 0x10u
-#define SD_CS__PORT 3u
-#define SD_CS__PRT CYREG_PRT3_PRT
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CS__PS CYREG_PRT3_PS
-#define SD_CS__SHIFT 4
-#define SD_CS__SLW CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
 
-/* LED1 */
-#define LED1__0__MASK 0x08u
-#define LED1__0__PC CYREG_PRT12_PC3
-#define LED1__0__PORT 12u
-#define LED1__0__SHIFT 3
-#define LED1__AG CYREG_PRT12_AG
-#define LED1__BIE CYREG_PRT12_BIE
-#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK
-#define LED1__BYP CYREG_PRT12_BYP
-#define LED1__DM0 CYREG_PRT12_DM0
-#define LED1__DM1 CYREG_PRT12_DM1
-#define LED1__DM2 CYREG_PRT12_DM2
-#define LED1__DR CYREG_PRT12_DR
-#define LED1__INP_DIS CYREG_PRT12_INP_DIS
-#define LED1__MASK 0x08u
-#define LED1__PORT 12u
-#define LED1__PRT CYREG_PRT12_PRT
-#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define LED1__PS CYREG_PRT12_PS
-#define LED1__SHIFT 3
-#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG
-#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define LED1__SLW CYREG_PRT12_SLW
+/* SCSI_Parity_Error */
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
-#define CYDEV_CHIP_MEMBER_5B 4u
-#define CYDEV_CHIP_FAMILY_PSOC5 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 4u
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
 #define BCLK__BUS_CLK__HZ 50000000U
 #define BCLK__BUS_CLK__KHZ 50000U
 #define BCLK__BUS_CLK__MHZ 50U
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CY_VERSION "PSoC Creator  3.1"
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 3u
-#define CYDEV_CHIP_DIE_PSOC4A 2u
+#define CYDEV_CHIP_DIE_PANTHER 6u
+#define CYDEV_CHIP_DIE_PSOC4A 3u
+#define CYDEV_CHIP_DIE_PSOC5LP 5u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
+#define CYDEV_CHIP_FAMILY_PSOC5 3u
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 2u
-#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_4A 3u
+#define CYDEV_CHIP_MEMBER_4D 2u
+#define CYDEV_CHIP_MEMBER_4F 4u
+#define CYDEV_CHIP_MEMBER_5A 6u
+#define CYDEV_CHIP_MEMBER_5B 5u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_3A_ES1 0u
 #define CYDEV_CHIP_REVISION_3A_ES2 1u
 #define CYDEV_CHIP_REVISION_3A_ES3 3u
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
 #define CYDEV_CHIP_REVISION_5B_ES0 0u
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
 #define CYDEV_CONFIGURATION_COMPRESSED 1
 #define CYDEV_CONFIGURATION_DMA 0
 #define CYDEV_CONFIGURATION_ECC 0
 #define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
 #define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
 #define CYDEV_CONFIGURATION_MODE_DMA 2
 #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DEBUGGING_DPS_Disable 3
 #define CYDEV_DEBUGGING_DPS_JTAG_4 1
 #define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
 #define CYDEV_DEBUGGING_ENABLE 1
 #define CYDEV_DEBUGGING_XRES 0
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DMA_CHANNELS_AVAILABLE 24u
 #define CYDEV_ECC_ENABLE 0
 #define CYDEV_HEAP_SIZE 0x0400
@@ -2985,7 +2991,7 @@
 #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
 #define CYDEV_PROJ_TYPE_STANDARD 0
 #define CYDEV_PROTECTION_ENABLE 0
-#define CYDEV_STACK_SIZE 0x2000
+#define CYDEV_STACK_SIZE 0x1000
 #define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
 #define CYDEV_USE_BUNDLED_CMSIS 1
 #define CYDEV_VARIABLE_VDDA 0
@@ -3001,14 +3007,34 @@
 #define CYDEV_VDDIO2_MV 5000
 #define CYDEV_VDDIO3 3.3
 #define CYDEV_VDDIO3_MV 3300
-#define CYDEV_VIO0 5
+#define CYDEV_VIO0 5.0
 #define CYDEV_VIO0_MV 5000
-#define CYDEV_VIO1 5
+#define CYDEV_VIO1 5.0
 #define CYDEV_VIO1_MV 5000
-#define CYDEV_VIO2 5
+#define CYDEV_VIO2 5.0
 #define CYDEV_VIO2_MV 5000
 #define CYDEV_VIO3 3.3
 #define CYDEV_VIO3_MV 3300
+#define CYIPBLOCK_ARM_CM3_VERSION 0
+#define CYIPBLOCK_P3_ANAIF_VERSION 0
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
+#define CYIPBLOCK_P3_COMP_VERSION 0
+#define CYIPBLOCK_P3_DMA_VERSION 0
+#define CYIPBLOCK_P3_DRQ_VERSION 0
+#define CYIPBLOCK_P3_EMIF_VERSION 0
+#define CYIPBLOCK_P3_I2C_VERSION 0
+#define CYIPBLOCK_P3_LCD_VERSION 0
+#define CYIPBLOCK_P3_LPF_VERSION 0
+#define CYIPBLOCK_P3_PM_VERSION 0
+#define CYIPBLOCK_P3_TIMER_VERSION 0
+#define CYIPBLOCK_P3_USB_VERSION 0
+#define CYIPBLOCK_P3_VIDAC_VERSION 0
+#define CYIPBLOCK_P3_VREF_VERSION 0
+#define CYIPBLOCK_S8_GPIO_VERSION 0
+#define CYIPBLOCK_S8_IRQ_VERSION 0
+#define CYIPBLOCK_S8_SAR_VERSION 0
+#define CYIPBLOCK_S8_SIO_VERSION 0
+#define CYIPBLOCK_S8_UDB_VERSION 0
 #define DMA_CHANNELS_USED__MASK0 0x0000000Fu
 #define CYDEV_BOOTLOADER_ENABLE 0
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 8463e7b6..f8cc0b1c 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator with device 
@@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode)
 }
 #endif
 
-#define CY_CFG_BASE_ADDR_COUNT 40u
+#define CY_CFG_BASE_ADDR_COUNT 41u
 CYPACKED typedef struct
 {
 	uint8 offset;
@@ -383,39 +383,40 @@ void cyfitter_cfg(void)
 			0x4000520Bu, /* Base address: 0x40005200 Count: 11 */
 			0x40006401u, /* Base address: 0x40006400 Count: 1 */
 			0x40006501u, /* Base address: 0x40006500 Count: 1 */
-			0x4001003Bu, /* Base address: 0x40010000 Count: 59 */
-			0x40010136u, /* Base address: 0x40010100 Count: 54 */
-			0x40010244u, /* Base address: 0x40010200 Count: 68 */
-			0x40010358u, /* Base address: 0x40010300 Count: 88 */
-			0x40010445u, /* Base address: 0x40010400 Count: 69 */
-			0x40010551u, /* Base address: 0x40010500 Count: 81 */
-			0x40010653u, /* Base address: 0x40010600 Count: 83 */
-			0x40010755u, /* Base address: 0x40010700 Count: 85 */
-			0x4001090Du, /* Base address: 0x40010900 Count: 13 */
-			0x40010A47u, /* Base address: 0x40010A00 Count: 71 */
-			0x40010B47u, /* Base address: 0x40010B00 Count: 71 */
-			0x40010C51u, /* Base address: 0x40010C00 Count: 81 */
-			0x40010D54u, /* Base address: 0x40010D00 Count: 84 */
-			0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */
-			0x40010F34u, /* Base address: 0x40010F00 Count: 52 */
-			0x4001141Eu, /* Base address: 0x40011400 Count: 30 */
-			0x40011555u, /* Base address: 0x40011500 Count: 85 */
-			0x40011655u, /* Base address: 0x40011600 Count: 85 */
-			0x40011746u, /* Base address: 0x40011700 Count: 70 */
-			0x40011907u, /* Base address: 0x40011900 Count: 7 */
-			0x40011B09u, /* Base address: 0x40011B00 Count: 9 */
-			0x40014018u, /* Base address: 0x40014000 Count: 24 */
-			0x40014122u, /* Base address: 0x40014100 Count: 34 */
-			0x40014209u, /* Base address: 0x40014200 Count: 9 */
-			0x4001430Bu, /* Base address: 0x40014300 Count: 11 */
-			0x4001440Fu, /* Base address: 0x40014400 Count: 15 */
-			0x4001451Cu, /* Base address: 0x40014500 Count: 28 */
+			0x4001004Eu, /* Base address: 0x40010000 Count: 78 */
+			0x40010137u, /* Base address: 0x40010100 Count: 55 */
+			0x4001024Du, /* Base address: 0x40010200 Count: 77 */
+			0x40010353u, /* Base address: 0x40010300 Count: 83 */
+			0x40010439u, /* Base address: 0x40010400 Count: 57 */
+			0x4001054Cu, /* Base address: 0x40010500 Count: 76 */
+			0x40010621u, /* Base address: 0x40010600 Count: 33 */
+			0x40010754u, /* Base address: 0x40010700 Count: 84 */
+			0x40010918u, /* Base address: 0x40010900 Count: 24 */
+			0x40010A42u, /* Base address: 0x40010A00 Count: 66 */
+			0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */
+			0x40010C43u, /* Base address: 0x40010C00 Count: 67 */
+			0x40010D53u, /* Base address: 0x40010D00 Count: 83 */
+			0x40010E55u, /* Base address: 0x40010E00 Count: 85 */
+			0x40010F35u, /* Base address: 0x40010F00 Count: 53 */
+			0x40011451u, /* Base address: 0x40011400 Count: 81 */
+			0x4001154Bu, /* Base address: 0x40011500 Count: 75 */
+			0x4001164Cu, /* Base address: 0x40011600 Count: 76 */
+			0x40011750u, /* Base address: 0x40011700 Count: 80 */
+			0x40011804u, /* Base address: 0x40011800 Count: 4 */
+			0x40011910u, /* Base address: 0x40011900 Count: 16 */
+			0x40011B07u, /* Base address: 0x40011B00 Count: 7 */
+			0x40014016u, /* Base address: 0x40014000 Count: 22 */
+			0x4001411Cu, /* Base address: 0x40014100 Count: 28 */
+			0x4001420Cu, /* Base address: 0x40014200 Count: 12 */
+			0x4001430Du, /* Base address: 0x40014300 Count: 13 */
+			0x40014411u, /* Base address: 0x40014400 Count: 17 */
+			0x4001451Au, /* Base address: 0x40014500 Count: 26 */
 			0x4001460Eu, /* Base address: 0x40014600 Count: 14 */
-			0x4001470Cu, /* Base address: 0x40014700 Count: 12 */
-			0x40014806u, /* Base address: 0x40014800 Count: 6 */
-			0x4001490Bu, /* Base address: 0x40014900 Count: 11 */
+			0x4001470Bu, /* Base address: 0x40014700 Count: 11 */
+			0x4001480Bu, /* Base address: 0x40014800 Count: 11 */
+			0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
 			0x40014C05u, /* Base address: 0x40014C00 Count: 5 */
-			0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */
+			0x40014D03u, /* Base address: 0x40014D00 Count: 3 */
 			0x40015002u, /* Base address: 0x40015000 Count: 2 */
 			0x40015104u, /* Base address: 0x40015100 Count: 4 */
 		};
@@ -423,836 +424,791 @@ void cyfitter_cfg(void)
 		static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
 			{0x7Eu, 0x02u},
 			{0x01u, 0x20u},
-			{0x0Au, 0x4Bu},
-			{0x00u, 0x11u},
-			{0x01u, 0x02u},
-			{0x18u, 0x04u},
+			{0x0Au, 0x36u},
+			{0x00u, 0x12u},
+			{0x01u, 0x04u},
+			{0x19u, 0x04u},
 			{0x1Cu, 0x71u},
 			{0x20u, 0x58u},
-			{0x21u, 0xC8u},
+			{0x21u, 0x98u},
 			{0x2Cu, 0x0Eu},
-			{0x30u, 0x05u},
-			{0x31u, 0x06u},
+			{0x30u, 0x0Au},
+			{0x31u, 0x0Cu},
 			{0x34u, 0x80u},
 			{0x7Cu, 0x40u},
-			{0x21u, 0x02u},
-			{0x84u, 0x0Fu},
-			{0x00u, 0x01u},
-			{0x10u, 0x04u},
-			{0x11u, 0x01u},
-			{0x19u, 0x02u},
-			{0x28u, 0x02u},
-			{0x30u, 0x04u},
-			{0x31u, 0x02u},
-			{0x33u, 0x01u},
-			{0x34u, 0x01u},
-			{0x36u, 0x02u},
-			{0x3Eu, 0x51u},
-			{0x3Fu, 0x05u},
+			{0x25u, 0x02u},
+			{0x87u, 0x0Fu},
+			{0x01u, 0x30u},
+			{0x02u, 0x08u},
+			{0x03u, 0xC0u},
+			{0x05u, 0x06u},
+			{0x07u, 0x09u},
+			{0x09u, 0x0Fu},
+			{0x0Bu, 0xF0u},
+			{0x11u, 0x05u},
+			{0x12u, 0x80u},
+			{0x13u, 0x0Au},
+			{0x16u, 0x17u},
+			{0x19u, 0x03u},
+			{0x1Au, 0x40u},
+			{0x1Bu, 0x0Cu},
+			{0x1Eu, 0x20u},
+			{0x20u, 0x0Au},
+			{0x22u, 0x05u},
+			{0x24u, 0x50u},
+			{0x25u, 0x50u},
+			{0x26u, 0xA0u},
+			{0x27u, 0xA0u},
+			{0x28u, 0x09u},
+			{0x2Au, 0x02u},
+			{0x2Cu, 0x04u},
+			{0x2Du, 0x60u},
+			{0x2Eu, 0x08u},
+			{0x2Fu, 0x90u},
+			{0x32u, 0x0Fu},
+			{0x34u, 0xC0u},
+			{0x36u, 0x30u},
+			{0x37u, 0xFFu},
+			{0x3Eu, 0x50u},
+			{0x3Fu, 0x40u},
 			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
+			{0x5Cu, 0x01u},
 			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x81u, 0x04u},
-			{0x83u, 0x10u},
-			{0x8Bu, 0x1Cu},
-			{0x8Fu, 0x08u},
-			{0x91u, 0x04u},
-			{0x93u, 0x08u},
-			{0x99u, 0x18u},
-			{0x9Bu, 0x04u},
-			{0x9Cu, 0x01u},
-			{0xA9u, 0x01u},
-			{0xADu, 0x02u},
-			{0xB0u, 0x01u},
-			{0xB1u, 0x1Cu},
-			{0xB3u, 0x02u},
-			{0xB5u, 0x01u},
-			{0xBEu, 0x01u},
-			{0xBFu, 0x14u},
-			{0xC0u, 0x53u},
-			{0xC1u, 0x04u},
-			{0xC2u, 0x20u},
-			{0xC5u, 0xECu},
-			{0xC6u, 0xD2u},
-			{0xC7u, 0xF0u},
-			{0xC8u, 0x2Fu},
-			{0xC9u, 0xFFu},
-			{0xCAu, 0xFFu},
-			{0xCBu, 0xFFu},
-			{0xCFu, 0x2Cu},
-			{0xD6u, 0x01u},
+			{0x81u, 0x0Fu},
+			{0x82u, 0x70u},
+			{0x83u, 0xF0u},
+			{0x84u, 0x90u},
+			{0x86u, 0x2Fu},
+			{0x87u, 0xFFu},
+			{0x8Bu, 0xFFu},
+			{0x8Cu, 0xC0u},
+			{0x8Du, 0x55u},
+			{0x8Eu, 0x1Fu},
+			{0x8Fu, 0xAAu},
+			{0x91u, 0xFFu},
+			{0x92u, 0x80u},
+			{0x94u, 0x06u},
+			{0x95u, 0xFFu},
+			{0x96u, 0x09u},
+			{0x9Cu, 0x05u},
+			{0x9Eu, 0x0Au},
+			{0x9Fu, 0xFFu},
+			{0xA0u, 0xA0u},
+			{0xA2u, 0x4Fu},
+			{0xA6u, 0x80u},
+			{0xA8u, 0x0Fu},
+			{0xA9u, 0x69u},
+			{0xABu, 0x96u},
+			{0xACu, 0x03u},
+			{0xADu, 0x33u},
+			{0xAEu, 0x0Cu},
+			{0xAFu, 0xCCu},
+			{0xB0u, 0x7Fu},
+			{0xB1u, 0xFFu},
+			{0xB2u, 0x80u},
+			{0xBBu, 0x02u},
+			{0xBEu, 0x04u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
-			{0xDAu, 0x04u},
-			{0xDBu, 0x04u},
-			{0xDCu, 0x10u},
-			{0xDDu, 0x01u},
+			{0xDCu, 0x11u},
 			{0xDFu, 0x01u},
-			{0xE2u, 0xC0u},
-			{0xE6u, 0x80u},
-			{0xE8u, 0x40u},
-			{0xE9u, 0x40u},
-			{0xEEu, 0x08u},
-			{0x00u, 0x01u},
+			{0x00u, 0x02u},
+			{0x05u, 0x41u},
+			{0x07u, 0x20u},
 			{0x08u, 0x02u},
-			{0x0Fu, 0x02u},
-			{0x12u, 0x04u},
-			{0x19u, 0x62u},
-			{0x1Eu, 0x80u},
-			{0x23u, 0x50u},
+			{0x09u, 0x40u},
+			{0x0Au, 0x24u},
+			{0x0Bu, 0x05u},
+			{0x0Du, 0x04u},
+			{0x0Eu, 0x01u},
+			{0x0Fu, 0x80u},
+			{0x10u, 0x01u},
+			{0x11u, 0x28u},
+			{0x13u, 0x02u},
+			{0x16u, 0x08u},
+			{0x17u, 0x4Au},
+			{0x18u, 0x08u},
+			{0x1Au, 0x22u},
+			{0x1Du, 0x01u},
+			{0x1Eu, 0x50u},
+			{0x21u, 0x80u},
 			{0x25u, 0x01u},
-			{0x26u, 0x16u},
 			{0x27u, 0x40u},
-			{0x2Fu, 0x05u},
-			{0x31u, 0x11u},
-			{0x37u, 0x11u},
-			{0x38u, 0xC0u},
-			{0x3Du, 0x02u},
-			{0x3Eu, 0xA0u},
-			{0x45u, 0x28u},
-			{0x47u, 0x01u},
-			{0x4Cu, 0x40u},
-			{0x4Du, 0x08u},
-			{0x4Eu, 0x02u},
-			{0x54u, 0x01u},
-			{0x56u, 0x80u},
-			{0x57u, 0x22u},
-			{0x58u, 0x40u},
-			{0x5Du, 0x02u},
-			{0x5Eu, 0xA8u},
-			{0x63u, 0x02u},
-			{0x65u, 0x60u},
-			{0x67u, 0x50u},
-			{0x68u, 0x02u},
-			{0x6Au, 0x24u},
-			{0x6Du, 0x19u},
-			{0x6Eu, 0x40u},
-			{0x75u, 0x80u},
-			{0x76u, 0x58u},
-			{0x82u, 0x02u},
-			{0x85u, 0x04u},
-			{0x86u, 0x04u},
-			{0x88u, 0x02u},
-			{0x8Cu, 0x40u},
-			{0xC0u, 0x08u},
-			{0xC2u, 0x88u},
-			{0xC4u, 0x02u},
-			{0xCAu, 0x30u},
-			{0xCCu, 0xA5u},
-			{0xCEu, 0xB0u},
-			{0xD0u, 0xE0u},
-			{0xD2u, 0x10u},
-			{0xD6u, 0xF8u},
-			{0xD8u, 0xF8u},
-			{0xE0u, 0x01u},
-			{0xE4u, 0x02u},
-			{0xE6u, 0x90u},
-			{0x03u, 0x2Cu},
-			{0x04u, 0xC0u},
-			{0x05u, 0x10u},
-			{0x07u, 0x01u},
-			{0x08u, 0x23u},
-			{0x0Au, 0x44u},
-			{0x0Bu, 0x7Fu},
-			{0x0Cu, 0x1Au},
-			{0x0Du, 0x08u},
-			{0x0Fu, 0x03u},
-			{0x10u, 0x04u},
-			{0x11u, 0x37u},
-			{0x12u, 0x1Au},
-			{0x13u, 0x40u},
-			{0x14u, 0x1Au},
-			{0x15u, 0x03u},
-			{0x18u, 0x1Au},
-			{0x19u, 0x4Fu},
-			{0x1Bu, 0x30u},
-			{0x1Cu, 0x1Au},
-			{0x24u, 0x25u},
-			{0x25u, 0x02u},
-			{0x26u, 0x88u},
-			{0x28u, 0x45u},
-			{0x2Au, 0x30u},
-			{0x2Cu, 0x1Au},
-			{0x30u, 0x1Eu},
-			{0x32u, 0xE0u},
-			{0x33u, 0x0Fu},
-			{0x36u, 0x01u},
-			{0x37u, 0x70u},
-			{0x38u, 0x08u},
-			{0x3Au, 0x02u},
-			{0x3Eu, 0x40u},
+			{0x28u, 0x02u},
+			{0x2Bu, 0x10u},
+			{0x2Du, 0x20u},
+			{0x2Eu, 0x80u},
+			{0x32u, 0x12u},
+			{0x35u, 0x40u},
+			{0x37u, 0x0Au},
+			{0x38u, 0x20u},
+			{0x3Bu, 0x05u},
+			{0x3Du, 0x22u},
+			{0x3Fu, 0x48u},
+			{0x58u, 0x04u},
+			{0x59u, 0x10u},
+			{0x5Au, 0x80u},
+			{0x61u, 0x08u},
+			{0x62u, 0x50u},
+			{0x81u, 0x90u},
+			{0x85u, 0x40u},
+			{0x86u, 0x40u},
+			{0x88u, 0x10u},
+			{0x8Eu, 0x40u},
+			{0xC0u, 0xB8u},
+			{0xC2u, 0xBFu},
+			{0xC4u, 0xFFu},
+			{0xCAu, 0x3Au},
+			{0xCCu, 0xD5u},
+			{0xCEu, 0xF7u},
+			{0xD6u, 0x0Eu},
+			{0xD8u, 0x0Eu},
+			{0xE0u, 0x08u},
+			{0xE2u, 0x02u},
+			{0xE4u, 0x01u},
+			{0xE6u, 0xC4u},
+			{0x01u, 0x02u},
+			{0x02u, 0x07u},
+			{0x07u, 0x20u},
+			{0x09u, 0x57u},
+			{0x0Bu, 0xA0u},
+			{0x0Cu, 0x06u},
+			{0x0Du, 0x03u},
+			{0x0Eu, 0x01u},
+			{0x11u, 0x6Fu},
+			{0x13u, 0x90u},
+			{0x15u, 0x08u},
+			{0x17u, 0x03u},
+			{0x19u, 0x30u},
+			{0x1Au, 0x02u},
+			{0x1Bu, 0xC0u},
+			{0x1Cu, 0x01u},
+			{0x1Du, 0x70u},
+			{0x1Eu, 0x04u},
+			{0x1Fu, 0x8Cu},
+			{0x20u, 0x10u},
+			{0x23u, 0x3Fu},
+			{0x24u, 0x08u},
+			{0x25u, 0x10u},
+			{0x27u, 0x01u},
+			{0x28u, 0x01u},
+			{0x2Au, 0x02u},
+			{0x30u, 0x10u},
+			{0x32u, 0x08u},
+			{0x33u, 0xF0u},
+			{0x36u, 0x07u},
+			{0x37u, 0x0Fu},
+			{0x3Bu, 0x08u},
+			{0x3Eu, 0x05u},
 			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
-			{0x5Cu, 0x10u},
+			{0x5Cu, 0x11u},
 			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x81u, 0x01u},
-			{0x85u, 0x01u},
+			{0x80u, 0x01u},
+			{0x81u, 0x02u},
+			{0x82u, 0x02u},
+			{0x83u, 0x01u},
+			{0x85u, 0x02u},
+			{0x87u, 0x01u},
 			{0x89u, 0x02u},
-			{0x8Au, 0x04u},
-			{0x8Bu, 0x04u},
-			{0x8Eu, 0x01u},
-			{0x94u, 0x05u},
-			{0x96u, 0x0Au},
-			{0x97u, 0x04u},
-			{0x9Au, 0x08u},
+			{0x8Bu, 0x05u},
+			{0x90u, 0x02u},
+			{0x92u, 0x01u},
+			{0x94u, 0x02u},
+			{0x96u, 0x09u},
+			{0x97u, 0x08u},
+			{0x98u, 0x02u},
+			{0x99u, 0x01u},
+			{0x9Au, 0x01u},
 			{0x9Bu, 0x02u},
-			{0xA1u, 0x01u},
-			{0xA5u, 0x01u},
-			{0xAEu, 0x02u},
-			{0xB2u, 0x0Cu},
-			{0xB4u, 0x03u},
-			{0xB5u, 0x06u},
-			{0xB7u, 0x01u},
-			{0xB9u, 0x80u},
-			{0xBEu, 0x14u},
-			{0xBFu, 0x50u},
+			{0x9Cu, 0x02u},
+			{0x9Eu, 0x05u},
+			{0xA1u, 0x02u},
+			{0xA3u, 0x11u},
+			{0xB0u, 0x03u},
+			{0xB1u, 0x04u},
+			{0xB3u, 0x10u},
+			{0xB4u, 0x04u},
+			{0xB5u, 0x03u},
+			{0xB6u, 0x08u},
+			{0xB7u, 0x08u},
+			{0xBAu, 0x02u},
+			{0xBBu, 0x20u},
 			{0xD6u, 0x08u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDBu, 0x04u},
+			{0xDCu, 0x99u},
 			{0xDDu, 0x90u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x80u},
-			{0x03u, 0x04u},
-			{0x04u, 0x20u},
-			{0x05u, 0x04u},
-			{0x06u, 0x02u},
-			{0x0Bu, 0x14u},
-			{0x0Cu, 0x90u},
-			{0x0Du, 0x04u},
-			{0x0Eu, 0x80u},
-			{0x13u, 0x40u},
-			{0x14u, 0x04u},
-			{0x15u, 0x40u},
-			{0x17u, 0x08u},
-			{0x1Au, 0x08u},
-			{0x1Bu, 0x08u},
-			{0x1Du, 0x84u},
-			{0x1Eu, 0xA0u},
-			{0x21u, 0x50u},
-			{0x25u, 0x48u},
-			{0x27u, 0x11u},
-			{0x2Bu, 0x90u},
-			{0x2Fu, 0x20u},
-			{0x30u, 0x08u},
-			{0x32u, 0x10u},
-			{0x35u, 0x08u},
-			{0x37u, 0x11u},
+			{0x01u, 0x02u},
+			{0x04u, 0x02u},
+			{0x07u, 0x02u},
+			{0x09u, 0x08u},
+			{0x0Au, 0x8Au},
+			{0x0Du, 0x80u},
+			{0x0Fu, 0x08u},
+			{0x16u, 0x50u},
+			{0x17u, 0x20u},
+			{0x19u, 0x02u},
+			{0x1Au, 0x0Au},
+			{0x1Du, 0xC4u},
+			{0x1Fu, 0x01u},
+			{0x21u, 0x01u},
+			{0x22u, 0x70u},
+			{0x23u, 0x18u},
+			{0x27u, 0x12u},
+			{0x28u, 0x40u},
+			{0x2Eu, 0x08u},
+			{0x2Fu, 0x80u},
+			{0x32u, 0x14u},
+			{0x35u, 0x40u},
+			{0x37u, 0x1Au},
 			{0x38u, 0x08u},
 			{0x39u, 0x02u},
 			{0x3Bu, 0x10u},
-			{0x3Du, 0x02u},
-			{0x3Eu, 0x24u},
-			{0x3Fu, 0x80u},
-			{0x58u, 0x08u},
-			{0x59u, 0x22u},
-			{0x5Au, 0x80u},
-			{0x5Fu, 0xA0u},
-			{0x60u, 0x12u},
-			{0x61u, 0x11u},
-			{0x62u, 0x04u},
-			{0x67u, 0x0Au},
-			{0x81u, 0x20u},
-			{0x83u, 0x80u},
-			{0x85u, 0x10u},
-			{0x88u, 0x0Au},
-			{0x8Bu, 0x80u},
-			{0x8Cu, 0x10u},
-			{0x8Du, 0x19u},
-			{0x90u, 0x48u},
-			{0x91u, 0x13u},
-			{0x92u, 0x44u},
-			{0x94u, 0x01u},
-			{0x95u, 0x84u},
-			{0x96u, 0x08u},
-			{0x97u, 0x0Au},
-			{0x99u, 0x88u},
-			{0x9Au, 0xD8u},
-			{0x9Bu, 0x40u},
-			{0x9Cu, 0x02u},
-			{0x9Du, 0x11u},
-			{0x9Eu, 0x24u},
-			{0x9Fu, 0x11u},
-			{0xA0u, 0x01u},
-			{0xA1u, 0x15u},
-			{0xA3u, 0x21u},
-			{0xA5u, 0x28u},
-			{0xA7u, 0x08u},
-			{0xA8u, 0x04u},
-			{0xA9u, 0x10u},
-			{0xAAu, 0x10u},
-			{0xADu, 0x01u},
-			{0xAEu, 0x04u},
-			{0xB0u, 0x40u},
-			{0xB3u, 0x08u},
-			{0xB5u, 0x40u},
-			{0xB7u, 0x02u},
-			{0xC0u, 0xE3u},
-			{0xC2u, 0xF6u},
-			{0xC4u, 0xE1u},
-			{0xCAu, 0x43u},
-			{0xCCu, 0xE6u},
+			{0x3Du, 0x21u},
+			{0x3Fu, 0x88u},
+			{0x44u, 0x01u},
+			{0x45u, 0x80u},
+			{0x58u, 0x24u},
+			{0x5Au, 0x01u},
+			{0x5Bu, 0x80u},
+			{0x5Du, 0x80u},
+			{0x5Eu, 0x20u},
+			{0x60u, 0x08u},
+			{0x62u, 0x89u},
+			{0x63u, 0x40u},
+			{0x65u, 0x20u},
+			{0x66u, 0x80u},
+			{0x80u, 0x04u},
+			{0x82u, 0x10u},
+			{0x84u, 0x04u},
+			{0x86u, 0x19u},
+			{0x89u, 0x02u},
+			{0x8Au, 0x08u},
+			{0x8Cu, 0x08u},
+			{0x8Fu, 0x98u},
+			{0x90u, 0x02u},
+			{0x92u, 0x50u},
+			{0x95u, 0x08u},
+			{0x96u, 0x04u},
+			{0x97u, 0x40u},
+			{0x9Au, 0x50u},
+			{0x9Cu, 0x03u},
+			{0x9Du, 0x60u},
+			{0x9Eu, 0x88u},
+			{0x9Fu, 0x2Au},
+			{0xA1u, 0x08u},
+			{0xA3u, 0x80u},
+			{0xA4u, 0x11u},
+			{0xA5u, 0x10u},
+			{0xA6u, 0x02u},
+			{0xA7u, 0x50u},
+			{0xA8u, 0x15u},
+			{0xA9u, 0x04u},
+			{0xABu, 0x84u},
+			{0xAEu, 0x01u},
+			{0xB0u, 0x04u},
+			{0xB2u, 0x11u},
+			{0xC0u, 0x98u},
+			{0xC2u, 0xCFu},
+			{0xC4u, 0x70u},
+			{0xCAu, 0xC1u},
+			{0xCCu, 0xF6u},
 			{0xCEu, 0xF7u},
 			{0xD6u, 0x3Fu},
 			{0xD8u, 0x3Fu},
-			{0xE2u, 0x08u},
-			{0xE6u, 0x0Fu},
-			{0xE8u, 0x02u},
-			{0xEAu, 0x21u},
-			{0xEEu, 0x53u},
-			{0x03u, 0x70u},
-			{0x04u, 0x05u},
-			{0x06u, 0x0Au},
-			{0x08u, 0x06u},
-			{0x0Au, 0x09u},
-			{0x0Bu, 0x08u},
-			{0x0Cu, 0x03u},
-			{0x0Eu, 0x0Cu},
-			{0x0Fu, 0x80u},
-			{0x10u, 0x30u},
-			{0x11u, 0x99u},
-			{0x12u, 0xC0u},
-			{0x13u, 0x22u},
-			{0x14u, 0x0Fu},
-			{0x15u, 0xAAu},
-			{0x16u, 0xF0u},
-			{0x17u, 0x55u},
-			{0x18u, 0x60u},
-			{0x1Au, 0x90u},
-			{0x1Bu, 0x07u},
-			{0x1Du, 0x44u},
-			{0x1Fu, 0x88u},
-			{0x28u, 0x50u},
-			{0x2Au, 0xA0u},
-			{0x31u, 0xF0u},
-			{0x35u, 0x0Fu},
-			{0x36u, 0xFFu},
-			{0x3Eu, 0x40u},
-			{0x56u, 0x08u},
-			{0x58u, 0x04u},
-			{0x59u, 0x04u},
-			{0x5Bu, 0x04u},
-			{0x5Cu, 0x10u},
-			{0x5Du, 0x90u},
-			{0x5Fu, 0x01u},
-			{0x80u, 0x3Au},
-			{0x81u, 0x44u},
-			{0x82u, 0x45u},
-			{0x83u, 0x88u},
-			{0x86u, 0x19u},
-			{0x87u, 0x80u},
-			{0x88u, 0x01u},
-			{0x8Au, 0x06u},
-			{0x8Cu, 0x2Au},
-			{0x8Du, 0x99u},
-			{0x8Eu, 0x55u},
-			{0x8Fu, 0x22u},
-			{0x90u, 0x01u},
-			{0x97u, 0x70u},
-			{0x98u, 0x08u},
-			{0x99u, 0xAAu},
-			{0x9Bu, 0x55u},
-			{0x9Cu, 0x18u},
-			{0x9Eu, 0x60u},
-			{0x9Fu, 0x07u},
-			{0xA2u, 0x10u},
-			{0xA3u, 0x08u},
-			{0xA8u, 0x33u},
-			{0xAAu, 0x4Cu},
-			{0xB4u, 0x07u},
-			{0xB5u, 0xF0u},
-			{0xB6u, 0x78u},
-			{0xB7u, 0x0Fu},
-			{0xBAu, 0xA0u},
-			{0xD8u, 0x04u},
-			{0xD9u, 0x04u},
-			{0xDBu, 0x04u},
-			{0xDCu, 0x11u},
-			{0xDFu, 0x01u},
-			{0x00u, 0x84u},
-			{0x03u, 0x04u},
-			{0x05u, 0x10u},
-			{0x06u, 0x20u},
-			{0x07u, 0x41u},
-			{0x0Bu, 0x54u},
-			{0x0Eu, 0x06u},
-			{0x0Fu, 0x80u},
-			{0x10u, 0x08u},
-			{0x16u, 0x80u},
-			{0x17u, 0x10u},
-			{0x1Au, 0x02u},
-			{0x1Du, 0x30u},
-			{0x1Eu, 0x02u},
-			{0x20u, 0x84u},
-			{0x21u, 0x01u},
-			{0x22u, 0x10u},
-			{0x24u, 0x02u},
-			{0x26u, 0x80u},
-			{0x27u, 0x04u},
-			{0x2Du, 0x01u},
-			{0x31u, 0x08u},
-			{0x32u, 0x10u},
-			{0x33u, 0x41u},
-			{0x36u, 0x80u},
-			{0x37u, 0x14u},
-			{0x39u, 0x02u},
-			{0x3Au, 0x50u},
-			{0x3Du, 0x82u},
-			{0x3Eu, 0x08u},
-			{0x58u, 0x80u},
-			{0x5Cu, 0x60u},
-			{0x5Du, 0x0Au},
-			{0x60u, 0x01u},
-			{0x64u, 0x01u},
-			{0x68u, 0x04u},
-			{0x69u, 0x84u},
-			{0x6Au, 0x81u},
-			{0x70u, 0x08u},
-			{0x73u, 0x45u},
-			{0x88u, 0xA1u},
-			{0x8Eu, 0x40u},
-			{0x90u, 0x40u},
-			{0x91u, 0x11u},
-			{0x92u, 0x44u},
-			{0x93u, 0x0Au},
-			{0x94u, 0x21u},
-			{0x95u, 0x4Cu},
-			{0x96u, 0x20u},
-			{0x97u, 0x54u},
-			{0x99u, 0x88u},
-			{0x9Au, 0xD8u},
-			{0x9Bu, 0x51u},
-			{0x9Cu, 0x14u},
-			{0x9Eu, 0x22u},
-			{0x9Fu, 0x0Cu},
-			{0xA0u, 0x01u},
-			{0xA1u, 0xDDu},
-			{0xA2u, 0x18u},
-			{0xA3u, 0x63u},
-			{0xA4u, 0xC8u},
-			{0xA5u, 0x20u},
-			{0xA7u, 0x10u},
-			{0xA8u, 0x01u},
-			{0xA9u, 0x02u},
-			{0xABu, 0x02u},
-			{0xAEu, 0x08u},
-			{0xB3u, 0x01u},
-			{0xB6u, 0x40u},
-			{0xB7u, 0x60u},
-			{0xC0u, 0xF7u},
-			{0xC2u, 0xDEu},
-			{0xC4u, 0x52u},
-			{0xCAu, 0x80u},
-			{0xCCu, 0x7Fu},
-			{0xCEu, 0xDDu},
-			{0xD6u, 0xF8u},
-			{0xD8u, 0x18u},
-			{0xE8u, 0x01u},
-			{0xEAu, 0x0Cu},
+			{0xE2u, 0x38u},
+			{0xE4u, 0x04u},
+			{0xE6u, 0x4Bu},
+			{0xEAu, 0x2Cu},
 			{0xEEu, 0x04u},
-			{0x01u, 0x33u},
-			{0x03u, 0xCCu},
-			{0x06u, 0x12u},
-			{0x08u, 0x88u},
-			{0x0Au, 0x03u},
-			{0x0Bu, 0xFFu},
-			{0x0Eu, 0x01u},
-			{0x0Fu, 0xFFu},
-			{0x14u, 0xE0u},
-			{0x15u, 0xFFu},
-			{0x18u, 0x21u},
-			{0x19u, 0xFFu},
-			{0x1Au, 0x02u},
-			{0x1Du, 0x0Fu},
-			{0x1Eu, 0xECu},
-			{0x1Fu, 0xF0u},
-			{0x23u, 0xFFu},
-			{0x24u, 0x04u},
-			{0x26u, 0x43u},
-			{0x29u, 0x55u},
-			{0x2Bu, 0xAAu},
-			{0x2Du, 0x69u},
-			{0x2Fu, 0x96u},
-			{0x30u, 0x10u},
-			{0x34u, 0xE0u},
-			{0x36u, 0x0Fu},
-			{0x37u, 0xFFu},
+			{0x00u, 0x02u},
+			{0x01u, 0x02u},
+			{0x03u, 0x0Du},
+			{0x05u, 0x0Du},
+			{0x0Bu, 0x10u},
+			{0x0Du, 0x0Du},
+			{0x11u, 0x02u},
+			{0x13u, 0x54u},
+			{0x15u, 0x0Du},
+			{0x19u, 0x01u},
+			{0x1Bu, 0x32u},
+			{0x1Du, 0x0Du},
+			{0x21u, 0x0Du},
+			{0x25u, 0x62u},
+			{0x27u, 0x08u},
+			{0x28u, 0x01u},
+			{0x29u, 0x80u},
+			{0x30u, 0x01u},
+			{0x33u, 0x70u},
+			{0x35u, 0x80u},
+			{0x36u, 0x02u},
+			{0x37u, 0x0Fu},
 			{0x3Bu, 0x80u},
-			{0x3Eu, 0x10u},
-			{0x54u, 0x01u},
+			{0x3Eu, 0x41u},
+			{0x3Fu, 0x10u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
-			{0x5Bu, 0x04u},
-			{0x5Cu, 0x10u},
-			{0x5Du, 0x10u},
 			{0x5Fu, 0x01u},
-			{0x80u, 0x03u},
-			{0x81u, 0x22u},
-			{0x82u, 0x0Cu},
-			{0x83u, 0x10u},
-			{0x84u, 0x20u},
-			{0x85u, 0x29u},
-			{0x86u, 0x4Fu},
-			{0x87u, 0x16u},
-			{0x89u, 0x17u},
-			{0x8Au, 0x70u},
-			{0x8Bu, 0x28u},
-			{0x8Cu, 0x05u},
-			{0x8Du, 0x06u},
-			{0x8Eu, 0x0Au},
-			{0x8Fu, 0x50u},
-			{0x95u, 0x52u},
-			{0x97u, 0x04u},
-			{0x98u, 0x0Fu},
-			{0x99u, 0x50u},
-			{0x9Bu, 0x06u},
-			{0x9Cu, 0x10u},
-			{0x9Du, 0x56u},
-			{0x9Eu, 0x2Fu},
-			{0xA0u, 0x40u},
-			{0xA1u, 0x56u},
-			{0xA2u, 0x1Fu},
-			{0xA5u, 0x04u},
-			{0xA8u, 0x06u},
-			{0xA9u, 0x31u},
-			{0xAAu, 0x09u},
-			{0xABu, 0x0Eu},
-			{0xAFu, 0x40u},
-			{0xB1u, 0x30u},
-			{0xB2u, 0x7Fu},
-			{0xB3u, 0x40u},
-			{0xB5u, 0x0Fu},
-			{0xB7u, 0x08u},
-			{0xB9u, 0x20u},
-			{0xBBu, 0x02u},
-			{0xBFu, 0x44u},
-			{0xD4u, 0x09u},
-			{0xD6u, 0x04u},
+			{0x80u, 0x02u},
+			{0x88u, 0x04u},
+			{0xACu, 0x01u},
+			{0xB0u, 0x02u},
+			{0xB2u, 0x01u},
+			{0xB4u, 0x04u},
+			{0xBEu, 0x15u},
+			{0xC0u, 0x14u},
+			{0xC1u, 0x02u},
+			{0xC2u, 0x30u},
+			{0xC5u, 0xD2u},
+			{0xC6u, 0xECu},
+			{0xC7u, 0x0Fu},
+			{0xC8u, 0x1Fu},
+			{0xC9u, 0xFFu},
+			{0xCAu, 0xFFu},
+			{0xCBu, 0xFFu},
+			{0xCFu, 0x2Cu},
+			{0xD6u, 0x01u},
 			{0xD8u, 0x04u},
-			{0xD9u, 0x04u},
+			{0xDAu, 0x04u},
 			{0xDBu, 0x04u},
-			{0xDCu, 0x01u},
+			{0xDDu, 0x01u},
 			{0xDFu, 0x01u},
+			{0xE2u, 0xC0u},
+			{0xE6u, 0x80u},
+			{0xE8u, 0x40u},
+			{0xE9u, 0x40u},
+			{0xEEu, 0x08u},
 			{0x02u, 0x80u},
-			{0x03u, 0x1Au},
-			{0x04u, 0x40u},
-			{0x05u, 0x18u},
-			{0x09u, 0x40u},
-			{0x0Au, 0x04u},
-			{0x0Bu, 0x04u},
-			{0x0Eu, 0x22u},
-			{0x0Fu, 0x08u},
-			{0x11u, 0x23u},
-			{0x15u, 0x80u},
+			{0x05u, 0x20u},
+			{0x06u, 0x80u},
+			{0x12u, 0x08u},
 			{0x16u, 0x01u},
-			{0x17u, 0x08u},
-			{0x1Bu, 0x08u},
+			{0x19u, 0x01u},
+			{0x1Au, 0x01u},
 			{0x1Cu, 0x40u},
-			{0x1Eu, 0x02u},
-			{0x1Fu, 0x10u},
-			{0x20u, 0x04u},
-			{0x21u, 0x09u},
-			{0x22u, 0x42u},
-			{0x23u, 0x08u},
-			{0x26u, 0x80u},
-			{0x28u, 0x24u},
-			{0x29u, 0x10u},
-			{0x2Au, 0x46u},
-			{0x2Du, 0x01u},
-			{0x2Fu, 0x05u},
-			{0x30u, 0x90u},
-			{0x32u, 0x14u},
+			{0x1Eu, 0x28u},
+			{0x20u, 0x11u},
+			{0x23u, 0x04u},
+			{0x28u, 0x28u},
+			{0x2Au, 0x02u},
+			{0x30u, 0x08u},
+			{0x31u, 0x10u},
+			{0x32u, 0x01u},
 			{0x33u, 0x40u},
-			{0x36u, 0x88u},
-			{0x37u, 0x10u},
-			{0x38u, 0x24u},
-			{0x39u, 0x42u},
-			{0x3Du, 0x80u},
-			{0x3Eu, 0x20u},
-			{0x3Fu, 0x02u},
-			{0x58u, 0x28u},
-			{0x59u, 0x01u},
-			{0x5Au, 0x80u},
-			{0x5Fu, 0x40u},
-			{0x61u, 0x80u},
-			{0x63u, 0x80u},
-			{0x83u, 0x40u},
-			{0x87u, 0x10u},
-			{0x8Bu, 0x48u},
-			{0x90u, 0x02u},
-			{0x91u, 0x94u},
-			{0x92u, 0x47u},
-			{0x93u, 0x0Bu},
-			{0x94u, 0x20u},
-			{0x95u, 0x48u},
-			{0x97u, 0x10u},
-			{0x99u, 0x80u},
-			{0x9Au, 0x20u},
-			{0x9Bu, 0x10u},
-			{0x9Cu, 0x14u},
-			{0x9Eu, 0x02u},
-			{0x9Fu, 0x08u},
-			{0xA0u, 0x04u},
-			{0xA1u, 0xD5u},
-			{0xA2u, 0x18u},
-			{0xA3u, 0x03u},
-			{0xA4u, 0x80u},
-			{0xA7u, 0x10u},
-			{0xA9u, 0x08u},
-			{0xAAu, 0x20u},
-			{0xACu, 0x04u},
-			{0xB0u, 0x01u},
-			{0xB1u, 0x02u},
-			{0xB2u, 0x01u},
-			{0xB3u, 0x20u},
-			{0xB6u, 0x01u},
-			{0xC0u, 0xEFu},
-			{0xC2u, 0xE3u},
-			{0xC4u, 0x2Au},
-			{0xCAu, 0xBFu},
-			{0xCCu, 0x7Eu},
-			{0xCEu, 0xBFu},
-			{0xD6u, 0x1Fu},
-			{0xD8u, 0x09u},
-			{0xE2u, 0x09u},
-			{0xEAu, 0x14u},
-			{0xECu, 0x06u},
-			{0xEEu, 0x10u},
-			{0x9Cu, 0x20u},
-			{0x9Eu, 0x02u},
-			{0xA0u, 0x02u},
-			{0xA5u, 0x11u},
-			{0xA6u, 0x04u},
-			{0xA9u, 0x03u},
-			{0xABu, 0x50u},
-			{0xADu, 0x04u},
-			{0xB2u, 0x44u},
-			{0xB4u, 0x40u},
-			{0xE2u, 0x09u},
-			{0xE8u, 0x20u},
-			{0xEEu, 0x31u},
-			{0x00u, 0x10u},
-			{0x02u, 0x08u},
-			{0x04u, 0x10u},
-			{0x06u, 0x08u},
+			{0x38u, 0x11u},
+			{0x39u, 0x44u},
+			{0x44u, 0x41u},
+			{0x45u, 0x90u},
+			{0x47u, 0x26u},
+			{0x4Du, 0x01u},
+			{0x4Fu, 0x08u},
+			{0x54u, 0x10u},
+			{0x57u, 0x68u},
+			{0x5Cu, 0x40u},
+			{0x5Eu, 0x29u},
+			{0x65u, 0x05u},
+			{0x67u, 0x06u},
+			{0x6Cu, 0x24u},
+			{0x6Eu, 0x02u},
+			{0x6Fu, 0x01u},
+			{0x74u, 0x01u},
+			{0x75u, 0x80u},
+			{0x76u, 0x08u},
+			{0x77u, 0x10u},
+			{0x84u, 0x02u},
+			{0x89u, 0x04u},
+			{0x8Fu, 0x10u},
+			{0x92u, 0x50u},
+			{0x93u, 0x02u},
+			{0x95u, 0x09u},
+			{0x96u, 0x04u},
+			{0x98u, 0x08u},
+			{0x99u, 0x24u},
+			{0x9Au, 0x81u},
+			{0x9Bu, 0x02u},
+			{0x9Cu, 0x02u},
+			{0x9Fu, 0x20u},
+			{0xA0u, 0x04u},
+			{0xA1u, 0x80u},
+			{0xA2u, 0xA8u},
+			{0xA3u, 0x80u},
+			{0xA4u, 0x11u},
+			{0xA5u, 0x10u},
+			{0xA6u, 0x02u},
+			{0xA7u, 0x5Cu},
+			{0xA9u, 0x80u},
+			{0xAAu, 0x80u},
+			{0xACu, 0x44u},
+			{0xB0u, 0x20u},
+			{0xB3u, 0x02u},
+			{0xB5u, 0x80u},
+			{0xC0u, 0x58u},
+			{0xC4u, 0x82u},
+			{0xCAu, 0x07u},
+			{0xCCu, 0x0Fu},
+			{0xCEu, 0x0Fu},
+			{0xD0u, 0xF0u},
+			{0xD6u, 0xF0u},
+			{0xD8u, 0xF0u},
+			{0xE6u, 0x02u},
+			{0xEAu, 0x19u},
+			{0xECu, 0x05u},
+			{0xEEu, 0x08u},
+			{0x02u, 0x70u},
+			{0x05u, 0x01u},
+			{0x09u, 0x13u},
+			{0x0Bu, 0x2Cu},
+			{0x0Cu, 0xAAu},
+			{0x0Eu, 0x55u},
+			{0x10u, 0x44u},
+			{0x11u, 0x1Cu},
+			{0x12u, 0x88u},
+			{0x13u, 0x23u},
+			{0x15u, 0x08u},
+			{0x16u, 0x07u},
+			{0x17u, 0x30u},
+			{0x19u, 0x08u},
+			{0x1Eu, 0x80u},
+			{0x22u, 0x08u},
+			{0x23u, 0x0Fu},
+			{0x28u, 0x99u},
+			{0x2Au, 0x22u},
+			{0x2Du, 0x10u},
+			{0x2Fu, 0x2Au},
+			{0x30u, 0xF0u},
+			{0x32u, 0x0Fu},
+			{0x33u, 0x07u},
+			{0x35u, 0x38u},
+			{0x3Bu, 0x20u},
+			{0x54u, 0x01u},
+			{0x58u, 0x04u},
+			{0x59u, 0x04u},
+			{0x5Bu, 0x04u},
+			{0x5Cu, 0x11u},
+			{0x5Du, 0x10u},
+			{0x5Fu, 0x01u},
+			{0x00u, 0x05u},
+			{0x05u, 0x01u},
 			{0x07u, 0x02u},
-			{0x08u, 0x08u},
-			{0x0Au, 0x10u},
-			{0x0Bu, 0x08u},
+			{0x0Bu, 0x09u},
 			{0x0Cu, 0x01u},
-			{0x0Eu, 0x02u},
-			{0x10u, 0x10u},
-			{0x12u, 0x08u},
-			{0x14u, 0x10u},
-			{0x16u, 0x08u},
-			{0x17u, 0x01u},
-			{0x1Au, 0x04u},
-			{0x1Bu, 0x04u},
-			{0x20u, 0x02u},
-			{0x22u, 0x01u},
-			{0x24u, 0x02u},
-			{0x26u, 0x01u},
-			{0x28u, 0x02u},
-			{0x2Au, 0x01u},
-			{0x2Cu, 0x02u},
-			{0x2Eu, 0x01u},
-			{0x30u, 0x04u},
-			{0x31u, 0x01u},
-			{0x33u, 0x04u},
-			{0x34u, 0x18u},
-			{0x35u, 0x02u},
-			{0x36u, 0x03u},
-			{0x37u, 0x08u},
-			{0x3Au, 0xA0u},
+			{0x0Eu, 0x12u},
+			{0x13u, 0x08u},
+			{0x17u, 0x21u},
+			{0x1Au, 0x08u},
+			{0x1Bu, 0x28u},
+			{0x1Du, 0x01u},
+			{0x1Eu, 0x10u},
+			{0x20u, 0x04u},
+			{0x24u, 0x30u},
+			{0x26u, 0x08u},
+			{0x27u, 0x24u},
+			{0x29u, 0x20u},
+			{0x2Au, 0x02u},
+			{0x2Bu, 0x01u},
+			{0x2Cu, 0x01u},
+			{0x2Fu, 0x80u},
+			{0x30u, 0x08u},
+			{0x32u, 0x01u},
+			{0x33u, 0x60u},
+			{0x36u, 0x20u},
+			{0x37u, 0x06u},
+			{0x39u, 0x46u},
+			{0x3Bu, 0x10u},
+			{0x3Cu, 0x18u},
+			{0x40u, 0x28u},
+			{0x41u, 0x08u},
+			{0x43u, 0x02u},
+			{0x49u, 0x38u},
+			{0x4Au, 0x80u},
+			{0x4Bu, 0x40u},
+			{0x50u, 0x02u},
+			{0x51u, 0x21u},
+			{0x52u, 0x44u},
+			{0x5Eu, 0x40u},
+			{0x60u, 0x80u},
+			{0x61u, 0x20u},
+			{0x62u, 0x40u},
+			{0x63u, 0x20u},
+			{0x83u, 0x01u},
+			{0x8Du, 0x01u},
+			{0x8Eu, 0x10u},
+			{0x90u, 0x08u},
+			{0x92u, 0x40u},
+			{0x95u, 0x44u},
+			{0x96u, 0x06u},
+			{0x98u, 0x41u},
+			{0x99u, 0x80u},
+			{0x9Au, 0x08u},
+			{0x9Bu, 0x13u},
+			{0x9Cu, 0x20u},
+			{0x9Du, 0x10u},
+			{0x9Eu, 0x02u},
+			{0x9Fu, 0x64u},
+			{0xA0u, 0x24u},
+			{0xA2u, 0x21u},
+			{0xA3u, 0x80u},
+			{0xA4u, 0x08u},
+			{0xA6u, 0x02u},
+			{0xABu, 0x40u},
+			{0xB1u, 0x01u},
+			{0xB3u, 0x08u},
+			{0xB4u, 0x10u},
+			{0xB6u, 0x10u},
+			{0xB7u, 0x20u},
+			{0xC0u, 0x9Cu},
+			{0xC2u, 0xB3u},
+			{0xC4u, 0x54u},
+			{0xCAu, 0x9Du},
+			{0xCCu, 0xEFu},
+			{0xCEu, 0x6Fu},
+			{0xD0u, 0x07u},
+			{0xD2u, 0x0Cu},
+			{0xD6u, 0x10u},
+			{0xD8u, 0x0Fu},
+			{0xE2u, 0x01u},
+			{0xE6u, 0x02u},
+			{0xE8u, 0x04u},
+			{0xEAu, 0x19u},
+			{0xEEu, 0x08u},
+			{0x82u, 0x10u},
+			{0x8Du, 0x10u},
+			{0x8Fu, 0x40u},
+			{0x92u, 0x50u},
+			{0x95u, 0x10u},
+			{0x96u, 0x08u},
+			{0x99u, 0x04u},
+			{0x9Au, 0x02u},
+			{0x9Fu, 0x14u},
+			{0xA1u, 0x04u},
+			{0xA5u, 0x10u},
+			{0xA6u, 0x0Au},
+			{0xA7u, 0x40u},
+			{0xA8u, 0x05u},
+			{0xB1u, 0x20u},
+			{0xB2u, 0x01u},
+			{0xB5u, 0x40u},
+			{0xB7u, 0x01u},
+			{0xE4u, 0x50u},
+			{0xE6u, 0x02u},
+			{0xE8u, 0x60u},
+			{0xEAu, 0x08u},
+			{0xECu, 0x90u},
+			{0xEEu, 0x08u},
+			{0x01u, 0xFFu},
+			{0x05u, 0x06u},
+			{0x06u, 0xFFu},
+			{0x07u, 0x09u},
+			{0x08u, 0x03u},
+			{0x0Au, 0x0Cu},
+			{0x0Bu, 0xFFu},
+			{0x10u, 0x0Fu},
+			{0x11u, 0x60u},
+			{0x12u, 0xF0u},
+			{0x13u, 0x90u},
+			{0x14u, 0x50u},
+			{0x15u, 0x05u},
+			{0x16u, 0xA0u},
+			{0x17u, 0x0Au},
+			{0x18u, 0x05u},
+			{0x19u, 0x50u},
+			{0x1Au, 0x0Au},
+			{0x1Bu, 0xA0u},
+			{0x1Du, 0x0Fu},
+			{0x1Eu, 0xFFu},
+			{0x1Fu, 0xF0u},
+			{0x21u, 0x03u},
+			{0x22u, 0xFFu},
+			{0x23u, 0x0Cu},
+			{0x24u, 0x30u},
+			{0x25u, 0x30u},
+			{0x26u, 0xC0u},
+			{0x27u, 0xC0u},
+			{0x28u, 0x09u},
+			{0x2Au, 0x06u},
+			{0x2Cu, 0x90u},
+			{0x2Eu, 0x60u},
+			{0x2Fu, 0xFFu},
+			{0x31u, 0xFFu},
+			{0x32u, 0xFFu},
+			{0x3Eu, 0x04u},
+			{0x3Fu, 0x01u},
 			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
-			{0x5Cu, 0x99u},
 			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x82u, 0x08u},
-			{0x83u, 0x01u},
-			{0x86u, 0x04u},
-			{0x89u, 0x04u},
-			{0x8Bu, 0x02u},
-			{0x8Du, 0x04u},
-			{0x8Eu, 0x01u},
-			{0x8Fu, 0x02u},
-			{0x90u, 0x08u},
-			{0x96u, 0x02u},
-			{0x98u, 0x08u},
-			{0x99u, 0x02u},
-			{0x9Bu, 0x04u},
-			{0x9Cu, 0x08u},
-			{0x9Du, 0x04u},
-			{0x9Fu, 0x02u},
-			{0xA6u, 0x08u},
-			{0xA9u, 0x04u},
-			{0xABu, 0x02u},
-			{0xB0u, 0x04u},
-			{0xB2u, 0x02u},
-			{0xB3u, 0x06u},
-			{0xB4u, 0x08u},
-			{0xB5u, 0x01u},
-			{0xB6u, 0x01u},
-			{0xBBu, 0x08u},
-			{0xBEu, 0x10u},
+			{0x82u, 0xFFu},
+			{0x84u, 0x55u},
+			{0x86u, 0xAAu},
+			{0x8Au, 0xFFu},
+			{0x8Cu, 0x0Fu},
+			{0x8Eu, 0xF0u},
+			{0x90u, 0xFFu},
+			{0x91u, 0x01u},
+			{0x96u, 0xFFu},
+			{0xA4u, 0x96u},
+			{0xA6u, 0x69u},
+			{0xA8u, 0xFFu},
+			{0xACu, 0x33u},
+			{0xAEu, 0xCCu},
+			{0xB0u, 0xFFu},
+			{0xB7u, 0x01u},
+			{0xBAu, 0x02u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
-			{0xDCu, 0x99u},
+			{0xDBu, 0x04u},
+			{0xDCu, 0x91u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x0Eu},
-			{0x01u, 0xA0u},
+			{0x01u, 0x04u},
+			{0x02u, 0x18u},
 			{0x04u, 0x40u},
-			{0x05u, 0x06u},
-			{0x08u, 0x02u},
-			{0x09u, 0x20u},
-			{0x0Au, 0x20u},
-			{0x0Cu, 0x20u},
-			{0x0Du, 0x02u},
-			{0x0Fu, 0x21u},
-			{0x12u, 0xAAu},
+			{0x05u, 0x02u},
+			{0x07u, 0x24u},
+			{0x09u, 0x80u},
+			{0x0Au, 0xF8u},
+			{0x0Bu, 0x02u},
+			{0x0Fu, 0x60u},
+			{0x10u, 0x11u},
+			{0x11u, 0xAAu},
+			{0x12u, 0x44u},
+			{0x14u, 0x0Au},
 			{0x15u, 0x08u},
-			{0x19u, 0xB0u},
-			{0x1Au, 0x40u},
+			{0x1Bu, 0x08u},
 			{0x1Cu, 0x40u},
-			{0x1Du, 0x44u},
-			{0x1Eu, 0x04u},
-			{0x1Fu, 0x08u},
-			{0x20u, 0x02u},
-			{0x21u, 0x10u},
-			{0x22u, 0x1Au},
-			{0x24u, 0x20u},
-			{0x25u, 0x04u},
-			{0x26u, 0x20u},
-			{0x27u, 0x10u},
-			{0x2Fu, 0x08u},
-			{0x32u, 0x28u},
-			{0x35u, 0x40u},
-			{0x37u, 0x10u},
-			{0x38u, 0x04u},
-			{0x39u, 0x20u},
-			{0x3Cu, 0x40u},
-			{0x3Fu, 0x22u},
-			{0x58u, 0x28u},
-			{0x5Bu, 0x40u},
-			{0x61u, 0x20u},
-			{0x62u, 0x80u},
-			{0x63u, 0x22u},
-			{0x8Eu, 0x01u},
-			{0x90u, 0x80u},
-			{0x91u, 0x08u},
-			{0x93u, 0x01u},
-			{0x94u, 0x20u},
-			{0x95u, 0x04u},
-			{0x96u, 0x40u},
-			{0x98u, 0x0Au},
-			{0x9Du, 0x91u},
-			{0x9Eu, 0x02u},
-			{0xA0u, 0x26u},
-			{0xA1u, 0x02u},
-			{0xA5u, 0x35u},
-			{0xA6u, 0x45u},
-			{0xAAu, 0xC0u},
-			{0xABu, 0x08u},
-			{0xADu, 0x04u},
-			{0xB0u, 0x28u},
-			{0xB2u, 0x02u},
-			{0xB6u, 0x08u},
-			{0xC0u, 0xBFu},
-			{0xC2u, 0xFEu},
-			{0xC4u, 0x2Fu},
-			{0xCAu, 0x20u},
-			{0xCCu, 0x36u},
-			{0xCEu, 0xB6u},
-			{0xD6u, 0x0Eu},
-			{0xD8u, 0x0Eu},
-			{0xE0u, 0x10u},
-			{0xE2u, 0x20u},
-			{0xEAu, 0x10u},
-			{0xECu, 0x20u},
-			{0xEEu, 0x55u},
-			{0x03u, 0xFFu},
-			{0x04u, 0x09u},
-			{0x06u, 0x06u},
+			{0x1Fu, 0x02u},
+			{0x22u, 0x01u},
+			{0x24u, 0x01u},
+			{0x28u, 0x10u},
+			{0x29u, 0x01u},
+			{0x2Au, 0x40u},
+			{0x30u, 0x01u},
+			{0x32u, 0x54u},
+			{0x35u, 0x02u},
+			{0x3Au, 0x14u},
+			{0x3Bu, 0x02u},
+			{0x58u, 0x40u},
+			{0x5Cu, 0x04u},
+			{0x5Du, 0x60u},
+			{0x5Eu, 0x01u},
+			{0x60u, 0x02u},
+			{0x67u, 0x01u},
+			{0x6Du, 0x89u},
+			{0x6Eu, 0x10u},
+			{0x75u, 0x04u},
+			{0x76u, 0x8Au},
+			{0x86u, 0x08u},
+			{0x88u, 0x40u},
+			{0x8Bu, 0x02u},
+			{0x8Du, 0x05u},
+			{0x8Eu, 0x08u},
+			{0x91u, 0x0Cu},
+			{0x92u, 0x40u},
+			{0x93u, 0x40u},
+			{0x95u, 0x11u},
+			{0x96u, 0x12u},
+			{0x98u, 0x08u},
+			{0x99u, 0x02u},
+			{0x9Bu, 0x20u},
+			{0x9Cu, 0x11u},
+			{0x9Du, 0x01u},
+			{0x9Eu, 0x86u},
+			{0x9Fu, 0x10u},
+			{0xA1u, 0x81u},
+			{0xA3u, 0x10u},
+			{0xA5u, 0x40u},
+			{0xA6u, 0x02u},
+			{0xA7u, 0x48u},
+			{0xA8u, 0x28u},
+			{0xAAu, 0x08u},
+			{0xABu, 0x10u},
+			{0xADu, 0x20u},
+			{0xAFu, 0x04u},
+			{0xB3u, 0x40u},
+			{0xC0u, 0xF6u},
+			{0xC2u, 0x3Fu},
+			{0xC4u, 0xEFu},
+			{0xCAu, 0x0Bu},
+			{0xCCu, 0x8Fu},
+			{0xCEu, 0x07u},
+			{0xD6u, 0xF8u},
+			{0xD8u, 0x18u},
+			{0xE2u, 0x10u},
+			{0xE6u, 0x80u},
+			{0xE8u, 0x20u},
+			{0xEAu, 0x98u},
+			{0xEEu, 0x42u},
 			{0x07u, 0xFFu},
-			{0x08u, 0x30u},
-			{0x09u, 0x55u},
-			{0x0Au, 0xC0u},
-			{0x0Bu, 0xAAu},
-			{0x0Cu, 0x90u},
-			{0x0Eu, 0x60u},
-			{0x10u, 0xFFu},
+			{0x09u, 0x0Fu},
+			{0x0Bu, 0xF0u},
+			{0x0Du, 0xFFu},
+			{0x10u, 0x08u},
+			{0x12u, 0x05u},
 			{0x13u, 0xFFu},
 			{0x15u, 0xFFu},
-			{0x19u, 0x0Fu},
-			{0x1Au, 0xFFu},
-			{0x1Bu, 0xF0u},
-			{0x1Cu, 0x03u},
-			{0x1Eu, 0x0Cu},
-			{0x20u, 0x05u},
-			{0x22u, 0x0Au},
-			{0x24u, 0x50u},
-			{0x25u, 0x33u},
-			{0x26u, 0xA0u},
-			{0x27u, 0xCCu},
-			{0x28u, 0xFFu},
-			{0x29u, 0xFFu},
-			{0x2Cu, 0x0Fu},
-			{0x2Du, 0x69u},
-			{0x2Eu, 0xF0u},
-			{0x2Fu, 0x96u},
-			{0x30u, 0xFFu},
+			{0x19u, 0x33u},
+			{0x1Bu, 0xCCu},
+			{0x1Cu, 0x0Du},
+			{0x1Eu, 0x32u},
+			{0x20u, 0x20u},
+			{0x22u, 0x12u},
+			{0x23u, 0xFFu},
+			{0x25u, 0x69u},
+			{0x26u, 0x40u},
+			{0x27u, 0x96u},
+			{0x28u, 0x04u},
+			{0x2Au, 0x08u},
+			{0x2Cu, 0x10u},
+			{0x2Du, 0x55u},
+			{0x2Eu, 0x20u},
+			{0x2Fu, 0xAAu},
+			{0x32u, 0x40u},
+			{0x34u, 0x03u},
 			{0x35u, 0xFFu},
-			{0x39u, 0x02u},
+			{0x36u, 0x3Cu},
 			{0x3Bu, 0x20u},
-			{0x3Eu, 0x01u},
-			{0x3Fu, 0x01u},
+			{0x3Eu, 0x50u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
-			{0x5Cu, 0x10u},
+			{0x5Bu, 0x04u},
+			{0x5Cu, 0x19u},
 			{0x5Fu, 0x01u},
-			{0x82u, 0x10u},
-			{0x84u, 0x02u},
-			{0x86u, 0x01u},
-			{0x87u, 0x04u},
-			{0x88u, 0x01u},
-			{0x89u, 0x02u},
-			{0x8Au, 0x02u},
-			{0x8Bu, 0x01u},
-			{0x8Cu, 0x02u},
-			{0x8Eu, 0x01u},
-			{0x90u, 0x02u},
-			{0x91u, 0x02u},
-			{0x92u, 0x01u},
-			{0x93u, 0x01u},
-			{0x94u, 0x04u},
-			{0x95u, 0x01u},
-			{0x97u, 0x02u},
-			{0x98u, 0x02u},
-			{0x99u, 0x02u},
-			{0x9Au, 0x01u},
-			{0x9Bu, 0x01u},
-			{0xA1u, 0x02u},
-			{0xA3u, 0x01u},
-			{0xA6u, 0x08u},
-			{0xAFu, 0x08u},
-			{0xB0u, 0x08u},
-			{0xB1u, 0x04u},
-			{0xB2u, 0x03u},
-			{0xB3u, 0x03u},
+			{0x80u, 0x01u},
+			{0x82u, 0x02u},
+			{0x89u, 0x04u},
+			{0x8Bu, 0x08u},
+			{0x92u, 0x04u},
+			{0x95u, 0x08u},
+			{0x97u, 0x04u},
+			{0x99u, 0x08u},
+			{0x9Bu, 0x05u},
+			{0x9Du, 0x08u},
+			{0x9Eu, 0x02u},
+			{0x9Fu, 0x04u},
+			{0xA2u, 0x08u},
+			{0xAAu, 0x01u},
+			{0xABu, 0x02u},
+			{0xADu, 0x08u},
+			{0xAFu, 0x04u},
+			{0xB0u, 0x03u},
+			{0xB2u, 0x08u},
+			{0xB3u, 0x02u},
 			{0xB4u, 0x04u},
-			{0xB5u, 0x08u},
-			{0xB6u, 0x10u},
-			{0xBAu, 0x08u},
-			{0xBBu, 0x08u},
+			{0xB5u, 0x0Cu},
+			{0xB7u, 0x01u},
+			{0xBBu, 0x20u},
+			{0xBEu, 0x01u},
 			{0xD6u, 0x08u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
@@ -1260,681 +1216,740 @@ void cyfitter_cfg(void)
 			{0xDCu, 0x99u},
 			{0xDDu, 0x90u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x94u},
-			{0x01u, 0x02u},
-			{0x03u, 0x04u},
-			{0x05u, 0x20u},
-			{0x06u, 0x20u},
-			{0x07u, 0x02u},
-			{0x09u, 0x24u},
-			{0x0Au, 0x40u},
-			{0x0Eu, 0x81u},
-			{0x0Fu, 0x04u},
-			{0x12u, 0x10u},
-			{0x14u, 0x44u},
-			{0x15u, 0x44u},
-			{0x18u, 0x10u},
-			{0x19u, 0x02u},
-			{0x1Au, 0x02u},
-			{0x1Bu, 0x20u},
-			{0x1Fu, 0x01u},
-			{0x20u, 0x88u},
-			{0x21u, 0x04u},
-			{0x22u, 0x08u},
-			{0x24u, 0x80u},
-			{0x26u, 0x20u},
-			{0x27u, 0x08u},
+			{0x00u, 0x02u},
+			{0x08u, 0x02u},
+			{0x09u, 0x40u},
+			{0x0Du, 0x40u},
+			{0x0Fu, 0x80u},
+			{0x12u, 0x84u},
+			{0x15u, 0x01u},
+			{0x16u, 0x12u},
+			{0x17u, 0x10u},
+			{0x18u, 0x80u},
+			{0x19u, 0x14u},
+			{0x1Du, 0x80u},
+			{0x1Eu, 0x05u},
+			{0x1Fu, 0x04u},
+			{0x21u, 0x18u},
+			{0x22u, 0x80u},
+			{0x23u, 0x08u},
+			{0x25u, 0x30u},
 			{0x28u, 0x02u},
-			{0x29u, 0x02u},
-			{0x2Cu, 0x08u},
-			{0x2Eu, 0x80u},
-			{0x2Fu, 0x10u},
-			{0x32u, 0x19u},
-			{0x36u, 0x2Au},
-			{0x38u, 0x04u},
-			{0x3Au, 0x10u},
-			{0x3Du, 0x08u},
-			{0x3Fu, 0x21u},
+			{0x2Bu, 0x04u},
+			{0x2Du, 0x8Au},
+			{0x31u, 0x14u},
+			{0x32u, 0x80u},
+			{0x34u, 0x28u},
+			{0x36u, 0x02u},
+			{0x39u, 0x20u},
+			{0x3Du, 0x20u},
+			{0x3Eu, 0x08u},
+			{0x3Fu, 0x40u},
+			{0x59u, 0x20u},
 			{0x5Au, 0x80u},
-			{0x5Bu, 0x10u},
+			{0x5Du, 0x42u},
+			{0x5Eu, 0x20u},
+			{0x5Fu, 0x08u},
 			{0x60u, 0x02u},
-			{0x62u, 0x10u},
-			{0x83u, 0x11u},
-			{0x87u, 0x20u},
-			{0x8Bu, 0x10u},
-			{0x8Cu, 0x28u},
-			{0x8Du, 0x02u},
-			{0x8Eu, 0x01u},
-			{0x8Fu, 0x10u},
-			{0x90u, 0x04u},
+			{0x62u, 0x30u},
+			{0x67u, 0x02u},
+			{0x68u, 0x01u},
+			{0x69u, 0x80u},
+			{0x6Au, 0x40u},
+			{0x6Cu, 0x08u},
+			{0x6Du, 0x04u},
+			{0x6Eu, 0x80u},
+			{0x80u, 0x08u},
+			{0x82u, 0x20u},
+			{0x83u, 0x01u},
+			{0x85u, 0x04u},
+			{0x89u, 0x04u},
+			{0x8Au, 0x54u},
+			{0x8Du, 0x08u},
+			{0x8Eu, 0x40u},
 			{0x91u, 0x40u},
-			{0x92u, 0x21u},
-			{0x93u, 0x05u},
-			{0x94u, 0x20u},
-			{0x95u, 0x0Cu},
-			{0x96u, 0x42u},
-			{0x98u, 0x44u},
-			{0x99u, 0x20u},
-			{0x9Au, 0x20u},
-			{0x9Bu, 0x02u},
-			{0x9Cu, 0x20u},
-			{0x9Du, 0x91u},
-			{0x9Eu, 0x03u},
-			{0x9Fu, 0x04u},
-			{0xA0u, 0x02u},
-			{0xA4u, 0x20u},
-			{0xA5u, 0x13u},
-			{0xA6u, 0x45u},
-			{0xA8u, 0x40u},
-			{0xA9u, 0x40u},
-			{0xABu, 0x40u},
-			{0xADu, 0x80u},
-			{0xAFu, 0x04u},
-			{0xC0u, 0xEFu},
-			{0xC2u, 0xDEu},
-			{0xC4u, 0xF4u},
-			{0xCAu, 0x79u},
-			{0xCCu, 0xE7u},
-			{0xCEu, 0xE6u},
-			{0xD6u, 0x0Cu},
-			{0xD8u, 0x0Cu},
-			{0xE0u, 0x70u},
-			{0xE2u, 0x8Cu},
-			{0xE4u, 0x50u},
-			{0xE6u, 0x23u},
-			{0xEAu, 0x80u},
-			{0xEEu, 0x04u},
-			{0x01u, 0x33u},
-			{0x03u, 0xCCu},
-			{0x05u, 0xFFu},
-			{0x0Bu, 0xFFu},
-			{0x0Du, 0x0Fu},
-			{0x0Fu, 0xF0u},
-			{0x11u, 0xFFu},
-			{0x12u, 0x04u},
-			{0x17u, 0xFFu},
-			{0x1Bu, 0xFFu},
-			{0x1Eu, 0x08u},
-			{0x21u, 0x55u},
-			{0x22u, 0x01u},
-			{0x23u, 0xAAu},
-			{0x25u, 0x96u},
-			{0x26u, 0x02u},
-			{0x27u, 0x69u},
-			{0x2Cu, 0x01u},
-			{0x2Eu, 0x02u},
+			{0x94u, 0x80u},
+			{0x95u, 0x14u},
+			{0x96u, 0x53u},
+			{0x99u, 0x82u},
+			{0x9Bu, 0x20u},
+			{0x9Cu, 0x11u},
+			{0x9Du, 0x01u},
+			{0x9Eu, 0x84u},
+			{0xA1u, 0x01u},
+			{0xA3u, 0x04u},
+			{0xA5u, 0x28u},
+			{0xA7u, 0x08u},
+			{0xA9u, 0x02u},
+			{0xAAu, 0x40u},
+			{0xADu, 0x20u},
+			{0xB0u, 0x20u},
+			{0xB3u, 0x20u},
+			{0xC0u, 0x08u},
+			{0xC2u, 0x99u},
+			{0xC4u, 0xFAu},
+			{0xCAu, 0xDCu},
+			{0xCCu, 0xEEu},
+			{0xCEu, 0x74u},
+			{0xD6u, 0xFCu},
+			{0xD8u, 0x1Cu},
+			{0xE0u, 0xC0u},
+			{0xE2u, 0x28u},
+			{0xE4u, 0x80u},
+			{0xE6u, 0x18u},
+			{0xECu, 0x20u},
+			{0xEEu, 0x80u},
+			{0x00u, 0x01u},
+			{0x02u, 0x02u},
+			{0x04u, 0x02u},
+			{0x05u, 0x02u},
+			{0x06u, 0x01u},
+			{0x09u, 0x02u},
+			{0x0Du, 0x08u},
+			{0x0Fu, 0x05u},
+			{0x11u, 0x02u},
+			{0x12u, 0x08u},
+			{0x14u, 0x02u},
+			{0x15u, 0x02u},
+			{0x16u, 0x01u},
+			{0x18u, 0x02u},
+			{0x19u, 0x08u},
+			{0x1Au, 0x05u},
+			{0x1Bu, 0x04u},
+			{0x1Du, 0x04u},
+			{0x1Fu, 0x08u},
+			{0x21u, 0x08u},
+			{0x23u, 0x14u},
+			{0x24u, 0x02u},
+			{0x26u, 0x11u},
+			{0x2Du, 0x08u},
+			{0x2Fu, 0x04u},
 			{0x30u, 0x03u},
-			{0x32u, 0x08u},
-			{0x34u, 0x04u},
-			{0x37u, 0xFFu},
+			{0x31u, 0x10u},
+			{0x32u, 0x04u},
+			{0x33u, 0x02u},
+			{0x34u, 0x10u},
+			{0x35u, 0x01u},
+			{0x36u, 0x08u},
+			{0x37u, 0x0Cu},
+			{0x39u, 0x08u},
+			{0x3Au, 0x02u},
 			{0x3Bu, 0x80u},
-			{0x3Eu, 0x01u},
+			{0x3Fu, 0x04u},
+			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
-			{0x5Cu, 0x19u},
+			{0x5Cu, 0x99u},
+			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x81u, 0x03u},
-			{0x83u, 0x0Cu},
-			{0x84u, 0x06u},
-			{0x86u, 0x09u},
+			{0x80u, 0x03u},
+			{0x81u, 0xFFu},
+			{0x82u, 0x0Cu},
+			{0x84u, 0xFFu},
 			{0x87u, 0xFFu},
-			{0x88u, 0x30u},
-			{0x89u, 0x06u},
-			{0x8Au, 0xC0u},
-			{0x8Bu, 0x09u},
-			{0x8Cu, 0x60u},
+			{0x88u, 0x06u},
+			{0x89u, 0x05u},
+			{0x8Au, 0x09u},
+			{0x8Bu, 0x0Au},
 			{0x8Du, 0x0Fu},
-			{0x8Eu, 0x90u},
 			{0x8Fu, 0xF0u},
-			{0x91u, 0x60u},
-			{0x92u, 0xFFu},
-			{0x93u, 0x90u},
-			{0x97u, 0xFFu},
-			{0x9Au, 0xFFu},
-			{0x9Cu, 0x03u},
-			{0x9Du, 0xFFu},
-			{0x9Eu, 0x0Cu},
-			{0xA0u, 0x05u},
-			{0xA1u, 0x05u},
-			{0xA2u, 0x0Au},
-			{0xA3u, 0x0Au},
-			{0xA4u, 0x50u},
-			{0xA5u, 0x50u},
-			{0xA6u, 0xA0u},
-			{0xA7u, 0xA0u},
-			{0xA8u, 0xFFu},
-			{0xA9u, 0x30u},
-			{0xABu, 0xC0u},
-			{0xACu, 0x0Fu},
-			{0xAEu, 0xF0u},
-			{0xB1u, 0xFFu},
-			{0xB6u, 0xFFu},
-			{0xBEu, 0x40u},
-			{0xBFu, 0x01u},
-			{0xD6u, 0x08u},
+			{0x90u, 0x0Fu},
+			{0x91u, 0x90u},
+			{0x92u, 0xF0u},
+			{0x93u, 0x60u},
+			{0x94u, 0x50u},
+			{0x96u, 0xA0u},
+			{0x98u, 0x30u},
+			{0x99u, 0x30u},
+			{0x9Au, 0xC0u},
+			{0x9Bu, 0xC0u},
+			{0x9Du, 0x03u},
+			{0x9Eu, 0xFFu},
+			{0x9Fu, 0x0Cu},
+			{0xA1u, 0xFFu},
+			{0xA5u, 0x09u},
+			{0xA6u, 0xFFu},
+			{0xA7u, 0x06u},
+			{0xA8u, 0x05u},
+			{0xA9u, 0x50u},
+			{0xAAu, 0x0Au},
+			{0xABu, 0xA0u},
+			{0xACu, 0x60u},
+			{0xAEu, 0x90u},
+			{0xB2u, 0xFFu},
+			{0xB3u, 0xFFu},
+			{0xBEu, 0x04u},
+			{0xBFu, 0x04u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
-			{0xDBu, 0x04u},
-			{0xDDu, 0x90u},
 			{0xDFu, 0x01u},
-			{0x05u, 0x20u},
-			{0x06u, 0x20u},
-			{0x07u, 0x02u},
-			{0x0Au, 0x42u},
-			{0x0Eu, 0x81u},
-			{0x0Fu, 0x04u},
-			{0x10u, 0x40u},
-			{0x11u, 0x44u},
-			{0x14u, 0x44u},
-			{0x15u, 0x44u},
-			{0x18u, 0x04u},
-			{0x19u, 0x02u},
-			{0x1Au, 0x20u},
-			{0x1Du, 0x80u},
+			{0x01u, 0x0Au},
+			{0x04u, 0x08u},
+			{0x05u, 0x01u},
+			{0x06u, 0x0Cu},
+			{0x07u, 0x40u},
+			{0x08u, 0x02u},
+			{0x09u, 0x08u},
+			{0x0Au, 0x04u},
+			{0x0Cu, 0x10u},
+			{0x0Eu, 0x51u},
+			{0x12u, 0x10u},
+			{0x14u, 0x01u},
+			{0x15u, 0x14u},
+			{0x19u, 0x0Au},
+			{0x1Au, 0x04u},
+			{0x1Bu, 0x84u},
+			{0x1Fu, 0x04u},
 			{0x21u, 0x40u},
-			{0x27u, 0x40u},
-			{0x28u, 0x20u},
-			{0x2Au, 0x01u},
-			{0x2Cu, 0x40u},
-			{0x2Du, 0x24u},
-			{0x2Eu, 0x02u},
-			{0x30u, 0x28u},
-			{0x31u, 0x02u},
-			{0x34u, 0x04u},
-			{0x36u, 0x45u},
-			{0x37u, 0x02u},
+			{0x22u, 0x58u},
+			{0x23u, 0x40u},
+			{0x24u, 0x20u},
+			{0x28u, 0x02u},
+			{0x2Bu, 0x80u},
+			{0x2Eu, 0x19u},
+			{0x32u, 0x51u},
+			{0x33u, 0x08u},
+			{0x34u, 0x11u},
+			{0x37u, 0x40u},
 			{0x38u, 0x20u},
-			{0x39u, 0x88u},
-			{0x3Bu, 0x0Au},
-			{0x3Du, 0x62u},
-			{0x3Eu, 0x21u},
-			{0x3Fu, 0x04u},
-			{0x59u, 0x91u},
+			{0x3Bu, 0x48u},
+			{0x3Du, 0x16u},
+			{0x3Eu, 0x40u},
+			{0x58u, 0xA0u},
+			{0x60u, 0x02u},
+			{0x62u, 0x10u},
+			{0x79u, 0xC0u},
+			{0x80u, 0x44u},
+			{0x81u, 0x01u},
+			{0x84u, 0x80u},
+			{0x85u, 0x80u},
+			{0x86u, 0x80u},
+			{0x8Eu, 0x08u},
+			{0xC0u, 0x7Cu},
+			{0xC2u, 0xFEu},
+			{0xC4u, 0xE4u},
+			{0xCAu, 0xE9u},
+			{0xCCu, 0xBFu},
+			{0xCEu, 0xFEu},
+			{0xD6u, 0x0Cu},
+			{0xD8u, 0x0Cu},
+			{0xE0u, 0x01u},
+			{0xE2u, 0x10u},
+			{0xE6u, 0x46u},
+			{0x00u, 0x0Cu},
+			{0x02u, 0x10u},
+			{0x04u, 0x11u},
+			{0x06u, 0x62u},
+			{0x08u, 0xC0u},
+			{0x0Cu, 0x1Cu},
+			{0x0Du, 0x04u},
+			{0x0Fu, 0x03u},
+			{0x10u, 0x24u},
+			{0x11u, 0x23u},
+			{0x12u, 0x10u},
+			{0x13u, 0x04u},
+			{0x14u, 0x70u},
+			{0x15u, 0x25u},
+			{0x16u, 0x0Fu},
+			{0x17u, 0x02u},
+			{0x1Bu, 0x08u},
+			{0x1Cu, 0x1Cu},
+			{0x20u, 0x08u},
+			{0x21u, 0x08u},
+			{0x23u, 0x10u},
+			{0x24u, 0x14u},
+			{0x26u, 0x08u},
+			{0x28u, 0x10u},
+			{0x29u, 0x21u},
+			{0x2Au, 0x0Cu},
+			{0x2Bu, 0x06u},
+			{0x2Cu, 0x21u},
+			{0x2Eu, 0x9Eu},
+			{0x2Fu, 0x10u},
+			{0x30u, 0x30u},
+			{0x31u, 0x07u},
+			{0x32u, 0xC1u},
+			{0x34u, 0x0Fu},
+			{0x35u, 0x18u},
+			{0x37u, 0x20u},
+			{0x38u, 0x08u},
+			{0x3Au, 0x02u},
+			{0x3Bu, 0x02u},
+			{0x3Fu, 0x50u},
+			{0x54u, 0x09u},
+			{0x56u, 0x04u},
+			{0x58u, 0x04u},
+			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
-			{0x5Cu, 0x40u},
-			{0x61u, 0x40u},
-			{0x67u, 0x02u},
-			{0x68u, 0x02u},
-			{0x69u, 0x40u},
-			{0x80u, 0x08u},
-			{0x83u, 0x01u},
-			{0x85u, 0x60u},
-			{0x87u, 0x04u},
-			{0x89u, 0x02u},
-			{0xC0u, 0xE0u},
-			{0xC2u, 0xD9u},
-			{0xC4u, 0xFDu},
-			{0xCAu, 0xE3u},
-			{0xCCu, 0xD7u},
-			{0xCEu, 0xFFu},
-			{0xD6u, 0x1Fu},
-			{0xD8u, 0x18u},
-			{0x80u, 0x02u},
-			{0x81u, 0x44u},
-			{0x82u, 0x41u},
-			{0x83u, 0x88u},
-			{0x8Bu, 0x80u},
-			{0x8Du, 0x99u},
-			{0x8Fu, 0x22u},
-			{0x94u, 0x53u},
-			{0x96u, 0xACu},
-			{0x97u, 0x07u},
-			{0x98u, 0x01u},
-			{0x99u, 0xAAu},
-			{0x9Au, 0x12u},
-			{0x9Bu, 0x55u},
-			{0x9Cu, 0x08u},
-			{0x9Eu, 0x84u},
-			{0x9Fu, 0x70u},
-			{0xA8u, 0x04u},
-			{0xAAu, 0x28u},
-			{0xAFu, 0x08u},
-			{0xB2u, 0xC0u},
-			{0xB3u, 0x0Fu},
-			{0xB4u, 0x30u},
-			{0xB6u, 0x0Fu},
-			{0xB7u, 0xF0u},
-			{0xBEu, 0x54u},
+			{0x5Fu, 0x01u},
+			{0x83u, 0x17u},
+			{0x87u, 0x40u},
+			{0x88u, 0x21u},
+			{0x8Au, 0x02u},
+			{0x91u, 0x04u},
+			{0x92u, 0x01u},
+			{0x93u, 0x08u},
+			{0x94u, 0x88u},
+			{0x95u, 0x09u},
+			{0x96u, 0x03u},
+			{0x97u, 0x02u},
+			{0x9Au, 0xECu},
+			{0x9Bu, 0x08u},
+			{0x9Du, 0x0Au},
+			{0x9Fu, 0x05u},
+			{0xA1u, 0x50u},
+			{0xA2u, 0x12u},
+			{0xA3u, 0xA0u},
+			{0xA4u, 0xE0u},
+			{0xA7u, 0x20u},
+			{0xACu, 0x04u},
+			{0xAEu, 0x43u},
+			{0xAFu, 0x80u},
+			{0xB0u, 0x10u},
+			{0xB1u, 0x0Fu},
+			{0xB4u, 0x0Fu},
+			{0xB5u, 0xC0u},
+			{0xB6u, 0xE0u},
+			{0xB7u, 0x30u},
+			{0xBEu, 0x40u},
+			{0xBFu, 0x50u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDCu, 0x10u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x08u},
-			{0x02u, 0x01u},
-			{0x03u, 0x84u},
-			{0x04u, 0x02u},
-			{0x08u, 0x02u},
-			{0x0Au, 0x02u},
-			{0x0Bu, 0x14u},
-			{0x0Eu, 0x09u},
-			{0x0Fu, 0x10u},
-			{0x10u, 0x10u},
+			{0x00u, 0x82u},
+			{0x03u, 0x2Cu},
+			{0x05u, 0x20u},
+			{0x09u, 0x08u},
+			{0x0Au, 0x41u},
+			{0x0Du, 0x0Au},
+			{0x0Eu, 0x08u},
+			{0x10u, 0x08u},
 			{0x11u, 0x04u},
 			{0x12u, 0x80u},
-			{0x17u, 0x20u},
-			{0x1Bu, 0x10u},
-			{0x1Eu, 0x04u},
-			{0x1Fu, 0x84u},
-			{0x21u, 0x08u},
-			{0x22u, 0x20u},
-			{0x23u, 0x40u},
-			{0x26u, 0x84u},
-			{0x28u, 0x12u},
-			{0x2Au, 0x01u},
-			{0x2Bu, 0x08u},
-			{0x2Du, 0x80u},
-			{0x32u, 0x20u},
-			{0x33u, 0x04u},
-			{0x36u, 0x84u},
+			{0x13u, 0x80u},
+			{0x15u, 0x02u},
+			{0x17u, 0x84u},
+			{0x19u, 0x20u},
+			{0x1Au, 0x40u},
+			{0x1Bu, 0x29u},
+			{0x1Du, 0x02u},
+			{0x1Eu, 0x0Au},
+			{0x20u, 0x48u},
+			{0x21u, 0x80u},
+			{0x24u, 0x02u},
+			{0x25u, 0x11u},
+			{0x26u, 0x02u},
+			{0x29u, 0x20u},
+			{0x2Au, 0x03u},
+			{0x2Bu, 0x02u},
+			{0x2Eu, 0x0Au},
+			{0x2Fu, 0x01u},
+			{0x31u, 0x08u},
+			{0x32u, 0x21u},
+			{0x34u, 0x41u},
+			{0x36u, 0x08u},
 			{0x37u, 0x10u},
-			{0x38u, 0x44u},
-			{0x3Bu, 0x10u},
-			{0x3Du, 0x92u},
-			{0x40u, 0x04u},
-			{0x43u, 0x0Au},
-			{0x49u, 0x1Au},
-			{0x4Au, 0x01u},
-			{0x51u, 0x20u},
-			{0x52u, 0x44u},
-			{0x62u, 0x20u},
-			{0x69u, 0x48u},
-			{0x6Au, 0x28u},
-			{0x6Bu, 0x40u},
-			{0x72u, 0x02u},
-			{0x73u, 0x01u},
-			{0x83u, 0x80u},
-			{0x86u, 0x04u},
-			{0x88u, 0x08u},
-			{0x89u, 0x0Au},
-			{0x8Bu, 0x40u},
-			{0x8Cu, 0x40u},
+			{0x38u, 0x40u},
+			{0x3Du, 0x0Au},
+			{0x59u, 0x1Au},
+			{0x5Au, 0x80u},
+			{0x61u, 0x80u},
+			{0x63u, 0x80u},
+			{0x82u, 0x08u},
+			{0x83u, 0x40u},
 			{0x8Du, 0x10u},
-			{0x8Eu, 0x01u},
-			{0x90u, 0x06u},
-			{0x91u, 0x14u},
-			{0x92u, 0x03u},
-			{0x93u, 0x14u},
-			{0x95u, 0x48u},
-			{0x96u, 0x28u},
-			{0x97u, 0x09u},
-			{0x98u, 0x02u},
-			{0x99u, 0x90u},
+			{0x8Eu, 0x81u},
+			{0x8Fu, 0x02u},
+			{0x91u, 0x06u},
+			{0x92u, 0x83u},
+			{0x93u, 0x02u},
+			{0x94u, 0x42u},
+			{0x96u, 0x40u},
+			{0x98u, 0x41u},
+			{0x99u, 0x0Au},
 			{0x9Au, 0x01u},
-			{0x9Bu, 0x34u},
-			{0x9Cu, 0x08u},
-			{0x9Du, 0x08u},
-			{0x9Eu, 0x46u},
-			{0x9Fu, 0x40u},
-			{0xA0u, 0x04u},
-			{0xA1u, 0x41u},
-			{0xA3u, 0x0Au},
-			{0xA5u, 0x20u},
-			{0xA6u, 0x80u},
-			{0xA7u, 0x10u},
-			{0xB2u, 0x80u},
-			{0xB6u, 0x01u},
-			{0xC0u, 0x1Fu},
-			{0xC2u, 0xEFu},
-			{0xC4u, 0x4Cu},
-			{0xCAu, 0x1Fu},
-			{0xCCu, 0x76u},
-			{0xCEu, 0xBEu},
-			{0xD0u, 0x07u},
-			{0xD2u, 0x0Cu},
-			{0xD8u, 0x04u},
-			{0xE0u, 0x10u},
-			{0xE4u, 0x04u},
-			{0x00u, 0x01u},
-			{0x01u, 0x44u},
-			{0x03u, 0x88u},
-			{0x04u, 0x10u},
-			{0x07u, 0x80u},
-			{0x08u, 0xA2u},
-			{0x0Au, 0x08u},
-			{0x0Cu, 0x04u},
-			{0x0Du, 0x99u},
-			{0x0Fu, 0x22u},
-			{0x12u, 0x40u},
-			{0x13u, 0x70u},
-			{0x14u, 0x01u},
-			{0x17u, 0x07u},
-			{0x18u, 0x07u},
-			{0x19u, 0xAAu},
-			{0x1Au, 0xD8u},
-			{0x1Bu, 0x55u},
-			{0x1Cu, 0x01u},
-			{0x20u, 0x01u},
-			{0x24u, 0x08u},
-			{0x26u, 0x61u},
-			{0x2Cu, 0x01u},
+			{0x9Bu, 0x90u},
+			{0x9Du, 0x20u},
+			{0xA0u, 0x49u},
+			{0xA1u, 0x0Cu},
+			{0xA2u, 0xA8u},
+			{0xA4u, 0x04u},
+			{0xA5u, 0x10u},
+			{0xA6u, 0x02u},
+			{0xA7u, 0x21u},
+			{0xA9u, 0x04u},
+			{0xAFu, 0x08u},
+			{0xB4u, 0x08u},
+			{0xC0u, 0x4Fu},
+			{0xC2u, 0x7Du},
+			{0xC4u, 0xBFu},
+			{0xCAu, 0xDDu},
+			{0xCCu, 0xF7u},
+			{0xCEu, 0xC8u},
+			{0xD6u, 0x0Fu},
+			{0xD8u, 0x09u},
+			{0xE2u, 0x10u},
+			{0xE6u, 0x01u},
+			{0xE8u, 0x4Cu},
+			{0x06u, 0x08u},
+			{0x07u, 0x07u},
+			{0x08u, 0x99u},
+			{0x0Au, 0x22u},
+			{0x11u, 0x44u},
+			{0x13u, 0x88u},
+			{0x16u, 0x07u},
+			{0x17u, 0x70u},
+			{0x19u, 0x99u},
+			{0x1Au, 0x70u},
+			{0x1Bu, 0x22u},
+			{0x1Du, 0xAAu},
+			{0x1Fu, 0x55u},
+			{0x20u, 0xAAu},
+			{0x22u, 0x55u},
+			{0x27u, 0x80u},
+			{0x2Au, 0x80u},
+			{0x2Cu, 0x44u},
+			{0x2Eu, 0x88u},
 			{0x2Fu, 0x08u},
-			{0x30u, 0xE0u},
-			{0x31u, 0xF0u},
-			{0x35u, 0x0Fu},
-			{0x36u, 0x3Fu},
-			{0x38u, 0x80u},
-			{0x3Eu, 0x40u},
+			{0x32u, 0x0Fu},
+			{0x33u, 0x0Fu},
+			{0x34u, 0xF0u},
+			{0x35u, 0xF0u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
-			{0x5Cu, 0x10u},
+			{0x5Cu, 0x11u},
 			{0x5Fu, 0x01u},
-			{0x80u, 0xE4u},
-			{0x81u, 0x80u},
-			{0x86u, 0x75u},
-			{0x87u, 0xFFu},
-			{0x88u, 0x07u},
-			{0x89u, 0x1Fu},
-			{0x8Au, 0x10u},
-			{0x8Bu, 0x20u},
-			{0x8Cu, 0x64u},
-			{0x8Du, 0x90u},
-			{0x8Eu, 0x80u},
-			{0x8Fu, 0x40u},
-			{0x90u, 0x08u},
-			{0x94u, 0x80u},
-			{0x95u, 0xC0u},
-			{0x96u, 0x64u},
-			{0x97u, 0x04u},
-			{0x98u, 0xA4u},
-			{0x99u, 0xC0u},
-			{0x9Au, 0x40u},
-			{0x9Bu, 0x08u},
+			{0x80u, 0xC1u},
+			{0x81u, 0x34u},
+			{0x84u, 0x07u},
+			{0x85u, 0x14u},
+			{0x86u, 0x18u},
+			{0x87u, 0x20u},
+			{0x8Au, 0x80u},
+			{0x8Bu, 0x34u},
+			{0x8Cu, 0x01u},
+			{0x8Du, 0x34u},
+			{0x8Eu, 0xC0u},
+			{0x90u, 0x01u},
+			{0x91u, 0x4Bu},
+			{0x93u, 0x30u},
+			{0x94u, 0x22u},
+			{0x95u, 0x08u},
+			{0x96u, 0x08u},
+			{0x97u, 0x75u},
+			{0x98u, 0x04u},
 			{0x9Cu, 0x08u},
-			{0x9Du, 0xC0u},
+			{0x9Du, 0x20u},
+			{0x9Eu, 0x21u},
 			{0x9Fu, 0x02u},
-			{0xA0u, 0xE4u},
-			{0xA1u, 0xC0u},
-			{0xA3u, 0x01u},
-			{0xA4u, 0x03u},
-			{0xA6u, 0x70u},
-			{0xA7u, 0x9Fu},
-			{0xA8u, 0x40u},
-			{0xA9u, 0x7Fu},
-			{0xAAu, 0x02u},
-			{0xABu, 0x80u},
-			{0xACu, 0x24u},
-			{0xAFu, 0x60u},
-			{0xB0u, 0x80u},
-			{0xB2u, 0x71u},
-			{0xB4u, 0x07u},
-			{0xB6u, 0x08u},
-			{0xB7u, 0xFFu},
+			{0xA0u, 0xC1u},
+			{0xA1u, 0x34u},
+			{0xA4u, 0xC1u},
+			{0xA8u, 0xC0u},
+			{0xA9u, 0x3Fu},
+			{0xABu, 0x40u},
+			{0xACu, 0x10u},
+			{0xADu, 0x14u},
+			{0xB0u, 0x40u},
+			{0xB1u, 0x78u},
+			{0xB3u, 0x07u},
+			{0xB4u, 0x80u},
+			{0xB6u, 0x3Fu},
+			{0xB7u, 0x40u},
 			{0xB8u, 0x80u},
-			{0xBAu, 0x30u},
-			{0xBEu, 0x01u},
+			{0xB9u, 0x02u},
+			{0xBBu, 0x0Cu},
+			{0xBEu, 0x51u},
 			{0xBFu, 0x40u},
-			{0xD4u, 0x40u},
-			{0xD6u, 0x04u},
+			{0xD6u, 0x02u},
+			{0xD7u, 0x2Cu},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDBu, 0x04u},
 			{0xDFu, 0x01u},
 			{0x01u, 0x40u},
-			{0x03u, 0x68u},
-			{0x05u, 0x58u},
-			{0x07u, 0x40u},
-			{0x09u, 0x80u},
-			{0x0Au, 0x28u},
-			{0x0Bu, 0x80u},
-			{0x0Du, 0x04u},
-			{0x0Eu, 0x80u},
-			{0x0Fu, 0x09u},
-			{0x12u, 0x06u},
-			{0x13u, 0x09u},
-			{0x15u, 0x42u},
-			{0x17u, 0x08u},
-			{0x18u, 0x20u},
-			{0x19u, 0x51u},
-			{0x1Bu, 0x2Eu},
-			{0x1Eu, 0x80u},
-			{0x1Fu, 0x40u},
-			{0x21u, 0x80u},
-			{0x26u, 0x01u},
-			{0x27u, 0x04u},
-			{0x29u, 0x58u},
+			{0x02u, 0x04u},
+			{0x03u, 0x60u},
+			{0x04u, 0x28u},
+			{0x0Au, 0x4Au},
+			{0x0Bu, 0x10u},
+			{0x0Eu, 0x28u},
+			{0x10u, 0x8Au},
+			{0x11u, 0x04u},
+			{0x14u, 0x41u},
+			{0x16u, 0x08u},
+			{0x18u, 0x01u},
+			{0x19u, 0x02u},
+			{0x1Bu, 0x12u},
+			{0x1Eu, 0x2Cu},
+			{0x21u, 0x08u},
+			{0x22u, 0x41u},
+			{0x23u, 0xD0u},
+			{0x25u, 0x04u},
+			{0x26u, 0x20u},
+			{0x27u, 0x08u},
+			{0x29u, 0x20u},
 			{0x2Au, 0x02u},
-			{0x2Eu, 0x40u},
-			{0x32u, 0x14u},
-			{0x33u, 0x40u},
-			{0x34u, 0x02u},
-			{0x36u, 0x01u},
-			{0x37u, 0x14u},
-			{0x38u, 0x24u},
-			{0x39u, 0x42u},
-			{0x3Du, 0x8Au},
-			{0x61u, 0x28u},
-			{0x62u, 0x40u},
-			{0x63u, 0x40u},
-			{0x87u, 0x40u},
-			{0x8Au, 0x40u},
-			{0x8Bu, 0x04u},
-			{0x90u, 0x06u},
-			{0x91u, 0x16u},
-			{0x92u, 0x43u},
-			{0x93u, 0x14u},
-			{0x94u, 0x20u},
-			{0x95u, 0x48u},
-			{0x96u, 0x28u},
-			{0x99u, 0x80u},
-			{0x9Au, 0x01u},
-			{0x9Bu, 0x38u},
+			{0x2Bu, 0x01u},
+			{0x2Cu, 0x20u},
+			{0x2Du, 0x80u},
+			{0x31u, 0x08u},
+			{0x32u, 0x81u},
+			{0x34u, 0x41u},
+			{0x37u, 0x28u},
+			{0x39u, 0x55u},
+			{0x3Du, 0x08u},
+			{0x60u, 0x40u},
+			{0x68u, 0x49u},
+			{0x69u, 0x55u},
+			{0x6Bu, 0x40u},
+			{0x70u, 0x80u},
+			{0x72u, 0x03u},
+			{0x83u, 0x01u},
+			{0x88u, 0x04u},
+			{0x8Cu, 0x01u},
+			{0x8Du, 0x10u},
+			{0x90u, 0x28u},
+			{0x91u, 0x02u},
+			{0x92u, 0x08u},
+			{0x94u, 0x01u},
+			{0x95u, 0x44u},
+			{0x96u, 0x06u},
+			{0x97u, 0x50u},
+			{0x98u, 0x41u},
+			{0x99u, 0x88u},
+			{0x9Au, 0x0Du},
+			{0x9Bu, 0x30u},
 			{0x9Cu, 0x08u},
-			{0x9Du, 0x19u},
-			{0x9Eu, 0x46u},
-			{0x9Fu, 0x44u},
-			{0xA0u, 0x04u},
-			{0xA1u, 0x4Du},
-			{0xA2u, 0x02u},
-			{0xA7u, 0x14u},
-			{0xABu, 0x04u},
-			{0xAFu, 0x10u},
-			{0xB7u, 0x21u},
-			{0xC0u, 0xFFu},
-			{0xC2u, 0xFFu},
-			{0xC4u, 0xBFu},
-			{0xCAu, 0x1Fu},
-			{0xCCu, 0xEEu},
-			{0xCEu, 0xDFu},
-			{0xD8u, 0x0Fu},
-			{0xE2u, 0x20u},
-			{0xE8u, 0x01u},
-			{0xEAu, 0x08u},
-			{0x9Cu, 0x20u},
+			{0x9Du, 0x20u},
 			{0x9Eu, 0x02u},
-			{0xA5u, 0x01u},
-			{0xA6u, 0x04u},
-			{0xA9u, 0x10u},
-			{0xACu, 0x02u},
-			{0xE0u, 0x80u},
-			{0x82u, 0x04u},
-			{0x8Cu, 0x20u},
-			{0x9Cu, 0x20u},
-			{0xA6u, 0x04u},
-			{0xB2u, 0x02u},
-			{0xB5u, 0x01u},
+			{0x9Fu, 0x40u},
+			{0xA0u, 0x22u},
+			{0xA2u, 0x88u},
+			{0xA4u, 0x08u},
+			{0xA5u, 0x08u},
+			{0xA6u, 0x12u},
+			{0xA7u, 0x13u},
+			{0xABu, 0x08u},
+			{0xB0u, 0x80u},
+			{0xB2u, 0x10u},
+			{0xB3u, 0x04u},
+			{0xB6u, 0x01u},
+			{0xB7u, 0x28u},
+			{0xC0u, 0x6Fu},
+			{0xC2u, 0x6Fu},
+			{0xC4u, 0xDFu},
+			{0xCAu, 0x5Du},
+			{0xCCu, 0xFBu},
+			{0xCEu, 0x4Fu},
+			{0xD8u, 0x01u},
+			{0xE2u, 0x48u},
+			{0xE6u, 0x14u},
+			{0xEAu, 0x20u},
+			{0xECu, 0x01u},
+			{0x39u, 0x20u},
+			{0x3Fu, 0x10u},
+			{0x59u, 0x04u},
+			{0x5Fu, 0x01u},
+			{0x27u, 0x08u},
+			{0x82u, 0x02u},
+			{0x87u, 0x08u},
+			{0x99u, 0x04u},
+			{0x9Au, 0x02u},
+			{0x9Fu, 0x10u},
+			{0xA1u, 0x04u},
+			{0xA6u, 0x08u},
+			{0xB1u, 0x10u},
+			{0xB2u, 0x04u},
+			{0xB6u, 0x42u},
+			{0xB7u, 0x04u},
 			{0xE0u, 0x20u},
-			{0xE4u, 0x20u},
-			{0xE8u, 0x90u},
+			{0xE8u, 0x80u},
+			{0xECu, 0x11u},
+			{0xEEu, 0x40u},
+			{0x81u, 0x04u},
+			{0x8Du, 0x04u},
+			{0x99u, 0x04u},
+			{0xA1u, 0x04u},
+			{0xABu, 0x10u},
+			{0xAEu, 0x08u},
+			{0xE6u, 0x40u},
 			{0x13u, 0x40u},
 			{0x17u, 0x48u},
-			{0x32u, 0x04u},
+			{0x32u, 0x02u},
 			{0x36u, 0x80u},
 			{0x37u, 0x08u},
-			{0x38u, 0x01u},
+			{0x39u, 0x01u},
 			{0x3Bu, 0x40u},
-			{0x3Eu, 0x28u},
+			{0x3Du, 0x04u},
+			{0x3Fu, 0x20u},
 			{0x43u, 0x10u},
-			{0x58u, 0x01u},
-			{0x5Fu, 0x20u},
-			{0x63u, 0x04u},
-			{0x65u, 0x40u},
-			{0x67u, 0x20u},
-			{0x85u, 0x40u},
+			{0x58u, 0x08u},
+			{0x5Eu, 0x42u},
+			{0x61u, 0x08u},
+			{0x66u, 0x08u},
 			{0x89u, 0x01u},
-			{0x8Cu, 0x01u},
+			{0x8Eu, 0x40u},
 			{0xC4u, 0xE0u},
 			{0xCCu, 0xE0u},
 			{0xCEu, 0xF0u},
 			{0xD0u, 0x10u},
 			{0xD6u, 0xE0u},
 			{0xD8u, 0xC0u},
-			{0xE6u, 0x10u},
-			{0x30u, 0x04u},
+			{0x32u, 0x04u},
 			{0x33u, 0x40u},
-			{0x36u, 0x20u},
-			{0x37u, 0x04u},
-			{0x3Au, 0x40u},
-			{0x53u, 0x20u},
-			{0x55u, 0x08u},
-			{0x58u, 0x80u},
-			{0x5Du, 0x01u},
-			{0x84u, 0x01u},
-			{0x86u, 0x64u},
-			{0x91u, 0x01u},
-			{0x96u, 0x08u},
-			{0x97u, 0x04u},
+			{0x34u, 0x10u},
+			{0x36u, 0x01u},
+			{0x3Bu, 0x10u},
+			{0x52u, 0x20u},
+			{0x56u, 0x20u},
+			{0x5Bu, 0x20u},
+			{0x5Fu, 0x02u},
+			{0x86u, 0x20u},
+			{0x8Bu, 0x02u},
+			{0x8Eu, 0x20u},
+			{0x8Fu, 0x10u},
+			{0x95u, 0x04u},
 			{0x9Bu, 0x40u},
-			{0x9Cu, 0x01u},
-			{0x9Eu, 0x08u},
+			{0x9Cu, 0x08u},
 			{0x9Fu, 0x10u},
-			{0xA1u, 0x08u},
-			{0xA3u, 0x20u},
-			{0xA6u, 0x80u},
-			{0xABu, 0x20u},
-			{0xADu, 0x08u},
-			{0xB3u, 0x10u},
-			{0xB6u, 0x20u},
-			{0xB7u, 0x20u},
+			{0xA5u, 0x08u},
+			{0xA6u, 0x82u},
+			{0xA7u, 0x10u},
+			{0xAAu, 0x01u},
+			{0xB2u, 0x08u},
 			{0xCCu, 0xF0u},
 			{0xCEu, 0x10u},
 			{0xD4u, 0xE0u},
 			{0xD6u, 0x80u},
-			{0xE2u, 0x50u},
-			{0xE6u, 0x50u},
-			{0xEAu, 0x40u},
-			{0xEEu, 0x20u},
+			{0xE6u, 0x40u},
+			{0xEEu, 0x80u},
 			{0x12u, 0x80u},
-			{0x63u, 0x01u},
-			{0x97u, 0x04u},
-			{0x9Cu, 0x84u},
-			{0x9Eu, 0x08u},
-			{0x9Fu, 0x14u},
-			{0xA6u, 0x80u},
+			{0x95u, 0x04u},
+			{0x96u, 0x08u},
+			{0x97u, 0x10u},
+			{0x9Cu, 0x18u},
+			{0x9Fu, 0x10u},
+			{0xA5u, 0x08u},
+			{0xA6u, 0x82u},
+			{0xABu, 0x20u},
+			{0xB6u, 0x01u},
 			{0xC4u, 0x10u},
-			{0xD6u, 0x40u},
-			{0x83u, 0x14u},
-			{0x84u, 0x04u},
-			{0x85u, 0x80u},
-			{0x97u, 0x04u},
-			{0x9Cu, 0x04u},
-			{0x9Eu, 0x08u},
-			{0x9Fu, 0x14u},
-			{0xB4u, 0x80u},
-			{0xB7u, 0x01u},
-			{0xE2u, 0xB0u},
+			{0xEAu, 0x80u},
+			{0x84u, 0x10u},
+			{0x95u, 0x04u},
+			{0x99u, 0x20u},
+			{0x9Cu, 0x18u},
+			{0x9Fu, 0x10u},
+			{0xA5u, 0x08u},
+			{0xAAu, 0x02u},
+			{0xAEu, 0x04u},
+			{0xAFu, 0x10u},
+			{0xB5u, 0x20u},
 			{0xE6u, 0x40u},
-			{0x08u, 0x02u},
-			{0x0Bu, 0x08u},
-			{0x0Fu, 0x80u},
-			{0x12u, 0x80u},
-			{0x17u, 0x02u},
-			{0x52u, 0x10u},
-			{0x57u, 0x80u},
-			{0x58u, 0x10u},
-			{0x5Eu, 0x20u},
-			{0x8Au, 0x10u},
+			{0xEAu, 0x90u},
+			{0xEEu, 0x10u},
+			{0x08u, 0x44u},
+			{0x0Fu, 0x40u},
+			{0x11u, 0x08u},
+			{0x14u, 0x10u},
+			{0x51u, 0x08u},
+			{0x56u, 0x08u},
+			{0x5Bu, 0x40u},
+			{0x5Fu, 0x80u},
+			{0x80u, 0x40u},
+			{0x83u, 0x80u},
+			{0x84u, 0x10u},
+			{0x8Eu, 0x40u},
 			{0xC2u, 0x0Eu},
 			{0xC4u, 0x0Cu},
 			{0xD4u, 0x07u},
 			{0xD6u, 0x04u},
-			{0xE0u, 0x01u},
+			{0xE2u, 0x08u},
 			{0x00u, 0x40u},
-			{0x01u, 0x08u},
-			{0x04u, 0x08u},
-			{0x05u, 0x20u},
-			{0x08u, 0x08u},
-			{0x09u, 0x40u},
-			{0x0Fu, 0x21u},
-			{0x80u, 0x04u},
-			{0x83u, 0x40u},
+			{0x03u, 0x80u},
+			{0x05u, 0x40u},
+			{0x06u, 0x40u},
+			{0x08u, 0x20u},
+			{0x0Au, 0x80u},
+			{0x0Eu, 0x11u},
+			{0x84u, 0x20u},
 			{0x86u, 0x01u},
-			{0x87u, 0x10u},
-			{0x88u, 0x08u},
-			{0x89u, 0x40u},
-			{0x93u, 0x08u},
-			{0x98u, 0x02u},
-			{0x9Bu, 0x02u},
-			{0x9Cu, 0x10u},
-			{0x9Du, 0x08u},
-			{0x9Eu, 0x10u},
-			{0xA3u, 0x40u},
-			{0xA7u, 0x80u},
-			{0xA9u, 0x08u},
-			{0xB2u, 0x80u},
+			{0x89u, 0x08u},
+			{0x8Eu, 0x30u},
+			{0x93u, 0x40u},
+			{0x94u, 0x40u},
+			{0x96u, 0x80u},
+			{0x9Eu, 0x08u},
+			{0x9Fu, 0x40u},
+			{0xA1u, 0x04u},
+			{0xA5u, 0x08u},
+			{0xB0u, 0x44u},
 			{0xC0u, 0x0Fu},
 			{0xC2u, 0x0Fu},
-			{0xE2u, 0x01u},
-			{0xE6u, 0x04u},
+			{0xE2u, 0x08u},
+			{0xE4u, 0x04u},
+			{0xE6u, 0x08u},
 			{0xEAu, 0x01u},
-			{0x89u, 0x20u},
-			{0x96u, 0x01u},
-			{0x97u, 0x20u},
-			{0x99u, 0x20u},
-			{0x9Bu, 0x02u},
-			{0x9Cu, 0x10u},
-			{0x9Eu, 0x10u},
-			{0xA7u, 0x80u},
-			{0xA8u, 0x42u},
-			{0xB3u, 0x04u},
-			{0xB7u, 0x11u},
-			{0xE2u, 0x04u},
+			{0xEEu, 0x01u},
+			{0x8Bu, 0x80u},
+			{0x9Cu, 0x80u},
+			{0x9Eu, 0x08u},
+			{0x9Fu, 0x40u},
+			{0xA3u, 0x80u},
+			{0xA6u, 0x20u},
+			{0xAEu, 0x40u},
+			{0xAFu, 0x40u},
+			{0xB1u, 0x40u},
+			{0xB4u, 0x80u},
+			{0xB5u, 0x04u},
+			{0xE2u, 0x01u},
 			{0xEAu, 0x09u},
-			{0xEEu, 0x08u},
-			{0x0Bu, 0x21u},
-			{0x0Cu, 0x02u},
-			{0x0Eu, 0x01u},
-			{0x83u, 0x01u},
-			{0x84u, 0x02u},
+			{0xEEu, 0x02u},
+			{0x08u, 0x80u},
+			{0x0Bu, 0x20u},
+			{0x0Eu, 0x21u},
+			{0x87u, 0x10u},
 			{0x96u, 0x01u},
-			{0x97u, 0x20u},
-			{0x9Cu, 0x10u},
-			{0x9Eu, 0x10u},
-			{0xA7u, 0x80u},
-			{0xABu, 0x02u},
-			{0xC2u, 0x0Fu},
-			{0x86u, 0x08u},
-			{0x8Bu, 0x08u},
-			{0x97u, 0x04u},
+			{0x9Cu, 0x80u},
 			{0x9Eu, 0x08u},
-			{0xA1u, 0x80u},
-			{0xE6u, 0x40u},
-			{0x04u, 0x08u},
-			{0x51u, 0x80u},
-			{0x57u, 0x08u},
-			{0x87u, 0x04u},
+			{0x9Fu, 0x40u},
+			{0xA6u, 0x30u},
+			{0xAEu, 0x11u},
+			{0xC2u, 0x0Fu},
+			{0x67u, 0x80u},
+			{0x87u, 0x40u},
+			{0x8Cu, 0x08u},
+			{0x8Du, 0x08u},
+			{0x99u, 0x20u},
+			{0x9Cu, 0x08u},
+			{0x9Fu, 0x10u},
+			{0xA5u, 0x08u},
+			{0xB1u, 0x04u},
+			{0xD8u, 0x80u},
+			{0xE2u, 0x10u},
+			{0x04u, 0x02u},
+			{0x50u, 0x04u},
+			{0x59u, 0x20u},
+			{0x83u, 0x10u},
 			{0x8Cu, 0x04u},
-			{0x97u, 0x04u},
-			{0xA1u, 0x80u},
-			{0xA3u, 0x08u},
+			{0x94u, 0x02u},
+			{0x99u, 0x20u},
+			{0x9Fu, 0x10u},
+			{0xB4u, 0x01u},
 			{0xC0u, 0x20u},
-			{0xD4u, 0x60u},
-			{0xE2u, 0x40u},
-			{0x8Bu, 0x80u},
-			{0x9Cu, 0x10u},
-			{0x9Eu, 0x10u},
-			{0xA7u, 0x80u},
-			{0xE0u, 0x01u},
-			{0x01u, 0x02u},
-			{0x88u, 0x10u},
-			{0x8Au, 0x10u},
-			{0x8Du, 0x02u},
-			{0x9Cu, 0x10u},
-			{0x9Eu, 0x10u},
-			{0xC0u, 0x08u},
+			{0xD4u, 0xA0u},
+			{0xE2u, 0x20u},
+			{0x8Au, 0x08u},
+			{0x9Eu, 0x08u},
+			{0xA6u, 0x20u},
+			{0xABu, 0x40u},
 			{0xE0u, 0x04u},
-			{0xE2u, 0x02u},
-			{0xE4u, 0x04u},
+			{0x02u, 0x20u},
+			{0xA6u, 0x20u},
+			{0xC0u, 0x08u},
 			{0x10u, 0x03u},
 			{0x1Au, 0x03u},
 			{0x00u, 0xFDu},
@@ -1961,31 +1976,32 @@ void cyfitter_cfg(void)
 			/* address, size */
 			{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
 			{(void CYFAR *)(CYREG_PRT1_DR), 16u},
-			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
-			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},
+			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
 			{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
 		};
 
-		/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
-		static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
-			0x00u, 0x00u, 0xFFu, 0x00u, 0x50u, 0x03u, 0xA0u, 0x04u, 0x09u, 0x28u, 0x06u, 0x50u, 0x90u, 0x05u, 0x60u, 0x02u, 
-			0x03u, 0x00u, 0x0Cu, 0x00u, 0x0Fu, 0x00u, 0xF0u, 0x08u, 0x00u, 0x04u, 0xFFu, 0x03u, 0x00u, 0x00u, 0xFFu, 0x00u, 
-			0x05u, 0x00u, 0x0Au, 0x10u, 0x30u, 0x00u, 0xC0u, 0x40u, 0x00u, 0x01u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x20u, 
-			0x00u, 0x60u, 0x00u, 0x18u, 0xFFu, 0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x10u, 0x05u, 
-			0x26u, 0x03u, 0x40u, 0x00u, 0x05u, 0xEBu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 
-			0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 
+		/* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */
+		static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {
+			0x04u, 0x00u, 0x00u, 0x9Fu, 0x04u, 0xC0u, 0x00u, 0x04u, 0x00u, 0x7Fu, 0x00u, 0x80u, 0x00u, 0x90u, 0x00u, 0x40u, 
+			0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0xC0u, 0x00u, 0x08u, 0x00u, 0x00u, 0x01u, 0x60u, 0x00u, 0xC0u, 0x02u, 0x02u, 
+			0x00u, 0xC0u, 0x00u, 0x01u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, 
+			0x00u, 0x00u, 0x03u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, 
+			0x53u, 0x06u, 0x40u, 0x00u, 0x02u, 0xCEu, 0xFDu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 
+			0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, 
 			0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 
 			0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
 
 		/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
 		static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
-			0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x00u, 0x01u, 0x02u, 0x01u};
+			0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u};
 
 		static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
 			/* dest, src, size */
-			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},
 			{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
 		};
 
@@ -1995,7 +2011,7 @@ void cyfitter_cfg(void)
 		for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
 		{
 			const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
-			CYMEMZERO(ms->address, (uint32)(ms->size));
+			CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
 		}
 
 		/* Copy device configuration data into registers */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
old mode 100755
new mode 100644
index 9481fd38..e4e1caf5
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 4d3ef9e3..814905cb 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -3,83 +3,110 @@
 .include "cydevicegnu.inc"
 .include "cydevicegnu_trm.inc"
 
-/* Debug_Timer_Interrupt */
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+/* LED1 */
+.set LED1__0__MASK, 0x08
+.set LED1__0__PC, CYREG_PRT12_PC3
+.set LED1__0__PORT, 12
+.set LED1__0__SHIFT, 3
+.set LED1__AG, CYREG_PRT12_AG
+.set LED1__BIE, CYREG_PRT12_BIE
+.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set LED1__BYP, CYREG_PRT12_BYP
+.set LED1__DM0, CYREG_PRT12_DM0
+.set LED1__DM1, CYREG_PRT12_DM1
+.set LED1__DM2, CYREG_PRT12_DM2
+.set LED1__DR, CYREG_PRT12_DR
+.set LED1__INP_DIS, CYREG_PRT12_INP_DIS
+.set LED1__MASK, 0x08
+.set LED1__PORT, 12
+.set LED1__PRT, CYREG_PRT12_PRT
+.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set LED1__PS, CYREG_PRT12_PS
+.set LED1__SHIFT, 3
+.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set LED1__SLW, CYREG_PRT12_SLW
 
-/* SD_RX_DMA_COMPLETE */
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SD_CD */
+.set SD_CD__0__MASK, 0x40
+.set SD_CD__0__PC, CYREG_PRT3_PC6
+.set SD_CD__0__PORT, 3
+.set SD_CD__0__SHIFT, 6
+.set SD_CD__AG, CYREG_PRT3_AG
+.set SD_CD__AMUX, CYREG_PRT3_AMUX
+.set SD_CD__BIE, CYREG_PRT3_BIE
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CD__BYP, CYREG_PRT3_BYP
+.set SD_CD__CTL, CYREG_PRT3_CTL
+.set SD_CD__DM0, CYREG_PRT3_DM0
+.set SD_CD__DM1, CYREG_PRT3_DM1
+.set SD_CD__DM2, CYREG_PRT3_DM2
+.set SD_CD__DR, CYREG_PRT3_DR
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CD__MASK, 0x40
+.set SD_CD__PORT, 3
+.set SD_CD__PRT, CYREG_PRT3_PRT
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CD__PS, CYREG_PRT3_PS
+.set SD_CD__SHIFT, 6
+.set SD_CD__SLW, CYREG_PRT3_SLW
 
-/* SD_TX_DMA_COMPLETE */
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SD_CS */
+.set SD_CS__0__MASK, 0x10
+.set SD_CS__0__PC, CYREG_PRT3_PC4
+.set SD_CS__0__PORT, 3
+.set SD_CS__0__SHIFT, 4
+.set SD_CS__AG, CYREG_PRT3_AG
+.set SD_CS__AMUX, CYREG_PRT3_AMUX
+.set SD_CS__BIE, CYREG_PRT3_BIE
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CS__BYP, CYREG_PRT3_BYP
+.set SD_CS__CTL, CYREG_PRT3_CTL
+.set SD_CS__DM0, CYREG_PRT3_DM0
+.set SD_CS__DM1, CYREG_PRT3_DM1
+.set SD_CS__DM2, CYREG_PRT3_DM2
+.set SD_CS__DR, CYREG_PRT3_DR
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CS__MASK, 0x10
+.set SD_CS__PORT, 3
+.set SD_CS__PRT, CYREG_PRT3_PRT
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CS__PS, CYREG_PRT3_PS
+.set SD_CS__SHIFT, 4
+.set SD_CS__SLW, CYREG_PRT3_SLW
 
-/* SCSI_Parity_Error */
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST
+/* USBFS_arb_int */
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_arb_int__INTC_MASK, 0x400000
+.set USBFS_arb_int__INTC_NUMBER, 22
+.set USBFS_arb_int__INTC_PRIOR_NUM, 7
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* USBFS_bus_reset */
 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -91,99 +118,131 @@
 .set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_PHASE */
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
-
-/* SCSI_Filtered */
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB14_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB14_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB14_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB14_ST
-
-/* SCSI_Out_Bits */
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-
-/* USBFS_arb_int */
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_arb_int__INTC_MASK, 0x400000
-.set USBFS_arb_int__INTC_NUMBER, 22
-.set USBFS_arb_int__INTC_PRIOR_NUM, 7
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* USBFS_Dm */
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x40
+.set USBFS_ep_1__INTC_NUMBER, 6
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x80
+.set USBFS_ep_2__INTC_NUMBER, 7
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_3__INTC_MASK, 0x100
+.set USBFS_ep_3__INTC_NUMBER, 8
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_4__INTC_MASK, 0x200
+.set USBFS_ep_4__INTC_NUMBER, 9
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -195,2186 +254,236 @@
 .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_Ctl */
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+/* USBFS_USB */
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
+.set USBFS_USB__CR0, CYREG_USB_CR0
+.set USBFS_USB__CR1, CYREG_USB_CR1
+.set USBFS_USB__CWA, CYREG_USB_CWA
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
+.set USBFS_USB__PM_ACT_MSK, 0x01
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
+.set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
+.set USBFS_USB__SOF0, CYREG_USB_SOF0
+.set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
 
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x08
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3
-.set SCSI_Out_DBx__0__PORT, 6
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__0__SHIFT, 3
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x04
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2
-.set SCSI_Out_DBx__1__PORT, 6
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__1__SHIFT, 2
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__2__MASK, 0x02
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1
-.set SCSI_Out_DBx__2__PORT, 6
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__2__SHIFT, 1
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x01
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0
-.set SCSI_Out_DBx__3__PORT, 6
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__3__SHIFT, 0
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x80
-.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7
-.set SCSI_Out_DBx__4__PORT, 4
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__4__SHIFT, 7
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x40
-.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6
-.set SCSI_Out_DBx__5__PORT, 4
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__5__SHIFT, 6
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x20
-.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5
-.set SCSI_Out_DBx__6__PORT, 4
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__6__SHIFT, 5
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x10
-.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4
-.set SCSI_Out_DBx__7__PORT, 4
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__7__SHIFT, 4
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x08
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3
-.set SCSI_Out_DBx__DB0__PORT, 6
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 3
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x04
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2
-.set SCSI_Out_DBx__DB1__PORT, 6
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 2
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB2__MASK, 0x02
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1
-.set SCSI_Out_DBx__DB2__PORT, 6
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 1
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x01
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0
-.set SCSI_Out_DBx__DB3__PORT, 6
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 0
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x80
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7
-.set SCSI_Out_DBx__DB4__PORT, 4
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 7
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x40
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6
-.set SCSI_Out_DBx__DB5__PORT, 4
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 6
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x20
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5
-.set SCSI_Out_DBx__DB6__PORT, 4
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 5
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x10
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4
-.set SCSI_Out_DBx__DB7__PORT, 4
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 4
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW
-
-/* SCSI_RST_ISR */
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RST_ISR__INTC_MASK, 0x04
-.set SCSI_RST_ISR__INTC_NUMBER, 2
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_RxStsReg__4__POS, 4
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
-.set SDCard_BSPIM_RxStsReg__5__POS, 5
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
-.set SDCard_BSPIM_RxStsReg__6__POS, 6
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
-.set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
-.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
-.set SDCard_BSPIM_TxStsReg__2__POS, 2
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
-.set SDCard_BSPIM_TxStsReg__3__POS, 3
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_TxStsReg__4__POS, 4
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__0__MASK, 0x10
-.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__0__PORT, 12
-.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__0__SHIFT, 4
-.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__1__MASK, 0x80
-.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7
-.set SCSI_In_DBx__1__PORT, 2
-.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__1__SHIFT, 7
-.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__2__MASK, 0x40
-.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6
-.set SCSI_In_DBx__2__PORT, 2
-.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__2__SHIFT, 6
-.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__3__MASK, 0x20
-.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__3__PORT, 2
-.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__3__SHIFT, 5
-.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__4__MASK, 0x10
-.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__4__PORT, 2
-.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__4__SHIFT, 4
-.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__5__MASK, 0x08
-.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3
-.set SCSI_In_DBx__5__PORT, 2
-.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__5__SHIFT, 3
-.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__6__MASK, 0x04
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2
-.set SCSI_In_DBx__6__PORT, 2
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__6__SHIFT, 2
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__7__MASK, 0x02
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1
-.set SCSI_In_DBx__7__PORT, 2
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__7__SHIFT, 1
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__DB0__MASK, 0x10
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__DB0__PORT, 12
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__DB0__SHIFT, 4
-.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB1__MASK, 0x80
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7
-.set SCSI_In_DBx__DB1__PORT, 2
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB1__SHIFT, 7
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB2__MASK, 0x40
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6
-.set SCSI_In_DBx__DB2__PORT, 2
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB2__SHIFT, 6
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB3__MASK, 0x20
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__DB3__PORT, 2
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB3__SHIFT, 5
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB4__MASK, 0x10
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__DB4__PORT, 2
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB4__SHIFT, 4
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB5__MASK, 0x08
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3
-.set SCSI_In_DBx__DB5__PORT, 2
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB5__SHIFT, 3
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB6__MASK, 0x04
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2
-.set SCSI_In_DBx__DB6__PORT, 2
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB6__SHIFT, 2
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB7__MASK, 0x02
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1
-.set SCSI_In_DBx__DB7__PORT, 2
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB7__SHIFT, 1
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_RX_DMA__DRQ_NUMBER, 0
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0
-.set SCSI_RX_DMA__PRIORITY, 2
-.set SCSI_RX_DMA__TERMIN_EN, 0
-.set SCSI_RX_DMA__TERMIN_SEL, 0
-.set SCSI_RX_DMA__TERMOUT0_EN, 1
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0
-.set SCSI_RX_DMA__TERMOUT1_EN, 0
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0
-
-/* SCSI_TX_DMA */
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_TX_DMA__DRQ_NUMBER, 1
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0
-.set SCSI_TX_DMA__PRIORITY, 2
-.set SCSI_TX_DMA__TERMIN_EN, 0
-.set SCSI_TX_DMA__TERMIN_SEL, 0
-.set SCSI_TX_DMA__TERMOUT0_EN, 1
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1
-.set SCSI_TX_DMA__TERMOUT1_EN, 0
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0
-
-/* SD_Data_Clk */
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
-.set SD_Data_Clk__INDEX, 0x00
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SD_Data_Clk__PM_ACT_MSK, 0x01
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SD_Data_Clk__PM_STBY_MSK, 0x01
-
-/* timer_clock */
-.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
-.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
-.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
-.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
-.set timer_clock__INDEX, 0x02
-.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set timer_clock__PM_ACT_MSK, 0x04
-.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set timer_clock__PM_STBY_MSK, 0x04
-
-/* SCSI_Noise */
-.set SCSI_Noise__0__AG, CYREG_PRT12_AG
-.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE
-.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP
-.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0
-.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1
-.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2
-.set SCSI_Noise__0__DR, CYREG_PRT12_DR
-.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_Noise__0__MASK, 0x20
-.set SCSI_Noise__0__PC, CYREG_PRT12_PC5
-.set SCSI_Noise__0__PORT, 12
-.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT
-.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_Noise__0__PS, CYREG_PRT12_PS
-.set SCSI_Noise__0__SHIFT, 5
-.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW
-.set SCSI_Noise__1__AG, CYREG_PRT6_AG
-.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__1__DR, CYREG_PRT6_DR
-.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__1__MASK, 0x10
-.set SCSI_Noise__1__PC, CYREG_PRT6_PC4
-.set SCSI_Noise__1__PORT, 6
-.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__1__PS, CYREG_PRT6_PS
-.set SCSI_Noise__1__SHIFT, 4
-.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__2__AG, CYREG_PRT5_AG
-.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE
-.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP
-.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL
-.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0
-.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1
-.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2
-.set SCSI_Noise__2__DR, CYREG_PRT5_DR
-.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Noise__2__MASK, 0x01
-.set SCSI_Noise__2__PC, CYREG_PRT5_PC0
-.set SCSI_Noise__2__PORT, 5
-.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT
-.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Noise__2__PS, CYREG_PRT5_PS
-.set SCSI_Noise__2__SHIFT, 0
-.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW
-.set SCSI_Noise__3__AG, CYREG_PRT6_AG
-.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__3__DR, CYREG_PRT6_DR
-.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__3__MASK, 0x40
-.set SCSI_Noise__3__PC, CYREG_PRT6_PC6
-.set SCSI_Noise__3__PORT, 6
-.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__3__PS, CYREG_PRT6_PS
-.set SCSI_Noise__3__SHIFT, 6
-.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__4__AG, CYREG_PRT6_AG
-.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__4__DR, CYREG_PRT6_DR
-.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__4__MASK, 0x20
-.set SCSI_Noise__4__PC, CYREG_PRT6_PC5
-.set SCSI_Noise__4__PORT, 6
-.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__4__PS, CYREG_PRT6_PS
-.set SCSI_Noise__4__SHIFT, 5
-.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
-.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
-.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__ACK__MASK, 0x20
-.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5
-.set SCSI_Noise__ACK__PORT, 6
-.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
-.set SCSI_Noise__ACK__SHIFT, 5
-.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG
-.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE
-.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP
-.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0
-.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1
-.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2
-.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR
-.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_Noise__ATN__MASK, 0x20
-.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5
-.set SCSI_Noise__ATN__PORT, 12
-.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT
-.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS
-.set SCSI_Noise__ATN__SHIFT, 5
-.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW
-.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
-.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
-.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__BSY__MASK, 0x10
-.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4
-.set SCSI_Noise__BSY__PORT, 6
-.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
-.set SCSI_Noise__BSY__SHIFT, 4
-.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__RST__AG, CYREG_PRT6_AG
-.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__RST__DR, CYREG_PRT6_DR
-.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__RST__MASK, 0x40
-.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6
-.set SCSI_Noise__RST__PORT, 6
-.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__RST__PS, CYREG_PRT6_PS
-.set SCSI_Noise__RST__SHIFT, 6
-.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG
-.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE
-.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP
-.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL
-.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0
-.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1
-.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2
-.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR
-.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Noise__SEL__MASK, 0x01
-.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0
-.set SCSI_Noise__SEL__PORT, 5
-.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT
-.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS
-.set SCSI_Noise__SEL__SHIFT, 0
-.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW
-
-/* scsiTarget */
-.set scsiTarget_StatusReg__0__MASK, 0x01
-.set scsiTarget_StatusReg__0__POS, 0
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
-.set scsiTarget_StatusReg__1__MASK, 0x02
-.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__2__MASK, 0x04
-.set scsiTarget_StatusReg__2__POS, 2
-.set scsiTarget_StatusReg__3__MASK, 0x08
-.set scsiTarget_StatusReg__3__POS, 3
-.set scsiTarget_StatusReg__4__MASK, 0x10
-.set scsiTarget_StatusReg__4__POS, 4
-.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB05_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB05_ST
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB01_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB01_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB01_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB01_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB01_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB01_MSK
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB01_02_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB01_02_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB01_02_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB01_02_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB01_02_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB01_02_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB01_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB01_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB01_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB01_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB01_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB01_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB01_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB01_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB01_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x40
-.set USBFS_ep_1__INTC_NUMBER, 6
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x80
-.set USBFS_ep_2__INTC_NUMBER, 7
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x100
-.set USBFS_ep_3__INTC_NUMBER, 8
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_4__INTC_MASK, 0x200
-.set USBFS_ep_4__INTC_NUMBER, 9
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_RX_DMA__DRQ_NUMBER, 2
-.set SD_RX_DMA__NUMBEROF_TDS, 0
-.set SD_RX_DMA__PRIORITY, 1
-.set SD_RX_DMA__TERMIN_EN, 0
-.set SD_RX_DMA__TERMIN_SEL, 0
-.set SD_RX_DMA__TERMOUT0_EN, 1
-.set SD_RX_DMA__TERMOUT0_SEL, 2
-.set SD_RX_DMA__TERMOUT1_EN, 0
-.set SD_RX_DMA__TERMOUT1_SEL, 0
-
-/* SD_TX_DMA */
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_TX_DMA__DRQ_NUMBER, 3
-.set SD_TX_DMA__NUMBEROF_TDS, 0
-.set SD_TX_DMA__PRIORITY, 2
-.set SD_TX_DMA__TERMIN_EN, 0
-.set SD_TX_DMA__TERMIN_SEL, 0
-.set SD_TX_DMA__TERMOUT0_EN, 1
-.set SD_TX_DMA__TERMOUT0_SEL, 3
-.set SD_TX_DMA__TERMOUT1_EN, 0
-.set SD_TX_DMA__TERMOUT1_SEL, 0
-
-/* USBFS_USB */
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
-.set USBFS_USB__CR0, CYREG_USB_CR0
-.set USBFS_USB__CR1, CYREG_USB_CR1
-.set USBFS_USB__CWA, CYREG_USB_CWA
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
-.set USBFS_USB__PM_ACT_MSK, 0x01
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
-.set USBFS_USB__PM_STBY_MSK, 0x01
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
-.set USBFS_USB__SOF0, CYREG_USB_SOF0
-.set USBFS_USB__SOF1, CYREG_USB_SOF1
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
-.set SCSI_CLK__INDEX, 0x01
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SCSI_CLK__PM_ACT_MSK, 0x02
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SCSI_CLK__PM_STBY_MSK, 0x02
-
-/* SCSI_Out */
-.set SCSI_Out__0__AG, CYREG_PRT4_AG
-.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__0__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__0__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__0__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__0__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__0__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__0__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__0__DR, CYREG_PRT4_DR
-.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__0__MASK, 0x08
-.set SCSI_Out__0__PC, CYREG_PRT4_PC3
-.set SCSI_Out__0__PORT, 4
-.set SCSI_Out__0__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__0__PS, CYREG_PRT4_PS
-.set SCSI_Out__0__SHIFT, 3
-.set SCSI_Out__0__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__1__AG, CYREG_PRT4_AG
-.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__1__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__1__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__1__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__1__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__1__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__1__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__1__DR, CYREG_PRT4_DR
-.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__1__MASK, 0x04
-.set SCSI_Out__1__PC, CYREG_PRT4_PC2
-.set SCSI_Out__1__PORT, 4
-.set SCSI_Out__1__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__1__PS, CYREG_PRT4_PS
-.set SCSI_Out__1__SHIFT, 2
-.set SCSI_Out__1__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__2__AG, CYREG_PRT0_AG
-.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__2__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__2__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__2__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__2__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__2__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__2__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__2__DR, CYREG_PRT0_DR
-.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__2__MASK, 0x80
-.set SCSI_Out__2__PC, CYREG_PRT0_PC7
-.set SCSI_Out__2__PORT, 0
-.set SCSI_Out__2__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__2__PS, CYREG_PRT0_PS
-.set SCSI_Out__2__SHIFT, 7
-.set SCSI_Out__2__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__3__AG, CYREG_PRT0_AG
-.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__3__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__3__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__3__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__3__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__3__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__3__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__3__DR, CYREG_PRT0_DR
-.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__3__MASK, 0x40
-.set SCSI_Out__3__PC, CYREG_PRT0_PC6
-.set SCSI_Out__3__PORT, 0
-.set SCSI_Out__3__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__3__PS, CYREG_PRT0_PS
-.set SCSI_Out__3__SHIFT, 6
-.set SCSI_Out__3__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__4__AG, CYREG_PRT0_AG
-.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__4__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__4__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__4__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__4__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__4__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__4__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__4__DR, CYREG_PRT0_DR
-.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__4__MASK, 0x20
-.set SCSI_Out__4__PC, CYREG_PRT0_PC5
-.set SCSI_Out__4__PORT, 0
-.set SCSI_Out__4__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__4__PS, CYREG_PRT0_PS
-.set SCSI_Out__4__SHIFT, 5
-.set SCSI_Out__4__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__5__AG, CYREG_PRT0_AG
-.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__5__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__5__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__5__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__5__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__5__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__5__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__5__DR, CYREG_PRT0_DR
-.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__5__MASK, 0x10
-.set SCSI_Out__5__PC, CYREG_PRT0_PC4
-.set SCSI_Out__5__PORT, 0
-.set SCSI_Out__5__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__5__PS, CYREG_PRT0_PS
-.set SCSI_Out__5__SHIFT, 4
-.set SCSI_Out__5__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__6__AG, CYREG_PRT0_AG
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__6__DR, CYREG_PRT0_DR
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__6__MASK, 0x08
-.set SCSI_Out__6__PC, CYREG_PRT0_PC3
-.set SCSI_Out__6__PORT, 0
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__6__PS, CYREG_PRT0_PS
-.set SCSI_Out__6__SHIFT, 3
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__7__AG, CYREG_PRT0_AG
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__7__DR, CYREG_PRT0_DR
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__7__MASK, 0x04
-.set SCSI_Out__7__PC, CYREG_PRT0_PC2
-.set SCSI_Out__7__PORT, 0
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__7__PS, CYREG_PRT0_PS
-.set SCSI_Out__7__SHIFT, 2
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__8__AG, CYREG_PRT0_AG
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__8__DR, CYREG_PRT0_DR
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__8__MASK, 0x02
-.set SCSI_Out__8__PC, CYREG_PRT0_PC1
-.set SCSI_Out__8__PORT, 0
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__8__PS, CYREG_PRT0_PS
-.set SCSI_Out__8__SHIFT, 1
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__9__AG, CYREG_PRT0_AG
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__9__DR, CYREG_PRT0_DR
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__9__MASK, 0x01
-.set SCSI_Out__9__PC, CYREG_PRT0_PC0
-.set SCSI_Out__9__PORT, 0
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__9__PS, CYREG_PRT0_PS
-.set SCSI_Out__9__SHIFT, 0
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__ACK__AG, CYREG_PRT0_AG
-.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__ACK__DR, CYREG_PRT0_DR
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__ACK__MASK, 0x40
-.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6
-.set SCSI_Out__ACK__PORT, 0
-.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__ACK__PS, CYREG_PRT0_PS
-.set SCSI_Out__ACK__SHIFT, 6
-.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__ATN__AG, CYREG_PRT4_AG
-.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__ATN__DR, CYREG_PRT4_DR
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__ATN__MASK, 0x04
-.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2
-.set SCSI_Out__ATN__PORT, 4
-.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__ATN__PS, CYREG_PRT4_PS
-.set SCSI_Out__ATN__SHIFT, 2
-.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__BSY__AG, CYREG_PRT0_AG
-.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__BSY__DR, CYREG_PRT0_DR
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__BSY__MASK, 0x80
-.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7
-.set SCSI_Out__BSY__PORT, 0
-.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__BSY__PS, CYREG_PRT0_PS
-.set SCSI_Out__BSY__SHIFT, 7
-.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__CD_raw__MASK, 0x04
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2
-.set SCSI_Out__CD_raw__PORT, 0
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__CD_raw__SHIFT, 2
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__DBP_raw__MASK, 0x08
-.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3
-.set SCSI_Out__DBP_raw__PORT, 4
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS
-.set SCSI_Out__DBP_raw__SHIFT, 3
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__IO_raw__MASK, 0x01
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0
-.set SCSI_Out__IO_raw__PORT, 0
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__IO_raw__SHIFT, 0
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__MSG_raw__MASK, 0x10
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4
-.set SCSI_Out__MSG_raw__PORT, 0
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__MSG_raw__SHIFT, 4
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__REQ__MASK, 0x02
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1
-.set SCSI_Out__REQ__PORT, 0
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS
-.set SCSI_Out__REQ__SHIFT, 1
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__RST__AG, CYREG_PRT0_AG
-.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__RST__DR, CYREG_PRT0_DR
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__RST__MASK, 0x20
-.set SCSI_Out__RST__PC, CYREG_PRT0_PC5
-.set SCSI_Out__RST__PORT, 0
-.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__RST__PS, CYREG_PRT0_PS
-.set SCSI_Out__RST__SHIFT, 5
-.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__SEL__MASK, 0x08
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3
-.set SCSI_Out__SEL__PORT, 0
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
-.set SCSI_Out__SEL__SHIFT, 3
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
-
-/* USBFS_Dm */
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_RxStsReg__4__POS, 4
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
+.set SDCard_BSPIM_RxStsReg__5__POS, 5
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
+.set SDCard_BSPIM_RxStsReg__6__POS, 6
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
+.set SDCard_BSPIM_TxStsReg__0__POS, 0
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
+.set SDCard_BSPIM_TxStsReg__1__POS, 1
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
+.set SDCard_BSPIM_TxStsReg__2__POS, 2
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
+.set SDCard_BSPIM_TxStsReg__3__POS, 3
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_TxStsReg__4__POS, 4
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
 
-/* USBFS_Dp */
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+.set SD_SCK__0__MASK, 0x04
+.set SD_SCK__0__PC, CYREG_PRT3_PC2
+.set SD_SCK__0__PORT, 3
+.set SD_SCK__0__SHIFT, 2
+.set SD_SCK__AG, CYREG_PRT3_AG
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX
+.set SD_SCK__BIE, CYREG_PRT3_BIE
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_SCK__BYP, CYREG_PRT3_BYP
+.set SD_SCK__CTL, CYREG_PRT3_CTL
+.set SD_SCK__DM0, CYREG_PRT3_DM0
+.set SD_SCK__DM1, CYREG_PRT3_DM1
+.set SD_SCK__DM2, CYREG_PRT3_DM2
+.set SD_SCK__DR, CYREG_PRT3_DR
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_SCK__MASK, 0x04
+.set SD_SCK__PORT, 3
+.set SD_SCK__PRT, CYREG_PRT3_PRT
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_SCK__PS, CYREG_PRT3_PS
+.set SD_SCK__SHIFT, 2
+.set SD_SCK__SLW, CYREG_PRT3_SLW
 
 /* SCSI_In */
 .set SCSI_In__0__AG, CYREG_PRT2_AG
@@ -2648,332 +757,2228 @@
 .set SCSI_In__REQ__SHIFT, 2
 .set SCSI_In__REQ__SLW, CYREG_PRT5_SLW
 
-/* SD_DAT1 */
-.set SD_DAT1__0__MASK, 0x01
-.set SD_DAT1__0__PC, CYREG_PRT3_PC0
-.set SD_DAT1__0__PORT, 3
-.set SD_DAT1__0__SHIFT, 0
-.set SD_DAT1__AG, CYREG_PRT3_AG
-.set SD_DAT1__AMUX, CYREG_PRT3_AMUX
-.set SD_DAT1__BIE, CYREG_PRT3_BIE
-.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_DAT1__BYP, CYREG_PRT3_BYP
-.set SD_DAT1__CTL, CYREG_PRT3_CTL
-.set SD_DAT1__DM0, CYREG_PRT3_DM0
-.set SD_DAT1__DM1, CYREG_PRT3_DM1
-.set SD_DAT1__DM2, CYREG_PRT3_DM2
-.set SD_DAT1__DR, CYREG_PRT3_DR
-.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_DAT1__MASK, 0x01
-.set SD_DAT1__PORT, 3
-.set SD_DAT1__PRT, CYREG_PRT3_PRT
-.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_DAT1__PS, CYREG_PRT3_PS
-.set SD_DAT1__SHIFT, 0
-.set SD_DAT1__SLW, CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__0__MASK, 0x10
+.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__0__PORT, 12
+.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__0__SHIFT, 4
+.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__1__MASK, 0x80
+.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7
+.set SCSI_In_DBx__1__PORT, 2
+.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__1__SHIFT, 7
+.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__2__MASK, 0x40
+.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6
+.set SCSI_In_DBx__2__PORT, 2
+.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__2__SHIFT, 6
+.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__3__MASK, 0x20
+.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__3__PORT, 2
+.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__3__SHIFT, 5
+.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__4__MASK, 0x10
+.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__4__PORT, 2
+.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__4__SHIFT, 4
+.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__5__MASK, 0x08
+.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3
+.set SCSI_In_DBx__5__PORT, 2
+.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__5__SHIFT, 3
+.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__6__MASK, 0x04
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2
+.set SCSI_In_DBx__6__PORT, 2
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__6__SHIFT, 2
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__7__MASK, 0x02
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1
+.set SCSI_In_DBx__7__PORT, 2
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__7__SHIFT, 1
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__DB0__MASK, 0x10
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__DB0__PORT, 12
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__DB0__SHIFT, 4
+.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB1__MASK, 0x80
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7
+.set SCSI_In_DBx__DB1__PORT, 2
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB1__SHIFT, 7
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB2__MASK, 0x40
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6
+.set SCSI_In_DBx__DB2__PORT, 2
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB2__SHIFT, 6
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB3__MASK, 0x20
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__DB3__PORT, 2
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB3__SHIFT, 5
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB4__MASK, 0x10
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__DB4__PORT, 2
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB4__SHIFT, 4
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB5__MASK, 0x08
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3
+.set SCSI_In_DBx__DB5__PORT, 2
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB5__SHIFT, 3
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB6__MASK, 0x04
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2
+.set SCSI_In_DBx__DB6__PORT, 2
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB6__SHIFT, 2
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB7__MASK, 0x02
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1
+.set SCSI_In_DBx__DB7__PORT, 2
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB7__SHIFT, 1
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
+
+/* SD_DAT1 */
+.set SD_DAT1__0__MASK, 0x01
+.set SD_DAT1__0__PC, CYREG_PRT3_PC0
+.set SD_DAT1__0__PORT, 3
+.set SD_DAT1__0__SHIFT, 0
+.set SD_DAT1__AG, CYREG_PRT3_AG
+.set SD_DAT1__AMUX, CYREG_PRT3_AMUX
+.set SD_DAT1__BIE, CYREG_PRT3_BIE
+.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_DAT1__BYP, CYREG_PRT3_BYP
+.set SD_DAT1__CTL, CYREG_PRT3_CTL
+.set SD_DAT1__DM0, CYREG_PRT3_DM0
+.set SD_DAT1__DM1, CYREG_PRT3_DM1
+.set SD_DAT1__DM2, CYREG_PRT3_DM2
+.set SD_DAT1__DR, CYREG_PRT3_DR
+.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_DAT1__MASK, 0x01
+.set SD_DAT1__PORT, 3
+.set SD_DAT1__PRT, CYREG_PRT3_PRT
+.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_DAT1__PS, CYREG_PRT3_PS
+.set SD_DAT1__SHIFT, 0
+.set SD_DAT1__SLW, CYREG_PRT3_SLW
+
+/* SD_DAT2 */
+.set SD_DAT2__0__MASK, 0x20
+.set SD_DAT2__0__PC, CYREG_PRT3_PC5
+.set SD_DAT2__0__PORT, 3
+.set SD_DAT2__0__SHIFT, 5
+.set SD_DAT2__AG, CYREG_PRT3_AG
+.set SD_DAT2__AMUX, CYREG_PRT3_AMUX
+.set SD_DAT2__BIE, CYREG_PRT3_BIE
+.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_DAT2__BYP, CYREG_PRT3_BYP
+.set SD_DAT2__CTL, CYREG_PRT3_CTL
+.set SD_DAT2__DM0, CYREG_PRT3_DM0
+.set SD_DAT2__DM1, CYREG_PRT3_DM1
+.set SD_DAT2__DM2, CYREG_PRT3_DM2
+.set SD_DAT2__DR, CYREG_PRT3_DR
+.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_DAT2__MASK, 0x20
+.set SD_DAT2__PORT, 3
+.set SD_DAT2__PRT, CYREG_PRT3_PRT
+.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_DAT2__PS, CYREG_PRT3_PS
+.set SD_DAT2__SHIFT, 5
+.set SD_DAT2__SLW, CYREG_PRT3_SLW
+
+/* SD_MISO */
+.set SD_MISO__0__MASK, 0x02
+.set SD_MISO__0__PC, CYREG_PRT3_PC1
+.set SD_MISO__0__PORT, 3
+.set SD_MISO__0__SHIFT, 1
+.set SD_MISO__AG, CYREG_PRT3_AG
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX
+.set SD_MISO__BIE, CYREG_PRT3_BIE
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MISO__BYP, CYREG_PRT3_BYP
+.set SD_MISO__CTL, CYREG_PRT3_CTL
+.set SD_MISO__DM0, CYREG_PRT3_DM0
+.set SD_MISO__DM1, CYREG_PRT3_DM1
+.set SD_MISO__DM2, CYREG_PRT3_DM2
+.set SD_MISO__DR, CYREG_PRT3_DR
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MISO__MASK, 0x02
+.set SD_MISO__PORT, 3
+.set SD_MISO__PRT, CYREG_PRT3_PRT
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MISO__PS, CYREG_PRT3_PS
+.set SD_MISO__SHIFT, 1
+.set SD_MISO__SLW, CYREG_PRT3_SLW
+
+/* SD_MOSI */
+.set SD_MOSI__0__MASK, 0x08
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3
+.set SD_MOSI__0__PORT, 3
+.set SD_MOSI__0__SHIFT, 3
+.set SD_MOSI__AG, CYREG_PRT3_AG
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
+.set SD_MOSI__BIE, CYREG_PRT3_BIE
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MOSI__BYP, CYREG_PRT3_BYP
+.set SD_MOSI__CTL, CYREG_PRT3_CTL
+.set SD_MOSI__DM0, CYREG_PRT3_DM0
+.set SD_MOSI__DM1, CYREG_PRT3_DM1
+.set SD_MOSI__DM2, CYREG_PRT3_DM2
+.set SD_MOSI__DR, CYREG_PRT3_DR
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MOSI__MASK, 0x08
+.set SD_MOSI__PORT, 3
+.set SD_MOSI__PRT, CYREG_PRT3_PRT
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MOSI__PS, CYREG_PRT3_PS
+.set SD_MOSI__SHIFT, 3
+.set SD_MOSI__SLW, CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
+.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SCSI_CLK__PM_STBY_MSK, 0x02
+
+/* SCSI_Out */
+.set SCSI_Out__0__AG, CYREG_PRT4_AG
+.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__0__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__0__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__0__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__0__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__0__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__0__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__0__DR, CYREG_PRT4_DR
+.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__0__MASK, 0x08
+.set SCSI_Out__0__PC, CYREG_PRT4_PC3
+.set SCSI_Out__0__PORT, 4
+.set SCSI_Out__0__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__0__PS, CYREG_PRT4_PS
+.set SCSI_Out__0__SHIFT, 3
+.set SCSI_Out__0__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__1__AG, CYREG_PRT4_AG
+.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__1__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__1__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__1__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__1__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__1__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__1__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__1__DR, CYREG_PRT4_DR
+.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__1__MASK, 0x04
+.set SCSI_Out__1__PC, CYREG_PRT4_PC2
+.set SCSI_Out__1__PORT, 4
+.set SCSI_Out__1__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__1__PS, CYREG_PRT4_PS
+.set SCSI_Out__1__SHIFT, 2
+.set SCSI_Out__1__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__2__AG, CYREG_PRT0_AG
+.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__2__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__2__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__2__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__2__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__2__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__2__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__2__DR, CYREG_PRT0_DR
+.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__2__MASK, 0x80
+.set SCSI_Out__2__PC, CYREG_PRT0_PC7
+.set SCSI_Out__2__PORT, 0
+.set SCSI_Out__2__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__2__PS, CYREG_PRT0_PS
+.set SCSI_Out__2__SHIFT, 7
+.set SCSI_Out__2__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__3__AG, CYREG_PRT0_AG
+.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__3__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__3__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__3__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__3__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__3__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__3__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__3__DR, CYREG_PRT0_DR
+.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__3__MASK, 0x40
+.set SCSI_Out__3__PC, CYREG_PRT0_PC6
+.set SCSI_Out__3__PORT, 0
+.set SCSI_Out__3__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__3__PS, CYREG_PRT0_PS
+.set SCSI_Out__3__SHIFT, 6
+.set SCSI_Out__3__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__4__AG, CYREG_PRT0_AG
+.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__4__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__4__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__4__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__4__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__4__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__4__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__4__DR, CYREG_PRT0_DR
+.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__4__MASK, 0x20
+.set SCSI_Out__4__PC, CYREG_PRT0_PC5
+.set SCSI_Out__4__PORT, 0
+.set SCSI_Out__4__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__4__PS, CYREG_PRT0_PS
+.set SCSI_Out__4__SHIFT, 5
+.set SCSI_Out__4__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__5__AG, CYREG_PRT0_AG
+.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__5__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__5__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__5__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__5__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__5__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__5__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__5__DR, CYREG_PRT0_DR
+.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__5__MASK, 0x10
+.set SCSI_Out__5__PC, CYREG_PRT0_PC4
+.set SCSI_Out__5__PORT, 0
+.set SCSI_Out__5__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__5__PS, CYREG_PRT0_PS
+.set SCSI_Out__5__SHIFT, 4
+.set SCSI_Out__5__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__6__AG, CYREG_PRT0_AG
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__6__DR, CYREG_PRT0_DR
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__6__MASK, 0x08
+.set SCSI_Out__6__PC, CYREG_PRT0_PC3
+.set SCSI_Out__6__PORT, 0
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__6__PS, CYREG_PRT0_PS
+.set SCSI_Out__6__SHIFT, 3
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__7__AG, CYREG_PRT0_AG
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__7__DR, CYREG_PRT0_DR
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__7__MASK, 0x04
+.set SCSI_Out__7__PC, CYREG_PRT0_PC2
+.set SCSI_Out__7__PORT, 0
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__7__PS, CYREG_PRT0_PS
+.set SCSI_Out__7__SHIFT, 2
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__8__AG, CYREG_PRT0_AG
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__8__DR, CYREG_PRT0_DR
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__8__MASK, 0x02
+.set SCSI_Out__8__PC, CYREG_PRT0_PC1
+.set SCSI_Out__8__PORT, 0
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__8__PS, CYREG_PRT0_PS
+.set SCSI_Out__8__SHIFT, 1
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__9__AG, CYREG_PRT0_AG
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__9__DR, CYREG_PRT0_DR
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__9__MASK, 0x01
+.set SCSI_Out__9__PC, CYREG_PRT0_PC0
+.set SCSI_Out__9__PORT, 0
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__9__PS, CYREG_PRT0_PS
+.set SCSI_Out__9__SHIFT, 0
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__ACK__AG, CYREG_PRT0_AG
+.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__ACK__DR, CYREG_PRT0_DR
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__ACK__MASK, 0x40
+.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6
+.set SCSI_Out__ACK__PORT, 0
+.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__ACK__PS, CYREG_PRT0_PS
+.set SCSI_Out__ACK__SHIFT, 6
+.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__ATN__AG, CYREG_PRT4_AG
+.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__ATN__DR, CYREG_PRT4_DR
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__ATN__MASK, 0x04
+.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2
+.set SCSI_Out__ATN__PORT, 4
+.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__ATN__PS, CYREG_PRT4_PS
+.set SCSI_Out__ATN__SHIFT, 2
+.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__BSY__AG, CYREG_PRT0_AG
+.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__BSY__DR, CYREG_PRT0_DR
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__BSY__MASK, 0x80
+.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7
+.set SCSI_Out__BSY__PORT, 0
+.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__BSY__PS, CYREG_PRT0_PS
+.set SCSI_Out__BSY__SHIFT, 7
+.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__CD_raw__MASK, 0x04
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2
+.set SCSI_Out__CD_raw__PORT, 0
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__CD_raw__SHIFT, 2
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__DBP_raw__MASK, 0x08
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3
+.set SCSI_Out__DBP_raw__PORT, 4
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS
+.set SCSI_Out__DBP_raw__SHIFT, 3
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__IO_raw__MASK, 0x01
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0
+.set SCSI_Out__IO_raw__PORT, 0
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__IO_raw__SHIFT, 0
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__MSG_raw__MASK, 0x10
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4
+.set SCSI_Out__MSG_raw__PORT, 0
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__MSG_raw__SHIFT, 4
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__REQ__MASK, 0x02
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1
+.set SCSI_Out__REQ__PORT, 0
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS
+.set SCSI_Out__REQ__SHIFT, 1
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__RST__AG, CYREG_PRT0_AG
+.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__RST__DR, CYREG_PRT0_DR
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__RST__MASK, 0x20
+.set SCSI_Out__RST__PC, CYREG_PRT0_PC5
+.set SCSI_Out__RST__PORT, 0
+.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__RST__PS, CYREG_PRT0_PS
+.set SCSI_Out__RST__SHIFT, 5
+.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__SEL__MASK, 0x08
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3
+.set SCSI_Out__SEL__PORT, 0
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
+.set SCSI_Out__SEL__SHIFT, 3
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+
+/* SCSI_Out_Ctl */
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
+
+/* SCSI_Out_DBx */
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x08
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3
+.set SCSI_Out_DBx__0__PORT, 6
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__0__SHIFT, 3
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x04
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2
+.set SCSI_Out_DBx__1__PORT, 6
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__1__SHIFT, 2
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__2__MASK, 0x02
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1
+.set SCSI_Out_DBx__2__PORT, 6
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__2__SHIFT, 1
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x01
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0
+.set SCSI_Out_DBx__3__PORT, 6
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__3__SHIFT, 0
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x80
+.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7
+.set SCSI_Out_DBx__4__PORT, 4
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__4__SHIFT, 7
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x40
+.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6
+.set SCSI_Out_DBx__5__PORT, 4
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__5__SHIFT, 6
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x20
+.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5
+.set SCSI_Out_DBx__6__PORT, 4
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__6__SHIFT, 5
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x10
+.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4
+.set SCSI_Out_DBx__7__PORT, 4
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__7__SHIFT, 4
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x08
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3
+.set SCSI_Out_DBx__DB0__PORT, 6
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 3
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x04
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2
+.set SCSI_Out_DBx__DB1__PORT, 6
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 2
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB2__MASK, 0x02
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1
+.set SCSI_Out_DBx__DB2__PORT, 6
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 1
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x01
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0
+.set SCSI_Out_DBx__DB3__PORT, 6
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 0
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x80
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7
+.set SCSI_Out_DBx__DB4__PORT, 4
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 7
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x40
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6
+.set SCSI_Out_DBx__DB5__PORT, 4
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 6
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x20
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5
+.set SCSI_Out_DBx__DB6__PORT, 4
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 5
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x10
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4
+.set SCSI_Out_DBx__DB7__PORT, 4
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 4
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW
+
+/* SD_RX_DMA */
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_RX_DMA__DRQ_NUMBER, 2
+.set SD_RX_DMA__NUMBEROF_TDS, 0
+.set SD_RX_DMA__PRIORITY, 2
+.set SD_RX_DMA__TERMIN_EN, 0
+.set SD_RX_DMA__TERMIN_SEL, 0
+.set SD_RX_DMA__TERMOUT0_EN, 1
+.set SD_RX_DMA__TERMOUT0_SEL, 2
+.set SD_RX_DMA__TERMOUT1_EN, 0
+.set SD_RX_DMA__TERMOUT1_SEL, 0
+
+/* SD_RX_DMA_COMPLETE */
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_TX_DMA__DRQ_NUMBER, 3
+.set SD_TX_DMA__NUMBEROF_TDS, 0
+.set SD_TX_DMA__PRIORITY, 2
+.set SD_TX_DMA__TERMIN_EN, 0
+.set SD_TX_DMA__TERMIN_SEL, 0
+.set SD_TX_DMA__TERMOUT0_EN, 1
+.set SD_TX_DMA__TERMOUT0_SEL, 3
+.set SD_TX_DMA__TERMOUT1_EN, 0
+.set SD_TX_DMA__TERMOUT1_SEL, 0
+
+/* SD_TX_DMA_COMPLETE */
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+.set SCSI_Noise__0__AG, CYREG_PRT12_AG
+.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP
+.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0
+.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1
+.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2
+.set SCSI_Noise__0__DR, CYREG_PRT12_DR
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_Noise__0__MASK, 0x20
+.set SCSI_Noise__0__PC, CYREG_PRT12_PC5
+.set SCSI_Noise__0__PORT, 12
+.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_Noise__0__PS, CYREG_PRT12_PS
+.set SCSI_Noise__0__SHIFT, 5
+.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__1__MASK, 0x10
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC4
+.set SCSI_Noise__1__PORT, 6
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS
+.set SCSI_Noise__1__SHIFT, 4
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__2__AG, CYREG_PRT5_AG
+.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP
+.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL
+.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0
+.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1
+.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2
+.set SCSI_Noise__2__DR, CYREG_PRT5_DR
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Noise__2__MASK, 0x01
+.set SCSI_Noise__2__PC, CYREG_PRT5_PC0
+.set SCSI_Noise__2__PORT, 5
+.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Noise__2__PS, CYREG_PRT5_PS
+.set SCSI_Noise__2__SHIFT, 0
+.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW
+.set SCSI_Noise__3__AG, CYREG_PRT6_AG
+.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__3__DR, CYREG_PRT6_DR
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__3__MASK, 0x40
+.set SCSI_Noise__3__PC, CYREG_PRT6_PC6
+.set SCSI_Noise__3__PORT, 6
+.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__3__PS, CYREG_PRT6_PS
+.set SCSI_Noise__3__SHIFT, 6
+.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__4__MASK, 0x20
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC5
+.set SCSI_Noise__4__PORT, 6
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS
+.set SCSI_Noise__4__SHIFT, 5
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__ACK__MASK, 0x20
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5
+.set SCSI_Noise__ACK__PORT, 6
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
+.set SCSI_Noise__ACK__SHIFT, 5
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG
+.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP
+.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0
+.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1
+.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2
+.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_Noise__ATN__MASK, 0x20
+.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5
+.set SCSI_Noise__ATN__PORT, 12
+.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS
+.set SCSI_Noise__ATN__SHIFT, 5
+.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__BSY__MASK, 0x10
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4
+.set SCSI_Noise__BSY__PORT, 6
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
+.set SCSI_Noise__BSY__SHIFT, 4
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__RST__AG, CYREG_PRT6_AG
+.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__RST__DR, CYREG_PRT6_DR
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__RST__MASK, 0x40
+.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6
+.set SCSI_Noise__RST__PORT, 6
+.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__RST__PS, CYREG_PRT6_PS
+.set SCSI_Noise__RST__SHIFT, 6
+.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP
+.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL
+.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0
+.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1
+.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2
+.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Noise__SEL__MASK, 0x01
+.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0
+.set SCSI_Noise__SEL__PORT, 5
+.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS
+.set SCSI_Noise__SEL__SHIFT, 0
+.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW
+
+/* scsiTarget */
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB05_06_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB05_06_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB05_06_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB05_06_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB05_06_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB05_06_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB05_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB05_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB05_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB05_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB05_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB05_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB05_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB05_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB05_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB05_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB05_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB05_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB05_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB05_MSK
+.set scsiTarget_StatusReg__0__MASK, 0x01
+.set scsiTarget_StatusReg__0__POS, 0
+.set scsiTarget_StatusReg__1__MASK, 0x02
+.set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set scsiTarget_StatusReg__2__MASK, 0x04
+.set scsiTarget_StatusReg__2__POS, 2
+.set scsiTarget_StatusReg__3__MASK, 0x08
+.set scsiTarget_StatusReg__3__POS, 3
+.set scsiTarget_StatusReg__4__MASK, 0x10
+.set scsiTarget_StatusReg__4__POS, 4
+.set scsiTarget_StatusReg__MASK, 0x1F
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST
 
-/* SD_DAT2 */
-.set SD_DAT2__0__MASK, 0x20
-.set SD_DAT2__0__PC, CYREG_PRT3_PC5
-.set SD_DAT2__0__PORT, 3
-.set SD_DAT2__0__SHIFT, 5
-.set SD_DAT2__AG, CYREG_PRT3_AG
-.set SD_DAT2__AMUX, CYREG_PRT3_AMUX
-.set SD_DAT2__BIE, CYREG_PRT3_BIE
-.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_DAT2__BYP, CYREG_PRT3_BYP
-.set SD_DAT2__CTL, CYREG_PRT3_CTL
-.set SD_DAT2__DM0, CYREG_PRT3_DM0
-.set SD_DAT2__DM1, CYREG_PRT3_DM1
-.set SD_DAT2__DM2, CYREG_PRT3_DM2
-.set SD_DAT2__DR, CYREG_PRT3_DR
-.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_DAT2__MASK, 0x20
-.set SD_DAT2__PORT, 3
-.set SD_DAT2__PRT, CYREG_PRT3_PRT
-.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_DAT2__PS, CYREG_PRT3_PS
-.set SD_DAT2__SHIFT, 5
-.set SD_DAT2__SLW, CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SD_MISO */
-.set SD_MISO__0__MASK, 0x02
-.set SD_MISO__0__PC, CYREG_PRT3_PC1
-.set SD_MISO__0__PORT, 3
-.set SD_MISO__0__SHIFT, 1
-.set SD_MISO__AG, CYREG_PRT3_AG
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX
-.set SD_MISO__BIE, CYREG_PRT3_BIE
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MISO__BYP, CYREG_PRT3_BYP
-.set SD_MISO__CTL, CYREG_PRT3_CTL
-.set SD_MISO__DM0, CYREG_PRT3_DM0
-.set SD_MISO__DM1, CYREG_PRT3_DM1
-.set SD_MISO__DM2, CYREG_PRT3_DM2
-.set SD_MISO__DR, CYREG_PRT3_DR
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MISO__MASK, 0x02
-.set SD_MISO__PORT, 3
-.set SD_MISO__PRT, CYREG_PRT3_PRT
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MISO__PS, CYREG_PRT3_PS
-.set SD_MISO__SHIFT, 1
-.set SD_MISO__SLW, CYREG_PRT3_SLW
+/* Debug_Timer_TimerHW */
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_RX_DMA__DRQ_NUMBER, 0
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0
+.set SCSI_RX_DMA__PRIORITY, 2
+.set SCSI_RX_DMA__TERMIN_EN, 0
+.set SCSI_RX_DMA__TERMIN_SEL, 0
+.set SCSI_RX_DMA__TERMOUT0_EN, 1
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0
+.set SCSI_RX_DMA__TERMOUT1_EN, 0
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0
+
+/* SCSI_RX_DMA_COMPLETE */
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_TX_DMA__DRQ_NUMBER, 1
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0
+.set SCSI_TX_DMA__PRIORITY, 2
+.set SCSI_TX_DMA__TERMIN_EN, 0
+.set SCSI_TX_DMA__TERMIN_SEL, 0
+.set SCSI_TX_DMA__TERMOUT0_EN, 1
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1
+.set SCSI_TX_DMA__TERMOUT1_EN, 0
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0
+
+/* SCSI_TX_DMA_COMPLETE */
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
+.set SD_Data_Clk__INDEX, 0x00
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SD_Data_Clk__PM_ACT_MSK, 0x01
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SD_Data_Clk__PM_STBY_MSK, 0x01
 
-/* SD_MOSI */
-.set SD_MOSI__0__MASK, 0x08
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3
-.set SD_MOSI__0__PORT, 3
-.set SD_MOSI__0__SHIFT, 3
-.set SD_MOSI__AG, CYREG_PRT3_AG
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
-.set SD_MOSI__BIE, CYREG_PRT3_BIE
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MOSI__BYP, CYREG_PRT3_BYP
-.set SD_MOSI__CTL, CYREG_PRT3_CTL
-.set SD_MOSI__DM0, CYREG_PRT3_DM0
-.set SD_MOSI__DM1, CYREG_PRT3_DM1
-.set SD_MOSI__DM2, CYREG_PRT3_DM2
-.set SD_MOSI__DR, CYREG_PRT3_DR
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MOSI__MASK, 0x08
-.set SD_MOSI__PORT, 3
-.set SD_MOSI__PRT, CYREG_PRT3_PRT
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MOSI__PS, CYREG_PRT3_PS
-.set SD_MOSI__SHIFT, 3
-.set SD_MOSI__SLW, CYREG_PRT3_SLW
+/* timer_clock */
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
+.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
+.set timer_clock__INDEX, 0x02
+.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set timer_clock__PM_ACT_MSK, 0x04
+.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set timer_clock__PM_STBY_MSK, 0x04
 
-/* SD_SCK */
-.set SD_SCK__0__MASK, 0x04
-.set SD_SCK__0__PC, CYREG_PRT3_PC2
-.set SD_SCK__0__PORT, 3
-.set SD_SCK__0__SHIFT, 2
-.set SD_SCK__AG, CYREG_PRT3_AG
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX
-.set SD_SCK__BIE, CYREG_PRT3_BIE
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_SCK__BYP, CYREG_PRT3_BYP
-.set SD_SCK__CTL, CYREG_PRT3_CTL
-.set SD_SCK__DM0, CYREG_PRT3_DM0
-.set SD_SCK__DM1, CYREG_PRT3_DM1
-.set SD_SCK__DM2, CYREG_PRT3_DM2
-.set SD_SCK__DR, CYREG_PRT3_DR
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_SCK__MASK, 0x04
-.set SD_SCK__PORT, 3
-.set SD_SCK__PRT, CYREG_PRT3_PRT
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_SCK__PS, CYREG_PRT3_PS
-.set SD_SCK__SHIFT, 2
-.set SD_SCK__SLW, CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RST_ISR__INTC_MASK, 0x04
+.set SCSI_RST_ISR__INTC_NUMBER, 2
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SD_CD */
-.set SD_CD__0__MASK, 0x40
-.set SD_CD__0__PC, CYREG_PRT3_PC6
-.set SD_CD__0__PORT, 3
-.set SD_CD__0__SHIFT, 6
-.set SD_CD__AG, CYREG_PRT3_AG
-.set SD_CD__AMUX, CYREG_PRT3_AMUX
-.set SD_CD__BIE, CYREG_PRT3_BIE
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CD__BYP, CYREG_PRT3_BYP
-.set SD_CD__CTL, CYREG_PRT3_CTL
-.set SD_CD__DM0, CYREG_PRT3_DM0
-.set SD_CD__DM1, CYREG_PRT3_DM1
-.set SD_CD__DM2, CYREG_PRT3_DM2
-.set SD_CD__DR, CYREG_PRT3_DR
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CD__MASK, 0x40
-.set SD_CD__PORT, 3
-.set SD_CD__PRT, CYREG_PRT3_PRT
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CD__PS, CYREG_PRT3_PS
-.set SD_CD__SHIFT, 6
-.set SD_CD__SLW, CYREG_PRT3_SLW
+/* SCSI_Filtered */
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST
 
-/* SD_CS */
-.set SD_CS__0__MASK, 0x10
-.set SD_CS__0__PC, CYREG_PRT3_PC4
-.set SD_CS__0__PORT, 3
-.set SD_CS__0__SHIFT, 4
-.set SD_CS__AG, CYREG_PRT3_AG
-.set SD_CS__AMUX, CYREG_PRT3_AMUX
-.set SD_CS__BIE, CYREG_PRT3_BIE
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CS__BYP, CYREG_PRT3_BYP
-.set SD_CS__CTL, CYREG_PRT3_CTL
-.set SD_CS__DM0, CYREG_PRT3_DM0
-.set SD_CS__DM1, CYREG_PRT3_DM1
-.set SD_CS__DM2, CYREG_PRT3_DM2
-.set SD_CS__DR, CYREG_PRT3_DR
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CS__MASK, 0x10
-.set SD_CS__PORT, 3
-.set SD_CS__PRT, CYREG_PRT3_PRT
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CS__PS, CYREG_PRT3_PS
-.set SD_CS__SHIFT, 4
-.set SD_CS__SLW, CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
 
-/* LED1 */
-.set LED1__0__MASK, 0x08
-.set LED1__0__PC, CYREG_PRT12_PC3
-.set LED1__0__PORT, 12
-.set LED1__0__SHIFT, 3
-.set LED1__AG, CYREG_PRT12_AG
-.set LED1__BIE, CYREG_PRT12_BIE
-.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set LED1__BYP, CYREG_PRT12_BYP
-.set LED1__DM0, CYREG_PRT12_DM0
-.set LED1__DM1, CYREG_PRT12_DM1
-.set LED1__DM2, CYREG_PRT12_DM2
-.set LED1__DR, CYREG_PRT12_DR
-.set LED1__INP_DIS, CYREG_PRT12_INP_DIS
-.set LED1__MASK, 0x08
-.set LED1__PORT, 12
-.set LED1__PRT, CYREG_PRT12_PRT
-.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set LED1__PS, CYREG_PRT12_PS
-.set LED1__SHIFT, 3
-.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set LED1__SLW, CYREG_PRT12_SLW
+/* SCSI_Parity_Error */
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
-.set CYDEV_CHIP_MEMBER_5B, 4
-.set CYDEV_CHIP_FAMILY_PSOC5, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 4
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
 .set BCLK__BUS_CLK__HZ, 50000000
 .set BCLK__BUS_CLK__KHZ, 50000
 .set BCLK__BUS_CLK__MHZ, 50
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 3
-.set CYDEV_CHIP_DIE_PSOC4A, 2
+.set CYDEV_CHIP_DIE_PANTHER, 6
+.set CYDEV_CHIP_DIE_PSOC4A, 3
+.set CYDEV_CHIP_DIE_PSOC5LP, 5
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
+.set CYDEV_CHIP_FAMILY_PSOC5, 3
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 2
-.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_4A, 3
+.set CYDEV_CHIP_MEMBER_4D, 2
+.set CYDEV_CHIP_MEMBER_4F, 4
+.set CYDEV_CHIP_MEMBER_5A, 6
+.set CYDEV_CHIP_MEMBER_5B, 5
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_3A_ES1, 0
 .set CYDEV_CHIP_REVISION_3A_ES2, 1
 .set CYDEV_CHIP_REVISION_3A_ES3, 3
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
 .set CYDEV_CHIP_REVISION_5B_ES0, 0
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
 .set CYDEV_CONFIGURATION_COMPRESSED, 1
 .set CYDEV_CONFIGURATION_DMA, 0
 .set CYDEV_CONFIGURATION_ECC, 0
 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
 .set CYDEV_CONFIGURATION_MODE_DMA, 2
 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DEBUGGING_DPS_Disable, 3
 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1
 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
 .set CYDEV_DEBUGGING_ENABLE, 1
 .set CYDEV_DEBUGGING_XRES, 0
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24
 .set CYDEV_ECC_ENABLE, 0
 .set CYDEV_HEAP_SIZE, 0x0400
@@ -2985,7 +2990,7 @@
 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
 .set CYDEV_PROJ_TYPE_STANDARD, 0
 .set CYDEV_PROTECTION_ENABLE, 0
-.set CYDEV_STACK_SIZE, 0x2000
+.set CYDEV_STACK_SIZE, 0x1000
 .set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1
 .set CYDEV_USE_BUNDLED_CMSIS, 1
 .set CYDEV_VARIABLE_VDDA, 0
@@ -2995,13 +3000,30 @@
 .set CYDEV_VDDIO1_MV, 5000
 .set CYDEV_VDDIO2_MV, 5000
 .set CYDEV_VDDIO3_MV, 3300
-.set CYDEV_VIO0, 5
 .set CYDEV_VIO0_MV, 5000
-.set CYDEV_VIO1, 5
 .set CYDEV_VIO1_MV, 5000
-.set CYDEV_VIO2, 5
 .set CYDEV_VIO2_MV, 5000
 .set CYDEV_VIO3_MV, 3300
+.set CYIPBLOCK_ARM_CM3_VERSION, 0
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
+.set CYIPBLOCK_P3_COMP_VERSION, 0
+.set CYIPBLOCK_P3_DMA_VERSION, 0
+.set CYIPBLOCK_P3_DRQ_VERSION, 0
+.set CYIPBLOCK_P3_EMIF_VERSION, 0
+.set CYIPBLOCK_P3_I2C_VERSION, 0
+.set CYIPBLOCK_P3_LCD_VERSION, 0
+.set CYIPBLOCK_P3_LPF_VERSION, 0
+.set CYIPBLOCK_P3_PM_VERSION, 0
+.set CYIPBLOCK_P3_TIMER_VERSION, 0
+.set CYIPBLOCK_P3_USB_VERSION, 0
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0
+.set CYIPBLOCK_P3_VREF_VERSION, 0
+.set CYIPBLOCK_S8_GPIO_VERSION, 0
+.set CYIPBLOCK_S8_IRQ_VERSION, 0
+.set CYIPBLOCK_S8_SAR_VERSION, 0
+.set CYIPBLOCK_S8_SIO_VERSION, 0
+.set CYIPBLOCK_S8_UDB_VERSION, 0
 .set DMA_CHANNELS_USED__MASK0, 0x0000000F
 .set CYDEV_BOOTLOADER_ENABLE, 0
 .endif
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index 51516708..2f123029 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -3,83 +3,110 @@
     INCLUDE cydeviceiar.inc
     INCLUDE cydeviceiar_trm.inc
 
-/* Debug_Timer_Interrupt */
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+/* LED1 */
+LED1__0__MASK EQU 0x08
+LED1__0__PC EQU CYREG_PRT12_PC3
+LED1__0__PORT EQU 12
+LED1__0__SHIFT EQU 3
+LED1__AG EQU CYREG_PRT12_AG
+LED1__BIE EQU CYREG_PRT12_BIE
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+LED1__BYP EQU CYREG_PRT12_BYP
+LED1__DM0 EQU CYREG_PRT12_DM0
+LED1__DM1 EQU CYREG_PRT12_DM1
+LED1__DM2 EQU CYREG_PRT12_DM2
+LED1__DR EQU CYREG_PRT12_DR
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS
+LED1__MASK EQU 0x08
+LED1__PORT EQU 12
+LED1__PRT EQU CYREG_PRT12_PRT
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+LED1__PS EQU CYREG_PRT12_PS
+LED1__SHIFT EQU 3
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+LED1__SLW EQU CYREG_PRT12_SLW
 
-/* SD_RX_DMA_COMPLETE */
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SD_CD */
+SD_CD__0__MASK EQU 0x40
+SD_CD__0__PC EQU CYREG_PRT3_PC6
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 6
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x40
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 6
+SD_CD__SLW EQU CYREG_PRT3_SLW
 
-/* SD_TX_DMA_COMPLETE */
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SD_CS */
+SD_CS__0__MASK EQU 0x10
+SD_CS__0__PC EQU CYREG_PRT3_PC4
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 4
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x10
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 4
+SD_CS__SLW EQU CYREG_PRT3_SLW
 
-/* SCSI_Parity_Error */
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
+/* USBFS_arb_int */
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* USBFS_bus_reset */
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -91,99 +118,131 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_PHASE */
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-
-/* SCSI_Filtered */
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST
-
-/* SCSI_Out_Bits */
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-
-/* USBFS_arb_int */
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* USBFS_Dm */
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x200
+USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -195,2186 +254,236 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_Ctl */
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+/* USBFS_USB */
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x08
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__0__PORT EQU 6
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__0__SHIFT EQU 3
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x04
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__1__PORT EQU 6
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__1__SHIFT EQU 2
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x02
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 1
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x01
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 0
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__4__PORT EQU 4
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__5__PORT EQU 4
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x20
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__6__PORT EQU 4
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__6__SHIFT EQU 5
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x10
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__7__PORT EQU 4
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__7__SHIFT EQU 4
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x08
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__DB0__PORT EQU 6
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 3
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x04
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__DB1__PORT EQU 6
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 2
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x02
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 1
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x01
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 0
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__DB4__PORT EQU 4
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__DB5__PORT EQU 4
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x20
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__DB6__PORT EQU 4
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 5
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x10
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__DB7__PORT EQU 4
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 4
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
-
-/* SCSI_RST_ISR */
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__0__MASK EQU 0x10
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__0__PORT EQU 12
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__0__SHIFT EQU 4
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x80
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7
-SCSI_In_DBx__1__PORT EQU 2
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__1__SHIFT EQU 7
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__2__MASK EQU 0x40
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__2__PORT EQU 2
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__2__SHIFT EQU 6
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x20
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__3__PORT EQU 2
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__3__SHIFT EQU 5
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__4__MASK EQU 0x10
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__4__PORT EQU 2
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__4__SHIFT EQU 4
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__5__MASK EQU 0x08
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3
-SCSI_In_DBx__5__PORT EQU 2
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__5__SHIFT EQU 3
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x04
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 2
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x02
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1
-SCSI_In_DBx__7__PORT EQU 2
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__7__SHIFT EQU 1
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB0__MASK EQU 0x10
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB0__PORT EQU 12
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB0__SHIFT EQU 4
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x80
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7
-SCSI_In_DBx__DB1__PORT EQU 2
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB1__SHIFT EQU 7
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB2__MASK EQU 0x40
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__DB2__PORT EQU 2
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB2__SHIFT EQU 6
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x20
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__DB3__PORT EQU 2
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB3__SHIFT EQU 5
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB4__MASK EQU 0x10
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB4__PORT EQU 2
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB4__SHIFT EQU 4
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB5__MASK EQU 0x08
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3
-SCSI_In_DBx__DB5__PORT EQU 2
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB5__SHIFT EQU 3
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x04
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 2
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x02
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1
-SCSI_In_DBx__DB7__PORT EQU 2
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB7__SHIFT EQU 1
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SCSI_TX_DMA */
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_Data_Clk */
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-/* timer_clock */
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
-
-/* SCSI_Noise */
-SCSI_Noise__0__AG EQU CYREG_PRT12_AG
-SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP
-SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0
-SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1
-SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2
-SCSI_Noise__0__DR EQU CYREG_PRT12_DR
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Noise__0__MASK EQU 0x20
-SCSI_Noise__0__PC EQU CYREG_PRT12_PC5
-SCSI_Noise__0__PORT EQU 12
-SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Noise__0__PS EQU CYREG_PRT12_PS
-SCSI_Noise__0__SHIFT EQU 5
-SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__1__MASK EQU 0x10
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC4
-SCSI_Noise__1__PORT EQU 6
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS
-SCSI_Noise__1__SHIFT EQU 4
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__2__AG EQU CYREG_PRT5_AG
-SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP
-SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL
-SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0
-SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1
-SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2
-SCSI_Noise__2__DR EQU CYREG_PRT5_DR
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Noise__2__MASK EQU 0x01
-SCSI_Noise__2__PC EQU CYREG_PRT5_PC0
-SCSI_Noise__2__PORT EQU 5
-SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Noise__2__PS EQU CYREG_PRT5_PS
-SCSI_Noise__2__SHIFT EQU 0
-SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW
-SCSI_Noise__3__AG EQU CYREG_PRT6_AG
-SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__3__DR EQU CYREG_PRT6_DR
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__3__MASK EQU 0x40
-SCSI_Noise__3__PC EQU CYREG_PRT6_PC6
-SCSI_Noise__3__PORT EQU 6
-SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__3__PS EQU CYREG_PRT6_PS
-SCSI_Noise__3__SHIFT EQU 6
-SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__4__MASK EQU 0x20
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC5
-SCSI_Noise__4__PORT EQU 6
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS
-SCSI_Noise__4__SHIFT EQU 5
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__ACK__MASK EQU 0x20
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5
-SCSI_Noise__ACK__PORT EQU 6
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Noise__ACK__SHIFT EQU 5
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG
-SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2
-SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Noise__ATN__MASK EQU 0x20
-SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5
-SCSI_Noise__ATN__PORT EQU 12
-SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS
-SCSI_Noise__ATN__SHIFT EQU 5
-SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__BSY__MASK EQU 0x10
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4
-SCSI_Noise__BSY__PORT EQU 6
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Noise__BSY__SHIFT EQU 4
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__RST__AG EQU CYREG_PRT6_AG
-SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__RST__DR EQU CYREG_PRT6_DR
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__RST__MASK EQU 0x40
-SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6
-SCSI_Noise__RST__PORT EQU 6
-SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__RST__PS EQU CYREG_PRT6_PS
-SCSI_Noise__RST__SHIFT EQU 6
-SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP
-SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2
-SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Noise__SEL__MASK EQU 0x01
-SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0
-SCSI_Noise__SEL__PORT EQU 5
-SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS
-SCSI_Noise__SEL__SHIFT EQU 0
-SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW
-
-/* scsiTarget */
-scsiTarget_StatusReg__0__MASK EQU 0x01
-scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-scsiTarget_StatusReg__1__MASK EQU 0x02
-scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__2__MASK EQU 0x04
-scsiTarget_StatusReg__2__POS EQU 2
-scsiTarget_StatusReg__3__MASK EQU 0x08
-scsiTarget_StatusReg__3__POS EQU 3
-scsiTarget_StatusReg__4__MASK EQU 0x10
-scsiTarget_StatusReg__4__POS EQU 4
-scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB05_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB01_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB01_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB01_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB01_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB01_02_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB01_02_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB01_02_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB01_02_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB01_02_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB01_02_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB01_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB01_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB01_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB01_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB01_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB01_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB01_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB01_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB01_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 1
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_TX_DMA */
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* USBFS_USB */
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-/* SCSI_Out */
-SCSI_Out__0__AG EQU CYREG_PRT4_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__0__DR EQU CYREG_PRT4_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__0__MASK EQU 0x08
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3
-SCSI_Out__0__PORT EQU 4
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT4_PS
-SCSI_Out__0__SHIFT EQU 3
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__1__AG EQU CYREG_PRT4_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__1__DR EQU CYREG_PRT4_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__1__MASK EQU 0x04
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2
-SCSI_Out__1__PORT EQU 4
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT4_PS
-SCSI_Out__1__SHIFT EQU 2
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__2__AG EQU CYREG_PRT0_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__2__DR EQU CYREG_PRT0_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__2__MASK EQU 0x80
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7
-SCSI_Out__2__PORT EQU 0
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT0_PS
-SCSI_Out__2__SHIFT EQU 7
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__3__AG EQU CYREG_PRT0_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__3__DR EQU CYREG_PRT0_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__3__MASK EQU 0x40
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6
-SCSI_Out__3__PORT EQU 0
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT0_PS
-SCSI_Out__3__SHIFT EQU 6
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__4__AG EQU CYREG_PRT0_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__4__DR EQU CYREG_PRT0_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__4__MASK EQU 0x20
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5
-SCSI_Out__4__PORT EQU 0
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT0_PS
-SCSI_Out__4__SHIFT EQU 5
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__5__AG EQU CYREG_PRT0_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__5__DR EQU CYREG_PRT0_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__5__MASK EQU 0x10
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4
-SCSI_Out__5__PORT EQU 0
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT0_PS
-SCSI_Out__5__SHIFT EQU 4
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__6__AG EQU CYREG_PRT0_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__6__DR EQU CYREG_PRT0_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__6__MASK EQU 0x08
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3
-SCSI_Out__6__PORT EQU 0
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT0_PS
-SCSI_Out__6__SHIFT EQU 3
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__7__AG EQU CYREG_PRT0_AG
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__7__DR EQU CYREG_PRT0_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__7__MASK EQU 0x04
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2
-SCSI_Out__7__PORT EQU 0
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT0_PS
-SCSI_Out__7__SHIFT EQU 2
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__8__AG EQU CYREG_PRT0_AG
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__8__DR EQU CYREG_PRT0_DR
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__8__MASK EQU 0x02
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1
-SCSI_Out__8__PORT EQU 0
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__8__PS EQU CYREG_PRT0_PS
-SCSI_Out__8__SHIFT EQU 1
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__9__AG EQU CYREG_PRT0_AG
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__9__DR EQU CYREG_PRT0_DR
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__9__MASK EQU 0x01
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0
-SCSI_Out__9__PORT EQU 0
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__9__PS EQU CYREG_PRT0_PS
-SCSI_Out__9__SHIFT EQU 0
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__ACK__MASK EQU 0x40
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6
-SCSI_Out__ACK__PORT EQU 0
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS
-SCSI_Out__ACK__SHIFT EQU 6
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__ATN__MASK EQU 0x04
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2
-SCSI_Out__ATN__PORT EQU 4
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS
-SCSI_Out__ATN__SHIFT EQU 2
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x80
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7
-SCSI_Out__BSY__PORT EQU 0
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS
-SCSI_Out__BSY__SHIFT EQU 7
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x04
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 2
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x08
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3
-SCSI_Out__DBP_raw__PORT EQU 4
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS
-SCSI_Out__DBP_raw__SHIFT EQU 3
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__IO_raw__MASK EQU 0x01
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0
-SCSI_Out__IO_raw__PORT EQU 0
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__IO_raw__SHIFT EQU 0
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x10
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4
-SCSI_Out__MSG_raw__PORT EQU 0
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__MSG_raw__SHIFT EQU 4
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x02
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1
-SCSI_Out__REQ__PORT EQU 0
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
-SCSI_Out__REQ__SHIFT EQU 1
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__RST__MASK EQU 0x20
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5
-SCSI_Out__RST__PORT EQU 0
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS
-SCSI_Out__RST__SHIFT EQU 5
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x08
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 3
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-
-/* USBFS_Dm */
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
 
-/* USBFS_Dp */
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+SD_SCK__0__MASK EQU 0x04
+SD_SCK__0__PC EQU CYREG_PRT3_PC2
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 2
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x04
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 2
+SD_SCK__SLW EQU CYREG_PRT3_SLW
 
 /* SCSI_In */
 SCSI_In__0__AG EQU CYREG_PRT2_AG
@@ -2648,332 +757,2228 @@ SCSI_In__REQ__PS EQU CYREG_PRT5_PS
 SCSI_In__REQ__SHIFT EQU 2
 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW
 
-/* SD_DAT1 */
-SD_DAT1__0__MASK EQU 0x01
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0
-SD_DAT1__0__PORT EQU 3
-SD_DAT1__0__SHIFT EQU 0
-SD_DAT1__AG EQU CYREG_PRT3_AG
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX
-SD_DAT1__BIE EQU CYREG_PRT3_BIE
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_DAT1__BYP EQU CYREG_PRT3_BYP
-SD_DAT1__CTL EQU CYREG_PRT3_CTL
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2
-SD_DAT1__DR EQU CYREG_PRT3_DR
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_DAT1__MASK EQU 0x01
-SD_DAT1__PORT EQU 3
-SD_DAT1__PRT EQU CYREG_PRT3_PRT
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_DAT1__PS EQU CYREG_PRT3_PS
-SD_DAT1__SHIFT EQU 0
-SD_DAT1__SLW EQU CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__0__MASK EQU 0x10
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__0__PORT EQU 12
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__0__SHIFT EQU 4
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x80
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__1__PORT EQU 2
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__1__SHIFT EQU 7
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__2__MASK EQU 0x40
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__2__PORT EQU 2
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__2__SHIFT EQU 6
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x20
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__3__PORT EQU 2
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__3__SHIFT EQU 5
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__4__MASK EQU 0x10
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__4__PORT EQU 2
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__4__SHIFT EQU 4
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__5__MASK EQU 0x08
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__5__PORT EQU 2
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__5__SHIFT EQU 3
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x04
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 2
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x02
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__7__SHIFT EQU 1
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB0__MASK EQU 0x10
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB0__PORT EQU 12
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB0__SHIFT EQU 4
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x80
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__DB1__PORT EQU 2
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB1__SHIFT EQU 7
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB2__MASK EQU 0x40
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__DB2__PORT EQU 2
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB2__SHIFT EQU 6
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x20
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB3__PORT EQU 2
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB3__SHIFT EQU 5
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB4__MASK EQU 0x10
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB4__PORT EQU 2
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB4__SHIFT EQU 4
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB5__MASK EQU 0x08
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__DB5__PORT EQU 2
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB5__SHIFT EQU 3
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x04
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 2
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x02
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB7__SHIFT EQU 1
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+/* SD_DAT1 */
+SD_DAT1__0__MASK EQU 0x01
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0
+SD_DAT1__0__PORT EQU 3
+SD_DAT1__0__SHIFT EQU 0
+SD_DAT1__AG EQU CYREG_PRT3_AG
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX
+SD_DAT1__BIE EQU CYREG_PRT3_BIE
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_DAT1__BYP EQU CYREG_PRT3_BYP
+SD_DAT1__CTL EQU CYREG_PRT3_CTL
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2
+SD_DAT1__DR EQU CYREG_PRT3_DR
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_DAT1__MASK EQU 0x01
+SD_DAT1__PORT EQU 3
+SD_DAT1__PRT EQU CYREG_PRT3_PRT
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_DAT1__PS EQU CYREG_PRT3_PS
+SD_DAT1__SHIFT EQU 0
+SD_DAT1__SLW EQU CYREG_PRT3_SLW
+
+/* SD_DAT2 */
+SD_DAT2__0__MASK EQU 0x20
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5
+SD_DAT2__0__PORT EQU 3
+SD_DAT2__0__SHIFT EQU 5
+SD_DAT2__AG EQU CYREG_PRT3_AG
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX
+SD_DAT2__BIE EQU CYREG_PRT3_BIE
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_DAT2__BYP EQU CYREG_PRT3_BYP
+SD_DAT2__CTL EQU CYREG_PRT3_CTL
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2
+SD_DAT2__DR EQU CYREG_PRT3_DR
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_DAT2__MASK EQU 0x20
+SD_DAT2__PORT EQU 3
+SD_DAT2__PRT EQU CYREG_PRT3_PRT
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_DAT2__PS EQU CYREG_PRT3_PS
+SD_DAT2__SHIFT EQU 5
+SD_DAT2__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MISO */
+SD_MISO__0__MASK EQU 0x02
+SD_MISO__0__PC EQU CYREG_PRT3_PC1
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 1
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x02
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 1
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MOSI */
+SD_MOSI__0__MASK EQU 0x08
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 3
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x08
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 3
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
+/* SCSI_Out */
+SCSI_Out__0__AG EQU CYREG_PRT4_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__0__DR EQU CYREG_PRT4_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__0__MASK EQU 0x08
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3
+SCSI_Out__0__PORT EQU 4
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT4_PS
+SCSI_Out__0__SHIFT EQU 3
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__1__AG EQU CYREG_PRT4_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__1__DR EQU CYREG_PRT4_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__1__MASK EQU 0x04
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2
+SCSI_Out__1__PORT EQU 4
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT4_PS
+SCSI_Out__1__SHIFT EQU 2
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__2__AG EQU CYREG_PRT0_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__2__DR EQU CYREG_PRT0_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__2__MASK EQU 0x80
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7
+SCSI_Out__2__PORT EQU 0
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT0_PS
+SCSI_Out__2__SHIFT EQU 7
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__3__AG EQU CYREG_PRT0_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__3__DR EQU CYREG_PRT0_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__3__MASK EQU 0x40
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6
+SCSI_Out__3__PORT EQU 0
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT0_PS
+SCSI_Out__3__SHIFT EQU 6
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__4__AG EQU CYREG_PRT0_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__4__DR EQU CYREG_PRT0_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__4__MASK EQU 0x20
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5
+SCSI_Out__4__PORT EQU 0
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT0_PS
+SCSI_Out__4__SHIFT EQU 5
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__5__AG EQU CYREG_PRT0_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__5__DR EQU CYREG_PRT0_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__5__MASK EQU 0x10
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4
+SCSI_Out__5__PORT EQU 0
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT0_PS
+SCSI_Out__5__SHIFT EQU 4
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__6__AG EQU CYREG_PRT0_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__6__DR EQU CYREG_PRT0_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__6__MASK EQU 0x08
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3
+SCSI_Out__6__PORT EQU 0
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT0_PS
+SCSI_Out__6__SHIFT EQU 3
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__7__AG EQU CYREG_PRT0_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__7__DR EQU CYREG_PRT0_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__7__MASK EQU 0x04
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2
+SCSI_Out__7__PORT EQU 0
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT0_PS
+SCSI_Out__7__SHIFT EQU 2
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__8__AG EQU CYREG_PRT0_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__8__DR EQU CYREG_PRT0_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__8__MASK EQU 0x02
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1
+SCSI_Out__8__PORT EQU 0
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT0_PS
+SCSI_Out__8__SHIFT EQU 1
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__9__AG EQU CYREG_PRT0_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__9__DR EQU CYREG_PRT0_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__9__MASK EQU 0x01
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0
+SCSI_Out__9__PORT EQU 0
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT0_PS
+SCSI_Out__9__SHIFT EQU 0
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x40
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6
+SCSI_Out__ACK__PORT EQU 0
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS
+SCSI_Out__ACK__SHIFT EQU 6
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x04
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2
+SCSI_Out__ATN__PORT EQU 4
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS
+SCSI_Out__ATN__SHIFT EQU 2
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x80
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7
+SCSI_Out__BSY__PORT EQU 0
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS
+SCSI_Out__BSY__SHIFT EQU 7
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x04
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 2
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x08
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3
+SCSI_Out__DBP_raw__PORT EQU 4
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__DBP_raw__SHIFT EQU 3
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x01
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0
+SCSI_Out__IO_raw__PORT EQU 0
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__IO_raw__SHIFT EQU 0
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4
+SCSI_Out__MSG_raw__PORT EQU 0
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x02
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1
+SCSI_Out__REQ__PORT EQU 0
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
+SCSI_Out__REQ__SHIFT EQU 1
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__RST__MASK EQU 0x20
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5
+SCSI_Out__RST__PORT EQU 0
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS
+SCSI_Out__RST__SHIFT EQU 5
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x08
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 3
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+
+/* SCSI_Out_Ctl */
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x08
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__0__PORT EQU 6
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__0__SHIFT EQU 3
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x04
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__1__PORT EQU 6
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__1__SHIFT EQU 2
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x02
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 1
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x01
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 0
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__4__PORT EQU 4
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__5__PORT EQU 4
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x20
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__6__PORT EQU 4
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__6__SHIFT EQU 5
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x10
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__7__PORT EQU 4
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__7__SHIFT EQU 4
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x08
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__DB0__PORT EQU 6
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 3
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x04
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__DB1__PORT EQU 6
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 2
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x02
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 1
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x01
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 0
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__DB4__PORT EQU 4
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__DB5__PORT EQU 4
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x20
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__DB6__PORT EQU 4
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 5
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x10
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__DB7__PORT EQU 4
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 4
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
+
+/* SD_RX_DMA */
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+
+/* SD_RX_DMA_COMPLETE */
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+
+/* SD_TX_DMA_COMPLETE */
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Noise__0__MASK EQU 0x20
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5
+SCSI_Noise__0__PORT EQU 12
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS
+SCSI_Noise__0__SHIFT EQU 5
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x10
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 4
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Noise__2__MASK EQU 0x01
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0
+SCSI_Noise__2__PORT EQU 5
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS
+SCSI_Noise__2__SHIFT EQU 0
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__3__MASK EQU 0x40
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6
+SCSI_Noise__3__PORT EQU 6
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS
+SCSI_Noise__3__SHIFT EQU 6
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x20
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 5
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x20
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 5
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Noise__ATN__MASK EQU 0x20
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5
+SCSI_Noise__ATN__PORT EQU 12
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS
+SCSI_Noise__ATN__SHIFT EQU 5
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x10
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 4
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x40
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6
+SCSI_Noise__RST__PORT EQU 6
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS
+SCSI_Noise__RST__SHIFT EQU 6
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x01
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0
+SCSI_Noise__SEL__PORT EQU 5
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS
+SCSI_Noise__SEL__SHIFT EQU 0
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW
+
+/* scsiTarget */
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__4__MASK EQU 0x10
+scsiTarget_StatusReg__4__POS EQU 4
+scsiTarget_StatusReg__MASK EQU 0x1F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
-/* SD_DAT2 */
-SD_DAT2__0__MASK EQU 0x20
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5
-SD_DAT2__0__PORT EQU 3
-SD_DAT2__0__SHIFT EQU 5
-SD_DAT2__AG EQU CYREG_PRT3_AG
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX
-SD_DAT2__BIE EQU CYREG_PRT3_BIE
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_DAT2__BYP EQU CYREG_PRT3_BYP
-SD_DAT2__CTL EQU CYREG_PRT3_CTL
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2
-SD_DAT2__DR EQU CYREG_PRT3_DR
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_DAT2__MASK EQU 0x20
-SD_DAT2__PORT EQU 3
-SD_DAT2__PRT EQU CYREG_PRT3_PRT
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_DAT2__PS EQU CYREG_PRT3_PS
-SD_DAT2__SHIFT EQU 5
-SD_DAT2__SLW EQU CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SD_MISO */
-SD_MISO__0__MASK EQU 0x02
-SD_MISO__0__PC EQU CYREG_PRT3_PC1
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 1
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x02
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 1
-SD_MISO__SLW EQU CYREG_PRT3_SLW
+/* Debug_Timer_TimerHW */
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+
+/* SCSI_RX_DMA_COMPLETE */
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+
+/* SCSI_TX_DMA_COMPLETE */
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
 
-/* SD_MOSI */
-SD_MOSI__0__MASK EQU 0x08
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 3
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x08
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 3
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
+/* timer_clock */
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
+timer_clock__INDEX EQU 0x02
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+timer_clock__PM_STBY_MSK EQU 0x04
 
-/* SD_SCK */
-SD_SCK__0__MASK EQU 0x04
-SD_SCK__0__PC EQU CYREG_PRT3_PC2
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 2
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x04
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 2
-SD_SCK__SLW EQU CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SD_CD */
-SD_CD__0__MASK EQU 0x40
-SD_CD__0__PC EQU CYREG_PRT3_PC6
-SD_CD__0__PORT EQU 3
-SD_CD__0__SHIFT EQU 6
-SD_CD__AG EQU CYREG_PRT3_AG
-SD_CD__AMUX EQU CYREG_PRT3_AMUX
-SD_CD__BIE EQU CYREG_PRT3_BIE
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CD__BYP EQU CYREG_PRT3_BYP
-SD_CD__CTL EQU CYREG_PRT3_CTL
-SD_CD__DM0 EQU CYREG_PRT3_DM0
-SD_CD__DM1 EQU CYREG_PRT3_DM1
-SD_CD__DM2 EQU CYREG_PRT3_DM2
-SD_CD__DR EQU CYREG_PRT3_DR
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CD__MASK EQU 0x40
-SD_CD__PORT EQU 3
-SD_CD__PRT EQU CYREG_PRT3_PRT
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CD__PS EQU CYREG_PRT3_PS
-SD_CD__SHIFT EQU 6
-SD_CD__SLW EQU CYREG_PRT3_SLW
+/* SCSI_Filtered */
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
 
-/* SD_CS */
-SD_CS__0__MASK EQU 0x10
-SD_CS__0__PC EQU CYREG_PRT3_PC4
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 4
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x10
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 4
-SD_CS__SLW EQU CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
-/* LED1 */
-LED1__0__MASK EQU 0x08
-LED1__0__PC EQU CYREG_PRT12_PC3
-LED1__0__PORT EQU 12
-LED1__0__SHIFT EQU 3
-LED1__AG EQU CYREG_PRT12_AG
-LED1__BIE EQU CYREG_PRT12_BIE
-LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-LED1__BYP EQU CYREG_PRT12_BYP
-LED1__DM0 EQU CYREG_PRT12_DM0
-LED1__DM1 EQU CYREG_PRT12_DM1
-LED1__DM2 EQU CYREG_PRT12_DM2
-LED1__DR EQU CYREG_PRT12_DR
-LED1__INP_DIS EQU CYREG_PRT12_INP_DIS
-LED1__MASK EQU 0x08
-LED1__PORT EQU 12
-LED1__PRT EQU CYREG_PRT12_PRT
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-LED1__PS EQU CYREG_PRT12_PS
-LED1__SHIFT EQU 3
-LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-LED1__SLW EQU CYREG_PRT12_SLW
+/* SCSI_Parity_Error */
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0400
@@ -2985,7 +2990,7 @@ CYDEV_PROJ_TYPE_LOADABLE EQU 2
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x2000
+CYDEV_STACK_SIZE EQU 0x1000
 CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
 CYDEV_USE_BUNDLED_CMSIS EQU 1
 CYDEV_VARIABLE_VDDA EQU 0
@@ -2995,13 +3000,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 3300
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
 CYDEV_VIO3_MV EQU 3300
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
 CYDEV_BOOTLOADER_ENABLE EQU 0
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index 6333438e..c42672d3 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -3,83 +3,110 @@ INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc
     GET cydevicerv_trm.inc
 
-; Debug_Timer_Interrupt
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_RX_DMA_COMPLETE
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_TX_DMA_COMPLETE
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; Debug_Timer_TimerHW
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+; LED1
+LED1__0__MASK EQU 0x08
+LED1__0__PC EQU CYREG_PRT12_PC3
+LED1__0__PORT EQU 12
+LED1__0__SHIFT EQU 3
+LED1__AG EQU CYREG_PRT12_AG
+LED1__BIE EQU CYREG_PRT12_BIE
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+LED1__BYP EQU CYREG_PRT12_BYP
+LED1__DM0 EQU CYREG_PRT12_DM0
+LED1__DM1 EQU CYREG_PRT12_DM1
+LED1__DM2 EQU CYREG_PRT12_DM2
+LED1__DR EQU CYREG_PRT12_DR
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS
+LED1__MASK EQU 0x08
+LED1__PORT EQU 12
+LED1__PRT EQU CYREG_PRT12_PRT
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+LED1__PS EQU CYREG_PRT12_PS
+LED1__SHIFT EQU 3
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+LED1__SLW EQU CYREG_PRT12_SLW
 
-; SD_RX_DMA_COMPLETE
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SD_CD
+SD_CD__0__MASK EQU 0x40
+SD_CD__0__PC EQU CYREG_PRT3_PC6
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 6
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x40
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 6
+SD_CD__SLW EQU CYREG_PRT3_SLW
 
-; SD_TX_DMA_COMPLETE
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SD_CS
+SD_CS__0__MASK EQU 0x10
+SD_CS__0__PC EQU CYREG_PRT3_PC4
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 4
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x10
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 4
+SD_CS__SLW EQU CYREG_PRT3_SLW
 
-; SCSI_Parity_Error
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
+; USBFS_arb_int
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; USBFS_bus_reset
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -91,99 +118,131 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_CTL_PHASE
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-
-; SCSI_Filtered
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST
-
-; SCSI_Out_Bits
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-
-; USBFS_arb_int
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; USBFS_Dm
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+; USBFS_Dp
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+; USBFS_dp_int
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_1
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_2
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_3
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_4
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x200
+USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; USBFS_sof_int
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -195,2186 +254,236 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_Out_Ctl
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+; USBFS_USB
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x08
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__0__PORT EQU 6
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__0__SHIFT EQU 3
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x04
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__1__PORT EQU 6
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__1__SHIFT EQU 2
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x02
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 1
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x01
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 0
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__4__PORT EQU 4
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__5__PORT EQU 4
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x20
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__6__PORT EQU 4
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__6__SHIFT EQU 5
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x10
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__7__PORT EQU 4
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__7__SHIFT EQU 4
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x08
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__DB0__PORT EQU 6
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 3
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x04
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__DB1__PORT EQU 6
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 2
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x02
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 1
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x01
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 0
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__DB4__PORT EQU 4
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__DB5__PORT EQU 4
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x20
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__DB6__PORT EQU 4
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 5
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x10
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__DB7__PORT EQU 4
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 4
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
-
-; SCSI_RST_ISR
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_In_DBx
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__0__MASK EQU 0x10
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__0__PORT EQU 12
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__0__SHIFT EQU 4
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x80
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7
-SCSI_In_DBx__1__PORT EQU 2
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__1__SHIFT EQU 7
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__2__MASK EQU 0x40
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__2__PORT EQU 2
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__2__SHIFT EQU 6
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x20
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__3__PORT EQU 2
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__3__SHIFT EQU 5
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__4__MASK EQU 0x10
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__4__PORT EQU 2
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__4__SHIFT EQU 4
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__5__MASK EQU 0x08
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3
-SCSI_In_DBx__5__PORT EQU 2
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__5__SHIFT EQU 3
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x04
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 2
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x02
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1
-SCSI_In_DBx__7__PORT EQU 2
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__7__SHIFT EQU 1
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB0__MASK EQU 0x10
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB0__PORT EQU 12
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB0__SHIFT EQU 4
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x80
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7
-SCSI_In_DBx__DB1__PORT EQU 2
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB1__SHIFT EQU 7
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB2__MASK EQU 0x40
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6
-SCSI_In_DBx__DB2__PORT EQU 2
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB2__SHIFT EQU 6
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x20
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__DB3__PORT EQU 2
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB3__SHIFT EQU 5
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB4__MASK EQU 0x10
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB4__PORT EQU 2
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB4__SHIFT EQU 4
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB5__MASK EQU 0x08
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3
-SCSI_In_DBx__DB5__PORT EQU 2
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB5__SHIFT EQU 3
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x04
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 2
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x02
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1
-SCSI_In_DBx__DB7__PORT EQU 2
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB7__SHIFT EQU 1
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; SCSI_RX_DMA
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SCSI_TX_DMA
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_Data_Clk
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-; timer_clock
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
-
-; SCSI_Noise
-SCSI_Noise__0__AG EQU CYREG_PRT12_AG
-SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP
-SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0
-SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1
-SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2
-SCSI_Noise__0__DR EQU CYREG_PRT12_DR
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Noise__0__MASK EQU 0x20
-SCSI_Noise__0__PC EQU CYREG_PRT12_PC5
-SCSI_Noise__0__PORT EQU 12
-SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Noise__0__PS EQU CYREG_PRT12_PS
-SCSI_Noise__0__SHIFT EQU 5
-SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__1__MASK EQU 0x10
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC4
-SCSI_Noise__1__PORT EQU 6
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS
-SCSI_Noise__1__SHIFT EQU 4
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__2__AG EQU CYREG_PRT5_AG
-SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP
-SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL
-SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0
-SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1
-SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2
-SCSI_Noise__2__DR EQU CYREG_PRT5_DR
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Noise__2__MASK EQU 0x01
-SCSI_Noise__2__PC EQU CYREG_PRT5_PC0
-SCSI_Noise__2__PORT EQU 5
-SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Noise__2__PS EQU CYREG_PRT5_PS
-SCSI_Noise__2__SHIFT EQU 0
-SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW
-SCSI_Noise__3__AG EQU CYREG_PRT6_AG
-SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__3__DR EQU CYREG_PRT6_DR
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__3__MASK EQU 0x40
-SCSI_Noise__3__PC EQU CYREG_PRT6_PC6
-SCSI_Noise__3__PORT EQU 6
-SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__3__PS EQU CYREG_PRT6_PS
-SCSI_Noise__3__SHIFT EQU 6
-SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__4__MASK EQU 0x20
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC5
-SCSI_Noise__4__PORT EQU 6
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS
-SCSI_Noise__4__SHIFT EQU 5
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__ACK__MASK EQU 0x20
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5
-SCSI_Noise__ACK__PORT EQU 6
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Noise__ACK__SHIFT EQU 5
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG
-SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2
-SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_Noise__ATN__MASK EQU 0x20
-SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5
-SCSI_Noise__ATN__PORT EQU 12
-SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS
-SCSI_Noise__ATN__SHIFT EQU 5
-SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__BSY__MASK EQU 0x10
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4
-SCSI_Noise__BSY__PORT EQU 6
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Noise__BSY__SHIFT EQU 4
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__RST__AG EQU CYREG_PRT6_AG
-SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__RST__DR EQU CYREG_PRT6_DR
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__RST__MASK EQU 0x40
-SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6
-SCSI_Noise__RST__PORT EQU 6
-SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__RST__PS EQU CYREG_PRT6_PS
-SCSI_Noise__RST__SHIFT EQU 6
-SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP
-SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2
-SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Noise__SEL__MASK EQU 0x01
-SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0
-SCSI_Noise__SEL__PORT EQU 5
-SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS
-SCSI_Noise__SEL__SHIFT EQU 0
-SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW
-
-; scsiTarget
-scsiTarget_StatusReg__0__MASK EQU 0x01
-scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-scsiTarget_StatusReg__1__MASK EQU 0x02
-scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__2__MASK EQU 0x04
-scsiTarget_StatusReg__2__POS EQU 2
-scsiTarget_StatusReg__3__MASK EQU 0x08
-scsiTarget_StatusReg__3__POS EQU 3
-scsiTarget_StatusReg__4__MASK EQU 0x10
-scsiTarget_StatusReg__4__POS EQU 4
-scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB05_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB01_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB01_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB01_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB01_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB01_02_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB01_02_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB01_02_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB01_02_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB01_02_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB01_02_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB01_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB01_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB01_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB01_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB01_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB01_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB01_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB01_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB01_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_3
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_4
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_RX_DMA
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 1
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_TX_DMA
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-; USBFS_USB
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-
-; SCSI_CLK
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-; SCSI_Out
-SCSI_Out__0__AG EQU CYREG_PRT4_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__0__DR EQU CYREG_PRT4_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__0__MASK EQU 0x08
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3
-SCSI_Out__0__PORT EQU 4
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT4_PS
-SCSI_Out__0__SHIFT EQU 3
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__1__AG EQU CYREG_PRT4_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__1__DR EQU CYREG_PRT4_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__1__MASK EQU 0x04
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2
-SCSI_Out__1__PORT EQU 4
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT4_PS
-SCSI_Out__1__SHIFT EQU 2
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__2__AG EQU CYREG_PRT0_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__2__DR EQU CYREG_PRT0_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__2__MASK EQU 0x80
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7
-SCSI_Out__2__PORT EQU 0
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT0_PS
-SCSI_Out__2__SHIFT EQU 7
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__3__AG EQU CYREG_PRT0_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__3__DR EQU CYREG_PRT0_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__3__MASK EQU 0x40
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6
-SCSI_Out__3__PORT EQU 0
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT0_PS
-SCSI_Out__3__SHIFT EQU 6
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__4__AG EQU CYREG_PRT0_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__4__DR EQU CYREG_PRT0_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__4__MASK EQU 0x20
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5
-SCSI_Out__4__PORT EQU 0
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT0_PS
-SCSI_Out__4__SHIFT EQU 5
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__5__AG EQU CYREG_PRT0_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__5__DR EQU CYREG_PRT0_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__5__MASK EQU 0x10
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4
-SCSI_Out__5__PORT EQU 0
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT0_PS
-SCSI_Out__5__SHIFT EQU 4
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__6__AG EQU CYREG_PRT0_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__6__DR EQU CYREG_PRT0_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__6__MASK EQU 0x08
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3
-SCSI_Out__6__PORT EQU 0
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT0_PS
-SCSI_Out__6__SHIFT EQU 3
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__7__AG EQU CYREG_PRT0_AG
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__7__DR EQU CYREG_PRT0_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__7__MASK EQU 0x04
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2
-SCSI_Out__7__PORT EQU 0
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT0_PS
-SCSI_Out__7__SHIFT EQU 2
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__8__AG EQU CYREG_PRT0_AG
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__8__DR EQU CYREG_PRT0_DR
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__8__MASK EQU 0x02
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1
-SCSI_Out__8__PORT EQU 0
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__8__PS EQU CYREG_PRT0_PS
-SCSI_Out__8__SHIFT EQU 1
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__9__AG EQU CYREG_PRT0_AG
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__9__DR EQU CYREG_PRT0_DR
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__9__MASK EQU 0x01
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0
-SCSI_Out__9__PORT EQU 0
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__9__PS EQU CYREG_PRT0_PS
-SCSI_Out__9__SHIFT EQU 0
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__ACK__MASK EQU 0x40
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6
-SCSI_Out__ACK__PORT EQU 0
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS
-SCSI_Out__ACK__SHIFT EQU 6
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__ATN__MASK EQU 0x04
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2
-SCSI_Out__ATN__PORT EQU 4
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS
-SCSI_Out__ATN__SHIFT EQU 2
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x80
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7
-SCSI_Out__BSY__PORT EQU 0
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS
-SCSI_Out__BSY__SHIFT EQU 7
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x04
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 2
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x08
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3
-SCSI_Out__DBP_raw__PORT EQU 4
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS
-SCSI_Out__DBP_raw__SHIFT EQU 3
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__IO_raw__MASK EQU 0x01
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0
-SCSI_Out__IO_raw__PORT EQU 0
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__IO_raw__SHIFT EQU 0
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x10
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4
-SCSI_Out__MSG_raw__PORT EQU 0
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__MSG_raw__SHIFT EQU 4
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x02
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1
-SCSI_Out__REQ__PORT EQU 0
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
-SCSI_Out__REQ__SHIFT EQU 1
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__RST__MASK EQU 0x20
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5
-SCSI_Out__RST__PORT EQU 0
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS
-SCSI_Out__RST__SHIFT EQU 5
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x08
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 3
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-
-; USBFS_Dm
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+; SDCard_BSPIM
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
 
-; USBFS_Dp
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+; SD_SCK
+SD_SCK__0__MASK EQU 0x04
+SD_SCK__0__PC EQU CYREG_PRT3_PC2
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 2
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x04
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 2
+SD_SCK__SLW EQU CYREG_PRT3_SLW
 
 ; SCSI_In
 SCSI_In__0__AG EQU CYREG_PRT2_AG
@@ -2648,332 +757,2228 @@ SCSI_In__REQ__PS EQU CYREG_PRT5_PS
 SCSI_In__REQ__SHIFT EQU 2
 SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW
 
-; SD_DAT1
-SD_DAT1__0__MASK EQU 0x01
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0
-SD_DAT1__0__PORT EQU 3
-SD_DAT1__0__SHIFT EQU 0
-SD_DAT1__AG EQU CYREG_PRT3_AG
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX
-SD_DAT1__BIE EQU CYREG_PRT3_BIE
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_DAT1__BYP EQU CYREG_PRT3_BYP
-SD_DAT1__CTL EQU CYREG_PRT3_CTL
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2
-SD_DAT1__DR EQU CYREG_PRT3_DR
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_DAT1__MASK EQU 0x01
-SD_DAT1__PORT EQU 3
-SD_DAT1__PRT EQU CYREG_PRT3_PRT
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_DAT1__PS EQU CYREG_PRT3_PS
-SD_DAT1__SHIFT EQU 0
-SD_DAT1__SLW EQU CYREG_PRT3_SLW
+; SCSI_In_DBx
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__0__MASK EQU 0x10
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__0__PORT EQU 12
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__0__SHIFT EQU 4
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x80
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__1__PORT EQU 2
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__1__SHIFT EQU 7
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__2__MASK EQU 0x40
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__2__PORT EQU 2
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__2__SHIFT EQU 6
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x20
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__3__PORT EQU 2
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__3__SHIFT EQU 5
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__4__MASK EQU 0x10
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__4__PORT EQU 2
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__4__SHIFT EQU 4
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__5__MASK EQU 0x08
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__5__PORT EQU 2
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__5__SHIFT EQU 3
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x04
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 2
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x02
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__7__SHIFT EQU 1
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB0__MASK EQU 0x10
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB0__PORT EQU 12
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB0__SHIFT EQU 4
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x80
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7
+SCSI_In_DBx__DB1__PORT EQU 2
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB1__SHIFT EQU 7
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB2__MASK EQU 0x40
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6
+SCSI_In_DBx__DB2__PORT EQU 2
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB2__SHIFT EQU 6
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x20
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB3__PORT EQU 2
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB3__SHIFT EQU 5
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB4__MASK EQU 0x10
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB4__PORT EQU 2
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB4__SHIFT EQU 4
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB5__MASK EQU 0x08
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3
+SCSI_In_DBx__DB5__PORT EQU 2
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB5__SHIFT EQU 3
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x04
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 2
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x02
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB7__SHIFT EQU 1
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+; SD_DAT1
+SD_DAT1__0__MASK EQU 0x01
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0
+SD_DAT1__0__PORT EQU 3
+SD_DAT1__0__SHIFT EQU 0
+SD_DAT1__AG EQU CYREG_PRT3_AG
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX
+SD_DAT1__BIE EQU CYREG_PRT3_BIE
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_DAT1__BYP EQU CYREG_PRT3_BYP
+SD_DAT1__CTL EQU CYREG_PRT3_CTL
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2
+SD_DAT1__DR EQU CYREG_PRT3_DR
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_DAT1__MASK EQU 0x01
+SD_DAT1__PORT EQU 3
+SD_DAT1__PRT EQU CYREG_PRT3_PRT
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_DAT1__PS EQU CYREG_PRT3_PS
+SD_DAT1__SHIFT EQU 0
+SD_DAT1__SLW EQU CYREG_PRT3_SLW
+
+; SD_DAT2
+SD_DAT2__0__MASK EQU 0x20
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5
+SD_DAT2__0__PORT EQU 3
+SD_DAT2__0__SHIFT EQU 5
+SD_DAT2__AG EQU CYREG_PRT3_AG
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX
+SD_DAT2__BIE EQU CYREG_PRT3_BIE
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_DAT2__BYP EQU CYREG_PRT3_BYP
+SD_DAT2__CTL EQU CYREG_PRT3_CTL
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2
+SD_DAT2__DR EQU CYREG_PRT3_DR
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_DAT2__MASK EQU 0x20
+SD_DAT2__PORT EQU 3
+SD_DAT2__PRT EQU CYREG_PRT3_PRT
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_DAT2__PS EQU CYREG_PRT3_PS
+SD_DAT2__SHIFT EQU 5
+SD_DAT2__SLW EQU CYREG_PRT3_SLW
+
+; SD_MISO
+SD_MISO__0__MASK EQU 0x02
+SD_MISO__0__PC EQU CYREG_PRT3_PC1
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 1
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x02
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 1
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+; SD_MOSI
+SD_MOSI__0__MASK EQU 0x08
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 3
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x08
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 3
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+; SCSI_CLK
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
+; SCSI_Out
+SCSI_Out__0__AG EQU CYREG_PRT4_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__0__DR EQU CYREG_PRT4_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__0__MASK EQU 0x08
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3
+SCSI_Out__0__PORT EQU 4
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT4_PS
+SCSI_Out__0__SHIFT EQU 3
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__1__AG EQU CYREG_PRT4_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__1__DR EQU CYREG_PRT4_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__1__MASK EQU 0x04
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2
+SCSI_Out__1__PORT EQU 4
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT4_PS
+SCSI_Out__1__SHIFT EQU 2
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__2__AG EQU CYREG_PRT0_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__2__DR EQU CYREG_PRT0_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__2__MASK EQU 0x80
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7
+SCSI_Out__2__PORT EQU 0
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT0_PS
+SCSI_Out__2__SHIFT EQU 7
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__3__AG EQU CYREG_PRT0_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__3__DR EQU CYREG_PRT0_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__3__MASK EQU 0x40
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6
+SCSI_Out__3__PORT EQU 0
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT0_PS
+SCSI_Out__3__SHIFT EQU 6
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__4__AG EQU CYREG_PRT0_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__4__DR EQU CYREG_PRT0_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__4__MASK EQU 0x20
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5
+SCSI_Out__4__PORT EQU 0
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT0_PS
+SCSI_Out__4__SHIFT EQU 5
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__5__AG EQU CYREG_PRT0_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__5__DR EQU CYREG_PRT0_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__5__MASK EQU 0x10
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4
+SCSI_Out__5__PORT EQU 0
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT0_PS
+SCSI_Out__5__SHIFT EQU 4
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__6__AG EQU CYREG_PRT0_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__6__DR EQU CYREG_PRT0_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__6__MASK EQU 0x08
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3
+SCSI_Out__6__PORT EQU 0
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT0_PS
+SCSI_Out__6__SHIFT EQU 3
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__7__AG EQU CYREG_PRT0_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__7__DR EQU CYREG_PRT0_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__7__MASK EQU 0x04
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2
+SCSI_Out__7__PORT EQU 0
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT0_PS
+SCSI_Out__7__SHIFT EQU 2
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__8__AG EQU CYREG_PRT0_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__8__DR EQU CYREG_PRT0_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__8__MASK EQU 0x02
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1
+SCSI_Out__8__PORT EQU 0
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT0_PS
+SCSI_Out__8__SHIFT EQU 1
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__9__AG EQU CYREG_PRT0_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__9__DR EQU CYREG_PRT0_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__9__MASK EQU 0x01
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0
+SCSI_Out__9__PORT EQU 0
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT0_PS
+SCSI_Out__9__SHIFT EQU 0
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x40
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6
+SCSI_Out__ACK__PORT EQU 0
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS
+SCSI_Out__ACK__SHIFT EQU 6
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x04
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2
+SCSI_Out__ATN__PORT EQU 4
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS
+SCSI_Out__ATN__SHIFT EQU 2
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x80
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7
+SCSI_Out__BSY__PORT EQU 0
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS
+SCSI_Out__BSY__SHIFT EQU 7
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x04
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 2
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x08
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3
+SCSI_Out__DBP_raw__PORT EQU 4
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__DBP_raw__SHIFT EQU 3
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x01
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0
+SCSI_Out__IO_raw__PORT EQU 0
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__IO_raw__SHIFT EQU 0
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4
+SCSI_Out__MSG_raw__PORT EQU 0
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x02
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1
+SCSI_Out__REQ__PORT EQU 0
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
+SCSI_Out__REQ__SHIFT EQU 1
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__RST__MASK EQU 0x20
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5
+SCSI_Out__RST__PORT EQU 0
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS
+SCSI_Out__RST__SHIFT EQU 5
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x08
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 3
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+
+; SCSI_Out_Bits
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+
+; SCSI_Out_Ctl
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+
+; SCSI_Out_DBx
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x08
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__0__PORT EQU 6
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__0__SHIFT EQU 3
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x04
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__1__PORT EQU 6
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__1__SHIFT EQU 2
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x02
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 1
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x01
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 0
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__4__PORT EQU 4
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__5__PORT EQU 4
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x20
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__6__PORT EQU 4
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__6__SHIFT EQU 5
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x10
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__7__PORT EQU 4
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__7__SHIFT EQU 4
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x08
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__DB0__PORT EQU 6
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 3
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x04
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__DB1__PORT EQU 6
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 2
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x02
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 1
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x01
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 0
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__DB4__PORT EQU 4
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__DB5__PORT EQU 4
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x20
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__DB6__PORT EQU 4
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 5
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x10
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__DB7__PORT EQU 4
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 4
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
+
+; SD_RX_DMA
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+
+; SD_RX_DMA_COMPLETE
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_TX_DMA
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+
+; SD_TX_DMA_COMPLETE
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_Noise
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Noise__0__MASK EQU 0x20
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5
+SCSI_Noise__0__PORT EQU 12
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS
+SCSI_Noise__0__SHIFT EQU 5
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x10
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 4
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Noise__2__MASK EQU 0x01
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0
+SCSI_Noise__2__PORT EQU 5
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS
+SCSI_Noise__2__SHIFT EQU 0
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__3__MASK EQU 0x40
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6
+SCSI_Noise__3__PORT EQU 6
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS
+SCSI_Noise__3__SHIFT EQU 6
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x20
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 5
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x20
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 5
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_Noise__ATN__MASK EQU 0x20
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5
+SCSI_Noise__ATN__PORT EQU 12
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS
+SCSI_Noise__ATN__SHIFT EQU 5
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x10
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 4
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x40
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6
+SCSI_Noise__RST__PORT EQU 6
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS
+SCSI_Noise__RST__SHIFT EQU 6
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x01
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0
+SCSI_Noise__SEL__PORT EQU 5
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS
+SCSI_Noise__SEL__SHIFT EQU 0
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW
+
+; scsiTarget
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__4__MASK EQU 0x10
+scsiTarget_StatusReg__4__POS EQU 4
+scsiTarget_StatusReg__MASK EQU 0x1F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
 
-; SD_DAT2
-SD_DAT2__0__MASK EQU 0x20
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5
-SD_DAT2__0__PORT EQU 3
-SD_DAT2__0__SHIFT EQU 5
-SD_DAT2__AG EQU CYREG_PRT3_AG
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX
-SD_DAT2__BIE EQU CYREG_PRT3_BIE
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_DAT2__BYP EQU CYREG_PRT3_BYP
-SD_DAT2__CTL EQU CYREG_PRT3_CTL
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2
-SD_DAT2__DR EQU CYREG_PRT3_DR
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_DAT2__MASK EQU 0x20
-SD_DAT2__PORT EQU 3
-SD_DAT2__PRT EQU CYREG_PRT3_PRT
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_DAT2__PS EQU CYREG_PRT3_PS
-SD_DAT2__SHIFT EQU 5
-SD_DAT2__SLW EQU CYREG_PRT3_SLW
+; Debug_Timer_Interrupt
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SD_MISO
-SD_MISO__0__MASK EQU 0x02
-SD_MISO__0__PC EQU CYREG_PRT3_PC1
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 1
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x02
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 1
-SD_MISO__SLW EQU CYREG_PRT3_SLW
+; Debug_Timer_TimerHW
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
+; SCSI_RX_DMA
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+
+; SCSI_RX_DMA_COMPLETE
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_TX_DMA
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+
+; SCSI_TX_DMA_COMPLETE
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_Data_Clk
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
 
-; SD_MOSI
-SD_MOSI__0__MASK EQU 0x08
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 3
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x08
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 3
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
+; timer_clock
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
+timer_clock__INDEX EQU 0x02
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+timer_clock__PM_STBY_MSK EQU 0x04
 
-; SD_SCK
-SD_SCK__0__MASK EQU 0x04
-SD_SCK__0__PC EQU CYREG_PRT3_PC2
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 2
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x04
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 2
-SD_SCK__SLW EQU CYREG_PRT3_SLW
+; SCSI_RST_ISR
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SD_CD
-SD_CD__0__MASK EQU 0x40
-SD_CD__0__PC EQU CYREG_PRT3_PC6
-SD_CD__0__PORT EQU 3
-SD_CD__0__SHIFT EQU 6
-SD_CD__AG EQU CYREG_PRT3_AG
-SD_CD__AMUX EQU CYREG_PRT3_AMUX
-SD_CD__BIE EQU CYREG_PRT3_BIE
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CD__BYP EQU CYREG_PRT3_BYP
-SD_CD__CTL EQU CYREG_PRT3_CTL
-SD_CD__DM0 EQU CYREG_PRT3_DM0
-SD_CD__DM1 EQU CYREG_PRT3_DM1
-SD_CD__DM2 EQU CYREG_PRT3_DM2
-SD_CD__DR EQU CYREG_PRT3_DR
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CD__MASK EQU 0x40
-SD_CD__PORT EQU 3
-SD_CD__PRT EQU CYREG_PRT3_PRT
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CD__PS EQU CYREG_PRT3_PS
-SD_CD__SHIFT EQU 6
-SD_CD__SLW EQU CYREG_PRT3_SLW
+; SCSI_Filtered
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
 
-; SD_CS
-SD_CS__0__MASK EQU 0x10
-SD_CS__0__PC EQU CYREG_PRT3_PC4
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 4
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x10
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 4
-SD_CS__SLW EQU CYREG_PRT3_SLW
+; SCSI_CTL_PHASE
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
-; LED1
-LED1__0__MASK EQU 0x08
-LED1__0__PC EQU CYREG_PRT12_PC3
-LED1__0__PORT EQU 12
-LED1__0__SHIFT EQU 3
-LED1__AG EQU CYREG_PRT12_AG
-LED1__BIE EQU CYREG_PRT12_BIE
-LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-LED1__BYP EQU CYREG_PRT12_BYP
-LED1__DM0 EQU CYREG_PRT12_DM0
-LED1__DM1 EQU CYREG_PRT12_DM1
-LED1__DM2 EQU CYREG_PRT12_DM2
-LED1__DR EQU CYREG_PRT12_DR
-LED1__INP_DIS EQU CYREG_PRT12_INP_DIS
-LED1__MASK EQU 0x08
-LED1__PORT EQU 12
-LED1__PRT EQU CYREG_PRT12_PRT
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-LED1__PS EQU CYREG_PRT12_PS
-LED1__SHIFT EQU 3
-LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-LED1__SLW EQU CYREG_PRT12_SLW
+; SCSI_Parity_Error
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST
 
 ; Miscellaneous
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0400
@@ -2985,7 +2990,7 @@ CYDEV_PROJ_TYPE_LOADABLE EQU 2
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x2000
+CYDEV_STACK_SIZE EQU 0x1000
 CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
 CYDEV_USE_BUNDLED_CMSIS EQU 1
 CYDEV_VARIABLE_VDDA EQU 0
@@ -2995,13 +3000,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 3300
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
 CYDEV_VIO3_MV EQU 3300
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
 CYDEV_BOOTLOADER_ENABLE EQU 0
     ENDIF
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
index 7480627d..dfdc40ae 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cymetadata.c
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file defines all extra memory spaces that need to be included.
@@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
 const uint8 cy_meta_loadable[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x01u, 0x04u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x05u, 0x04u,
     0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
old mode 100755
new mode 100644
index 3af7484a..a1a727b2
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
@@ -1,9 +1,9 @@
 /*******************************************************************************
 * File Name: cypins.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   This file contains the function prototypes and constants used for port/pin
+*   This file contains the function prototypes and constants used for a port/pin
 *   in access and control.
 *
 *  Note:
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -103,6 +103,13 @@
 *  Note that this only has an effect for pins configured as software pins that
 *  are not driven by hardware.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16).
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -123,7 +130,14 @@
 ********************************************************************************
 *
 * Summary:
-*  This macro sets the state of the specified pin to 0
+*  This macro sets the state of the specified pin to 0.
+*
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
 *
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
@@ -147,6 +161,13 @@
 * Summary:
 *  Sets the drive mode for the pin (DM).
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16)
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -193,7 +214,7 @@
 *
 *
 * Return:
-*   mode:  Current drive mode for the pin
+*   mode:  The current drive mode for the pin
 *
 *   Define                Source
 *   PIN_DM_ALG_HIZ        Analog HiZ
@@ -214,10 +235,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to fast edge rate.
+*  Set the slew rate for the pin to fast the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -239,10 +267,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to slow edge rate.
+*  Set the slew rate for the pin to slow the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -259,7 +294,18 @@
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)
 #define PC_DRIVE_MODE_MASK  (CY_PINS_PC_DRIVE_MODE_MASK)
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
old mode 100755
new mode 100644
index c2a20ad3..d48f29a5
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cytypes.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  CyTypes provides register access macros and approved types for use in
@@ -12,12 +12,12 @@
 *  data the correct way.
 *
 *  Register Access macros and functions perform their operations on an
-*  input of type pointer to void.  The arguments passed to it should be
+*  input of the type pointer to void.  The arguments passed to it should be
 *  pointers to the type associated with the register size.
 *  (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -40,7 +40,7 @@
 
 #if defined( __ICCARM__ )
     /* Suppress warning for multiple volatile variables in an expression. */
-    /* This is common in component code and the usage is not order dependent. */
+    /* This is common in component code and usage is not order dependent. */
     #pragma diag_suppress=Pa082
 #endif  /* defined( __ICCARM__ ) */
 
@@ -61,28 +61,98 @@
 /*******************************************************************************
 * MEMBER encodes both the family and the detailed architecture
 *******************************************************************************/
-#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
 #ifdef CYDEV_CHIP_MEMBER_4D
-    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
 #else
-    #define CY_PSOC4D   (0u != 0u)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (0u != 0u)
 #endif  /* CYDEV_CHIP_MEMBER_4D */
 
-#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
-#ifdef CYDEV_CHIP_MEMBER_5B
-    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#define CY_PSOC4_4100       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#define CY_PSOC4_4200       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+
+#ifdef CYDEV_CHIP_MEMBER_4F
+    #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
+    #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
 #else
-    #define CY_PSOC5LP  (0u != 0u)
-#endif  /* CYDEV_CHIP_MEMBER_5B */
+    #define CY_PSOC4_4100BL (0u != 0u)
+    #define CY_PSOC4_4200BL (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_4F */
 
 
 /*******************************************************************************
-* UDB revisions
+* IP blocks
 *******************************************************************************/
-#define CY_UDB_V0 (CY_PSOC5A)
-#define CY_UDB_V1 (!CY_UDB_V0)
+#if (CY_PSOC4)
+
+    /* Using SRSSv2 or SRS-Lite */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_SRSSV2            (0u == 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #else
+        #define CY_IP_SRSSV2            (0u != 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (0u == 0u)
+    #else
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (!CY_IP_CPUSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Product uses FLASH-Lite or regular FLASH */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FMLT              (0u != 0u)          /* FLASH-Lite */
+        #define CY_IP_FM                (!CY_IP_FMLT)       /* Regular FLASH */
+    #else
+        #define CY_IP_FMLT              (-1u != 0u)
+        #define CY_IP_FM                (!CY_IP_FMLT)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of interrupt request inputs to CM0 */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_INT_NR            (32u)
+    #else
+        #define CY_IP_INT_NR            (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FLASH_MACROS      (1u)
+    #else
+        #define CY_IP_FLASH_MACROS      (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_BLESS             (0u != 0u)
+    #else
+        #define CY_IP_BLESS             (0u != 0u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Watch Crystal Oscillator (WCO) is present (32kHz) */
+    #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_WCO               (0u != 0u)
+    #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)
+        #define CY_IP_WCO               (0u == 0u)
+    #elif (CY_IP_SRSSV2)
+        #define CY_IP_WCO               (-1u)
+    #else
+        #define CY_IP_WCO               (0u != 0u)
+    #endif  /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* The components version defines. Available started from cy_boot 4.20
+* Use the following construction in order to identify cy_boot version:
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)
+*******************************************************************************/
+#define CY_BOOT_4_20            (420u)
+#define CY_BOOT_VERSION         (CY_BOOT_4_20)
 
 
 /*******************************************************************************
@@ -104,7 +174,7 @@ typedef          float  float32;
 
 #endif  /* (!CY_PSOC3) */
 
-/* Signed or unsigned depending on the compiler selection */
+/* Signed or unsigned depending on compiler selection */
 typedef          char   char8;
 
 
@@ -154,7 +224,7 @@ typedef          char   char8;
 
 #else
 
-    /* Prototype for function to set a 24-bit register. Located at cyutils.c */
+    /* Prototype for function to set 24-bit register. Located at cyutils.c */
     extern void     CySetReg24(uint32 volatile * addr, uint32 value);
 
     #if(CY_PSOC4)
@@ -204,18 +274,39 @@ typedef          char   char8;
     #define XDATA
 
     #if defined(__ARMCC_VERSION)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit"), zero_init))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
+
+        /* Specifies a minimum alignment (in bytes) for variables of the
+        *  specified type.
+        */
         #define CY_ALIGN(align)     __align(align)
+
+
+        /* Attached to an enum, struct, or union type definition, specified that
+        *  the minimum required memory be used to represent the type.
+        */
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           __inline
     #elif defined (__GNUC__)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit")))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
         #define CY_ALIGN(align)     __attribute__ ((aligned(align)))
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           inline
     #elif defined (__ICCARM__)
+
         #define CY_NOINIT           __no_init
         #define CY_NORETURN         __noreturn
+        #define CY_PACKED           __packed
+        #define CY_PACKED_ATTR
+        #define CY_INLINE           inline
     #endif  /* (__ARMCC_VERSION) */
 
 #endif  /* (CY_PSOC3) */
@@ -223,12 +314,12 @@ typedef          char   char8;
 
 #if(CY_PSOC3)
 
-    /* 8051 naturally returns an 8 bit value. */
+    /* 8051 naturally returns 8 bit value. */
     typedef unsigned char cystatus;
 
 #else
 
-    /* ARM naturally returns a 32 bit value. */
+    /* ARM naturally returns 32 bit value. */
     typedef unsigned long cystatus;
 
 #endif  /* (CY_PSOC3) */
@@ -274,7 +365,7 @@ typedef volatile uint32 CYXDATA reg32;
     * KEIL for the 8051 is a big endian compiler This causes problems as the on chip
     * registers are little endian.  Byte swapping for two and four byte registers is
     * implemented in the functions below.  This will require conditional compilation
-    * of function prototypes in code.
+    * of function prototypes in the code.
     *******************************************************************************/
 
     /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
@@ -347,24 +438,24 @@ typedef volatile uint32 CYXDATA reg32;
 *  Data manipulation defines
 *******************************************************************************/
 
-/* Get 8 bits of a 16 bit value. */
+/* Get 8 bits of 16 bit value. */
 #define LO8(x)                  ((uint8) ((x) & 0xFFu))
 #define HI8(x)                  ((uint8) ((uint16)(x) >> 8))
 
-/* Get 16 bits of a 32 bit value. */
+/* Get 16 bits of 32 bit value. */
 #define LO16(x)                 ((uint16) ((x) & 0xFFFFu))
 #define HI16(x)                 ((uint16) ((uint32)(x) >> 16))
 
-/* Swap the byte ordering of a 32 bit value */
+/* Swap the byte ordering of 32 bit value */
 #define CYSWAP_ENDIAN32(x)  \
         ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))
 
-/* Swap the byte ordering of a 16 bit value */
+/* Swap the byte ordering of 16 bit value */
 #define CYSWAP_ENDIAN16(x)      ((uint16)(((x) << 8) | ((x) >> 8)))
 
 
 /*******************************************************************************
-* Defines the standard return values used PSoC content. A function is
+* Defines the standard return values used in PSoC content. A function is
 * not limited to these return values but can use them when returning standard
 * error values. Return values can be overloaded if documented in the function
 * header. On the 8051 a function can use a larger return type but still use the
@@ -413,24 +504,55 @@ typedef volatile uint32 CYXDATA reg32;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+#define CY_UDB_V0           (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#define CY_UDB_V1           (!CY_UDB_V0)
+#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#else
+    #define CY_PSOC4D   (0u != 0u)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#endif  /* CYDEV_CHIP_MEMBER_4D */
+#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#ifdef CYDEV_CHIP_MEMBER_5B
+    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#else
+    #define CY_PSOC5LP  (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_5B */
+
+#if (!CY_PSOC4)
+
+    /* Device is PSoC 3 and the revision is ES2 or earlier */
+    #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
 
-/* Device is PSoC 3 and the revision is ES2 or earlier */
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
+    /* Device is PSoC 3 and the revision is ES3 or later */
+    #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
 
-/* Device is PSoC 3 and the revision is ES3 or later */
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
+    /* Device is PSoC 5 and the revision is ES1 or earlier */
+    #define CY_PSOC5_ES1 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES1 or earlier */
-#define CY_PSOC5_ES1 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
+    /* Device is PSoC 5 and the revision is ES2 or later */
+    #define CY_PSOC5_ES2 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES2 or later */
-#define CY_PSOC5_ES2 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
+#endif  /* (!CY_PSOC4) */
 
 #endif  /* CY_BOOT_CYTYPES_H */
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
old mode 100755
new mode 100644
index 0a112316..4d2b71a4
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * FILENAME: cyutils.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   CyUtils provides function to handle 24-bit value writes.
+*   CyUtils provides a function to handle 24-bit value writes.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,11 +21,11 @@
     ****************************************************************************
     *
     * Summary:
-    *  Writes the 24-bit value to the specified register.
+    *  Writes a 24-bit value to the specified register.
     *
     * Parameters:
-    *  addr : adress where data must be written
-    *  value: data that must be written
+    *  addr : the address where data must be written.
+    *  value: the data that must be written.
     *
     * Return:
     *  None
@@ -56,7 +56,7 @@
         *  Reads the 24-bit value from the specified register.
         *
         * Parameters:
-        *  addr : adress where data must be read
+        *  addr : the address where data must be read.
         *
         * Return:
         *  None
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
index cdd707b5..b48e729d 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
  * File Name: project.h
- * PSoC Creator 3.0 Component Pack 7
+ * PSoC Creator  3.1
  *
  *  Description:
  *  This file is automatically generated by PSoC Creator and should not 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c
index b4c30ae2..81727948 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: timer_clock.c
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h
index 6690d480..7fbbb4cc 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: timer_clock.h
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
index 00a0252f..cb10da0b 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
@@ -7,11 +7,11 @@
   <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
   </block>
   <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" />
   </block>
   <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
@@ -82,9 +82,9 @@
   <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x4000646E" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x4000648E" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649E" bitWidth="8" desc="">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x4000648C" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -144,7 +144,7 @@
   <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
   </block>
   <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -166,19 +166,35 @@
     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   </block>
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
-    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
@@ -211,7 +227,7 @@
     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
-      <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />
+      <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
     </register>
     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr
index ebcde149..ad662c83 100755
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr differ
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
index 11b98e4e..3040c7e1 100644
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
index 4fd79e06..43b5b687 100755
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -259,6 +259,13 @@
 <build_action v="NONE" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="debug.h" persistent="..\..\src\debug.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -3184,14 +3191,14 @@
 <GlobalPages />
 <GlobalTools name="Code Generation">
 <GlobalPages>
+<name_val_pair name="General@Application Type" v="Bootloadable" />
+<name_val_pair name="General@Custom Code Gen Options" v="" />
+<name_val_pair name="General@Skip Code Generation" v="False" />
+<name_val_pair name="General@Custom Synthesis Options" v="" />
+<name_val_pair name="General@Quiet Output" v="True" />
 <name_val_pair name="General@Synthesis Goal" v="Speed" />
 <name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />
-<name_val_pair name="General@Quiet Output" v="True" />
-<name_val_pair name="General@Custom Synthesis Options" v="" />
-<name_val_pair name="General@Skip Code Generation" v="False" />
-<name_val_pair name="General@Custom Code Gen Options" v="" />
 <name_val_pair name="General@Virtual Node Substitution" v="3" />
-<name_val_pair name="General@Application Type" v="Bootloadable" />
 <name_val_pair name="General@Custom Fitter Options" v="" />
 </GlobalPages>
 </GlobalTools>
@@ -3202,9 +3209,9 @@
 </GlobalTools>
 <GlobalTools name="Customizer">
 <GlobalPages>
-<name_val_pair name="General@Customizer Build Mode" v="Release" />
-<name_val_pair name="General@Command Line Options" v="" />
 <name_val_pair name="General@Assembly References" v="" />
+<name_val_pair name="General@Command Line Options" v="" />
+<name_val_pair name="General@Customizer Build Mode" v="Release" />
 </GlobalPages>
 </GlobalTools>
 </name>
@@ -3212,485 +3219,500 @@
 <platform>
 <name v="c9323d49-d323-40b8-9b59-cc008d68a989">
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Preprocessor Definitions" v="DEBUG" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Struct Return Method" v="System Default" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Verbose Asm" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
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 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
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+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
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 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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 <name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
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+<WriteAppVersionLastSavedWith v="3.1.0.1570" />
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 </CyXmlSerializer>
\ No newline at end of file
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
index 592d03d2..6c4fda20 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
@@ -9,10 +9,10 @@
     <peripheral>
       <name>SCSI_Out_Bits</name>
       <description>No description available</description>
-      <baseAddress>0x40006474</baseAddress>
+      <baseAddress>0x4000647B</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -30,10 +30,10 @@
     <peripheral>
       <name>SCSI_Out_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x4000647E</baseAddress>
+      <baseAddress>0x4000647D</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -51,17 +51,17 @@
     <peripheral>
       <name>Debug_Timer</name>
       <description>No description available</description>
-      <baseAddress>0x400043A3</baseAddress>
+      <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0xB64</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
         <register>
           <name>Debug_Timer_GLOBAL_ENABLE</name>
           <description>PM.ACT.CFG</description>
-          <addressOffset>0x0</addressOffset>
+          <addressOffset>0x400043A3</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -79,7 +79,7 @@
         <register>
           <name>Debug_Timer_CONTROL</name>
           <description>TMRx.CFG0</description>
-          <addressOffset>0xB5D</addressOffset>
+          <addressOffset>0x40004F00</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -163,7 +163,7 @@
         <register>
           <name>Debug_Timer_CONTROL2</name>
           <description>TMRx.CFG1</description>
-          <addressOffset>0xB5E</addressOffset>
+          <addressOffset>0x40004F01</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -228,7 +228,7 @@
         <register>
           <name>Debug_Timer_CONTROL3_</name>
           <description>TMRx.CFG2</description>
-          <addressOffset>0xB5F</addressOffset>
+          <addressOffset>0x40004F02</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -323,7 +323,7 @@
         <register>
           <name>Debug_Timer_PERIOD</name>
           <description>TMRx.PER0 - Assigned Period</description>
-          <addressOffset>0xB61</addressOffset>
+          <addressOffset>0x40004F04</addressOffset>
           <size>16</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -332,7 +332,7 @@
         <register>
           <name>Debug_Timer_COUNTER</name>
           <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
-          <addressOffset>0xB63</addressOffset>
+          <addressOffset>0x40004F06</addressOffset>
           <size>16</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -343,10 +343,10 @@
     <peripheral>
       <name>SCSI_Filtered</name>
       <description>No description available</description>
-      <baseAddress>0x4000646E</baseAddress>
+      <baseAddress>0x4000646C</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x31</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -501,7 +501,7 @@
       <baseAddress>0x40006466</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x31</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -653,10 +653,10 @@
     <peripheral>
       <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x40006470</baseAddress>
+      <baseAddress>0x4000647C</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -674,17 +674,17 @@
     <peripheral>
       <name>USBFS</name>
       <description>USBFS</description>
-      <baseAddress>0x40004394</baseAddress>
+      <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1D0A</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
         <register>
           <name>USBFS_PM_USB_CR0</name>
           <description>USB Power Mode Control Register 0</description>
-          <addressOffset>0x0</addressOffset>
+          <addressOffset>0x40004394</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -716,7 +716,7 @@
         <register>
           <name>USBFS_PM_ACT_CFG</name>
           <description>Active Power Mode Configuration Register</description>
-          <addressOffset>0x11</addressOffset>
+          <addressOffset>0x400043A5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -725,7 +725,7 @@
         <register>
           <name>USBFS_PM_STBY_CFG</name>
           <description>Standby Power Mode Configuration Register</description>
-          <addressOffset>0x21</addressOffset>
+          <addressOffset>0x400043B5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -734,7 +734,7 @@
         <register>
           <name>USBFS_PRT_PS</name>
           <description>Port Pin State Register</description>
-          <addressOffset>0xE5D</addressOffset>
+          <addressOffset>0x400051F1</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -759,7 +759,7 @@
         <register>
           <name>USBFS_PRT_DM0</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5E</addressOffset>
+          <addressOffset>0x400051F2</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -784,7 +784,7 @@
         <register>
           <name>USBFS_PRT_DM1</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5F</addressOffset>
+          <addressOffset>0x400051F3</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -809,7 +809,7 @@
         <register>
           <name>USBFS_PRT_INP_DIS</name>
           <description>Input buffer disable override</description>
-          <addressOffset>0xE64</addressOffset>
+          <addressOffset>0x400051F8</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -834,7 +834,7 @@
         <register>
           <name>USBFS_EP0_DR0</name>
           <description>bmRequestType</description>
-          <addressOffset>0x1C6C</addressOffset>
+          <addressOffset>0x40006000</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -843,7 +843,7 @@
         <register>
           <name>USBFS_EP0_DR1</name>
           <description>bRequest</description>
-          <addressOffset>0x1C6D</addressOffset>
+          <addressOffset>0x40006001</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -852,7 +852,7 @@
         <register>
           <name>USBFS_EP0_DR2</name>
           <description>wValueLo</description>
-          <addressOffset>0x1C6E</addressOffset>
+          <addressOffset>0x40006002</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -861,7 +861,7 @@
         <register>
           <name>USBFS_EP0_DR3</name>
           <description>wValueHi</description>
-          <addressOffset>0x1C6F</addressOffset>
+          <addressOffset>0x40006003</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -870,7 +870,7 @@
         <register>
           <name>USBFS_EP0_DR4</name>
           <description>wIndexLo</description>
-          <addressOffset>0x1C70</addressOffset>
+          <addressOffset>0x40006004</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -879,7 +879,7 @@
         <register>
           <name>USBFS_EP0_DR5</name>
           <description>wIndexHi</description>
-          <addressOffset>0x1C71</addressOffset>
+          <addressOffset>0x40006005</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -888,7 +888,7 @@
         <register>
           <name>USBFS_EP0_DR6</name>
           <description>lengthLo</description>
-          <addressOffset>0x1C72</addressOffset>
+          <addressOffset>0x40006006</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -897,7 +897,7 @@
         <register>
           <name>USBFS_EP0_DR7</name>
           <description>lengthHi</description>
-          <addressOffset>0x1C73</addressOffset>
+          <addressOffset>0x40006007</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -906,7 +906,7 @@
         <register>
           <name>USBFS_CR0</name>
           <description>USB Control Register 0</description>
-          <addressOffset>0x1C74</addressOffset>
+          <addressOffset>0x40006008</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -915,8 +915,8 @@
             <field>
               <name>device_address</name>
               <description>No description available</description>
-              <lsb>6</lsb>
-              <msb>0</msb>
+              <lsb>0</lsb>
+              <msb>6</msb>
               <access>read-only</access>
             </field>
             <field>
@@ -931,7 +931,7 @@
         <register>
           <name>USBFS_CR1</name>
           <description>USB Control Register 1</description>
-          <addressOffset>0x1C75</addressOffset>
+          <addressOffset>0x40006009</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -970,7 +970,7 @@
         <register>
           <name>USBFS_SIE_EP1_CR0</name>
           <description>The Endpoint1 Control Register</description>
-          <addressOffset>0x1C7A</addressOffset>
+          <addressOffset>0x4000600E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -979,7 +979,7 @@
         <register>
           <name>USBFS_USBIO_CR0</name>
           <description>USBIO Control Register 0</description>
-          <addressOffset>0x1C7C</addressOffset>
+          <addressOffset>0x40006010</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1018,7 +1018,7 @@
         <register>
           <name>USBFS_USBIO_CR1</name>
           <description>USBIO Control Register 1</description>
-          <addressOffset>0x1C7E</addressOffset>
+          <addressOffset>0x40006012</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1057,7 +1057,7 @@
         <register>
           <name>USBFS_SIE_EP2_CR0</name>
           <description>The Endpoint2 Control Register</description>
-          <addressOffset>0x1C8A</addressOffset>
+          <addressOffset>0x4000601E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1066,7 +1066,7 @@
         <register>
           <name>USBFS_SIE_EP3_CR0</name>
           <description>The Endpoint3 Control Register</description>
-          <addressOffset>0x1C9A</addressOffset>
+          <addressOffset>0x4000602E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1075,7 +1075,7 @@
         <register>
           <name>USBFS_SIE_EP4_CR0</name>
           <description>The Endpoint4 Control Register</description>
-          <addressOffset>0x1CAA</addressOffset>
+          <addressOffset>0x4000603E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1084,7 +1084,7 @@
         <register>
           <name>USBFS_SIE_EP5_CR0</name>
           <description>The Endpoint5 Control Register</description>
-          <addressOffset>0x1CBA</addressOffset>
+          <addressOffset>0x4000604E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1093,7 +1093,7 @@
         <register>
           <name>USBFS_SIE_EP6_CR0</name>
           <description>The Endpoint6 Control Register</description>
-          <addressOffset>0x1CCA</addressOffset>
+          <addressOffset>0x4000605E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1102,7 +1102,7 @@
         <register>
           <name>USBFS_SIE_EP7_CR0</name>
           <description>The Endpoint7 Control Register</description>
-          <addressOffset>0x1CDA</addressOffset>
+          <addressOffset>0x4000606E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1111,7 +1111,7 @@
         <register>
           <name>USBFS_SIE_EP8_CR0</name>
           <description>The Endpoint8 Control Register</description>
-          <addressOffset>0x1CEA</addressOffset>
+          <addressOffset>0x4000607E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1120,7 +1120,7 @@
         <register>
           <name>USBFS_BUF_SIZE</name>
           <description>Dedicated Endpoint Buffer Size Register</description>
-          <addressOffset>0x1CF8</addressOffset>
+          <addressOffset>0x4000608C</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1129,7 +1129,7 @@
         <register>
           <name>USBFS_EP_ACTIVE</name>
           <description>Endpoint Active Indication Register</description>
-          <addressOffset>0x1CFA</addressOffset>
+          <addressOffset>0x4000608E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1138,7 +1138,7 @@
         <register>
           <name>USBFS_EP_TYPE</name>
           <description>Endpoint Type (IN/OUT) Indication</description>
-          <addressOffset>0x1CFB</addressOffset>
+          <addressOffset>0x4000608F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1147,7 +1147,7 @@
         <register>
           <name>USBFS_USB_CLK_EN</name>
           <description>USB Block Clock Enable Register</description>
-          <addressOffset>0x1D09</addressOffset>
+          <addressOffset>0x4000609D</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
index 9d0ffff8..8bbd6de3 100755
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c
index ea1c5aa3..4470b3b5 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: BL.c
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloader component. The API includes functions
@@ -8,7 +8,7 @@
 *   jumping to the application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -24,22 +24,26 @@
 * The Checksum and SizeBytes are forcefully set in code. We then post process
 * the hex file from the linker and inject their values then. When the hex file
 * is loaded onto the device these two variables should have valid values.
-* Because the compiler can do optimizations remove the constant
+* Because the compiler can do optimizations to remove the constant
 * accesses, these should not be accessed directly. Instead, the variables
 * CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the
 * proper values at runtime.
 *******************************************************************************/
 #if defined(__ARMCC_VERSION) || defined (__GNUC__)
-    __attribute__((section (".bootloader")))
+    __attribute__((section (".bootloader"), used))
 #elif defined (__ICCARM__)
     #pragma location=".bootloader"
 #endif  /* defined(__ARMCC_VERSION) || defined (__GNUC__) */
 
-const uint8  CYCODE BL_Checksum = 0u;
+#if defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__)
+           const uint8  CYCODE BL_Checksum = 0u;
+#elif defined (__ICCARM__)
+    __root const uint8  CYCODE BL_Checksum = 0u;
+#endif  /* defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__) */
 const uint8  CYCODE *BL_ChecksumAccess  = (const uint8  CYCODE *)(&BL_Checksum);
 
 #if defined(__ARMCC_VERSION) || defined (__GNUC__)
-    __attribute__((section (".bootloader")))
+    __attribute__((section (".bootloader"), used))
 #elif defined (__ICCARM__)
     #pragma location=".bootloader"
 #endif  /* defined(__ARMCC_VERSION) || defined (__GNUC__) */
@@ -64,25 +68,12 @@ static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMAL
 static uint16   BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \
                                     ;
 
-static uint8    BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \
-                                    ;
-#if(!CY_PSOC4)
-static uint8    BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \
-                                    ;
-#endif /* (!CY_PSOC4) */
-
 static void     BL_HostLink(uint8 timeOut) \
                                     ;
 
 static void     BL_LaunchApplication(void) CYSMALL \
                                     ;
 
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
-                                    ;
-
-static uint32   BL_GetMetadata(uint8 fieldName, uint8 appId)\
-                                    ;
-
 #if(!CY_PSOC3)
     /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file.  */
     static void     BL_LaunchBootloadable(uint32 appAddr);
@@ -101,7 +92,7 @@ static uint32   BL_GetMetadata(uint8 fieldName, uint8 appId)\
 *  buffer:
 *     The buffer containing the data to compute the checksum for
 *  size:
-*     The number of bytes in buffer to compute the checksum for
+*     The number of bytes in the buffer to compute the checksum for
 *
 * Returns:
 *  16 bit checksum for the provided data
@@ -169,14 +160,19 @@ static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \
 
 
 /*******************************************************************************
-* Function Name: BL_Calc8BitFlashSum
+* Function Name: BL_Calc8BitSum
 ********************************************************************************
 *
 * Summary:
 *  This computes the 8 bit sum for the provided number of bytes contained in
-*  flash.
+*  FLASH (if baseAddr equals CY_FLASH_BASE) or EEPROM (if baseAddr equals
+*  CY_EEPROM_BASE).
 *
 * Parameters:
+* baseAddr:
+*   CY_FLASH_BASE
+*   CY_EEPROM_BASE - applicable only for PSoC 3 / PSoC 5LP devices.
+*
 *  start:
 *     The starting address to start summing data for
 *  size:
@@ -186,87 +182,62 @@ static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \
 *   8 bit sum for the provided data
 *
 *******************************************************************************/
-static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) \
                 CYSMALL 
 {
     uint8 CYDATA sum = 0u;
 
+    #if(!CY_PSOC4)
+        CYASSERT((baseAddr == CY_EEPROM_BASE) || (baseAddr == CY_FLASH_BASE));
+    #else
+        CYASSERT(baseAddr == CY_FLASH_BASE);
+    #endif  /* (!CY_PSOC4) */
+
     while (size > 0u)
     {
         size--;
-        sum += BL_GET_CODE_BYTE(start + size);
+        sum += (*((uint8  *)(baseAddr + start + size)));
     }
 
     return(sum);
 }
 
 
-#if(!CY_PSOC4)
-
-    /*******************************************************************************
-    * Function Name: BL_Calc8BitEepromSum
-    ********************************************************************************
-    *
-    * Summary:
-    *  This computes the 8 bit sum for the provided number of bytes contained in
-    *  EEPROM.
-    *
-    * Parameters:
-    *  start:
-    *     The starting address to start summing data for
-    *  size:
-    *     The number of bytes to read and compute the sum for
-    *
-    * Returns:
-    *   8 bit sum for the provided data
-    *
-    *******************************************************************************/
-    static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \
-                    CYSMALL 
-    {
-        uint8 CYDATA sum = 0u;
-
-        while (size > 0u)
-        {
-            size--;
-            sum += BL_GET_EEPROM_BYTE(start + size);
-        }
-
-        return(sum);
-    }
-
-#endif  /* (!CY_PSOC4) */
-
-
 /*******************************************************************************
 * Function Name: BL_Start
 ********************************************************************************
 * Summary:
-*  This function is called in order executing following algorithm:
+*  This function is called in order to execute the following algorithm:
 *
-*  - Identify active bootloadable application (applicable only to
-*    Multi-application bootloader)
+*  - Identify the active bootloadable application (applicable only to
+*    the Multi-application bootloader)
 *
-*  - Validate bootloader application (desing-time configurable, Bootloader
+*  - Validate the bootloader application (design-time configurable, Bootloader
 *    application validation option of the component customizer)
 *
-*  - Validate active bootloadable application
+*  - Validate the active bootloadable application. If active bootloadable
+*    application is not valid, and the other bootloadable application (inactive)
+*    is valid, the last one is started.
 *
-*  - Run communication subroutine (desing-time configurable, Wait for command
+*  - Run a communication subroutine (design-time configurable, Wait for command
 *    option of the component customizer)
 *
-*  - Schedule bootloadable and reset device
+*  - Schedule the bootloadable and reset the device
 *
 * Parameters:
 *  None
 *
 * Return:
 *  This method will never return. It will either load a new application and
-*  reset the device or it will jump directly to the existing application.
+*  reset the device or jump directly to the existing application. The CPU is
+*  halted, if validation failed when "Bootloader application validation" option
+*  is enabled.
+*  PSoC 3/PSoC 5: The CPU is halted if Flash initialization fails.
 *
 * Side Effects:
-*  If this method determines that the bootloader appliation itself is corrupt,
-*  this method will not return, instead it will simply hang the application.
+*  If Bootloader application validation option is enabled and this method
+*  determines that the bootloader application itself is corrupt, this method
+*  will not return, instead it will simply hang the application.
 *
 *******************************************************************************/
 void BL_Start(void) CYSMALL 
@@ -276,60 +247,149 @@ void BL_Start(void) CYSMALL
     #endif    /* (0u != BL_BOOTLOADER_APP_VALIDATION) */
 
     #if(!CY_PSOC4)
-        uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+        #if(0u != BL_FAST_APP_VALIDATION)
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required starting from cy_boot 4.20 */
+                uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u != BL_FAST_APP_VALIDATION) */
     #endif  /* (!CY_PSOC4) */
 
-    cystatus tmpStatus;
+    cystatus validApp  = CYRET_BAD_DATA;
 
 
     /* Identify active bootloadable application */
     #if(0u != BL_DUAL_APP_BOOTLOADER)
 
-        if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE)
+        /* Assumes no active bootloadable application. Bootloader is active. */
+        BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;
+
+        /* Bootloadable # A is active */
+        if(BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 0u) == BL_MD_BTLDB_IS_ACTIVE)
         {
-            BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+            /*******************************************************************
+            * -----------------------------------------------------------
+            * |      | Bootloadable A | Bootloadable B |                |
+            * | Case |---------------------------------|     Action     |
+            * |      | Active | Valid | Active | Valid |                |
+            * |------|--------------------------------------------------|
+            * |  9   |    1   |   0   |   0    |   0   | Bootloader     |
+            * |  10  |    1   |   0   |   0    |   1   | Bootloadable B |
+            * |  11  |    1   |   0   |   1    |   0   | Bootloader     |
+            * |  12  |    1   |   0   |   1    |   1   | Bootloadable B |
+            * |  13  |    1   |   1   |   0    |   0   | Bootloadable A |
+            * |  14  |    1   |   1   |   0    |   1   | Bootloadable A |
+            * |  15  |    1   |   1   |   1    |   0   | Bootloadable A |
+            * |  16  |    1   |   1   |   1    |   1   | Bootloadable A |
+            * -----------------------------------------------------------
+            *******************************************************************/
+            if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
+            {
+                /* Cases # 13,  14, 15, and 16 */
+                BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+                validApp = CYRET_SUCCESS;
+            }
+            else
+            {
+                if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))
+                {
+                    /* Cases # 10 and 12 */
+                    BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+                    validApp = CYRET_SUCCESS;
+                }
+            }
         }
-        else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE)
+
+        /*  Active bootloadable application is not identified */
+        if(BL_activeApp == BL_MD_BTLDB_ACTIVE_NONE)
         {
-            BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+            /*******************************************************************
+            * -----------------------------------------------------------
+            * |      | Bootloadable A | Bootloadable B |                |
+            * | Case |---------------------------------|     Action     |
+            * |      | Active | Valid | Active | Valid |                |
+            * |------|--------------------------------------------------|
+            * |  1   |    0   |   0   |   0    |   0   | Bootloader     |
+            * |  2   |    0   |   0   |   0    |   1   | Bootloader     |
+            * |  3   |    0   |   0   |   1    |   0   | Bootloader     |
+            * |  4   |    0   |   0   |   1    |   1   | Bootloadable B |
+            * |  5   |    0   |   1   |   0    |   0   | Bootloader     |
+            * |  6   |    0   |   1   |   0    |   1   | Bootloader     |
+            * |  7   |    0   |   1   |   1    |   0   | Bootloadable A |
+            * |  8   |    0   |   1   |   1    |   1   | Bootloadable B |
+            * -----------------------------------------------------------
+            *******************************************************************/
+            if (BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 1u) ==
+                    BL_MD_BTLDB_IS_ACTIVE)
+            {
+                /* Cases # 3, 4, 7, and 8 */
+                if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))
+                {
+                    /* Cases # 4 and 8 */
+                    BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+                    validApp = CYRET_SUCCESS;
+                }
+                else
+                {
+                    if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
+                    {
+                        /* Cases # 7 */
+                        BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+                        validApp = CYRET_SUCCESS;
+                    }
+                }
+            }
         }
-        else
+    #else
+        if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
         {
-            BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;
+            validApp = CYRET_SUCCESS;
         }
-
     #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
 
 
     /* Initialize Flash subsystem for non-PSoC 4 devices */
     #if(!CY_PSOC4)
-        if (CYRET_SUCCESS != CySetTemp())
-        {
-            CyHalt(0x00u);
-        }
+        #if(0u != BL_FAST_APP_VALIDATION)
 
-        if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
-        {
-            CyHalt(0x00u);
-        }
+            if (CYRET_SUCCESS != CySetTemp())
+            {
+                CyHalt(0x00u);
+            }
+
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required with cy_boot 4.20 */
+                if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
+                {
+                    CyHalt(0x00u);
+                }
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u != BL_FAST_APP_VALIDATION) */
     #endif  /* (CY_PSOC4) */
 
 
     /***********************************************************************
     * Bootloader Application Validation
     *
-    * Halt device if:
-    *  - Calculated checksum does not much one stored in metadata section
-    *  - Invalid pointer to the place where bootloader application ends
-    *  - Flash subsystem where not initialized correctly
+    * Halt the device if:
+    *  - A calculated checksum does not match the one stored in the metadata
+    *     section.
+    *  - There is an invalid pointer to the place where the bootloader
+    *    application ends.
+    *  - Flash subsystem was not initialized correctly
     ***********************************************************************/
     #if(0u != BL_BOOTLOADER_APP_VALIDATION)
 
         /* Calculate Bootloader application checksum */
-        calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR,
+        calcedChecksum = BL_Calc8BitSum(CY_FLASH_BASE,
+                BL_MD_BTLDR_ADDR_PTR,
                 *BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR);
 
-        /* we actually included the checksum, so remove it */
+        /* we included checksum, so remove it */
         calcedChecksum -= *BL_ChecksumAccess;
         calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);
 
@@ -344,17 +404,14 @@ void BL_Start(void) CYSMALL
 
 
     /***********************************************************************
-    * Active Bootloadable Application Validation
-    *
-    * If active bootloadable application is invalid or bootloader
+    * If the active bootloadable application is invalid or a bootloader
     * application is scheduled - do the following:
-    *  - schedule bootloader application to be run after software reset
-    *  - Go to the communication subroutine. Will wait for commands forever
+    *  - schedule the bootloader application to be run after software reset
+    *  - Go to the communication subroutine. The HostLink() will wait for
+    *    the commands forever.
     ***********************************************************************/
-    tmpStatus = BL_ValidateBootloadable(BL_activeApp);
-
     if ((BL_GET_RUN_TYPE == BL_START_BTLDR) ||
-        (CYRET_SUCCESS != tmpStatus))
+        (CYRET_SUCCESS != validApp))
     {
         BL_SET_RUN_TYPE(0u);
 
@@ -362,10 +419,10 @@ void BL_Start(void) CYSMALL
     }
 
 
-    /* Go to the communication subroutine. Will wait for commands specifed time */
+    /* Go to communication subroutine. Will wait for commands for specifed time */
     #if(0u != BL_WAIT_FOR_COMMAND)
 
-        /* Timeout is in 100s of miliseconds */
+        /* Timeout is in 100s of milliseconds */
         BL_HostLink(BL_WAIT_FOR_COMMAND_TIME);
 
     #endif  /* (0u != BL_WAIT_FOR_COMMAND) */
@@ -381,13 +438,13 @@ void BL_Start(void) CYSMALL
 ********************************************************************************
 *
 * Summary:
-*  Jumps the PC to the start address of the user application in flash.
+*  Schedules bootloadable application and resets device
 *
 * Parameters:
 *  None
 *
 * Returns:
-*  This method will never return if it succesfully goes to the user application.
+*  This method will never return.
 *
 *******************************************************************************/
 static void BL_LaunchApplication(void) CYSMALL 
@@ -399,21 +456,83 @@ static void BL_LaunchApplication(void) CYSMALL
 }
 
 
+/*******************************************************************************
+* Function Name: BL_Exit
+********************************************************************************
+*
+* Summary:
+*  Schedules the specified application and performs software reset to launch
+*  a specified application.
+*
+*  If the specified application is not valid, the Bootloader (the result of the
+*  ValidateBootloadable() function execution returns other than CYRET_SUCCESS,
+*  the bootloader application is launched.
+*
+* Parameters:
+*  appId: application to be started:
+*  BL_EXIT_TO_BTLDR   - Bootloader application will be started on
+*                                     software reset.
+*  BL_EXIT_TO_BTLDB,
+*  BL_EXIT_TO_BTLDB_1 - Bootloadable application # 1 will be
+*                                     started on software reset.
+*  BL_EXIT_TO_BTLDB_2 - Bootloadable application # 2 will be
+*                                     started on software reset. Available only
+*                                     if Multi-Application option is enabled in
+*                                     the component customizer.
+* Returns:
+*  This function never returns.
+*
+*******************************************************************************/
+void BL_Exit(uint8 appId) CYSMALL 
+{
+    if(BL_EXIT_TO_BTLDR == appId)
+    {
+        BL_SET_RUN_TYPE(0x0u);
+    }
+    else
+    {
+        if(CYRET_SUCCESS == BL_ValidateBootloadable(appId))
+        {
+            /* Set active application in metadata */
+            uint8 CYDATA idx;
+            for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++)
+            {
+                BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx),
+                                              (uint8 )(idx == appId));
+            }
+
+        #if(0u != BL_DUAL_APP_BOOTLOADER)
+            BL_activeApp = appId;
+        #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+            BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);
+        }
+        else
+        {
+            BL_SET_RUN_TYPE(0u);
+        }
+    }
+
+    CySoftwareReset();
+}
+
+
 /*******************************************************************************
 * Function Name: CyBtldr_CheckLaunch
 ********************************************************************************
 *
 * Summary:
-*  This routine checks to see if the bootloader or the bootloadable application
-*  should be run.  If the application is to be run, it will start executing.
-*  If the bootloader is to be run, it will return so the bootloader can
+*  This routine checks if the bootloader or the bootloadable application has to
+*  be run.  If the application has to be run, it will start executing.
+*  If the bootloader is to be run, it will return, so the bootloader can
 *  continue starting up.
 *
 * Parameters:
 *  None
 *
 * Returns:
-*  None
+*  It will not return if it determines that the bootloadable application should
+*  be run.
 *
 *******************************************************************************/
 void CyBtldr_CheckLaunch(void) CYSMALL 
@@ -422,7 +541,7 @@ void CyBtldr_CheckLaunch(void) CYSMALL
 #if(CY_PSOC4)
 
     /*******************************************************************************
-    * Set cyBtldrRunType to zero in case of non-software reset occured. This means
+    * Set cyBtldrRunType to zero in case of non-software reset occurred. This means
     * that bootloader application is scheduled - that is initial clean state. The
     * value of cyBtldrRunType is valid only in case of software reset.
     *******************************************************************************/
@@ -444,17 +563,17 @@ void CyBtldr_CheckLaunch(void) CYSMALL
         * application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS
         * is something other than 0.
         *******************************************************************************/
-        if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp))
+        if(0u != BL_GetMetadata(BL_GET_BTLDB_ADDR, BL_activeApp))
         {
             /* Never return from this method */
-            BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR,
+            BL_LaunchBootloadable(BL_GetMetadata(BL_GET_BTLDB_ADDR,
                                                                              BL_activeApp));
         }
     }
 }
 
 
-/* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */
+/* Moves argument appAddr (RO) into PC, moving execution to appAddr */
 #if defined (__ARMCC_VERSION)
 
     __asm static void BL_LaunchBootloadable(uint32 appAddr)
@@ -486,25 +605,37 @@ void CyBtldr_CheckLaunch(void) CYSMALL
 * Function Name: BL_ValidateBootloadable
 ********************************************************************************
 * Summary:
-*  This routine computes the checksum, zero check, 0xFF check of the
-*  application area to determine whether a valid application is loaded.
+*  Performs the bootloadable application validation by calculating the
+*  application image checksum and comparing it with the checksum value stored
+*  in the Bootloadable Application Checksum field of the metadata section.
+*
+*  If the Fast bootloadable application validation option is enabled in the
+*  component customizer and bootloadable application successfully passes
+*  validation, the Bootloadable Application Verification Status field of the
+*  metadata section is updated. Refer to the Metadata Layout section for the
+*  details.
+*
+*  If the Fast bootloadable application validation option is enabled and
+*  Bootloadable Application Verification Status field of the metadata section
+*  claims that bootloadable application is valid, the function returns
+*  CYRET_SUCCESS without further checksum calculation.
 *
 * Parameters:
 *  appId:
-*      The application number to verify
+*  The number of the bootloadable application should be 0 for the normal
+*  bootloader and 0 or 1 for the Multi-Application bootloader.
 *
 * Returns:
-*  CYRET_SUCCESS  - if successful
-*  CYRET_BAD_DATA - if the bootloadable is corrupt
+*  Returns CYRET_SUCCESS if the specified bootloadable application is valid.
 *
 *******************************************************************************/
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
+cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 
     {
         uint32 CYDATA idx;
 
         uint32 CYDATA end   = BL_FIRST_APP_BYTE(appId) +
-                                BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH,
+                                BL_GetMetadata(BL_GET_BTLDB_LENGTH,
                                                        appId);
 
         CYBIT         valid = 0u; /* Assume bad flash image */
@@ -523,7 +654,9 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 
         #if(0u != BL_FAST_APP_VALIDATION)
 
-            if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED)
+
+            if(BL_GetMetadata(BL_GET_BTLDB_STATUS, appId) ==
+               BL_MD_BTLDB_IS_VERIFIED)
             {
                 return(CYRET_SUCCESS);
             }
@@ -557,7 +690,7 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
             /* Add ECC data to checksum */
             idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u);
 
-            /* Flash may run into meta data, ECC does not so use full row */
+            /* Flash may run into meta data, so ECC does not use full row */
             end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF))
                 ? (CY_FLASH_SIZE >> 3u)
                 : (end >> 3u);
@@ -572,7 +705,8 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 
         calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);
 
-        if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) ||
+
+        if((calcedChecksum != BL_GetMetadata(BL_GET_BTLDB_CHECKSUM, appId)) ||
            (0u == valid))
         {
             return(CYRET_BAD_DATA);
@@ -601,7 +735,7 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 * Parameters:
 *  timeOut:
 *   The amount of time to listen for data before giving up. Timeout is
-*   measured in 10s of ms.  Use 0 for infinite wait.
+*   measured in 10s of ms.  Use 0 for an infinite wait.
 *
 * Return:
 *   None
@@ -618,9 +752,9 @@ static void BL_HostLink(uint8 timeOut)
     uint16    CYDATA dataOffset = 0u;
     uint8     CYDATA timeOutCnt = 10u;
 
-    #if(0u == BL_DUAL_APP_BOOTLOADER)
+    #if(0u != BL_FAST_APP_VALIDATION)
         uint8 CYDATA clearedMetaData = 0u;
-    #endif  /* (0u == BL_DUAL_APP_BOOTLOADER) */
+    #endif  /* (0u != BL_FAST_APP_VALIDATION) */
 
     CYBIT     communicationState = BL_COMMUNICATION_STATE_IDLE;
 
@@ -628,6 +762,40 @@ static void BL_HostLink(uint8 timeOut)
     uint8     dataBuffer  [BL_SIZEOF_COMMAND_BUFFER];
 
 
+    #if(!CY_PSOC4)
+        #if(0u == BL_FAST_APP_VALIDATION)
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required with cy_boot 4.20 */
+                uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u == BL_FAST_APP_VALIDATION) */
+    #endif  /* (CY_PSOC4) */
+
+
+
+    #if(!CY_PSOC4)
+        #if(0u == BL_FAST_APP_VALIDATION)
+
+            /* Initialize Flash subsystem for non-PSoC 4 devices */
+            if (CYRET_SUCCESS != CySetTemp())
+            {
+                CyHalt(0x00u);
+            }
+
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required with cy_boot 4.20 */
+                if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
+                {
+                    CyHalt(0x00u);
+                }
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u == BL_FAST_APP_VALIDATION) */
+    #endif  /* (CY_PSOC4) */
+
     /* Initialize communications channel. */
     CyBtldrCommStart();
 
@@ -716,10 +884,12 @@ static void BL_HostLink(uint8 timeOut)
                         {
                             #if(CY_PSOC3)
                                 (void) memcpy(&packetBuffer[BL_DATA_ADDR],
-                                            ((uint8  CYCODE *) (BL_META_BASE(btldrData))), 56);
+                                            ((uint8  CYCODE *) (BL_META_BASE(btldrData))),
+                                            BL_GET_METADATA_RESPONSE_SIZE);
                             #else
                                 (void) memcpy(&packetBuffer[BL_DATA_ADDR],
-                                            (uint8 *) BL_META_BASE(btldrData), 56u);
+                                            (uint8 *) BL_META_BASE(btldrData),
+                                            BL_GET_METADATA_RESPONSE_SIZE);
                             #endif  /* (CY_PSOC3) */
 
                             rspSize = 56u;
@@ -754,25 +924,59 @@ static void BL_HostLink(uint8 timeOut)
             /***************************************************************************
             *   Get flash size
             ***************************************************************************/
+
+            /* Replace BL_NUM_OF_FLASH_ARRAYS with CY_FLASH_NUMBER_ARRAYS */
+
+
             #if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL)
 
                 case BL_COMMAND_REPORT_SIZE:
 
+                    /* btldrData - holds flash array ID sent by host */
+
                     if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u))
                     {
-                        /* btldrData holds flash array ID sent by host */
-                        if(btldrData < BL_NUM_OF_FLASH_ARRAYS)
+                        if(btldrData < CY_FLASH_NUMBER_ARRAYS)
                         {
-                            #if (1u == BL_NUM_OF_FLASH_ARRAYS)
-                                uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE;
-                            #else
-                                uint16 CYDATA startRow = 0u;
-                            #endif  /* (1u == BL_NUM_OF_FLASH_ARRAYS) */
+                            uint16 CYDATA startRow;
+                            uint8  CYDATA ArrayIdBtlderEnds;
+
+
+                            /*******************************************************************************
+                            * - For the flash array where bootloader application ends, return the first
+                            *   full row after the bootloader application.
+                            *
+                            * - For the fully occupied flash array, the number of rows in array is returned.
+                            *   As there is no space for the bootloadable application in this array.
+                            *
+                            * - For the arrays next to the occupied array, zero is returned.
+                            *   The bootloadable application can written from the their beginning.
+                            *
+                            *******************************************************************************/
+                            ArrayIdBtlderEnds = (uint8)  (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ARRAY);
+
+                            if (btldrData == ArrayIdBtlderEnds)
+                            {
+                                startRow = (uint16) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ROW) %
+                                            BL_NUMBER_OF_ROWS_IN_ARRAY;
+                            }
+                            else if (btldrData > ArrayIdBtlderEnds)
+                            {
+                                startRow = BL_FIRST_ROW_IN_ARRAY;
+                            }
+                            else /* (btldrData < ArrayIdBtlderEnds) */
+                            {
+                                startRow = BL_NUMBER_OF_ROWS_IN_ARRAY;
+                            }
 
                             packetBuffer[BL_DATA_ADDR]      = LO8(startRow);
                             packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow);
-                            packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u);
-                            packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u);
+
+                            packetBuffer[BL_DATA_ADDR + 2u] =
+                                        LO8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);
+
+                            packetBuffer[BL_DATA_ADDR + 3u] =
+                                        HI8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);
 
                             rspSize = 4u;
                             ackCode = CYRET_SUCCESS;
@@ -800,7 +1004,7 @@ static void BL_HostLink(uint8 timeOut)
                                 (uint8)BL_ValidateBootloadable(btldrData);
 
                             packetBuffer[BL_DATA_ADDR + 1u] =
-                                (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData);
+                                (uint8) BL_GetMetadata(BL_GET_BTLDB_ACTIVE, btldrData);
 
                             rspSize = 2u;
                             ackCode = CYRET_SUCCESS;
@@ -846,7 +1050,7 @@ static void BL_HostLink(uint8 timeOut)
                         #if(CY_PSOC3)
                             (void) memset(dataBuffer, (char8) 0, (int16) dataOffset);
                         #else
-                            (void) memset(dataBuffer, 0, dataOffset);
+                            (void) memset(dataBuffer, 0, (uint32) dataOffset);
                         #endif  /* (CY_PSOC3) */
                     }
                     else
@@ -865,11 +1069,11 @@ static void BL_HostLink(uint8 timeOut)
                     #if(CY_PSOC3)
                         (void) memcpy(&dataBuffer[dataOffset],
                                       &packetBuffer[BL_DATA_ADDR + 3u],
-                                      ( int16 )pktSize - 3);
+                                      (int16) pktSize - 3);
                     #else
                         (void) memcpy(&dataBuffer[dataOffset],
                                       &packetBuffer[BL_DATA_ADDR + 3u],
-                                      pktSize - 3u);
+                                      (uint32) pktSize - 3u);
                     #endif  /* (CY_PSOC3) */
 
                     dataOffset += (pktSize - 3u);
@@ -898,82 +1102,155 @@ static void BL_HostLink(uint8 timeOut)
                     /* Check if we have all data to program */
                     if(dataOffset == pktSize)
                     {
-                        /* Get FLASH/EEPROM row number */
+                        uint16 row;
+                        uint16 firstRow;
+
+                        /* Get FLASH/EEPROM row number inside of the array */
                         dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) |
                                               packetBuffer[BL_DATA_ADDR + 1u];
 
+
+                        /* Metadata section resides in Flash (cannot be in EEPROM). */
                         #if(!CY_PSOC4)
                             if(btldrData <= BL_LAST_FLASH_ARRAYID)
                             {
                         #endif  /* (!CY_PSOC4) */
 
-                        #if(0u == BL_DUAL_APP_BOOTLOADER)
 
-                            if(0u == clearedMetaData)
-                            {
-                                /* Metadata section must be filled with zeroes */
+                        /* btldrData  - holds flash array Id sent by host */
+                        /* dataOffset - holds flash row Id sent by host   */
+                        row = (uint16)(btldrData * BL_NUMBER_OF_ROWS_IN_ARRAY) + dataOffset;
 
-                                uint8 erase[BL_FROW_SIZE];
 
-                                #if(CY_PSOC3)
-                                    (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);
-                                #else
-                                    (void) memset(erase, 0, BL_FROW_SIZE);
-                                #endif  /* (CY_PSOC3) */
+                        /*******************************************************************************
+                        * Refuse to write to the row within range of the bootloader application
+                        *******************************************************************************/
 
-                                #if(CY_PSOC4)
-                                    (void) CySysFlashWriteRow(BL_MD_ROW, erase);
-                                #else
-                                    (void) CyWriteRowFull((uint8)  BL_MD_FLASH_ARRAY_NUM,
-                                                          (uint16) BL_MD_ROW,
-                                                                    erase,
-                                                                    BL_FROW_SIZE);
-                                #endif  /* (CY_PSOC4) */
+                        /* First empty flash row after bootloader application */
+                        firstRow = (uint16) (*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE);
+                        if ((*BL_SizeBytesAccess % CYDEV_FLS_ROW_SIZE) != 0u)
+                        {
+                            firstRow++;
+                        }
 
-                                /* Set up flag that metadata was cleared */
-                                clearedMetaData = 1u;
-                            }
+                        /* Check to see if the row to program will not corrupt the bootloader application */
+                        if(row < firstRow)
+                        {
+                            ackCode = BL_ERR_ROW;
+                            dataOffset = 0u;
+                            break;
+                        }
 
-                        #else
+
+                        #if(0u != BL_DUAL_APP_BOOTLOADER)
 
                             if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE)
                             {
-                                /* First active bootloadable application row */
-                                uint16 firstRow = (uint16) 1u +
-                                    (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW,
+                                uint16 lastRow;
+
+
+                                /*******************************************************************************
+                                * For the first bootloadable application gets the last flash row occupied by
+                                * the bootloader application image:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<--firstRow---|>
+                                *
+                                * For the second bootloadable application gets the last flash row occupied by
+                                * the first bootloadable application:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<-------------firstRow-----------------|>
+                                *
+                                * Incremented by 1 to get the first available row.
+                                *
+                                * Note: M1 and M2 stands for the metadata # 1 and metadata # 2, metadata
+                                * sections for the 1st and 2nd bootloadable applications.
+                                *******************************************************************************/
+                                firstRow = (uint16) 1u +
+                                    (uint16) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW,
                                                                           BL_activeApp);
 
-                                #if(CY_PSOC4)
-                                    uint16 row = dataOffset;
-                                #else
-                                    uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDEV_FLS_ROW_SIZE)) +
-                                                  dataOffset;
-                                #endif  /* (CY_PSOC4) */
+
+                                /*******************************************************************************
+                                * The number of flash rows available for the both bootloadable applications:
+                                *
+                                * First bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                *                |<-------------------lastRow -------------------->|
+                                *
+                                * Second bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                *                                         |<-------lastRow-------->|
+                                *******************************************************************************/
+                                lastRow = (uint16)(CY_FLASH_NUMBER_ROWS -
+                                                    BL_NUMBER_OF_METADATA_ROWS -
+                                                    firstRow);
 
 
                                 /*******************************************************************************
-                                * Last row is equal to the first row plus the number of rows available for each
-                                * app. To compute this, we first subtract the number of appliaction images from
-                                * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u).
+                                * The number of flash rows available for the active bootloadable application:
                                 *
-                                * Then subtract off the first row:
-                                * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow)
-                                * Then divide that number by the number of application that must fit within the
-                                * space, if we are app1 then that number is 2, if app2 then 1.  Our divisor is
-                                * then: (2u - BL_activeApp).
+                                * First bootloadable application is active: the number of flash rows available
+                                * for the both bootloadable applications should be divided by 2 - 2 bootloadable
+                                * applications should fit there.
                                 *
-                                * Adding this number to firstRow gives the address right beyond our valid range
-                                * so we subtract 1.
+                                * Second bootloadable application is active: the number of flash rows available
+                                * for the both bootloadable applications should be divided by 1 - 1 bootloadable
+                                * application should fit there.
                                 *******************************************************************************/
-                                uint16 lastRow = (firstRow - 1u) +
-                                                  ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 2u - firstRow) /
-                                                  ((uint16)2u - (uint16)BL_activeApp));
+                                lastRow = lastRow / (BL_NUMBER_OF_BTLDBLE_APPS -
+                                                BL_activeApp);
 
 
                                 /*******************************************************************************
-                                * Check to see if the row to program is within the range of the active
-                                * application, or if it maches the active application's metadata row.  If so,
-                                * refuse to program as it would corrupt the active app.
+                                * The last row equals to the first row plus the number of rows available for
+                                * the each bootloadable application. That gives the flash row number right
+                                * beyond the valid range, so we subtract 1.
+                                *
+                                * First bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<----------------lastRow ------------->|
+                                *
+                                * Second bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<-----------------------------lastRow-------------------------->|
+                                *******************************************************************************/
+                                lastRow = (firstRow + lastRow) - 1u;
+
+
+                                /*******************************************************************************
+                                * 1. Refuse to write row within the range of the active application
+                                *
+                                *  First bootloadable application is active:
+                                *   ---------------------------------------------------------------------------
+                                *  | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *   ---------------------------------------------------------------------------
+                                *  |<----------------lastRow ------------->|
+                                *  |<--firstRow---|>
+                                *                 |<-------protected------>|
+                                *
+                                *  Second bootloadable application is active:
+                                *   ---------------------------------------------------------------------------
+                                *  | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *   ---------------------------------------------------------------------------
+                                *  |<-------------firstRow-----------------|>
+                                *  |<-----------------------------lastRow-------------------------->|
+                                *                                          |<-------protected------>|
+                                *
+                                * 2. Refuse to write to the row that contains metadata of the active
+                                *    bootloadable application.
+                                *
                                 *******************************************************************************/
                                 if(((row >= firstRow) && (row <= lastRow)) ||
                                    ((btldrData == BL_MD_FLASH_ARRAY_NUM) &&
@@ -985,26 +1262,99 @@ static void BL_HostLink(uint8 timeOut)
                                 }
                             }
 
-                        #endif  /* (0u == BL_DUAL_APP_BOOTLOADER) */
+                        #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
 
-                        #if(!CY_PSOC4)
+
+
+                        /*******************************************************************************
+                        * Clear row that contains the metadata, when 'Fast bootloadable application
+                        * validation' option is enabled.
+                        *
+                        * If 'Fast bootloadable application validation' option is enabled, the
+                        * bootloader only computes the checksum the first time and assumes that it
+                        * remains valid in each future startup. The metadata row is cleared because the
+                        * bootloadable application might become corrupted during update, while
+                        * 'Bootloadable Application Verification Status' field will still report that
+                        * application is valid.
+                        *******************************************************************************/
+                        #if(0u != BL_FAST_APP_VALIDATION)
+
+                            if(0u == clearedMetaData)
+                            {
+                                /* Metadata section must be filled with zeros */
+
+                                uint8 erase[BL_FROW_SIZE];
+                                uint8 BL_notActiveApp;
+
+
+                                #if(CY_PSOC3)
+                                    (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);
+                                #else
+                                    (void) memset(erase, 0, BL_FROW_SIZE);
+                                #endif  /* (CY_PSOC3) */
+
+
+                                #if(0u != BL_DUAL_APP_BOOTLOADER)
+                                    if (BL_MD_BTLDB_ACTIVE_0 == BL_activeApp)
+                                    {
+                                        BL_notActiveApp = BL_MD_BTLDB_ACTIVE_1;
+                                    }
+                                    else
+                                    {
+                                        BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;
+                                    }
+                                #else
+                                    BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;
+                                #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+
+                                #if(CY_PSOC4)
+                                    (void) CySysFlashWriteRow(
+                                            BL_MD_ROW_NUM(BL_notActiveApp),
+                                            erase);
+                                #else
+                                    (void) CyWriteRowFull(
+                                            (uint8)  BL_MD_FLASH_ARRAY_NUM,
+                                            (uint16) BL_MD_ROW_NUM(BL_notActiveApp),
+                                            erase,
+                                            BL_FROW_SIZE);
+                                #endif  /* (CY_PSOC4) */
+
+                                /* PSoC 5: Do not care about flushing the cache as flash row has been erased. */
+
+                                /* Set up flag that metadata was cleared */
+                                clearedMetaData = 1u;
                             }
+
+                        #endif  /* (0u != BL_FAST_APP_VALIDATION) */
+
+
+                        #if(!CY_PSOC4)
+                            }   /* (btldrData <= BL_LAST_FLASH_ARRAYID) */
                         #endif  /* (!CY_PSOC4) */
 
-                        #if(CY_PSOC4)
 
-                            ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dataBuffer)) \
+                        #if(CY_PSOC4)
+                            ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) row, dataBuffer)) \
                                 ? BL_ERR_ROW \
                                 : CYRET_SUCCESS;
-
                         #else
-
                             ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \
                                 ? BL_ERR_ROW \
                                 : CYRET_SUCCESS;
-
                         #endif  /* (CY_PSOC4) */
 
+
+                        #if(CY_PSOC5)
+                            /***************************************************************************
+                            * When writing Flash, data in the instruction cache can become stale.
+                            * Therefore, the cache data does not correlate to the data just written to
+                            * Flash. A call to CyFlushCache() is required to invalidate the data in the
+                            * cache and force fresh information to be loaded from Flash.
+                            ***************************************************************************/
+                            CyFlushCache();
+                        #endif /* (CY_PSOC5) */
+
                     }
                     else
                     {
@@ -1028,7 +1378,7 @@ static void BL_HostLink(uint8 timeOut)
                     /* If something failed the host would send this command to reset the bootloader. */
                     dataOffset = 0u;
 
-                    /* Don't ack the packet, just get ready to accept the next one */
+                    /* Don't acknowledge the packet, just get ready to accept the next one */
                     continue;
                 }
                 break;
@@ -1037,7 +1387,7 @@ static void BL_HostLink(uint8 timeOut)
 
 
             /***************************************************************************
-            *   Set active application
+            *   Set an active application
             ***************************************************************************/
             #if(0u != BL_DUAL_APP_BOOTLOADER)
 
@@ -1088,7 +1438,7 @@ static void BL_HostLink(uint8 timeOut)
                             #else
                                 (void) memcpy(&dataBuffer[dataOffset],
                                               &packetBuffer[BL_DATA_ADDR],
-                                              pktSize);
+                                              (uint32) pktSize);
                             #endif  /* (CY_PSOC3) */
 
                             dataOffset += pktSize;
@@ -1134,7 +1484,7 @@ static void BL_HostLink(uint8 timeOut)
                     #else
                         (void) memcpy(&packetBuffer[BL_DATA_ADDR],
                                       &BtldrVersion,
-                                      rspSize);
+                                      (uint32) rspSize);
                     #endif  /* (CY_PSOC3) */
 
                     ackCode = CYRET_SUCCESS;
@@ -1145,6 +1495,8 @@ static void BL_HostLink(uint8 timeOut)
             /***************************************************************************
             *   Verify row
             ***************************************************************************/
+            #if (0u != BL_CMD_VERIFY_ROW_AVAIL)
+
             case BL_COMMAND_VERIFY:
 
                 if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u))
@@ -1165,7 +1517,7 @@ static void BL_HostLink(uint8 timeOut)
                             /* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */
                             rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE;
 
-                            checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE);
+                            checksum = BL_Calc8BitSum(CY_EEPROM_BASE, rowAddr, CYDEV_EEPROM_ROW_SIZE);
                         }
                         else
                         {
@@ -1173,7 +1525,7 @@ static void BL_HostLink(uint8 timeOut)
                             rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)
                                        + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);
 
-                            checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);
+                            checksum = BL_Calc8BitSum(CY_FLASH_BASE, rowAddr, CYDEV_FLS_ROW_SIZE);
                         }
 
                     #else
@@ -1181,7 +1533,9 @@ static void BL_HostLink(uint8 timeOut)
                         uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)
                                             + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);
 
-                        uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);
+                        uint8 CYDATA checksum = BL_Calc8BitSum(CY_FLASH_BASE,
+                                                                             rowAddr,
+                                                                             CYDEV_FLS_ROW_SIZE);
 
                     #endif  /* (!CY_PSOC4) */
 
@@ -1206,15 +1560,19 @@ static void BL_HostLink(uint8 timeOut)
 
 
                     /*******************************************************************************
-                    * App Verified & App Active are information that is updated in flash at runtime
-                    * remove these items from the checksum to allow the host to verify everything is
+                    * App Verified & App Active are information that is updated in Flash at runtime.
+                    * Remove these items from the checksum to allow the host to verify everything is
                     * correct.
                      ******************************************************************************/
                     if((BL_MD_FLASH_ARRAY_NUM == btldrData) &&
                        (BL_CONTAIN_METADATA(rowNum)))
                     {
-                        checksum -= BL_MD_BTLDB_ACTIVE_VALUE  (BL_GET_APP_ID(rowNum));
-                        checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum));
+
+                        checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_ACTIVE,
+                                                                 BL_GET_APP_ID(rowNum));
+
+                        checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_STATUS,
+                                                                 BL_GET_APP_ID(rowNum));
                     }
 
                     packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum);
@@ -1223,6 +1581,8 @@ static void BL_HostLink(uint8 timeOut)
                 }
                 break;
 
+            #endif /* (0u != BL_CMD_VERIFY_ROW_AVAIL) */
+
 
             /***************************************************************************
             *   Exit bootloader
@@ -1231,7 +1591,7 @@ static void BL_HostLink(uint8 timeOut)
 
                 if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp))
                 {
-                    BL_SET_RUN_TYPE(BL_START_APP);
+                    BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);
                 }
 
                 CySoftwareReset();
@@ -1249,7 +1609,7 @@ static void BL_HostLink(uint8 timeOut)
             }
         }
 
-        /* ?CK the packet and function. */
+        /* Reply with acknowledge or not acknowledge packet */
         (void) BL_WritePacket(ackCode, packetBuffer, rspSize);
 
     } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState));
@@ -1261,7 +1621,7 @@ static void BL_HostLink(uint8 timeOut)
 ********************************************************************************
 *
 * Summary:
-*  Creates a bootloader responce packet and transmits it back to the bootloader
+*  Creates a bootloader response packet and transmits it back to the bootloader
 *  host application over the already established communications protocol.
 *
 * Parameters:
@@ -1273,8 +1633,7 @@ static void BL_HostLink(uint8 timeOut)
 *      The number of bytes contained within the buffer to pass back
 *
 * Return:
-*   CYRET_SUCCESS if successful.
-*   CYRET_UNKNOWN if there was an error tranmitting the packet.
+*   CYRET_SUCCESS if successful. Any other non-zero value if failure occurred.
 *
 *******************************************************************************/
 static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \
@@ -1282,20 +1641,20 @@ static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMAL
 {
     uint16 CYDATA checksum;
 
-    /* Start of the packet. */
+    /* Start of packet. */
     buffer[BL_SOP_ADDR]      = BL_SOP;
     buffer[BL_CMD_ADDR]      = status;
     buffer[BL_SIZE_ADDR]     = LO8(size);
     buffer[BL_SIZE_ADDR + 1u] = HI8(size);
 
-    /* Compute the checksum. */
+    /* Compute checksum. */
     checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR);
 
     buffer[BL_CHK_ADDR(size)]     = LO8(checksum);
     buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum);
     buffer[BL_EOP_ADDR(size)]     = BL_EOP;
 
-    /* Start the packet transmit. */
+    /* Start packet transmit. */
     return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u));
 }
 
@@ -1305,11 +1664,11 @@ static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMAL
 ********************************************************************************
 *
 * Summary:
-*  Writes byte a flash memory location
+*  Writes a byte to the specified Flash memory location.
 *
 * Parameters:
 *  address:
-*      Address in Flash memory where data will be written
+*      The address in Flash memory where data will be written
 *
 *  runType:
 *      Byte to be written
@@ -1327,7 +1686,12 @@ void BL_SetFlashByte(uint32 address, uint8 runType)
         uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
     #endif  /* !(CY_PSOC4) */
 
-    uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
     uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
     uint16 idx;
 
@@ -1343,6 +1707,16 @@ void BL_SetFlashByte(uint32 address, uint8 runType)
     #else
         (void) CyWriteRowData(arrayId, rowNum, rowData);
     #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing Flash, data in the instruction cache can become stale.
+        * Therefore, the cache data does not correlate to the data just written to
+        * Flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from Flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
 }
 
 
@@ -1351,69 +1725,90 @@ void BL_SetFlashByte(uint32 address, uint8 runType)
 ********************************************************************************
 *
 * Summary:
-*  Returns value of the multi-byte field.
+*  Returns the value of the specified field of the metadata section.
 *
 * Parameters:
-*  fieldName:
+*  field:
 *   The field to get data from:
-*     BL_GET_METADATA_BTLDB_ADDR
-*     BL_GET_METADATA_BTLDR_LAST_ROW
-*     BL_GET_METADATA_BTLDB_LENGTH
-*     BL_GET_METADATA_BTLDR_APP_VERSION
-*     BL_GET_METADATA_BTLDB_APP_VERSION
-*     BL_GET_METADATA_BTLDB_APP_ID
-*     BL_GET_METADATA_BTLDB_APP_CUST_ID
+*   BL_GET_BTLDB_CHECKSUM    - Bootloadable Application Checksum
+*   BL_GET_BTLDB_ADDR        - Bootloadable Application Start
+*                                            Routine Address
+*   BL_GET_BTLDR_LAST_ROW    - Bootloader Last Flash Row
+*   BL_GET_BTLDB_LENGTH      - Bootloadable Application Length
+*   BL_GET_BTLDB_ACTIVE      - Active Bootloadable Application
+*   BL_GET_BTLDB_STATUS      - Bootloadable Application
+*                                            Verification Status
+*   BL_GET_BTLDR_APP_VERSION - Bootloader Application Version
+*   BL_GET_BTLDB_APP_VERSION - Bootloadable Application Version
+*   BL_GET_BTLDB_APP_ID      - Bootloadable Application ID
+*   BL_GET_BTLDB_APP_CUST_ID - Bootloadable Application Custom ID
 *
 *  appId:
-*   Number of the bootlodable application.
+*   Number of the bootlodable application. Should be 0 for the normal
+*   bootloader and 0 or 1 for the Multi-Application bootloader.
 *
 * Return:
-*  None
+*  The value of the specified field of the specified application.
 *
 *******************************************************************************/
-static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)
+uint32 BL_GetMetadata(uint8 field, uint8 appId)
 {
     uint32 fieldPtr;
     uint8  fieldSize = 2u;
-    uint32 result;
+    uint32 result = 0u;
 
-    switch (fieldName)
+    switch (field)
     {
-    case BL_GET_METADATA_BTLDB_APP_CUST_ID:
-        fieldPtr  = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);
-        fieldSize = 4u;
-        break;
-
-    case BL_GET_METADATA_BTLDR_APP_VERSION:
-        fieldPtr  = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);
+    case BL_GET_BTLDB_CHECKSUM:
+        fieldPtr  = BL_MD_BTLDB_CHECKSUM_OFFSET(appId);
+        fieldSize = 1u;
         break;
 
-    case BL_GET_METADATA_BTLDB_ADDR:
+    case BL_GET_BTLDB_ADDR:
         fieldPtr  = BL_MD_BTLDB_ADDR_OFFSET(appId);
     #if(!CY_PSOC3)
         fieldSize = 4u;
     #endif  /* (!CY_PSOC3) */
         break;
 
-    case BL_GET_METADATA_BTLDR_LAST_ROW:
+    case BL_GET_BTLDR_LAST_ROW:
         fieldPtr  = BL_MD_BTLDR_LAST_ROW_OFFSET(appId);
         break;
 
-    case BL_GET_METADATA_BTLDB_LENGTH:
+    case BL_GET_BTLDB_LENGTH:
         fieldPtr  = BL_MD_BTLDB_LENGTH_OFFSET(appId);
     #if(!CY_PSOC3)
         fieldSize = 4u;
     #endif  /* (!CY_PSOC3) */
         break;
 
-    case BL_GET_METADATA_BTLDB_APP_VERSION:
+    case BL_GET_BTLDB_ACTIVE:
+        fieldPtr  = BL_MD_BTLDB_ACTIVE_OFFSET(appId);
+        fieldSize = 1u;
+        break;
+
+    case BL_GET_BTLDB_STATUS:
+        fieldPtr  = BL_MD_BTLDB_VERIFIED_OFFSET(appId);
+        fieldSize = 1u;
+        break;
+
+    case BL_GET_BTLDB_APP_VERSION:
         fieldPtr  = BL_MD_BTLDB_APP_VERSION_OFFSET(appId);
         break;
 
-    case BL_GET_METADATA_BTLDB_APP_ID:
+    case BL_GET_BTLDR_APP_VERSION:
+        fieldPtr  = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);
+        break;
+
+    case BL_GET_BTLDB_APP_ID:
         fieldPtr  = BL_MD_BTLDB_APP_ID_OFFSET(appId);
         break;
 
+    case BL_GET_BTLDB_APP_CUST_ID:
+        fieldPtr  = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);
+        fieldSize = 4u;
+        break;
+
     default:
         /* Should never be here */
         CYASSERT(0u != 0u);
@@ -1422,38 +1817,44 @@ static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)
     }
 
 
-    /* Read all fields as big-endian */
-    if (2u == fieldSize)
-    {
-        result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr      ) <<  8u;
-    }
-    else
+    if (1u == fieldSize)
     {
-        result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) <<  8u;
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     )) << 24u;
+        result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)fieldPtr);
     }
 
-    /* Following fields should be little-endian */
-#if(!CY_PSOC3)
-    switch (fieldName)
-    {
-    case BL_GET_METADATA_BTLDR_LAST_ROW:
-        result = CYSWAP_ENDIAN16(result);
-        break;
+    #if(CY_PSOC3)   /* Big-endian */
 
-    case BL_GET_METADATA_BTLDB_ADDR:
-    case BL_GET_METADATA_BTLDB_LENGTH:
-        result = CYSWAP_ENDIAN32(result);
-        break;
+        if (2u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     )) <<  8u;
+        }
 
-    default:
-        break;
-    }
+        if (4u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) <<  8u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     )) << 24u;
+        }
 
-#endif  /* (!CY_PSOC3) */
+    #else   /* PSoC 4 and PSoC 5: Little-endian */
+
+        if (2u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr     ));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr + 1u)) <<  8u;
+        }
+
+        if (4u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     ));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) <<  8u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 16u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)) << 24u;
+        }
+
+    #endif /* (CY_PSOC3) */
 
     return (result);
 }
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h
index e459c555..82341df6 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: BL.h
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloader. The API includes functions for starting
@@ -8,7 +8,7 @@
 *   application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -18,14 +18,7 @@
 #define CY_BOOTLOADER_BL_H
 
 #include "cytypes.h"
-
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component Bootloader_v1_20 requires cy_boot v3.0 or later
-#endif /* (CY_ PSOC5X) */
-
+#include "CyFlash.h"
 
 #define BL_DUAL_APP_BOOTLOADER        (0u)
 #define BL_BOOTLOADER_APP_VERSION     (0u)
@@ -62,7 +55,6 @@
 #define BL_SCHEDULE_BTLDR             (0x40u)
 #define BL_SCHEDULE_MASK              (0xC0u)
 
-
 #if defined(__ARMCC_VERSION) || defined (__GNUC__)
     __attribute__((section (".bootloader")))
 #elif defined (__ICCARM__)
@@ -114,9 +106,9 @@ extern const uint32 CYCODE *BL_SizeBytesAccess;
 
 /*******************************************************************************
 * Get the reason of the device reset
-*  Return cyBtldrRunType in case if software reset was reset reason and
+*  Return cyBtldrRunType in the case if software reset was the reset reason and
 *  set cyBtldrRunType to zero (bootloader application is scheduled - that is
-*  initial clean state) and return zero.
+*  the initial clean state) and return zero.
 *******************************************************************************/
 #if(CY_PSOC4)
     #define BL_GET_RUN_TYPE           (cyBtldrRunType)
@@ -135,8 +127,10 @@ extern const uint32 CYCODE *BL_SizeBytesAccess;
 #endif  /* (CY_PSOC4) */
 
 
-/* Returns the number of Flash arrays availalbe in the device */
-#define BL_NUM_OF_FLASH_ARRAYS    (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
+/* Returns the number of Flash arrays available in the device */
+#ifndef CY_FLASH_NUMBER_ARRAYS
+    #define CY_FLASH_NUMBER_ARRAYS                  (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
+#endif /* CY_FLASH_NUMBER_ARRAYS */
 
 
 /*******************************************************************************
@@ -145,13 +139,20 @@ extern const uint32 CYCODE *BL_SizeBytesAccess;
 void BL_SetFlashByte(uint32 address, uint8 runType);
 void CyBtldr_CheckLaunch(void)  CYSMALL ;
 void BL_Start(void) CYSMALL ;
+cystatus BL_ValidateBootloadable(uint8 appId) \
+            CYSMALL ;
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) CYSMALL \
+                                    ;
+uint32   BL_GetMetadata(uint8 field, uint8 appId) \
+                                    ;
+void BL_Exit(uint8 appId) CYSMALL ;
 
 #if(CY_PSOC3)
     /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file.  */
-    extern void     BL_LaunchBootloadable(uint32 appAddr);
+    void     BL_LaunchBootloadable(uint32 appAddr);
 #endif  /* (CY_PSOC3) */
 
-/* If using custom interface as the IO Component, user must provide these functions */
+/* When using a custom interface as the IO Component, the user must provide these functions */
 #if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)
 
     extern void CyBtldrCommStart(void);
@@ -163,30 +164,55 @@ void BL_Start(void) CYSMALL ;
 #endif  /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */
 
 
+/*******************************************************************************
+* BL_GetMetadata()
+*******************************************************************************/
+#define BL_GET_BTLDB_CHECKSUM         (1u)
+#define BL_GET_BTLDB_ADDR             (2u)
+#define BL_GET_BTLDR_LAST_ROW         (3u)
+#define BL_GET_BTLDB_LENGTH           (4u)
+#define BL_GET_BTLDB_ACTIVE           (5u)
+#define BL_GET_BTLDB_STATUS           (6u)
+#define BL_GET_BTLDR_APP_VERSION      (7u)
+#define BL_GET_BTLDB_APP_VERSION      (8u)
+#define BL_GET_BTLDB_APP_ID           (9u)
+#define BL_GET_BTLDB_APP_CUST_ID      (10u)
+
+#define BL_GET_METADATA_RESPONSE_SIZE (56u)
+
+/*******************************************************************************
+* BL_Exit()
+*******************************************************************************/
+#define BL_EXIT_TO_BTLDR              (2u)
+#define BL_EXIT_TO_BTLDB              (0u)
+#if(0u != BL_DUAL_APP_BOOTLOADER)
+    #define BL_EXIT_TO_BTLDB_1        (0u)
+    #define BL_EXIT_TO_BTLDB_2        (1u)
+#endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+
 /*******************************************************************************
 * Kept for backward compatibility.
 *******************************************************************************/
 #if(0u != BL_DUAL_APP_BOOTLOADER)
     #define BL_ValidateApp(x)                 BL_ValidateBootloadable((x))
-    #define BL_ValidateApplication            \
+    #define BL_ValidateApplication()            \
                             BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)
 #else
-    #define BL_ValidateApplication            \
+    #define BL_ValidateApplication()            \
                             BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)
     #define BL_ValidateApp(x)                 BL_ValidateBootloadable((x))
 #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
+#define BL_Calc8BitFlashSum(start, size)      BL_Calc8BitSum(CY_FLASH_BASE, (start), (size))
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.10
+* The following code is DEPRECATED and must not be used.
 *******************************************************************************/
 #define BL_BOOTLOADABLE_APP_VALID     (BL_BOOTLOADER_APP_VALIDATION)
 #define CyBtldr_Start                               BL_Start
 
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.20
-*******************************************************************************/
+#define BL_NUM_OF_FLASH_ARRAYS            (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
 #define BL_META_BASE(x)                   (CYDEV_FLASH_BASE + \
                                                             (CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \
                                                             BL_META_DATA_SIZE))
@@ -215,8 +241,14 @@ void BL_Start(void) CYSMALL ;
                                                             BL_META_APP_CHECKSUM_OFFSET)
 #if(0u == BL_DUAL_APP_BOOTLOADER)
     #define BL_MD_BASE                    BL_META_BASE(0u)
-    #define BL_MD_ROW                     ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
-                                                           - 1u)
+
+    #if(!CY_PSOC4)
+        #define BL_MD_ROW                 ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
+                                                        - 1u)
+    #else
+        #define BL_MD_ROW                 (CY_FLASH_NUMBER_ROWS - 1u)
+    #endif /* (CY_PSOC4) */
+
     #define BL_MD_CHECKSUM_ADDR           BL_META_CHECKSUM_ADDR(0u)
     #define BL_MD_LAST_BLDR_ROW_ADDR      BL_META_LAST_BLDR_ROW_ADDR(0u)
     #define BL_MD_APP_BYTE_LEN            BL_META_APP_BYTE_LEN(0u)
@@ -224,8 +256,13 @@ void BL_Start(void) CYSMALL ;
     #define BL_MD_APP_ENTRY_POINT_ADDR    BL_META_APP_ENTRY_POINT_ADDR(0u)
     #define BL_MD_APP_RUN_ADDR            BL_META_APP_RUN_ADDR(0u)
 #else
-    #define BL_MD_ROW(x)                  ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
-                                                            - 1u - ( uint32 )(x))
+    #if(!CY_PSOC4)
+        #define BL_MD_ROW(x)              ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
+                                                        - 1u - ( uint32 )(x))
+    #else
+        #define BL_MD_ROW(x)              (CY_FLASH_NUMBER_ROWS - 1u - ( uint32 )(x))
+    #endif /* (CY_PSOC4) */
+
     #define BL_MD_CHECKSUM_ADDR           BL_META_CHECKSUM_ADDR(appId)
     #define BL_MD_LAST_BLDR_ROW_ADDR      BL_META_LAST_BLDR_ROW_ADDR(appId)
     #define BL_MD_APP_BYTE_LEN            BL_META_APP_BYTE_LEN(appId)
@@ -302,7 +339,7 @@ void BL_Start(void) CYSMALL ;
 #define BL_START_APP                  (BL_SCHEDULE_BTLDB)
 #define BL_START_BTLDR                (BL_SCHEDULE_BTLDR)
 
-/* Some PSoC Creator versions used to generate only one name types */
+/* Some PSoC Creator versions are used to generate only one name types */
 #if !defined (CYDEV_FLASH_BASE)
     #define CYDEV_FLASH_BASE                                (CYDEV_FLS_BASE)
 #endif /* !defined (CYDEV_FLASH_BASE) */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h
index 9d12d71a..e7c52ed0 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: BL_PVT.h
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloader.
 *
 ********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -28,7 +28,7 @@ typedef struct
 
 
 #define BL_VERSION        {\
-                                            (uint8)20, \
+                                            (uint8)30, \
                                             (uint8)1, \
                                             (uint8)0x01u \
                                         }
@@ -38,7 +38,7 @@ typedef struct
 #define BL_EOP            (0x17u)    /* End of Packet */
 
 
-/* Bootloader command responces */
+/* Bootloader command responses */
 #define BL_ERR_KEY       (0x01u)  /* The provided key does not match the expected value          */
 #define BL_ERR_VERIFY    (0x02u)  /* The verification of flash failed                            */
 #define BL_ERR_LENGTH    (0x03u)  /* The amount of data available is outside the expected range  */
@@ -88,7 +88,7 @@ typedef struct
 BL_ValidateBootloadable()
 *******************************************************************************/
 #define BL_FIRST_APP_BYTE(appId)      ((uint32)CYDEV_FLS_ROW_SIZE * \
-        ((uint32) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, appId) + \
+        ((uint32) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW, appId) + \
          (uint32) 1u))
 
 #define BL_MD_BTLDB_IS_VERIFIED       (0x01u)
@@ -101,7 +101,7 @@ BL_ValidateBootloadable()
 #define BL_WAIT_FOR_COMMAND_FOREVER   (0x00u)
 
 
- /* Maximum number of bytes accepted in a packet plus some */
+ /* The maximum number of bytes accepted in a packet plus some */
 #define BL_SIZEOF_COMMAND_BUFFER      (300u)
 
 
@@ -136,18 +136,6 @@ BL_ValidateBootloadable()
 #endif /* (0u != BL_PACKET_CHECKSUM_CRC) */
 
 
-/*******************************************************************************
-* BL_GetMetadata()
-*******************************************************************************/
-#define BL_GET_METADATA_BTLDB_ADDR             (1u)
-#define BL_GET_METADATA_BTLDR_LAST_ROW         (2u)
-#define BL_GET_METADATA_BTLDB_LENGTH           (3u)
-#define BL_GET_METADATA_BTLDR_APP_VERSION      (4u)
-#define BL_GET_METADATA_BTLDB_APP_VERSION      (5u)
-#define BL_GET_METADATA_BTLDB_APP_ID           (6u)
-#define BL_GET_METADATA_BTLDB_APP_CUST_ID      (7u)
-
-
 /*******************************************************************************
 * CyBtldr_CheckLaunch()
 *******************************************************************************/
@@ -161,11 +149,11 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Metadata base address. In case of bootloader application, the metadata is
-* placed at row N-1; in case of multi-application bootloader, the bootloadable
-* application number 1 will use row N-1, and application number 2 will use row
-* N-2 to store its metadata, where N is the total number of rows for the
-* selected device.
+* The Metadata base address. In the case of the bootloader application, the
+* metadata is placed at row N-1; in the case of the multi-application
+* bootloader, the bootloadable application number 1 will use row N-1, and
+* application number 2 will use row N-2 to store its metadata, where N is the
+* total number of the rows for the selected device.
 *******************************************************************************/
 #define BL_MD_BASE_ADDR(appId)        (CYDEV_FLASH_BASE + \
                                                         (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \
@@ -173,8 +161,13 @@ BL_ValidateBootloadable()
 
 #define BL_MD_FLASH_ARRAY_NUM         (BL_NUM_OF_FLASH_ARRAYS - 1u)
 
-#define BL_MD_ROW_NUM(appId)          ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \
-                                                        1u - (uint32)(appId))
+#if(!CY_PSOC4)
+    #define BL_MD_ROW_NUM(appId)      ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \
+                                                    1u - (uint32)(appId))
+#else
+    #define BL_MD_ROW_NUM(appId)      (CY_FLASH_NUMBER_ROWS - 1u - (uint32)(appId))
+#endif /* (!CY_PSOC4) */
+
 
 #define     BL_MD_BTLDB_CHECKSUM_OFFSET(appId)       (BL_MD_BASE_ADDR(appId) + 0u)
 #if(CY_PSOC3)
@@ -194,50 +187,6 @@ BL_ValidateBootloadable()
 #define     BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId)    (BL_MD_BASE_ADDR(appId) + 24u)
 
 
-/*******************************************************************************
-* Macro for 1 byte long metadata fields
-*******************************************************************************/
-#define BL_MD_BTLDB_CHECKSUM_PTR  (appId)    \
-            ((reg8 *)(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))
-#define BL_MD_BTLDB_CHECKSUM_VALUE(appId)    \
-            (CY_GET_XTND_REG8(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))
-
-#define BL_MD_BTLDB_ACTIVE_PTR(appId)        \
-            ((reg8 *)(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))
-#define BL_MD_BTLDB_ACTIVE_VALUE(appId)      \
-            (CY_GET_XTND_REG8(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))
-
-#define BL_MD_BTLDB_VERIFIED_PTR(appId)      \
-            ((reg8 *)(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))
-#define BL_MD_BTLDB_VERIFIED_VALUE(appId)    \
-            (CY_GET_XTND_REG8(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))
-
-
-/*******************************************************************************
-* Macro for multiple bytes long metadata fields pointers 
-*******************************************************************************/
-#define BL_MD_BTLDB_ADDR_PTR  (appId)        \
-            ((reg8 *)(BL_MD_BTLDB_ADDR_OFFSET(appId)))
-
-#define BL_MD_BTLDR_LAST_ROW_PTR  (appId)    \
-            ((reg8 *)(BL_MD_BTLDR_LAST_ROW_OFFSET(appId)))
-
-#define BL_MD_BTLDB_LENGTH_PTR(appId)        \
-            ((reg8 *)(BL_MD_BTLDB_LENGTH_OFFSET(appId)))
-
-#define BL_MD_BTLDR_APP_VERSION_PTR(appId)    \
-            ((reg8 *)(BL_MD_BTLDR_APP_VERSION_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_ID_PTR(appId)         \
-            ((reg8 *)(BL_MD_BTLDB_APP_ID_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_VERSION_PTR(appId)    \
-            ((reg8 *)(BL_MD_BTLDB_APP_VERSION_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_CUST_ID_PTR(appId)    \
-            ((reg8 *)(BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId)))
-
-
 /*******************************************************************************
 * Get data byte from FLASH
 *******************************************************************************/
@@ -262,7 +211,8 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Offset of the Bootloader application in flash
+* Number of addresses remapped from Flash to RAM, when interrupt vectors are
+* configured to be stored in RAM (default setting, configured by cy_boot).
 *******************************************************************************/
 #if(CY_PSOC4)
     #define BL_MD_BTLDR_ADDR_PTR        (0xC0u)     /* Exclude the vector */
@@ -272,7 +222,7 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Maximum number of Bootloadable applications
+* The maximum number of Bootloadable applications
 *******************************************************************************/
 #if(1u == BL_DUAL_APP_BOOTLOADER)
     #define BL_MAX_NUM_OF_BTLDB       (0x02u)
@@ -282,7 +232,7 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Returns TRUE if row specified as parameter contains metadata section
+* Returns TRUE if the row specified as a parameter contains a metadata section
 *******************************************************************************/
 #if(0u != BL_DUAL_APP_BOOTLOADER)
     #define BL_CONTAIN_METADATA(row)  \
@@ -295,10 +245,10 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Metadata section is located at the last flash row for the Boootloader, for the
-* Multi-Application Bootloader, metadata section of the Bootloadable application
-* # 0 is located at the last flash row, and metadata section of the Bootloadable
-* application # 1 is located in the flash row before last.
+* The Metadata section is located in the last flash row for the Boootloader, for
+* the Multi-Application Bootloader, the metadata section of the Bootloadable
+* application # 0 is located in the last flash row, and the metadata section of
+* the Bootloadable application # 1 is located in the flash row before last.
 *******************************************************************************/
 #if(0u != BL_DUAL_APP_BOOTLOADER)
     #define BL_GET_APP_ID(row)     \
@@ -309,6 +259,29 @@ BL_ValidateBootloadable()
     #define BL_GET_APP_ID(row)     (BL_MD_BTLDB_ACTIVE_0)
 #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
 
+
+/*******************************************************************************
+* Defines the number of flash rows reserved for the metadata section
+*******************************************************************************/
+#if(0u == BL_DUAL_APP_BOOTLOADER)
+    #define BL_NUMBER_OF_METADATA_ROWS            (1u)
+#else
+    #define BL_NUMBER_OF_METADATA_ROWS            (2u)
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+
+
+/*******************************************************************************
+* Defines the number of possible bootloadable applications
+*******************************************************************************/
+#if(0u == BL_DUAL_APP_BOOTLOADER)
+    #define BL_NUMBER_OF_BTLDBLE_APPS            (1u)
+#else
+    #define BL_NUMBER_OF_BTLDBLE_APPS            (2u)
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+
+#define BL_NUMBER_OF_ROWS_IN_ARRAY                ((uint16)(CY_FLASH_SIZEOF_ARRAY/CY_FLASH_SIZEOF_ROW))
+#define BL_FIRST_ROW_IN_ARRAY                     (0u)
+
 #endif /* CY_BOOTLOADER_BL_PVT_H */
 
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
index f5416ec8..c998f034 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
@@ -40,7 +40,10 @@ define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   {
 define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
 define block HSTACK      {block HEAP, last block CSTACK};
 
+if (CY_APPL_LOADABLE)
+{
 define block LOADER     { readonly section .cybootloader };
+}
 define block APPL       with fixed order {readonly section .romvectors, readonly};
 
 /* The address of Flash row next after Bootloader image */
@@ -83,7 +86,11 @@ do not initialize  { section .noinit };
 do not initialize  { readwrite section .ramvectors };
 
 /******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
 ".cybootloader"    : place at start of ROM_region {block LOADER};
+}
+
 "APPL"             : place at start of APPL_region {block APPL};
 
 "RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
@@ -101,7 +108,10 @@ keep {  section .cybootloader,
         section .cymeta };
 
 ".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
 ".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
 ".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
 ".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
 ".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
index 7c39f669..f26af91a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
@@ -4,7 +4,7 @@
 
 ;********************************************************************************
 ;* File Name: Cm3RealView.scat
-;* Version 4.0
+;* Version 4.20
 ;*
 ;*  Description:
 ;*  This Linker Descriptor file describes the memory layout of the PSoC5
@@ -14,7 +14,7 @@
 ;*
 ;*  Note:
 ;*
-;*  romvectors: Cypress default Interrupt sevice routine vector table.
+;*  romvectors: Cypress default Interrupt service routine vector table.
 ;*
 ;*      This is the ISR vector table at bootup. Used only for the reset vector.
 ;*
@@ -25,7 +25,7 @@
 ;*
 ;*
 ;********************************************************************************
-;* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+;* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ;* You may use this file only in accordance with the license, terms, conditions,
 ;* disclaimers, and limitations in the end user license agreement accompanying
 ;* the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c
index f4d6607e..dd1cc0bc 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: Cm3Start.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  Startup code for the ARM CM3.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -52,6 +52,12 @@ CY_ISR(IntDefaultHandler);
     extern void __iar_data_init3 (void);
 #endif  /* (__ARMCC_VERSION) */
 
+#if defined(__GNUC__)
+    #include <errno.h>
+    extern int  errno;
+    extern int  end;
+#endif  /* defined(__GNUC__) */
+
 /* Global variables */
 #if !defined (__ICCARM__)
     CY_NOINIT static uint32 cySysNoInitDataValid;
@@ -76,7 +82,7 @@ cyisraddress CyRamVectors[CY_NUM_VECTORS];
 ********************************************************************************
 *
 * Summary:
-*  This function is called for all interrupts, other than reset, that get
+*  This function is called for all interrupts, other than a reset that gets
 *  called before the system is setup.
 *
 * Parameters:
@@ -95,7 +101,7 @@ CY_ISR(IntDefaultHandler)
     while(1)
     {
         /***********************************************************************
-        * We should never get here. If we do, a serious problem occured, so go
+        * We must not get here. If we do, a serious problem occurs, so go
         * into an infinite loop.
         ***********************************************************************/
     }
@@ -104,7 +110,7 @@ CY_ISR(IntDefaultHandler)
 
 #if defined(__ARMCC_VERSION)
 
-/* Local function for the device reset. */
+/* Local function for device reset. */
 extern void Reset(void);
 
 /* Application entry point. */
@@ -161,7 +167,7 @@ void Reset(void)
 ********************************************************************************
 *
 * Summary:
-*  This function is called imediatly before the users main
+*  This function is called immediately before the users main
 *
 * Parameters:
 *  None
@@ -179,7 +185,7 @@ void $Sub$$main(void)
 
     while (1)
     {
-        /* If main returns it is undefined what we should do. */
+        /* If main returns, it is undefined what we should do. */
     }
 }
 
@@ -193,7 +199,7 @@ extern void __cy_stack(void);
 /* Application entry point. */
 extern int main(void);
 
-/* The static objects constructors initializer */
+/* Static objects constructors initializer */
 extern void __libc_init_array(void);
 
 typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
@@ -211,6 +217,84 @@ extern const char __cy_region_num __attribute__((weak));
 #define __cy_region_num ((size_t)&__cy_region_num)
 
 
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+*  Exit a program without cleaning up files. If your system doesn't provide
+*  this, it is best to avoid linking with subroutines that require it (exit,
+*  system).
+*
+* Parameters:
+*  status: Status caused program exit.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+    /* Cause divide by 0 exception */
+    int x = status / (int) INT_MAX;
+    x = 4 / x;
+
+    while(1)
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+*  Increase program data space. As malloc and related functions depend on this,
+*  it is useful to have a working implementation. The following suffices for a
+*  standalone system; it exploits the symbol end automatically defined by the
+*  GNU linker.
+*
+* Parameters:
+*  nbytes: The number of bytes requested (if the parameter value is positive)
+*  from the heap or returned back to the heap (if the parameter value is
+*  negative).
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
+    void *      returnValue;
+
+    /* The statically held previous end of the heap, with its initialization. */
+    static void *heapPointer = (void *) &end;                 /* Previous end */
+
+    if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+    {
+        returnValue  = heapPointer;
+        heapPointer += nbytes;
+    }
+    else
+    {
+        errno = ENOMEM;
+        returnValue = (void *) -1;
+    }
+
+    return (returnValue);
+}
+
+
 /*******************************************************************************
 * Function Name: Reset
 ********************************************************************************
@@ -249,17 +333,6 @@ void Reset(void)
     Start_c();
 }
 
-__attribute__((weak))
-void _exit(int status)
-{
-    /* Cause a divide by 0 exception */
-    int x = status / INT_MAX;
-    x = 4 / x;
-
-    while(1)
-    {
-    }
-}
 
 /*******************************************************************************
 * Function Name: Start_c
@@ -267,7 +340,7 @@ void _exit(int status)
 *
 * Summary:
 *  This function handles initializing the .data and .bss sections in
-*  preperation for running standard C code.  Once initialization is complete
+*  preparation for running the standard C code.  Once initialization is complete
 *  it will call main(). This function will never return.
 *
 * Parameters:
@@ -284,7 +357,7 @@ void Start_c(void)
     const struct __cy_region *rptr = __cy_regions;
 
     /* Initialize memory */
-    for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+    for (regions = __cy_region_num; regions != 0u; regions--)
     {
         uint32 *src = (uint32 *)rptr->init;
         uint32 *dst = (uint32 *)rptr->data;
@@ -293,13 +366,18 @@ void Start_c(void)
 
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = *src++;
+            *dst = *src;
+            dst++;
+            src++;
         }
         limit = rptr->zero_size;
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = 0u;
+            *dst = 0u;
+            dst++;
         }
+
+        rptr++;
     }
 
     /* Invoke static objects constructors */
@@ -320,8 +398,8 @@ void Start_c(void)
 ********************************************************************************
 *
 * Summary:
-*  This function perform early initializations for the IAR Embedded
-*  Workbench IDE. It is executed in the context of reset interrupt handler
+*  This function performs early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of a reset interrupt handler
 *  before the data sections are initialized.
 *
 * Parameters:
@@ -383,14 +461,14 @@ int __low_level_init(void)
     const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
 #endif  /* defined (__ICCARM__) */
 {
-    INITIAL_STACK_POINTER,   /* The initial stack pointer  0 */
-    #if defined (__ICCARM__) /* The reset handler          1 */
+    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
+    #if defined (__ICCARM__) /* Reset handler          1 */
         __iar_program_start,
     #else
         (cyisraddress)&Reset,
     #endif  /* defined (__ICCARM__) */
-    &IntDefaultHandler,      /* The NMI handler            2 */
-    &IntDefaultHandler,      /* The hard fault handler     3 */
+    &IntDefaultHandler,      /* NMI handler            2 */
+    &IntDefaultHandler,      /* Hard fault handler     3 */
 };
 
 #if defined(__ARMCC_VERSION)
@@ -438,7 +516,7 @@ void initialize_psoc(void)
     /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
     CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
 
-    /* Point NVIC at the RAM vector table. */
+    /* Point NVIC at RAM vector table. */
     *CYINT_VECT_TABLE = CyRamVectors;
 
     /* Initialize the configuration registers. */
@@ -446,7 +524,7 @@ void initialize_psoc(void)
 
     #if(0u != DMA_CHANNELS_USED__MASK0)
 
-        /* Setup DMA - only necessary if the design contains a DMA component. */
+        /* Setup DMA - only necessary if design contains DMA component. */
         CyDmacConfigure();
 
     #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
index a8797f7e..e8c87a4a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: CyBootAsmGnu.s
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Assembly routines for GNU as.
 *
 ********************************************************************************
-* Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
index 166ba871..330202c8 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmIar.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for IAR Embedded Workbench IDE.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2013-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -30,7 +30,7 @@
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic. Therefore, to avoid corrupting processor state, it must be the policy 
+;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
 ;  that all interrupt routines restore the interrupt enable bits as they were 
 ;  found on entry.
 ;
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
index 6c40635e..8b1cc20a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmRv.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for RealView.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -110,7 +110,7 @@ byte_4 DCB 0x09
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
 ;  corrupting processor state, it must be the policy that all interrupt routines
 ;  restore the interrupt enable bits as they were found on entry.
 ;
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c
index f4983c39..2a1ef96a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the DMAC component. The API includes functions for the
@@ -18,10 +18,10 @@
 *  not being used.
 *
 *  This code uses the first byte of each TD to manage the free list of TD's.
-*  The user can over write this once the TD is allocated.
+*  The user can overwrite this once the TD is allocated.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,8 +37,8 @@
 * are initialized. To avoid zeroing, these variables should be initialized
 * properly during segments initialization as well.
 *******************************************************************************/
-static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements in the list */
-static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
 static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
 
 
@@ -48,7 +48,7 @@ static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map
 *
 * Summary:
 *  Creates a linked list of all the TDs to be allocated. This function is called
-*  by the startup code; you do not normally need to call it. You could call this
+*  by the startup code; you do not normally need to call it. You can call this
 *  function if all of the DMA channels are inactive.
 *
 * Parameters:
@@ -72,7 +72,7 @@ void CyDmacConfigure(void)
         CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
     }
 
-    /* Make the last one point to zero. */
+    /* Make last one point to zero. */
     CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
 }
 
@@ -102,8 +102,8 @@ void CyDmacConfigure(void)
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 uint8 CyDmacError(void) 
@@ -131,15 +131,15 @@ uint8 CyDmacError(void)
 *   Set to 1 when an access is attempted to an invalid address.
 *
 *  DMAC_BUS_TIMEOUT:
-*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Return:
 *  None
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 void CyDmacClearError(uint8 error) 
@@ -153,7 +153,7 @@ void CyDmacClearError(uint8 error)
 ********************************************************************************
 *
 * Summary:
-*  When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the
+*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
 *  address of the error is written to the error address register and can be read
 *  with this function.
 *
@@ -198,12 +198,12 @@ uint8 CyDmaChAlloc(void)
     /* Enter critical section! */
     interruptState = CyEnterCriticalSection();
 
-    /* Look for a free channel. */
+    /* Look for free channel. */
     for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
     {
         if(0uL == (CyDmaChannels & channel))
         {
-            /* Mark the channel as used. */
+            /* Mark channel as used. */
             CyDmaChannels |= channel;
             break;
         }
@@ -249,7 +249,7 @@ cystatus CyDmaChFree(uint8 chHandle)
         /* Enter critical section */
         interruptState = CyEnterCriticalSection();
 
-        /* Clear the bit mask that keeps track of ownership. */
+        /* Clear bit mask that keeps track of ownership. */
         CyDmaChannels &= ~(((uint32) 1u) << chHandle);
 
         /* Exit critical section */
@@ -277,10 +277,10 @@ cystatus CyDmaChFree(uint8 chHandle)
 *   Preserves the original TD state when the TD has completed. This parameter
 *   applies to all TDs in the channel.
 *
-*   0 - When a TD is completed, the DMAC leaves the TD configuration values in
+*   0 - When TD is completed, the DMAC leaves the TD configuration values in
 *   their current state, and does not restore them to their original state.
 *
-*   1 - When a TD is completed, the DMAC restores the original configuration
+*   1 - When TD is completed, the DMAC restores the original configuration
 *   values of the TD.
 *
 *  When preserveTds is set, the TD slot that equals the channel number becomes
@@ -309,14 +309,14 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds)
     {
         if (0u != preserveTds)
         {
-            /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
-            *  preserve the original TD chain
+            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve original TD chain
             */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
         }
         else
         {
-            /* Store the intermediate and final TD states on top of the original TD chain */
+            /* Store intermediate and final TD states on top of original TD chain */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
         }
 
@@ -365,7 +365,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
         /* Disable channel */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
 
-        /* Store the intermediate and final TD states on top of the original TD chain */
+        /* Store intermediate and final TD states on top of original TD chain */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
         status = CYRET_SUCCESS;
     }
@@ -379,7 +379,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
 ********************************************************************************
 *
 * Summary:
-*  Clears pending DMA data request.
+*  Clears pending the DMA data request.
 *
 * Parameters:
 *  uint8 chHandle:
@@ -518,7 +518,7 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
 *   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
 *
 *  uint8 startTd:
-*   The index of TD to set as the first TD associated with the channel. Zero is
+*   Set the TD index as the first TD associated with the channel. Zero is
 *   a valid TD index.
 *
 * Return:
@@ -759,13 +759,13 @@ uint8 CyDmaTdAllocate(void)
 
     if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
     {
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         element = CyDmaTdFreeIndex;
 
         /* Decrement the count. */
         CyDmaTdCurrentNumber--;
 
-        /* Update the next available pointer. */
+        /* Update next available pointer. */
         CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
     }
 
@@ -798,7 +798,7 @@ void CyDmaTdFree(uint8 tdHandle)
         /* Enter critical section! */
         uint8 interruptState = CyEnterCriticalSection();
 
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
 
         /* Set new Next Available. */
@@ -942,9 +942,9 @@ cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nex
 *  CYRET_BAD_PARAM if tdHandle is invalid.
 *
 * Side Effects:
-*  If a TD has a transfer count of N and is executed, the transfer count becomes
+*  If TD has a transfer count of N and is executed, the transfer count becomes
 *  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-*  request for indefinite transfer. Be careful when requesting a TD with a
+*  request for indefinite transfer. Be careful when requesting TD with a
 *  transfer count of zero.
 *
 *******************************************************************************/
@@ -955,25 +955,25 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 *
 
     if(tdHandle < CY_DMA_NUMBEROF_TDS)
     {
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != transferCount)
         {
-            /* Get the 12 bits of the transfer count */
+            /* Get 12 bits of transfer count */
             reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
             *transferCount = 0x0FFFu & CY_GET_REG16(convert);
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != nextTd)
         {
-            /* Get the Next TD pointer */
+            /* Get Next TD pointer */
             *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != configuration)
         {
-            /* Get the configuration the TD */
+            /* Get configuration TD */
             *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
         }
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h
index 6a3ee851..8bbb4a7d 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the DMA Controller.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -116,7 +116,7 @@ typedef struct dmac_tdmem2_struct
 
 #define CY_DMA_TD_SIZE              0x08u
 
-/* The "u" was removed as workaround for Keil compiler bug */
+/* "u" was removed as workaround for Keil compiler bug */
 #define CY_DMA_TD_SWAP_EN           0x80
 #define CY_DMA_TD_SWAP_SIZE4        0x40
 #define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
@@ -178,7 +178,18 @@ typedef struct dmac_tdmem2_struct
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
 #define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c
index e692e661..38ffe998 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the FLASH/EEPROM.
@@ -13,7 +13,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,9 +21,12 @@
 
 #include "CyFlash.h"
 
+/*  The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
+
 
 /*******************************************************************************
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
 * The first byte is the sign of the temperature (0 = negative, 1 = positive).
 * The second byte is the magnitude.
 *******************************************************************************/
@@ -35,6 +38,7 @@ uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 
 
 static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
 
 
 /*******************************************************************************
@@ -53,13 +57,48 @@ static cystatus CySetTempInt(void);
 *******************************************************************************/
 void CyFlash_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or eeprom to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable flash. Active flash macros consume current, but re-enabling a
+    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+    * macro during that time, it will be stalled. This bit allows the flash to
+    * be enabled even if the CPU is disabled, which allows a quicker return to
+    * code execution.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
 
-    CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -83,11 +122,14 @@ void CyFlash_Start(void)
 *******************************************************************************/
 void CyFlash_Stop(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -97,7 +139,7 @@ void CyFlash_Stop(void)
 *
 * Summary:
 *  Sends a command to the SPC to read the die temperature. Sets a global value
-*  used by the Write functions. This function must be called once before
+*  used by the Write function. This function must be called once before
 *  executing a series of Flash writing functions.
 *
 * Parameters:
@@ -153,13 +195,65 @@ static cystatus CySetTempInt(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        status = CySpcGetAlgorithm();
+
+        if(CYRET_STARTED == status)
+        {
+            while(CY_SPC_BUSY)
+            {
+                /* Spin until idle. */
+                CyDelayUs(1u);
+            }
+
+            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySetTemp
 ********************************************************************************
 *
 * Summary:
-*  This is a wraparound for CySetTempInt(). It is used to return second
-*  successful read of temperature value.
+*  This is a wraparound for CySetTempInt(). It is used to return the second
+*  successful read of the temperature value.
 *
 * Parameters:
 *  None
@@ -171,14 +265,14 @@ static cystatus CySetTempInt(void)
 *   CYRET_UNKNOWN if there was an SPC error.
 *
 *  uint8 dieTemperature[2]:
-*   Holds die temperature for the flash writting algorithm. The first byte is
+*   Holds the die temperature for the flash writing algorithm. The first byte is
 *   the sign of the temperature (0 = negative, 1 = positive). The second byte is
 *   the magnitude.
 *
 *******************************************************************************/
 cystatus CySetTemp(void) 
 {
-    cystatus status = CySetTempInt();
+    cystatus status = CyFlashGetSpcAlgorithm();
 
     if(status == CYRET_SUCCESS)
     {
@@ -195,12 +289,12 @@ cystatus CySetTemp(void)
 *
 * Summary:
 *  Sets the user supplied temporary buffer to store SPC data while performing
-*  flash and EEPROM commands. This buffer is only necessary when Flash ECC is
+*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
 *  disabled.
 *
 * Parameters:
 *  buffer:
-*   Address of block of memory to store temporary memory. The size of the block
+*   The address of a block of memory to store temporary memory. The size of the block
 *   of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
 *
 * Return:
@@ -219,10 +313,12 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
         if(NULL == buffer)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_BAD_PARAM;
         }
         else if(CySpcLock() != CYRET_SUCCESS)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_LOCKED;
         }
         else
@@ -233,7 +329,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
     #else
 
-        /* To supress the warning */
+        /* To suppress warning */
         buffer = buffer;
 
     #endif  /* (CYDEV_ECC_ENABLE == 0u) */
@@ -242,120 +338,48 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 }
 
 
-#if(CYDEV_ECC_ENABLE == 1)
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sends a command to the SPC to load and program a row of data in
-    *  Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID:    ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress: rowAddress of flash row to program.
-    *  rowData:    Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint16 rowSize;
-        cystatus status;
-
-        rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
-        status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
-        return(status);
-    }
-
-#else
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *   Sends a command to the SPC to load and program a row of data in
-    *   Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID      : ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress   : rowAddress of flash row to program.
-    *  rowData      : Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint8 i;
-        uint32 offset;
-        uint16 rowSize;
-        cystatus status;
-
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
-            {
-                rowSize = CYDEV_EEPROM_ROW_SIZE;
-            }
-            else
-            {
-                rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
-
-                /* Save the ECC area. */
-                offset = CYDEV_ECC_BASE +
-                        ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
-                        ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
-
-                for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
-                {
-                    *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-                }
-            }
-
-            /* Copy the rowdata to the temporary buffer. */
-        #if(CY_PSOC3)
-            (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
-        #else
-            (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
-        #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to load and program a row of data in
+*  Flash or EEPROM.
+*
+* Parameters:
+*  arrayID:    ID of the array to write.
+*   The type of write, Flash or EEPROM, is determined from the array ID.
+*   The arrays in the part are sequential starting at the first ID for the
+*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+*  rowAddress: rowAddress of flash row to program.
+*  rowData:    Array of bytes to write.
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED if the SPC is already in use.
+*   CYRET_CANCELED if command not accepted
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
+{
+    uint16 rowSize;
+    cystatus status;
 
-        return(status);
-    }
+    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
 
-#endif /* (CYDEV_ECC_ENABLE == 0u) */
+    return(status);
+}
 
 
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
 #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
 
     /*******************************************************************************
@@ -363,7 +387,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a command to the SPC to load and program a row of config data in flash.
+    *  Sends a command to the SPC to load and program a row of config data in the Flash.
     *  This function is only valid for Flash array IDs (not for EEPROM).
     *
     * Parameters:
@@ -371,8 +395,8 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     *   The arrays in the part are sequential starting at the first ID for the
     *   specific memory type. The array ID for the Flash memory lasts
     *   from 0x00 to 0x3F.
-    *  rowAddress:   Address of the sector to erase.
-    *  rowECC:       Array of bytes to write.
+    *  rowAddress:   The address of the sector to erase.
+    *  rowECC:       The array of bytes to write.
     *
     * Return:
     *  status:
@@ -385,42 +409,9 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
     
     {
-        uint32 offset;
-        uint16 i;
         cystatus status;
 
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            /* Read the existing flash data. */
-            offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
-                     ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
-
-            #if (CYDEV_FLS_BASE != 0u)
-                offset += CYDEV_FLS_BASE;
-            #endif  /* (CYDEV_FLS_BASE != 0u) */
-
-            for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
-            {
-                rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-            }
-
-            #if(CY_PSOC3)
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (void *)(uint32)rowECC,
-                              (int16)CYDEV_ECC_ROW_SIZE);
-            #else
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (const void *)rowECC,
-                              CYDEV_ECC_ROW_SIZE);
-            #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
 
         return (status);
     }
@@ -433,7 +424,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 * Function Name: CyWriteRowFull
 ********************************************************************************
 * Summary:
-*  Sends a command to the SPC to load and program a row of data in flash.
+*  Sends a command to the SPC to load and program a row of data in the Flash.
 *  rowData array is expected to contain Flash and ECC data if needed.
 *
 * Parameters:
@@ -452,63 +443,107 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
         
 {
-    cystatus status;
+    cystatus status = CYRET_SUCCESS;
 
-    if(CySpcLock() == CYRET_SUCCESS)
+    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
     {
-        /* Load row data into SPC internal latch */
-        status = CySpcLoadRow(arrayId, rowData, rowSize);
+        status = CYRET_BAD_PARAM;
+    }
 
-        if(CYRET_STARTED == status)
+    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
+    {
+        /* Flash */
+        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
         {
-            while(CY_SPC_BUSY)
-            {
-                /* Wait for SPC to finish and get SPC status */
-                CyDelayUs(1u);
-            }
+            status = CYRET_BAD_PARAM;
+        }
+    }
+    else
+    {
+        /* EEPROM */
+        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
 
-            /* Hide SPC status */
-            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-            {
-                status = CYRET_SUCCESS;
-            }
-            else
-            {
-                status = CYRET_UNKNOWN;
-            }
+        if(CY_EEPROM_SIZEOF_ROW != rowSize)
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
 
-            if(CYRET_SUCCESS == status)
+    if(rowData == NULL)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    if(status == CYRET_SUCCESS)
+    {
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Load row data into SPC internal latch */
+            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+            if(CYRET_STARTED == status)
             {
-                /* Erase and program flash with the data from SPC interval latch */
-                status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait for SPC to finish and get SPC status */
+                    CyDelayUs(1u);
+                }
 
-                if(CYRET_STARTED == status)
+                /* Hide SPC status */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
                 {
-                    while(CY_SPC_BUSY)
-                    {
-                        /* Wait for SPC to finish and get SPC status */
-                        CyDelayUs(1u);
-                    }
+                    status = CYRET_SUCCESS;
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
 
-                    /* Hide SPC status */
-                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                    {
-                        status = CYRET_SUCCESS;
-                    }
-                    else
+                if(CYRET_SUCCESS == status)
+                {
+                    /* Erase and program flash with data from SPC interval latch */
+                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+                    if(CYRET_STARTED == status)
                     {
-                        status = CYRET_UNKNOWN;
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait for SPC to finish and get SPC status */
+                            CyDelayUs(1u);
+                        }
+
+                        /* Hide SPC status */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                        else
+                        {
+                            status = CYRET_UNKNOWN;
+                        }
                     }
                 }
             }
-
+            CySpcUnlock();
+        }   /* if(CySpcLock() == CYRET_SUCCESS) */
+        else
+        {
+            status = CYRET_LOCKED;
         }
-
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_LOCKED;
     }
 
     return(status);
@@ -521,9 +556,9 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, u
 *
 * Summary:
 *  Sets the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash. This function must be called before increasing CPU
-*  clock frequency. It can optionally be called after lowering CPU clock
-*  frequency in order to improve CPU performance.
+*  coming back from the Flash. This function must be called before increasing the CPU
+*  clock frequency. It can optionally be called after lowering the CPU clock
+*  frequency in order to improve the CPU performance.
 *
 * Parameters:
 *  uint8 freq:
@@ -542,55 +577,42 @@ void CyFlash_SetWaitCycles(uint8 freq)
 
     /***************************************************************************
     * The number of clock cycles the cache will wait before it samples data
-    * coming back from Flash must be equal or greater to to the CPU frequency
+    * coming back from the Flash must be equal or greater to to the CPU frequency
     * outlined in clock cycles.
     ***************************************************************************/
 
-    #if (CY_PSOC3)
-
-        if (freq <= 22u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 44u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC3) */
-
-
-    #if (CY_PSOC5)
-
-        if (freq <= 16u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 33u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 50u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC5) */
+    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
+    }
+#if (CY_PSOC5)
+    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
+    }
+    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
+    }
+#endif  /* (CY_PSOC5) */
+    else
+    {
+        /* Halt CPU in debug mode if frequency is invalid */
+        CYASSERT(0u != 0u);
+    }
 
     /* Restore global interrupt enable state */
     CyExitCriticalSection(interruptState);
@@ -613,11 +635,45 @@ void CyFlash_SetWaitCycles(uint8 freq)
 *******************************************************************************/
 void CyEEPROM_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or EEPROM to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+    * the EE will not acknowledge a PHUB request.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -637,11 +693,14 @@ void CyEEPROM_Start(void)
 *******************************************************************************/
 void CyEEPROM_Stop (void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    uint8 interruptState;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -661,12 +720,12 @@ void CyEEPROM_Stop (void)
 *******************************************************************************/
 void CyEEPROM_ReadReserve(void) 
 {
-    /* Make a request for PHUB to have access */
-    *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+    /* Make request for PHUB to have access */
+    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
 
-    while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
+    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
     {
-        /* Wait for acknowledgement from PHUB */
+        /* Wait for acknowledgment from PHUB */
     }
 }
 
@@ -687,7 +746,7 @@ void CyEEPROM_ReadReserve(void)
 *******************************************************************************/
 void CyEEPROM_ReadRelease(void) 
 {
-    *CY_FLASH_EE_SCR_PTR |= 0x00u;
+    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
 }
 
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h
index 69f8c88c..119d7fc6 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the FLASH/EEPROM.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,13 +41,19 @@ extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 #define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
 #define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
 
+#if(CYDEV_ECC_ENABLE == 0)
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
 #define CY_EEPROM_BASE              (CYDEV_EE_BASE)
 #define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
 #define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EEPROM_SECTOR_SIZE)
 #define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS       (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
 #define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-
+#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
 
 #if !defined(CYDEV_FLS_BASE)
     #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
@@ -85,13 +91,29 @@ void CyEEPROM_ReadRelease(void) ;
 /***************************************
 *     Registers
 ***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
+
 /* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
 
 /* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
 
 
 /* Cache Control Register */
@@ -119,35 +141,64 @@ void CyEEPROM_ReadRelease(void) ;
 ***************************************/
 
 /* Power Mode Masks */
-#define CY_FLASH_PM_EE_MASK                 (0x10u)
-#define CY_FLASH_PM_FLASH_MASK              (0x01u)
 
-/* Frequency Constants */
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
+
+/* Enable Flash */
 #if (CY_PSOC3)
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
+#else
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
+#endif  /* (CY_PSOC3) */
+
 
-    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
-    #define CY_FLASH_GREATER_44MHz              (0x03u)
 
+/* Frequency Constants */
+#if (CY_PSOC3)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
 #endif  /* (CY_PSOC3) */
 
 #if (CY_PSOC5)
-
-    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
-    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
-    #define CY_FLASH_GREATER_51MHz              (0x00u)
-
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
+    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
+    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
+    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
 #endif  /* (CY_PSOC5) */
 
 #define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
 #define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-#define CY_FLASH_EE_STARTUP_DELAY               (5u)
 
 #define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
 #define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
 
 
+#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
 
 /* Default values for getting temperature. */
 
@@ -167,7 +218,42 @@ void CyEEPROM_ReadRelease(void) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
+    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
+    #define CY_FLASH_GREATER_51MHz              (0x00u)
+#endif  /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
+    #define CY_FLASH_GREATER_44MHz              (0x03u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
 *******************************************************************************/
 #define FLASH_SIZE                  (CY_FLASH_SIZE)
 #define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
@@ -177,12 +263,10 @@ void CyEEPROM_ReadRelease(void) ;
 #define EEPROM_SIZEOF_SECTOR        (CY_EEPROM_SIZEOF_ARRAY)
 #define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
 #define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_NUMBER_SECTORS    (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_SIZEOF_SECTOR     (CY_EEPROM_SIZEOF_ARRAY)
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
 *******************************************************************************/
 #define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c
index 206c6cb1..a36bee0d 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c
@@ -1,16 +1,16 @@
 /*******************************************************************************
 * File Name: CyLib.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   Provides system API for the clocking, interrupts and watchdog timer.
+*   Provides a system API for the clocking, interrupts and watchdog timer.
 *
 *  Note:
 *   Documentation of the API's in this file is located in the
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -49,6 +49,12 @@ static uint8 CyUSB_PowerOnCheck(void)  ;
 static void CyIMO_SetTrimValue(uint8 freq) ;
 static void CyBusClk_Internal_SetDivider(uint16 divider);
 
+#if(CY_PSOC5)
+	static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+    static void CySysTickServiceCallbacks(void);
+    uint32 CySysTickInitVar = 0u;
+#endif  /* (CY_PSOC5) */
+
 
 /*******************************************************************************
 * Function Name: CyPLL_OUT_Start
@@ -72,7 +78,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider);
 *     clock can still be used.
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -95,7 +101,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
     uint8 pmTwCfg2State;
 
 
-    /* Enables the PLL circuit  */
+    /* Enables PLL circuit  */
     CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
 
     if(wait != 0u)
@@ -111,7 +117,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
 
         while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
             if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
             {
                 if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
@@ -180,11 +186,11 @@ void CyPLL_OUT_Stop(void)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -235,11 +241,11 @@ void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -279,7 +285,7 @@ void CyPLL_OUT_SetSource(uint8 source)
 *  None
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -305,7 +311,7 @@ void CyIMO_Start(uint8 wait)
 
     if(0u != wait)
     {
-        /* Need to turn on the 100KHz ILO if it happens to not already be running.*/
+        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
         ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
         pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
         pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
@@ -314,7 +320,7 @@ void CyIMO_Start(uint8 wait)
 
         while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
         }
 
         if(0u == ilo100KhzEnable)
@@ -442,7 +448,7 @@ static void CyIMO_SetTrimValue(uint8 freq)
         /* If USB is powered */
         if(usbPowerOn == 1u)
         {
-            /* Lock the USB Oscillator */
+            /* Lock USB Oscillator */
             CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
         }
         break;
@@ -477,11 +483,11 @@ static void CyIMO_SetTrimValue(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When the USB setting is chosen, the USB clock locking circuit is enabled.
@@ -495,15 +501,15 @@ void CyIMO_SetFreq(uint8 freq)
     uint8 nextFreq;
 
     /***************************************************************************
-    * When changing the IMO frequency the Trim values must also be set
+    * If the IMO frequency is changed,the Trim values must also be set
     * accordingly.This requires reading the current frequency. If the new
-    * frequency is faster, then set the new trim and then change the frequency,
-    * otherwise change the frequency and then set the new trim values.
+    * frequency is faster, then set a new trim and then change the frequency,
+    * otherwise change the frequency and then set new trim values.
     ***************************************************************************/
 
     currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
 
-    /* Check if the requested frequency is USB. */
+    /* Check if requested frequency is USB. */
     nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
 
     switch (currentFreq)
@@ -545,11 +551,11 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq >= currentFreq)
     {
-        /* Set the new trim first */
+        /* Set new trim first */
         CyIMO_SetTrimValue(freq);
     }
 
-    /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
     switch(freq)
     {
     case CY_IMO_FREQ_3MHZ:
@@ -599,7 +605,7 @@ void CyIMO_SetFreq(uint8 freq)
         break;
     }
 
-    /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */
+    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
     if (freq == CY_IMO_FREQ_USB)
     {
         CyIMO_EnableDoubler();
@@ -611,7 +617,7 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq < currentFreq)
     {
-        /* Set the new trim after setting the frequency */
+        /* Set the trim after setting frequency */
         CyIMO_SetTrimValue(freq);
     }
 }
@@ -625,7 +631,7 @@ void CyIMO_SetFreq(uint8 freq)
 *  Sets the source of the clock output from the IMO block.
 *
 *  The output from the IMO is by default the IMO itself. Optionally the MHz
-*  Crystal or a DSI input can be the source of the IMO output instead.
+*  Crystal or DSI input can be the source of the IMO output instead.
 *
 * Parameters:
 *   source: CY_IMO_SOURCE_DSI to set the DSI as source.
@@ -636,11 +642,11 @@ void CyIMO_SetFreq(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -687,7 +693,7 @@ void CyIMO_SetSource(uint8 source)
 *******************************************************************************/
 void CyIMO_EnableDoubler(void) 
 {
-    /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */
+    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
     CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
 }
 
@@ -733,11 +739,11 @@ void CyIMO_DisableDoubler(void)
 *  The current source and the new source must both be running and stable before
 *  calling this function.
 *
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -757,18 +763,18 @@ void CyMasterClk_SetSource(uint8 source)
 *
 * Parameters:
 *  uint8 divider:
-*   Valid range [0-255]. The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   The valid range is [0-255]. The clock will be divided by this value + 1.
+*   For example to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When changing the Master or Bus clock divider value from div-by-n to div-by-1
@@ -787,12 +793,12 @@ void CyMasterClk_SetDivider(uint8 divider)
 ********************************************************************************
 *
 * Summary:
-*  Function used by CyBusClk_SetDivider(). For internal use only.
+*  The function used by CyBusClk_SetDivider(). For internal use only.
 *
 * Parameters:
 *   divider: Valid range [0-65535].
 *   The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
@@ -807,7 +813,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
     /* Enable mask bits to enable shadow loads */
     CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
 
-    /* Update Shadow Divider Value Register with the new divider */
+    /* Update Shadow Divider Value Register with new divider */
     CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
     CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
 
@@ -827,21 +833,21 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
 ********************************************************************************
 *
 * Summary:
-*  Sets the divider value used to generate Bus Clock.
+*  Sets the divider value used to generate the Bus Clock.
 *
 * Parameters:
 *  divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-*  For example to divide by 2 this parameter should be set to 1.
+*  For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -853,13 +859,13 @@ void CyBusClk_SetDivider(uint16 divider)
 
     interruptState = CyEnterCriticalSection();
 
-    /* Work around to set the bus clock divider value */
+    /* Work around to set bus clock divider value */
     busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
     busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
 
     if ((divider == 0u) || (busClkDiv == 0u))
     {
-        /* Save away the master clock divider value */
+        /* Save away master clock divider value */
         masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
 
         if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
@@ -870,7 +876,7 @@ void CyBusClk_SetDivider(uint16 divider)
 
         if (divider == 0u)
         {
-            /* Set the SSS bit and the divider register desired value */
+            /* Set SSS bit and divider register desired value */
             CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
             CyBusClk_Internal_SetDivider(divider);
         }
@@ -880,7 +886,7 @@ void CyBusClk_SetDivider(uint16 divider)
             CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
         }
 
-        /* Restore the master clock */
+        /* Restore master clock */
         CyMasterClk_SetDivider(masterClkDiv);
     }
     else
@@ -904,17 +910,17 @@ void CyBusClk_SetDivider(uint16 divider)
     *
     * Parameters:
     *  divider: Valid range [0-15]. The clock will be divided by this value + 1.
-    *  For example to divide by 2 this parameter should be set to 1.
+    *  For example, to divide this parameter by two should be set to 1.
     *
     * Return:
     *  None
     *
     * Side Effects:
-    *  If as result of this function execution the CPU clock frequency is increased
-    *  then the number of clock cycles the cache will wait before it samples data
-    *  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-    *  with appropriate parameter. It can be optionally called if CPU clock
-    *  frequency is lowered in order to improve CPU performance.
+    *  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
     *  See CyFlash_SetWaitCycles() description for more information.
     *
     *******************************************************************************/
@@ -972,7 +978,7 @@ void CyUsbClk_SetSource(uint8 source)
 *******************************************************************************/
 void CyILO_Start1K(void) 
 {
-    /* Set the bit 1 of ILO RS */
+    /* Set bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
 }
 
@@ -984,7 +990,7 @@ void CyILO_Start1K(void)
 * Summary:
 *  Disables the ILO 1 KHz oscillator.
 *
-*  Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power
+*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
 *  mode APIs are expected to be used. For more information, refer to the Power
 *  Management section of this document.
 *
@@ -1000,7 +1006,7 @@ void CyILO_Start1K(void)
 *******************************************************************************/
 void CyILO_Stop1K(void) 
 {
-    /* Clear the bit 1 of ILO RS */
+    /* Clear bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
 }
 
@@ -1064,7 +1070,7 @@ void CyILO_Stop100K(void)
 *******************************************************************************/
 void CyILO_Enable33K(void) 
 {
-    /* Set the bit 5 of ILO RS */
+    /* Set bit 5 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
 }
 
@@ -1141,7 +1147,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
     /* Get current state. */
     state = CY_LIB_SLOWCLK_ILO_CR0_REG;
 
-    /* Set the the oscillator power mode. */
+    /* Set the oscillator power mode. */
     if(mode != CY_ILO_FAST_START)
     {
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
@@ -1151,7 +1157,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
     }
 
-    /* Return the old mode. */
+    /* Return old mode. */
     return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
 }
 
@@ -1183,14 +1189,14 @@ void CyXTAL_32KHZ_Start(void)
         CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
     #endif  /* (CY_PSOC3) */
 
-    /* Enable operation of the 32K Crystal Oscillator */
+    /* Enable operation of 32K Crystal Oscillator */
     CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
 
     for (i = 1000u; i > 0u; i--)
     {
         if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
         {
-            /* Ready - switch to the hign power mode */
+            /* Ready - switch to high power mode */
             (void) CyXTAL_32KHZ_SetPowerMode(0u);
 
             break;
@@ -1256,9 +1262,9 @@ uint8 CyXTAL_32KHZ_ReadStatus(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the power mode for the 32 KHz oscillator used during sleep mode.
+*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
 *  Allows for lower power during sleep when there are fewer sources of noise.
-*  During active mode the oscillator is always run in high power mode.
+*  During the active mode the oscillator is always run in the high power mode.
 *
 * Parameters:
 *  uint8 mode
@@ -1345,7 +1351,7 @@ cystatus CyXTAL_Start(uint8 wait)
     uint8 pmTwCfg2Tmp;
 
 
-    /* Enables the MHz crystal oscillator circuit  */
+    /* Enables MHz crystal oscillator circuit  */
     CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
 
 
@@ -1366,19 +1372,19 @@ cystatus CyXTAL_Start(uint8 wait)
             /* Read XERR bit to clear it */
             (void) CY_CLK_XMHZ_CSR_REG;
 
-            /* Wait for a millisecond - 4 x 250 us */
+            /* Wait for 1 millisecond - 4 x 250 us */
             for(count = 4u; count > 0u; count--)
             {
                 while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
                 {
-                    /* Wait for the FTW interrupt event */
+                    /* Wait for FTW interrupt event */
                 }
             }
 
 
             /*******************************************************************
-            * High output indicates oscillator failure.
-            * Only can be used after start-up interval (1 ms) is completed.
+            * High output indicates an oscillator failure.
+            * Only can be used after a start-up interval (1 ms) is completed.
             *******************************************************************/
             if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
             {
@@ -1417,7 +1423,7 @@ cystatus CyXTAL_Start(uint8 wait)
 *******************************************************************************/
 void CyXTAL_Stop(void) 
 {
-    /* Disable the the oscillator. */
+    /* Disable oscillator. */
     FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
 }
 
@@ -1472,7 +1478,7 @@ void CyXTAL_DisableErrStatus(void)
 *
 * Summary:
 *  Reads the XERR status bit for the megahertz crystal. This status bit is a
-*  sticky clear on read value. This function is not available for PSoC5.
+*  sticky, clear on read. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1486,8 +1492,8 @@ void CyXTAL_DisableErrStatus(void)
 uint8 CyXTAL_ReadStatus(void) 
 {
     /***************************************************************************
-    * High output indicates oscillator failure. Only use this after start-up
-    * interval is completed. This can be used for status and failure recovery.
+    * High output indicates an oscillator failure. Only use this after a start-up
+    * interval is completed. This can be used for the status and failure recovery.
     ***************************************************************************/
     return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
 }
@@ -1501,7 +1507,7 @@ uint8 CyXTAL_ReadStatus(void)
 *  Enables the fault recovery circuit which will switch to the IMO in the case
 *  of a fault in the megahertz crystal circuit. The crystal must be up and
 *  running with the XERR bit at 0, before calling this function to prevent
-*  immediate fault switchover. This function is not available for PSoC5.
+*  an immediate fault switchover. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1543,7 +1549,7 @@ void CyXTAL_DisableFaultRecovery(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the startup settings for the crystal. Logic model outputs a frequency
+*  Sets the startup settings for the crystal. The logic model outputs a frequency
 *  (setting + 4) MHz when enabled.
 *
 *  This is artificial as the actual frequency is determined by an attached
@@ -1551,7 +1557,7 @@ void CyXTAL_DisableFaultRecovery(void)
 *
 * Parameters:
 *  setting: Valid range [0-31].
-*   Value is dependent on the frequency and quality of the crystal being used.
+*   The value is dependent on the frequency and quality of the crystal being used.
 *   Refer to the device TRM and datasheet for more information.
 *
 * Return:
@@ -1648,7 +1654,7 @@ void CyHalt(uint8 reason) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Forces a software reset of the device.
+*  Forces a device software reset.
 *
 * Parameters:
 *  None
@@ -1672,9 +1678,9 @@ void CySoftwareReset(void)
 *
 *  Note:
 *  CyDelay has been implemented with the instruction cache assumed enabled. When
-*  instruction cache is disabled on PSoC5, CyDelay will be two times larger. For
-*  example, with instruction cache disabled CyDelay(100) would result in about
-*  200 ms delay instead of 100 ms.
+*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+*  For example, with instruction cache disabled CyDelay(100) would result in
+*  about 200 ms delay instead of 100 ms.
 *
 * Parameters:
 *  milliseconds: number of milliseconds to delay.
@@ -1724,8 +1730,8 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
     *
     * Side Effects:
     *  CyDelayUS has been implemented with the instruction cache assumed enabled.
-    *  When instruction cache is disabled on PSoC 5, CyDelayUs will be two times
-    *  larger. For example, with instruction cache disabled CyDelayUs(100) would
+    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
     *  result in about 200 us delay instead of 100 us.
     *
     *  If the bus clock frequency is a small non-integer number, the actual delay
@@ -1745,10 +1751,10 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Sets clock frequency for CyDelay.
+*  Sets the clock frequency for CyDelay.
 *
 * Parameters:
-*  freq: Frequency of bus clock in Hertz.
+*  freq: The frequency of the bus clock in Hertz.
 *
 * Return:
 *  None
@@ -1779,7 +1785,7 @@ void CyDelayFreq(uint32 freq) CYREENTRANT
 *  Enables the watchdog timer.
 *
 *  The timer is configured for the specified count interval, the central
-*  timewheel is cleared, the setting for low power mode is configured and the
+*  timewheel is cleared, the setting for the low power mode is configured and the
 *  watchdog timer is enabled.
 *
 *  Once enabled the watchdog cannot be disabled. The watchdog counts each time
@@ -1826,11 +1832,11 @@ void CyWdtStart(uint8 ticks, uint8 lpMode)
     CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
     CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
 
-    /* Setting the low power mode */
+    /* Setting low power mode */
     CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
                        (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
 
-    /* Enables the watchdog reset */
+    /* Enables watchdog reset */
     CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
 }
 
@@ -1862,16 +1868,16 @@ void CyWdtClear(void)
 *
 * Summary:
 *  Enables the digital low voltage monitors to generate interrupt on Vddd
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vddd threshold:
+*  reset: The option to reset the device at a specified Vddd threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
 *  threshold: Sets the trip level for the voltage monitor.
-*  Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-*  interval.
+*  Values from 1.70 V to 5.45 V are accepted with an interval  of approximately
+*  250 mV.
 *
 * Return:
 *  None
@@ -1887,7 +1893,7 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
                             (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -1912,10 +1918,10 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
 *
 * Summary:
 *  Enables the analog low voltage monitors to generate interrupt on Vdda
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vdda threshold:
+*  reset: The option to reset the device at a specified Vdda threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
@@ -1936,7 +1942,7 @@ void CyVdLvAnalogEnable(uint8 reset, uint8 threshold)
     CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -2258,31 +2264,14 @@ void CyEnableInts(uint32 mask)
         CY_NOP;
         CY_NOP;
 
-        /* All entries in the cache are invalidated on the next clock cycle. */
+        /* All entries in cache are invalidated on next clock cycle. */
         CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
 
+        /* Once this is executed it's guaranteed the cache has been flushed */
+        (void) CY_CACHE_CONTROL_REG;
 
-        /***********************************************************************
-        * The prefetch unit could/would be filled with the instructions that
-        * succeed the flush. Since a flush is desired then theoretically those
-        * instructions might be considered stale/invalid.
-        ***********************************************************************/
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
+        /* Flush the pipeline */
+        CY_SYS_ISB;
 
         /* Restore global interrupt enable state */
         CyExitCriticalSection(interruptState);
@@ -2298,8 +2287,18 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *  number: Interrupt number, valid range [0-15].
-       address: Pointer to an interrupt service routine.
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    *  address: Pointer to an interrupt service routine.
     *
     * Return:
     *   The old ISR vector at this location.
@@ -2332,7 +2331,16 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *   number: The interrupt number, valid range [0-15].
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
     *
     * Return:
     *   Address of the ISR in the interrupt vector table.
@@ -2390,7 +2398,7 @@ void CyEnableInts(uint32 mask)
     *  number: Valid range [0-31].  Interrupt number
     *
     * Return:
-    *  Address of the ISR in the interrupt vector table.
+    *  The address of the ISR in the interrupt vector table.
     *
     *******************************************************************************/
     cyisraddress CyIntGetVector(uint8 number)
@@ -2471,10 +2479,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR;
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
     }
 
@@ -2609,10 +2617,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
     }
 
@@ -2630,20 +2638,20 @@ void CyEnableInts(uint32 mask)
     *  If 1 is passed as a parameter:
     *   - if any of the SC blocks are used - enable pumps for the SC blocks and
     *     start boost clock.
-    *   - For the each enabled SC block set boost clock index and enable boost
+    *   - For each enabled SC block set a boost clock index and enable the boost
     *     clock.
     *
     *  If non-1 value is passed as a parameter:
     *   - If all SC blocks are not used - disable pumps for the SC blocks and
-    *     stop boost clock.
-    *   - For the each enabled SC block clear boost clock index and disable boost
+    *     stop the boost clock.
+    *   - For each enabled SC block clear the boost clock index and disable the  boost
     *     clock.
     *
-    *  The global variable CyScPumpEnabled is updated to be equal to passed
+    *  The global variable CyScPumpEnabled is updated to be equal to passed the
     *  parameter.
     *
     * Parameters:
-    *   uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.
+    *   uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
     *                 1 - Enable
     *                 0 - Disable
     *
@@ -2707,4 +2715,391 @@ void CyEnableInts(uint32 mask)
 #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
+#if(CY_PSOC5)
+    /*******************************************************************************
+    * Function Name: CySysTickStart
+    ********************************************************************************
+    *
+    * Summary:
+    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
+    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
+    *  Refer to the corresponding function description for the details.
+
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStart(void)
+    {
+        if (0u == CySysTickInitVar)
+        {
+            CySysTickInit();
+            CySysTickInitVar = 1u;
+        }
+
+        CySysTickEnable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickInit
+    ********************************************************************************
+    *
+    * Summary:
+    *  Initializes the callback addresses with pointers to NULL, associates the
+    *  SysTick system vector with the function that is responsible for calling
+    *  registered callback functions, configures SysTick timer to generate interrupt
+    * every 1 ms.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set.
+    *
+    *  The 1 ms interrupt interval is configured based on the frequency determined
+    *  by PSoC Creator at build time. If System clock frequency is changed in
+    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
+    *
+    *******************************************************************************/
+    void CySysTickInit(void)
+    {
+        uint32 i;
+
+        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+        {
+            CySysTickCallbacks[i] = (void *) 0;
+        }
+
+    	(void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+        CySysTickSetReload(cydelay_freq_hz/1000u);
+        CySysTickClear();
+        CyIntEnable(CY_INT_SYSTICK_IRQN);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick timer and its interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnable(void)
+    {
+        CySysTickEnableInterrupt();
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickStop
+    ********************************************************************************
+    *
+    * Summary:
+    *  Stops the system timer (SysTick).
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStop(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickDisableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickDisableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero. This
+    *  function do not change or reset current sysTick counter value, so it should
+    *  be cleared using CySysTickClear() API.
+    *
+    * Parameters:
+    *  value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickSetReload(uint32 value)
+    {
+        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Counter reset value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetReload(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetValue
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets current SysTick counter value.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Current SysTick counter value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetValue(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetClockSource
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the clock source for the SysTick counter.
+    *
+    * Parameters:
+    *  clockSource: Clock source for SysTick counter
+    *         Define                     Clock Source
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                              clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set. If clock source is not ready this
+    *  function call will have no effect. After changing clock source to the low frequency
+    *  clock the counter and reload register values will remain unchanged so time to
+    *  the interrupt will be significantly bigger and vice versa.
+    *
+    *******************************************************************************/
+    void CySysTickSetClockSource(uint32 clockSource)
+    {
+        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+        {
+            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+        }
+        else
+        {
+            CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCountFlag
+    ********************************************************************************
+    *
+    * Summary:
+    *  The count flag is set once SysTick counter reaches zero.
+    *   The flag cleared on read.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Returns non-zero value if counter is set, otherwise zero is returned.
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetCountFlag(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickClear
+    ********************************************************************************
+    *
+    * Summary:
+    *  Clears the SysTick counter for well-defined startup.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickClear(void)
+    {
+        CY_SYS_SYST_CVR_REG = 0u;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function set the pointers to the functions that will be called on
+    *  SysTick interrupt.
+    *
+    * Parameters:
+    *  number:  The number of callback function address to be set.
+    *           The valid range is from 0 to 4.
+    *  CallbackFunction: Function address.
+    *
+    * Return:
+    *  Returns the address of the previous callback function.
+    *  The NULL is returned if the specified address in not set.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+    {
+        cySysTickCallback retVal;
+
+        retVal = CySysTickCallbacks[number];
+        CySysTickCallbacks[number] = function;
+        return (retVal);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function get the specified callback pointer.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickGetCallback(uint32 number)
+    {
+        return ((cySysTickCallback) CySysTickCallbacks[number]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickServiceCallbacks
+    ********************************************************************************
+    *
+    * Summary:
+    *  System Tick timer interrupt routine
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    static void CySysTickServiceCallbacks(void)
+    {
+        uint32 i;
+
+        /* Verify that tick timer flag was set */
+        if (1u == CySysTickGetCountFlag())
+        {
+            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+            {
+                if (CySysTickCallbacks[i] != (void *) 0)
+                {
+                    (void)(CySysTickCallbacks[i])();
+                }
+            }
+        }
+    }
+#endif /* (CY_PSOC5) */
+
+
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h
index 8a69921b..a718ffad 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyLib.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the system, clocking, interrupts and
@@ -11,7 +11,7 @@
 *  Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -163,6 +163,30 @@ uint8 CyVdRealTimeStatus(void) ;
 
 void CySetScPumps(uint8 enable) ;
 
+#if(CY_PSOC5)
+    /* Default interrupt handler */
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif  /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+    /* System tick timer APIs */
+    typedef void (*cySysTickCallback)(void);
+
+    void CySysTickStart(void);
+    void CySysTickInit(void);
+    void CySysTickEnable(void);
+    void CySysTickStop(void);
+    void CySysTickEnableInterrupt(void);
+    void CySysTickDisableInterrupt(void);
+    void CySysTickSetReload(uint32 value);
+    uint32 CySysTickGetReload(void);
+    uint32 CySysTickGetValue(void);
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+    cySysTickCallback CySysTickGetCallback(uint32 number);
+    void CySysTickSetClockSource(uint32 clockSource);
+    uint32 CySysTickGetCountFlag(void);
+    void CySysTickClear(void);
+#endif  /* (CY_PSOC5) */
 
 /***************************************
 * API Constants
@@ -400,6 +424,23 @@ void CySetScPumps(uint8 enable) ;
 #define CY_ALT_ACT_USB_ENABLED          (0x01u)
 
 
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * Instruction Synchronization Barrier flushes the pipeline in the processor,
+    * so that all instructions following the ISB are fetched from cache or
+    * memory, after the instruction has been completed.
+    ***************************************************************************/
+
+    #if defined(__ARMCC_VERSION)
+        #define CY_SYS_ISB       __isb(0x0f)
+    #else   /* ASM for GCC & IAR */
+        #define CY_SYS_ISB       asm volatile ("isb \n")
+    #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
 /***************************************
 * Registers
 ***************************************/
@@ -689,16 +730,29 @@ void CySetScPumps(uint8 enable) ;
     #define CY_CACHE_CONTROL_REG        (* (reg16 *) CYREG_CACHE_CC_CTL )
     #define CY_CACHE_CONTROL_PTR        (  (reg16 *) CYREG_CACHE_CC_CTL )
 
+    /* System tick registers */
+    #define CY_SYS_SYST_CSR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+    #define CY_SYS_SYST_CSR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+    #define CY_SYS_SYST_RVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+    #define CY_SYS_SYST_RVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+    #define CY_SYS_SYST_CVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+    #define CY_SYS_SYST_CVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+    #define CY_SYS_SYST_CALIB_REG       (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+    #define CY_SYS_SYST_CALIB_PTR       ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
 #elif (CY_PSOC3)
 
     /* Interrupt Address Vector registers */
     #define CY_INT_VECT_TABLE           ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
 
-    /* Interrrupt Controller Priority Registers */
+    /* Interrupt Controller Priority Registers */
     #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_INTC_PRIOR0)
     #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_INTC_PRIOR0)
 
-    /* Interrrupt Controller Set Enable Registers */
+    /* Interrupt Controller Set Enable Registers */
     #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
     #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
 
@@ -714,7 +768,7 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
     #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
 
-    /* Interrrupt Controller Clear Enable Registers */
+    /* Interrupt Controller Clear Enable Registers */
     #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
     #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
 
@@ -731,11 +785,11 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
 
 
-    /* Interrrupt Controller Set Pend Registers */
+    /* Interrupt Controller Set Pend Registers */
     #define CY_INT_SET_PEND_REG         (* (reg8 *) CYREG_INTC_SET_PD0)
     #define CY_INT_SET_PEND_PTR         (  (reg8 *) CYREG_INTC_SET_PD0)
 
-    /* Interrrupt Controller Clear Pend Registers */
+    /* Interrupt Controller Clear Pend Registers */
     #define CY_INT_CLR_PEND_REG         (* (reg8 *) CYREG_INTC_CLR_PD0)
     #define CY_INT_CLR_PEND_PTR         (  (reg8 *) CYREG_INTC_CLR_PD0)
 
@@ -753,8 +807,8 @@ void CySetScPumps(uint8 enable) ;
 * Macro Name: CyAssert
 ********************************************************************************
 * Summary:
-*  Macro that evaluates the expression and if it is false (evaluates to 0) then
-*  the processor is halted.
+*  The macro that evaluates the expression and if it is false (evaluates to 0)
+*  then the processor is halted.
 *
 *  This macro is evaluated unless NDEBUG is defined.
 *
@@ -791,7 +845,7 @@ void CySetScPumps(uint8 enable) ;
 #define CY_RESET_GPIO1              (0x80u)
 
 
-/* Interrrupt Controller Configuration and Status Register */
+/* Interrupt Controller Configuration and Status Register */
 #if(CY_PSOC3)
     #define INTERRUPT_CSR               ((reg8 *) CYREG_INTC_CSR_EN)
     #define DISABLE_IRQ_SET             ((uint8)(0x01u << 1u))    /* INTC_CSR_EN */
@@ -844,6 +898,19 @@ void CySetScPumps(uint8 enable) ;
 #define CY_CACHE_CONTROL_FLUSH          (0x0004u)
 #define CY_LIB_RESET_CR2_RESET          (0x01u)
 
+#if(CY_PSOC5)
+    /* System tick API constants */
+    #define CY_SYS_SYST_CSR_ENABLE              ((uint32) (0x01u))
+    #define CY_SYS_SYST_CSR_ENABLE_INT          ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT    ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT     ((uint32) (16u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK      ((uint32) (1u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK       ((uint32) (0u))
+    #define CY_SYS_SYST_RVR_CNT_MASK            ((uint32) (0x00FFFFFFu))
+    #define CY_SYS_SYST_NUM_OF_CALLBACKS        ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
 
 /*******************************************************************************
 * Interrupt API constants
@@ -876,6 +943,20 @@ void CySetScPumps(uint8 enable) ;
 /* Mask to get valid range of system interrupt 0-15 */
 #define CY_INT_SYS_NUMBER_MASK          (0xFu)
 
+#if(CY_PSOC5)
+
+    /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+    #define CY_INT_NMI_IRQN                  ( 2u)      /* Non Maskable Interrupt      */
+    #define CY_INT_HARD_FAULT_IRQN           ( 3u)      /* Hard Fault Interrupt        */
+    #define CY_INT_MEM_MANAGE_IRQN           ( 4u)      /* Memory Management Interrupt */
+    #define CY_INT_BUS_FAULT_IRQN            ( 5u)      /* Bus Fault Interrupt         */
+    #define CY_INT_USAGE_FAULT_IRQN          ( 6u)      /* Usage Fault Interrupt       */
+    #define CY_INT_SVCALL_IRQN               (11u)      /* SV Call Interrupt           */
+    #define CY_INT_DEBUG_MONITOR_IRQN        (12u)      /* Debug Monitor Interrupt     */
+    #define CY_INT_PEND_SV_IRQN              (14u)      /* Pend SV Interrupt           */
+    #define CY_INT_SYSTICK_IRQN              (15u)      /* System Tick Interrupt       */
+
+#endif  /* (CY_PSOC5) */
 
 /*******************************************************************************
 * Interrupt Macros
@@ -1027,18 +1108,26 @@ void CySetScPumps(uint8 enable) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used.
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+
 #define CYGlobalIntEnable       CyGlobalIntEnable
 #define CYGlobalIntDisable      CyGlobalIntDisable
 
 #define cymemset(s,c,n)         memset((s),(c),(n))
 #define cymemcpy(d,s,n)         memcpy((d),(s),(n))
 
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
-*******************************************************************************/
 #define MFGCFG_X32_TR_PTR               (CY_CLK_XTAL32_TR_PTR)
 #define MFGCFG_X32_TR                   (CY_CLK_XTAL32_TR_REG)
 #define SLOWCLK_X32_TST_PTR             (CY_CLK_XTAL32_TST_PTR)
@@ -1123,10 +1212,6 @@ void CySetScPumps(uint8 enable) ;
 #define CY_VD_PRESISTENT_STATUS_PTR    (CY_VD_PERSISTENT_STATUS_PTR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20
-*******************************************************************************/
-
 #if(CY_PSOC5)
 
     #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
@@ -1153,9 +1238,7 @@ void CySetScPumps(uint8 enable) ;
 #endif  /* (CY_PSOC5) */
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
-*******************************************************************************/
+
 #define BUS_AMASK_CLEAR                 (0xF0u)
 #define BUS_DMASK_CLEAR                 (0x00u)
 #define CLKDIST_LD_LOAD_SET             (0x01u)
@@ -1190,9 +1273,6 @@ void CySetScPumps(uint8 enable) ;
 #define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
-*******************************************************************************/
 #define IMO_PM_ENABLE                   (0x10u)
 #define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
 #define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c
index 0d2b9302..21811611 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the System Performance Component.
@@ -8,7 +8,7 @@
 *   application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -231,6 +231,11 @@ cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], u
 * Summary:
 *  Loads a row of data into the row latch of a Flash/EEPROM array.
 *
+*  The buffer pointer should point to the data that should be written to the
+*  flash row directly (no data in ECC/flash will be preserved). It is Flash API
+*  responsibility to prepare data: the preserved data are copied from flash into
+*  array with the modified data.
+*
 * Parameters:
 *  uint8 array:
 *   Id of the array.
@@ -286,6 +291,149 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+*  Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+*  The only data that are going to be changed should be passed. The function
+*  will handle unmodified data preservation based on DWR settings and input
+*  parameters.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 row:
+*   Flash row number to be loaded.
+*
+*  uint8* buffer:
+*   Data to be loaded to the row latch
+*
+*  uint8 size:
+*   The number of data bytes that the SPC expects to be written. Depends on the
+*   type of the array and, if the array is Flash, whether ECC is being enabled
+*   or not. There are following values: flash row latch size with ECC enabled,
+*   flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+    cystatus status = CYRET_STARTED;
+    uint16 i;
+
+    #if (CYDEV_ECC_ENABLE == 0)
+        uint32 offset;
+    #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+            * Data in ECC" DWR options are disabled, ECC section is available
+            * for user data.
+            *******************************************************************/
+            #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+                /*******************************************************************
+                * If size parameter equals size of the ECC row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the ECC section.
+                * In this case flash data must be preserved. The flash data copied
+                * from flash data section to the SPC data register.
+                *******************************************************************/
+                if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_FLS_BASE +
+                             ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+                             ((uint32)   row * CYDEV_FLS_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+            for(i = 0u; i < size; i++)
+            {
+                CY_SPC_CPU_DATA_REG = buffer[i];
+            }
+
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+            * ECC section can be used for storing device configuration data
+            * ("Store Configuration Data in ECC" DWR option is enabled) or for
+            * storing user data in the ECC section ("Store Configuration Data in
+            * ECC" DWR option is enabled). In both cases, the data in the ECC
+            * section must be preserved if flash data is written.
+            *******************************************************************/
+            #if (CYDEV_ECC_ENABLE == 0)
+
+
+                /*******************************************************************
+                * If size parameter equals size of the flash row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the flash data
+                * section. In this case, ECC section data must be preserved.
+                * The ECC section data copied from ECC section to the SPC data
+                * register.
+                *******************************************************************/
+                if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_ECC_BASE +
+                            ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+                            ((uint32) row   * CYDEV_ECC_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #else
+
+                if(0u != row)
+                {
+                    /* To remove unreferenced local variable warning */
+                }
+
+            #endif /* (CYDEV_ECC_ENABLE == 0) */
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySpcWriteRow
 ********************************************************************************
@@ -551,4 +699,38 @@ void CySpcUnlock(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+*  Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
 /* [] END OF FILE */
+
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h
index 6a5828c5..36f764ef 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides definitions for the System Performance Component API.
@@ -8,7 +8,7 @@
 *  application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,10 +37,13 @@ uint8    CySpcReadData(uint8 buffer[], uint8 size);
 cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
 ;
 cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
 cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
 ;
 cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
 cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
 cystatus CySpcLock(void);
 void     CySpcUnlock(void);
 
@@ -69,7 +72,7 @@ void     CySpcUnlock(void);
 #define CY_SPC_STATUS_CODE_MASK             (0xFCu)
 #define CY_SPC_STATUS_CODE_SHIFT            (0x02u)
 
-/* Status codes for the SPC. */
+/* Status codes for SPC. */
 #define CY_SPC_STATUS_SUCCESS               (0x00u)   /* Operation Successful */
 #define CY_SPC_STATUS_INVALID_ARRAY_ID      (0x01u)   /* Invalid Array ID for given command */
 #define CY_SPC_STATUS_INVALID_2BYTEKEY      (0x02u)   /* Invalid 2-byte key */
@@ -137,7 +140,18 @@ void     CySpcUnlock(void);
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define FIRST_FLASH_ARRAYID         (CY_SPC_FIRST_FLASH_ARRAYID)
 #define LAST_FLASH_ARRAYID          (CY_SPC_LAST_FLASH_ARRAYID)
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
index 740ea099..7b232529 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_DBx.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,23 +25,23 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_DBx_0		SCSI_Out_DBx__0__PC
-#define SCSI_Out_DBx_1		SCSI_Out_DBx__1__PC
-#define SCSI_Out_DBx_2		SCSI_Out_DBx__2__PC
-#define SCSI_Out_DBx_3		SCSI_Out_DBx__3__PC
-#define SCSI_Out_DBx_4		SCSI_Out_DBx__4__PC
-#define SCSI_Out_DBx_5		SCSI_Out_DBx__5__PC
-#define SCSI_Out_DBx_6		SCSI_Out_DBx__6__PC
-#define SCSI_Out_DBx_7		SCSI_Out_DBx__7__PC
-
-#define SCSI_Out_DBx_DB0		SCSI_Out_DBx__DB0__PC
-#define SCSI_Out_DBx_DB1		SCSI_Out_DBx__DB1__PC
-#define SCSI_Out_DBx_DB2		SCSI_Out_DBx__DB2__PC
-#define SCSI_Out_DBx_DB3		SCSI_Out_DBx__DB3__PC
-#define SCSI_Out_DBx_DB4		SCSI_Out_DBx__DB4__PC
-#define SCSI_Out_DBx_DB5		SCSI_Out_DBx__DB5__PC
-#define SCSI_Out_DBx_DB6		SCSI_Out_DBx__DB6__PC
-#define SCSI_Out_DBx_DB7		SCSI_Out_DBx__DB7__PC
+#define SCSI_Out_DBx_0		(SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1		(SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2		(SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3		(SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4		(SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5		(SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6		(SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7		(SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0		(SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1		(SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2		(SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3		(SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4		(SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5		(SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6		(SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7		(SCSI_Out_DBx__DB7__PC)
 
 #endif /* End Pins SCSI_Out_DBx_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
index e8aa91f9..fca70c86 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,27 +25,27 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_0		SCSI_Out__0__PC
-#define SCSI_Out_1		SCSI_Out__1__PC
-#define SCSI_Out_2		SCSI_Out__2__PC
-#define SCSI_Out_3		SCSI_Out__3__PC
-#define SCSI_Out_4		SCSI_Out__4__PC
-#define SCSI_Out_5		SCSI_Out__5__PC
-#define SCSI_Out_6		SCSI_Out__6__PC
-#define SCSI_Out_7		SCSI_Out__7__PC
-#define SCSI_Out_8		SCSI_Out__8__PC
-#define SCSI_Out_9		SCSI_Out__9__PC
-
-#define SCSI_Out_DBP_raw		SCSI_Out__DBP_raw__PC
-#define SCSI_Out_ATN		SCSI_Out__ATN__PC
-#define SCSI_Out_BSY		SCSI_Out__BSY__PC
-#define SCSI_Out_ACK		SCSI_Out__ACK__PC
-#define SCSI_Out_RST		SCSI_Out__RST__PC
-#define SCSI_Out_MSG		SCSI_Out__MSG__PC
-#define SCSI_Out_SEL		SCSI_Out__SEL__PC
-#define SCSI_Out_CD		SCSI_Out__CD__PC
-#define SCSI_Out_REQ		SCSI_Out__REQ__PC
-#define SCSI_Out_IO_raw		SCSI_Out__IO_raw__PC
+#define SCSI_Out_0		(SCSI_Out__0__PC)
+#define SCSI_Out_1		(SCSI_Out__1__PC)
+#define SCSI_Out_2		(SCSI_Out__2__PC)
+#define SCSI_Out_3		(SCSI_Out__3__PC)
+#define SCSI_Out_4		(SCSI_Out__4__PC)
+#define SCSI_Out_5		(SCSI_Out__5__PC)
+#define SCSI_Out_6		(SCSI_Out__6__PC)
+#define SCSI_Out_7		(SCSI_Out__7__PC)
+#define SCSI_Out_8		(SCSI_Out__8__PC)
+#define SCSI_Out_9		(SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw		(SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN		(SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY		(SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK		(SCSI_Out__ACK__PC)
+#define SCSI_Out_RST		(SCSI_Out__RST__PC)
+#define SCSI_Out_MSG		(SCSI_Out__MSG__PC)
+#define SCSI_Out_SEL		(SCSI_Out__SEL__PC)
+#define SCSI_Out_CD		(SCSI_Out__CD__PC)
+#define SCSI_Out_REQ		(SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw		(SCSI_Out__IO_raw__PC)
 
 #endif /* End Pins SCSI_Out_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c
index a5aa27ee..7c54d5b7 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_PULLUP.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_PULLUP_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_PULLUP_DM_STRONG     Strong Drive 
+*  SD_PULLUP_DM_OD_HI      Open Drain, Drives High 
+*  SD_PULLUP_DM_OD_LO      Open Drain, Drives Low 
+*  SD_PULLUP_DM_RES_UP     Resistive Pull Up 
+*  SD_PULLUP_DM_RES_DWN    Resistive Pull Down 
+*  SD_PULLUP_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_PULLUP_DM_DIG_HIZ    High Impedance Digital 
+*  SD_PULLUP_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h
index 07394f01..cf13ee94 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_PULLUP.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h
index bf8bd1df..2a5b9bb4 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_PULLUP.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,11 +25,11 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_PULLUP_0		SD_PULLUP__0__PC
-#define SD_PULLUP_1		SD_PULLUP__1__PC
-#define SD_PULLUP_2		SD_PULLUP__2__PC
-#define SD_PULLUP_3		SD_PULLUP__3__PC
-#define SD_PULLUP_4		SD_PULLUP__4__PC
+#define SD_PULLUP_0		(SD_PULLUP__0__PC)
+#define SD_PULLUP_1		(SD_PULLUP__1__PC)
+#define SD_PULLUP_2		(SD_PULLUP__2__PC)
+#define SD_PULLUP_3		(SD_PULLUP__3__PC)
+#define SD_PULLUP_4		(SD_PULLUP__4__PC)
 
 #endif /* End Pins SD_PULLUP_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c
index 081e687e..7ebd294a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  API for USBFS Component.
@@ -11,7 +11,7 @@
 *  registers are indexed by variations of epNumber - 1.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -23,28 +23,33 @@
 #include "USBFS_hid.h"
 #if(USBFS_DMA1_REMOVE == 0u)
     #include "USBFS_ep1_dma.h"
-#endif   /* End USBFS_DMA1_REMOVE */
+#endif   /*  USBFS_DMA1_REMOVE */
 #if(USBFS_DMA2_REMOVE == 0u)
     #include "USBFS_ep2_dma.h"
-#endif   /* End USBFS_DMA2_REMOVE */
+#endif   /*  USBFS_DMA2_REMOVE */
 #if(USBFS_DMA3_REMOVE == 0u)
     #include "USBFS_ep3_dma.h"
-#endif   /* End USBFS_DMA3_REMOVE */
+#endif   /*  USBFS_DMA3_REMOVE */
 #if(USBFS_DMA4_REMOVE == 0u)
     #include "USBFS_ep4_dma.h"
-#endif   /* End USBFS_DMA4_REMOVE */
+#endif   /*  USBFS_DMA4_REMOVE */
 #if(USBFS_DMA5_REMOVE == 0u)
     #include "USBFS_ep5_dma.h"
-#endif   /* End USBFS_DMA5_REMOVE */
+#endif   /*  USBFS_DMA5_REMOVE */
 #if(USBFS_DMA6_REMOVE == 0u)
     #include "USBFS_ep6_dma.h"
-#endif   /* End USBFS_DMA6_REMOVE */
+#endif   /*  USBFS_DMA6_REMOVE */
 #if(USBFS_DMA7_REMOVE == 0u)
     #include "USBFS_ep7_dma.h"
-#endif   /* End USBFS_DMA7_REMOVE */
+#endif   /*  USBFS_DMA7_REMOVE */
 #if(USBFS_DMA8_REMOVE == 0u)
     #include "USBFS_ep8_dma.h"
-#endif   /* End USBFS_DMA8_REMOVE */
+#endif   /*  USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP_DMA_Done_isr.h"
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /***************************************
@@ -55,7 +60,25 @@ uint8 USBFS_initVar = 0u;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     uint8 USBFS_DmaChan[USBFS_MAX_EP];
     uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+    uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+    {   0u,
+        USBFS_ep1_TD_TERMOUT_EN,
+        USBFS_ep2_TD_TERMOUT_EN,
+        USBFS_ep3_TD_TERMOUT_EN,
+        USBFS_ep4_TD_TERMOUT_EN,
+        USBFS_ep5_TD_TERMOUT_EN,
+        USBFS_ep6_TD_TERMOUT_EN,
+        USBFS_ep7_TD_TERMOUT_EN,
+        USBFS_ep8_TD_TERMOUT_EN
+    };
+    volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -137,7 +160,7 @@ void USBFS_Init(void)
     uint8 enableInterrupts;
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         uint16 i;
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     enableInterrupts = CyEnterCriticalSection();
 
@@ -190,8 +213,11 @@ void USBFS_Init(void)
         for (i = 0u; i < USBFS_MAX_EP; i++)
         {
             USBFS_DmaTd[i] = DMA_INVALID_TD;
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
         }
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     CyExitCriticalSection(enableInterrupts);
 
@@ -204,7 +230,7 @@ void USBFS_Init(void)
     #if(USBFS_SOF_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_SOF_VECT_NUM,   &USBFS_SOF_ISR);
         CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
-    #endif   /* End USBFS_SOF_ISR_REMOVE */
+    #endif   /*  USBFS_SOF_ISR_REMOVE */
 
     /* Set the Control Endpoint Interrupt. */
     (void) CyIntSetVector(USBFS_EP_0_VECT_NUM,   &USBFS_EP_0_ISR);
@@ -214,55 +240,55 @@ void USBFS_Init(void)
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_1_VECT_NUM,   &USBFS_EP_1_ISR);
         CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
 
     /* Set the Data Endpoint 2 Interrupt. */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_2_VECT_NUM,   &USBFS_EP_2_ISR);
         CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
 
     /* Set the Data Endpoint 3 Interrupt. */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_3_VECT_NUM,   &USBFS_EP_3_ISR);
         CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
 
     /* Set the Data Endpoint 4 Interrupt. */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_4_VECT_NUM,   &USBFS_EP_4_ISR);
         CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
 
     /* Set the Data Endpoint 5 Interrupt. */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_5_VECT_NUM,   &USBFS_EP_5_ISR);
         CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
 
     /* Set the Data Endpoint 6 Interrupt. */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_6_VECT_NUM,   &USBFS_EP_6_ISR);
         CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
 
      /* Set the Data Endpoint 7 Interrupt. */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_7_VECT_NUM,   &USBFS_EP_7_ISR);
         CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
 
     /* Set the Data Endpoint 8 Interrupt. */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_8_VECT_NUM,   &USBFS_EP_8_ISR);
         CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* Set the ARB Interrupt. */
         (void) CyIntSetVector(USBFS_ARB_VECT_NUM,   &USBFS_ARB_ISR);
         CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
 }
 
@@ -339,45 +365,50 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
     CyIntEnable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* usb arb interrupt enable */
         USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
         CyIntEnable(USBFS_ARB_VECT_NUM);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Arbiter configuration for DMA transfers */
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /*Set cfg cmplt this rises DMA request when the full configuration is done */
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+                /* Init interrupt which handles verification of the successful DMA transaction */
+                USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+                USBFS_EP17_DMA_Done_SR_InterruptEnable();
+                USBFS_EP8_DMA_Done_SR_InterruptEnable();
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     USBFS_transferState = USBFS_TRANS_STATE_IDLE;
 
@@ -395,7 +426,7 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
             #else
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
-            #endif /* End USBFS_VDDD_MV < USBFS_3500MV */
+            #endif /*  USBFS_VDDD_MV < USBFS_3500MV */
             break;
     }
 
@@ -535,7 +566,7 @@ void USBFS_Stop(void)
 
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Disable the SIE */
     USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
@@ -551,28 +582,28 @@ void USBFS_Stop(void)
     CyIntDisable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     /* Clear all of the component data */
     USBFS_configuration = 0u;
@@ -768,7 +799,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
     *  No.
     *
     *******************************************************************************/
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                                     
     {
         uint16 src;
@@ -788,56 +819,56 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 src = HI16(CYDEV_PERIPH_BASE);
                 dst = HI16(pData);
             }
-        #endif  /* End C51 */
+        #endif  /*  C51 */
         switch(epNumber)
         {
             case USBFS_EP1:
                 #if(USBFS_DMA1_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA1_REMOVE */
+                #endif   /*  USBFS_DMA1_REMOVE */
                 break;
             case USBFS_EP2:
                 #if(USBFS_DMA2_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA2_REMOVE */
+                #endif   /*  USBFS_DMA2_REMOVE */
                 break;
             case USBFS_EP3:
                 #if(USBFS_DMA3_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA3_REMOVE */
+                #endif   /*  USBFS_DMA3_REMOVE */
                 break;
             case USBFS_EP4:
                 #if(USBFS_DMA4_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA4_REMOVE */
+                #endif   /*  USBFS_DMA4_REMOVE */
                 break;
             case USBFS_EP5:
                 #if(USBFS_DMA5_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA5_REMOVE */
+                #endif   /*  USBFS_DMA5_REMOVE */
                 break;
             case USBFS_EP6:
                 #if(USBFS_DMA6_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA6_REMOVE */
+                #endif   /*  USBFS_DMA6_REMOVE */
                 break;
             case USBFS_EP7:
                 #if(USBFS_DMA7_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA7_REMOVE */
+                #endif   /*  USBFS_DMA7_REMOVE */
                 break;
             case USBFS_EP8:
                 #if(USBFS_DMA8_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA8_REMOVE */
+                #endif   /*  USBFS_DMA8_REMOVE */
                 break;
             default:
                 /* Do not support EP0 DMA transfers */
@@ -846,6 +877,10 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
         if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
         {
             USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+            #endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
         }
     }
 
@@ -879,11 +914,74 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 CyDmaTdFree(USBFS_DmaTd[i]);
                 USBFS_DmaTd[i] = DMA_INVALID_TD;
             }
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+                {
+                    CyDmaTdFree(USBFS_DmaNextTd[i]);
+                    USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+                }
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
             i++;
         }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
     }
 
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_LoadNextInEP
+    ********************************************************************************
+    *
+    * Summary:
+    *  This internal function is used for IN endpoint DMA reconfiguration in
+    *  Auto DMA mode.
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number.
+    *  mode:   0 - Configure DMA to send the the rest of data.
+    *          1 - Configure DMA to repeat 2 last bytes of the first burst.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) 
+    {
+        reg16 *convert;
+
+        if(mode == 0u)
+        {
+            /* Configure DMA to send the the rest of data */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                            USBFS_DMA_BYTES_PER_BURST));
+            USBFS_inBufFull[epNumber] = 1u;
+        }
+        else
+        {
+            /* Configure DMA to repeat 2 last bytes of the first burst. */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert,  LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                   USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+        }
+
+        /* CyDmaChSetInitialTd API is optimised to init TD */
+        CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -891,8 +989,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
 ********************************************************************************
 *
 * Summary:
-*  Loads and enables the specified USB data endpoint for an IN interrupt or bulk
-*  transfer.
+*  Loads and enables the specified USB data endpoint for an IN transfer.
 *
 * Parameters:
 *  epNumber: Contains the data endpoint number.
@@ -916,7 +1013,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
     {
@@ -929,7 +1026,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             {
                 length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Set the count and data toggle */
         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
@@ -950,15 +1047,15 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
         #else
             /* Init DMA if it was not initialized */
-            if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+            if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-            if((pData != NULL) && (length > 0u))
+            if ((pData != NULL) && (length > 0u))
             {
                 /* Enable DMA in mode2 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
@@ -978,16 +1075,37 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 /* When zero-length packet - write the Mode register directly */
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            if(pData != NULL)
+            if (pData != NULL)
             {
                 /* Enable DMA in mode3 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                USBFS_inLength[epNumber] = length;
+                USBFS_inDataPointer[epNumber] = pData;
+                /* Configure DMA to send the data only for the first burst */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+                    (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+                    USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+                /* The second TD will be executed only when the first one fails.
+                *  The intention of this TD is to generate NRQ interrupt
+                *  and repeat 2 last bytes of the first burst.
+                */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+                                               USBFS_DmaNextTd[epNumber],
+                                               USBFS_epX_TD_TERMOUT_EN[epNumber]);
+                /* Configure DmaNextTd to clear Data ready status */
+                (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber],  LO16((uint32)&clearInDataRdyStatus),
+                                                                LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+            #else /* Configure DMA to send all data*/
                 (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
                                                USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
                 (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
                 /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
                 (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
                 /* Enable the DMA */
@@ -999,8 +1117,28 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
                 if(length > 0u)
                 {
+                #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                    USBFS_inLength[epNumber] = length;
+                    USBFS_inBufFull[epNumber] = 0u;
+                    (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+                    /* Configure DMA to send the data only for the first burst */
+                    (void) CyDmaTdSetConfiguration(
+                        USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+                        USBFS_DMA_BYTES_PER_BURST : length,
+                        USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+                    (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+                                             LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+                    /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+                    (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+                    /* Enable the DMA */
+                    (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                    (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+                #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
                     /* Set Data ready status, This will generate DMA request */
-                    * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #ifndef USBFS_MANUAL_IN_EP_ARM
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #endif  /* USBFS_MANUAL_IN_EP_ARM */
                     /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
                 }
                 else
@@ -1009,8 +1147,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                     CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
                 }
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
     }
 }
 
@@ -1047,10 +1184,10 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 xferCount;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
     {
@@ -1064,7 +1201,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 length = xferCount;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         #if(USBFS_EP_MM == USBFS__EP_MANUAL)
             /* Copy the data using the arbiter data register */
@@ -1081,7 +1218,8 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             /* Enable DMA in mode2 for transferring data */
@@ -1097,7 +1235,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /* Enable DMA in mode3 for transferring data */
@@ -1112,7 +1250,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
             (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     }
     else
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h
index e7fd8992..be2eca86 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: USBFS.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,6 +20,11 @@
 #include "cyfitter.h"
 #include "CyLib.h"
 
+/*  User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
 
 /***************************************
 * Conditional Compilation Parameters
@@ -28,7 +33,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component USBFS_v2_60 requires cy_boot v3.0 or later
+    #error Component USBFS_v2_80 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -47,7 +52,7 @@
 #else
     #define USBFS_DATA
     #define USBFS_XDATA
-#endif /* End __C51__ */
+#endif /*  __C51__ */
 #define USBFS_NULL       NULL
 
 
@@ -98,6 +103,7 @@
 #define USBFS_EP8_ISR_REMOVE                 (1u)
 #define USBFS_EP_MM                          (0u)
 #define USBFS_EP_MA                          (0u)
+#define USBFS_EP_DMA_AUTO_OPT                (0u)
 #define USBFS_DMA1_REMOVE                    (1u)
 #define USBFS_DMA2_REMOVE                    (1u)
 #define USBFS_DMA3_REMOVE                    (1u)
@@ -219,7 +225,7 @@ void   USBFS_Resume(void) ;
 #endif  /* USBFS_ENABLE_FWSN_STRING */
 #if (USBFS_MON_VBUS == 1u)
     uint8  USBFS_VBusPresent(void) ;
-#endif /* End USBFS_MON_VBUS */
+#endif /*  USBFS_MON_VBUS */
 
 #if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
@@ -227,19 +233,24 @@ void   USBFS_Resume(void) ;
     void USBFS_CyBtldrCommStart(void) ;
     void USBFS_CyBtldrCommStop(void) ;
     void USBFS_CyBtldrCommReset(void) ;
-    cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
-    cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommRead       (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
 
-    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER      (64u)    /* EP 1 OUT */
-    #define USBFS_BTLDR_SIZEOF_READ_BUFFER       (64u)    /* EP 2 IN */
-    #define USBFS_BTLDR_MAX_PACKET_SIZE          USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+    #define USBFS_BTLDR_OUT_EP      (0x01u)
+    #define USBFS_BTLDR_IN_EP       (0x02u)
+
+    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER  (64u)   /* EP 1 OUT */
+    #define USBFS_BTLDR_SIZEOF_READ_BUFFER   (64u)   /* EP 2 IN  */
+    #define USBFS_BTLDR_MAX_PACKET_SIZE      USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+    #define USBFS_BTLDR_WAIT_1_MS            (1u)    /* Time Out quantity equal 1mS */
 
     /* These defines active if used USBFS interface as an
     *  IO Component for bootloading. When Custom_Interface selected
     *  in Bootloder configuration as the IO Component, user must
-    *  provide these functions
+    *  provide these functions.
     */
     #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
         #define CyBtldrCommStart        USBFS_CyBtldrCommStart
@@ -249,13 +260,13 @@ void   USBFS_Resume(void) ;
         #define CyBtldrCommRead         USBFS_CyBtldrCommRead
     #endif  /*End   CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP  */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP  */
 
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                     ;
     void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL) */
 
 #if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
     void USBFS_MIDI_EP_Init(void) ;
@@ -270,7 +281,7 @@ void   USBFS_Resume(void) ;
         void USBFS_MIDI_OUT_EP_Service(void) ;
     #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
 
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */
+#endif /*  USBFS_ENABLE_MIDI_API != 0u */
 
 /* Renamed Functions for backward compatibility.
 *  Should not be used in new designs.
@@ -483,10 +494,10 @@ void   USBFS_Resume(void) ;
 #define USBFS_EP_USAGE_TYPE_RESERVED         (0x30u)
 #define USBFS_EP_USAGE_TYPE_MASK             (0x30u)
 
-/* Endpoint Status defines */
+/* point Status defines */
 #define USBFS_EP_STATUS_LENGTH               (0x02u)
 
-/* Endpoint Device defines */
+/* point Device defines */
 #define USBFS_DEVICE_STATUS_LENGTH           (0x02u)
 
 #define USBFS_STATUS_LENGTH_MAX \
@@ -513,14 +524,60 @@ void   USBFS_Resume(void) ;
     /* DMA manual mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (0u)
     #define USBFS_DMA_REQUEST_PER_BURST      (0u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
     /* DMA automatic mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (32u)
+    #define USBFS_DMA_BYTES_REPEAT           (2u)
     /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes  44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
     #define USBFS_DMA_BUF_SIZE               (0x55u)
     #define USBFS_DMA_REQUEST_PER_BURST      (1u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+    #if(USBFS_DMA1_REMOVE == 0u)
+        #define USBFS_ep1_TD_TERMOUT_EN      USBFS_ep1__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep1_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA1_REMOVE == 0u */
+    #if(USBFS_DMA2_REMOVE == 0u)
+        #define USBFS_ep2_TD_TERMOUT_EN      USBFS_ep2__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep2_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA2_REMOVE == 0u */
+    #if(USBFS_DMA3_REMOVE == 0u)
+        #define USBFS_ep3_TD_TERMOUT_EN      USBFS_ep3__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep3_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA3_REMOVE == 0u */
+    #if(USBFS_DMA4_REMOVE == 0u)
+        #define USBFS_ep4_TD_TERMOUT_EN      USBFS_ep4__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep4_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA4_REMOVE == 0u */
+    #if(USBFS_DMA5_REMOVE == 0u)
+        #define USBFS_ep5_TD_TERMOUT_EN      USBFS_ep5__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep5_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA5_REMOVE == 0u */
+    #if(USBFS_DMA6_REMOVE == 0u)
+        #define USBFS_ep6_TD_TERMOUT_EN      USBFS_ep6__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep6_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA6_REMOVE == 0u */
+    #if(USBFS_DMA7_REMOVE == 0u)
+        #define USBFS_ep7_TD_TERMOUT_EN      USBFS_ep7__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep7_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA7_REMOVE == 0u */
+    #if(USBFS_DMA8_REMOVE == 0u)
+        #define USBFS_ep8_TD_TERMOUT_EN      USBFS_ep8__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep8_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA8_REMOVE == 0u */
+
+    #define     USBFS_EP17_SR_MASK           (0x7fu)
+    #define     USBFS_EP8_SR_MASK            (0x03u)
+
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
 /* DIE ID string descriptor defines */
 #if defined(USBFS_ENABLE_IDSN_STRING)
@@ -805,7 +862,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #if(!CY_PSOC5LP)
     #define USBFS_USBIO_CR2_PTR      (  (reg8 *) USBFS_USB__USBIO_CR2)
     #define USBFS_USBIO_CR2_REG      (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /* End CY_PSOC5LP */
+#endif /*  CY_PSOC5LP */
 
 #define USBFS_DIE_ID             CYDEV_FLSHID_CUST_TABLES_BASE
 
@@ -831,8 +888,8 @@ extern volatile uint8 USBFS_deviceStatus;
     #else
         #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
         #define USBFS_VBUS_MASK          (0x01u)
-    #endif /* End USBFS_EXTERN_VBUS == 0u */
-#endif /* End USBFS_MON_VBUS */
+    #endif /*  USBFS_EXTERN_VBUS == 0u */
+#endif /*  USBFS_MON_VBUS */
 
 /* Renamed Registers for backward compatibility.
 *  Should not be used in new designs.
@@ -1010,7 +1067,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
     #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
     #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /* End CYDEV_CHIP_DIE_EXPECT */
+#endif /*  CYDEV_CHIP_DIE_EXPECT */
 
 
 /***************************************
@@ -1131,6 +1188,8 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_ARB_EPX_CFG_CRC_BYPASS     (0x04u)
 #define USBFS_ARB_EPX_CFG_DMA_REQ        (0x02u)
 #define USBFS_ARB_EPX_CFG_IN_DATA_RDY    (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT        (USBFS_ARB_EPX_CFG_RESET | \
+                                                     USBFS_ARB_EPX_CFG_CRC_BYPASS)
 
 #define USBFS_ARB_EPX_SR_IN_BUF_FULL     (0x01u)
 #define USBFS_ARB_EPX_SR_DMA_GNT         (0x02u)
@@ -1146,7 +1205,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_ARB_EPX_INT_MASK           (0x1Du)
 #else
     #define USBFS_ARB_EPX_INT_MASK           (0x1Fu)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 #define USBFS_ARB_INT_MASK       (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
                                             (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
                                             (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
@@ -1183,7 +1242,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_DYN_RECONFIG_RDY_STS       (0x10u)
 
 
-#endif /* End CY_USBFS_USBFS_H */
+#endif /*  CY_USBFS_USBFS_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
index afae8fad..6bb45afa 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dm_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dm_DM_STRONG     Strong Drive 
+*  USBFS_Dm_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dm_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dm_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dm_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dm_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dm_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dm_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
index c1aa9b99..5166935a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
index bc4f686d..faf08704 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dm_0		USBFS_Dm__0__PC
+#define USBFS_Dm_0		(USBFS_Dm__0__PC)
 
 #endif /* End Pins USBFS_Dm_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
index 304d5d61..7121119d 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dp_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dp_DM_STRONG     Strong Drive 
+*  USBFS_Dp_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dp_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dp_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dp_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dp_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dp_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dp_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
index 2d03ad93..fb0a19c0 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
index b77c3b9a..5268950d 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dp_0		USBFS_Dp__0__PC
+#define USBFS_Dp_0		(USBFS_Dp__0__PC)
 
 #endif /* End Pins USBFS_Dp_ALIASES_H */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c
index cec388be..2cd1304a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB AUDIO Class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,9 +21,9 @@
 
 #include "USBFS_audio.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -52,7 +53,7 @@
                                                                                   USBFS_VOL_MAX_MSB};
     volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,
                                                                                      USBFS_VOL_RES_MSB};
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+#endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
 
 /*******************************************************************************
@@ -93,17 +94,18 @@
 uint8 USBFS_DispatchAUDIOClassRqst(void) 
 {
     uint8 requestHandled = USBFS_FALSE;
+    uint8 bmRequestType  = CY_GET_REG8(USBFS_bmRequestType);
 
     #if defined(USBFS_ENABLE_AUDIO_STREAMING)
         uint8 epNumber;
         epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;
-    #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+    #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
-    if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
+
+    if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
     {
         /* Control Read */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
             /* Endpoint */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -112,12 +114,12 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlRead();
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_READ_REQUESTS` Place other request handler here */
 
@@ -127,8 +129,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -140,7 +141,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */
 
                         /* `#END` */
-                        
+
                          /* Entity ID Control Selector is MUTE */
                         USBFS_currentTD.wCount = 1u;
                         USBFS_currentTD.pData  = &USBFS_currentMute;
@@ -199,7 +200,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         USBFS_currentTD.wCount = 0u;
                         requestHandled   = USBFS_InitControlWrite();
 
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
 
@@ -213,27 +214,25 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
         {   /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \
-                                                                                    USBFS_RQST_DIR_H2D)
+    else
     {
         /* Control Write */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
-            /* Endpoint */
+            /* point */
             switch (CY_GET_REG8(USBFS_bRequest))
             {
                 case USBFS_SET_CUR:
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlWrite();
                         USBFS_frequencyChanged = epNumber;
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
 
@@ -243,8 +242,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -279,7 +277,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
                         /* `#END` */
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
 
@@ -290,17 +288,14 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
             }
         }
         else
-        {   /* USBFS_RQST_RCPT_OTHER */
+        {
+            /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else
-    {   /* requestHandled is initialized as FALSE by default */
-    }
 
     return(requestHandled);
 }
 
-
 #endif /* USER_SUPPLIED_AUDIO_HANDLER */
 
 
@@ -312,7 +307,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_AUDIO_CLASS*/
+#endif  /*  USBFS_ENABLE_AUDIO_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h
index 1e6186bf..0cae2dc9 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -45,7 +48,7 @@
 #define USBFS_GET_MEM                    (0x85u)
 #define USBFS_GET_STAT                   (0xFFu)
 
-/* Endpoint Control Selectors (AUDIO Table A-19) */
+/* point Control Selectors (AUDIO Table A-19) */
 #define USBFS_EP_CONTROL_UNDEFINED       (0x00u)
 #define USBFS_SAMPLING_FREQ_CONTROL      (0x01u)
 #define USBFS_PITCH_CONTROL              (0x02u)
@@ -89,7 +92,7 @@ extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];
 
-#endif /* End CY_USBFS_USBFS_audio_H */
+#endif /*  CY_USBFS_USBFS_audio_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c
index 28430575..75b91270 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_boot.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Boot loader API for USBFS Component.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,23 +20,11 @@
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
 
 
-/***************************************
-*    Bootloader defines
-***************************************/
-
-#define USBFS_CyBtLdrStarttimer(X, T)         {USBFS_universalTime = T * 10; X = 0u;}
-#define USBFS_CyBtLdrChecktimer(X)            ((X++ < USBFS_universalTime) ? 1u : 0u)
-
-#define USBFS_BTLDR_OUT_EP      (0x01u)
-#define USBFS_BTLDR_IN_EP       (0x02u)
-
-
 /***************************************
 *    Bootloader Variables
 ***************************************/
 
-static uint16 USBFS_universalTime;
-static uint8 USBFS_started = 0u;
+static uint8  USBFS_started = 0u;
 
 
 /*******************************************************************************
@@ -68,7 +56,6 @@ void USBFS_CyBtldrCommStart(void)
 
     /* USB component started, the correct enumeration will be checked in first Read operation */
     USBFS_started = 1u;
-
 }
 
 
@@ -100,13 +87,13 @@ void USBFS_CyBtldrCommStop(void)
 *  Resets the receive and transmit communication Buffers.
 *
 * Parameters:
-*  None.
+*  None
 *
 * Return:
-*  None.
+*  None
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
 void USBFS_CyBtldrCommReset(void) 
@@ -135,39 +122,39 @@ void USBFS_CyBtldrCommReset(void)
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    uint16 time;
-    cystatus status;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
     /* Enable IN transfer */
     USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);
 
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
-
     /* Wait for the master to read it. */
-    while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+    while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&
+           (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)
     {
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
     else
     {
         *count = size;
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
 
-    return(status);
+    return(retCode);
 }
 
 
@@ -193,70 +180,77 @@ cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    cystatus status;
-    uint16 time;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
-    if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
+    if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
     {
         size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;
     }
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
 
     /* Wait on enumeration in first time */
-    if(USBFS_started)
+    if (0u != USBFS_started)
     {
         /* Wait for Device to enumerate */
-        while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))
+        while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))
         {
-            CyDelay(1u); /* 1ms delay */
+            CyDelay(USBFS_BTLDR_WAIT_1_MS);
+            timeoutMs--;
         }
+
         /* Enable first OUT, if enumeration complete */
-        if(USBFS_GetConfiguration())
+        if (0u != USBFS_GetConfiguration())
         {
-            USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
+            (void) USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
             USBFS_CyBtldrCommReset();
             USBFS_started = 0u;
         }
     }
     else /* Check for configuration changes, has been done by Host */
     {
-        if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */
+        if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */
         {
-            if(USBFS_GetConfiguration() != 0u)   /* Init OUT endpoints when device reconfigured */
+            if (0u != USBFS_GetConfiguration())   /* Init OUT endpoints when device reconfigured */
             {
                 USBFS_CyBtldrCommReset();
             }
         }
     }
+
+    timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */
+
     /* Wait on next packet */
     while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+          (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     /* OUT EP has completed */
     if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)
     {
         *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
     else
     {
         *count = 0u;
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
-    return(status);
+
+    return(retCode);
 }
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
index 82951c8a..63ebf120 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  USB HID Class request handler.
+*  USB CDC class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
 *
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -26,7 +27,13 @@
 *    CDC Variables
 ***************************************/
 
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =
+{
+    0x00u, 0xC2u, 0x01u, 0x00u,     /* Data terminal rate 115200 */
+    0x00u,                          /* 1 Stop bit */
+    0x00u,                          /* None parity */
+    0x08u                           /* 8 data bits */
+};
 volatile uint8 USBFS_lineChanged;
 volatile uint16 USBFS_lineControlBitmap;
 volatile uint8 USBFS_cdc_data_in_ep;
@@ -36,7 +43,9 @@ volatile uint8 USBFS_cdc_data_out_ep;
 /***************************************
 *     Static Function Prototypes
 ***************************************/
-static uint16 USBFS_StrLen(const char8 string[]) ;
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
+    static uint16 USBFS_StrLen(const char8 string[]) ;
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */
 
 
 /***************************************
@@ -138,7 +147,6 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 ***************************************/
 #if (USBFS_ENABLE_CDC_CLASS_API != 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_CDC_Init
     ********************************************************************************
@@ -173,14 +181,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a specified number of bytes from the location specified by a
-    *  pointer to the PC.
+    *  This function sends a specified number of bytes from the location specified
+    *  by a pointer to the PC. The USBFS_CDCIsReady() function should be
+    *  called before sending new data, to be sure that the previous data has
+    *  finished sending.
+    *  If the last sent packet is less than maximum packet size the USB transfer
+    *  of this short packet will identify the end of the segment. If the last sent
+    *  packet is exactly maximum packet size, it shall be followed by a zero-length
+    *  packet (which is a short packet) to assure the end of segment is properly
+    *  identified. To send zero-length packet, use USBFS_PutData() API
+    *  with length parameter set to zero.
     *
     * Parameters:
     *  pData: pointer to the buffer containing data to be sent.
     *  length: Specifies the number of bytes to send from the pData
     *  buffer. Maximum length will be limited by the maximum packet
-    *  size for the endpoint.
+    *  size for the endpoint. Data will be lost if length is greater than Max
+    *  Packet Size.
     *
     * Return:
     *  None.
@@ -239,10 +256,15 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a null terminated string to the PC.
+    *  This function sends a null terminated string to the PC. This function will
+    *  block if there is not enough memory to place the whole string. It will block
+    *  until the entire string has been written to the transmit buffer.
+    *  The USBUART_CDCIsReady() function should be called before sending data with
+    *  a new call to USBFS_PutString(), to be sure that the previous data
+    *  has finished sending.
     *
     * Parameters:
-    *  string: pointer to the string to be sent to the PC
+    *  string: pointer to the string to be sent to the PC.
     *
     * Return:
     *  None.
@@ -254,41 +276,44 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     * Reentrant:
     *  No.
     *
-    * Theory:
-    *  This function will block if there is not enough memory to place the whole
-    *  string, it will block until the entire string has been written to the
-    *  transmit buffer.
-    *
     *******************************************************************************/
     void USBFS_PutString(const char8 string[]) 
     {
-        uint16 str_length;
-        uint16 send_length;
-        uint16 buf_index = 0u;
+        uint16 strLength;
+        uint16 sendLength;
+        uint16 bufIndex = 0u;
 
         /* Get length of the null terminated string */
-        str_length = USBFS_StrLen(string);
+        strLength = USBFS_StrLen(string);
         do
         {
             /* Limits length to maximum packet size for the EP */
-            send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
-                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;
+            sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
+                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;
              /* Enable IN transfer */
-            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);
-            str_length -= send_length;
+            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);
+            strLength -= sendLength;
 
-            /* If more data are present to send */
-            if(str_length > 0u)
+            /* If more data are present to send or full packet was sent */
+            if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))
             {
-                buf_index += send_length;
+                bufIndex += sendLength;
                 /* Wait for the Host to read it. */
                 while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==
                                           USBFS_IN_BUFFER_FULL)
                 {
                     ;
                 }
+                /* If the last sent packet is exactly maximum packet size,
+                *  it shall be followed by a zero-length packet to assure the
+                *  end of segment is properly identified by the terminal.
+                */
+                if(strLength == 0u)
+                {
+                    USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);
+                }
             }
-        }while(str_length > 0u);
+        }while(strLength > 0u);
     }
 
 
@@ -357,12 +382,17 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  This function returns the number of bytes that were received from the PC.
+    *  The returned length value should be passed to USBFS_GetData() as
+    *  a parameter to read all received data. If all of the received data is not
+    *  read at one time by the USBFS_GetData() API, the unread data will
+    *  be lost.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  Returns the number of received bytes.
+    *  Returns the number of received bytes. The maximum amount of received data at
+    *  a time is limited by the maximum packet size for the endpoint.
     *
     * Global variables:
     *   USBFS_cdc_data_out_ep: CDC OUT endpoint number used.
@@ -370,12 +400,16 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *******************************************************************************/
     uint16 USBFS_GetCount(void) 
     {
-        uint16 bytesCount = 0u;
+        uint16 bytesCount;
 
         if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)
         {
             bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);
         }
+        else
+        {
+            bytesCount = 0u;
+        }
 
         return(bytesCount);
     }
@@ -387,9 +421,9 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  Returns a nonzero value if the component received data or received
-    *  zero-length packet. The GetAll() or GetData() API should be called to read
-    *  data from the buffer and re-init OUT endpoint even when zero-length packet
-    *  received.
+    *  zero-length packet. The USBFS_GetAll() or
+    *  USBFS_GetData() API should be called to read data from the buffer
+    *  and re-init OUT endpoint even when zero-length packet received.
     *
     * Parameters:
     *  None.
@@ -413,17 +447,19 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Returns a nonzero value if the component is ready to send more data to the
-    *  PC. Otherwise returns zero. Should be called before sending new data to
-    *  ensure the previous data has finished sending.This function returns the
-    *  number of bytes that were received from the PC.
+    *  This function returns a nonzero value if the component is ready to send more
+    *  data to the PC; otherwise, it returns zero. The function should be called
+    *  before sending new data when using any of the following APIs:
+    *  USBFS_PutData(),USBFS_PutString(),
+    *  USBFS_PutChar or USBFS_PutCRLF(),
+    *  to be sure that the previous data has finished sending.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If the buffer can accept new data then this function returns a nonzero value.
-    *  Otherwise zero is returned.
+    *  If the buffer can accept new data, this function returns a nonzero value.
+    *  Otherwise, it returns zero.
     *
     * Global variables:
     *   USBFS_cdc_data_in_ep: CDC IN endpoint number used.
@@ -440,10 +476,12 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Gets a specified number of bytes from the input buffer and places it in a
-    *  data array specified by the passed pointer.
-    *  USBFS_DataIsReady() API should be called before, to be sure
-    *  that data is received from the Host.
+    *  This function gets a specified number of bytes from the input buffer and
+    *  places them in a data array specified by the passed pointer.
+    *  The USBFS_DataIsReady() API should be called first, to be sure
+    *  that data is received from the host. If all received data will not be read at
+    *  once, the unread data will be lost. The USBFS_GetData() API should
+    *  be called to get the number of bytes that were received.
     *
     * Parameters:
     *  pData: Pointer to the data array where data will be placed.
@@ -502,7 +540,8 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Reads one byte of received data from the buffer.
+    *  This function reads one byte of received data from the buffer. If more than
+    *  one byte has been received from the host, the rest of the data will be lost.
     *
     * Parameters:
     *  None.
@@ -531,17 +570,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  This function returns clear on read status of the line.
+    *  This function returns clear on read status of the line. It returns not zero
+    *  value when the host sends updated coding or control information to the
+    *  device. The USBFS_GetDTERate(), USBFS_GetCharFormat()
+    *  or USBFS_GetParityType() or USBFS_GetDataBits() API
+    *  should be called to read data coding information.
+    *  The USBFS_GetLineControl() API should be called to read line
+    *  control information.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not
-    *  zero value returned. Otherwise zero is returned.
+    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it
+    *  returns a nonzero value. Otherwise, it returns zero.
     *
     * Global variables:
-    *  USBFS_transferState - it is checked to be sure then OUT data
+    *  USBFS_transferState: it is checked to be sure then OUT data
     *    phase has been complete, and data written to the lineCoding or Control
     *    Bitmap buffer.
     *  USBFS_lineChanged: used as a flag to be aware that Host has been
@@ -689,7 +734,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
         return(USBFS_lineControlBitmap);
     }
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API*/
 
 
 /*******************************************************************************
@@ -700,7 +745,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS*/
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
index 334bc589..11c94d05 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
@@ -1,13 +1,16 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component.
+*  Header File for the USBFS component.
 *  Contains CDC class prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,7 +44,7 @@
     uint8 USBFS_GetParityType(void) ;
     uint8 USBFS_GetDataBits(void) ;
     uint16 USBFS_GetLineControl(void) ;
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API */
 
 
 /***************************************
@@ -86,7 +89,7 @@ extern volatile uint16 USBFS_lineControlBitmap;
 extern volatile uint8 USBFS_cdc_data_in_ep;
 extern volatile uint8 USBFS_cdc_data_out_ep;
 
-#endif /* End CY_USBFS_USBFS_cdc_H */
+#endif /*  CY_USBFS_USBFS_cdc_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
index c3477c28..9bbefb9b 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
@@ -1,12 +1,12 @@
 ;******************************************************************************
 ; File Name: USBFS_cdc.inf
-; Version 2.60
+; Version 2.80
 ;
 ; Description:
 ;  Windows USB CDC setup file for USBUART Device.
 ;
 ;******************************************************************************
-; Copyright 2007-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2007-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c
index 7bbd8d11..a9801ead 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_cls.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Class request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -57,8 +57,8 @@ uint8 USBFS_DispatchClassRqst(void)
             break;
         case USBFS_RQST_RCPT_EP:         /* Class-specific request directed to the endpoint */
             /* Find related interface to the endpoint, wIndexLo contain EP number */
-            interfaceNumber =
-                USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;
+            interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &
+                              USBFS_DIR_UNUSED].interface;
             break;
         default:    /* RequestHandled is initialized as FALSE by default */
             break;
@@ -74,7 +74,7 @@ uint8 USBFS_DispatchClassRqst(void)
         case USBFS_CLASS_AUDIO:
             #if defined(USBFS_ENABLE_AUDIO_CLASS)
                 requestHandled = USBFS_DispatchAUDIOClassRqst();
-            #endif /* USBFS_ENABLE_HID_CLASS */
+            #endif /* USBFS_CLASS_AUDIO */
             break;
         case USBFS_CLASS_CDC:
             #if defined(USBFS_ENABLE_CDC_CLASS)
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
index da144461..9886a40c 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_descr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB descriptors and storage.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,7 @@
 
 /*****************************************************************************
 *  User supplied descriptors.  If you want to specify your own descriptors,
-*  remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and
-*  add your descriptors.
+*  define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.
 *****************************************************************************/
 /* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c
index e78a41b2..282c938d 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_drv.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Endpoint 0 Driver for the USBFS Component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c
index cd88e929..b3cd8e33 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_episr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Data endpoint Interrupt Service Routines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -16,9 +16,13 @@
 
 #include "USBFS.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 
 /***************************************
@@ -48,7 +52,8 @@
     ******************************************************************************/
     CY_ISR(USBFS_EP_1_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT)  && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -56,7 +61,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -72,23 +78,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &
                                                                     (uint8)~USBFS_SIE_EP_INT_EP1_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP1)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP1_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP1_ISR_REMOVE */
+#endif   /*  USBFS_EP1_ISR_REMOVE */
 
 
 #if(USBFS_EP2_ISR_REMOVE == 0u)
@@ -109,7 +117,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_2_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -117,7 +126,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -133,23 +143,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP2_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP2)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP2_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP2_ISR_REMOVE */
+#endif   /*  USBFS_EP2_ISR_REMOVE */
 
 
 #if(USBFS_EP3_ISR_REMOVE == 0u)
@@ -170,7 +182,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_3_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -178,7 +191,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -194,23 +208,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP3_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP3)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP3_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP3_ISR_REMOVE */
+#endif   /*  USBFS_EP3_ISR_REMOVE */
 
 
 #if(USBFS_EP4_ISR_REMOVE == 0u)
@@ -231,7 +247,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_4_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -239,7 +256,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -255,23 +273,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP4_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP4)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP4_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP4_ISR_REMOVE */
+#endif   /*  USBFS_EP4_ISR_REMOVE */
 
 
 #if(USBFS_EP5_ISR_REMOVE == 0u)
@@ -292,7 +312,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_5_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -300,7 +321,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -316,22 +338,24 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP5_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP5)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP5_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
-#endif   /* End USBFS_EP5_ISR_REMOVE */
+#endif   /*  USBFS_EP5_ISR_REMOVE */
 
 
 #if(USBFS_EP6_ISR_REMOVE == 0u)
@@ -352,7 +376,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_6_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -360,7 +385,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -376,23 +402,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP6_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP6)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP6_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP6_ISR_REMOVE */
+#endif   /*  USBFS_EP6_ISR_REMOVE */
 
 
 #if(USBFS_EP7_ISR_REMOVE == 0u)
@@ -413,7 +441,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_7_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -421,7 +450,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -437,23 +467,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP7_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP7)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP7_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP7_ISR_REMOVE */
+#endif   /*  USBFS_EP7_ISR_REMOVE */
 
 
 #if(USBFS_EP8_ISR_REMOVE == 0u)
@@ -474,7 +506,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_8_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -482,7 +515,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -498,23 +532,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP8_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP8)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP8_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP8_ISR_REMOVE */
+#endif   /*  USBFS_EP8_ISR_REMOVE */
 
 
 /*******************************************************************************
@@ -611,6 +647,17 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                         /* Clear Data ready status */
                         *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=
                                                                     (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                        #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                            /* Setup common area DMA with rest of the data */
+                            if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)
+                            {
+                                USBFS_LoadNextInEP(ep, 0u);
+                            }
+                            else
+                            {
+                                USBFS_inBufFull[ep] = 1u;
+                            }
+                        #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
                         /* Write the Mode register */
                         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);
                         #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)
@@ -618,7 +665,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                             {   /* Clear MIDI input pointer */
                                 USBFS_midiInPointer = 0u;
                             }
-                        #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                 }
                 /* (re)arm Out EP only for mode2 */
@@ -634,7 +681,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                                                                                     USBFS_EP[ep].epMode);
                         }
                     }
-                #endif /* End USBFS_EP_MM */
+                #endif /*  USBFS_EP_MM */
 
                 /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */
 
@@ -652,7 +699,82 @@ CY_ISR(USBFS_BUS_RESET_ISR)
         /* `#END` */
     }
 
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    /******************************************************************************
+    * Function Name: USBFS_EP_DMA_DONE_ISR
+    *******************************************************************************
+    *
+    * Summary:
+    *  Endpoint 1 DMA Done Interrupt Service Routine
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  None.
+    *
+    ******************************************************************************/
+    CY_ISR(USBFS_EP_DMA_DONE_ISR)
+    {
+        uint8 int8Status;
+        uint8 int17Status;
+        uint8 ep_status;
+        uint8 ep = USBFS_EP1;
+        uint8 ptr = 0u;
+
+        /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
+
+        /* `#END` */
+
+        /* Read clear on read status register with the EP source of interrupt */
+        int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;
+        int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;
+
+        while(int8Status != 0u)
+        {
+            while(int17Status != 0u)
+            {
+                if((int17Status & 1u) != 0u)  /* If EpX interrupt present */
+                {
+                    /* Read Endpoint Status Register */
+                    ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));
+                    if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&
+                        (USBFS_inBufFull[ep] == 0u))
+                    {
+                        /* `#START EP_DMA_DONE_USER_CODE` Place your code here */
+
+                        /* `#END` */
+
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
+                        /* repeat 2 last bytes to prefetch endpoint area */
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
+                                    USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);
+                        USBFS_LoadNextInEP(ep, 1);
+                        /* Set Data ready status, This will generate DMA request */
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    }
+                }
+                ptr += USBFS_EPX_CNTX_ADDR_OFFSET;               /* prepare pointer for next EP */
+                ep++;
+                int17Status >>= 1u;
+            }
+            int8Status >>= 1u;
+            if(int8Status != 0u)
+            {
+                /* Prepare pointer for EP8 */
+                ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+                ep = USBFS_EP8;
+                int17Status = int8Status & 0x01u;
+            }
+        }
+
+        /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
+
+        /* `#END` */
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c
index ba9fdf5b..fedf8b0b 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c
@@ -1,14 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_hid.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB HID Class request handler.
 *
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
+*
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -416,7 +419,7 @@ void USBFS_FindReport(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_HID_CLASS */
+#endif  /*  USBFS_ENABLE_HID_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h
index 9a6201c1..e802023f 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_hid.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -58,7 +61,7 @@ uint8 USBFS_GetProtocol(uint8 interface) ;
 #define USBFS_HID_GET_REPORT_OUTPUT      (0x02u)
 #define USBFS_HID_GET_REPORT_FEATURE     (0x03u)
 
-#endif /* End CY_USBFS_USBFS_hid_H */
+#endif /*  CY_USBFS_USBFS_hid_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c
index 1f0ce51a..be7060bf 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c
@@ -1,14 +1,18 @@
 /*******************************************************************************
 * File Name: USBFS_midi.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  MIDI Streaming request handler.
 *  This file contains routines for sending and receiving MIDI
 *  messages, and handles running status in both directions.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -60,15 +64,15 @@
         volatile uint16 USBFS_midiInPointer;                            /* Input endpoint buffer pointer */
     #else
         volatile uint8 USBFS_midiInPointer;                             /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */
     volatile uint8 USBFS_midi_in_ep;                                    /* Input endpoint number */
     uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];       /* Input endpoint buffer */
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
     volatile uint8 USBFS_midi_out_ep;                                   /* Output endpoint number */
     uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE];     /* Output endpoint buffer */
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event;            /* MIDI RX status structure */
@@ -79,8 +83,8 @@
         static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event;        /* MIDI RX status structure */
         static volatile uint8 USBFS_MIDI2_TxRunStat;                     /* MIDI Output running status */
         volatile uint8 USBFS_MIDI2_InqFlags;                             /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
 
 /***************************************
@@ -134,30 +138,30 @@ void USBFS_MIDI_EP_Init(void)
 {
     #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
        USBFS_midiInPointer = 0u;
-    #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
         #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
             /* Init DMA configurations for IN EP*/
             USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,
                                                                                 USBFS_MIDI_IN_BUFF_SIZE);
-                                                                                
-        #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+        #endif  /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
         #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
             /* Init DMA configurations for OUT EP*/
             (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,
                                                                                 USBFS_MIDI_OUT_BUFF_SIZE);
-        #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-    #endif  /* End USBFS__EP_DMAAUTO */
+        #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
+    #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
 
     #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
         USBFS_EnableOutEP(USBFS_midi_out_ep);
-    #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
     /* Initialize the MIDI port(s) */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
         USBFS_MIDI_Init();
-    #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 }
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
@@ -199,37 +203,43 @@ void USBFS_MIDI_EP_Init(void)
         #else
             uint8 outLength;
             uint8 outPointer;
-        #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */
+        #endif /*  USBFS_MIDI_OUT_BUFF_SIZE >=256 */
 
         uint8 dmaState = 0u;
 
         /* Service the USB MIDI output endpoint */
         if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)
         {
-            #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+            #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                 outLength = USBFS_GetEPCount(USBFS_midi_out_ep);
             #else
                 outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);
-            #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+            #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
             #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-                #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+                #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                     outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, outLength);
                 #else
                     outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, (uint16)outLength);
-                #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+                #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
                 #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                     do  /* wait for DMA transfer complete */
                     {
-                        (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
-                    }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-            #endif  /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+                        (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
+                    }
+                    while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
+                #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */
+
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
+
             if(dmaState != 0u)
             {
                 /* Suppress compiler warning */
             }
+
             if (outLength >= USBFS_EVENT_LENGTH)
             {
                 outPointer = 0u;
@@ -252,7 +262,7 @@ void USBFS_MIDI_EP_Init(void)
                         {
                             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                                 USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);
-                            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+                            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
                         }
                         else
                         {
@@ -260,7 +270,7 @@ void USBFS_MIDI_EP_Init(void)
 
                             /* `#END` */
                         }
-                    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+                    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
                     /* Process any local MIDI output functions */
                     USBFS_callbackLocalMidiEvent(
@@ -272,7 +282,7 @@ void USBFS_MIDI_EP_Init(void)
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /* Enable Out EP*/
                 USBFS_EnableOutEP(USBFS_midi_out_ep);
-            #endif  /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif  /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
         }
     }
 
@@ -322,12 +332,12 @@ void USBFS_MIDI_EP_Init(void)
             #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
                 /* rearm IN EP */
                 USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);
-            #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
 
             /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */
             #if(USBFS_EP_MM == USBFS__EP_MANUAL)
                 USBFS_midiInPointer = 0u;
-            #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
+            #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */
             }
         }
     }
@@ -370,7 +380,8 @@ void USBFS_MIDI_EP_Init(void)
             uint8 m2 = 0u;
             do
             {
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI1 input port for a complete event */
                     m1 = USBFS_MIDI1_GetEvent();
@@ -382,7 +393,8 @@ void USBFS_MIDI_EP_Init(void)
                 }
 
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI2 input port for a complete event */
                     m2 = USBFS_MIDI2_GetEvent();
@@ -392,11 +404,12 @@ void USBFS_MIDI_EP_Init(void)
                                                     USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);
                     }
                 }
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 
-            }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
-                   && ((m1 != 0u) || (m2 != 0u)) );
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            }while( (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&
+                    ((m1 != 0u) || (m2 != 0u)) );
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         /* Service the USB MIDI input endpoint */
         USBFS_MIDI_IN_EP_Service();
@@ -453,8 +466,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_DisableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_DisableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         if (USBFS_midiInPointer >
                     (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
@@ -481,15 +494,16 @@ void USBFS_MIDI_EP_Init(void)
                         (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                     {
                         USBFS_MIDI_IN_EP_Service();
-                        if (USBFS_midiInPointer >
-                            (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
+                        if(USBFS_midiInPointer >
+                          (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                         {
                             /* Error condition. HOST is not ready to receive this packet. */
                             retError = USBFS_TRUE;
                             break;
                         }
                     }
-                }while(ic > USBFS_EVENT_BYTE3);
+                }
+                while(ic > USBFS_EVENT_BYTE3);
 
                 if(retError == USBFS_FALSE)
                 {
@@ -507,8 +521,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_EnableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_EnableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         return (retError);
     }
@@ -712,7 +726,7 @@ void USBFS_MIDI_EP_Init(void)
             /* Change the priority of the UART TX interrupt */
             CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);
             CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
+        #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
 
         /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */
 
@@ -915,12 +929,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI1_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;
@@ -930,12 +945,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI1_UART_rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI1_UART_rxBufferWrite;
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary buffer pointer
@@ -948,7 +963,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /*  ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI1_UART_rxBuffer[rxBufferRead];
                     /* Increment pointer with a wrap */
@@ -965,11 +980,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI1_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                         MIDI1_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -984,11 +999,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI1_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1105,6 +1120,7 @@ void USBFS_MIDI_EP_Init(void)
         /* `#END` */
     }
 
+
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
 
 
@@ -1137,12 +1153,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI2_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;
@@ -1152,12 +1169,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI2_UART_rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI2_UART_rxBufferWrite;
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary output pointer to
@@ -1170,7 +1187,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI2_UART_rxBuffer[rxBufferRead];
                     rxBufferRead++;
@@ -1186,11 +1203,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI2_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                         MIDI2_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -1205,11 +1222,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI2_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1325,17 +1342,17 @@ void USBFS_MIDI_EP_Init(void)
 
         /* `#END` */
     }
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
-#endif  /* End (USBFS_ENABLE_MIDI_API != 0u) */
+#endif  /*  (USBFS_ENABLE_MIDI_API != 0u) */
 
 
 /* `#START MIDI_FUNCTIONS` Place any additional functions here */
 
 /* `#END` */
 
-#endif  /* End defined(USBFS_ENABLE_MIDI_STREAMING) */
+#endif  /*  defined(USBFS_ENABLE_MIDI_STREAMING) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h
index 5a720340..ad6e5d7b 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h
@@ -1,13 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_midi.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Header File for the USBFS MIDI module.
 *  Contains prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,7 +25,7 @@
 
 
 /***************************************
-*    Data Struct Definition
+*    Data Structure Definition
 ***************************************/
 
 /* The following structure is used to hold status information for
@@ -112,12 +116,13 @@ typedef struct
 #define USBFS_CUSTOM_UART_TX_PRIOR_NUM   (0x04u)
 #define USBFS_CUSTOM_UART_RX_PRIOR_NUM   (0x02u)
 
-#define USBFS_ISR_SERVICE_MIDI_OUT     \
+#define USBFS_ISR_SERVICE_MIDI_OUT         \
         ( (USBFS_ENABLE_MIDI_API != 0u) && \
-          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )
+          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))
 #define USBFS_ISR_SERVICE_MIDI_IN     \
         ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )
 
+
 /***************************************
 * External function references
 ***************************************/
@@ -132,13 +137,13 @@ void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     #include "MIDI1_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
     #include "MIDI2_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     #include <CyDmac.h>
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 
 
 /***************************************
@@ -159,8 +164,8 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         uint8 USBFS_MIDI2_GetEvent(void) ;
         void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])
                                                     ;
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 
 /***************************************
@@ -174,7 +179,7 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         extern volatile uint16 USBFS_midiInPointer;                       /* Input endpoint buffer pointer */
     #else
         extern volatile uint8 USBFS_midiInPointer;                        /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /*  USBFS_MIDI_IN_BUFF_SIZE >=256 */
     extern volatile uint8 USBFS_midi_in_ep;                               /* Input endpoint number */
     extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];  /* Input endpoint buffer */
 #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
@@ -188,13 +193,13 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
     extern volatile uint8 USBFS_MIDI1_InqFlags;                              /* Device inquiry flag */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
         extern volatile uint8 USBFS_MIDI2_InqFlags;                          /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
 
 
-#endif /* End CY_USBFS_USBFS_midi_H */
+#endif /*  CY_USBFS_USBFS_midi_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c
index 00c88f64..3540214e 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_pm.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This file provides Suspend/Resume APIs functionality.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -36,7 +36,6 @@ static USBFS_BACKUP_STRUCT  USBFS_backup;
 
 #if(USBFS_DP_ISR_REMOVE == 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_DP_Interrupt
     ********************************************************************************
@@ -119,7 +118,7 @@ void USBFS_RestoreConfig(void)
 ********************************************************************************
 *
 * Summary:
-*  This function disables the USBFS block and prepares for power donwn mode.
+*  This function disables the USBFS block and prepares for power down mode.
 *
 * Parameters:
 *  None.
@@ -145,7 +144,7 @@ void USBFS_Suspend(void)
 
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
         USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;
@@ -158,7 +157,7 @@ void USBFS_Suspend(void)
         /* Disable the SIE */
         USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;
 
-        CyDelayUs(0u);  /*~50ns delay */
+        CyDelayUs(0u);  /* ~50ns delay */
         /* Store mode and Disable VRegulator*/
         USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;
         USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;
@@ -181,16 +180,16 @@ void USBFS_Suspend(void)
     {
         USBFS_backup.enableState = 0u;
     }
+
     CyExitCriticalSection(enableInterrupts);
 
     /* Set the DP Interrupt for wake-up from sleep mode. */
     #if(USBFS_DP_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM,   &USBFS_DP_ISR);
+        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
         CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);
         CyIntClearPending(USBFS_DP_INTC_VECT_NUM);
         CyIntEnable(USBFS_DP_INTC_VECT_NUM);
     #endif /* (USBFS_DP_ISR_REMOVE == 0u) */
-
 }
 
 
@@ -223,7 +222,7 @@ void USBFS_Resume(void)
     {
         #if(USBFS_DP_ISR_REMOVE == 0u)
             CyIntDisable(USBFS_DP_INTC_VECT_NUM);
-        #endif /* End USBFS_DP_ISR_REMOVE */
+        #endif /*  USBFS_DP_ISR_REMOVE */
 
         /* Enable USB block */
         USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
@@ -245,18 +244,18 @@ void USBFS_Resume(void)
         /* Set the USBIO pull-up enable */
         USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
 
-        /* Reinit Arbiter configuration for DMA transfers */
+        /* Re-init Arbiter configuration for DMA transfers */
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-            /* usb arb interrupt enable */
+            /* Usb arb interrupt enable */
             USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
             #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /*Set cfg cmplt this rises DMA request when the full configuration is done */
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* STALL_IN_OUT */
         CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
@@ -268,8 +267,8 @@ void USBFS_Resume(void)
 
         /* Restore USB register settings */
         USBFS_RestoreConfig();
-
     }
+
     CyExitCriticalSection(enableInterrupts);
 }
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
index 499fe263..0c73e91a 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: .h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This private file provides constants and parameter values for the
@@ -10,7 +10,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -66,7 +66,14 @@ extern volatile T_USBFS_TD USBFS_currentTD;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     extern uint8 USBFS_DmaChan[USBFS_MAX_EP];
     extern uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];
+    extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 extern volatile uint8 USBFS_ep0Toggle;
 extern volatile uint8 USBFS_lastPacketSize;
@@ -106,7 +113,7 @@ void USBFS_Config(uint8 clearAltSetting) ;
 void USBFS_ConfigAltChanged(void) ;
 void USBFS_ConfigReg(void) ;
 
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                             ;
 const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)
                                                             ;
@@ -119,56 +126,62 @@ uint8 USBFS_ValidateAlternateSetting(void) ;
 void USBFS_SaveConfig(void) ;
 void USBFS_RestoreConfig(void) ;
 
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
 #if defined(USBFS_ENABLE_IDSN_STRING)
     void USBFS_ReadDieID(uint8 descr[]) ;
 #endif /* USBFS_ENABLE_IDSN_STRING */
 
 #if defined(USBFS_ENABLE_HID_CLASS)
     uint8 USBFS_DispatchHIDClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_AUDIO_CLASS)
     uint8 USBFS_DispatchAUDIOClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_CDC_CLASS)
     uint8 USBFS_DispatchCDCClassRqst(void);
-#endif /* End USBFS_ENABLE_CDC_CLASS */
+#endif /*  USBFS_ENABLE_CDC_CLASS */
 
 CY_ISR_PROTO(USBFS_EP_0_ISR);
 #if(USBFS_EP1_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_1_ISR);
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /*  USBFS_EP1_ISR_REMOVE */
 #if(USBFS_EP2_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_2_ISR);
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /*  USBFS_EP2_ISR_REMOVE */
 #if(USBFS_EP3_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_3_ISR);
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /*  USBFS_EP3_ISR_REMOVE */
 #if(USBFS_EP4_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_4_ISR);
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /*  USBFS_EP4_ISR_REMOVE */
 #if(USBFS_EP5_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_5_ISR);
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /*  USBFS_EP5_ISR_REMOVE */
 #if(USBFS_EP6_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_6_ISR);
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /*  USBFS_EP6_ISR_REMOVE */
 #if(USBFS_EP7_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_7_ISR);
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /*  USBFS_EP7_ISR_REMOVE */
 #if(USBFS_EP8_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_8_ISR);
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /*  USBFS_EP8_ISR_REMOVE */
 CY_ISR_PROTO(USBFS_BUS_RESET_ISR);
 #if(USBFS_SOF_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_SOF_ISR);
-#endif /* End USBFS_SOF_ISR_REMOVE */
+#endif /*  USBFS_SOF_ISR_REMOVE */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     CY_ISR_PROTO(USBFS_ARB_ISR);
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 #if(USBFS_DP_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_DP_ISR);
-#endif /* End USBFS_DP_ISR_REMOVE */
-
+#endif /*  USBFS_DP_ISR_REMOVE */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 /***************************************
 * Request Handlers
@@ -182,6 +195,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    HID Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_HID_CLASS)
     void USBFS_FindReport(void) ;
     void USBFS_FindReportDescriptor(void) ;
@@ -192,6 +206,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    MIDI Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_MIDI_STREAMING)
     void USBFS_MIDI_IN_EP_Service(void) ;
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c
index 18f0364a..b047b37d 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_std.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Standard request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -17,9 +17,9 @@
 #include "USBFS.h"
 #include "USBFS_cdc.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -33,7 +33,6 @@
 
 #if defined(USBFS_ENABLE_FWSN_STRING)
 
-
     /*******************************************************************************
     * Function Name: USBFS_SerialNumString
     ********************************************************************************
@@ -57,10 +56,10 @@
         USBFS_snStringConfirm = USBFS_FALSE;
         if(snString != NULL)
         {
-            USBFS_fwSerialNumberStringDescriptor = snString;
             /* Check descriptor validation */
             if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )
             {
+                USBFS_fwSerialNumberStringDescriptor = snString;
                 USBFS_snStringConfirm = USBFS_TRUE;
             }
         }
@@ -90,6 +89,7 @@ uint8 USBFS_HandleStandardRqst(void)
 {
     uint8 requestHandled = USBFS_FALSE;
     uint8 interfaceNumber;
+    uint8 configurationN;
     #if defined(USBFS_ENABLE_STRINGS)
         volatile uint8 *pStr = 0u;
         #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)
@@ -117,11 +117,14 @@ uint8 USBFS_HandleStandardRqst(void)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)
                 {
                     pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));
-                    USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
-                    USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
-                                      USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
-                                     (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
-                    requestHandled  = USBFS_InitControlRead();
+                    if( pTmp != NULL )  /* Verify that requested descriptor exists */
+                    {
+                        USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
+                        USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
+                                          USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
+                                         (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
+                        requestHandled  = USBFS_InitControlRead();
+                    }
                 }
                 #if defined(USBFS_ENABLE_STRINGS)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)
@@ -138,34 +141,39 @@ uint8 USBFS_HandleStandardRqst(void)
                             pStr = &pStr[descrLength];
                             nStr++;
                         }
-                    #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */
+                    #endif /*  USBFS_ENABLE_DESCRIPTOR_STRINGS */
                     /* Microsoft OS String*/
                     #if defined(USBFS_ENABLE_MSOS_STRING)
                         if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )
                         {
                             pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];
                         }
-                    #endif /* End USBFS_ENABLE_MSOS_STRING*/
+                    #endif /*  USBFS_ENABLE_MSOS_STRING*/
                     /* SN string */
                     #if defined(USBFS_ENABLE_SN_STRING)
                         if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&
                             (CY_GET_REG8(USBFS_wValueLo) ==
                             USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )
                         {
-                            pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
-                            #if defined(USBFS_ENABLE_FWSN_STRING)
-                                if(USBFS_snStringConfirm != USBFS_FALSE)
-                                {
-                                    pStr = USBFS_fwSerialNumberStringDescriptor;
-                                }
-                            #endif  /* USBFS_ENABLE_FWSN_STRING */
+
                             #if defined(USBFS_ENABLE_IDSN_STRING)
                                 /* Read DIE ID and generate string descriptor in RAM */
                                 USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);
                                 pStr = USBFS_idSerialNumberStringDescriptor;
-                            #endif    /* End USBFS_ENABLE_IDSN_STRING */
+                            #elif defined(USBFS_ENABLE_FWSN_STRING)
+                                if(USBFS_snStringConfirm != USBFS_FALSE)
+                                {
+                                    pStr = USBFS_fwSerialNumberStringDescriptor;
+                                }
+                                else
+                                {
+                                    pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                                }
+                            #else
+                                pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                            #endif  /* defined(USBFS_ENABLE_IDSN_STRING) */
                         }
-                    #endif    /* End USBFS_ENABLE_SN_STRING */
+                    #endif    /*  USBFS_ENABLE_SN_STRING */
                     if (*pStr != 0u)
                     {
                         USBFS_currentTD.count = *pStr;
@@ -173,7 +181,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         requestHandled  = USBFS_InitControlRead();
                     }
                 }
-                #endif /* End USBFS_ENABLE_STRINGS */
+                #endif /*  USBFS_ENABLE_STRINGS */
                 else
                 {
                     requestHandled = USBFS_DispatchClassRqst();
@@ -225,10 +233,23 @@ uint8 USBFS_HandleStandardRqst(void)
                 requestHandled = USBFS_InitNoDataControlTransfer();
                 break;
             case USBFS_SET_CONFIGURATION:
-                USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);
-                USBFS_configurationChanged = USBFS_TRUE;
-                USBFS_Config(USBFS_TRUE);
-                requestHandled = USBFS_InitNoDataControlTransfer();
+                configurationN = CY_GET_REG8(USBFS_wValueLo);
+                if(configurationN > 0u)
+                {   /* Verify that configuration descriptor exists */
+                    pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);
+                }
+                /* Responds with a Request Error when configuration number is invalid */
+                if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))
+                {
+                    /* Set new configuration if it has been changed */
+                    if(configurationN != USBFS_configuration)
+                    {
+                        USBFS_configuration = configurationN;
+                        USBFS_configurationChanged = USBFS_TRUE;
+                        USBFS_Config(USBFS_TRUE);
+                    }
+                    requestHandled = USBFS_InitNoDataControlTransfer();
+                }
                 break;
             case USBFS_SET_INTERFACE:
                 if (USBFS_ValidateAlternateSetting() != 0u)
@@ -241,7 +262,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         USBFS_Config(USBFS_FALSE);
                     #else
                         USBFS_ConfigAltChanged();
-                    #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+                    #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
                     /* Update handled Alt setting changes status */
                     USBFS_interfaceSetting_last[interfaceNumber] =
                          USBFS_interfaceSetting[interfaceNumber];
@@ -342,7 +363,6 @@ uint8 USBFS_HandleStandardRqst(void)
         uint8 value;
         const char8 CYCODE hex[16u] = "0123456789ABCDEF";
 
-
         /* Check descriptor validation */
         if( descr != NULL)
         {
@@ -360,7 +380,7 @@ uint8 USBFS_HandleStandardRqst(void)
         }
     }
 
-#endif /* End USBFS_ENABLE_IDSN_STRING */
+#endif /*  USBFS_ENABLE_IDSN_STRING */
 
 
 /*******************************************************************************
@@ -384,20 +404,18 @@ void USBFS_ConfigReg(void)
     uint8 ep;
     uint8 i;
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-        uint8 ep_type = 0u;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        uint8 epType = 0u;
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     /* Set the endpoint buffer addresses */
     ep = USBFS_EP1;
     for (i = 0u; i < 0x80u; i+= 0x10u)
     {
-        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |
-                                                          USBFS_ARB_EPX_CFG_RESET);
-
+        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */
             CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)
         {
@@ -410,8 +428,8 @@ void USBFS_ConfigReg(void)
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);
                 /* Prepare EP type mask for automatic memory allocation */
                 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-                    ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                    epType |= (uint8)(0x01u << (ep - USBFS_EP1));
+                #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
         }
         else
@@ -427,7 +445,7 @@ void USBFS_ConfigReg(void)
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i),     USBFS_EP[ep].buffOffset & 0xFFu);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         ep++;
     }
@@ -438,13 +456,13 @@ void USBFS_ConfigReg(void)
         USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST;   /* DMA burst threshold */
         USBFS_DMA_THRES_MSB_REG = 0u;
         USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;
-        USBFS_EP_TYPE_REG = ep_type;
+        USBFS_EP_TYPE_REG = epType;
         /* Cfg_cmp bit set to 1 once configuration is complete. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |
                                        USBFS_ARB_CFG_CFG_CPM;
         /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);
 }
@@ -477,11 +495,11 @@ void USBFS_Config(uint8 clearAltSetting)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     const uint8 *pDescr;
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 buffCount = 0u;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     const T_USBFS_LUT CYCODE *pTmp;
     const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;
@@ -534,56 +552,56 @@ void USBFS_Config(uint8 clearAltSetting)
             pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;
             for (i = 0u; i < ep; i++)
             {
-                /* Compare current Alternate setting with EP Alt*/
+                /* Compare current Alternate setting with EP Alt */
                 if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                 {
                     cur_ep = pEP->addr & USBFS_DIR_UNUSED;
-                    ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                    epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                     if (pEP->addr & USBFS_DIR_IN)
                     {
                         /* IN Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     else
                     {
                         /* OUT Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                      (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;
                     USBFS_EP[cur_ep].addr = pEP->addr;
@@ -591,7 +609,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 }
                 pEP = &pEP[1u];
             }
-        #else /* Config for static EP memory allocation  */
+        #else /* Configure for static EP memory allocation  */
             for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)
             {
                 /* p_list points the endpoint setting table. */
@@ -610,67 +628,67 @@ void USBFS_Config(uint8 clearAltSetting)
                         /* Compare current Alternate setting with EP Alt*/
                         if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                         {
-                            ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                            epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                             if ((pEP->addr & USBFS_DIR_IN) != 0u)
                             {
                                 /* IN Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             else
                             {
                                 /* OUT Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             USBFS_EP[i].addr = pEP->addr;
                             USBFS_EP[i].attrib = pEP->attributes;
 
                             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                                 break;      /* use first EP setting in Auto memory managment */
-                            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
                         }
                     }
                     pEP = &pEP[1u];
                 }
             }
-        #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+        #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
 
         /* Init class array for each interface and interface number for each EP.
         *  It is used for handling Class specific requests directed to either an
@@ -694,7 +712,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 USBFS_EP[ep].buffOffset = buffCount;
                  buffCount += USBFS_EP[ep].bufferSize;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Configure hardware registers */
         USBFS_ConfigReg();
@@ -725,7 +743,7 @@ void USBFS_ConfigAltChanged(void)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     uint8 ri;
 
     const T_USBFS_LUT CYCODE *pTmp;
@@ -753,19 +771,19 @@ void USBFS_ConfigAltChanged(void)
             {
                 cur_ep = pEP->addr & USBFS_DIR_UNUSED;
                 ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-                ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                 if ((pEP->addr & USBFS_DIR_IN) != 0u)
                 {
                     /* IN Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                 }
                 else
                 {
                     /* OUT Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                 }
                  /* Change the SIE mode for the selected EP to NAK ALL */
@@ -823,7 +841,7 @@ void USBFS_ConfigAltChanged(void)
                                                                 USBFS_EP[cur_ep].buffOffset & 0xFFu);
                 CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),
                                                                 USBFS_EP[cur_ep].buffOffset >> 8u);
-            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
             /* Get next EP element */
             pEP = &pEP[1u];
@@ -840,13 +858,13 @@ void USBFS_ConfigAltChanged(void)
 *  This routine returns a pointer a configuration table entry
 *
 * Parameters:
-*  c:  Configuration Index
+*  confIndex:  Configuration Index
 *
 * Return:
-*  Device Descriptor pointer.
+*  Device Descriptor pointer or NULL when descriptor isn't exists.
 *
 *******************************************************************************/
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                         
 {
     /* Device Table */
@@ -856,8 +874,20 @@ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
 
     /* The first entry points to the Device Descriptor,
     *  the rest configuration entries.
-	*/
-    return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );
+    *  Set pointer to the first Configuration Descriptor
+    */
+    pTmp = &pTmp[1u];
+    /* For this table, c is the number of configuration descriptors  */
+    if(confIndex >= pTmp->c)   /* Verify that required configuration descriptor exists */
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) NULL;
+    }
+    else
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;
+    }
+
+    return( pTmp );
 }
 
 
@@ -902,14 +932,24 @@ const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void)
                                                         
 {
     const T_USBFS_LUT CYCODE *pTmp;
+    const uint8 CYCODE *pInterfaceClass;
     uint8 currentInterfacesNum;
 
     pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
-    currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
-    /* Third entry in the LUT starts the Interface Table pointers */
-    /* The INTERFACE_CLASS table is located after all interfaces */
-    pTmp = &pTmp[currentInterfacesNum + 2u];
-    return( (const uint8 CYCODE *) pTmp->p_list );
+    if( pTmp != NULL )
+    {
+        currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
+        /* Third entry in the LUT starts the Interface Table pointers */
+        /* The INTERFACE_CLASS table is located after all interfaces */
+        pTmp = &pTmp[currentInterfacesNum + 2u];
+        pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;
+    }
+    else
+    {
+        pInterfaceClass = (const uint8 CYCODE *) NULL;
+    }
+
+    return( pInterfaceClass );
 }
 
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
index 15b68a55..ef4d5f14 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_vnd.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB vendor request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -34,7 +34,7 @@
 ********************************************************************************
 *
 * Summary:
-*  This routine provide users with a method to implement vendor specifc
+*  This routine provide users with a method to implement vendor specific
 *  requests.
 *
 *  To implement vendor specific requests, add your code in this function to
@@ -66,7 +66,7 @@ uint8 USBFS_HandleVendorRqst(void)
                     USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     requestHandled  = USBFS_InitControlRead();
-                #endif /* End USBFS_ENABLE_MSOS_STRING */
+                #endif /*  USBFS_ENABLE_MSOS_STRING */
                 break;
             default:
                 break;
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld
index 6427452c..676540d2 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld
@@ -45,10 +45,10 @@ CY_METADATA_SIZE    = 64;
  */
 EXTERN(Reset)
 
-/* Bring in the interrupt routines & vector */
+/* Bring in interrupt routines & vector */
 EXTERN(main)
 
-/* Bring in the meta data */
+/* Bring in meta data */
 EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
 EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 
@@ -90,7 +90,7 @@ SECTIONS
     /* Make sure we pulled in some reset code.  */
     ASSERT (. != __cy_reset, "No reset code");
 
-	/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
+	/* Place DMA initialization before text to ensure it gets placed in first 64K of flash */
     *(.dma_init)
     ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
 		
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
index a7c7be7c..959fde97 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: core_cm3_psoc5.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides important type information for the PSoC5.  This includes types
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c
index 01f07941..33ecdf44 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the power management.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,8 @@
 
 
 /*******************************************************************
-* Place your includes, defines and code here. Do not use merge
-* region below unless any component datasheet suggest to do so.
+* Place your includes, defines, and code here. Do not use the merge
+* region below unless any component datasheet suggests doing so.
 *******************************************************************/
 /* `#START CY_PM_HEADER_INCLUDE` */
 
@@ -51,8 +51,8 @@ static void CyPmHviLviRestore(void) ;
 *
 * Summary:
 *  This function is called in preparation for entering sleep or hibernate low
-*  power modes. Saves all state of the clocking system that does not persist
-*  during sleep/hibernate or that needs to be altered in preparation for
+*  power modes. Saves all the states of the clocking system that do not persist
+*  during sleep/hibernate or that need to be altered in preparation for
 *  sleep/hibernate. Shutdowns all the digital and analog clock dividers for the
 *  active power mode configuration.
 *
@@ -105,6 +105,45 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imo2x = CY_PM_DISABLED;
     }
 
+    /* Master clock - save source */
+    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+
+    /* Switch Master clock's source from PLL's output to PLL's source */
+    if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)
+    {
+        switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)
+        {
+        case CY_PM_CLKDIST_PLL_SRC_IMO:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_XTAL:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_DSI:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);
+            break;
+
+        default:
+            CYASSERT(0u != 0u);
+            break;
+        }
+    }
+
+    /* PLL - check enable state, disable if needed */
+    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
+    {
+        /* PLL is enabled - save state and disable */
+        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
+        CyPLL_OUT_Stop();
+    }
+    else
+    {
+        /* PLL is disabled - save state */
+        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
+    }
+
     /* IMO - set appropriate frequency for LPM */
     CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);
 
@@ -119,8 +158,11 @@ void CyPmSaveClocks(void)
         /* IMO - save disabled state */
         cyPmClockBackup.imoEnable = CY_PM_DISABLED;
 
-        /* IMO - enable */
+        /* Enable the IMO. Use software delay instead of the FTW-based inside */
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
+
+        /* Settling time of the IMO is of the order of less than 6us */
+        CyDelayUs(6u);
     }
 
     /* IMO - save the current IMOCLK source and set to IMO if not yet */
@@ -130,7 +172,7 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imoClkSrc =
             (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;
 
-        /* IMO -  set IMOCLK source to MHz OSC */
+        /* IMO -  set IMOCLK source to IMO */
         CyIMO_SetSource(CY_IMO_SOURCE_IMO);
     }
     else
@@ -161,16 +203,13 @@ void CyPmSaveClocks(void)
     if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)
     {
         CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);
-    }    /* Need to change nothing if master clock divider is 1 */
-
-    /* Master clock - save current source */
-    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+    }    /* No change if master clock divider is 1 */
 
     /* Master clock source - set it to IMO if not yet. */
     if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)
     {
         CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
-    }    /* Need to change nothing if master clock source is IMO */
+    }    /* No change if master clock source is IMO */
 
     /* Bus clock - save divider and set it, if needed, to divide-by-one */
     cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
@@ -180,22 +219,9 @@ void CyPmSaveClocks(void)
         CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);
     }    /* Do nothing if saved and actual values are equal */
 
-    /* Set number of wait cycles for the flash according CPU frequency in MHz */
+    /* Set number of wait cycles for flash according to CPU frequency in MHz */
     CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);
 
-    /* PLL - check enable state, disable if needed */
-    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
-    {
-        /* PLL is enabled - save state and disable */
-        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
-        CyPLL_OUT_Stop();
-    }
-    else
-    {
-        /* PLL is disabled - save state */
-        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
-    }
-
     /* MHz ECO - check enable state and disable if needed */
     if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))
     {
@@ -211,8 +237,8 @@ void CyPmSaveClocks(void)
 
 
     /***************************************************************************
-    * Save enable state of delay between the system bus clock and each of the
-    * 4 individual analog clocks. This bit non-retention and it's value should
+    * Save the enable state of delay between the system bus clock and each of the
+    * 4 individual analog clocks. This bit non-retention and its value should
     * be restored on wakeup.
     ***************************************************************************/
     if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))
@@ -240,11 +266,11 @@ void CyPmSaveClocks(void)
 *
 *  PSoC 3 and PSoC 5LP:
 *  The merge region could be used to process state when the megahertz crystal is
-*  not ready after the hold-off timeout.
+*  not ready after a hold-off timeout.
 *
 *  PSoC 5:
-*  The 130 ms is given for the megahertz crystal to stabilize. It's readiness is
-*  not verified after the hold-off timeout.
+*  The 130 ms is given for the megahertz crystal to stabilize. Its readiness is
+*  not verified after a hold-off timeout.
 *
 * Parameters:
 *  None
@@ -265,10 +291,10 @@ void CyPmRestoreClocks(void)
         CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ,  CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,
         CY_IMO_FREQ_48MHZ, 5u, 6u};
 
-    /* Restore enable state of delay between the system bus clock and ACLKs. */
+    /* Restore enable state of delay between system bus clock and ACLKs. */
     if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)
     {
-        /* Delay for both the bandgap and the delay line to settle out */
+        /* Delay for both bandgap and delay line to settle out */
         CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *
                         CY_PM_GET_CPU_FREQ_MHZ);
 
@@ -279,7 +305,7 @@ void CyPmRestoreClocks(void)
     if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)
     {
         /***********************************************************************
-        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait
+        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait
         * period uses FTW for period measurement. This could cause a problem
         * if CTW/FTW is used as a wake up time in the low power modes APIs.
         * So, the XTAL wait procedure is implemented with a software delay.
@@ -309,7 +335,7 @@ void CyPmRestoreClocks(void)
         {
             /*******************************************************************
             * Process the situation when megahertz crystal is not ready.
-            * Time to stabialize value is crystal specific.
+            * Time to stabilize the value is crystal specific.
             *******************************************************************/
            /* `#START_MHZ_ECO_TIMEOUT` */
 
@@ -318,10 +344,10 @@ void CyPmRestoreClocks(void)
     }   /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */
 
 
-    /* Temprorary set the maximum flash wait cycles */
+    /* Temprorary set maximum flash wait cycles */
     CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);
 
-    /* The XTAL and DSI clocks are ready to be source for Master clock. */
+    /* XTAL and DSI clocks are ready to be source for Master clock. */
     if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||
        (CY_PM_MASTER_CLK_SRC_DSI  == cyPmClockBackup.masterClkSrc))
     {
@@ -366,13 +392,6 @@ void CyPmRestoreClocks(void)
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
     }
 
-    /* IMO - restore disable state if needed */
-    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
-       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
-    {
-        CyIMO_Stop();
-    }
-
     /* IMO - restore IMOCLK source */
     CyIMO_SetSource(cyPmClockBackup.imoClkSrc);
 
@@ -389,6 +408,7 @@ void CyPmRestoreClocks(void)
                                 cyPmClockBackup.clkImoSrc;
     }
 
+
     /* PLL restore state */
     if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)
     {
@@ -398,12 +418,38 @@ void CyPmRestoreClocks(void)
         * as a wakeup time in the low power modes APIs. To omit this issue PLL
         * wait procedure is implemented with a software delay.
         ***********************************************************************/
+        status = CYRET_TIMEOUT;
 
         /* Enable PLL */
         (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);
 
-        /* Make a 250 us delay */
-        CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);
+        /* Read to clear lock status after delay */
+        CyDelayUs((uint32)80u);
+        (void) CY_PM_FASTCLK_PLL_SR_REG;
+
+        /* It should take 250 us lock: 251-80 = 171 */
+        for(i = 171u; i > 0u; i--)
+        {
+            CyDelayUs((uint32)1u);
+
+            /* Accept PLL is OK after two consecutive polls indicate PLL lock */
+            if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&
+               (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))
+            {
+                status = CYRET_SUCCESS;
+                break;
+            }
+        }
+
+        if(CYRET_TIMEOUT == status)
+        {
+            /*******************************************************************
+            * Process the situation when PLL is not ready.
+            *******************************************************************/
+           /* `#START_PLL_TIMEOUT` */
+
+           /* `#END` */
+        }
     }   /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */
 
 
@@ -421,6 +467,13 @@ void CyPmRestoreClocks(void)
         CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);
     }
 
+    /* IMO - disable if it was originally disabled */
+    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
+       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
+    {
+        CyIMO_Stop();
+    }
+
     /* Bus clock - restore divider, if needed */
     clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
     clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;
@@ -490,7 +543,7 @@ void CyPmRestoreClocks(void)
 *  Sleep Timer component and one second interval should be configured with the
 *  RTC component.
 *
-*  The wakeup behavior depends on wakeupSource parameter in the following
+*  The wakeup behavior depends on the wakeupSource parameter in the following
 *  manner: upon function execution the device will be switched from Active to
 *  Alternate Active mode and then the CPU will be halted. When an enabled wakeup
 *  event occurs the device will return to Active mode.  Similarly when an
@@ -534,7 +587,7 @@ void CyPmRestoreClocks(void)
             For PSoC 3 silicon the valid range of  values is 1 to 256.
 *
 *  wakeUpSource:    Specifies a bitwise mask of wakeup sources. In addition, if
-*                   a wakeupTime has been specified the associated timer will be
+*                   a wakeupTime has been specified, the associated timer will be
 *                   included as a wakeup source.
 *
 *           Define                      Source
@@ -556,13 +609,13 @@ void CyPmRestoreClocks(void)
 *  *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.
 *  **Note: CTW and One PPS wakeup signals are in the same mask bit.
 *
-*  When specifying a Comparator as the wakeupSource an instance specific define
-*  should be used that will track with the specific comparator that the instance
-*  is placed into. As an example, for a Comparator instance named MyComp the
+*  When specifying a Comparator as the wakeupSource, an instance specific define
+*  that will track with the specific comparator that the instance
+*  is placed into should be used. As an example, for a Comparator instance named MyComp the
 *  value to OR into the mask is: MyComp_ctComp__CMP_MASK.
 *
 *  When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()
-*  function must be called upon wakeup with corresponding parameter. Please
+*  function must be called upon wakeup with a corresponding parameter. Please
 *  refer to the CyPmReadStatus() API in the System Reference Guide for more
 *  information.
 *
@@ -576,7 +629,7 @@ void CyPmRestoreClocks(void)
 *  If a wakeupTime other than NONE is specified, then upon exit the state of the
 *  specified timer will be left as specified by wakeupTime with the timer
 *  enabled and the interrupt disabled.  Also, the ILO 1 KHz (if CTW timer is
-*  used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)
+*  used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)
 *  will be left started.
 *
 *******************************************************************************/
@@ -602,7 +655,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
         {
             CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_FTW;
         }
 
@@ -612,7 +665,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current CTW configuration and set new one */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_CTW;
         }
 
@@ -622,7 +675,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current 1PPS configuration and set new one */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;
         }
 
@@ -674,7 +727,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  Puts the part into the Sleep state.
 *
 *  Note Before calling this function, you must manually configure the power
-*  mode of the source clocks for the timer that is used as wakeup timer.
+*  mode of the source clocks for the timer that is used as the wakeup timer.
 *
 *  Note Before calling this function, you must prepare clock tree configuration
 *  for the low power mode by calling CyPmSaveClocks(). And restore clock
@@ -685,7 +738,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  PSoC 3:
 *  Before switching to Sleep, if a wakeupTime other than NONE is specified,
 *  then the appropriate timer state is configured as specified with the
-*  interrupt for that timer disabled.  The wakeup source will be the combination
+*  interrupt for that timer disabled.  The wakeup source will be a combination
 *  of the values specified in the wakeupSource and any timer specified in the
 *  wakeupTime argument.  Once the wakeup condition is satisfied, then all saved
 *  state is restored and the function returns in the Active state.
@@ -706,7 +759,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  The wakeupTime parameter is not used and the only NONE can be specified.
 *  The wakeup time must be configured with the component, SleepTimer for CTW
 *  intervals and RTC for 1PPS interval. The component must be configured to
-*  generate an interrrupt.
+*  generate interrupt.
 *
 * Parameters:
 *  wakeupTime:      Specifies a timer wakeup source and the frequency of that
@@ -780,7 +833,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  detect (power supply supervising capabilities) are required in a design
 *  during sleep, use the Central Time Wheel (CTW) to periodically wake the
 *  device, perform software buzz, and refresh the supervisory services. If LVI,
-*  HVI, or Brown Out is not required, then use of the CTW is not required.
+*  HVI, or Brown Out is not required, then CTW is not required.
 *  Refer to the device errata for more information.
 *
 *******************************************************************************/
@@ -816,13 +869,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
     /***********************************************************************
     * PSoC3 < TO6:
-    * - Hardware buzz must be disabled before sleep mode entry.
+    * - Hardware buzz must be disabled before the sleep mode entry.
     * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must
-    *   be aslo disabled.
+    *   be also disabled.
     *
     * PSoC3 >= TO6:
-    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be
-    *   enabled before sleep mode entry and restored on wakeup.
+    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware
+    *   buzz must be enabled before the sleep mode entry and restored on
+    *   the wakeup.
     ***********************************************************************/
     #if(CY_PSOC3)
 
@@ -860,9 +914,9 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************************
-    * For ARM-based devices, an interrupt is required for the CPU to wake up. The
+    * For ARM-based devices,interrupt is required for the CPU to wake up. The
     * Power Management implementation assumes that wakeup time is configured with a
-    * separate component (component-based wakeup time configuration) for an
+    * separate component (component-based wakeup time configuration) for
     * interrupt to be issued on terminal count. For more information, refer to the
     * Wakeup Time Configuration section of System Reference Guide.
     *******************************************************************************/
@@ -887,10 +941,10 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         /* CTW - save current and set new configuration */
         if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))
         {
-            /* Save current and set new configuration of the CTW */
+            /* Save current and set new configuration of CTW */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_CTW;
         }
 
@@ -900,7 +954,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
             /* Save current and set new configuration of the 1PPS */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_ONE_PPS;
         }
 
@@ -923,8 +977,8 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************
-    * Do not use merge region below unless any component datasheet
-    * suggest to do so.
+    * Do not use the merge region below unless any component datasheet
+    * suggests doing so.
     *******************************************************************/
     /* `#START CY_PM_JUST_BEFORE_SLEEP` */
 
@@ -949,13 +1003,13 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));
     }
 
-    /* Switch to the Sleep mode */
+    /* Switch to Sleep mode */
     CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);
 
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1023,7 +1077,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  PSoC 3 and PSoC 5LP:
 *  Before switching to Hibernate, the current status of the PICU wakeup source
 *  bit is saved and then set. This configures the device to wake up from the
-*  PICU. Make sure you have at least one pin configured to generate a PICU
+*  PICU. Make sure you have at least one pin configured to generate PICU
 *  interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls
 *  the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."
 *  In the Pins component datasheet, this register is referred to as the IRQ
@@ -1046,14 +1100,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  requirement begins when the device wakes up. There is no hardware check that
 *  this requirement is met. The specified delay should be done on ISR entry.
 *
-*  After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
+*  After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
 *  instance name of the Pins component) function must be called to clear the
-*  latched pin events to allow proper Hibernate mode entry andd to enable
+*  latched pin events to allow the proper Hibernate mode entry and to enable
 *  detection of future events.
 *
 *  The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to
 *  measure Hibernate/Sleep regulator settling time after a reset. The holdoff
-*  delay is measured using rising edges of the 1 kHz ILO.
+*  delay is measured using the rising edges of the 1 kHz ILO.
 *
 *******************************************************************************/
 void CyPmHibernate(void) 
@@ -1065,8 +1119,8 @@ void CyPmHibernate(void)
 
         /***********************************************************************
         * The Hibernate/Sleep regulator has a settling time after a reset.
-        * During this time, the system ignores requests to enter Sleep and
-        * Hibernate modes. The holdoff delay is measured using rising edges of
+        * During this time, the system ignores requests to enter the Sleep and
+        * Hibernate modes. The holdoff delay is measured using the rising edges of
         * the 1 kHz ILO.
         ***********************************************************************/
         if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))
@@ -1123,7 +1177,7 @@ void CyPmHibernate(void)
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1193,7 +1247,7 @@ uint8 CyPmReadStatus(uint8 mask)
     /* Enter critical section */
     interruptState = CyEnterCriticalSection();
 
-    /* Save value of the register, copy it and clear desired bit */
+    /* Save value of register, copy it and clear desired bit */
     interruptStatus |= CY_PM_INT_SR_REG;
     tmpStatus = interruptStatus;
     interruptStatus &= ((uint8)(~mask));
@@ -1234,11 +1288,11 @@ static void CyPmHibSaveSet(void)
     if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))
     {
         /***********************************************************************
-        * If I2C backup regulator is enabled, all the fixed-function registers
-        * store their values while device is in low power mode, otherwise their
+        * If the I2C backup regulator is enabled, all the fixed-function registers
+        * store their values while the device is in the low power mode, otherwise their
         * configuration is lost. The I2C API makes a decision to restore or not
         * to restore I2C registers based on this. If this regulator will be
-        * disabled and then enabled, I2C API will suppose that I2C block
+        * disabled and then enabled, I2C API will suppose that the I2C block
         * registers preserved their values, while this is not true. So, the
         * backup regulator is disabled. The I2C sleep APIs is responsible for
         * restoration.
@@ -1289,7 +1343,7 @@ static void CyPmHibSaveSet(void)
 
 
     /***************************************************************************
-    * Save and set power mode wakeup trim registers
+    * Save and set the power mode wakeup trim registers
     ***************************************************************************/
     cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;
     cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;
@@ -1304,12 +1358,12 @@ static void CyPmHibSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Restore device for proper Hibernate mode exit:
-*  - Restore LVI/HVI configuration - call CyPmHviLviRestore()
+*  Restores the device for the proper Hibernate mode exit:
+*  - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()
 *  - CyPmHibSlpSaveRestore() function is called
-*  - Restores ILO power down mode state and enable it
-*  - Restores state of 1 kHz and 100 kHz ILO and disable them
-*  - Restores sleep regulator settings
+*  - Restores ILO power down mode state and enables it
+*  - Restores the state of 1 kHz and 100 kHz ILO and disables them
+*  - Restores the sleep regulator settings
 *
 * Parameters:
 *  None
@@ -1352,7 +1406,7 @@ static void CyPmHibRestore(void)
 
 
     /***************************************************************************
-    * Restore power mode wakeup trim registers
+    * Restore the power mode wakeup trim registers
     ***************************************************************************/
     CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;
     CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;
@@ -1364,10 +1418,10 @@ static void CyPmHibRestore(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs CTW configuration:
-*  - Disables CTW interrupt
+*  Performs the CTW configuration:
+*  - Disables the CTW interrupt
 *  - Enables 1 kHz ILO
-*  - Sets new CTW interval
+*  - Sets a new CTW interval
 *
 * Parameters:
 *  ctwInterval: the CTW interval to be set.
@@ -1404,11 +1458,11 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
         /* Set CTW interval if needed */
         if(CY_PM_TW_CFG1_REG != ctwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG1_REG = ctwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the CTW */
+        /* Enable CTW */
         CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;
     }
 }
@@ -1421,7 +1475,7 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
 * Summary:
 *  Performs 1PPS configuration:
 *  - Starts 32 KHz XTAL
-*  - Disables 1PPS interupts
+*  - Disables 1PPS interrupts
 *  - Enables 1PPS
 *
 * Parameters:
@@ -1453,10 +1507,10 @@ void CyPmOppsSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs FTW configuration:
-*  - Disables FTW interrupt
+*  Performs the FTW configuration:
+*  - Disables the FTW interrupt
 *  - Enables 100 kHz ILO
-*  - Sets new FTW interval.
+*  - Sets a new FTW interval.
 *
 * Parameters:
 *  ftwInterval - FTW counter interval.
@@ -1465,7 +1519,7 @@ void CyPmOppsSet(void)
 *  None
 *
 * Side Effects:
-*  Enables ILO 100 KHz clock and leaves it enabled.
+*  Enables the ILO 100 KHz clock and leaves it enabled.
 *
 *******************************************************************************/
 void CyPmFtwSetInterval(uint8 ftwInterval) 
@@ -1476,13 +1530,13 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
     /* Enable 100kHz ILO */
     CyILO_Start100K();
 
-    /* Iterval could be set only while FTW is disabled */
+    /* Interval could be set only while FTW is disabled */
     if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))
     {
         /* Disable FTW, set new FTW interval if needed and enable it again */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Disable the CTW, set new CTW interval and enable it again */
+            /* Disable CTW, set new CTW interval and enable it again */
             CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));
             CY_PM_TW_CFG0_REG = ftwInterval;
             CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
@@ -1493,11 +1547,11 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
         /* Set new FTW counter interval if needed. FTW is disabled. */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG0_REG = ftwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the FTW */
+        /* Enable FTW */
         CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
     }
 }
@@ -1508,12 +1562,12 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for preparing device for Sleep and Hibernate low power
+*  This API is used for preparing the device for the Sleep and Hibernate low power
 *  modes entry:
-*  - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)
-*  - Saves SC/CT routing connections (PSoC 3/5/5LP)
-*  - Disables Serial Wire Viewer (SWV) (PSoC 3)
-*  - Save boost reference selection and set it to internal
+*  - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)
+*  - Saves the SC/CT routing connections (PSoC 3/5/5LP)
+*  - Disables the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Saves the boost reference selection and sets it to internal
 *
 * Parameters:
 *  None
@@ -1643,11 +1697,11 @@ static void CyPmHibSlpSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for restoring device configurations after wakeup from Sleep
+*  This API is used for restoring the device configurations after wakeup from the Sleep
 *  and Hibernate low power modes:
-*  - Restores SC/CT routing connections
-*  - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)
-*  - Restore boost reference selection
+*  - Restores the SC/CT routing connections
+*  - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Restores the  boost reference selection
 *
 * Parameters:
 *  None
@@ -1740,7 +1794,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lvidEn = CY_PM_ENABLED;
         cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;
 
-        /* Save state of reset device at a specified Vddd threshold */
+        /* Save state of reset device at specified Vddd threshold */
         cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1756,7 +1810,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lviaEn = CY_PM_ENABLED;
         cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;
 
-        /* Save state of reset device at a specified Vdda threshold */
+        /* Save state of reset device at specified Vdda threshold */
         cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1784,7 +1838,7 @@ static void CyPmHviLviSaveDisable(void)
 ********************************************************************************
 *
 * Summary:
-*  Restores analog and digital LVI and HVI configuration.
+*  Restores the analog and digital LVI and HVI configuration.
 *
 * Parameters:
 *  None
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h
index bfa22143..0110c377 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the power management API.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -54,7 +54,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC3)
 
-    /* Wake up time for the Sleep mode */
+    /* Wake up time for Sleep mode */
     #define PM_SLEEP_TIME_ONE_PPS           (0x01u)
     #define PM_SLEEP_TIME_CTW_2MS           (0x02u)
     #define PM_SLEEP_TIME_CTW_4MS           (0x03u)
@@ -72,7 +72,7 @@ void CyPmOppsSet(void) ;
     /* Difference between parameter's value and register's one */
     #define CY_PM_FTW_INTERVAL_SHIFT        (0x000Eu)
 
-    /* Wake up time for the Alternate Active mode */
+    /* Wake up time for Alternate Active mode */
     #define PM_ALT_ACT_TIME_ONE_PPS         (0x0001u)
     #define PM_ALT_ACT_TIME_CTW_2MS         (0x0002u)
     #define PM_ALT_ACT_TIME_CTW_4MS         (0x0003u)
@@ -91,7 +91,7 @@ void CyPmOppsSet(void) ;
 #endif  /* (CY_PSOC3) */
 
 
-/* Wake up sources for the Sleep mode */
+/* Wake up sources for Sleep mode */
 #define PM_SLEEP_SRC_COMPARATOR0        (0x0001u)
 #define PM_SLEEP_SRC_COMPARATOR1        (0x0002u)
 #define PM_SLEEP_SRC_COMPARATOR2        (0x0004u)
@@ -104,7 +104,7 @@ void CyPmOppsSet(void) ;
 #define PM_SLEEP_SRC_ONE_PPS            (0x0800u)
 #define PM_SLEEP_SRC_LCD                (0x1000u)
 
-/* Wake up sources for the Alternate Active mode */
+/* Wake up sources for Alternate Active mode */
 #define PM_ALT_ACT_SRC_COMPARATOR0      (0x0001u)
 #define PM_ALT_ACT_SRC_COMPARATOR1      (0x0002u)
 #define PM_ALT_ACT_SRC_COMPARATOR2      (0x0004u)
@@ -145,7 +145,7 @@ void CyPmOppsSet(void) ;
 #define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (5u)
 
 
-/* Delay line bandgap current settling time starting from a wakeup event */
+/* Delay line bandgap current settling time starting from wakeup event */
 #define     CY_PM_CLK_DELAY_BANDGAP_SETTLE_US       (50u)
 
 /* Delay line internal bias settling */
@@ -177,7 +177,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC5)
 
-    /* The CPU clock is directly derived from bus clock */
+    /* CPU clock is directly derived from bus clock */
     #define     CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])
 
 #endif  /* (CY_PSOC5) */
@@ -186,7 +186,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low
 * power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI
 * instruction into the instruction stream generated by the compiler. The GCC
 * compiler has to execute assembly language instruction.
 *******************************************************************************/
@@ -219,7 +219,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * This macro defines the IMO frequency that will be set by CyPmSaveClocks()
 * function based on Enable Fast IMO during Startup option from the DWR file.
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the
 * low power mode and restore IMO back to the value set by CyPmSaveClocks()
 * immediately on wakeup.
 *******************************************************************************/
@@ -243,7 +243,7 @@ typedef struct cyPmClockBackupStruct
     /* CyPmSaveClocks()/CyPmRestoreClocks() */
     uint8  enClkA;              /* Analog clocks enable         */
     uint8  enClkD;              /* Digital clocks enable        */
-    uint8  masterClkSrc;        /* The Master clock source      */
+    uint8  masterClkSrc;        /* Master clock source          */
     uint8  imoFreq;             /* IMO frequency (reg's value)  */
     uint8  imoUsbClk;           /* IMO USB CLK (reg's value)    */
     uint8  flashWaitCycles;     /* Flash wait cycles            */
@@ -252,7 +252,7 @@ typedef struct cyPmClockBackupStruct
     uint8  clkImoSrc;
     uint8  imo2x;               /* IMO doubler enable state     */
     uint8  clkSyncDiv;          /* Master clk divider           */
-    uint16 clkBusDiv;           /* The clk_bus divider          */
+    uint16 clkBusDiv;           /* clk_bus divider              */
     uint8  pllEnableState;      /* PLL enable state             */
     uint8  xmhzEnableState;     /* XM HZ enable state           */
     uint8  clkDistDelay;        /* Delay for clk_bus and ACLKs  */
@@ -472,6 +472,14 @@ typedef struct cyPmBackupStruct
 #define CY_PM_BOOST_CR2_REG           (* (reg8 *) CYREG_BOOST_CR2 )
 #define CY_PM_BOOST_CR2_PTR           (  (reg8 *) CYREG_BOOST_CR2 )
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_REG           (* (reg8 *) CYREG_INTC_CSR_EN )
+    #define CY_PM_INTC_CSR_EN_PTR           (  (reg8 *) CYREG_INTC_CSR_EN )
+
+#endif  /* (CY_PSOC3) */
+
 
 /***************************************
 * Register Constants
@@ -521,7 +529,12 @@ typedef struct cyPmBackupStruct
 #define CY_PM_CLKDIST_IMO_OUT_IMO       (0x00u)
 #define CY_PM_CLKDIST_IMO2X_SRC         (0x40u)
 
-/* Waiting for the hibernate/sleep regulator to stabilize */
+#define CY_PM_CLKDIST_PLL_SRC_MASK      (0x03u)
+#define CY_PM_CLKDIST_PLL_SRC_IMO       (0x00u)
+#define CY_PM_CLKDIST_PLL_SRC_XTAL      (0x01u)
+#define CY_PM_CLKDIST_PLL_SRC_DSI       (0x02u)
+
+/* Waiting for hibernate/sleep regulator to stabilize */
 #define CY_PM_MODE_CSR_PWRUP_PULSE_Q    (0x08u)
 
 #define CY_PM_MODE_CSR_ACTIVE           (0x00u)     /* Active power mode      */
@@ -533,10 +546,10 @@ typedef struct cyPmBackupStruct
 /* I2C regulator backup enable */
 #define CY_PM_PWRSYS_CR1_I2CREG_BACKUP  (0x04u)
 
-/* When set, prepares the system to disable the LDO-A */
+/* When set, prepares system to disable LDO-A */
 #define CY_PM_PWRSYS_CR1_LDOA_ISO       (0x01u)
 
-/* When set, disables the analog LDO regulator */
+/* When set, disables analog LDO regulator */
 #define CY_PM_PWRSYS_CR1_LDOA_DIS       (0x02u)
 
 #define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET  (0x04u)
@@ -554,19 +567,19 @@ typedef struct cyPmBackupStruct
 /* Bus Clock divider to divide-by-one */
 #define CY_PM_BUS_CLK_DIV_BY_ONE        (0x00u)
 
-/* HVI/LVI feature on the external analog and digital supply mask */
+/* HVI/LVI feature on external analog and digital supply mask */
 #define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)
 
-/* The high-voltage-interrupt feature on the external analog supply */
+/* High-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_HVIA_EN         (0x04u)
 
-/* The low-voltage-interrupt feature on the external analog supply */
+/* Low-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_LVIA_EN         (0x02u)
 
-/* The low-voltage-interrupt feature on the external digital supply */
+/* Low-voltage-interrupt feature on external digital supply */
 #define CY_PM_RESET_CR1_LVID_EN         (0x01u)
 
-/* Allows the system to program delays on clk_sync_d */
+/* Allows system to program delays on clk_sync_d */
 #define CY_PM_CLKDIST_DELAY_EN          (0x04u)
 
 
@@ -595,7 +608,7 @@ typedef struct cyPmBackupStruct
 #endif  /* (CY_PSOC3) */
 
 
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+/* Disables sleep regulator and shorts vccd to vpwrsleep */
 #define CY_PM_PWRSYS_SLP_TR_BYPASS          (0x10u)
 
 /* Boost Control 2: Select external precision reference */
@@ -615,9 +628,37 @@ typedef struct cyPmBackupStruct
 
 #endif  /* (CY_PSOC5) */
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_CLK       (0x01u)
+
+#endif  /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of
+* whether lock is subsequently lost) until it is read. Upon reading it will
+* clear. If lock is still true then the bit will simply set again. If lock
+* happens to be false when the clear on read occurs then the bit will stay
+* cleared until the next lock event.
+*******************************************************************************/
+#define CY_PM_FASTCLK_PLL_LOCKED       (0x01u)
+
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #if(CY_PSOC3)
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h
old mode 100755
new mode 100644
index 5f1b198d..d5394a10
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h
old mode 100755
new mode 100644
index e2c0687f..023cea0d
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
old mode 100755
new mode 100644
index 1776ef90..b5460484
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
old mode 100755
new mode 100644
index 3c24869c..dfe5fca5
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
old mode 100755
new mode 100644
index e4f1a443..8c2cb7d6
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
old mode 100755
new mode 100644
index ebd1b1dc..6481aaf0
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc
old mode 100755
new mode 100644
index 4ed74edd..189d0303
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
old mode 100755
new mode 100644
index d4d800c6..7c853db5
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h
old mode 100755
new mode 100644
index c8ba6468..1ecfa692
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -3,6 +3,16 @@
 #include <cydevice.h>
 #include <cydevice_trm.h>
 
+/* USBFS_arb_int */
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_arb_int__INTC_MASK 0x400000u
+#define USBFS_arb_int__INTC_NUMBER 22u
+#define USBFS_arb_int__INTC_PRIOR_NUM 7u
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
 /* USBFS_bus_reset */
 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@@ -13,15 +23,111 @@
 #define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* USBFS_arb_int */
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_arb_int__INTC_MASK 0x400000u
-#define USBFS_arb_int__INTC_NUMBER 22u
-#define USBFS_arb_int__INTC_PRIOR_NUM 7u
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* USBFS_Dm */
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x01u
+#define USBFS_ep_1__INTC_NUMBER 0u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x02u
+#define USBFS_ep_2__INTC_NUMBER 1u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 #define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -33,528 +139,6 @@
 #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x08u
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3
-#define SCSI_Out_DBx__0__PORT 6u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__0__SHIFT 3
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x04u
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2
-#define SCSI_Out_DBx__1__PORT 6u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__1__SHIFT 2
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__2__MASK 0x02u
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1
-#define SCSI_Out_DBx__2__PORT 6u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__2__SHIFT 1
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x01u
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0
-#define SCSI_Out_DBx__3__PORT 6u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__3__SHIFT 0
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x80u
-#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7
-#define SCSI_Out_DBx__4__PORT 4u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__4__SHIFT 7
-#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x40u
-#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6
-#define SCSI_Out_DBx__5__PORT 4u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__5__SHIFT 6
-#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x20u
-#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5
-#define SCSI_Out_DBx__6__PORT 4u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__6__SHIFT 5
-#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x10u
-#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4
-#define SCSI_Out_DBx__7__PORT 4u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__7__SHIFT 4
-#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x08u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3
-#define SCSI_Out_DBx__DB0__PORT 6u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB0__SHIFT 3
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x04u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2
-#define SCSI_Out_DBx__DB1__PORT 6u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB1__SHIFT 2
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB2__MASK 0x02u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1
-#define SCSI_Out_DBx__DB2__PORT 6u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB2__SHIFT 1
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x01u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0
-#define SCSI_Out_DBx__DB3__PORT 6u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB3__SHIFT 0
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x80u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7
-#define SCSI_Out_DBx__DB4__PORT 4u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB4__SHIFT 7
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x40u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6
-#define SCSI_Out_DBx__DB5__PORT 4u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB5__SHIFT 6
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x20u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5
-#define SCSI_Out_DBx__DB6__PORT 4u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB6__SHIFT 5
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x10u
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4
-#define SCSI_Out_DBx__DB7__PORT 4u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS
-#define SCSI_Out_DBx__DB7__SHIFT 4
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x01u
-#define USBFS_ep_1__INTC_NUMBER 0u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x02u
-#define USBFS_ep_2__INTC_NUMBER 1u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-#define SD_PULLUP__0__MASK 0x02u
-#define SD_PULLUP__0__PC CYREG_PRT3_PC1
-#define SD_PULLUP__0__PORT 3u
-#define SD_PULLUP__0__SHIFT 1
-#define SD_PULLUP__1__MASK 0x04u
-#define SD_PULLUP__1__PC CYREG_PRT3_PC2
-#define SD_PULLUP__1__PORT 3u
-#define SD_PULLUP__1__SHIFT 2
-#define SD_PULLUP__2__MASK 0x08u
-#define SD_PULLUP__2__PC CYREG_PRT3_PC3
-#define SD_PULLUP__2__PORT 3u
-#define SD_PULLUP__2__SHIFT 3
-#define SD_PULLUP__3__MASK 0x10u
-#define SD_PULLUP__3__PC CYREG_PRT3_PC4
-#define SD_PULLUP__3__PORT 3u
-#define SD_PULLUP__3__SHIFT 4
-#define SD_PULLUP__4__MASK 0x20u
-#define SD_PULLUP__4__PC CYREG_PRT3_PC5
-#define SD_PULLUP__4__PORT 3u
-#define SD_PULLUP__4__SHIFT 5
-#define SD_PULLUP__AG CYREG_PRT3_AG
-#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
-#define SD_PULLUP__BIE CYREG_PRT3_BIE
-#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_PULLUP__BYP CYREG_PRT3_BYP
-#define SD_PULLUP__CTL CYREG_PRT3_CTL
-#define SD_PULLUP__DM0 CYREG_PRT3_DM0
-#define SD_PULLUP__DM1 CYREG_PRT3_DM1
-#define SD_PULLUP__DM2 CYREG_PRT3_DM2
-#define SD_PULLUP__DR CYREG_PRT3_DR
-#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_PULLUP__MASK 0x3Eu
-#define SD_PULLUP__PORT 3u
-#define SD_PULLUP__PRT CYREG_PRT3_PRT
-#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_PULLUP__PS CYREG_PRT3_PS
-#define SD_PULLUP__SHIFT 1
-#define SD_PULLUP__SLW CYREG_PRT3_SLW
-
 /* USBFS_USB */
 #define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
 #define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
@@ -632,6 +216,8 @@
 #define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
 #define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
 #define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
 #define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
 #define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
 #define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
@@ -642,13 +228,13 @@
 #define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
 #define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
 #define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
 #define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
 #define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
 #define USBFS_USB__PM_ACT_MSK 0x01u
 #define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
 #define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
 #define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
 #define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
 #define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
@@ -673,13 +259,11 @@
 #define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
 #define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
 #define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
 #define USBFS_USB__SOF0 CYREG_USB_SOF0
 #define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
 #define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
 
 /* SCSI_Out */
 #define SCSI_Out__0__AG CYREG_PRT4_AG
@@ -1223,149 +807,571 @@
 #define SCSI_Out__SEL__SHIFT 3
 #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
+/* SCSI_Out_DBx */
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x08u
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3
+#define SCSI_Out_DBx__0__PORT 6u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__0__SHIFT 3
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x04u
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2
+#define SCSI_Out_DBx__1__PORT 6u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__1__SHIFT 2
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__2__MASK 0x02u
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1
+#define SCSI_Out_DBx__2__PORT 6u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__2__SHIFT 1
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x01u
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0
+#define SCSI_Out_DBx__3__PORT 6u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__3__SHIFT 0
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x80u
+#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7
+#define SCSI_Out_DBx__4__PORT 4u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__4__SHIFT 7
+#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x40u
+#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6
+#define SCSI_Out_DBx__5__PORT 4u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__5__SHIFT 6
+#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x20u
+#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5
+#define SCSI_Out_DBx__6__PORT 4u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__6__SHIFT 5
+#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x10u
+#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4
+#define SCSI_Out_DBx__7__PORT 4u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__7__SHIFT 4
+#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x08u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3
+#define SCSI_Out_DBx__DB0__PORT 6u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB0__SHIFT 3
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x04u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2
+#define SCSI_Out_DBx__DB1__PORT 6u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB1__SHIFT 2
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB2__MASK 0x02u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1
+#define SCSI_Out_DBx__DB2__PORT 6u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB2__SHIFT 1
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x01u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0
+#define SCSI_Out_DBx__DB3__PORT 6u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB3__SHIFT 0
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x80u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7
+#define SCSI_Out_DBx__DB4__PORT 4u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB4__SHIFT 7
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x40u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6
+#define SCSI_Out_DBx__DB5__PORT 4u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB5__SHIFT 6
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x20u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5
+#define SCSI_Out_DBx__DB6__PORT 4u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB6__SHIFT 5
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x10u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4
+#define SCSI_Out_DBx__DB7__PORT 4u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS
+#define SCSI_Out_DBx__DB7__SHIFT 4
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW
 
-/* USBFS_Dp */
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+/* SD_PULLUP */
+#define SD_PULLUP__0__MASK 0x02u
+#define SD_PULLUP__0__PC CYREG_PRT3_PC1
+#define SD_PULLUP__0__PORT 3u
+#define SD_PULLUP__0__SHIFT 1
+#define SD_PULLUP__1__MASK 0x04u
+#define SD_PULLUP__1__PC CYREG_PRT3_PC2
+#define SD_PULLUP__1__PORT 3u
+#define SD_PULLUP__1__SHIFT 2
+#define SD_PULLUP__2__MASK 0x08u
+#define SD_PULLUP__2__PC CYREG_PRT3_PC3
+#define SD_PULLUP__2__PORT 3u
+#define SD_PULLUP__2__SHIFT 3
+#define SD_PULLUP__3__MASK 0x10u
+#define SD_PULLUP__3__PC CYREG_PRT3_PC4
+#define SD_PULLUP__3__PORT 3u
+#define SD_PULLUP__3__SHIFT 4
+#define SD_PULLUP__4__MASK 0x20u
+#define SD_PULLUP__4__PC CYREG_PRT3_PC5
+#define SD_PULLUP__4__PORT 3u
+#define SD_PULLUP__4__SHIFT 5
+#define SD_PULLUP__AG CYREG_PRT3_AG
+#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
+#define SD_PULLUP__BIE CYREG_PRT3_BIE
+#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_PULLUP__BYP CYREG_PRT3_BYP
+#define SD_PULLUP__CTL CYREG_PRT3_CTL
+#define SD_PULLUP__DM0 CYREG_PRT3_DM0
+#define SD_PULLUP__DM1 CYREG_PRT3_DM1
+#define SD_PULLUP__DM2 CYREG_PRT3_DM2
+#define SD_PULLUP__DR CYREG_PRT3_DR
+#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_PULLUP__MASK 0x3Eu
+#define SD_PULLUP__PORT 3u
+#define SD_PULLUP__PRT CYREG_PRT3_PRT
+#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_PULLUP__PS CYREG_PRT3_PS
+#define SD_PULLUP__SHIFT 1
+#define SD_PULLUP__SLW CYREG_PRT3_SLW
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
-#define CYDEV_CHIP_MEMBER_5B 4u
-#define CYDEV_CHIP_FAMILY_PSOC5 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 4u
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
-#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1
 #define BCLK__BUS_CLK__HZ 64000000U
 #define BCLK__BUS_CLK__KHZ 64000U
 #define BCLK__BUS_CLK__MHZ 64U
+#define CY_VERSION "PSoC Creator  3.1"
 #define CYDEV_BOOTLOADER_APPLICATIONS 1u
 #define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
 #define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
+#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
+#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1
+#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
 #define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 3u
-#define CYDEV_CHIP_DIE_PSOC4A 2u
+#define CYDEV_CHIP_DIE_PANTHER 6u
+#define CYDEV_CHIP_DIE_PSOC4A 3u
+#define CYDEV_CHIP_DIE_PSOC5LP 5u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
+#define CYDEV_CHIP_FAMILY_PSOC5 3u
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 2u
-#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_4A 3u
+#define CYDEV_CHIP_MEMBER_4D 2u
+#define CYDEV_CHIP_MEMBER_4F 4u
+#define CYDEV_CHIP_MEMBER_5A 6u
+#define CYDEV_CHIP_MEMBER_5B 5u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_3A_ES1 0u
 #define CYDEV_CHIP_REVISION_3A_ES2 1u
 #define CYDEV_CHIP_REVISION_3A_ES3 3u
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
 #define CYDEV_CHIP_REVISION_5B_ES0 0u
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
 #define CYDEV_CONFIGURATION_COMPRESSED 1
 #define CYDEV_CONFIGURATION_DMA 0
 #define CYDEV_CONFIGURATION_ECC 0
 #define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
 #define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
 #define CYDEV_CONFIGURATION_MODE_DMA 2
 #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DEBUGGING_DPS_Disable 3
 #define CYDEV_DEBUGGING_DPS_JTAG_4 1
 #define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
 #define CYDEV_DEBUGGING_ENABLE 1
 #define CYDEV_DEBUGGING_XRES 0
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DMA_CHANNELS_AVAILABLE 24u
 #define CYDEV_ECC_ENABLE 0
 #define CYDEV_HEAP_SIZE 0x0800
@@ -1393,16 +1399,34 @@
 #define CYDEV_VDDIO2_MV 5000
 #define CYDEV_VDDIO3 5.0
 #define CYDEV_VDDIO3_MV 5000
-#define CYDEV_VIO0 5
+#define CYDEV_VIO0 5.0
 #define CYDEV_VIO0_MV 5000
-#define CYDEV_VIO1 5
+#define CYDEV_VIO1 5.0
 #define CYDEV_VIO1_MV 5000
-#define CYDEV_VIO2 5
+#define CYDEV_VIO2 5.0
 #define CYDEV_VIO2_MV 5000
-#define CYDEV_VIO3 5
+#define CYDEV_VIO3 5.0
 #define CYDEV_VIO3_MV 5000
-#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
+#define CYIPBLOCK_ARM_CM3_VERSION 0
+#define CYIPBLOCK_P3_ANAIF_VERSION 0
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
+#define CYIPBLOCK_P3_COMP_VERSION 0
+#define CYIPBLOCK_P3_DMA_VERSION 0
+#define CYIPBLOCK_P3_DRQ_VERSION 0
+#define CYIPBLOCK_P3_EMIF_VERSION 0
+#define CYIPBLOCK_P3_I2C_VERSION 0
+#define CYIPBLOCK_P3_LCD_VERSION 0
+#define CYIPBLOCK_P3_LPF_VERSION 0
+#define CYIPBLOCK_P3_PM_VERSION 0
+#define CYIPBLOCK_P3_TIMER_VERSION 0
+#define CYIPBLOCK_P3_USB_VERSION 0
+#define CYIPBLOCK_P3_VIDAC_VERSION 0
+#define CYIPBLOCK_P3_VREF_VERSION 0
+#define CYIPBLOCK_S8_GPIO_VERSION 0
+#define CYIPBLOCK_S8_IRQ_VERSION 0
+#define CYIPBLOCK_S8_SAR_VERSION 0
+#define CYIPBLOCK_S8_SIO_VERSION 0
+#define CYIPBLOCK_S8_UDB_VERSION 0
 #define DMA_CHANNELS_USED__MASK0 0x00000000u
 #define CYDEV_BOOTLOADER_ENABLE 1
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
old mode 100755
new mode 100644
index 361d24a1..690329ed
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator with device 
@@ -403,7 +403,7 @@ void cyfitter_cfg(void)
 		for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
 		{
 			const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
-			CYMEMZERO(ms->address, (uint32)(ms->size));
+			CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
 		}
 
 		cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
old mode 100755
new mode 100644
index 9481fd38..e4e1caf5
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
old mode 100755
new mode 100644
index e370ffad..28238381
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -3,6 +3,16 @@
 .include "cydevicegnu.inc"
 .include "cydevicegnu_trm.inc"
 
+/* USBFS_arb_int */
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_arb_int__INTC_MASK, 0x400000
+.set USBFS_arb_int__INTC_NUMBER, 22
+.set USBFS_arb_int__INTC_PRIOR_NUM, 7
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
 /* USBFS_bus_reset */
 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@@ -13,15 +23,111 @@
 .set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* USBFS_arb_int */
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_arb_int__INTC_MASK, 0x400000
-.set USBFS_arb_int__INTC_NUMBER, 22
-.set USBFS_arb_int__INTC_PRIOR_NUM, 7
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* USBFS_Dm */
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x01
+.set USBFS_ep_1__INTC_NUMBER, 0
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x02
+.set USBFS_ep_2__INTC_NUMBER, 1
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -33,528 +139,6 @@
 .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x08
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3
-.set SCSI_Out_DBx__0__PORT, 6
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__0__SHIFT, 3
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x04
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2
-.set SCSI_Out_DBx__1__PORT, 6
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__1__SHIFT, 2
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__2__MASK, 0x02
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1
-.set SCSI_Out_DBx__2__PORT, 6
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__2__SHIFT, 1
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x01
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0
-.set SCSI_Out_DBx__3__PORT, 6
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__3__SHIFT, 0
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x80
-.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7
-.set SCSI_Out_DBx__4__PORT, 4
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__4__SHIFT, 7
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x40
-.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6
-.set SCSI_Out_DBx__5__PORT, 4
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__5__SHIFT, 6
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x20
-.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5
-.set SCSI_Out_DBx__6__PORT, 4
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__6__SHIFT, 5
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x10
-.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4
-.set SCSI_Out_DBx__7__PORT, 4
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__7__SHIFT, 4
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x08
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3
-.set SCSI_Out_DBx__DB0__PORT, 6
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 3
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x04
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2
-.set SCSI_Out_DBx__DB1__PORT, 6
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 2
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB2__MASK, 0x02
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1
-.set SCSI_Out_DBx__DB2__PORT, 6
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 1
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x01
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0
-.set SCSI_Out_DBx__DB3__PORT, 6
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 0
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x80
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7
-.set SCSI_Out_DBx__DB4__PORT, 4
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 7
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x40
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6
-.set SCSI_Out_DBx__DB5__PORT, 4
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 6
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x20
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5
-.set SCSI_Out_DBx__DB6__PORT, 4
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 5
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x10
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4
-.set SCSI_Out_DBx__DB7__PORT, 4
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 4
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x01
-.set USBFS_ep_1__INTC_NUMBER, 0
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x02
-.set USBFS_ep_2__INTC_NUMBER, 1
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-.set SD_PULLUP__0__MASK, 0x02
-.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
-.set SD_PULLUP__0__PORT, 3
-.set SD_PULLUP__0__SHIFT, 1
-.set SD_PULLUP__1__MASK, 0x04
-.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
-.set SD_PULLUP__1__PORT, 3
-.set SD_PULLUP__1__SHIFT, 2
-.set SD_PULLUP__2__MASK, 0x08
-.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
-.set SD_PULLUP__2__PORT, 3
-.set SD_PULLUP__2__SHIFT, 3
-.set SD_PULLUP__3__MASK, 0x10
-.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
-.set SD_PULLUP__3__PORT, 3
-.set SD_PULLUP__3__SHIFT, 4
-.set SD_PULLUP__4__MASK, 0x20
-.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
-.set SD_PULLUP__4__PORT, 3
-.set SD_PULLUP__4__SHIFT, 5
-.set SD_PULLUP__AG, CYREG_PRT3_AG
-.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX
-.set SD_PULLUP__BIE, CYREG_PRT3_BIE
-.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_PULLUP__BYP, CYREG_PRT3_BYP
-.set SD_PULLUP__CTL, CYREG_PRT3_CTL
-.set SD_PULLUP__DM0, CYREG_PRT3_DM0
-.set SD_PULLUP__DM1, CYREG_PRT3_DM1
-.set SD_PULLUP__DM2, CYREG_PRT3_DM2
-.set SD_PULLUP__DR, CYREG_PRT3_DR
-.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_PULLUP__MASK, 0x3E
-.set SD_PULLUP__PORT, 3
-.set SD_PULLUP__PRT, CYREG_PRT3_PRT
-.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_PULLUP__PS, CYREG_PRT3_PS
-.set SD_PULLUP__SHIFT, 1
-.set SD_PULLUP__SLW, CYREG_PRT3_SLW
-
 /* USBFS_USB */
 .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
 .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
@@ -632,6 +216,8 @@
 .set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
 .set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
 .set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
 .set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
 .set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
 .set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
@@ -642,13 +228,13 @@
 .set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
 .set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
 .set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
 .set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
 .set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
 .set USBFS_USB__PM_ACT_MSK, 0x01
 .set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
 .set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
 .set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
 .set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
 .set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
@@ -673,13 +259,11 @@
 .set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
 .set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
 .set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
 .set USBFS_USB__SOF0, CYREG_USB_SOF0
 .set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
 .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
 
 /* SCSI_Out */
 .set SCSI_Out__0__AG, CYREG_PRT4_AG
@@ -1223,149 +807,570 @@
 .set SCSI_Out__SEL__SHIFT, 3
 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+/* SCSI_Out_DBx */
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x08
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3
+.set SCSI_Out_DBx__0__PORT, 6
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__0__SHIFT, 3
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x04
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2
+.set SCSI_Out_DBx__1__PORT, 6
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__1__SHIFT, 2
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__2__MASK, 0x02
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1
+.set SCSI_Out_DBx__2__PORT, 6
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__2__SHIFT, 1
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x01
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0
+.set SCSI_Out_DBx__3__PORT, 6
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__3__SHIFT, 0
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x80
+.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7
+.set SCSI_Out_DBx__4__PORT, 4
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__4__SHIFT, 7
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x40
+.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6
+.set SCSI_Out_DBx__5__PORT, 4
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__5__SHIFT, 6
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x20
+.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5
+.set SCSI_Out_DBx__6__PORT, 4
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__6__SHIFT, 5
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x10
+.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4
+.set SCSI_Out_DBx__7__PORT, 4
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__7__SHIFT, 4
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x08
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3
+.set SCSI_Out_DBx__DB0__PORT, 6
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 3
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x04
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2
+.set SCSI_Out_DBx__DB1__PORT, 6
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 2
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB2__MASK, 0x02
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1
+.set SCSI_Out_DBx__DB2__PORT, 6
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 1
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x01
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0
+.set SCSI_Out_DBx__DB3__PORT, 6
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 0
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x80
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7
+.set SCSI_Out_DBx__DB4__PORT, 4
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 7
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x40
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6
+.set SCSI_Out_DBx__DB5__PORT, 4
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 6
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x20
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5
+.set SCSI_Out_DBx__DB6__PORT, 4
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 5
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x10
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4
+.set SCSI_Out_DBx__DB7__PORT, 4
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 4
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW
 
-/* USBFS_Dp */
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+/* SD_PULLUP */
+.set SD_PULLUP__0__MASK, 0x02
+.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
+.set SD_PULLUP__0__PORT, 3
+.set SD_PULLUP__0__SHIFT, 1
+.set SD_PULLUP__1__MASK, 0x04
+.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
+.set SD_PULLUP__1__PORT, 3
+.set SD_PULLUP__1__SHIFT, 2
+.set SD_PULLUP__2__MASK, 0x08
+.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
+.set SD_PULLUP__2__PORT, 3
+.set SD_PULLUP__2__SHIFT, 3
+.set SD_PULLUP__3__MASK, 0x10
+.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
+.set SD_PULLUP__3__PORT, 3
+.set SD_PULLUP__3__SHIFT, 4
+.set SD_PULLUP__4__MASK, 0x20
+.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
+.set SD_PULLUP__4__PORT, 3
+.set SD_PULLUP__4__SHIFT, 5
+.set SD_PULLUP__AG, CYREG_PRT3_AG
+.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX
+.set SD_PULLUP__BIE, CYREG_PRT3_BIE
+.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_PULLUP__BYP, CYREG_PRT3_BYP
+.set SD_PULLUP__CTL, CYREG_PRT3_CTL
+.set SD_PULLUP__DM0, CYREG_PRT3_DM0
+.set SD_PULLUP__DM1, CYREG_PRT3_DM1
+.set SD_PULLUP__DM2, CYREG_PRT3_DM2
+.set SD_PULLUP__DR, CYREG_PRT3_DR
+.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_PULLUP__MASK, 0x3E
+.set SD_PULLUP__PORT, 3
+.set SD_PULLUP__PRT, CYREG_PRT3_PRT
+.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_PULLUP__PS, CYREG_PRT3_PS
+.set SD_PULLUP__SHIFT, 1
+.set SD_PULLUP__SLW, CYREG_PRT3_SLW
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
-.set CYDEV_CHIP_MEMBER_5B, 4
-.set CYDEV_CHIP_FAMILY_PSOC5, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 4
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
-.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1
 .set BCLK__BUS_CLK__HZ, 64000000
 .set BCLK__BUS_CLK__KHZ, 64000
 .set BCLK__BUS_CLK__MHZ, 64
 .set CYDEV_BOOTLOADER_APPLICATIONS, 1
 .set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0
 .set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1
+.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0
+.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1
+.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
 .set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 3
-.set CYDEV_CHIP_DIE_PSOC4A, 2
+.set CYDEV_CHIP_DIE_PANTHER, 6
+.set CYDEV_CHIP_DIE_PSOC4A, 3
+.set CYDEV_CHIP_DIE_PSOC5LP, 5
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
+.set CYDEV_CHIP_FAMILY_PSOC5, 3
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 2
-.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_4A, 3
+.set CYDEV_CHIP_MEMBER_4D, 2
+.set CYDEV_CHIP_MEMBER_4F, 4
+.set CYDEV_CHIP_MEMBER_5A, 6
+.set CYDEV_CHIP_MEMBER_5B, 5
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_3A_ES1, 0
 .set CYDEV_CHIP_REVISION_3A_ES2, 1
 .set CYDEV_CHIP_REVISION_3A_ES3, 3
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
 .set CYDEV_CHIP_REVISION_5B_ES0, 0
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
 .set CYDEV_CONFIGURATION_COMPRESSED, 1
 .set CYDEV_CONFIGURATION_DMA, 0
 .set CYDEV_CONFIGURATION_ECC, 0
 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
 .set CYDEV_CONFIGURATION_MODE_DMA, 2
 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DEBUGGING_DPS_Disable, 3
 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1
 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
 .set CYDEV_DEBUGGING_ENABLE, 1
 .set CYDEV_DEBUGGING_XRES, 0
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24
 .set CYDEV_ECC_ENABLE, 0
 .set CYDEV_HEAP_SIZE, 0x0800
@@ -1387,16 +1392,30 @@
 .set CYDEV_VDDIO1_MV, 5000
 .set CYDEV_VDDIO2_MV, 5000
 .set CYDEV_VDDIO3_MV, 5000
-.set CYDEV_VIO0, 5
 .set CYDEV_VIO0_MV, 5000
-.set CYDEV_VIO1, 5
 .set CYDEV_VIO1_MV, 5000
-.set CYDEV_VIO2, 5
 .set CYDEV_VIO2_MV, 5000
-.set CYDEV_VIO3, 5
 .set CYDEV_VIO3_MV, 5000
-.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
+.set CYIPBLOCK_ARM_CM3_VERSION, 0
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
+.set CYIPBLOCK_P3_COMP_VERSION, 0
+.set CYIPBLOCK_P3_DMA_VERSION, 0
+.set CYIPBLOCK_P3_DRQ_VERSION, 0
+.set CYIPBLOCK_P3_EMIF_VERSION, 0
+.set CYIPBLOCK_P3_I2C_VERSION, 0
+.set CYIPBLOCK_P3_LCD_VERSION, 0
+.set CYIPBLOCK_P3_LPF_VERSION, 0
+.set CYIPBLOCK_P3_PM_VERSION, 0
+.set CYIPBLOCK_P3_TIMER_VERSION, 0
+.set CYIPBLOCK_P3_USB_VERSION, 0
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0
+.set CYIPBLOCK_P3_VREF_VERSION, 0
+.set CYIPBLOCK_S8_GPIO_VERSION, 0
+.set CYIPBLOCK_S8_IRQ_VERSION, 0
+.set CYIPBLOCK_S8_SAR_VERSION, 0
+.set CYIPBLOCK_S8_SIO_VERSION, 0
+.set CYIPBLOCK_S8_UDB_VERSION, 0
 .set DMA_CHANNELS_USED__MASK0, 0x00000000
 .set CYDEV_BOOTLOADER_ENABLE, 1
 .endif
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
old mode 100755
new mode 100644
index fb84c624..708bf910
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -3,6 +3,16 @@
     INCLUDE cydeviceiar.inc
     INCLUDE cydeviceiar_trm.inc
 
+/* USBFS_arb_int */
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
 /* USBFS_bus_reset */
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@@ -13,15 +23,111 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* USBFS_arb_int */
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* USBFS_Dm */
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x01
+USBFS_ep_1__INTC_NUMBER EQU 0
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x02
+USBFS_ep_2__INTC_NUMBER EQU 1
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -33,528 +139,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x08
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__0__PORT EQU 6
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__0__SHIFT EQU 3
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x04
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__1__PORT EQU 6
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__1__SHIFT EQU 2
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x02
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 1
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x01
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 0
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__4__PORT EQU 4
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__5__PORT EQU 4
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x20
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__6__PORT EQU 4
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__6__SHIFT EQU 5
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x10
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__7__PORT EQU 4
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__7__SHIFT EQU 4
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x08
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__DB0__PORT EQU 6
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 3
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x04
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__DB1__PORT EQU 6
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 2
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x02
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 1
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x01
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 0
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__DB4__PORT EQU 4
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__DB5__PORT EQU 4
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x20
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__DB6__PORT EQU 4
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 5
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x10
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__DB7__PORT EQU 4
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 4
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x01
-USBFS_ep_1__INTC_NUMBER EQU 0
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x02
-USBFS_ep_2__INTC_NUMBER EQU 1
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-SD_PULLUP__0__MASK EQU 0x02
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
-SD_PULLUP__0__PORT EQU 3
-SD_PULLUP__0__SHIFT EQU 1
-SD_PULLUP__1__MASK EQU 0x04
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
-SD_PULLUP__1__PORT EQU 3
-SD_PULLUP__1__SHIFT EQU 2
-SD_PULLUP__2__MASK EQU 0x08
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
-SD_PULLUP__2__PORT EQU 3
-SD_PULLUP__2__SHIFT EQU 3
-SD_PULLUP__3__MASK EQU 0x10
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
-SD_PULLUP__3__PORT EQU 3
-SD_PULLUP__3__SHIFT EQU 4
-SD_PULLUP__4__MASK EQU 0x20
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
-SD_PULLUP__4__PORT EQU 3
-SD_PULLUP__4__SHIFT EQU 5
-SD_PULLUP__AG EQU CYREG_PRT3_AG
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
-SD_PULLUP__DR EQU CYREG_PRT3_DR
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_PULLUP__MASK EQU 0x3E
-SD_PULLUP__PORT EQU 3
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_PULLUP__PS EQU CYREG_PRT3_PS
-SD_PULLUP__SHIFT EQU 1
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW
-
 /* USBFS_USB */
 USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
 USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
@@ -632,6 +216,8 @@ USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
 USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
 USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
 USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
 USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
 USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
@@ -642,13 +228,13 @@ USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
 USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
 USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
 USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
 USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
 USBFS_USB__PM_ACT_MSK EQU 0x01
 USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
 USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
 USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
 USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
@@ -673,13 +259,11 @@ USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
 USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
 USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
 USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SOF0 EQU CYREG_USB_SOF0
 USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 
 /* SCSI_Out */
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
@@ -1223,149 +807,570 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
 SCSI_Out__SEL__SHIFT EQU 3
 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x08
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__0__PORT EQU 6
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__0__SHIFT EQU 3
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x04
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__1__PORT EQU 6
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__1__SHIFT EQU 2
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x02
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 1
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x01
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 0
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__4__PORT EQU 4
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__5__PORT EQU 4
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x20
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__6__PORT EQU 4
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__6__SHIFT EQU 5
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x10
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__7__PORT EQU 4
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__7__SHIFT EQU 4
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x08
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__DB0__PORT EQU 6
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 3
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x04
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__DB1__PORT EQU 6
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 2
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x02
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 1
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x01
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 0
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__DB4__PORT EQU 4
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__DB5__PORT EQU 4
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x20
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__DB6__PORT EQU 4
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 5
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x10
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__DB7__PORT EQU 4
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 4
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
 
-/* USBFS_Dp */
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+/* SD_PULLUP */
+SD_PULLUP__0__MASK EQU 0x02
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
+SD_PULLUP__0__PORT EQU 3
+SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__MASK EQU 0x04
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
+SD_PULLUP__1__PORT EQU 3
+SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__MASK EQU 0x08
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
+SD_PULLUP__2__PORT EQU 3
+SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__MASK EQU 0x10
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
+SD_PULLUP__3__PORT EQU 3
+SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__MASK EQU 0x20
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
+SD_PULLUP__4__PORT EQU 3
+SD_PULLUP__4__SHIFT EQU 5
+SD_PULLUP__AG EQU CYREG_PRT3_AG
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
+SD_PULLUP__DR EQU CYREG_PRT3_DR
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_PULLUP__MASK EQU 0x3E
+SD_PULLUP__PORT EQU 3
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_PULLUP__PS EQU CYREG_PRT3_PS
+SD_PULLUP__SHIFT EQU 1
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
 BCLK__BUS_CLK__HZ EQU 64000000
 BCLK__BUS_CLK__KHZ EQU 64000
 BCLK__BUS_CLK__MHZ EQU 64
 CYDEV_BOOTLOADER_APPLICATIONS EQU 1
 CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
 CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
 CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0800
@@ -1387,16 +1392,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 5000
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
-CYDEV_VIO3 EQU 5
 CYDEV_VIO3_MV EQU 5000
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x00000000
 CYDEV_BOOTLOADER_ENABLE EQU 1
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
old mode 100755
new mode 100644
index 2f81aaf1..da1fe2e3
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -3,6 +3,16 @@ INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc
     GET cydevicerv_trm.inc
 
+; USBFS_arb_int
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
 ; USBFS_bus_reset
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@@ -13,15 +23,111 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; USBFS_arb_int
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; USBFS_Dm
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+; USBFS_Dp
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+; USBFS_dp_int
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_1
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x01
+USBFS_ep_1__INTC_NUMBER EQU 0
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_2
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x02
+USBFS_ep_2__INTC_NUMBER EQU 1
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; USBFS_sof_int
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -33,528 +139,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x08
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__0__PORT EQU 6
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__0__SHIFT EQU 3
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x04
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__1__PORT EQU 6
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__1__SHIFT EQU 2
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x02
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 1
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x01
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 0
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__4__PORT EQU 4
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__5__PORT EQU 4
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x20
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__6__PORT EQU 4
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__6__SHIFT EQU 5
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x10
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__7__PORT EQU 4
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__7__SHIFT EQU 4
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x08
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
-SCSI_Out_DBx__DB0__PORT EQU 6
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 3
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x04
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
-SCSI_Out_DBx__DB1__PORT EQU 6
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 2
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x02
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 1
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x01
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 0
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
-SCSI_Out_DBx__DB4__PORT EQU 4
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
-SCSI_Out_DBx__DB5__PORT EQU 4
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x20
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
-SCSI_Out_DBx__DB6__PORT EQU 4
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 5
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x10
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
-SCSI_Out_DBx__DB7__PORT EQU 4
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 4
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x01
-USBFS_ep_1__INTC_NUMBER EQU 0
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x02
-USBFS_ep_2__INTC_NUMBER EQU 1
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_PULLUP
-SD_PULLUP__0__MASK EQU 0x02
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
-SD_PULLUP__0__PORT EQU 3
-SD_PULLUP__0__SHIFT EQU 1
-SD_PULLUP__1__MASK EQU 0x04
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
-SD_PULLUP__1__PORT EQU 3
-SD_PULLUP__1__SHIFT EQU 2
-SD_PULLUP__2__MASK EQU 0x08
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
-SD_PULLUP__2__PORT EQU 3
-SD_PULLUP__2__SHIFT EQU 3
-SD_PULLUP__3__MASK EQU 0x10
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
-SD_PULLUP__3__PORT EQU 3
-SD_PULLUP__3__SHIFT EQU 4
-SD_PULLUP__4__MASK EQU 0x20
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
-SD_PULLUP__4__PORT EQU 3
-SD_PULLUP__4__SHIFT EQU 5
-SD_PULLUP__AG EQU CYREG_PRT3_AG
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
-SD_PULLUP__DR EQU CYREG_PRT3_DR
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_PULLUP__MASK EQU 0x3E
-SD_PULLUP__PORT EQU 3
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_PULLUP__PS EQU CYREG_PRT3_PS
-SD_PULLUP__SHIFT EQU 1
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW
-
 ; USBFS_USB
 USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
 USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
@@ -632,6 +216,8 @@ USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
 USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
 USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
 USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
 USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
 USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
@@ -642,13 +228,13 @@ USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
 USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
 USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
 USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
 USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
 USBFS_USB__PM_ACT_MSK EQU 0x01
 USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
 USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
 USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
 USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
@@ -673,13 +259,11 @@ USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
 USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
 USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
 USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SOF0 EQU CYREG_USB_SOF0
 USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 
 ; SCSI_Out
 SCSI_Out__0__AG EQU CYREG_PRT4_AG
@@ -1223,149 +807,570 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
 SCSI_Out__SEL__SHIFT EQU 3
 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
 
-; USBFS_Dm
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+; SCSI_Out_DBx
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x08
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__0__PORT EQU 6
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__0__SHIFT EQU 3
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x04
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__1__PORT EQU 6
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__1__SHIFT EQU 2
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x02
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 1
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x01
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 0
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__4__PORT EQU 4
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__5__PORT EQU 4
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x20
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__6__PORT EQU 4
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__6__SHIFT EQU 5
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x10
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__7__PORT EQU 4
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__7__SHIFT EQU 4
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x08
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3
+SCSI_Out_DBx__DB0__PORT EQU 6
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 3
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x04
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2
+SCSI_Out_DBx__DB1__PORT EQU 6
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 2
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x02
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 1
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x01
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 0
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7
+SCSI_Out_DBx__DB4__PORT EQU 4
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6
+SCSI_Out_DBx__DB5__PORT EQU 4
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x20
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5
+SCSI_Out_DBx__DB6__PORT EQU 4
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 5
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x10
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4
+SCSI_Out_DBx__DB7__PORT EQU 4
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 4
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW
 
-; USBFS_Dp
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+; SD_PULLUP
+SD_PULLUP__0__MASK EQU 0x02
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
+SD_PULLUP__0__PORT EQU 3
+SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__MASK EQU 0x04
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
+SD_PULLUP__1__PORT EQU 3
+SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__MASK EQU 0x08
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
+SD_PULLUP__2__PORT EQU 3
+SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__MASK EQU 0x10
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
+SD_PULLUP__3__PORT EQU 3
+SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__MASK EQU 0x20
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
+SD_PULLUP__4__PORT EQU 3
+SD_PULLUP__4__SHIFT EQU 5
+SD_PULLUP__AG EQU CYREG_PRT3_AG
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
+SD_PULLUP__DR EQU CYREG_PRT3_DR
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_PULLUP__MASK EQU 0x3E
+SD_PULLUP__PORT EQU 3
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_PULLUP__PS EQU CYREG_PRT3_PS
+SD_PULLUP__SHIFT EQU 1
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW
 
 ; Miscellaneous
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
 BCLK__BUS_CLK__HZ EQU 64000000
 BCLK__BUS_CLK__KHZ EQU 64000
 BCLK__BUS_CLK__MHZ EQU 64
 CYDEV_BOOTLOADER_APPLICATIONS EQU 1
 CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
 CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
 CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0800
@@ -1387,16 +1392,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 5000
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
-CYDEV_VIO3 EQU 5
 CYDEV_VIO3_MV EQU 5000
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x00000000
 CYDEV_BOOTLOADER_ENABLE EQU 1
     ENDIF
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c
old mode 100755
new mode 100644
index a4c9cf07..4efe26bc
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cymetadata.c
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file defines all extra memory spaces that need to be included.
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h
index 3af7484a..a1a727b2 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h
@@ -1,9 +1,9 @@
 /*******************************************************************************
 * File Name: cypins.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   This file contains the function prototypes and constants used for port/pin
+*   This file contains the function prototypes and constants used for a port/pin
 *   in access and control.
 *
 *  Note:
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -103,6 +103,13 @@
 *  Note that this only has an effect for pins configured as software pins that
 *  are not driven by hardware.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16).
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -123,7 +130,14 @@
 ********************************************************************************
 *
 * Summary:
-*  This macro sets the state of the specified pin to 0
+*  This macro sets the state of the specified pin to 0.
+*
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
 *
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
@@ -147,6 +161,13 @@
 * Summary:
 *  Sets the drive mode for the pin (DM).
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16)
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -193,7 +214,7 @@
 *
 *
 * Return:
-*   mode:  Current drive mode for the pin
+*   mode:  The current drive mode for the pin
 *
 *   Define                Source
 *   PIN_DM_ALG_HIZ        Analog HiZ
@@ -214,10 +235,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to fast edge rate.
+*  Set the slew rate for the pin to fast the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -239,10 +267,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to slow edge rate.
+*  Set the slew rate for the pin to slow the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -259,7 +294,18 @@
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)
 #define PC_DRIVE_MODE_MASK  (CY_PINS_PC_DRIVE_MODE_MASK)
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h
index c2a20ad3..d48f29a5 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cytypes.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  CyTypes provides register access macros and approved types for use in
@@ -12,12 +12,12 @@
 *  data the correct way.
 *
 *  Register Access macros and functions perform their operations on an
-*  input of type pointer to void.  The arguments passed to it should be
+*  input of the type pointer to void.  The arguments passed to it should be
 *  pointers to the type associated with the register size.
 *  (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -40,7 +40,7 @@
 
 #if defined( __ICCARM__ )
     /* Suppress warning for multiple volatile variables in an expression. */
-    /* This is common in component code and the usage is not order dependent. */
+    /* This is common in component code and usage is not order dependent. */
     #pragma diag_suppress=Pa082
 #endif  /* defined( __ICCARM__ ) */
 
@@ -61,28 +61,98 @@
 /*******************************************************************************
 * MEMBER encodes both the family and the detailed architecture
 *******************************************************************************/
-#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
 #ifdef CYDEV_CHIP_MEMBER_4D
-    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
 #else
-    #define CY_PSOC4D   (0u != 0u)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (0u != 0u)
 #endif  /* CYDEV_CHIP_MEMBER_4D */
 
-#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
-#ifdef CYDEV_CHIP_MEMBER_5B
-    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#define CY_PSOC4_4100       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#define CY_PSOC4_4200       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+
+#ifdef CYDEV_CHIP_MEMBER_4F
+    #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
+    #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
 #else
-    #define CY_PSOC5LP  (0u != 0u)
-#endif  /* CYDEV_CHIP_MEMBER_5B */
+    #define CY_PSOC4_4100BL (0u != 0u)
+    #define CY_PSOC4_4200BL (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_4F */
 
 
 /*******************************************************************************
-* UDB revisions
+* IP blocks
 *******************************************************************************/
-#define CY_UDB_V0 (CY_PSOC5A)
-#define CY_UDB_V1 (!CY_UDB_V0)
+#if (CY_PSOC4)
+
+    /* Using SRSSv2 or SRS-Lite */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_SRSSV2            (0u == 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #else
+        #define CY_IP_SRSSV2            (0u != 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (0u == 0u)
+    #else
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (!CY_IP_CPUSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Product uses FLASH-Lite or regular FLASH */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FMLT              (0u != 0u)          /* FLASH-Lite */
+        #define CY_IP_FM                (!CY_IP_FMLT)       /* Regular FLASH */
+    #else
+        #define CY_IP_FMLT              (-1u != 0u)
+        #define CY_IP_FM                (!CY_IP_FMLT)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of interrupt request inputs to CM0 */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_INT_NR            (32u)
+    #else
+        #define CY_IP_INT_NR            (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FLASH_MACROS      (1u)
+    #else
+        #define CY_IP_FLASH_MACROS      (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_BLESS             (0u != 0u)
+    #else
+        #define CY_IP_BLESS             (0u != 0u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Watch Crystal Oscillator (WCO) is present (32kHz) */
+    #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_WCO               (0u != 0u)
+    #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)
+        #define CY_IP_WCO               (0u == 0u)
+    #elif (CY_IP_SRSSV2)
+        #define CY_IP_WCO               (-1u)
+    #else
+        #define CY_IP_WCO               (0u != 0u)
+    #endif  /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* The components version defines. Available started from cy_boot 4.20
+* Use the following construction in order to identify cy_boot version:
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)
+*******************************************************************************/
+#define CY_BOOT_4_20            (420u)
+#define CY_BOOT_VERSION         (CY_BOOT_4_20)
 
 
 /*******************************************************************************
@@ -104,7 +174,7 @@ typedef          float  float32;
 
 #endif  /* (!CY_PSOC3) */
 
-/* Signed or unsigned depending on the compiler selection */
+/* Signed or unsigned depending on compiler selection */
 typedef          char   char8;
 
 
@@ -154,7 +224,7 @@ typedef          char   char8;
 
 #else
 
-    /* Prototype for function to set a 24-bit register. Located at cyutils.c */
+    /* Prototype for function to set 24-bit register. Located at cyutils.c */
     extern void     CySetReg24(uint32 volatile * addr, uint32 value);
 
     #if(CY_PSOC4)
@@ -204,18 +274,39 @@ typedef          char   char8;
     #define XDATA
 
     #if defined(__ARMCC_VERSION)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit"), zero_init))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
+
+        /* Specifies a minimum alignment (in bytes) for variables of the
+        *  specified type.
+        */
         #define CY_ALIGN(align)     __align(align)
+
+
+        /* Attached to an enum, struct, or union type definition, specified that
+        *  the minimum required memory be used to represent the type.
+        */
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           __inline
     #elif defined (__GNUC__)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit")))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
         #define CY_ALIGN(align)     __attribute__ ((aligned(align)))
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           inline
     #elif defined (__ICCARM__)
+
         #define CY_NOINIT           __no_init
         #define CY_NORETURN         __noreturn
+        #define CY_PACKED           __packed
+        #define CY_PACKED_ATTR
+        #define CY_INLINE           inline
     #endif  /* (__ARMCC_VERSION) */
 
 #endif  /* (CY_PSOC3) */
@@ -223,12 +314,12 @@ typedef          char   char8;
 
 #if(CY_PSOC3)
 
-    /* 8051 naturally returns an 8 bit value. */
+    /* 8051 naturally returns 8 bit value. */
     typedef unsigned char cystatus;
 
 #else
 
-    /* ARM naturally returns a 32 bit value. */
+    /* ARM naturally returns 32 bit value. */
     typedef unsigned long cystatus;
 
 #endif  /* (CY_PSOC3) */
@@ -274,7 +365,7 @@ typedef volatile uint32 CYXDATA reg32;
     * KEIL for the 8051 is a big endian compiler This causes problems as the on chip
     * registers are little endian.  Byte swapping for two and four byte registers is
     * implemented in the functions below.  This will require conditional compilation
-    * of function prototypes in code.
+    * of function prototypes in the code.
     *******************************************************************************/
 
     /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
@@ -347,24 +438,24 @@ typedef volatile uint32 CYXDATA reg32;
 *  Data manipulation defines
 *******************************************************************************/
 
-/* Get 8 bits of a 16 bit value. */
+/* Get 8 bits of 16 bit value. */
 #define LO8(x)                  ((uint8) ((x) & 0xFFu))
 #define HI8(x)                  ((uint8) ((uint16)(x) >> 8))
 
-/* Get 16 bits of a 32 bit value. */
+/* Get 16 bits of 32 bit value. */
 #define LO16(x)                 ((uint16) ((x) & 0xFFFFu))
 #define HI16(x)                 ((uint16) ((uint32)(x) >> 16))
 
-/* Swap the byte ordering of a 32 bit value */
+/* Swap the byte ordering of 32 bit value */
 #define CYSWAP_ENDIAN32(x)  \
         ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))
 
-/* Swap the byte ordering of a 16 bit value */
+/* Swap the byte ordering of 16 bit value */
 #define CYSWAP_ENDIAN16(x)      ((uint16)(((x) << 8) | ((x) >> 8)))
 
 
 /*******************************************************************************
-* Defines the standard return values used PSoC content. A function is
+* Defines the standard return values used in PSoC content. A function is
 * not limited to these return values but can use them when returning standard
 * error values. Return values can be overloaded if documented in the function
 * header. On the 8051 a function can use a larger return type but still use the
@@ -413,24 +504,55 @@ typedef volatile uint32 CYXDATA reg32;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+#define CY_UDB_V0           (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#define CY_UDB_V1           (!CY_UDB_V0)
+#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#else
+    #define CY_PSOC4D   (0u != 0u)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#endif  /* CYDEV_CHIP_MEMBER_4D */
+#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#ifdef CYDEV_CHIP_MEMBER_5B
+    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#else
+    #define CY_PSOC5LP  (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_5B */
+
+#if (!CY_PSOC4)
+
+    /* Device is PSoC 3 and the revision is ES2 or earlier */
+    #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
 
-/* Device is PSoC 3 and the revision is ES2 or earlier */
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
+    /* Device is PSoC 3 and the revision is ES3 or later */
+    #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
 
-/* Device is PSoC 3 and the revision is ES3 or later */
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
+    /* Device is PSoC 5 and the revision is ES1 or earlier */
+    #define CY_PSOC5_ES1 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES1 or earlier */
-#define CY_PSOC5_ES1 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
+    /* Device is PSoC 5 and the revision is ES2 or later */
+    #define CY_PSOC5_ES2 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES2 or later */
-#define CY_PSOC5_ES2 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
+#endif  /* (!CY_PSOC4) */
 
 #endif  /* CY_BOOT_CYTYPES_H */
 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c
index 0a112316..4d2b71a4 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * FILENAME: cyutils.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   CyUtils provides function to handle 24-bit value writes.
+*   CyUtils provides a function to handle 24-bit value writes.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,11 +21,11 @@
     ****************************************************************************
     *
     * Summary:
-    *  Writes the 24-bit value to the specified register.
+    *  Writes a 24-bit value to the specified register.
     *
     * Parameters:
-    *  addr : adress where data must be written
-    *  value: data that must be written
+    *  addr : the address where data must be written.
+    *  value: the data that must be written.
     *
     * Return:
     *  None
@@ -56,7 +56,7 @@
         *  Reads the 24-bit value from the specified register.
         *
         * Parameters:
-        *  addr : adress where data must be read
+        *  addr : the address where data must be read.
         *
         * Return:
         *  None
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h
old mode 100755
new mode 100644
index 0027c911..1fefe633
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
  * File Name: project.h
- * PSoC Creator 3.0 Component Pack 7
+ * PSoC Creator  3.1
  *
  *  Description:
  *  This file is automatically generated by PSoC Creator and should not 
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch
index 0dd5ad1b..1e6615b0 100755
Binary files a/software/SCSI2SD/v3/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cycdx b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cycdx
index 8f6ac4e9..d92aa5be 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cycdx
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cycdx
@@ -4,17 +4,33 @@
   <block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
-    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
@@ -47,7 +63,7 @@
     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
-      <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />
+      <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
     </register>
     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cydwr b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cydwr
index f8532ed5..ef8691d3 100755
Binary files a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cydwr and b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cydwr differ
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit
index 744fc438..953ab81d 100644
Binary files a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj
index 2fdfa0d3..574dac60 100755
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj
@@ -908,14 +908,14 @@
 <GlobalPages />
 <GlobalTools name="Code Generation">
 <GlobalPages>
+<name_val_pair name="General@Application Type" v="Bootloader" />
+<name_val_pair name="General@Custom Code Gen Options" v="" />
+<name_val_pair name="General@Skip Code Generation" v="False" />
+<name_val_pair name="General@Custom Synthesis Options" v="" />
+<name_val_pair name="General@Quiet Output" v="True" />
 <name_val_pair name="General@Synthesis Goal" v="Speed" />
 <name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />
-<name_val_pair name="General@Quiet Output" v="True" />
-<name_val_pair name="General@Custom Synthesis Options" v="" />
-<name_val_pair name="General@Skip Code Generation" v="False" />
-<name_val_pair name="General@Custom Code Gen Options" v="" />
 <name_val_pair name="General@Virtual Node Substitution" v="3" />
-<name_val_pair name="General@Application Type" v="Bootloader" />
 <name_val_pair name="General@Custom Fitter Options" v="" />
 </GlobalPages>
 </GlobalTools>
@@ -926,9 +926,9 @@
 </GlobalTools>
 <GlobalTools name="Customizer">
 <GlobalPages>
-<name_val_pair name="General@Customizer Build Mode" v="Release" />
-<name_val_pair name="General@Command Line Options" v="" />
 <name_val_pair name="General@Assembly References" v="" />
+<name_val_pair name="General@Command Line Options" v="" />
+<name_val_pair name="General@Customizer Build Mode" v="Release" />
 </GlobalPages>
 </GlobalTools>
 </name>
@@ -936,133 +936,323 @@
 <platform>
 <name v="c9323d49-d323-40b8-9b59-cc008d68a989">
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Preprocessor Definitions" v="DEBUG" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Struct Return Method" v="System Default" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Verbose Asm" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Warning Level" v="High" />
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>
 </platform>
 </platforms>
@@ -1071,18 +1261,9 @@
 <component_generation v="PSoC Creator  3.0" />
 <last_selected_tab v="Cypress" />
 <component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1)" />
-<WriteAppVersionLastSavedWith v="3.0.0.1539" />
-<WriteAppMarketingVersionLastSavedWith v=" 3.0 Component Pack 7" />
-<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" />
-<custom_data>
-<CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">
-<CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2">
-<userData />
-</CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997>
-<properties />
-</CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111>
-</custom_data>
-</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
+<WriteAppVersionLastSavedWith v="3.1.0.1570" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
 </CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
 <top_block v="TopDesign" />
 <selected_device v="CY8C5267AXI-LP051" />
@@ -1093,8 +1274,8 @@
 <CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
 <ignored_deps />
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
-<boot_component v="cy_boot_v4_0" />
+<boot_component v="cy_boot_v4_20" />
 <BootloaderTag hexFile="" elfFile="" />
-<current_generation v="0" />
+<current_generation v="1" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
 </CyXmlSerializer>
\ No newline at end of file
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
index 2a57dc00..688eb60e 100755
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
@@ -7,12 +7,12 @@
 <userData>
 <dataGuid v="47ec7058-2f43-4a2f-ae73-172624e235df">
 <CyGuid_47ec7058-2f43-4a2f-ae73-172624e235df type_name="CyDesigner.Common.ProjMgmt.Model.CyConfDepList" version="1">
-<boot_component v="cy_boot_v4_0" />
+<boot_component v="cy_boot_v4_20" />
 <name v="cmpl_deps">
 <CyGuid_f44455c5-3770-4452-b988-0a7a7ff46256 type_name="CyDesigner.Common.ProjMgmt.Model.CyConfigDependencies" version="1">
 <dependency_info name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3" xml_contents_version="2">
 <CyGuid_1173175f-1b9b-4ad4-a065-754a48a27021 type_name="CyDesigner.Common.Base.CyFileDeps" version="1">
-<file name=".\CortexM3\ARM_GCC_473\Release\main.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\main.o">
 <dep name=".\Generated_Source\PSoC5\BL.h" />
 <dep name=".\Generated_Source\PSoC5\BL_PVT.h" />
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
@@ -82,7 +82,7 @@
 <file name=".\Generated_Source\PSoC5\cytypes.h" />
 <file name=".\Generated_Source\PSoC5\project.h" />
 <file name=".\main.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\BL.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\BL.o">
 <dep name=".\Generated_Source\PSoC5\BL.h" />
 <dep name=".\Generated_Source\PSoC5\BL_PVT.h" />
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
@@ -119,7 +119,7 @@
 <dep name=".\Generated_Source\PSoC5\BL.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\BL.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\Cm3Start.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\Cm3Start.o">
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
@@ -133,7 +133,7 @@
 <dep name=".\Generated_Source\PSoC5\Cm3Start.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\Cm3Start.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\CyDmac.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\CyDmac.o">
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
@@ -146,7 +146,7 @@
 <dep name=".\Generated_Source\PSoC5\CyDmac.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\CyDmac.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\CyFlash.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\CyFlash.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -158,7 +158,7 @@
 <dep name=".\Generated_Source\PSoC5\CyFlash.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\CyFlash.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\CyLib.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\CyLib.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -170,7 +170,7 @@
 <dep name=".\Generated_Source\PSoC5\CyLib.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\CyLib.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\CySpc.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\CySpc.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -182,7 +182,7 @@
 <dep name=".\Generated_Source\PSoC5\CySpc.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\CySpc.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\SD_PULLUP.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\SD_PULLUP.o">
 <dep name=".\Generated_Source\PSoC5\SD_PULLUP.h" />
 <dep name=".\Generated_Source\PSoC5\SD_PULLUP_aliases.h" />
 <dep name=".\Generated_Source\PSoC5\cydevice.h" />
@@ -193,7 +193,7 @@
 <dep name=".\Generated_Source\PSoC5\SD_PULLUP.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\SD_PULLUP.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS.o">
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
@@ -209,7 +209,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_Dm.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_Dm.o">
 <dep name=".\Generated_Source\PSoC5\USBFS_Dm.h" />
 <dep name=".\Generated_Source\PSoC5\USBFS_Dm_aliases.h" />
 <dep name=".\Generated_Source\PSoC5\cydevice.h" />
@@ -220,7 +220,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_Dm.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_Dm.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_Dp.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_Dp.o">
 <dep name=".\Generated_Source\PSoC5\USBFS_Dp.h" />
 <dep name=".\Generated_Source\PSoC5\USBFS_Dp_aliases.h" />
 <dep name=".\Generated_Source\PSoC5\cydevice.h" />
@@ -231,7 +231,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_Dp.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_Dp.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_audio.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_audio.o">
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
@@ -248,7 +248,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_audio.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_audio.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_boot.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_boot.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -261,7 +261,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_boot.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_boot.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_cdc.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_cdc.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -276,7 +276,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_cdc.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_cdc.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_cls.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_cls.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -290,7 +290,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_cls.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_cls.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_descr.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_descr.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -304,7 +304,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_descr.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_descr.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_drv.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_drv.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -318,7 +318,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_drv.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_drv.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_episr.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_episr.o">
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
@@ -334,7 +334,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_episr.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_episr.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_hid.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_hid.o">
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
 <dep name=".\Generated_Source\PSoC5\CySpc.h" />
@@ -349,7 +349,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_hid.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_hid.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_midi.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_midi.o">
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
 <dep name=".\Generated_Source\PSoC5\CyFlash.h" />
 <dep name=".\Generated_Source\PSoC5\CyLib.h" />
@@ -365,7 +365,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_midi.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_midi.c" />
-<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_pm.o">
+<file name=".\CortexM3\ARM_GCC_484\Release\USBFS_pm.o">
 <dep name=".\Generated_Source\PSoC5\BL.h" />
 <dep name=".\Generated_Source\PSoC5\BL_PVT.h" />
 <dep name=".\Generated_Source\PSoC5\CyDmac.h" />
@@ -402,7 +402,7 @@
 <dep name=".\Generated_Source\PSoC5\USBFS_pm.c" />
 </file>
 <file name=".\Generated_Source\PSoC5\USBFS_pm.c" />
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@@ -419,7 +419,7 @@
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@@ -433,7 +433,7 @@
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@@ -445,7 +445,7 @@
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@@ -458,7 +458,7 @@
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@@ -466,7 +466,7 @@
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@@ -474,7 +474,7 @@
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@@ -484,6 +484,414 @@
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+<dep name=".\Generated_Source\PSoC5\USBFS_Dp_aliases.h" />
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+<dep name=".\Generated_Source\PSoC5\USBFS_midi.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_pvt.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_midi.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_pm.o">
+<dep name=".\Generated_Source\PSoC5\BL.h" />
+<dep name=".\Generated_Source\PSoC5\BL_PVT.h" />
+<dep name=".\Generated_Source\PSoC5\CyDmac.h" />
+<dep name=".\Generated_Source\PSoC5\CyFlash.h" />
+<dep name=".\Generated_Source\PSoC5\CyLib.h" />
+<dep name=".\Generated_Source\PSoC5\CySpc.h" />
+<dep name=".\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h" />
+<dep name=".\Generated_Source\PSoC5\SCSI_Out_aliases.h" />
+<dep name=".\Generated_Source\PSoC5\SD_PULLUP.h" />
+<dep name=".\Generated_Source\PSoC5\SD_PULLUP_aliases.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_Dm.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_Dm_aliases.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_Dp.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_Dp_aliases.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_audio.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_cdc.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_hid.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_midi.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_pvt.h" />
+<dep name=".\Generated_Source\PSoC5\core_cm3.h" />
+<dep name=".\Generated_Source\PSoC5\core_cm3_psoc5.h" />
+<dep name=".\Generated_Source\PSoC5\core_cmFunc.h" />
+<dep name=".\Generated_Source\PSoC5\core_cmInstr.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cydisabledsheets.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter_cfg.h" />
+<dep name=".\Generated_Source\PSoC5\cypins.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\project.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_pm.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_std.o">
+<dep name=".\Generated_Source\PSoC5\CyDmac.h" />
+<dep name=".\Generated_Source\PSoC5\CyFlash.h" />
+<dep name=".\Generated_Source\PSoC5\CyLib.h" />
+<dep name=".\Generated_Source\PSoC5\CySpc.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_cdc.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_midi.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_pvt.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_std.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\USBFS_vnd.o">
+<dep name=".\Generated_Source\PSoC5\CyFlash.h" />
+<dep name=".\Generated_Source\PSoC5\CyLib.h" />
+<dep name=".\Generated_Source\PSoC5\CySpc.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_pvt.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\USBFS_vnd.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\cyPm.o">
+<dep name=".\Generated_Source\PSoC5\CyFlash.h" />
+<dep name=".\Generated_Source\PSoC5\CyLib.h" />
+<dep name=".\Generated_Source\PSoC5\CySpc.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\cyfitter_cfg.o">
+<dep name=".\Generated_Source\PSoC5\CyFlash.h" />
+<dep name=".\Generated_Source\PSoC5\CyLib.h" />
+<dep name=".\Generated_Source\PSoC5\CySpc.h" />
+<dep name=".\Generated_Source\PSoC5\cyPm.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter_cfg.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter_cfg.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\cymetadata.o">
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\cymetadata.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\cyutils.o">
+<dep name=".\Generated_Source\PSoC5\cydevice.h" />
+<dep name=".\Generated_Source\PSoC5\cydevice_trm.h" />
+<dep name=".\Generated_Source\PSoC5\cyfitter.h" />
+<dep name=".\Generated_Source\PSoC5\cytypes.h" />
+<dep name=".\Generated_Source\PSoC5\cyutils.c" />
+</file>
+<file name=".\CortexM3\ARM_GCC_473\Release\CyBootAsmGnu.o">
+<dep name=".\Generated_Source\PSoC5\cydevicegnu.inc" />
+<dep name=".\Generated_Source\PSoC5\cydevicegnu_trm.inc" />
+<dep name=".\Generated_Source\PSoC5\cyfittergnu.inc" />
+<dep name=".\Generated_Source\PSoC5\CyBootAsmGnu.s" />
+</file>
 </CyGuid_1173175f-1b9b-4ad4-a065-754a48a27021>
 </dependency_info>
 <dependency_info name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3" xml_contents_version="2">
@@ -968,37 +1376,37 @@
 <CyGuid_f44455c5-3770-4452-b988-0a7a7ff46256 type_name="CyDesigner.Common.ProjMgmt.Model.CyConfigDependencies" version="1">
 <dependency_info name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3" xml_contents_version="2">
 <CyGuid_1173175f-1b9b-4ad4-a065-754a48a27021 type_name="CyDesigner.Common.Base.CyFileDeps" version="1">
-<file name=".\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex">
-<dep name=".\CortexM3\ARM_GCC_473\Release\main.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\cyfitter_cfg.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\cymetadata.o" />
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-<dep name=".\CortexM3\ARM_GCC_473\Release\USBFS_descr.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\USBFS_drv.o" />
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-<dep name=".\CortexM3\ARM_GCC_473\Release\USBFS_pm.o" />
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-<dep name=".\CortexM3\ARM_GCC_473\Release\USBFS_midi.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\BL.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\USBFS_Dm.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\USBFS_Dp.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\Cm3Start.o" />
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-<dep name=".\CortexM3\ARM_GCC_473\Release\CyFlash.o" />
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-<dep name=".\CortexM3\ARM_GCC_473\Release\CySpc.o" />
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-<dep name=".\CortexM3\ARM_GCC_473\Release\SD_PULLUP.o" />
-<dep name=".\CortexM3\ARM_GCC_473\Release\USB_Bootloader.a" />
-<dep name="${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\CortexM3\ARM_GCC_473\Release\CyComponentLibrary.a" />
+<file name=".\CortexM3\ARM_GCC_484\Release\USB_Bootloader.hex">
+<dep name=".\CortexM3\ARM_GCC_484\Release\main.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\cyfitter_cfg.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\cymetadata.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_audio.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_boot.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_cdc.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_cls.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_descr.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_drv.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_episr.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_hid.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_pm.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_std.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_vnd.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_midi.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\BL.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_Dm.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USBFS_Dp.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\Cm3Start.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\CyBootAsmGnu.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\CyDmac.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\CyFlash.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\CyLib.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\cyPm.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\CySpc.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\cyutils.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\SD_PULLUP.o" />
+<dep name=".\CortexM3\ARM_GCC_484\Release\USB_Bootloader.a" />
+<dep name="${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\CortexM3\ARM_GCC_484\Release\CyComponentLibrary.a" />
 </file>
 </CyGuid_1173175f-1b9b-4ad4-a065-754a48a27021>
 </dependency_info>
@@ -1046,36 +1454,36 @@
 <CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68 type_name="CyDesigner.Common.ProjMgmt.Common.CyCmdLineData" version="2">
 <genericCmdLineData>
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-<name_val_pair name=".\Generated_Source\PSoC5\USBFS_pm.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\USBFS_std.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
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-<name_val_pair name=".\Generated_Source\PSoC5\Cm3Start.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\CyBootAsmGnu.s" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-g &quot;&quot;-alh=${OutputDir}/${CompileFile}.lst &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\CyDmac.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\CyFlash.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\CyLib.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\cyPm.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\CySpc.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\cyutils.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
+<name_val_pair name=".\main.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\cyfitter_cfg.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\cymetadata.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_audio.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_boot.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_cdc.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_cls.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_descr.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_drv.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_episr.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_hid.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_pm.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_std.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_vnd.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_midi.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\BL.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_Dm.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\USBFS_Dp.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\Cm3Start.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\CyBootAsmGnu.s" v="-mcpu=cortex-m3 -mthumb -I. -I.\Generated_Source\PSoC5 -alh=${OutputDir}/${CompileFile}.lst -g" />
+<name_val_pair name=".\Generated_Source\PSoC5\CyDmac.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\CyFlash.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\CyLib.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\cyPm.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\CySpc.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
+<name_val_pair name=".\Generated_Source\PSoC5\cyutils.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
 <name_val_pair name="Z:\projects\SCSI2SD\git\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
 <name_val_pair name="W:\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
-<name_val_pair name=".\Generated_Source\PSoC5\SD_PULLUP.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;NDEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-Os &quot;&quot;-ffunction-sections &quot;" />
+<name_val_pair name=".\Generated_Source\PSoC5\SD_PULLUP.c" v="-mcpu=cortex-m3 -mthumb -Wno-main -I. -I.\Generated_Source\PSoC5 -Wa,-alh=${OutputDir}/${CompileFile}.lst -g -D NDEBUG -Wall -ffunction-sections -Os" />
 <name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
 <name_val_pair name="Z:\projects\SCSI2SD\git-3.4_debug\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
 <name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
@@ -1083,6 +1491,7 @@
 <name_val_pair name="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
 <name_val_pair name="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
 <name_val_pair name="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
+<name_val_pair name="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_484\Release\USB_Bootloader.hex" v="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -Wl,-Map,${OutputDir}/${ProjectShortName}.map -T .\Generated_Source\PSoC5\cm3gcc.ld -g -specs=nano.specs &quot;-u _printf_float&quot; &quot;&quot; -Wl,--gc-sections" />
 </name>
 <name v="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3">
 <name_val_pair name=".\main.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;DEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-ffunction-sections &quot;" />
@@ -1116,7 +1525,7 @@
 <name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Debug\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />
 </name>
 </genericCmdLineData>
-<codeGenCmdLineTag v="&quot;-.appdatapath&quot; &quot;C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0&quot; &quot;-.fdsnotice&quot; &quot;-.fdswarpdepfile=warp_dependencies.txt&quot; &quot;-.fdselabdepfile=elab_dependencies.txt&quot; &quot;-.fdsbldfile=generated_files.txt&quot; &quot;-p&quot; &quot;Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj&quot; &quot;-d&quot; &quot;CY8C5267AXI-LP051&quot; &quot;-s&quot; &quot;Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5&quot; &quot;--&quot; &quot;-yv2&quot; &quot;-v3&quot; &quot;-ygs&quot; &quot;-q10&quot; &quot;-o2&quot; &quot;-.fftcfgtype=LE&quot; " />
+<codeGenCmdLineTag v="-.appdatapath &quot;C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.1&quot; -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE" />
 </CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68>
 </dataGuid>
 <dataGuid v="597c5b74-0c46-4204-8b7f-96f3570671dc">
@@ -1147,20 +1556,20 @@
 <v>Cypress Component Catalog\Digital\Functions\CRC [v2.40]</v>
 <v>Cypress Component Catalog\Digital\Functions\PrISM [v2.20]</v>
 <v>Cypress Component Catalog\Digital\Functions\PRS [v2.40]</v>
-<v>Cypress Component Catalog\Digital\Functions\PWM [v3.0]</v>
-<v>Cypress Component Catalog\Digital\Functions\Quadrature Decoder [v2.30]</v>
+<v>Cypress Component Catalog\Digital\Functions\PWM [v3.10]</v>
+<v>Cypress Component Catalog\Digital\Functions\Quadrature Decoder [v2.40]</v>
 <v>Cypress Component Catalog\Digital\Functions\Shift Register [v2.30]</v>
-<v>Cypress Component Catalog\Digital\Functions\Timer [v2.50]</v>
+<v>Cypress Component Catalog\Digital\Functions\Timer [v2.70]</v>
 <v>Cypress Component Catalog\Digital\Logic</v>
 <v>Cypress Component Catalog\Digital\Registers</v>
 <v>Cypress Component Catalog\Digital\Utility</v>
 <v>Cypress Component Catalog\Display</v>
 <v>Cypress Component Catalog\Filters</v>
 <v>Cypress Component Catalog\Ports and Pins</v>
-<v>Cypress Component Catalog\Ports and Pins\Analog Pin [v1.90]</v>
-<v>Cypress Component Catalog\Ports and Pins\Digital Bidirectional Pin [v1.90]</v>
-<v>Cypress Component Catalog\Ports and Pins\Digital Input Pin [v1.90]</v>
-<v>Cypress Component Catalog\Ports and Pins\Digital Output Pin [v1.90]</v>
+<v>Cypress Component Catalog\Ports and Pins\Analog Pin [v2.10]</v>
+<v>Cypress Component Catalog\Ports and Pins\Digital Bidirectional Pin [v2.10]</v>
+<v>Cypress Component Catalog\Ports and Pins\Digital Input Pin [v2.10]</v>
+<v>Cypress Component Catalog\Ports and Pins\Digital Output Pin [v2.10]</v>
 <v>Cypress Component Catalog\Power Supervision</v>
 <v>Cypress Component Catalog\System</v>
 <v>Cypress Component Catalog\System\Boost Converter [v5.0]</v>
@@ -1188,117 +1597,119 @@
 <CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectPSoCExe+CyCodeGenDepUserInfo" version="1">
 <deps_list>
 <v>.\TopDesign\TopDesign.cysch</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cysym</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.pdf</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cycdx</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\USBFS_v2_60.cystate</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_audio.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_audio.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_boot.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cdc.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cdc.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_cls.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_descr.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_drv.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_episr.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_hid.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\USBFS_v2_60\API\USBFS_hid.h</v>
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+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cygeneralcontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cyinputcontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cymappingcontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cyoutputcontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cypinaliasdialog.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cypinscontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cyporcontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\Resource1.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\Custom\cyclockingcontrol.resx</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\PSoC5\API\aliases.h</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\PSoC5\API\pins.c</v>
+<v>${CyRoot}\psoc\content\cyprimitives\CyPrimitives.cylib\cy_pins_v2_10\PSoC5\API\pins.h</v>
 <v>.\USB_Bootloader.cydwr</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cm3gcc.ld</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\Cm3RealView.scat</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\Cm3Start.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\core_cm3.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\core_cm3_psoc5.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyBootAsmGnu.s</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyBootAsmRv.s</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyDmac.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyDmac.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyFlash.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyFlash.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyLib.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyLib.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cypins.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cyPm.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cyPm.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CySpc.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CySpc.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cytypes.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\cyutils.c</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\core_cmFunc.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\core_cmInstr.h</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\Cm3Iar.icf</v>
-<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC5\API\CyBootAsmIar.s</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\cm3gcc.ld</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\Cm3RealView.scat</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\Cm3Start.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\core_cm3.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\core_cm3_psoc5.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyBootAsmGnu.s</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyBootAsmRv.s</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyDmac.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyDmac.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyFlash.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyFlash.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyLib.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyLib.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\cypins.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\cyPm.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\cyPm.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CySpc.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CySpc.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\cytypes.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\cyutils.c</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\core_cmFunc.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\core_cmInstr.h</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\Cm3Iar.icf</v>
+<v>${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\cy_boot_v4_20\PSoC5\API\CyBootAsmIar.s</v>
 </deps_list>
 <gen_list>
 <v>.\Generated_Source\PSoC5\cyfitter_cfg.h</v>
@@ -1665,18 +2135,20 @@
 <v>.\Generated_Source\PSoC5\SD_PULLUP.h</v>
 </gen_list>
 <warp_dep>
-<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif</v>
-<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>
-<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>
+<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\warp\lib\ieee\work\stdlogic.vif</v>
+<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>
+<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v</v>
+<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v</v>
+<v>C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>
 </warp_dep>
-<deps_time v="130621702845187692" />
+<deps_time v="130664015022693971" />
 <top_block v="TopDesign" />
-<last_generation v="0" />
+<last_generation v="1" />
 </CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>
 </dataGuid>
 <dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">
 <CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">
-<deps_time v="130621704041554601" />
+<deps_time v="130664016042069689" />
 </CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>
 </dataGuid>
 <dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">
diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.svd b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.svd
index 2171fc78..9e5792a5 100644
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.svd
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.svd
@@ -9,17 +9,17 @@
     <peripheral>
       <name>USBFS</name>
       <description>USBFS</description>
-      <baseAddress>0x40004394</baseAddress>
+      <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1D0A</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
         <register>
           <name>USBFS_PM_USB_CR0</name>
           <description>USB Power Mode Control Register 0</description>
-          <addressOffset>0x0</addressOffset>
+          <addressOffset>0x40004394</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -51,7 +51,7 @@
         <register>
           <name>USBFS_PM_ACT_CFG</name>
           <description>Active Power Mode Configuration Register</description>
-          <addressOffset>0x11</addressOffset>
+          <addressOffset>0x400043A5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -60,7 +60,7 @@
         <register>
           <name>USBFS_PM_STBY_CFG</name>
           <description>Standby Power Mode Configuration Register</description>
-          <addressOffset>0x21</addressOffset>
+          <addressOffset>0x400043B5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -69,7 +69,7 @@
         <register>
           <name>USBFS_PRT_PS</name>
           <description>Port Pin State Register</description>
-          <addressOffset>0xE5D</addressOffset>
+          <addressOffset>0x400051F1</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -94,7 +94,7 @@
         <register>
           <name>USBFS_PRT_DM0</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5E</addressOffset>
+          <addressOffset>0x400051F2</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -119,7 +119,7 @@
         <register>
           <name>USBFS_PRT_DM1</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5F</addressOffset>
+          <addressOffset>0x400051F3</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -144,7 +144,7 @@
         <register>
           <name>USBFS_PRT_INP_DIS</name>
           <description>Input buffer disable override</description>
-          <addressOffset>0xE64</addressOffset>
+          <addressOffset>0x400051F8</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -169,7 +169,7 @@
         <register>
           <name>USBFS_EP0_DR0</name>
           <description>bmRequestType</description>
-          <addressOffset>0x1C6C</addressOffset>
+          <addressOffset>0x40006000</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -178,7 +178,7 @@
         <register>
           <name>USBFS_EP0_DR1</name>
           <description>bRequest</description>
-          <addressOffset>0x1C6D</addressOffset>
+          <addressOffset>0x40006001</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -187,7 +187,7 @@
         <register>
           <name>USBFS_EP0_DR2</name>
           <description>wValueLo</description>
-          <addressOffset>0x1C6E</addressOffset>
+          <addressOffset>0x40006002</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -196,7 +196,7 @@
         <register>
           <name>USBFS_EP0_DR3</name>
           <description>wValueHi</description>
-          <addressOffset>0x1C6F</addressOffset>
+          <addressOffset>0x40006003</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -205,7 +205,7 @@
         <register>
           <name>USBFS_EP0_DR4</name>
           <description>wIndexLo</description>
-          <addressOffset>0x1C70</addressOffset>
+          <addressOffset>0x40006004</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -214,7 +214,7 @@
         <register>
           <name>USBFS_EP0_DR5</name>
           <description>wIndexHi</description>
-          <addressOffset>0x1C71</addressOffset>
+          <addressOffset>0x40006005</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -223,7 +223,7 @@
         <register>
           <name>USBFS_EP0_DR6</name>
           <description>lengthLo</description>
-          <addressOffset>0x1C72</addressOffset>
+          <addressOffset>0x40006006</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -232,7 +232,7 @@
         <register>
           <name>USBFS_EP0_DR7</name>
           <description>lengthHi</description>
-          <addressOffset>0x1C73</addressOffset>
+          <addressOffset>0x40006007</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -241,7 +241,7 @@
         <register>
           <name>USBFS_CR0</name>
           <description>USB Control Register 0</description>
-          <addressOffset>0x1C74</addressOffset>
+          <addressOffset>0x40006008</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -250,8 +250,8 @@
             <field>
               <name>device_address</name>
               <description>No description available</description>
-              <lsb>6</lsb>
-              <msb>0</msb>
+              <lsb>0</lsb>
+              <msb>6</msb>
               <access>read-only</access>
             </field>
             <field>
@@ -266,7 +266,7 @@
         <register>
           <name>USBFS_CR1</name>
           <description>USB Control Register 1</description>
-          <addressOffset>0x1C75</addressOffset>
+          <addressOffset>0x40006009</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -305,7 +305,7 @@
         <register>
           <name>USBFS_SIE_EP1_CR0</name>
           <description>The Endpoint1 Control Register</description>
-          <addressOffset>0x1C7A</addressOffset>
+          <addressOffset>0x4000600E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -314,7 +314,7 @@
         <register>
           <name>USBFS_USBIO_CR0</name>
           <description>USBIO Control Register 0</description>
-          <addressOffset>0x1C7C</addressOffset>
+          <addressOffset>0x40006010</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -353,7 +353,7 @@
         <register>
           <name>USBFS_USBIO_CR1</name>
           <description>USBIO Control Register 1</description>
-          <addressOffset>0x1C7E</addressOffset>
+          <addressOffset>0x40006012</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -392,7 +392,7 @@
         <register>
           <name>USBFS_SIE_EP2_CR0</name>
           <description>The Endpoint2 Control Register</description>
-          <addressOffset>0x1C8A</addressOffset>
+          <addressOffset>0x4000601E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -401,7 +401,7 @@
         <register>
           <name>USBFS_SIE_EP3_CR0</name>
           <description>The Endpoint3 Control Register</description>
-          <addressOffset>0x1C9A</addressOffset>
+          <addressOffset>0x4000602E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -410,7 +410,7 @@
         <register>
           <name>USBFS_SIE_EP4_CR0</name>
           <description>The Endpoint4 Control Register</description>
-          <addressOffset>0x1CAA</addressOffset>
+          <addressOffset>0x4000603E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -419,7 +419,7 @@
         <register>
           <name>USBFS_SIE_EP5_CR0</name>
           <description>The Endpoint5 Control Register</description>
-          <addressOffset>0x1CBA</addressOffset>
+          <addressOffset>0x4000604E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -428,7 +428,7 @@
         <register>
           <name>USBFS_SIE_EP6_CR0</name>
           <description>The Endpoint6 Control Register</description>
-          <addressOffset>0x1CCA</addressOffset>
+          <addressOffset>0x4000605E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -437,7 +437,7 @@
         <register>
           <name>USBFS_SIE_EP7_CR0</name>
           <description>The Endpoint7 Control Register</description>
-          <addressOffset>0x1CDA</addressOffset>
+          <addressOffset>0x4000606E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -446,7 +446,7 @@
         <register>
           <name>USBFS_SIE_EP8_CR0</name>
           <description>The Endpoint8 Control Register</description>
-          <addressOffset>0x1CEA</addressOffset>
+          <addressOffset>0x4000607E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -455,7 +455,7 @@
         <register>
           <name>USBFS_BUF_SIZE</name>
           <description>Dedicated Endpoint Buffer Size Register</description>
-          <addressOffset>0x1CF8</addressOffset>
+          <addressOffset>0x4000608C</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -464,7 +464,7 @@
         <register>
           <name>USBFS_EP_ACTIVE</name>
           <description>Endpoint Active Indication Register</description>
-          <addressOffset>0x1CFA</addressOffset>
+          <addressOffset>0x4000608E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -473,7 +473,7 @@
         <register>
           <name>USBFS_EP_TYPE</name>
           <description>Endpoint Type (IN/OUT) Indication</description>
-          <addressOffset>0x1CFB</addressOffset>
+          <addressOffset>0x4000608F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -482,7 +482,7 @@
         <register>
           <name>USBFS_USB_CLK_EN</name>
           <description>USB Block Clock Enable Register</description>
-          <addressOffset>0x1D09</addressOffset>
+          <addressOffset>0x4000609D</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
index c5058bc0..91e52258 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c
@@ -1,13 +1,13 @@
 /*******************************************************************************
 * File Name: Bootloadable_1.c
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloadable application. The API includes a
-*   single function for starting bootloader.
+*   single function for starting the bootloader.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,7 +20,7 @@
 * Function Name: Bootloadable_1_Load
 ********************************************************************************
 * Summary:
-*  Begins the bootloading algorithm, downloading a new ACD image from the host.
+*  Begins the bootloading algorithm downloading a new ACD image from the host.
 *
 * Parameters:
 *  None
@@ -40,28 +40,23 @@ void Bootloadable_1_Load(void)
 
 
 /*******************************************************************************
-* Function Name: Bootloadable_1_SetFlashByte
-********************************************************************************
-* Summary:
-*  Sets byte at specified address in Flash.
-*
-* Parameters:
-*  None
-*
-* Returns:
-*  None
-*
+* The following code is OBSOLETE and must not be used.
 *******************************************************************************/
 void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) 
 {
     uint32 flsAddr = address - CYDEV_FLASH_BASE;
-    uint8 rowData[CYDEV_FLS_ROW_SIZE];
+    uint8  rowData[CYDEV_FLS_ROW_SIZE];
 
     #if !(CY_PSOC4)
-        uint8 arrayId = (uint8)(flsAddr / CYDEV_FLS_SECTOR_SIZE);
+        uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
     #endif  /* !(CY_PSOC4) */
 
-    uint16 rowNum = (uint16)((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
     uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
     uint16 idx;
 
@@ -72,12 +67,21 @@ void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType)
     }
     rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
 
-
     #if(CY_PSOC4)
-        (void) CySysFlashWriteRow((uint32)rowNum, rowData);
+        (void) CySysFlashWriteRow((uint32) rowNum, rowData);
     #else
         (void) CyWriteRowData(arrayId, rowNum, rowData);
     #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing Flash, data in the instruction cache can become stale.
+        * Therefore, the cache data does not correlate to the data just written to
+        * Flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from Flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
 }
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
index 437dec25..8d4bedc2 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h
@@ -1,13 +1,13 @@
 /*******************************************************************************
 * File Name: Bootloadable_1.h
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloadable application. The API includes a
 *   single function for starting bootloader.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -24,7 +24,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component Bootloadable_v1_20 requires cy_boot v3.0 or later
+    #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later
 #endif /* !defined (CY_PSOC5LP) */
 
 
@@ -89,13 +89,13 @@ extern void Bootloadable_1_Load(void) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.10
+* The following code is OBSOLETE and must not be used starting from version 1.10
 *******************************************************************************/
 #define CYBTDLR_SET_RUN_TYPE(x)     Bootloadable_1_SET_RUN_TYPE(x)
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.20
+* The following code is OBSOLETE and must not be used starting from version 1.20
 *******************************************************************************/
 #define Bootloadable_1_START_APP                      (0x80u)
 #define Bootloadable_1_START_BTLDR                    (0x40u)
@@ -136,12 +136,26 @@ extern void Bootloadable_1_Load(void) ;
 #define Bootloadable_1_SetFlashRunType(runType)           \
                         Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
 
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
 
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
 #if(CY_PSOC4)
-    #define Bootloadable_1_SOFTWARE_RESET         CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u)
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
 #else
-    #define Bootloadable_1_SOFTWARE_RESET         CY_SET_REG8(CYREG_RESET_CR2, 0x01u)
+    #define Bootloadable_1_SOFTWARE_RESET         CySoftwareReset()
 #endif  /* (CY_PSOC4) */
 
 #if(CY_PSOC4)
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
index 061f4f45..9cb1d7dd 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
@@ -9,8 +9,8 @@ define symbol __ICFEDIT_region_ROM_end__   = 131072 - 1;
 define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
 define symbol __ICFEDIT_region_RAM_end__   = 0x20000000 + (32768 / 2) - 1;
 /*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x4000;
-define symbol __ICFEDIT_size_heap__   = 0x1000;
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__   = 0x0400;
 /**** End of ICF editor section. ###ICF###*/
 
 
@@ -40,7 +40,10 @@ define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   {
 define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
 define block HSTACK      {block HEAP, last block CSTACK};
 
+if (CY_APPL_LOADABLE)
+{
 define block LOADER     { readonly section .cybootloader };
+}
 define block APPL       with fixed order {readonly section .romvectors, readonly};
 
 /* The address of Flash row next after Bootloader image */
@@ -83,7 +86,11 @@ do not initialize  { section .noinit };
 do not initialize  { readwrite section .ramvectors };
 
 /******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
 ".cybootloader"    : place at start of ROM_region {block LOADER};
+}
+
 "APPL"             : place at start of APPL_region {block APPL};
 
 "RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
@@ -101,7 +108,10 @@ keep {  section .cybootloader,
         section .cymeta };
 
 ".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
 ".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
 ".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
 ".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
 ".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
index 65833c8b..4dc965b2 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
@@ -4,7 +4,7 @@
 
 ;********************************************************************************
 ;* File Name: Cm3RealView.scat
-;* Version 4.0
+;* Version 4.20
 ;*
 ;*  Description:
 ;*  This Linker Descriptor file describes the memory layout of the PSoC5
@@ -14,7 +14,7 @@
 ;*
 ;*  Note:
 ;*
-;*  romvectors: Cypress default Interrupt sevice routine vector table.
+;*  romvectors: Cypress default Interrupt service routine vector table.
 ;*
 ;*      This is the ISR vector table at bootup. Used only for the reset vector.
 ;*
@@ -25,7 +25,7 @@
 ;*
 ;*
 ;********************************************************************************
-;* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+;* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ;* You may use this file only in accordance with the license, terms, conditions,
 ;* disclaimers, and limitations in the end user license agreement accompanying
 ;* the software package with which this file was provided.
@@ -112,11 +112,11 @@ APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
         .ANY (+RW, +ZI)
     }
 
-    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x1000 - 0x4000) EMPTY 0x1000
+    ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
     {
     }
 
-    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x4000
+    ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
     {
     }
 }
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
index 14bcbf8d..55a20e28 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: Cm3Start.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  Startup code for the ARM CM3.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -52,6 +52,12 @@ CY_ISR(IntDefaultHandler);
     extern void __iar_data_init3 (void);
 #endif  /* (__ARMCC_VERSION) */
 
+#if defined(__GNUC__)
+    #include <errno.h>
+    extern int  errno;
+    extern int  end;
+#endif  /* defined(__GNUC__) */
+
 /* Global variables */
 #if !defined (__ICCARM__)
     CY_NOINIT static uint32 cySysNoInitDataValid;
@@ -76,7 +82,7 @@ cyisraddress CyRamVectors[CY_NUM_VECTORS];
 ********************************************************************************
 *
 * Summary:
-*  This function is called for all interrupts, other than reset, that get
+*  This function is called for all interrupts, other than a reset that gets
 *  called before the system is setup.
 *
 * Parameters:
@@ -95,7 +101,7 @@ CY_ISR(IntDefaultHandler)
     while(1)
     {
         /***********************************************************************
-        * We should never get here. If we do, a serious problem occured, so go
+        * We must not get here. If we do, a serious problem occurs, so go
         * into an infinite loop.
         ***********************************************************************/
     }
@@ -104,7 +110,7 @@ CY_ISR(IntDefaultHandler)
 
 #if defined(__ARMCC_VERSION)
 
-/* Local function for the device reset. */
+/* Local function for device reset. */
 extern void Reset(void);
 
 /* Application entry point. */
@@ -161,7 +167,7 @@ void Reset(void)
 ********************************************************************************
 *
 * Summary:
-*  This function is called imediatly before the users main
+*  This function is called immediately before the users main
 *
 * Parameters:
 *  None
@@ -179,7 +185,7 @@ void $Sub$$main(void)
 
     while (1)
     {
-        /* If main returns it is undefined what we should do. */
+        /* If main returns, it is undefined what we should do. */
     }
 }
 
@@ -193,7 +199,7 @@ extern void __cy_stack(void);
 /* Application entry point. */
 extern int main(void);
 
-/* The static objects constructors initializer */
+/* Static objects constructors initializer */
 extern void __libc_init_array(void);
 
 typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
@@ -211,6 +217,84 @@ extern const char __cy_region_num __attribute__((weak));
 #define __cy_region_num ((size_t)&__cy_region_num)
 
 
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+*  Exit a program without cleaning up files. If your system doesn't provide
+*  this, it is best to avoid linking with subroutines that require it (exit,
+*  system).
+*
+* Parameters:
+*  status: Status caused program exit.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+    /* Cause divide by 0 exception */
+    int x = status / (int) INT_MAX;
+    x = 4 / x;
+
+    while(1)
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+*  Increase program data space. As malloc and related functions depend on this,
+*  it is useful to have a working implementation. The following suffices for a
+*  standalone system; it exploits the symbol end automatically defined by the
+*  GNU linker.
+*
+* Parameters:
+*  nbytes: The number of bytes requested (if the parameter value is positive)
+*  from the heap or returned back to the heap (if the parameter value is
+*  negative).
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
+    void *      returnValue;
+
+    /* The statically held previous end of the heap, with its initialization. */
+    static void *heapPointer = (void *) &end;                 /* Previous end */
+
+    if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+    {
+        returnValue  = heapPointer;
+        heapPointer += nbytes;
+    }
+    else
+    {
+        errno = ENOMEM;
+        returnValue = (void *) -1;
+    }
+
+    return (returnValue);
+}
+
+
 /*******************************************************************************
 * Function Name: Reset
 ********************************************************************************
@@ -249,17 +333,6 @@ void Reset(void)
     Start_c();
 }
 
-__attribute__((weak))
-void _exit(int status)
-{
-    /* Cause a divide by 0 exception */
-    int x = status / INT_MAX;
-    x = 4 / x;
-
-    while(1)
-    {
-    }
-}
 
 /*******************************************************************************
 * Function Name: Start_c
@@ -267,7 +340,7 @@ void _exit(int status)
 *
 * Summary:
 *  This function handles initializing the .data and .bss sections in
-*  preperation for running standard C code.  Once initialization is complete
+*  preparation for running the standard C code.  Once initialization is complete
 *  it will call main(). This function will never return.
 *
 * Parameters:
@@ -284,7 +357,7 @@ void Start_c(void)
     const struct __cy_region *rptr = __cy_regions;
 
     /* Initialize memory */
-    for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+    for (regions = __cy_region_num; regions != 0u; regions--)
     {
         uint32 *src = (uint32 *)rptr->init;
         uint32 *dst = (uint32 *)rptr->data;
@@ -293,13 +366,18 @@ void Start_c(void)
 
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = *src++;
+            *dst = *src;
+            dst++;
+            src++;
         }
         limit = rptr->zero_size;
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = 0u;
+            *dst = 0u;
+            dst++;
         }
+
+        rptr++;
     }
 
     /* Invoke static objects constructors */
@@ -320,8 +398,8 @@ void Start_c(void)
 ********************************************************************************
 *
 * Summary:
-*  This function perform early initializations for the IAR Embedded
-*  Workbench IDE. It is executed in the context of reset interrupt handler
+*  This function performs early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of a reset interrupt handler
 *  before the data sections are initialized.
 *
 * Parameters:
@@ -383,14 +461,14 @@ int __low_level_init(void)
     const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
 #endif  /* defined (__ICCARM__) */
 {
-    INITIAL_STACK_POINTER,   /* The initial stack pointer  0 */
-    #if defined (__ICCARM__) /* The reset handler          1 */
+    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
+    #if defined (__ICCARM__) /* Reset handler          1 */
         __iar_program_start,
     #else
         (cyisraddress)&Reset,
     #endif  /* defined (__ICCARM__) */
-    &IntDefaultHandler,      /* The NMI handler            2 */
-    &IntDefaultHandler,      /* The hard fault handler     3 */
+    &IntDefaultHandler,      /* NMI handler            2 */
+    &IntDefaultHandler,      /* Hard fault handler     3 */
 };
 
 #if defined(__ARMCC_VERSION)
@@ -438,7 +516,7 @@ void initialize_psoc(void)
     /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
     CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
 
-    /* Point NVIC at the RAM vector table. */
+    /* Point NVIC at RAM vector table. */
     *CYINT_VECT_TABLE = CyRamVectors;
 
     /* Initialize the configuration registers. */
@@ -446,7 +524,7 @@ void initialize_psoc(void)
 
     #if(0u != DMA_CHANNELS_USED__MASK0)
 
-        /* Setup DMA - only necessary if the design contains a DMA component. */
+        /* Setup DMA - only necessary if design contains DMA component. */
         CyDmacConfigure();
 
     #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
index 5ac6ba97..f72c2559 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: CyBootAsmGnu.s
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Assembly routines for GNU as.
 *
 ********************************************************************************
-* Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
index f2e8f940..2c356b3e 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmIar.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for IAR Embedded Workbench IDE.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2013-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -30,7 +30,7 @@
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic. Therefore, to avoid corrupting processor state, it must be the policy 
+;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
 ;  that all interrupt routines restore the interrupt enable bits as they were 
 ;  found on entry.
 ;
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
index c10181e7..8753fe17 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmRv.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for RealView.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -110,7 +110,7 @@ byte_4 DCB 0x09
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
 ;  corrupting processor state, it must be the policy that all interrupt routines
 ;  restore the interrupt enable bits as they were found on entry.
 ;
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
index e3858c62..c41fea02 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the DMAC component. The API includes functions for the
@@ -18,10 +18,10 @@
 *  not being used.
 *
 *  This code uses the first byte of each TD to manage the free list of TD's.
-*  The user can over write this once the TD is allocated.
+*  The user can overwrite this once the TD is allocated.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,8 +37,8 @@
 * are initialized. To avoid zeroing, these variables should be initialized
 * properly during segments initialization as well.
 *******************************************************************************/
-static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements in the list */
-static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
 static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
 
 
@@ -48,7 +48,7 @@ static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map
 *
 * Summary:
 *  Creates a linked list of all the TDs to be allocated. This function is called
-*  by the startup code; you do not normally need to call it. You could call this
+*  by the startup code; you do not normally need to call it. You can call this
 *  function if all of the DMA channels are inactive.
 *
 * Parameters:
@@ -72,7 +72,7 @@ void CyDmacConfigure(void)
         CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
     }
 
-    /* Make the last one point to zero. */
+    /* Make last one point to zero. */
     CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
 }
 
@@ -102,8 +102,8 @@ void CyDmacConfigure(void)
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 uint8 CyDmacError(void) 
@@ -131,15 +131,15 @@ uint8 CyDmacError(void)
 *   Set to 1 when an access is attempted to an invalid address.
 *
 *  DMAC_BUS_TIMEOUT:
-*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Return:
 *  None
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 void CyDmacClearError(uint8 error) 
@@ -153,7 +153,7 @@ void CyDmacClearError(uint8 error)
 ********************************************************************************
 *
 * Summary:
-*  When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the
+*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
 *  address of the error is written to the error address register and can be read
 *  with this function.
 *
@@ -198,12 +198,12 @@ uint8 CyDmaChAlloc(void)
     /* Enter critical section! */
     interruptState = CyEnterCriticalSection();
 
-    /* Look for a free channel. */
+    /* Look for free channel. */
     for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
     {
         if(0uL == (CyDmaChannels & channel))
         {
-            /* Mark the channel as used. */
+            /* Mark channel as used. */
             CyDmaChannels |= channel;
             break;
         }
@@ -249,7 +249,7 @@ cystatus CyDmaChFree(uint8 chHandle)
         /* Enter critical section */
         interruptState = CyEnterCriticalSection();
 
-        /* Clear the bit mask that keeps track of ownership. */
+        /* Clear bit mask that keeps track of ownership. */
         CyDmaChannels &= ~(((uint32) 1u) << chHandle);
 
         /* Exit critical section */
@@ -277,10 +277,10 @@ cystatus CyDmaChFree(uint8 chHandle)
 *   Preserves the original TD state when the TD has completed. This parameter
 *   applies to all TDs in the channel.
 *
-*   0 - When a TD is completed, the DMAC leaves the TD configuration values in
+*   0 - When TD is completed, the DMAC leaves the TD configuration values in
 *   their current state, and does not restore them to their original state.
 *
-*   1 - When a TD is completed, the DMAC restores the original configuration
+*   1 - When TD is completed, the DMAC restores the original configuration
 *   values of the TD.
 *
 *  When preserveTds is set, the TD slot that equals the channel number becomes
@@ -309,14 +309,14 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds)
     {
         if (0u != preserveTds)
         {
-            /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
-            *  preserve the original TD chain
+            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve original TD chain
             */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
         }
         else
         {
-            /* Store the intermediate and final TD states on top of the original TD chain */
+            /* Store intermediate and final TD states on top of original TD chain */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
         }
 
@@ -365,7 +365,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
         /* Disable channel */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
 
-        /* Store the intermediate and final TD states on top of the original TD chain */
+        /* Store intermediate and final TD states on top of original TD chain */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
         status = CYRET_SUCCESS;
     }
@@ -379,7 +379,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
 ********************************************************************************
 *
 * Summary:
-*  Clears pending DMA data request.
+*  Clears pending the DMA data request.
 *
 * Parameters:
 *  uint8 chHandle:
@@ -518,7 +518,7 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
 *   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
 *
 *  uint8 startTd:
-*   The index of TD to set as the first TD associated with the channel. Zero is
+*   Set the TD index as the first TD associated with the channel. Zero is
 *   a valid TD index.
 *
 * Return:
@@ -759,13 +759,13 @@ uint8 CyDmaTdAllocate(void)
 
     if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
     {
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         element = CyDmaTdFreeIndex;
 
         /* Decrement the count. */
         CyDmaTdCurrentNumber--;
 
-        /* Update the next available pointer. */
+        /* Update next available pointer. */
         CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
     }
 
@@ -798,7 +798,7 @@ void CyDmaTdFree(uint8 tdHandle)
         /* Enter critical section! */
         uint8 interruptState = CyEnterCriticalSection();
 
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
 
         /* Set new Next Available. */
@@ -942,9 +942,9 @@ cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nex
 *  CYRET_BAD_PARAM if tdHandle is invalid.
 *
 * Side Effects:
-*  If a TD has a transfer count of N and is executed, the transfer count becomes
+*  If TD has a transfer count of N and is executed, the transfer count becomes
 *  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-*  request for indefinite transfer. Be careful when requesting a TD with a
+*  request for indefinite transfer. Be careful when requesting TD with a
 *  transfer count of zero.
 *
 *******************************************************************************/
@@ -955,25 +955,25 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 *
 
     if(tdHandle < CY_DMA_NUMBEROF_TDS)
     {
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != transferCount)
         {
-            /* Get the 12 bits of the transfer count */
+            /* Get 12 bits of transfer count */
             reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
             *transferCount = 0x0FFFu & CY_GET_REG16(convert);
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != nextTd)
         {
-            /* Get the Next TD pointer */
+            /* Get Next TD pointer */
             *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != configuration)
         {
-            /* Get the configuration the TD */
+            /* Get configuration TD */
             *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
         }
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
index 5dfac11a..f78f3e32 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the DMA Controller.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -116,7 +116,7 @@ typedef struct dmac_tdmem2_struct
 
 #define CY_DMA_TD_SIZE              0x08u
 
-/* The "u" was removed as workaround for Keil compiler bug */
+/* "u" was removed as workaround for Keil compiler bug */
 #define CY_DMA_TD_SWAP_EN           0x80
 #define CY_DMA_TD_SWAP_SIZE4        0x40
 #define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
@@ -178,7 +178,18 @@ typedef struct dmac_tdmem2_struct
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
 #define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
index 6f27d8c0..fc1eee33 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the FLASH/EEPROM.
@@ -13,7 +13,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,9 +21,12 @@
 
 #include "CyFlash.h"
 
+/*  The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
+
 
 /*******************************************************************************
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
 * The first byte is the sign of the temperature (0 = negative, 1 = positive).
 * The second byte is the magnitude.
 *******************************************************************************/
@@ -35,6 +38,7 @@ uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 
 
 static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
 
 
 /*******************************************************************************
@@ -53,13 +57,48 @@ static cystatus CySetTempInt(void);
 *******************************************************************************/
 void CyFlash_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or eeprom to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable flash. Active flash macros consume current, but re-enabling a
+    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+    * macro during that time, it will be stalled. This bit allows the flash to
+    * be enabled even if the CPU is disabled, which allows a quicker return to
+    * code execution.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
 
-    CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -83,11 +122,14 @@ void CyFlash_Start(void)
 *******************************************************************************/
 void CyFlash_Stop(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -97,7 +139,7 @@ void CyFlash_Stop(void)
 *
 * Summary:
 *  Sends a command to the SPC to read the die temperature. Sets a global value
-*  used by the Write functions. This function must be called once before
+*  used by the Write function. This function must be called once before
 *  executing a series of Flash writing functions.
 *
 * Parameters:
@@ -153,13 +195,65 @@ static cystatus CySetTempInt(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        status = CySpcGetAlgorithm();
+
+        if(CYRET_STARTED == status)
+        {
+            while(CY_SPC_BUSY)
+            {
+                /* Spin until idle. */
+                CyDelayUs(1u);
+            }
+
+            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySetTemp
 ********************************************************************************
 *
 * Summary:
-*  This is a wraparound for CySetTempInt(). It is used to return second
-*  successful read of temperature value.
+*  This is a wraparound for CySetTempInt(). It is used to return the second
+*  successful read of the temperature value.
 *
 * Parameters:
 *  None
@@ -171,14 +265,14 @@ static cystatus CySetTempInt(void)
 *   CYRET_UNKNOWN if there was an SPC error.
 *
 *  uint8 dieTemperature[2]:
-*   Holds die temperature for the flash writting algorithm. The first byte is
+*   Holds the die temperature for the flash writing algorithm. The first byte is
 *   the sign of the temperature (0 = negative, 1 = positive). The second byte is
 *   the magnitude.
 *
 *******************************************************************************/
 cystatus CySetTemp(void) 
 {
-    cystatus status = CySetTempInt();
+    cystatus status = CyFlashGetSpcAlgorithm();
 
     if(status == CYRET_SUCCESS)
     {
@@ -195,12 +289,12 @@ cystatus CySetTemp(void)
 *
 * Summary:
 *  Sets the user supplied temporary buffer to store SPC data while performing
-*  flash and EEPROM commands. This buffer is only necessary when Flash ECC is
+*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
 *  disabled.
 *
 * Parameters:
 *  buffer:
-*   Address of block of memory to store temporary memory. The size of the block
+*   The address of a block of memory to store temporary memory. The size of the block
 *   of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
 *
 * Return:
@@ -219,10 +313,12 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
         if(NULL == buffer)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_BAD_PARAM;
         }
         else if(CySpcLock() != CYRET_SUCCESS)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_LOCKED;
         }
         else
@@ -233,7 +329,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
     #else
 
-        /* To supress the warning */
+        /* To suppress warning */
         buffer = buffer;
 
     #endif  /* (CYDEV_ECC_ENABLE == 0u) */
@@ -242,120 +338,48 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 }
 
 
-#if(CYDEV_ECC_ENABLE == 1)
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sends a command to the SPC to load and program a row of data in
-    *  Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID:    ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress: rowAddress of flash row to program.
-    *  rowData:    Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint16 rowSize;
-        cystatus status;
-
-        rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
-        status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
-        return(status);
-    }
-
-#else
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *   Sends a command to the SPC to load and program a row of data in
-    *   Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID      : ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress   : rowAddress of flash row to program.
-    *  rowData      : Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint8 i;
-        uint32 offset;
-        uint16 rowSize;
-        cystatus status;
-
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
-            {
-                rowSize = CYDEV_EEPROM_ROW_SIZE;
-            }
-            else
-            {
-                rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
-
-                /* Save the ECC area. */
-                offset = CYDEV_ECC_BASE +
-                        ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
-                        ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
-
-                for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
-                {
-                    *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-                }
-            }
-
-            /* Copy the rowdata to the temporary buffer. */
-        #if(CY_PSOC3)
-            (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
-        #else
-            (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
-        #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to load and program a row of data in
+*  Flash or EEPROM.
+*
+* Parameters:
+*  arrayID:    ID of the array to write.
+*   The type of write, Flash or EEPROM, is determined from the array ID.
+*   The arrays in the part are sequential starting at the first ID for the
+*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+*  rowAddress: rowAddress of flash row to program.
+*  rowData:    Array of bytes to write.
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED if the SPC is already in use.
+*   CYRET_CANCELED if command not accepted
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
+{
+    uint16 rowSize;
+    cystatus status;
 
-        return(status);
-    }
+    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
 
-#endif /* (CYDEV_ECC_ENABLE == 0u) */
+    return(status);
+}
 
 
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
 #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
 
     /*******************************************************************************
@@ -363,7 +387,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a command to the SPC to load and program a row of config data in flash.
+    *  Sends a command to the SPC to load and program a row of config data in the Flash.
     *  This function is only valid for Flash array IDs (not for EEPROM).
     *
     * Parameters:
@@ -371,8 +395,8 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     *   The arrays in the part are sequential starting at the first ID for the
     *   specific memory type. The array ID for the Flash memory lasts
     *   from 0x00 to 0x3F.
-    *  rowAddress:   Address of the sector to erase.
-    *  rowECC:       Array of bytes to write.
+    *  rowAddress:   The address of the sector to erase.
+    *  rowECC:       The array of bytes to write.
     *
     * Return:
     *  status:
@@ -385,42 +409,9 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
     
     {
-        uint32 offset;
-        uint16 i;
         cystatus status;
 
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            /* Read the existing flash data. */
-            offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
-                     ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
-
-            #if (CYDEV_FLS_BASE != 0u)
-                offset += CYDEV_FLS_BASE;
-            #endif  /* (CYDEV_FLS_BASE != 0u) */
-
-            for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
-            {
-                rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-            }
-
-            #if(CY_PSOC3)
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (void *)(uint32)rowECC,
-                              (int16)CYDEV_ECC_ROW_SIZE);
-            #else
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (const void *)rowECC,
-                              CYDEV_ECC_ROW_SIZE);
-            #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
 
         return (status);
     }
@@ -433,7 +424,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 * Function Name: CyWriteRowFull
 ********************************************************************************
 * Summary:
-*  Sends a command to the SPC to load and program a row of data in flash.
+*  Sends a command to the SPC to load and program a row of data in the Flash.
 *  rowData array is expected to contain Flash and ECC data if needed.
 *
 * Parameters:
@@ -452,63 +443,107 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
         
 {
-    cystatus status;
+    cystatus status = CYRET_SUCCESS;
 
-    if(CySpcLock() == CYRET_SUCCESS)
+    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
     {
-        /* Load row data into SPC internal latch */
-        status = CySpcLoadRow(arrayId, rowData, rowSize);
+        status = CYRET_BAD_PARAM;
+    }
 
-        if(CYRET_STARTED == status)
+    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
+    {
+        /* Flash */
+        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
         {
-            while(CY_SPC_BUSY)
-            {
-                /* Wait for SPC to finish and get SPC status */
-                CyDelayUs(1u);
-            }
+            status = CYRET_BAD_PARAM;
+        }
+    }
+    else
+    {
+        /* EEPROM */
+        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
 
-            /* Hide SPC status */
-            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-            {
-                status = CYRET_SUCCESS;
-            }
-            else
-            {
-                status = CYRET_UNKNOWN;
-            }
+        if(CY_EEPROM_SIZEOF_ROW != rowSize)
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
 
-            if(CYRET_SUCCESS == status)
+    if(rowData == NULL)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    if(status == CYRET_SUCCESS)
+    {
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Load row data into SPC internal latch */
+            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+            if(CYRET_STARTED == status)
             {
-                /* Erase and program flash with the data from SPC interval latch */
-                status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait for SPC to finish and get SPC status */
+                    CyDelayUs(1u);
+                }
 
-                if(CYRET_STARTED == status)
+                /* Hide SPC status */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
                 {
-                    while(CY_SPC_BUSY)
-                    {
-                        /* Wait for SPC to finish and get SPC status */
-                        CyDelayUs(1u);
-                    }
+                    status = CYRET_SUCCESS;
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
 
-                    /* Hide SPC status */
-                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                    {
-                        status = CYRET_SUCCESS;
-                    }
-                    else
+                if(CYRET_SUCCESS == status)
+                {
+                    /* Erase and program flash with data from SPC interval latch */
+                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+                    if(CYRET_STARTED == status)
                     {
-                        status = CYRET_UNKNOWN;
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait for SPC to finish and get SPC status */
+                            CyDelayUs(1u);
+                        }
+
+                        /* Hide SPC status */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                        else
+                        {
+                            status = CYRET_UNKNOWN;
+                        }
                     }
                 }
             }
-
+            CySpcUnlock();
+        }   /* if(CySpcLock() == CYRET_SUCCESS) */
+        else
+        {
+            status = CYRET_LOCKED;
         }
-
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_LOCKED;
     }
 
     return(status);
@@ -521,9 +556,9 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, u
 *
 * Summary:
 *  Sets the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash. This function must be called before increasing CPU
-*  clock frequency. It can optionally be called after lowering CPU clock
-*  frequency in order to improve CPU performance.
+*  coming back from the Flash. This function must be called before increasing the CPU
+*  clock frequency. It can optionally be called after lowering the CPU clock
+*  frequency in order to improve the CPU performance.
 *
 * Parameters:
 *  uint8 freq:
@@ -542,55 +577,42 @@ void CyFlash_SetWaitCycles(uint8 freq)
 
     /***************************************************************************
     * The number of clock cycles the cache will wait before it samples data
-    * coming back from Flash must be equal or greater to to the CPU frequency
+    * coming back from the Flash must be equal or greater to to the CPU frequency
     * outlined in clock cycles.
     ***************************************************************************/
 
-    #if (CY_PSOC3)
-
-        if (freq <= 22u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 44u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC3) */
-
-
-    #if (CY_PSOC5)
-
-        if (freq <= 16u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 33u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 50u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC5) */
+    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
+    }
+#if (CY_PSOC5)
+    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
+    }
+    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
+    }
+#endif  /* (CY_PSOC5) */
+    else
+    {
+        /* Halt CPU in debug mode if frequency is invalid */
+        CYASSERT(0u != 0u);
+    }
 
     /* Restore global interrupt enable state */
     CyExitCriticalSection(interruptState);
@@ -613,11 +635,45 @@ void CyFlash_SetWaitCycles(uint8 freq)
 *******************************************************************************/
 void CyEEPROM_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or EEPROM to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+    * the EE will not acknowledge a PHUB request.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -637,11 +693,14 @@ void CyEEPROM_Start(void)
 *******************************************************************************/
 void CyEEPROM_Stop (void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    uint8 interruptState;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -661,12 +720,12 @@ void CyEEPROM_Stop (void)
 *******************************************************************************/
 void CyEEPROM_ReadReserve(void) 
 {
-    /* Make a request for PHUB to have access */
-    *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+    /* Make request for PHUB to have access */
+    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
 
-    while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
+    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
     {
-        /* Wait for acknowledgement from PHUB */
+        /* Wait for acknowledgment from PHUB */
     }
 }
 
@@ -687,7 +746,7 @@ void CyEEPROM_ReadReserve(void)
 *******************************************************************************/
 void CyEEPROM_ReadRelease(void) 
 {
-    *CY_FLASH_EE_SCR_PTR |= 0x00u;
+    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
 }
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
index 002b2ebf..b8a18c2f 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the FLASH/EEPROM.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,13 +41,19 @@ extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 #define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
 #define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
 
+#if(CYDEV_ECC_ENABLE == 0)
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
 #define CY_EEPROM_BASE              (CYDEV_EE_BASE)
 #define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
 #define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EEPROM_SECTOR_SIZE)
 #define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS       (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
 #define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-
+#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
 
 #if !defined(CYDEV_FLS_BASE)
     #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
@@ -85,13 +91,29 @@ void CyEEPROM_ReadRelease(void) ;
 /***************************************
 *     Registers
 ***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
+
 /* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
 
 /* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
 
 
 /* Cache Control Register */
@@ -119,35 +141,64 @@ void CyEEPROM_ReadRelease(void) ;
 ***************************************/
 
 /* Power Mode Masks */
-#define CY_FLASH_PM_EE_MASK                 (0x10u)
-#define CY_FLASH_PM_FLASH_MASK              (0x01u)
 
-/* Frequency Constants */
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
+
+/* Enable Flash */
 #if (CY_PSOC3)
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
+#else
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
+#endif  /* (CY_PSOC3) */
+
 
-    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
-    #define CY_FLASH_GREATER_44MHz              (0x03u)
 
+/* Frequency Constants */
+#if (CY_PSOC3)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
 #endif  /* (CY_PSOC3) */
 
 #if (CY_PSOC5)
-
-    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
-    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
-    #define CY_FLASH_GREATER_51MHz              (0x00u)
-
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
+    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
+    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
+    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
 #endif  /* (CY_PSOC5) */
 
 #define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
 #define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-#define CY_FLASH_EE_STARTUP_DELAY               (5u)
 
 #define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
 #define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
 
 
+#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
 
 /* Default values for getting temperature. */
 
@@ -167,7 +218,42 @@ void CyEEPROM_ReadRelease(void) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
+    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
+    #define CY_FLASH_GREATER_51MHz              (0x00u)
+#endif  /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
+    #define CY_FLASH_GREATER_44MHz              (0x03u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
 *******************************************************************************/
 #define FLASH_SIZE                  (CY_FLASH_SIZE)
 #define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
@@ -177,12 +263,10 @@ void CyEEPROM_ReadRelease(void) ;
 #define EEPROM_SIZEOF_SECTOR        (CY_EEPROM_SIZEOF_ARRAY)
 #define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
 #define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_NUMBER_SECTORS    (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_SIZEOF_SECTOR     (CY_EEPROM_SIZEOF_ARRAY)
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
 *******************************************************************************/
 #define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
index 5278bdf1..8d3c1c4f 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
@@ -1,16 +1,16 @@
 /*******************************************************************************
 * File Name: CyLib.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   Provides system API for the clocking, interrupts and watchdog timer.
+*   Provides a system API for the clocking, interrupts and watchdog timer.
 *
 *  Note:
 *   Documentation of the API's in this file is located in the
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -49,6 +49,12 @@ static uint8 CyUSB_PowerOnCheck(void)  ;
 static void CyIMO_SetTrimValue(uint8 freq) ;
 static void CyBusClk_Internal_SetDivider(uint16 divider);
 
+#if(CY_PSOC5)
+	static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+    static void CySysTickServiceCallbacks(void);
+    uint32 CySysTickInitVar = 0u;
+#endif  /* (CY_PSOC5) */
+
 
 /*******************************************************************************
 * Function Name: CyPLL_OUT_Start
@@ -72,7 +78,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider);
 *     clock can still be used.
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -95,7 +101,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
     uint8 pmTwCfg2State;
 
 
-    /* Enables the PLL circuit  */
+    /* Enables PLL circuit  */
     CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
 
     if(wait != 0u)
@@ -111,7 +117,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
 
         while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
             if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
             {
                 if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
@@ -180,11 +186,11 @@ void CyPLL_OUT_Stop(void)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -235,11 +241,11 @@ void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -279,7 +285,7 @@ void CyPLL_OUT_SetSource(uint8 source)
 *  None
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -305,7 +311,7 @@ void CyIMO_Start(uint8 wait)
 
     if(0u != wait)
     {
-        /* Need to turn on the 100KHz ILO if it happens to not already be running.*/
+        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
         ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
         pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
         pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
@@ -314,7 +320,7 @@ void CyIMO_Start(uint8 wait)
 
         while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
         }
 
         if(0u == ilo100KhzEnable)
@@ -442,7 +448,7 @@ static void CyIMO_SetTrimValue(uint8 freq)
         /* If USB is powered */
         if(usbPowerOn == 1u)
         {
-            /* Lock the USB Oscillator */
+            /* Lock USB Oscillator */
             CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
         }
         break;
@@ -477,11 +483,11 @@ static void CyIMO_SetTrimValue(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When the USB setting is chosen, the USB clock locking circuit is enabled.
@@ -495,15 +501,15 @@ void CyIMO_SetFreq(uint8 freq)
     uint8 nextFreq;
 
     /***************************************************************************
-    * When changing the IMO frequency the Trim values must also be set
+    * If the IMO frequency is changed,the Trim values must also be set
     * accordingly.This requires reading the current frequency. If the new
-    * frequency is faster, then set the new trim and then change the frequency,
-    * otherwise change the frequency and then set the new trim values.
+    * frequency is faster, then set a new trim and then change the frequency,
+    * otherwise change the frequency and then set new trim values.
     ***************************************************************************/
 
     currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
 
-    /* Check if the requested frequency is USB. */
+    /* Check if requested frequency is USB. */
     nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
 
     switch (currentFreq)
@@ -545,11 +551,11 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq >= currentFreq)
     {
-        /* Set the new trim first */
+        /* Set new trim first */
         CyIMO_SetTrimValue(freq);
     }
 
-    /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
     switch(freq)
     {
     case CY_IMO_FREQ_3MHZ:
@@ -599,7 +605,7 @@ void CyIMO_SetFreq(uint8 freq)
         break;
     }
 
-    /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */
+    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
     if (freq == CY_IMO_FREQ_USB)
     {
         CyIMO_EnableDoubler();
@@ -611,7 +617,7 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq < currentFreq)
     {
-        /* Set the new trim after setting the frequency */
+        /* Set the trim after setting frequency */
         CyIMO_SetTrimValue(freq);
     }
 }
@@ -625,7 +631,7 @@ void CyIMO_SetFreq(uint8 freq)
 *  Sets the source of the clock output from the IMO block.
 *
 *  The output from the IMO is by default the IMO itself. Optionally the MHz
-*  Crystal or a DSI input can be the source of the IMO output instead.
+*  Crystal or DSI input can be the source of the IMO output instead.
 *
 * Parameters:
 *   source: CY_IMO_SOURCE_DSI to set the DSI as source.
@@ -636,11 +642,11 @@ void CyIMO_SetFreq(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -687,7 +693,7 @@ void CyIMO_SetSource(uint8 source)
 *******************************************************************************/
 void CyIMO_EnableDoubler(void) 
 {
-    /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */
+    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
     CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
 }
 
@@ -733,11 +739,11 @@ void CyIMO_DisableDoubler(void)
 *  The current source and the new source must both be running and stable before
 *  calling this function.
 *
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -757,18 +763,18 @@ void CyMasterClk_SetSource(uint8 source)
 *
 * Parameters:
 *  uint8 divider:
-*   Valid range [0-255]. The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   The valid range is [0-255]. The clock will be divided by this value + 1.
+*   For example to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When changing the Master or Bus clock divider value from div-by-n to div-by-1
@@ -787,12 +793,12 @@ void CyMasterClk_SetDivider(uint8 divider)
 ********************************************************************************
 *
 * Summary:
-*  Function used by CyBusClk_SetDivider(). For internal use only.
+*  The function used by CyBusClk_SetDivider(). For internal use only.
 *
 * Parameters:
 *   divider: Valid range [0-65535].
 *   The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
@@ -807,7 +813,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
     /* Enable mask bits to enable shadow loads */
     CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
 
-    /* Update Shadow Divider Value Register with the new divider */
+    /* Update Shadow Divider Value Register with new divider */
     CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
     CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
 
@@ -827,21 +833,21 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
 ********************************************************************************
 *
 * Summary:
-*  Sets the divider value used to generate Bus Clock.
+*  Sets the divider value used to generate the Bus Clock.
 *
 * Parameters:
 *  divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-*  For example to divide by 2 this parameter should be set to 1.
+*  For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -853,13 +859,13 @@ void CyBusClk_SetDivider(uint16 divider)
 
     interruptState = CyEnterCriticalSection();
 
-    /* Work around to set the bus clock divider value */
+    /* Work around to set bus clock divider value */
     busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
     busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
 
     if ((divider == 0u) || (busClkDiv == 0u))
     {
-        /* Save away the master clock divider value */
+        /* Save away master clock divider value */
         masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
 
         if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
@@ -870,7 +876,7 @@ void CyBusClk_SetDivider(uint16 divider)
 
         if (divider == 0u)
         {
-            /* Set the SSS bit and the divider register desired value */
+            /* Set SSS bit and divider register desired value */
             CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
             CyBusClk_Internal_SetDivider(divider);
         }
@@ -880,7 +886,7 @@ void CyBusClk_SetDivider(uint16 divider)
             CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
         }
 
-        /* Restore the master clock */
+        /* Restore master clock */
         CyMasterClk_SetDivider(masterClkDiv);
     }
     else
@@ -904,17 +910,17 @@ void CyBusClk_SetDivider(uint16 divider)
     *
     * Parameters:
     *  divider: Valid range [0-15]. The clock will be divided by this value + 1.
-    *  For example to divide by 2 this parameter should be set to 1.
+    *  For example, to divide this parameter by two should be set to 1.
     *
     * Return:
     *  None
     *
     * Side Effects:
-    *  If as result of this function execution the CPU clock frequency is increased
-    *  then the number of clock cycles the cache will wait before it samples data
-    *  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-    *  with appropriate parameter. It can be optionally called if CPU clock
-    *  frequency is lowered in order to improve CPU performance.
+    *  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
     *  See CyFlash_SetWaitCycles() description for more information.
     *
     *******************************************************************************/
@@ -972,7 +978,7 @@ void CyUsbClk_SetSource(uint8 source)
 *******************************************************************************/
 void CyILO_Start1K(void) 
 {
-    /* Set the bit 1 of ILO RS */
+    /* Set bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
 }
 
@@ -984,7 +990,7 @@ void CyILO_Start1K(void)
 * Summary:
 *  Disables the ILO 1 KHz oscillator.
 *
-*  Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power
+*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
 *  mode APIs are expected to be used. For more information, refer to the Power
 *  Management section of this document.
 *
@@ -1000,7 +1006,7 @@ void CyILO_Start1K(void)
 *******************************************************************************/
 void CyILO_Stop1K(void) 
 {
-    /* Clear the bit 1 of ILO RS */
+    /* Clear bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
 }
 
@@ -1064,7 +1070,7 @@ void CyILO_Stop100K(void)
 *******************************************************************************/
 void CyILO_Enable33K(void) 
 {
-    /* Set the bit 5 of ILO RS */
+    /* Set bit 5 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
 }
 
@@ -1141,7 +1147,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
     /* Get current state. */
     state = CY_LIB_SLOWCLK_ILO_CR0_REG;
 
-    /* Set the the oscillator power mode. */
+    /* Set the oscillator power mode. */
     if(mode != CY_ILO_FAST_START)
     {
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
@@ -1151,7 +1157,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
     }
 
-    /* Return the old mode. */
+    /* Return old mode. */
     return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
 }
 
@@ -1183,14 +1189,14 @@ void CyXTAL_32KHZ_Start(void)
         CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
     #endif  /* (CY_PSOC3) */
 
-    /* Enable operation of the 32K Crystal Oscillator */
+    /* Enable operation of 32K Crystal Oscillator */
     CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
 
     for (i = 1000u; i > 0u; i--)
     {
         if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
         {
-            /* Ready - switch to the hign power mode */
+            /* Ready - switch to high power mode */
             (void) CyXTAL_32KHZ_SetPowerMode(0u);
 
             break;
@@ -1256,9 +1262,9 @@ uint8 CyXTAL_32KHZ_ReadStatus(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the power mode for the 32 KHz oscillator used during sleep mode.
+*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
 *  Allows for lower power during sleep when there are fewer sources of noise.
-*  During active mode the oscillator is always run in high power mode.
+*  During the active mode the oscillator is always run in the high power mode.
 *
 * Parameters:
 *  uint8 mode
@@ -1345,7 +1351,7 @@ cystatus CyXTAL_Start(uint8 wait)
     uint8 pmTwCfg2Tmp;
 
 
-    /* Enables the MHz crystal oscillator circuit  */
+    /* Enables MHz crystal oscillator circuit  */
     CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
 
 
@@ -1366,19 +1372,19 @@ cystatus CyXTAL_Start(uint8 wait)
             /* Read XERR bit to clear it */
             (void) CY_CLK_XMHZ_CSR_REG;
 
-            /* Wait for a millisecond - 4 x 250 us */
+            /* Wait for 1 millisecond - 4 x 250 us */
             for(count = 4u; count > 0u; count--)
             {
                 while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
                 {
-                    /* Wait for the FTW interrupt event */
+                    /* Wait for FTW interrupt event */
                 }
             }
 
 
             /*******************************************************************
-            * High output indicates oscillator failure.
-            * Only can be used after start-up interval (1 ms) is completed.
+            * High output indicates an oscillator failure.
+            * Only can be used after a start-up interval (1 ms) is completed.
             *******************************************************************/
             if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
             {
@@ -1417,7 +1423,7 @@ cystatus CyXTAL_Start(uint8 wait)
 *******************************************************************************/
 void CyXTAL_Stop(void) 
 {
-    /* Disable the the oscillator. */
+    /* Disable oscillator. */
     FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
 }
 
@@ -1472,7 +1478,7 @@ void CyXTAL_DisableErrStatus(void)
 *
 * Summary:
 *  Reads the XERR status bit for the megahertz crystal. This status bit is a
-*  sticky clear on read value. This function is not available for PSoC5.
+*  sticky, clear on read. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1486,8 +1492,8 @@ void CyXTAL_DisableErrStatus(void)
 uint8 CyXTAL_ReadStatus(void) 
 {
     /***************************************************************************
-    * High output indicates oscillator failure. Only use this after start-up
-    * interval is completed. This can be used for status and failure recovery.
+    * High output indicates an oscillator failure. Only use this after a start-up
+    * interval is completed. This can be used for the status and failure recovery.
     ***************************************************************************/
     return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
 }
@@ -1501,7 +1507,7 @@ uint8 CyXTAL_ReadStatus(void)
 *  Enables the fault recovery circuit which will switch to the IMO in the case
 *  of a fault in the megahertz crystal circuit. The crystal must be up and
 *  running with the XERR bit at 0, before calling this function to prevent
-*  immediate fault switchover. This function is not available for PSoC5.
+*  an immediate fault switchover. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1543,7 +1549,7 @@ void CyXTAL_DisableFaultRecovery(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the startup settings for the crystal. Logic model outputs a frequency
+*  Sets the startup settings for the crystal. The logic model outputs a frequency
 *  (setting + 4) MHz when enabled.
 *
 *  This is artificial as the actual frequency is determined by an attached
@@ -1551,7 +1557,7 @@ void CyXTAL_DisableFaultRecovery(void)
 *
 * Parameters:
 *  setting: Valid range [0-31].
-*   Value is dependent on the frequency and quality of the crystal being used.
+*   The value is dependent on the frequency and quality of the crystal being used.
 *   Refer to the device TRM and datasheet for more information.
 *
 * Return:
@@ -1648,7 +1654,7 @@ void CyHalt(uint8 reason) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Forces a software reset of the device.
+*  Forces a device software reset.
 *
 * Parameters:
 *  None
@@ -1672,9 +1678,9 @@ void CySoftwareReset(void)
 *
 *  Note:
 *  CyDelay has been implemented with the instruction cache assumed enabled. When
-*  instruction cache is disabled on PSoC5, CyDelay will be two times larger. For
-*  example, with instruction cache disabled CyDelay(100) would result in about
-*  200 ms delay instead of 100 ms.
+*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+*  For example, with instruction cache disabled CyDelay(100) would result in
+*  about 200 ms delay instead of 100 ms.
 *
 * Parameters:
 *  milliseconds: number of milliseconds to delay.
@@ -1724,8 +1730,8 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
     *
     * Side Effects:
     *  CyDelayUS has been implemented with the instruction cache assumed enabled.
-    *  When instruction cache is disabled on PSoC 5, CyDelayUs will be two times
-    *  larger. For example, with instruction cache disabled CyDelayUs(100) would
+    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
     *  result in about 200 us delay instead of 100 us.
     *
     *  If the bus clock frequency is a small non-integer number, the actual delay
@@ -1745,10 +1751,10 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Sets clock frequency for CyDelay.
+*  Sets the clock frequency for CyDelay.
 *
 * Parameters:
-*  freq: Frequency of bus clock in Hertz.
+*  freq: The frequency of the bus clock in Hertz.
 *
 * Return:
 *  None
@@ -1779,7 +1785,7 @@ void CyDelayFreq(uint32 freq) CYREENTRANT
 *  Enables the watchdog timer.
 *
 *  The timer is configured for the specified count interval, the central
-*  timewheel is cleared, the setting for low power mode is configured and the
+*  timewheel is cleared, the setting for the low power mode is configured and the
 *  watchdog timer is enabled.
 *
 *  Once enabled the watchdog cannot be disabled. The watchdog counts each time
@@ -1826,11 +1832,11 @@ void CyWdtStart(uint8 ticks, uint8 lpMode)
     CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
     CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
 
-    /* Setting the low power mode */
+    /* Setting low power mode */
     CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
                        (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
 
-    /* Enables the watchdog reset */
+    /* Enables watchdog reset */
     CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
 }
 
@@ -1862,16 +1868,16 @@ void CyWdtClear(void)
 *
 * Summary:
 *  Enables the digital low voltage monitors to generate interrupt on Vddd
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vddd threshold:
+*  reset: The option to reset the device at a specified Vddd threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
 *  threshold: Sets the trip level for the voltage monitor.
-*  Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-*  interval.
+*  Values from 1.70 V to 5.45 V are accepted with an interval  of approximately
+*  250 mV.
 *
 * Return:
 *  None
@@ -1887,7 +1893,7 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
                             (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -1912,10 +1918,10 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
 *
 * Summary:
 *  Enables the analog low voltage monitors to generate interrupt on Vdda
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vdda threshold:
+*  reset: The option to reset the device at a specified Vdda threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
@@ -1936,7 +1942,7 @@ void CyVdLvAnalogEnable(uint8 reset, uint8 threshold)
     CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -2258,31 +2264,14 @@ void CyEnableInts(uint32 mask)
         CY_NOP;
         CY_NOP;
 
-        /* All entries in the cache are invalidated on the next clock cycle. */
+        /* All entries in cache are invalidated on next clock cycle. */
         CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
 
+        /* Once this is executed it's guaranteed the cache has been flushed */
+        (void) CY_CACHE_CONTROL_REG;
 
-        /***********************************************************************
-        * The prefetch unit could/would be filled with the instructions that
-        * succeed the flush. Since a flush is desired then theoretically those
-        * instructions might be considered stale/invalid.
-        ***********************************************************************/
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
+        /* Flush the pipeline */
+        CY_SYS_ISB;
 
         /* Restore global interrupt enable state */
         CyExitCriticalSection(interruptState);
@@ -2298,8 +2287,18 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *  number: Interrupt number, valid range [0-15].
-       address: Pointer to an interrupt service routine.
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    *  address: Pointer to an interrupt service routine.
     *
     * Return:
     *   The old ISR vector at this location.
@@ -2332,7 +2331,16 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *   number: The interrupt number, valid range [0-15].
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
     *
     * Return:
     *   Address of the ISR in the interrupt vector table.
@@ -2390,7 +2398,7 @@ void CyEnableInts(uint32 mask)
     *  number: Valid range [0-31].  Interrupt number
     *
     * Return:
-    *  Address of the ISR in the interrupt vector table.
+    *  The address of the ISR in the interrupt vector table.
     *
     *******************************************************************************/
     cyisraddress CyIntGetVector(uint8 number)
@@ -2471,10 +2479,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR;
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
     }
 
@@ -2609,10 +2617,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
     }
 
@@ -2630,20 +2638,20 @@ void CyEnableInts(uint32 mask)
     *  If 1 is passed as a parameter:
     *   - if any of the SC blocks are used - enable pumps for the SC blocks and
     *     start boost clock.
-    *   - For the each enabled SC block set boost clock index and enable boost
+    *   - For each enabled SC block set a boost clock index and enable the boost
     *     clock.
     *
     *  If non-1 value is passed as a parameter:
     *   - If all SC blocks are not used - disable pumps for the SC blocks and
-    *     stop boost clock.
-    *   - For the each enabled SC block clear boost clock index and disable boost
+    *     stop the boost clock.
+    *   - For each enabled SC block clear the boost clock index and disable the  boost
     *     clock.
     *
-    *  The global variable CyScPumpEnabled is updated to be equal to passed
+    *  The global variable CyScPumpEnabled is updated to be equal to passed the
     *  parameter.
     *
     * Parameters:
-    *   uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.
+    *   uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
     *                 1 - Enable
     *                 0 - Disable
     *
@@ -2707,4 +2715,391 @@ void CyEnableInts(uint32 mask)
 #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
+#if(CY_PSOC5)
+    /*******************************************************************************
+    * Function Name: CySysTickStart
+    ********************************************************************************
+    *
+    * Summary:
+    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
+    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
+    *  Refer to the corresponding function description for the details.
+
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStart(void)
+    {
+        if (0u == CySysTickInitVar)
+        {
+            CySysTickInit();
+            CySysTickInitVar = 1u;
+        }
+
+        CySysTickEnable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickInit
+    ********************************************************************************
+    *
+    * Summary:
+    *  Initializes the callback addresses with pointers to NULL, associates the
+    *  SysTick system vector with the function that is responsible for calling
+    *  registered callback functions, configures SysTick timer to generate interrupt
+    * every 1 ms.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set.
+    *
+    *  The 1 ms interrupt interval is configured based on the frequency determined
+    *  by PSoC Creator at build time. If System clock frequency is changed in
+    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
+    *
+    *******************************************************************************/
+    void CySysTickInit(void)
+    {
+        uint32 i;
+
+        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+        {
+            CySysTickCallbacks[i] = (void *) 0;
+        }
+
+    	(void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+        CySysTickSetReload(cydelay_freq_hz/1000u);
+        CySysTickClear();
+        CyIntEnable(CY_INT_SYSTICK_IRQN);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick timer and its interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnable(void)
+    {
+        CySysTickEnableInterrupt();
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickStop
+    ********************************************************************************
+    *
+    * Summary:
+    *  Stops the system timer (SysTick).
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStop(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickDisableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickDisableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero. This
+    *  function do not change or reset current sysTick counter value, so it should
+    *  be cleared using CySysTickClear() API.
+    *
+    * Parameters:
+    *  value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickSetReload(uint32 value)
+    {
+        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Counter reset value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetReload(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetValue
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets current SysTick counter value.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Current SysTick counter value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetValue(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetClockSource
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the clock source for the SysTick counter.
+    *
+    * Parameters:
+    *  clockSource: Clock source for SysTick counter
+    *         Define                     Clock Source
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                              clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set. If clock source is not ready this
+    *  function call will have no effect. After changing clock source to the low frequency
+    *  clock the counter and reload register values will remain unchanged so time to
+    *  the interrupt will be significantly bigger and vice versa.
+    *
+    *******************************************************************************/
+    void CySysTickSetClockSource(uint32 clockSource)
+    {
+        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+        {
+            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+        }
+        else
+        {
+            CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCountFlag
+    ********************************************************************************
+    *
+    * Summary:
+    *  The count flag is set once SysTick counter reaches zero.
+    *   The flag cleared on read.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Returns non-zero value if counter is set, otherwise zero is returned.
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetCountFlag(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickClear
+    ********************************************************************************
+    *
+    * Summary:
+    *  Clears the SysTick counter for well-defined startup.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickClear(void)
+    {
+        CY_SYS_SYST_CVR_REG = 0u;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function set the pointers to the functions that will be called on
+    *  SysTick interrupt.
+    *
+    * Parameters:
+    *  number:  The number of callback function address to be set.
+    *           The valid range is from 0 to 4.
+    *  CallbackFunction: Function address.
+    *
+    * Return:
+    *  Returns the address of the previous callback function.
+    *  The NULL is returned if the specified address in not set.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+    {
+        cySysTickCallback retVal;
+
+        retVal = CySysTickCallbacks[number];
+        CySysTickCallbacks[number] = function;
+        return (retVal);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function get the specified callback pointer.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickGetCallback(uint32 number)
+    {
+        return ((cySysTickCallback) CySysTickCallbacks[number]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickServiceCallbacks
+    ********************************************************************************
+    *
+    * Summary:
+    *  System Tick timer interrupt routine
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    static void CySysTickServiceCallbacks(void)
+    {
+        uint32 i;
+
+        /* Verify that tick timer flag was set */
+        if (1u == CySysTickGetCountFlag())
+        {
+            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+            {
+                if (CySysTickCallbacks[i] != (void *) 0)
+                {
+                    (void)(CySysTickCallbacks[i])();
+                }
+            }
+        }
+    }
+#endif /* (CY_PSOC5) */
+
+
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
index 3bc638c7..2e2c66ad 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyLib.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the system, clocking, interrupts and
@@ -11,7 +11,7 @@
 *  Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -163,6 +163,30 @@ uint8 CyVdRealTimeStatus(void) ;
 
 void CySetScPumps(uint8 enable) ;
 
+#if(CY_PSOC5)
+    /* Default interrupt handler */
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif  /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+    /* System tick timer APIs */
+    typedef void (*cySysTickCallback)(void);
+
+    void CySysTickStart(void);
+    void CySysTickInit(void);
+    void CySysTickEnable(void);
+    void CySysTickStop(void);
+    void CySysTickEnableInterrupt(void);
+    void CySysTickDisableInterrupt(void);
+    void CySysTickSetReload(uint32 value);
+    uint32 CySysTickGetReload(void);
+    uint32 CySysTickGetValue(void);
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+    cySysTickCallback CySysTickGetCallback(uint32 number);
+    void CySysTickSetClockSource(uint32 clockSource);
+    uint32 CySysTickGetCountFlag(void);
+    void CySysTickClear(void);
+#endif  /* (CY_PSOC5) */
 
 /***************************************
 * API Constants
@@ -400,6 +424,23 @@ void CySetScPumps(uint8 enable) ;
 #define CY_ALT_ACT_USB_ENABLED          (0x01u)
 
 
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * Instruction Synchronization Barrier flushes the pipeline in the processor,
+    * so that all instructions following the ISB are fetched from cache or
+    * memory, after the instruction has been completed.
+    ***************************************************************************/
+
+    #if defined(__ARMCC_VERSION)
+        #define CY_SYS_ISB       __isb(0x0f)
+    #else   /* ASM for GCC & IAR */
+        #define CY_SYS_ISB       asm volatile ("isb \n")
+    #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
 /***************************************
 * Registers
 ***************************************/
@@ -689,16 +730,29 @@ void CySetScPumps(uint8 enable) ;
     #define CY_CACHE_CONTROL_REG        (* (reg16 *) CYREG_CACHE_CC_CTL )
     #define CY_CACHE_CONTROL_PTR        (  (reg16 *) CYREG_CACHE_CC_CTL )
 
+    /* System tick registers */
+    #define CY_SYS_SYST_CSR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+    #define CY_SYS_SYST_CSR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+    #define CY_SYS_SYST_RVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+    #define CY_SYS_SYST_RVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+    #define CY_SYS_SYST_CVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+    #define CY_SYS_SYST_CVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+    #define CY_SYS_SYST_CALIB_REG       (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+    #define CY_SYS_SYST_CALIB_PTR       ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
 #elif (CY_PSOC3)
 
     /* Interrupt Address Vector registers */
     #define CY_INT_VECT_TABLE           ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
 
-    /* Interrrupt Controller Priority Registers */
+    /* Interrupt Controller Priority Registers */
     #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_INTC_PRIOR0)
     #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_INTC_PRIOR0)
 
-    /* Interrrupt Controller Set Enable Registers */
+    /* Interrupt Controller Set Enable Registers */
     #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
     #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
 
@@ -714,7 +768,7 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
     #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
 
-    /* Interrrupt Controller Clear Enable Registers */
+    /* Interrupt Controller Clear Enable Registers */
     #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
     #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
 
@@ -731,11 +785,11 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
 
 
-    /* Interrrupt Controller Set Pend Registers */
+    /* Interrupt Controller Set Pend Registers */
     #define CY_INT_SET_PEND_REG         (* (reg8 *) CYREG_INTC_SET_PD0)
     #define CY_INT_SET_PEND_PTR         (  (reg8 *) CYREG_INTC_SET_PD0)
 
-    /* Interrrupt Controller Clear Pend Registers */
+    /* Interrupt Controller Clear Pend Registers */
     #define CY_INT_CLR_PEND_REG         (* (reg8 *) CYREG_INTC_CLR_PD0)
     #define CY_INT_CLR_PEND_PTR         (  (reg8 *) CYREG_INTC_CLR_PD0)
 
@@ -753,8 +807,8 @@ void CySetScPumps(uint8 enable) ;
 * Macro Name: CyAssert
 ********************************************************************************
 * Summary:
-*  Macro that evaluates the expression and if it is false (evaluates to 0) then
-*  the processor is halted.
+*  The macro that evaluates the expression and if it is false (evaluates to 0)
+*  then the processor is halted.
 *
 *  This macro is evaluated unless NDEBUG is defined.
 *
@@ -791,7 +845,7 @@ void CySetScPumps(uint8 enable) ;
 #define CY_RESET_GPIO1              (0x80u)
 
 
-/* Interrrupt Controller Configuration and Status Register */
+/* Interrupt Controller Configuration and Status Register */
 #if(CY_PSOC3)
     #define INTERRUPT_CSR               ((reg8 *) CYREG_INTC_CSR_EN)
     #define DISABLE_IRQ_SET             ((uint8)(0x01u << 1u))    /* INTC_CSR_EN */
@@ -844,6 +898,19 @@ void CySetScPumps(uint8 enable) ;
 #define CY_CACHE_CONTROL_FLUSH          (0x0004u)
 #define CY_LIB_RESET_CR2_RESET          (0x01u)
 
+#if(CY_PSOC5)
+    /* System tick API constants */
+    #define CY_SYS_SYST_CSR_ENABLE              ((uint32) (0x01u))
+    #define CY_SYS_SYST_CSR_ENABLE_INT          ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT    ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT     ((uint32) (16u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK      ((uint32) (1u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK       ((uint32) (0u))
+    #define CY_SYS_SYST_RVR_CNT_MASK            ((uint32) (0x00FFFFFFu))
+    #define CY_SYS_SYST_NUM_OF_CALLBACKS        ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
 
 /*******************************************************************************
 * Interrupt API constants
@@ -876,6 +943,20 @@ void CySetScPumps(uint8 enable) ;
 /* Mask to get valid range of system interrupt 0-15 */
 #define CY_INT_SYS_NUMBER_MASK          (0xFu)
 
+#if(CY_PSOC5)
+
+    /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+    #define CY_INT_NMI_IRQN                  ( 2u)      /* Non Maskable Interrupt      */
+    #define CY_INT_HARD_FAULT_IRQN           ( 3u)      /* Hard Fault Interrupt        */
+    #define CY_INT_MEM_MANAGE_IRQN           ( 4u)      /* Memory Management Interrupt */
+    #define CY_INT_BUS_FAULT_IRQN            ( 5u)      /* Bus Fault Interrupt         */
+    #define CY_INT_USAGE_FAULT_IRQN          ( 6u)      /* Usage Fault Interrupt       */
+    #define CY_INT_SVCALL_IRQN               (11u)      /* SV Call Interrupt           */
+    #define CY_INT_DEBUG_MONITOR_IRQN        (12u)      /* Debug Monitor Interrupt     */
+    #define CY_INT_PEND_SV_IRQN              (14u)      /* Pend SV Interrupt           */
+    #define CY_INT_SYSTICK_IRQN              (15u)      /* System Tick Interrupt       */
+
+#endif  /* (CY_PSOC5) */
 
 /*******************************************************************************
 * Interrupt Macros
@@ -1027,18 +1108,26 @@ void CySetScPumps(uint8 enable) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used.
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+
 #define CYGlobalIntEnable       CyGlobalIntEnable
 #define CYGlobalIntDisable      CyGlobalIntDisable
 
 #define cymemset(s,c,n)         memset((s),(c),(n))
 #define cymemcpy(d,s,n)         memcpy((d),(s),(n))
 
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
-*******************************************************************************/
 #define MFGCFG_X32_TR_PTR               (CY_CLK_XTAL32_TR_PTR)
 #define MFGCFG_X32_TR                   (CY_CLK_XTAL32_TR_REG)
 #define SLOWCLK_X32_TST_PTR             (CY_CLK_XTAL32_TST_PTR)
@@ -1123,10 +1212,6 @@ void CySetScPumps(uint8 enable) ;
 #define CY_VD_PRESISTENT_STATUS_PTR    (CY_VD_PERSISTENT_STATUS_PTR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20
-*******************************************************************************/
-
 #if(CY_PSOC5)
 
     #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
@@ -1153,9 +1238,7 @@ void CySetScPumps(uint8 enable) ;
 #endif  /* (CY_PSOC5) */
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
-*******************************************************************************/
+
 #define BUS_AMASK_CLEAR                 (0xF0u)
 #define BUS_DMASK_CLEAR                 (0x00u)
 #define CLKDIST_LD_LOAD_SET             (0x01u)
@@ -1190,9 +1273,6 @@ void CySetScPumps(uint8 enable) ;
 #define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
-*******************************************************************************/
 #define IMO_PM_ENABLE                   (0x10u)
 #define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
 #define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
index 8ea15809..949b6752 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the System Performance Component.
@@ -8,7 +8,7 @@
 *   application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -231,6 +231,11 @@ cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], u
 * Summary:
 *  Loads a row of data into the row latch of a Flash/EEPROM array.
 *
+*  The buffer pointer should point to the data that should be written to the
+*  flash row directly (no data in ECC/flash will be preserved). It is Flash API
+*  responsibility to prepare data: the preserved data are copied from flash into
+*  array with the modified data.
+*
 * Parameters:
 *  uint8 array:
 *   Id of the array.
@@ -286,6 +291,149 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+*  Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+*  The only data that are going to be changed should be passed. The function
+*  will handle unmodified data preservation based on DWR settings and input
+*  parameters.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 row:
+*   Flash row number to be loaded.
+*
+*  uint8* buffer:
+*   Data to be loaded to the row latch
+*
+*  uint8 size:
+*   The number of data bytes that the SPC expects to be written. Depends on the
+*   type of the array and, if the array is Flash, whether ECC is being enabled
+*   or not. There are following values: flash row latch size with ECC enabled,
+*   flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+    cystatus status = CYRET_STARTED;
+    uint16 i;
+
+    #if (CYDEV_ECC_ENABLE == 0)
+        uint32 offset;
+    #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+            * Data in ECC" DWR options are disabled, ECC section is available
+            * for user data.
+            *******************************************************************/
+            #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+                /*******************************************************************
+                * If size parameter equals size of the ECC row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the ECC section.
+                * In this case flash data must be preserved. The flash data copied
+                * from flash data section to the SPC data register.
+                *******************************************************************/
+                if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_FLS_BASE +
+                             ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+                             ((uint32)   row * CYDEV_FLS_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+            for(i = 0u; i < size; i++)
+            {
+                CY_SPC_CPU_DATA_REG = buffer[i];
+            }
+
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+            * ECC section can be used for storing device configuration data
+            * ("Store Configuration Data in ECC" DWR option is enabled) or for
+            * storing user data in the ECC section ("Store Configuration Data in
+            * ECC" DWR option is enabled). In both cases, the data in the ECC
+            * section must be preserved if flash data is written.
+            *******************************************************************/
+            #if (CYDEV_ECC_ENABLE == 0)
+
+
+                /*******************************************************************
+                * If size parameter equals size of the flash row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the flash data
+                * section. In this case, ECC section data must be preserved.
+                * The ECC section data copied from ECC section to the SPC data
+                * register.
+                *******************************************************************/
+                if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_ECC_BASE +
+                            ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+                            ((uint32) row   * CYDEV_ECC_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #else
+
+                if(0u != row)
+                {
+                    /* To remove unreferenced local variable warning */
+                }
+
+            #endif /* (CYDEV_ECC_ENABLE == 0) */
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySpcWriteRow
 ********************************************************************************
@@ -551,4 +699,38 @@ void CySpcUnlock(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+*  Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
 /* [] END OF FILE */
+
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
index 3757e132..22827133 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides definitions for the System Performance Component API.
@@ -8,7 +8,7 @@
 *  application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,10 +37,13 @@ uint8    CySpcReadData(uint8 buffer[], uint8 size);
 cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
 ;
 cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
 cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
 ;
 cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
 cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
 cystatus CySpcLock(void);
 void     CySpcUnlock(void);
 
@@ -69,7 +72,7 @@ void     CySpcUnlock(void);
 #define CY_SPC_STATUS_CODE_MASK             (0xFCu)
 #define CY_SPC_STATUS_CODE_SHIFT            (0x02u)
 
-/* Status codes for the SPC. */
+/* Status codes for SPC. */
 #define CY_SPC_STATUS_SUCCESS               (0x00u)   /* Operation Successful */
 #define CY_SPC_STATUS_INVALID_ARRAY_ID      (0x01u)   /* Invalid Array ID for given command */
 #define CY_SPC_STATUS_INVALID_2BYTEKEY      (0x02u)   /* Invalid 2-byte key */
@@ -137,7 +140,18 @@ void     CySpcUnlock(void);
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define FIRST_FLASH_ARRAYID         (CY_SPC_FIRST_FLASH_ARRAYID)
 #define LAST_FLASH_ARRAYID          (CY_SPC_LAST_FLASH_ARRAYID)
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c
index 2d991148..ba36af7a 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Debug_Timer.c
-* Version 2.50
+* Version 2.70
 *
 * Description:
 *  The Timer component consists of a 8, 16, 24 or 32-bit timer with
@@ -15,7 +15,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -129,10 +129,12 @@ void Debug_Timer_Init(void)
         #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
 
         #if (Debug_Timer_SoftwareTriggerMode)
-            if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
-            {
-                Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
-            }
+            #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+                if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
+                {
+                    Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
+                }
+            #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
         #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
 
         /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
@@ -148,12 +150,11 @@ void Debug_Timer_Init(void)
         #if (Debug_Timer_EnableTriggerMode)
             Debug_Timer_EnableTrigger();
         #endif /* Set Trigger enable bit for UDB implementation in the control register*/
-
-        #if (Debug_Timer_InterruptOnCaptureCount)
-             #if (!Debug_Timer_ControlRegRemoved)
-                Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
-            #endif /* Set interrupt count in control register if control register is not removed */
-        #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+		
+		
+        #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
+            Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
+        #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
 
         Debug_Timer_ClearFIFO();
     #endif /* Configure additional features of UDB implementation */
@@ -185,7 +186,7 @@ void Debug_Timer_Enable(void)
     #endif /* Set Enable bit for enabling Fixed function timer*/
 
     /* Remove assignment if control register is removed */
-    #if (!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
         Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
     #endif /* Remove assignment if control register is removed */
 }
@@ -246,7 +247,7 @@ void Debug_Timer_Start(void)
 void Debug_Timer_Stop(void) 
 {
     /* Disable Timer */
-    #if(!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
         Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
     #endif /* Remove assignment if control register is removed */
 
@@ -301,7 +302,11 @@ void Debug_Timer_SetInterruptMode(uint8 interruptMode)
 void Debug_Timer_SoftwareCapture(void) 
 {
     /* Generate a software capture by reading the counter register */
-    (void)Debug_Timer_COUNTER_LSB;
+    #if(Debug_Timer_UsingFixedFunction)
+        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+    #else
+        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+    #endif/* (Debug_Timer_UsingFixedFunction) */
     /* Capture Data is now in the FIFO */
 }
 
@@ -331,7 +336,7 @@ uint8   Debug_Timer_ReadStatusRegister(void)
 }
 
 
-#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
+#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
 
 
 /*******************************************************************************
@@ -350,7 +355,11 @@ uint8   Debug_Timer_ReadStatusRegister(void)
 *******************************************************************************/
 uint8 Debug_Timer_ReadControlRegister(void) 
 {
-    return ((uint8)Debug_Timer_CONTROL);
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
+        return ((uint8)Debug_Timer_CONTROL);
+    #else
+        return (0);
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
 
 
@@ -369,9 +378,14 @@ uint8 Debug_Timer_ReadControlRegister(void)
 *******************************************************************************/
 void Debug_Timer_WriteControlRegister(uint8 control) 
 {
-    Debug_Timer_CONTROL = control;
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) 
+        Debug_Timer_CONTROL = control;
+    #else
+        control = 0u;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
-#endif /* Remove API if control register is removed */
+
+#endif /* Remove API if control register is unused */
 
 
 /*******************************************************************************
@@ -463,8 +477,7 @@ uint16 Debug_Timer_ReadCapture(void)
 *  void
 *
 *******************************************************************************/
-void Debug_Timer_WriteCounter(uint16 counter) \
-                                   
+void Debug_Timer_WriteCounter(uint16 counter) 
 {
    #if(Debug_Timer_UsingFixedFunction)
         /* This functionality is removed until a FixedFunction HW update to
@@ -494,11 +507,14 @@ void Debug_Timer_WriteCounter(uint16 counter) \
 *******************************************************************************/
 uint16 Debug_Timer_ReadCounter(void) 
 {
-
     /* Force capture by reading Accumulator */
     /* Must first do a software capture to be able to read the counter */
     /* It is up to the user code to make sure there isn't already captured data in the FIFO */
-    (void)Debug_Timer_COUNTER_LSB;
+    #if(Debug_Timer_UsingFixedFunction)
+        (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+    #else
+        (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+    #endif/* (Debug_Timer_UsingFixedFunction) */
 
     /* Read the data from the FIFO (or capture register for Fixed Function)*/
     #if(Debug_Timer_UsingFixedFunction)
@@ -511,6 +527,7 @@ uint16 Debug_Timer_ReadCounter(void)
 
 #if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
 
+    
 /*******************************************************************************
  * The functions below this point are only available using the UDB
  * implementation.  If a feature is selected, then the API is enabled.
@@ -552,11 +569,13 @@ void Debug_Timer_SetCaptureMode(uint8 captureMode)
     captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
     captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
 
-    /* Clear the Current Setting */
-    Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
 
-    /* Write The New Setting */
-    Debug_Timer_CONTROL |= captureMode;
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= captureMode;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
 #endif /* Remove API if Capture Mode is not Software Controlled */
 
@@ -588,12 +607,14 @@ void Debug_Timer_SetTriggerMode(uint8 triggerMode)
     /* This must only set to two bits of the control register associated */
     triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
 
-    /* Clear the Current Setting */
-    Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
-
-    /* Write The New Setting */
-    Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
+    
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
 
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+    #endif /* Remove code section if control register is not used */
 }
 #endif /* Remove API if Trigger Mode is not Software Controlled */
 
@@ -616,7 +637,7 @@ void Debug_Timer_SetTriggerMode(uint8 triggerMode)
 *******************************************************************************/
 void Debug_Timer_EnableTrigger(void) 
 {
-    #if (!Debug_Timer_ControlRegRemoved)   /* Remove assignment if control register is removed */
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)   /* Remove assignment if control register is removed */
         Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
     #endif /* Remove code section if control register is not used */
 }
@@ -638,15 +659,13 @@ void Debug_Timer_EnableTrigger(void)
 *******************************************************************************/
 void Debug_Timer_DisableTrigger(void) 
 {
-    #if (!Debug_Timer_ControlRegRemoved)   /* Remove assignment if control register is removed */
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED )   /* Remove assignment if control register is removed */
         Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
     #endif /* Remove code section if control register is not used */
 }
 #endif /* Remove API is Trigger Mode is set to None */
 
-
 #if(Debug_Timer_InterruptOnCaptureCount)
-#if (!Debug_Timer_ControlRegRemoved)   /* Remove API if control register is removed */
 
 
 /*******************************************************************************
@@ -671,12 +690,13 @@ void Debug_Timer_SetInterruptCount(uint8 interruptCount)
     /* This must only set to two bits of the control register associated */
     interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
 
-    /* Clear the Current Setting */
-    Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
-    /* Write The New Setting */
-    Debug_Timer_CONTROL |= interruptCount;
+    #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+        /* Clear the Current Setting */
+        Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
+        /* Write The New Setting */
+        Debug_Timer_CONTROL |= interruptCount;
+    #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 }
-#endif /* Remove API if control register is removed */
 #endif /* Debug_Timer_InterruptOnCaptureCount */
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h
index 2170009e..2a8742cb 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Debug_Timer.h
-* Version 2.50
+* Version 2.70
 *
 *  Description:
 *     Contains the function prototypes and constants available to the timer
@@ -10,14 +10,14 @@
 *     None
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
 ********************************************************************************/
 
-#if !defined(CY_Timer_v2_30_Debug_Timer_H)
-#define CY_Timer_v2_30_Debug_Timer_H
+#if !defined(CY_Timer_v2_60_Debug_Timer_H)
+#define CY_Timer_v2_60_Debug_Timer_H
 
 #include "cytypes.h"
 #include "cyfitter.h"
@@ -28,7 +28,7 @@ extern uint8 Debug_Timer_initVar;
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component Timer_v2_50 requires cy_boot v3.0 or later
+    #error Component Timer_v2_70 requires cy_boot v3.0 or later
 #endif /* (CY_ PSOC5LP) */
 
 
@@ -47,6 +47,14 @@ extern uint8 Debug_Timer_initVar;
 #define Debug_Timer_RunModeUsed                0u
 #define Debug_Timer_ControlRegRemoved          0u
 
+#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
+#elif  (Debug_Timer_UsingFixedFunction)
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (0u)
+#else 
+    #define Debug_Timer_UDB_CONTROL_REG_REMOVED            (1u)
+#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
+
 
 /***************************************
 *       Type defines
@@ -60,27 +68,18 @@ typedef struct
 {
     uint8 TimerEnableState;
     #if(!Debug_Timer_UsingFixedFunction)
-        #if (CY_UDB_V0)
-            uint16 TimerUdb;                 /* Timer internal counter value */
-            uint16 TimerPeriod;              /* Timer Period value       */
-            uint8 InterruptMaskValue;       /* Timer Compare Value */
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                uint8 TimerCaptureCounter;  /* Timer Capture Counter Value */
-            #endif /* variable declaration for backing up Capture Counter value*/
-        #endif /* variables for non retention registers in CY_UDB_V0 */
-
-        #if (CY_UDB_V1)
-            uint16 TimerUdb;
-            uint8 InterruptMaskValue;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                uint8 TimerCaptureCounter;
-            #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
-        #endif /* (CY_UDB_V1) */
-
-        #if (!Debug_Timer_ControlRegRemoved)
+
+        uint16 TimerUdb;
+        uint8 InterruptMaskValue;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            uint8 TimerCaptureCounter;
+        #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+
+        #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
             uint8 TimerControlRegister;
         #endif /* variable declaration for backing up enable state of the Timer */
     #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+
 }Debug_Timer_backupStruct;
 
 
@@ -96,22 +95,18 @@ uint8   Debug_Timer_ReadStatusRegister(void) ;
 /* Deprecated function. Do not use this in future. Retained for backward compatibility */
 #define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
 
-#if(!Debug_Timer_ControlRegRemoved)
+#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
     uint8   Debug_Timer_ReadControlRegister(void) ;
-    void    Debug_Timer_WriteControlRegister(uint8 control) \
-        ;
-#endif /* (!Debug_Timer_ControlRegRemoved) */
+    void    Debug_Timer_WriteControlRegister(uint8 control) ;
+#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
 
 uint16  Debug_Timer_ReadPeriod(void) ;
-void    Debug_Timer_WritePeriod(uint16 period) \
-    ;
+void    Debug_Timer_WritePeriod(uint16 period) ;
 uint16  Debug_Timer_ReadCounter(void) ;
-void    Debug_Timer_WriteCounter(uint16 counter) \
-    ;
+void    Debug_Timer_WriteCounter(uint16 counter) ;
 uint16  Debug_Timer_ReadCapture(void) ;
 void    Debug_Timer_SoftwareCapture(void) ;
 
-
 #if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
     #if (Debug_Timer_SoftwareCaptureMode)
         void    Debug_Timer_SetCaptureMode(uint8 captureMode) ;
@@ -120,21 +115,19 @@ void    Debug_Timer_SoftwareCapture(void) ;
     #if (Debug_Timer_SoftwareTriggerMode)
         void    Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
     #endif /* (Debug_Timer_SoftwareTriggerMode) */
+
     #if (Debug_Timer_EnableTriggerMode)
         void    Debug_Timer_EnableTrigger(void) ;
         void    Debug_Timer_DisableTrigger(void) ;
     #endif /* (Debug_Timer_EnableTriggerMode) */
 
+
     #if(Debug_Timer_InterruptOnCaptureCount)
-        #if(!Debug_Timer_ControlRegRemoved)
-            void    Debug_Timer_SetInterruptCount(uint8 interruptCount) \
-                ;
-        #endif /* (!Debug_Timer_ControlRegRemoved) */
+        void    Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
     #endif /* (Debug_Timer_InterruptOnCaptureCount) */
 
     #if (Debug_Timer_UsingHWCaptureCounter)
-        void    Debug_Timer_SetCaptureCount(uint8 captureCount) \
-            ;
+        void    Debug_Timer_SetCaptureCount(uint8 captureCount) ;
         uint8   Debug_Timer_ReadCaptureCount(void) ;
     #endif /* (Debug_Timer_UsingHWCaptureCounter) */
 
@@ -256,8 +249,8 @@ void Debug_Timer_Wakeup(void)        ;
     #if (CY_PSOC5A)
         /* Use CFG1 Mode bits to set run mode */
         /* As defined by Verilog Implementation */
-        #define Debug_Timer_CTRL_MODE_SHIFT                     0x01u
-        #define Debug_Timer_CTRL_MODE_MASK                     ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
+        #define Debug_Timer_CTRL_MODE_SHIFT                 0x01u
+        #define Debug_Timer_CTRL_MODE_MASK                 ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
     #endif /* (CY_PSOC5A) */
     #if (CY_PSOC3 || CY_PSOC5LP)
         /* Control3 Register Bit Locations */
@@ -367,6 +360,8 @@ void Debug_Timer_Wakeup(void)        ;
         #endif /* CY_PSOC3 || CY_PSOC5 */ 
     #endif
 
+    #define Debug_Timer_COUNTER_LSB_PTR_8BIT       ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+    
     #if (Debug_Timer_UsingHWCaptureCounter)
         #define Debug_Timer_CAP_COUNT              (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
         #define Debug_Timer_CAP_COUNT_PTR          ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c
index 97f2d96d..c9c443b9 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: Debug_Timer_PM.c
-* Version 2.50
+* Version 2.70
 *
 *  Description:
 *     This file provides the power management source code to API for the
@@ -10,13 +10,14 @@
 *     None
 *
 *******************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
 ********************************************************************************/
 
 #include "Debug_Timer.h"
+
 static Debug_Timer_backupStruct Debug_Timer_backup;
 
 
@@ -42,25 +43,13 @@ static Debug_Timer_backupStruct Debug_Timer_backup;
 void Debug_Timer_SaveConfig(void) 
 {
     #if (!Debug_Timer_UsingFixedFunction)
-        /* Backup the UDB non-rentention registers for CY_UDB_V0 */
-        #if (CY_UDB_V0)
-            Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
-            Debug_Timer_backup.TimerPeriod = Debug_Timer_ReadPeriod();
-            Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
-            #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
-        #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
-
-        #if (CY_UDB_V1)
-            Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
-            Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
-            #endif /* Back Up capture counter register  */
-        #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+        Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+        Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
+        #endif /* Back Up capture counter register  */
 
-        #if(!Debug_Timer_ControlRegRemoved)
+        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
             Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
         #endif /* Backup the enable state of the Timer component */
     #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
@@ -88,35 +77,14 @@ void Debug_Timer_SaveConfig(void)
 void Debug_Timer_RestoreConfig(void) 
 {   
     #if (!Debug_Timer_UsingFixedFunction)
-        /* Restore the UDB non-rentention registers for CY_UDB_V0 */
-        #if (CY_UDB_V0)
-            /* Interrupt State Backup for Critical Region*/
-            uint8 Debug_Timer_interruptState;
-
-            Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
-            Debug_Timer_WritePeriod(Debug_Timer_backup.TimerPeriod);
-            /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
-            /* Enter Critical Region*/
-            Debug_Timer_interruptState = CyEnterCriticalSection();
-            /* Use the interrupt output of the status register for IRQ output */
-            Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
-            /* Exit Critical Region*/
-            CyExitCriticalSection(Debug_Timer_interruptState);
-            Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
-            #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
-        #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
 
-        #if (CY_UDB_V1)
-            Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
-            Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
-            #if (Debug_Timer_UsingHWCaptureCounter)
-                Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
-            #endif /* Restore Capture counter register*/
-        #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+        Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+        Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+        #if (Debug_Timer_UsingHWCaptureCounter)
+            Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
+        #endif /* Restore Capture counter register*/
 
-        #if(!Debug_Timer_ControlRegRemoved)
+        #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
             Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
         #endif /* Restore the enable state of the Timer component */
     #endif /* Restore non retention registers in the UDB implementation only */
@@ -143,7 +111,7 @@ void Debug_Timer_RestoreConfig(void)
 *******************************************************************************/
 void Debug_Timer_Sleep(void) 
 {
-    #if(!Debug_Timer_ControlRegRemoved)
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
         /* Save Counter's enable state */
         if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
         {
@@ -182,7 +150,7 @@ void Debug_Timer_Sleep(void)
 void Debug_Timer_Wakeup(void) 
 {
     Debug_Timer_RestoreConfig();
-    #if(!Debug_Timer_ControlRegRemoved)
+    #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
         if(Debug_Timer_backup.TimerEnableState == 1u)
         {     /* Enable Timer's operation */
                 Debug_Timer_Enable();
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c
index 2c94324f..da01c040 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: EXTLED.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void EXTLED_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  EXTLED_DM_STRONG     Strong Drive 
+*  EXTLED_DM_OD_HI      Open Drain, Drives High 
+*  EXTLED_DM_OD_LO      Open Drain, Drives Low 
+*  EXTLED_DM_RES_UP     Resistive Pull Up 
+*  EXTLED_DM_RES_DWN    Resistive Pull Down 
+*  EXTLED_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  EXTLED_DM_DIG_HIZ    High Impedance Digital 
+*  EXTLED_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h
index 1ac27a69..78d2db01 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: EXTLED.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h
index cbd80b57..e46ccb66 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: EXTLED.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define EXTLED_0		EXTLED__0__PC
+#define EXTLED_0		(EXTLED__0__PC)
 
 #endif /* End Pins EXTLED_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c
index abb76427..af5ba6e1 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED1.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void LED1_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  LED1_DM_STRONG     Strong Drive 
+*  LED1_DM_OD_HI      Open Drain, Drives High 
+*  LED1_DM_OD_LO      Open Drain, Drives Low 
+*  LED1_DM_RES_UP     Resistive Pull Up 
+*  LED1_DM_RES_DWN    Resistive Pull Down 
+*  LED1_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  LED1_DM_DIG_HIZ    High Impedance Digital 
+*  LED1_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h
index 740e999d..877fd813 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED1.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h
index 02aa04d4..e3c4c769 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED1.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define LED1_0		LED1__0__PC
+#define LED1_0		(LED1__0__PC)
 
 #endif /* End Pins LED1_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
index 16a02412..6e8f8085 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_CLK.c
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
index 5c915030..e4c3e105 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_CLK.h
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
index 97e00b20..702808b3 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_In_DBx.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,23 +25,23 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_In_DBx_0		SCSI_In_DBx__0__PC
-#define SCSI_In_DBx_1		SCSI_In_DBx__1__PC
-#define SCSI_In_DBx_2		SCSI_In_DBx__2__PC
-#define SCSI_In_DBx_3		SCSI_In_DBx__3__PC
-#define SCSI_In_DBx_4		SCSI_In_DBx__4__PC
-#define SCSI_In_DBx_5		SCSI_In_DBx__5__PC
-#define SCSI_In_DBx_6		SCSI_In_DBx__6__PC
-#define SCSI_In_DBx_7		SCSI_In_DBx__7__PC
-
-#define SCSI_In_DBx_DB0		SCSI_In_DBx__DB0__PC
-#define SCSI_In_DBx_DB1		SCSI_In_DBx__DB1__PC
-#define SCSI_In_DBx_DB2		SCSI_In_DBx__DB2__PC
-#define SCSI_In_DBx_DB3		SCSI_In_DBx__DB3__PC
-#define SCSI_In_DBx_DB4		SCSI_In_DBx__DB4__PC
-#define SCSI_In_DBx_DB5		SCSI_In_DBx__DB5__PC
-#define SCSI_In_DBx_DB6		SCSI_In_DBx__DB6__PC
-#define SCSI_In_DBx_DB7		SCSI_In_DBx__DB7__PC
+#define SCSI_In_DBx_0		(SCSI_In_DBx__0__PC)
+#define SCSI_In_DBx_1		(SCSI_In_DBx__1__PC)
+#define SCSI_In_DBx_2		(SCSI_In_DBx__2__PC)
+#define SCSI_In_DBx_3		(SCSI_In_DBx__3__PC)
+#define SCSI_In_DBx_4		(SCSI_In_DBx__4__PC)
+#define SCSI_In_DBx_5		(SCSI_In_DBx__5__PC)
+#define SCSI_In_DBx_6		(SCSI_In_DBx__6__PC)
+#define SCSI_In_DBx_7		(SCSI_In_DBx__7__PC)
+
+#define SCSI_In_DBx_DB0		(SCSI_In_DBx__DB0__PC)
+#define SCSI_In_DBx_DB1		(SCSI_In_DBx__DB1__PC)
+#define SCSI_In_DBx_DB2		(SCSI_In_DBx__DB2__PC)
+#define SCSI_In_DBx_DB3		(SCSI_In_DBx__DB3__PC)
+#define SCSI_In_DBx_DB4		(SCSI_In_DBx__DB4__PC)
+#define SCSI_In_DBx_DB5		(SCSI_In_DBx__DB5__PC)
+#define SCSI_In_DBx_DB6		(SCSI_In_DBx__DB6__PC)
+#define SCSI_In_DBx_DB7		(SCSI_In_DBx__DB7__PC)
 
 #endif /* End Pins SCSI_In_DBx_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
index 66ac80a6..ef4e517c 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_In.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,17 +25,17 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_In_0		SCSI_In__0__PC
-#define SCSI_In_1		SCSI_In__1__PC
-#define SCSI_In_2		SCSI_In__2__PC
-#define SCSI_In_3		SCSI_In__3__PC
-#define SCSI_In_4		SCSI_In__4__PC
-
-#define SCSI_In_DBP		SCSI_In__DBP__PC
-#define SCSI_In_MSG		SCSI_In__MSG__PC
-#define SCSI_In_CD		SCSI_In__CD__PC
-#define SCSI_In_REQ		SCSI_In__REQ__PC
-#define SCSI_In_IO		SCSI_In__IO__PC
+#define SCSI_In_0		(SCSI_In__0__PC)
+#define SCSI_In_1		(SCSI_In__1__PC)
+#define SCSI_In_2		(SCSI_In__2__PC)
+#define SCSI_In_3		(SCSI_In__3__PC)
+#define SCSI_In_4		(SCSI_In__4__PC)
+
+#define SCSI_In_DBP		(SCSI_In__DBP__PC)
+#define SCSI_In_MSG		(SCSI_In__MSG__PC)
+#define SCSI_In_CD		(SCSI_In__CD__PC)
+#define SCSI_In_REQ		(SCSI_In__REQ__PC)
+#define SCSI_In_IO		(SCSI_In__IO__PC)
 
 #endif /* End Pins SCSI_In_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
index ffd841d4..2bf11476 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Noise.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,17 +25,17 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Noise_0		SCSI_Noise__0__PC
-#define SCSI_Noise_1		SCSI_Noise__1__PC
-#define SCSI_Noise_2		SCSI_Noise__2__PC
-#define SCSI_Noise_3		SCSI_Noise__3__PC
-#define SCSI_Noise_4		SCSI_Noise__4__PC
-
-#define SCSI_Noise_ATN		SCSI_Noise__ATN__PC
-#define SCSI_Noise_BSY		SCSI_Noise__BSY__PC
-#define SCSI_Noise_SEL		SCSI_Noise__SEL__PC
-#define SCSI_Noise_RST		SCSI_Noise__RST__PC
-#define SCSI_Noise_ACK		SCSI_Noise__ACK__PC
+#define SCSI_Noise_0		(SCSI_Noise__0__PC)
+#define SCSI_Noise_1		(SCSI_Noise__1__PC)
+#define SCSI_Noise_2		(SCSI_Noise__2__PC)
+#define SCSI_Noise_3		(SCSI_Noise__3__PC)
+#define SCSI_Noise_4		(SCSI_Noise__4__PC)
+
+#define SCSI_Noise_ATN		(SCSI_Noise__ATN__PC)
+#define SCSI_Noise_BSY		(SCSI_Noise__BSY__PC)
+#define SCSI_Noise_SEL		(SCSI_Noise__SEL__PC)
+#define SCSI_Noise_RST		(SCSI_Noise__RST__PC)
+#define SCSI_Noise_ACK		(SCSI_Noise__ACK__PC)
 
 #endif /* End Pins SCSI_Noise_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
index cab58f9f..6fcc5f6a 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_DBx.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,23 +25,23 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_DBx_0		SCSI_Out_DBx__0__PC
-#define SCSI_Out_DBx_1		SCSI_Out_DBx__1__PC
-#define SCSI_Out_DBx_2		SCSI_Out_DBx__2__PC
-#define SCSI_Out_DBx_3		SCSI_Out_DBx__3__PC
-#define SCSI_Out_DBx_4		SCSI_Out_DBx__4__PC
-#define SCSI_Out_DBx_5		SCSI_Out_DBx__5__PC
-#define SCSI_Out_DBx_6		SCSI_Out_DBx__6__PC
-#define SCSI_Out_DBx_7		SCSI_Out_DBx__7__PC
-
-#define SCSI_Out_DBx_DB0		SCSI_Out_DBx__DB0__PC
-#define SCSI_Out_DBx_DB1		SCSI_Out_DBx__DB1__PC
-#define SCSI_Out_DBx_DB2		SCSI_Out_DBx__DB2__PC
-#define SCSI_Out_DBx_DB3		SCSI_Out_DBx__DB3__PC
-#define SCSI_Out_DBx_DB4		SCSI_Out_DBx__DB4__PC
-#define SCSI_Out_DBx_DB5		SCSI_Out_DBx__DB5__PC
-#define SCSI_Out_DBx_DB6		SCSI_Out_DBx__DB6__PC
-#define SCSI_Out_DBx_DB7		SCSI_Out_DBx__DB7__PC
+#define SCSI_Out_DBx_0		(SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1		(SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2		(SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3		(SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4		(SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5		(SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6		(SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7		(SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0		(SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1		(SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2		(SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3		(SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4		(SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5		(SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6		(SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7		(SCSI_Out_DBx__DB7__PC)
 
 #endif /* End Pins SCSI_Out_DBx_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
index 56439346..9c83cca7 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,27 +25,27 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_0		SCSI_Out__0__PC
-#define SCSI_Out_1		SCSI_Out__1__PC
-#define SCSI_Out_2		SCSI_Out__2__PC
-#define SCSI_Out_3		SCSI_Out__3__PC
-#define SCSI_Out_4		SCSI_Out__4__PC
-#define SCSI_Out_5		SCSI_Out__5__PC
-#define SCSI_Out_6		SCSI_Out__6__PC
-#define SCSI_Out_7		SCSI_Out__7__PC
-#define SCSI_Out_8		SCSI_Out__8__PC
-#define SCSI_Out_9		SCSI_Out__9__PC
-
-#define SCSI_Out_DBP_raw		SCSI_Out__DBP_raw__PC
-#define SCSI_Out_ATN		SCSI_Out__ATN__PC
-#define SCSI_Out_BSY		SCSI_Out__BSY__PC
-#define SCSI_Out_ACK		SCSI_Out__ACK__PC
-#define SCSI_Out_RST		SCSI_Out__RST__PC
-#define SCSI_Out_MSG_raw		SCSI_Out__MSG_raw__PC
-#define SCSI_Out_SEL		SCSI_Out__SEL__PC
-#define SCSI_Out_CD_raw		SCSI_Out__CD_raw__PC
-#define SCSI_Out_REQ		SCSI_Out__REQ__PC
-#define SCSI_Out_IO_raw		SCSI_Out__IO_raw__PC
+#define SCSI_Out_0		(SCSI_Out__0__PC)
+#define SCSI_Out_1		(SCSI_Out__1__PC)
+#define SCSI_Out_2		(SCSI_Out__2__PC)
+#define SCSI_Out_3		(SCSI_Out__3__PC)
+#define SCSI_Out_4		(SCSI_Out__4__PC)
+#define SCSI_Out_5		(SCSI_Out__5__PC)
+#define SCSI_Out_6		(SCSI_Out__6__PC)
+#define SCSI_Out_7		(SCSI_Out__7__PC)
+#define SCSI_Out_8		(SCSI_Out__8__PC)
+#define SCSI_Out_9		(SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw		(SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN		(SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY		(SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK		(SCSI_Out__ACK__PC)
+#define SCSI_Out_RST		(SCSI_Out__RST__PC)
+#define SCSI_Out_MSG_raw		(SCSI_Out__MSG_raw__PC)
+#define SCSI_Out_SEL		(SCSI_Out__SEL__PC)
+#define SCSI_Out_CD_raw		(SCSI_Out__CD_raw__PC)
+#define SCSI_Out_REQ		(SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw		(SCSI_Out__IO_raw__PC)
 
 #endif /* End Pins SCSI_Out_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c
index 27d45e34..ce96101c 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CD.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_CD_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_CD_DM_STRONG     Strong Drive 
+*  SD_CD_DM_OD_HI      Open Drain, Drives High 
+*  SD_CD_DM_OD_LO      Open Drain, Drives Low 
+*  SD_CD_DM_RES_UP     Resistive Pull Up 
+*  SD_CD_DM_RES_DWN    Resistive Pull Down 
+*  SD_CD_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_CD_DM_DIG_HIZ    High Impedance Digital 
+*  SD_CD_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h
index a6b71774..923fbb02 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CD.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h
index 6d4a2cd0..0f9c440e 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CD.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_CD_0		SD_CD__0__PC
+#define SD_CD_0		(SD_CD__0__PC)
 
 #endif /* End Pins SD_CD_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c
index e6fe1f41..fe425b2c 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CS.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_CS_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_CS_DM_STRONG     Strong Drive 
+*  SD_CS_DM_OD_HI      Open Drain, Drives High 
+*  SD_CS_DM_OD_LO      Open Drain, Drives Low 
+*  SD_CS_DM_RES_UP     Resistive Pull Up 
+*  SD_CS_DM_RES_DWN    Resistive Pull Down 
+*  SD_CS_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_CS_DM_DIG_HIZ    High Impedance Digital 
+*  SD_CS_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h
index c2d5c0de..742cd79f 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CS.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h
index 32d2dca5..35f21ec2 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_CS.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_CS_0		SD_CS__0__PC
+#define SD_CS_0		(SD_CS__0__PC)
 
 #endif /* End Pins SD_CS_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
index f90dc2cc..2e919907 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Data_Clk.c
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
index ac373a31..dc40003e 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_Data_Clk.h
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c
index 536c08e5..0d2bc9dc 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MISO.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_MISO_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_MISO_DM_STRONG     Strong Drive 
+*  SD_MISO_DM_OD_HI      Open Drain, Drives High 
+*  SD_MISO_DM_OD_LO      Open Drain, Drives Low 
+*  SD_MISO_DM_RES_UP     Resistive Pull Up 
+*  SD_MISO_DM_RES_DWN    Resistive Pull Down 
+*  SD_MISO_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_MISO_DM_DIG_HIZ    High Impedance Digital 
+*  SD_MISO_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h
index 5583fbdb..cf6404e8 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MISO.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h
index b392bb88..3273effe 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MISO.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_MISO_0		SD_MISO__0__PC
+#define SD_MISO_0		(SD_MISO__0__PC)
 
 #endif /* End Pins SD_MISO_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c
index 2658af80..268ee96e 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MOSI.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_MOSI_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_MOSI_DM_STRONG     Strong Drive 
+*  SD_MOSI_DM_OD_HI      Open Drain, Drives High 
+*  SD_MOSI_DM_OD_LO      Open Drain, Drives Low 
+*  SD_MOSI_DM_RES_UP     Resistive Pull Up 
+*  SD_MOSI_DM_RES_DWN    Resistive Pull Down 
+*  SD_MOSI_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_MOSI_DM_DIG_HIZ    High Impedance Digital 
+*  SD_MOSI_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h
index 73f55e08..73c3b028 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MOSI.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h
index c97abbd8..e0175e4d 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_MOSI.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_MOSI_0		SD_MOSI__0__PC
+#define SD_MOSI_0		(SD_MOSI__0__PC)
 
 #endif /* End Pins SD_MOSI_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c
index 1ca28998..9c457668 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_SCK.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_SCK_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_SCK_DM_STRONG     Strong Drive 
+*  SD_SCK_DM_OD_HI      Open Drain, Drives High 
+*  SD_SCK_DM_OD_LO      Open Drain, Drives Low 
+*  SD_SCK_DM_RES_UP     Resistive Pull Up 
+*  SD_SCK_DM_RES_DWN    Resistive Pull Down 
+*  SD_SCK_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_SCK_DM_DIG_HIZ    High Impedance Digital 
+*  SD_SCK_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h
index 2fb0b372..4477bfc2 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_SCK.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h
index 026596c5..bb464158 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_SCK.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_SCK_0		SD_SCK__0__PC
+#define SD_SCK_0		(SD_SCK__0__PC)
 
 #endif /* End Pins SD_SCK_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c
index 0750c413..ef789c5a 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  API for USBFS Component.
@@ -11,7 +11,7 @@
 *  registers are indexed by variations of epNumber - 1.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -23,28 +23,33 @@
 #include "USBFS_hid.h"
 #if(USBFS_DMA1_REMOVE == 0u)
     #include "USBFS_ep1_dma.h"
-#endif   /* End USBFS_DMA1_REMOVE */
+#endif   /*  USBFS_DMA1_REMOVE */
 #if(USBFS_DMA2_REMOVE == 0u)
     #include "USBFS_ep2_dma.h"
-#endif   /* End USBFS_DMA2_REMOVE */
+#endif   /*  USBFS_DMA2_REMOVE */
 #if(USBFS_DMA3_REMOVE == 0u)
     #include "USBFS_ep3_dma.h"
-#endif   /* End USBFS_DMA3_REMOVE */
+#endif   /*  USBFS_DMA3_REMOVE */
 #if(USBFS_DMA4_REMOVE == 0u)
     #include "USBFS_ep4_dma.h"
-#endif   /* End USBFS_DMA4_REMOVE */
+#endif   /*  USBFS_DMA4_REMOVE */
 #if(USBFS_DMA5_REMOVE == 0u)
     #include "USBFS_ep5_dma.h"
-#endif   /* End USBFS_DMA5_REMOVE */
+#endif   /*  USBFS_DMA5_REMOVE */
 #if(USBFS_DMA6_REMOVE == 0u)
     #include "USBFS_ep6_dma.h"
-#endif   /* End USBFS_DMA6_REMOVE */
+#endif   /*  USBFS_DMA6_REMOVE */
 #if(USBFS_DMA7_REMOVE == 0u)
     #include "USBFS_ep7_dma.h"
-#endif   /* End USBFS_DMA7_REMOVE */
+#endif   /*  USBFS_DMA7_REMOVE */
 #if(USBFS_DMA8_REMOVE == 0u)
     #include "USBFS_ep8_dma.h"
-#endif   /* End USBFS_DMA8_REMOVE */
+#endif   /*  USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP_DMA_Done_isr.h"
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /***************************************
@@ -55,7 +60,25 @@ uint8 USBFS_initVar = 0u;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     uint8 USBFS_DmaChan[USBFS_MAX_EP];
     uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+    uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+    {   0u,
+        USBFS_ep1_TD_TERMOUT_EN,
+        USBFS_ep2_TD_TERMOUT_EN,
+        USBFS_ep3_TD_TERMOUT_EN,
+        USBFS_ep4_TD_TERMOUT_EN,
+        USBFS_ep5_TD_TERMOUT_EN,
+        USBFS_ep6_TD_TERMOUT_EN,
+        USBFS_ep7_TD_TERMOUT_EN,
+        USBFS_ep8_TD_TERMOUT_EN
+    };
+    volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -137,7 +160,7 @@ void USBFS_Init(void)
     uint8 enableInterrupts;
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         uint16 i;
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     enableInterrupts = CyEnterCriticalSection();
 
@@ -190,8 +213,11 @@ void USBFS_Init(void)
         for (i = 0u; i < USBFS_MAX_EP; i++)
         {
             USBFS_DmaTd[i] = DMA_INVALID_TD;
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
         }
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     CyExitCriticalSection(enableInterrupts);
 
@@ -204,7 +230,7 @@ void USBFS_Init(void)
     #if(USBFS_SOF_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_SOF_VECT_NUM,   &USBFS_SOF_ISR);
         CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
-    #endif   /* End USBFS_SOF_ISR_REMOVE */
+    #endif   /*  USBFS_SOF_ISR_REMOVE */
 
     /* Set the Control Endpoint Interrupt. */
     (void) CyIntSetVector(USBFS_EP_0_VECT_NUM,   &USBFS_EP_0_ISR);
@@ -214,55 +240,55 @@ void USBFS_Init(void)
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_1_VECT_NUM,   &USBFS_EP_1_ISR);
         CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
 
     /* Set the Data Endpoint 2 Interrupt. */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_2_VECT_NUM,   &USBFS_EP_2_ISR);
         CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
 
     /* Set the Data Endpoint 3 Interrupt. */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_3_VECT_NUM,   &USBFS_EP_3_ISR);
         CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
 
     /* Set the Data Endpoint 4 Interrupt. */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_4_VECT_NUM,   &USBFS_EP_4_ISR);
         CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
 
     /* Set the Data Endpoint 5 Interrupt. */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_5_VECT_NUM,   &USBFS_EP_5_ISR);
         CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
 
     /* Set the Data Endpoint 6 Interrupt. */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_6_VECT_NUM,   &USBFS_EP_6_ISR);
         CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
 
      /* Set the Data Endpoint 7 Interrupt. */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_7_VECT_NUM,   &USBFS_EP_7_ISR);
         CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
 
     /* Set the Data Endpoint 8 Interrupt. */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_8_VECT_NUM,   &USBFS_EP_8_ISR);
         CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* Set the ARB Interrupt. */
         (void) CyIntSetVector(USBFS_ARB_VECT_NUM,   &USBFS_ARB_ISR);
         CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
 }
 
@@ -339,45 +365,50 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
     CyIntEnable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* usb arb interrupt enable */
         USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
         CyIntEnable(USBFS_ARB_VECT_NUM);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Arbiter configuration for DMA transfers */
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /*Set cfg cmplt this rises DMA request when the full configuration is done */
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+                /* Init interrupt which handles verification of the successful DMA transaction */
+                USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+                USBFS_EP17_DMA_Done_SR_InterruptEnable();
+                USBFS_EP8_DMA_Done_SR_InterruptEnable();
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     USBFS_transferState = USBFS_TRANS_STATE_IDLE;
 
@@ -395,7 +426,7 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
             #else
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
-            #endif /* End USBFS_VDDD_MV < USBFS_3500MV */
+            #endif /*  USBFS_VDDD_MV < USBFS_3500MV */
             break;
     }
 
@@ -535,7 +566,7 @@ void USBFS_Stop(void)
 
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Disable the SIE */
     USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
@@ -551,28 +582,28 @@ void USBFS_Stop(void)
     CyIntDisable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     /* Clear all of the component data */
     USBFS_configuration = 0u;
@@ -768,7 +799,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
     *  No.
     *
     *******************************************************************************/
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                                     
     {
         uint16 src;
@@ -788,56 +819,56 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 src = HI16(CYDEV_PERIPH_BASE);
                 dst = HI16(pData);
             }
-        #endif  /* End C51 */
+        #endif  /*  C51 */
         switch(epNumber)
         {
             case USBFS_EP1:
                 #if(USBFS_DMA1_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA1_REMOVE */
+                #endif   /*  USBFS_DMA1_REMOVE */
                 break;
             case USBFS_EP2:
                 #if(USBFS_DMA2_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA2_REMOVE */
+                #endif   /*  USBFS_DMA2_REMOVE */
                 break;
             case USBFS_EP3:
                 #if(USBFS_DMA3_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA3_REMOVE */
+                #endif   /*  USBFS_DMA3_REMOVE */
                 break;
             case USBFS_EP4:
                 #if(USBFS_DMA4_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA4_REMOVE */
+                #endif   /*  USBFS_DMA4_REMOVE */
                 break;
             case USBFS_EP5:
                 #if(USBFS_DMA5_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA5_REMOVE */
+                #endif   /*  USBFS_DMA5_REMOVE */
                 break;
             case USBFS_EP6:
                 #if(USBFS_DMA6_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA6_REMOVE */
+                #endif   /*  USBFS_DMA6_REMOVE */
                 break;
             case USBFS_EP7:
                 #if(USBFS_DMA7_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA7_REMOVE */
+                #endif   /*  USBFS_DMA7_REMOVE */
                 break;
             case USBFS_EP8:
                 #if(USBFS_DMA8_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA8_REMOVE */
+                #endif   /*  USBFS_DMA8_REMOVE */
                 break;
             default:
                 /* Do not support EP0 DMA transfers */
@@ -846,6 +877,10 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
         if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
         {
             USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+            #endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
         }
     }
 
@@ -879,11 +914,74 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 CyDmaTdFree(USBFS_DmaTd[i]);
                 USBFS_DmaTd[i] = DMA_INVALID_TD;
             }
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+                {
+                    CyDmaTdFree(USBFS_DmaNextTd[i]);
+                    USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+                }
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
             i++;
         }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
     }
 
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_LoadNextInEP
+    ********************************************************************************
+    *
+    * Summary:
+    *  This internal function is used for IN endpoint DMA reconfiguration in
+    *  Auto DMA mode.
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number.
+    *  mode:   0 - Configure DMA to send the the rest of data.
+    *          1 - Configure DMA to repeat 2 last bytes of the first burst.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) 
+    {
+        reg16 *convert;
+
+        if(mode == 0u)
+        {
+            /* Configure DMA to send the the rest of data */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                            USBFS_DMA_BYTES_PER_BURST));
+            USBFS_inBufFull[epNumber] = 1u;
+        }
+        else
+        {
+            /* Configure DMA to repeat 2 last bytes of the first burst. */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert,  LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                   USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+        }
+
+        /* CyDmaChSetInitialTd API is optimised to init TD */
+        CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -891,8 +989,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
 ********************************************************************************
 *
 * Summary:
-*  Loads and enables the specified USB data endpoint for an IN interrupt or bulk
-*  transfer.
+*  Loads and enables the specified USB data endpoint for an IN transfer.
 *
 * Parameters:
 *  epNumber: Contains the data endpoint number.
@@ -916,7 +1013,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
     {
@@ -929,7 +1026,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             {
                 length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Set the count and data toggle */
         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
@@ -950,15 +1047,15 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
         #else
             /* Init DMA if it was not initialized */
-            if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+            if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-            if((pData != NULL) && (length > 0u))
+            if ((pData != NULL) && (length > 0u))
             {
                 /* Enable DMA in mode2 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
@@ -978,16 +1075,37 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 /* When zero-length packet - write the Mode register directly */
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            if(pData != NULL)
+            if (pData != NULL)
             {
                 /* Enable DMA in mode3 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                USBFS_inLength[epNumber] = length;
+                USBFS_inDataPointer[epNumber] = pData;
+                /* Configure DMA to send the data only for the first burst */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+                    (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+                    USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+                /* The second TD will be executed only when the first one fails.
+                *  The intention of this TD is to generate NRQ interrupt
+                *  and repeat 2 last bytes of the first burst.
+                */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+                                               USBFS_DmaNextTd[epNumber],
+                                               USBFS_epX_TD_TERMOUT_EN[epNumber]);
+                /* Configure DmaNextTd to clear Data ready status */
+                (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber],  LO16((uint32)&clearInDataRdyStatus),
+                                                                LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+            #else /* Configure DMA to send all data*/
                 (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
                                                USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
                 (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
                 /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
                 (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
                 /* Enable the DMA */
@@ -999,8 +1117,28 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
                 if(length > 0u)
                 {
+                #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                    USBFS_inLength[epNumber] = length;
+                    USBFS_inBufFull[epNumber] = 0u;
+                    (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+                    /* Configure DMA to send the data only for the first burst */
+                    (void) CyDmaTdSetConfiguration(
+                        USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+                        USBFS_DMA_BYTES_PER_BURST : length,
+                        USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+                    (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+                                             LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+                    /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+                    (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+                    /* Enable the DMA */
+                    (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                    (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+                #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
                     /* Set Data ready status, This will generate DMA request */
-                    * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #ifndef USBFS_MANUAL_IN_EP_ARM
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #endif  /* USBFS_MANUAL_IN_EP_ARM */
                     /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
                 }
                 else
@@ -1009,8 +1147,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                     CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
                 }
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
     }
 }
 
@@ -1047,10 +1184,10 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 xferCount;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
     {
@@ -1064,7 +1201,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 length = xferCount;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         #if(USBFS_EP_MM == USBFS__EP_MANUAL)
             /* Copy the data using the arbiter data register */
@@ -1081,7 +1218,8 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             /* Enable DMA in mode2 for transferring data */
@@ -1097,7 +1235,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /* Enable DMA in mode3 for transferring data */
@@ -1112,7 +1250,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
             (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     }
     else
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h
index 5392bd64..5121efac 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: USBFS.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,6 +20,11 @@
 #include "cyfitter.h"
 #include "CyLib.h"
 
+/*  User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
 
 /***************************************
 * Conditional Compilation Parameters
@@ -28,7 +33,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component USBFS_v2_60 requires cy_boot v3.0 or later
+    #error Component USBFS_v2_80 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -47,7 +52,7 @@
 #else
     #define USBFS_DATA
     #define USBFS_XDATA
-#endif /* End __C51__ */
+#endif /*  __C51__ */
 #define USBFS_NULL       NULL
 
 
@@ -105,6 +110,7 @@
 #define USBFS_EP8_ISR_REMOVE                 (1u)
 #define USBFS_EP_MM                          (0u)
 #define USBFS_EP_MA                          (0u)
+#define USBFS_EP_DMA_AUTO_OPT                (0u)
 #define USBFS_DMA1_REMOVE                    (1u)
 #define USBFS_DMA2_REMOVE                    (1u)
 #define USBFS_DMA3_REMOVE                    (1u)
@@ -226,7 +232,7 @@ void   USBFS_Resume(void) ;
 #endif  /* USBFS_ENABLE_FWSN_STRING */
 #if (USBFS_MON_VBUS == 1u)
     uint8  USBFS_VBusPresent(void) ;
-#endif /* End USBFS_MON_VBUS */
+#endif /*  USBFS_MON_VBUS */
 
 #if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
@@ -234,19 +240,24 @@ void   USBFS_Resume(void) ;
     void USBFS_CyBtldrCommStart(void) ;
     void USBFS_CyBtldrCommStop(void) ;
     void USBFS_CyBtldrCommReset(void) ;
-    cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
-    cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommRead       (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
 
-    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER      (64u)    /* EP 1 OUT */
-    #define USBFS_BTLDR_SIZEOF_READ_BUFFER       (64u)    /* EP 2 IN */
-    #define USBFS_BTLDR_MAX_PACKET_SIZE          USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+    #define USBFS_BTLDR_OUT_EP      (0x01u)
+    #define USBFS_BTLDR_IN_EP       (0x02u)
+
+    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER  (64u)   /* EP 1 OUT */
+    #define USBFS_BTLDR_SIZEOF_READ_BUFFER   (64u)   /* EP 2 IN  */
+    #define USBFS_BTLDR_MAX_PACKET_SIZE      USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+    #define USBFS_BTLDR_WAIT_1_MS            (1u)    /* Time Out quantity equal 1mS */
 
     /* These defines active if used USBFS interface as an
     *  IO Component for bootloading. When Custom_Interface selected
     *  in Bootloder configuration as the IO Component, user must
-    *  provide these functions
+    *  provide these functions.
     */
     #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
         #define CyBtldrCommStart        USBFS_CyBtldrCommStart
@@ -256,13 +267,13 @@ void   USBFS_Resume(void) ;
         #define CyBtldrCommRead         USBFS_CyBtldrCommRead
     #endif  /*End   CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP  */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP  */
 
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                     ;
     void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL) */
 
 #if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
     void USBFS_MIDI_EP_Init(void) ;
@@ -277,7 +288,7 @@ void   USBFS_Resume(void) ;
         void USBFS_MIDI_OUT_EP_Service(void) ;
     #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
 
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */
+#endif /*  USBFS_ENABLE_MIDI_API != 0u */
 
 /* Renamed Functions for backward compatibility.
 *  Should not be used in new designs.
@@ -490,10 +501,10 @@ void   USBFS_Resume(void) ;
 #define USBFS_EP_USAGE_TYPE_RESERVED         (0x30u)
 #define USBFS_EP_USAGE_TYPE_MASK             (0x30u)
 
-/* Endpoint Status defines */
+/* point Status defines */
 #define USBFS_EP_STATUS_LENGTH               (0x02u)
 
-/* Endpoint Device defines */
+/* point Device defines */
 #define USBFS_DEVICE_STATUS_LENGTH           (0x02u)
 
 #define USBFS_STATUS_LENGTH_MAX \
@@ -520,14 +531,60 @@ void   USBFS_Resume(void) ;
     /* DMA manual mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (0u)
     #define USBFS_DMA_REQUEST_PER_BURST      (0u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
     /* DMA automatic mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (32u)
+    #define USBFS_DMA_BYTES_REPEAT           (2u)
     /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes  44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
     #define USBFS_DMA_BUF_SIZE               (0x55u)
     #define USBFS_DMA_REQUEST_PER_BURST      (1u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+    #if(USBFS_DMA1_REMOVE == 0u)
+        #define USBFS_ep1_TD_TERMOUT_EN      USBFS_ep1__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep1_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA1_REMOVE == 0u */
+    #if(USBFS_DMA2_REMOVE == 0u)
+        #define USBFS_ep2_TD_TERMOUT_EN      USBFS_ep2__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep2_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA2_REMOVE == 0u */
+    #if(USBFS_DMA3_REMOVE == 0u)
+        #define USBFS_ep3_TD_TERMOUT_EN      USBFS_ep3__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep3_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA3_REMOVE == 0u */
+    #if(USBFS_DMA4_REMOVE == 0u)
+        #define USBFS_ep4_TD_TERMOUT_EN      USBFS_ep4__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep4_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA4_REMOVE == 0u */
+    #if(USBFS_DMA5_REMOVE == 0u)
+        #define USBFS_ep5_TD_TERMOUT_EN      USBFS_ep5__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep5_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA5_REMOVE == 0u */
+    #if(USBFS_DMA6_REMOVE == 0u)
+        #define USBFS_ep6_TD_TERMOUT_EN      USBFS_ep6__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep6_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA6_REMOVE == 0u */
+    #if(USBFS_DMA7_REMOVE == 0u)
+        #define USBFS_ep7_TD_TERMOUT_EN      USBFS_ep7__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep7_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA7_REMOVE == 0u */
+    #if(USBFS_DMA8_REMOVE == 0u)
+        #define USBFS_ep8_TD_TERMOUT_EN      USBFS_ep8__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep8_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA8_REMOVE == 0u */
+
+    #define     USBFS_EP17_SR_MASK           (0x7fu)
+    #define     USBFS_EP8_SR_MASK            (0x03u)
+
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
 /* DIE ID string descriptor defines */
 #if defined(USBFS_ENABLE_IDSN_STRING)
@@ -812,7 +869,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #if(!CY_PSOC5LP)
     #define USBFS_USBIO_CR2_PTR      (  (reg8 *) USBFS_USB__USBIO_CR2)
     #define USBFS_USBIO_CR2_REG      (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /* End CY_PSOC5LP */
+#endif /*  CY_PSOC5LP */
 
 #define USBFS_DIE_ID             CYDEV_FLSHID_CUST_TABLES_BASE
 
@@ -838,8 +895,8 @@ extern volatile uint8 USBFS_deviceStatus;
     #else
         #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
         #define USBFS_VBUS_MASK          (0x01u)
-    #endif /* End USBFS_EXTERN_VBUS == 0u */
-#endif /* End USBFS_MON_VBUS */
+    #endif /*  USBFS_EXTERN_VBUS == 0u */
+#endif /*  USBFS_MON_VBUS */
 
 /* Renamed Registers for backward compatibility.
 *  Should not be used in new designs.
@@ -1017,7 +1074,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
     #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
     #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /* End CYDEV_CHIP_DIE_EXPECT */
+#endif /*  CYDEV_CHIP_DIE_EXPECT */
 
 
 /***************************************
@@ -1138,6 +1195,8 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_ARB_EPX_CFG_CRC_BYPASS     (0x04u)
 #define USBFS_ARB_EPX_CFG_DMA_REQ        (0x02u)
 #define USBFS_ARB_EPX_CFG_IN_DATA_RDY    (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT        (USBFS_ARB_EPX_CFG_RESET | \
+                                                     USBFS_ARB_EPX_CFG_CRC_BYPASS)
 
 #define USBFS_ARB_EPX_SR_IN_BUF_FULL     (0x01u)
 #define USBFS_ARB_EPX_SR_DMA_GNT         (0x02u)
@@ -1153,7 +1212,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_ARB_EPX_INT_MASK           (0x1Du)
 #else
     #define USBFS_ARB_EPX_INT_MASK           (0x1Fu)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 #define USBFS_ARB_INT_MASK       (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
                                             (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
                                             (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
@@ -1190,7 +1249,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_DYN_RECONFIG_RDY_STS       (0x10u)
 
 
-#endif /* End CY_USBFS_USBFS_H */
+#endif /*  CY_USBFS_USBFS_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
index e942a8f8..3840625b 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dm_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dm_DM_STRONG     Strong Drive 
+*  USBFS_Dm_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dm_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dm_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dm_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dm_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dm_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dm_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
index bbfcfee4..42e93ad7 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
index 21242d52..2f649353 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dm_0		USBFS_Dm__0__PC
+#define USBFS_Dm_0		(USBFS_Dm__0__PC)
 
 #endif /* End Pins USBFS_Dm_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
index 5904f4ae..6f4efeff 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dp_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dp_DM_STRONG     Strong Drive 
+*  USBFS_Dp_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dp_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dp_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dp_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dp_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dp_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dp_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
index 217b6a3f..a3671299 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
index 702fb7ed..fd693968 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dp_0		USBFS_Dp__0__PC
+#define USBFS_Dp_0		(USBFS_Dp__0__PC)
 
 #endif /* End Pins USBFS_Dp_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c
index e837975c..9282b04f 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB AUDIO Class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,9 +21,9 @@
 
 #include "USBFS_audio.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -52,7 +53,7 @@
                                                                                   USBFS_VOL_MAX_MSB};
     volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,
                                                                                      USBFS_VOL_RES_MSB};
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+#endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
 
 /*******************************************************************************
@@ -93,17 +94,18 @@
 uint8 USBFS_DispatchAUDIOClassRqst(void) 
 {
     uint8 requestHandled = USBFS_FALSE;
+    uint8 bmRequestType  = CY_GET_REG8(USBFS_bmRequestType);
 
     #if defined(USBFS_ENABLE_AUDIO_STREAMING)
         uint8 epNumber;
         epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;
-    #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+    #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
-    if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
+
+    if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
     {
         /* Control Read */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
             /* Endpoint */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -112,12 +114,12 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlRead();
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_READ_REQUESTS` Place other request handler here */
 
@@ -127,8 +129,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -140,7 +141,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */
 
                         /* `#END` */
-                        
+
                          /* Entity ID Control Selector is MUTE */
                         USBFS_currentTD.wCount = 1u;
                         USBFS_currentTD.pData  = &USBFS_currentMute;
@@ -199,7 +200,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         USBFS_currentTD.wCount = 0u;
                         requestHandled   = USBFS_InitControlWrite();
 
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
 
@@ -213,27 +214,25 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
         {   /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \
-                                                                                    USBFS_RQST_DIR_H2D)
+    else
     {
         /* Control Write */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
-            /* Endpoint */
+            /* point */
             switch (CY_GET_REG8(USBFS_bRequest))
             {
                 case USBFS_SET_CUR:
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlWrite();
                         USBFS_frequencyChanged = epNumber;
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
 
@@ -243,8 +242,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -279,7 +277,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
                         /* `#END` */
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
 
@@ -290,17 +288,14 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
             }
         }
         else
-        {   /* USBFS_RQST_RCPT_OTHER */
+        {
+            /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else
-    {   /* requestHandled is initialized as FALSE by default */
-    }
 
     return(requestHandled);
 }
 
-
 #endif /* USER_SUPPLIED_AUDIO_HANDLER */
 
 
@@ -312,7 +307,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_AUDIO_CLASS*/
+#endif  /*  USBFS_ENABLE_AUDIO_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h
index 0e0feb20..6aa9357c 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -45,7 +48,7 @@
 #define USBFS_GET_MEM                    (0x85u)
 #define USBFS_GET_STAT                   (0xFFu)
 
-/* Endpoint Control Selectors (AUDIO Table A-19) */
+/* point Control Selectors (AUDIO Table A-19) */
 #define USBFS_EP_CONTROL_UNDEFINED       (0x00u)
 #define USBFS_SAMPLING_FREQ_CONTROL      (0x01u)
 #define USBFS_PITCH_CONTROL              (0x02u)
@@ -89,7 +92,7 @@ extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];
 
-#endif /* End CY_USBFS_USBFS_audio_H */
+#endif /*  CY_USBFS_USBFS_audio_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c
index 3cbb2f9d..747b0b0e 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_boot.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Boot loader API for USBFS Component.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,23 +20,11 @@
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
 
 
-/***************************************
-*    Bootloader defines
-***************************************/
-
-#define USBFS_CyBtLdrStarttimer(X, T)         {USBFS_universalTime = T * 10; X = 0u;}
-#define USBFS_CyBtLdrChecktimer(X)            ((X++ < USBFS_universalTime) ? 1u : 0u)
-
-#define USBFS_BTLDR_OUT_EP      (0x01u)
-#define USBFS_BTLDR_IN_EP       (0x02u)
-
-
 /***************************************
 *    Bootloader Variables
 ***************************************/
 
-static uint16 USBFS_universalTime;
-static uint8 USBFS_started = 0u;
+static uint8  USBFS_started = 0u;
 
 
 /*******************************************************************************
@@ -68,7 +56,6 @@ void USBFS_CyBtldrCommStart(void)
 
     /* USB component started, the correct enumeration will be checked in first Read operation */
     USBFS_started = 1u;
-
 }
 
 
@@ -100,13 +87,13 @@ void USBFS_CyBtldrCommStop(void)
 *  Resets the receive and transmit communication Buffers.
 *
 * Parameters:
-*  None.
+*  None
 *
 * Return:
-*  None.
+*  None
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
 void USBFS_CyBtldrCommReset(void) 
@@ -135,39 +122,39 @@ void USBFS_CyBtldrCommReset(void)
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    uint16 time;
-    cystatus status;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
     /* Enable IN transfer */
     USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);
 
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
-
     /* Wait for the master to read it. */
-    while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+    while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&
+           (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)
     {
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
     else
     {
         *count = size;
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
 
-    return(status);
+    return(retCode);
 }
 
 
@@ -193,70 +180,77 @@ cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    cystatus status;
-    uint16 time;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
-    if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
+    if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
     {
         size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;
     }
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
 
     /* Wait on enumeration in first time */
-    if(USBFS_started)
+    if (0u != USBFS_started)
     {
         /* Wait for Device to enumerate */
-        while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))
+        while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))
         {
-            CyDelay(1u); /* 1ms delay */
+            CyDelay(USBFS_BTLDR_WAIT_1_MS);
+            timeoutMs--;
         }
+
         /* Enable first OUT, if enumeration complete */
-        if(USBFS_GetConfiguration())
+        if (0u != USBFS_GetConfiguration())
         {
-            USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
+            (void) USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
             USBFS_CyBtldrCommReset();
             USBFS_started = 0u;
         }
     }
     else /* Check for configuration changes, has been done by Host */
     {
-        if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */
+        if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */
         {
-            if(USBFS_GetConfiguration() != 0u)   /* Init OUT endpoints when device reconfigured */
+            if (0u != USBFS_GetConfiguration())   /* Init OUT endpoints when device reconfigured */
             {
                 USBFS_CyBtldrCommReset();
             }
         }
     }
+
+    timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */
+
     /* Wait on next packet */
     while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+          (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     /* OUT EP has completed */
     if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)
     {
         *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
     else
     {
         *count = 0u;
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
-    return(status);
+
+    return(retCode);
 }
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
index 7d65d6b7..1a68c5f6 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  USB HID Class request handler.
+*  USB CDC class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
 *
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -26,7 +27,13 @@
 *    CDC Variables
 ***************************************/
 
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =
+{
+    0x00u, 0xC2u, 0x01u, 0x00u,     /* Data terminal rate 115200 */
+    0x00u,                          /* 1 Stop bit */
+    0x00u,                          /* None parity */
+    0x08u                           /* 8 data bits */
+};
 volatile uint8 USBFS_lineChanged;
 volatile uint16 USBFS_lineControlBitmap;
 volatile uint8 USBFS_cdc_data_in_ep;
@@ -36,7 +43,9 @@ volatile uint8 USBFS_cdc_data_out_ep;
 /***************************************
 *     Static Function Prototypes
 ***************************************/
-static uint16 USBFS_StrLen(const char8 string[]) ;
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
+    static uint16 USBFS_StrLen(const char8 string[]) ;
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */
 
 
 /***************************************
@@ -138,7 +147,6 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 ***************************************/
 #if (USBFS_ENABLE_CDC_CLASS_API != 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_CDC_Init
     ********************************************************************************
@@ -173,14 +181,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a specified number of bytes from the location specified by a
-    *  pointer to the PC.
+    *  This function sends a specified number of bytes from the location specified
+    *  by a pointer to the PC. The USBFS_CDCIsReady() function should be
+    *  called before sending new data, to be sure that the previous data has
+    *  finished sending.
+    *  If the last sent packet is less than maximum packet size the USB transfer
+    *  of this short packet will identify the end of the segment. If the last sent
+    *  packet is exactly maximum packet size, it shall be followed by a zero-length
+    *  packet (which is a short packet) to assure the end of segment is properly
+    *  identified. To send zero-length packet, use USBFS_PutData() API
+    *  with length parameter set to zero.
     *
     * Parameters:
     *  pData: pointer to the buffer containing data to be sent.
     *  length: Specifies the number of bytes to send from the pData
     *  buffer. Maximum length will be limited by the maximum packet
-    *  size for the endpoint.
+    *  size for the endpoint. Data will be lost if length is greater than Max
+    *  Packet Size.
     *
     * Return:
     *  None.
@@ -239,10 +256,15 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a null terminated string to the PC.
+    *  This function sends a null terminated string to the PC. This function will
+    *  block if there is not enough memory to place the whole string. It will block
+    *  until the entire string has been written to the transmit buffer.
+    *  The USBUART_CDCIsReady() function should be called before sending data with
+    *  a new call to USBFS_PutString(), to be sure that the previous data
+    *  has finished sending.
     *
     * Parameters:
-    *  string: pointer to the string to be sent to the PC
+    *  string: pointer to the string to be sent to the PC.
     *
     * Return:
     *  None.
@@ -254,41 +276,44 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     * Reentrant:
     *  No.
     *
-    * Theory:
-    *  This function will block if there is not enough memory to place the whole
-    *  string, it will block until the entire string has been written to the
-    *  transmit buffer.
-    *
     *******************************************************************************/
     void USBFS_PutString(const char8 string[]) 
     {
-        uint16 str_length;
-        uint16 send_length;
-        uint16 buf_index = 0u;
+        uint16 strLength;
+        uint16 sendLength;
+        uint16 bufIndex = 0u;
 
         /* Get length of the null terminated string */
-        str_length = USBFS_StrLen(string);
+        strLength = USBFS_StrLen(string);
         do
         {
             /* Limits length to maximum packet size for the EP */
-            send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
-                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;
+            sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
+                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;
              /* Enable IN transfer */
-            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);
-            str_length -= send_length;
+            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);
+            strLength -= sendLength;
 
-            /* If more data are present to send */
-            if(str_length > 0u)
+            /* If more data are present to send or full packet was sent */
+            if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))
             {
-                buf_index += send_length;
+                bufIndex += sendLength;
                 /* Wait for the Host to read it. */
                 while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==
                                           USBFS_IN_BUFFER_FULL)
                 {
                     ;
                 }
+                /* If the last sent packet is exactly maximum packet size,
+                *  it shall be followed by a zero-length packet to assure the
+                *  end of segment is properly identified by the terminal.
+                */
+                if(strLength == 0u)
+                {
+                    USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);
+                }
             }
-        }while(str_length > 0u);
+        }while(strLength > 0u);
     }
 
 
@@ -357,12 +382,17 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  This function returns the number of bytes that were received from the PC.
+    *  The returned length value should be passed to USBFS_GetData() as
+    *  a parameter to read all received data. If all of the received data is not
+    *  read at one time by the USBFS_GetData() API, the unread data will
+    *  be lost.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  Returns the number of received bytes.
+    *  Returns the number of received bytes. The maximum amount of received data at
+    *  a time is limited by the maximum packet size for the endpoint.
     *
     * Global variables:
     *   USBFS_cdc_data_out_ep: CDC OUT endpoint number used.
@@ -370,12 +400,16 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *******************************************************************************/
     uint16 USBFS_GetCount(void) 
     {
-        uint16 bytesCount = 0u;
+        uint16 bytesCount;
 
         if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)
         {
             bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);
         }
+        else
+        {
+            bytesCount = 0u;
+        }
 
         return(bytesCount);
     }
@@ -387,9 +421,9 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  Returns a nonzero value if the component received data or received
-    *  zero-length packet. The GetAll() or GetData() API should be called to read
-    *  data from the buffer and re-init OUT endpoint even when zero-length packet
-    *  received.
+    *  zero-length packet. The USBFS_GetAll() or
+    *  USBFS_GetData() API should be called to read data from the buffer
+    *  and re-init OUT endpoint even when zero-length packet received.
     *
     * Parameters:
     *  None.
@@ -413,17 +447,19 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Returns a nonzero value if the component is ready to send more data to the
-    *  PC. Otherwise returns zero. Should be called before sending new data to
-    *  ensure the previous data has finished sending.This function returns the
-    *  number of bytes that were received from the PC.
+    *  This function returns a nonzero value if the component is ready to send more
+    *  data to the PC; otherwise, it returns zero. The function should be called
+    *  before sending new data when using any of the following APIs:
+    *  USBFS_PutData(),USBFS_PutString(),
+    *  USBFS_PutChar or USBFS_PutCRLF(),
+    *  to be sure that the previous data has finished sending.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If the buffer can accept new data then this function returns a nonzero value.
-    *  Otherwise zero is returned.
+    *  If the buffer can accept new data, this function returns a nonzero value.
+    *  Otherwise, it returns zero.
     *
     * Global variables:
     *   USBFS_cdc_data_in_ep: CDC IN endpoint number used.
@@ -440,10 +476,12 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Gets a specified number of bytes from the input buffer and places it in a
-    *  data array specified by the passed pointer.
-    *  USBFS_DataIsReady() API should be called before, to be sure
-    *  that data is received from the Host.
+    *  This function gets a specified number of bytes from the input buffer and
+    *  places them in a data array specified by the passed pointer.
+    *  The USBFS_DataIsReady() API should be called first, to be sure
+    *  that data is received from the host. If all received data will not be read at
+    *  once, the unread data will be lost. The USBFS_GetData() API should
+    *  be called to get the number of bytes that were received.
     *
     * Parameters:
     *  pData: Pointer to the data array where data will be placed.
@@ -502,7 +540,8 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Reads one byte of received data from the buffer.
+    *  This function reads one byte of received data from the buffer. If more than
+    *  one byte has been received from the host, the rest of the data will be lost.
     *
     * Parameters:
     *  None.
@@ -531,17 +570,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  This function returns clear on read status of the line.
+    *  This function returns clear on read status of the line. It returns not zero
+    *  value when the host sends updated coding or control information to the
+    *  device. The USBFS_GetDTERate(), USBFS_GetCharFormat()
+    *  or USBFS_GetParityType() or USBFS_GetDataBits() API
+    *  should be called to read data coding information.
+    *  The USBFS_GetLineControl() API should be called to read line
+    *  control information.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not
-    *  zero value returned. Otherwise zero is returned.
+    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it
+    *  returns a nonzero value. Otherwise, it returns zero.
     *
     * Global variables:
-    *  USBFS_transferState - it is checked to be sure then OUT data
+    *  USBFS_transferState: it is checked to be sure then OUT data
     *    phase has been complete, and data written to the lineCoding or Control
     *    Bitmap buffer.
     *  USBFS_lineChanged: used as a flag to be aware that Host has been
@@ -689,7 +734,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
         return(USBFS_lineControlBitmap);
     }
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API*/
 
 
 /*******************************************************************************
@@ -700,7 +745,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS*/
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
index ca79f63e..0b95f086 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
@@ -1,13 +1,16 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component.
+*  Header File for the USBFS component.
 *  Contains CDC class prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,7 +44,7 @@
     uint8 USBFS_GetParityType(void) ;
     uint8 USBFS_GetDataBits(void) ;
     uint16 USBFS_GetLineControl(void) ;
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API */
 
 
 /***************************************
@@ -86,7 +89,7 @@ extern volatile uint16 USBFS_lineControlBitmap;
 extern volatile uint8 USBFS_cdc_data_in_ep;
 extern volatile uint8 USBFS_cdc_data_out_ep;
 
-#endif /* End CY_USBFS_USBFS_cdc_H */
+#endif /*  CY_USBFS_USBFS_cdc_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
index 8a8f5bea..e1fa37f1 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
@@ -1,12 +1,12 @@
 ;******************************************************************************
 ; File Name: USBFS_cdc.inf
-; Version 2.60
+; Version 2.80
 ;
 ; Description:
 ;  Windows USB CDC setup file for USBUART Device.
 ;
 ;******************************************************************************
-; Copyright 2007-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2007-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c
index 7b5dc275..16f6191b 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_cls.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Class request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -57,8 +57,8 @@ uint8 USBFS_DispatchClassRqst(void)
             break;
         case USBFS_RQST_RCPT_EP:         /* Class-specific request directed to the endpoint */
             /* Find related interface to the endpoint, wIndexLo contain EP number */
-            interfaceNumber =
-                USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;
+            interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &
+                              USBFS_DIR_UNUSED].interface;
             break;
         default:    /* RequestHandled is initialized as FALSE by default */
             break;
@@ -74,7 +74,7 @@ uint8 USBFS_DispatchClassRqst(void)
         case USBFS_CLASS_AUDIO:
             #if defined(USBFS_ENABLE_AUDIO_CLASS)
                 requestHandled = USBFS_DispatchAUDIOClassRqst();
-            #endif /* USBFS_ENABLE_HID_CLASS */
+            #endif /* USBFS_CLASS_AUDIO */
             break;
         case USBFS_CLASS_CDC:
             #if defined(USBFS_ENABLE_CDC_CLASS)
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
index 6bc5b1ec..9c108261 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_descr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB descriptors and storage.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,7 @@
 
 /*****************************************************************************
 *  User supplied descriptors.  If you want to specify your own descriptors,
-*  remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and
-*  add your descriptors.
+*  define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.
 *****************************************************************************/
 /* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */
 
@@ -95,7 +94,7 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = {
 /*  bEndpointAddress                       */ 0x01u,
 /*  bmAttributes                           */ 0x03u,
 /*  wMaxPacketSize                         */ 0x40u, 0x00u,
-/*  bInterval                              */ 0x80u,
+/*  bInterval                              */ 0x20u,
 /*********************************************************************
 * Endpoint Descriptor
 *********************************************************************/
@@ -104,7 +103,7 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = {
 /*  bEndpointAddress                       */ 0x82u,
 /*  bmAttributes                           */ 0x03u,
 /*  wMaxPacketSize                         */ 0x40u, 0x00u,
-/*  bInterval                              */ 0x40u,
+/*  bInterval                              */ 0x20u,
 /*********************************************************************
 * Interface Descriptor
 *********************************************************************/
@@ -136,7 +135,7 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = {
 /*  bEndpointAddress                       */ 0x03u,
 /*  bmAttributes                           */ 0x03u,
 /*  wMaxPacketSize                         */ 0x40u, 0x00u,
-/*  bInterval                              */ 0x80u,
+/*  bInterval                              */ 0x20u,
 /*********************************************************************
 * Endpoint Descriptor
 *********************************************************************/
@@ -145,7 +144,7 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = {
 /*  bEndpointAddress                       */ 0x84u,
 /*  bmAttributes                           */ 0x03u,
 /*  wMaxPacketSize                         */ 0x40u, 0x00u,
-/*  bInterval                              */ 0x40u
+/*  bInterval                              */ 0x20u
 };
 
 /*********************************************************************
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c
index f4308eab..a5fd19d6 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_drv.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Endpoint 0 Driver for the USBFS Component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c
index d758bf4d..37691f22 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_episr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Data endpoint Interrupt Service Routines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -16,9 +16,13 @@
 
 #include "USBFS.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 
 /***************************************
@@ -48,7 +52,8 @@
     ******************************************************************************/
     CY_ISR(USBFS_EP_1_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT)  && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -56,7 +61,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -72,23 +78,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &
                                                                     (uint8)~USBFS_SIE_EP_INT_EP1_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP1)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP1_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP1_ISR_REMOVE */
+#endif   /*  USBFS_EP1_ISR_REMOVE */
 
 
 #if(USBFS_EP2_ISR_REMOVE == 0u)
@@ -109,7 +117,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_2_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -117,7 +126,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -133,23 +143,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP2_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP2)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP2_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP2_ISR_REMOVE */
+#endif   /*  USBFS_EP2_ISR_REMOVE */
 
 
 #if(USBFS_EP3_ISR_REMOVE == 0u)
@@ -170,7 +182,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_3_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -178,7 +191,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -194,23 +208,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP3_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP3)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP3_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP3_ISR_REMOVE */
+#endif   /*  USBFS_EP3_ISR_REMOVE */
 
 
 #if(USBFS_EP4_ISR_REMOVE == 0u)
@@ -231,7 +247,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_4_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -239,7 +256,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -255,23 +273,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP4_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP4)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP4_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP4_ISR_REMOVE */
+#endif   /*  USBFS_EP4_ISR_REMOVE */
 
 
 #if(USBFS_EP5_ISR_REMOVE == 0u)
@@ -292,7 +312,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_5_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -300,7 +321,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -316,22 +338,24 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP5_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP5)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP5_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
-#endif   /* End USBFS_EP5_ISR_REMOVE */
+#endif   /*  USBFS_EP5_ISR_REMOVE */
 
 
 #if(USBFS_EP6_ISR_REMOVE == 0u)
@@ -352,7 +376,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_6_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -360,7 +385,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -376,23 +402,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP6_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP6)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP6_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP6_ISR_REMOVE */
+#endif   /*  USBFS_EP6_ISR_REMOVE */
 
 
 #if(USBFS_EP7_ISR_REMOVE == 0u)
@@ -413,7 +441,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_7_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -421,7 +450,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -437,23 +467,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP7_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP7)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP7_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP7_ISR_REMOVE */
+#endif   /*  USBFS_EP7_ISR_REMOVE */
 
 
 #if(USBFS_EP8_ISR_REMOVE == 0u)
@@ -474,7 +506,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_8_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -482,7 +515,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -498,23 +532,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP8_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP8)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP8_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP8_ISR_REMOVE */
+#endif   /*  USBFS_EP8_ISR_REMOVE */
 
 
 /*******************************************************************************
@@ -611,6 +647,17 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                         /* Clear Data ready status */
                         *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=
                                                                     (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                        #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                            /* Setup common area DMA with rest of the data */
+                            if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)
+                            {
+                                USBFS_LoadNextInEP(ep, 0u);
+                            }
+                            else
+                            {
+                                USBFS_inBufFull[ep] = 1u;
+                            }
+                        #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
                         /* Write the Mode register */
                         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);
                         #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)
@@ -618,7 +665,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                             {   /* Clear MIDI input pointer */
                                 USBFS_midiInPointer = 0u;
                             }
-                        #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                 }
                 /* (re)arm Out EP only for mode2 */
@@ -634,7 +681,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                                                                                     USBFS_EP[ep].epMode);
                         }
                     }
-                #endif /* End USBFS_EP_MM */
+                #endif /*  USBFS_EP_MM */
 
                 /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */
 
@@ -652,7 +699,82 @@ CY_ISR(USBFS_BUS_RESET_ISR)
         /* `#END` */
     }
 
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    /******************************************************************************
+    * Function Name: USBFS_EP_DMA_DONE_ISR
+    *******************************************************************************
+    *
+    * Summary:
+    *  Endpoint 1 DMA Done Interrupt Service Routine
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  None.
+    *
+    ******************************************************************************/
+    CY_ISR(USBFS_EP_DMA_DONE_ISR)
+    {
+        uint8 int8Status;
+        uint8 int17Status;
+        uint8 ep_status;
+        uint8 ep = USBFS_EP1;
+        uint8 ptr = 0u;
+
+        /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
+
+        /* `#END` */
+
+        /* Read clear on read status register with the EP source of interrupt */
+        int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;
+        int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;
+
+        while(int8Status != 0u)
+        {
+            while(int17Status != 0u)
+            {
+                if((int17Status & 1u) != 0u)  /* If EpX interrupt present */
+                {
+                    /* Read Endpoint Status Register */
+                    ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));
+                    if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&
+                        (USBFS_inBufFull[ep] == 0u))
+                    {
+                        /* `#START EP_DMA_DONE_USER_CODE` Place your code here */
+
+                        /* `#END` */
+
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
+                        /* repeat 2 last bytes to prefetch endpoint area */
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
+                                    USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);
+                        USBFS_LoadNextInEP(ep, 1);
+                        /* Set Data ready status, This will generate DMA request */
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    }
+                }
+                ptr += USBFS_EPX_CNTX_ADDR_OFFSET;               /* prepare pointer for next EP */
+                ep++;
+                int17Status >>= 1u;
+            }
+            int8Status >>= 1u;
+            if(int8Status != 0u)
+            {
+                /* Prepare pointer for EP8 */
+                ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+                ep = USBFS_EP8;
+                int17Status = int8Status & 0x01u;
+            }
+        }
+
+        /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
+
+        /* `#END` */
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c
index cc1ea1e2..5a9ac690 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c
@@ -1,14 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_hid.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB HID Class request handler.
 *
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
+*
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -416,7 +419,7 @@ void USBFS_FindReport(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_HID_CLASS */
+#endif  /*  USBFS_ENABLE_HID_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h
index a34e4e73..c8075d2a 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_hid.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -58,7 +61,7 @@ uint8 USBFS_GetProtocol(uint8 interface) ;
 #define USBFS_HID_GET_REPORT_OUTPUT      (0x02u)
 #define USBFS_HID_GET_REPORT_FEATURE     (0x03u)
 
-#endif /* End CY_USBFS_USBFS_hid_H */
+#endif /*  CY_USBFS_USBFS_hid_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c
index 0247caf2..7354b89d 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c
@@ -1,14 +1,18 @@
 /*******************************************************************************
 * File Name: USBFS_midi.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  MIDI Streaming request handler.
 *  This file contains routines for sending and receiving MIDI
 *  messages, and handles running status in both directions.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -60,15 +64,15 @@
         volatile uint16 USBFS_midiInPointer;                            /* Input endpoint buffer pointer */
     #else
         volatile uint8 USBFS_midiInPointer;                             /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */
     volatile uint8 USBFS_midi_in_ep;                                    /* Input endpoint number */
     uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];       /* Input endpoint buffer */
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
     volatile uint8 USBFS_midi_out_ep;                                   /* Output endpoint number */
     uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE];     /* Output endpoint buffer */
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event;            /* MIDI RX status structure */
@@ -79,8 +83,8 @@
         static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event;        /* MIDI RX status structure */
         static volatile uint8 USBFS_MIDI2_TxRunStat;                     /* MIDI Output running status */
         volatile uint8 USBFS_MIDI2_InqFlags;                             /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
 
 /***************************************
@@ -134,30 +138,30 @@ void USBFS_MIDI_EP_Init(void)
 {
     #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
        USBFS_midiInPointer = 0u;
-    #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
         #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
             /* Init DMA configurations for IN EP*/
             USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,
                                                                                 USBFS_MIDI_IN_BUFF_SIZE);
-                                                                                
-        #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+        #endif  /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
         #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
             /* Init DMA configurations for OUT EP*/
             (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,
                                                                                 USBFS_MIDI_OUT_BUFF_SIZE);
-        #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-    #endif  /* End USBFS__EP_DMAAUTO */
+        #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
+    #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
 
     #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
         USBFS_EnableOutEP(USBFS_midi_out_ep);
-    #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
     /* Initialize the MIDI port(s) */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
         USBFS_MIDI_Init();
-    #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 }
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
@@ -199,37 +203,43 @@ void USBFS_MIDI_EP_Init(void)
         #else
             uint8 outLength;
             uint8 outPointer;
-        #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */
+        #endif /*  USBFS_MIDI_OUT_BUFF_SIZE >=256 */
 
         uint8 dmaState = 0u;
 
         /* Service the USB MIDI output endpoint */
         if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)
         {
-            #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+            #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                 outLength = USBFS_GetEPCount(USBFS_midi_out_ep);
             #else
                 outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);
-            #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+            #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
             #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-                #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+                #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                     outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, outLength);
                 #else
                     outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, (uint16)outLength);
-                #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+                #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
                 #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                     do  /* wait for DMA transfer complete */
                     {
-                        (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
-                    }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-            #endif  /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+                        (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
+                    }
+                    while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
+                #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */
+
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
+
             if(dmaState != 0u)
             {
                 /* Suppress compiler warning */
             }
+
             if (outLength >= USBFS_EVENT_LENGTH)
             {
                 outPointer = 0u;
@@ -252,7 +262,7 @@ void USBFS_MIDI_EP_Init(void)
                         {
                             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                                 USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);
-                            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+                            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
                         }
                         else
                         {
@@ -260,7 +270,7 @@ void USBFS_MIDI_EP_Init(void)
 
                             /* `#END` */
                         }
-                    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+                    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
                     /* Process any local MIDI output functions */
                     USBFS_callbackLocalMidiEvent(
@@ -272,7 +282,7 @@ void USBFS_MIDI_EP_Init(void)
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /* Enable Out EP*/
                 USBFS_EnableOutEP(USBFS_midi_out_ep);
-            #endif  /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif  /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
         }
     }
 
@@ -322,12 +332,12 @@ void USBFS_MIDI_EP_Init(void)
             #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
                 /* rearm IN EP */
                 USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);
-            #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
 
             /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */
             #if(USBFS_EP_MM == USBFS__EP_MANUAL)
                 USBFS_midiInPointer = 0u;
-            #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
+            #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */
             }
         }
     }
@@ -370,7 +380,8 @@ void USBFS_MIDI_EP_Init(void)
             uint8 m2 = 0u;
             do
             {
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI1 input port for a complete event */
                     m1 = USBFS_MIDI1_GetEvent();
@@ -382,7 +393,8 @@ void USBFS_MIDI_EP_Init(void)
                 }
 
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI2 input port for a complete event */
                     m2 = USBFS_MIDI2_GetEvent();
@@ -392,11 +404,12 @@ void USBFS_MIDI_EP_Init(void)
                                                     USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);
                     }
                 }
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 
-            }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
-                   && ((m1 != 0u) || (m2 != 0u)) );
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            }while( (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&
+                    ((m1 != 0u) || (m2 != 0u)) );
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         /* Service the USB MIDI input endpoint */
         USBFS_MIDI_IN_EP_Service();
@@ -453,8 +466,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_DisableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_DisableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         if (USBFS_midiInPointer >
                     (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
@@ -481,15 +494,16 @@ void USBFS_MIDI_EP_Init(void)
                         (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                     {
                         USBFS_MIDI_IN_EP_Service();
-                        if (USBFS_midiInPointer >
-                            (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
+                        if(USBFS_midiInPointer >
+                          (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                         {
                             /* Error condition. HOST is not ready to receive this packet. */
                             retError = USBFS_TRUE;
                             break;
                         }
                     }
-                }while(ic > USBFS_EVENT_BYTE3);
+                }
+                while(ic > USBFS_EVENT_BYTE3);
 
                 if(retError == USBFS_FALSE)
                 {
@@ -507,8 +521,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_EnableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_EnableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         return (retError);
     }
@@ -712,7 +726,7 @@ void USBFS_MIDI_EP_Init(void)
             /* Change the priority of the UART TX interrupt */
             CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);
             CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
+        #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
 
         /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */
 
@@ -915,12 +929,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI1_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;
@@ -930,12 +945,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI1_UART_rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI1_UART_rxBufferWrite;
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary buffer pointer
@@ -948,7 +963,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /*  ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI1_UART_rxBuffer[rxBufferRead];
                     /* Increment pointer with a wrap */
@@ -965,11 +980,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI1_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                         MIDI1_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -984,11 +999,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI1_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1105,6 +1120,7 @@ void USBFS_MIDI_EP_Init(void)
         /* `#END` */
     }
 
+
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
 
 
@@ -1137,12 +1153,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI2_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;
@@ -1152,12 +1169,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI2_UART_rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI2_UART_rxBufferWrite;
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary output pointer to
@@ -1170,7 +1187,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI2_UART_rxBuffer[rxBufferRead];
                     rxBufferRead++;
@@ -1186,11 +1203,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI2_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                         MIDI2_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -1205,11 +1222,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI2_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1325,17 +1342,17 @@ void USBFS_MIDI_EP_Init(void)
 
         /* `#END` */
     }
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
-#endif  /* End (USBFS_ENABLE_MIDI_API != 0u) */
+#endif  /*  (USBFS_ENABLE_MIDI_API != 0u) */
 
 
 /* `#START MIDI_FUNCTIONS` Place any additional functions here */
 
 /* `#END` */
 
-#endif  /* End defined(USBFS_ENABLE_MIDI_STREAMING) */
+#endif  /*  defined(USBFS_ENABLE_MIDI_STREAMING) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h
index 473cc26d..c4c236d9 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h
@@ -1,13 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_midi.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Header File for the USBFS MIDI module.
 *  Contains prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,7 +25,7 @@
 
 
 /***************************************
-*    Data Struct Definition
+*    Data Structure Definition
 ***************************************/
 
 /* The following structure is used to hold status information for
@@ -112,12 +116,13 @@ typedef struct
 #define USBFS_CUSTOM_UART_TX_PRIOR_NUM   (0x04u)
 #define USBFS_CUSTOM_UART_RX_PRIOR_NUM   (0x02u)
 
-#define USBFS_ISR_SERVICE_MIDI_OUT     \
+#define USBFS_ISR_SERVICE_MIDI_OUT         \
         ( (USBFS_ENABLE_MIDI_API != 0u) && \
-          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )
+          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))
 #define USBFS_ISR_SERVICE_MIDI_IN     \
         ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )
 
+
 /***************************************
 * External function references
 ***************************************/
@@ -132,13 +137,13 @@ void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     #include "MIDI1_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
     #include "MIDI2_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     #include <CyDmac.h>
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 
 
 /***************************************
@@ -159,8 +164,8 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         uint8 USBFS_MIDI2_GetEvent(void) ;
         void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])
                                                     ;
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 
 /***************************************
@@ -174,7 +179,7 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         extern volatile uint16 USBFS_midiInPointer;                       /* Input endpoint buffer pointer */
     #else
         extern volatile uint8 USBFS_midiInPointer;                        /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /*  USBFS_MIDI_IN_BUFF_SIZE >=256 */
     extern volatile uint8 USBFS_midi_in_ep;                               /* Input endpoint number */
     extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];  /* Input endpoint buffer */
 #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
@@ -188,13 +193,13 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
     extern volatile uint8 USBFS_MIDI1_InqFlags;                              /* Device inquiry flag */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
         extern volatile uint8 USBFS_MIDI2_InqFlags;                          /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
 
 
-#endif /* End CY_USBFS_USBFS_midi_H */
+#endif /*  CY_USBFS_USBFS_midi_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c
index 003d7f17..f0e9a277 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_pm.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This file provides Suspend/Resume APIs functionality.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -36,7 +36,6 @@ static USBFS_BACKUP_STRUCT  USBFS_backup;
 
 #if(USBFS_DP_ISR_REMOVE == 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_DP_Interrupt
     ********************************************************************************
@@ -119,7 +118,7 @@ void USBFS_RestoreConfig(void)
 ********************************************************************************
 *
 * Summary:
-*  This function disables the USBFS block and prepares for power donwn mode.
+*  This function disables the USBFS block and prepares for power down mode.
 *
 * Parameters:
 *  None.
@@ -145,7 +144,7 @@ void USBFS_Suspend(void)
 
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
         USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;
@@ -158,7 +157,7 @@ void USBFS_Suspend(void)
         /* Disable the SIE */
         USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;
 
-        CyDelayUs(0u);  /*~50ns delay */
+        CyDelayUs(0u);  /* ~50ns delay */
         /* Store mode and Disable VRegulator*/
         USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;
         USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;
@@ -181,16 +180,16 @@ void USBFS_Suspend(void)
     {
         USBFS_backup.enableState = 0u;
     }
+
     CyExitCriticalSection(enableInterrupts);
 
     /* Set the DP Interrupt for wake-up from sleep mode. */
     #if(USBFS_DP_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM,   &USBFS_DP_ISR);
+        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
         CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);
         CyIntClearPending(USBFS_DP_INTC_VECT_NUM);
         CyIntEnable(USBFS_DP_INTC_VECT_NUM);
     #endif /* (USBFS_DP_ISR_REMOVE == 0u) */
-
 }
 
 
@@ -223,7 +222,7 @@ void USBFS_Resume(void)
     {
         #if(USBFS_DP_ISR_REMOVE == 0u)
             CyIntDisable(USBFS_DP_INTC_VECT_NUM);
-        #endif /* End USBFS_DP_ISR_REMOVE */
+        #endif /*  USBFS_DP_ISR_REMOVE */
 
         /* Enable USB block */
         USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
@@ -245,18 +244,18 @@ void USBFS_Resume(void)
         /* Set the USBIO pull-up enable */
         USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
 
-        /* Reinit Arbiter configuration for DMA transfers */
+        /* Re-init Arbiter configuration for DMA transfers */
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-            /* usb arb interrupt enable */
+            /* Usb arb interrupt enable */
             USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
             #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /*Set cfg cmplt this rises DMA request when the full configuration is done */
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* STALL_IN_OUT */
         CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
@@ -268,8 +267,8 @@ void USBFS_Resume(void)
 
         /* Restore USB register settings */
         USBFS_RestoreConfig();
-
     }
+
     CyExitCriticalSection(enableInterrupts);
 }
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
index 6c332eeb..e361aee3 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: .h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This private file provides constants and parameter values for the
@@ -10,7 +10,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -77,7 +77,14 @@ extern volatile T_USBFS_TD USBFS_currentTD;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     extern uint8 USBFS_DmaChan[USBFS_MAX_EP];
     extern uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];
+    extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 extern volatile uint8 USBFS_ep0Toggle;
 extern volatile uint8 USBFS_lastPacketSize;
@@ -117,7 +124,7 @@ void USBFS_Config(uint8 clearAltSetting) ;
 void USBFS_ConfigAltChanged(void) ;
 void USBFS_ConfigReg(void) ;
 
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                             ;
 const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)
                                                             ;
@@ -130,56 +137,62 @@ uint8 USBFS_ValidateAlternateSetting(void) ;
 void USBFS_SaveConfig(void) ;
 void USBFS_RestoreConfig(void) ;
 
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
 #if defined(USBFS_ENABLE_IDSN_STRING)
     void USBFS_ReadDieID(uint8 descr[]) ;
 #endif /* USBFS_ENABLE_IDSN_STRING */
 
 #if defined(USBFS_ENABLE_HID_CLASS)
     uint8 USBFS_DispatchHIDClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_AUDIO_CLASS)
     uint8 USBFS_DispatchAUDIOClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_CDC_CLASS)
     uint8 USBFS_DispatchCDCClassRqst(void);
-#endif /* End USBFS_ENABLE_CDC_CLASS */
+#endif /*  USBFS_ENABLE_CDC_CLASS */
 
 CY_ISR_PROTO(USBFS_EP_0_ISR);
 #if(USBFS_EP1_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_1_ISR);
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /*  USBFS_EP1_ISR_REMOVE */
 #if(USBFS_EP2_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_2_ISR);
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /*  USBFS_EP2_ISR_REMOVE */
 #if(USBFS_EP3_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_3_ISR);
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /*  USBFS_EP3_ISR_REMOVE */
 #if(USBFS_EP4_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_4_ISR);
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /*  USBFS_EP4_ISR_REMOVE */
 #if(USBFS_EP5_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_5_ISR);
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /*  USBFS_EP5_ISR_REMOVE */
 #if(USBFS_EP6_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_6_ISR);
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /*  USBFS_EP6_ISR_REMOVE */
 #if(USBFS_EP7_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_7_ISR);
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /*  USBFS_EP7_ISR_REMOVE */
 #if(USBFS_EP8_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_8_ISR);
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /*  USBFS_EP8_ISR_REMOVE */
 CY_ISR_PROTO(USBFS_BUS_RESET_ISR);
 #if(USBFS_SOF_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_SOF_ISR);
-#endif /* End USBFS_SOF_ISR_REMOVE */
+#endif /*  USBFS_SOF_ISR_REMOVE */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     CY_ISR_PROTO(USBFS_ARB_ISR);
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 #if(USBFS_DP_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_DP_ISR);
-#endif /* End USBFS_DP_ISR_REMOVE */
-
+#endif /*  USBFS_DP_ISR_REMOVE */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 /***************************************
 * Request Handlers
@@ -193,6 +206,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    HID Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_HID_CLASS)
     void USBFS_FindReport(void) ;
     void USBFS_FindReportDescriptor(void) ;
@@ -203,6 +217,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    MIDI Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_MIDI_STREAMING)
     void USBFS_MIDI_IN_EP_Service(void) ;
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c
index af2f201a..0a177d20 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_std.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Standard request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -17,9 +17,9 @@
 #include "USBFS.h"
 #include "USBFS_cdc.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -33,7 +33,6 @@
 
 #if defined(USBFS_ENABLE_FWSN_STRING)
 
-
     /*******************************************************************************
     * Function Name: USBFS_SerialNumString
     ********************************************************************************
@@ -57,10 +56,10 @@
         USBFS_snStringConfirm = USBFS_FALSE;
         if(snString != NULL)
         {
-            USBFS_fwSerialNumberStringDescriptor = snString;
             /* Check descriptor validation */
             if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )
             {
+                USBFS_fwSerialNumberStringDescriptor = snString;
                 USBFS_snStringConfirm = USBFS_TRUE;
             }
         }
@@ -90,6 +89,7 @@ uint8 USBFS_HandleStandardRqst(void)
 {
     uint8 requestHandled = USBFS_FALSE;
     uint8 interfaceNumber;
+    uint8 configurationN;
     #if defined(USBFS_ENABLE_STRINGS)
         volatile uint8 *pStr = 0u;
         #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)
@@ -117,11 +117,14 @@ uint8 USBFS_HandleStandardRqst(void)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)
                 {
                     pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));
-                    USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
-                    USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
-                                      USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
-                                     (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
-                    requestHandled  = USBFS_InitControlRead();
+                    if( pTmp != NULL )  /* Verify that requested descriptor exists */
+                    {
+                        USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
+                        USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
+                                          USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
+                                         (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
+                        requestHandled  = USBFS_InitControlRead();
+                    }
                 }
                 #if defined(USBFS_ENABLE_STRINGS)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)
@@ -138,34 +141,39 @@ uint8 USBFS_HandleStandardRqst(void)
                             pStr = &pStr[descrLength];
                             nStr++;
                         }
-                    #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */
+                    #endif /*  USBFS_ENABLE_DESCRIPTOR_STRINGS */
                     /* Microsoft OS String*/
                     #if defined(USBFS_ENABLE_MSOS_STRING)
                         if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )
                         {
                             pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];
                         }
-                    #endif /* End USBFS_ENABLE_MSOS_STRING*/
+                    #endif /*  USBFS_ENABLE_MSOS_STRING*/
                     /* SN string */
                     #if defined(USBFS_ENABLE_SN_STRING)
                         if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&
                             (CY_GET_REG8(USBFS_wValueLo) ==
                             USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )
                         {
-                            pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
-                            #if defined(USBFS_ENABLE_FWSN_STRING)
-                                if(USBFS_snStringConfirm != USBFS_FALSE)
-                                {
-                                    pStr = USBFS_fwSerialNumberStringDescriptor;
-                                }
-                            #endif  /* USBFS_ENABLE_FWSN_STRING */
+
                             #if defined(USBFS_ENABLE_IDSN_STRING)
                                 /* Read DIE ID and generate string descriptor in RAM */
                                 USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);
                                 pStr = USBFS_idSerialNumberStringDescriptor;
-                            #endif    /* End USBFS_ENABLE_IDSN_STRING */
+                            #elif defined(USBFS_ENABLE_FWSN_STRING)
+                                if(USBFS_snStringConfirm != USBFS_FALSE)
+                                {
+                                    pStr = USBFS_fwSerialNumberStringDescriptor;
+                                }
+                                else
+                                {
+                                    pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                                }
+                            #else
+                                pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                            #endif  /* defined(USBFS_ENABLE_IDSN_STRING) */
                         }
-                    #endif    /* End USBFS_ENABLE_SN_STRING */
+                    #endif    /*  USBFS_ENABLE_SN_STRING */
                     if (*pStr != 0u)
                     {
                         USBFS_currentTD.count = *pStr;
@@ -173,7 +181,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         requestHandled  = USBFS_InitControlRead();
                     }
                 }
-                #endif /* End USBFS_ENABLE_STRINGS */
+                #endif /*  USBFS_ENABLE_STRINGS */
                 else
                 {
                     requestHandled = USBFS_DispatchClassRqst();
@@ -225,10 +233,23 @@ uint8 USBFS_HandleStandardRqst(void)
                 requestHandled = USBFS_InitNoDataControlTransfer();
                 break;
             case USBFS_SET_CONFIGURATION:
-                USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);
-                USBFS_configurationChanged = USBFS_TRUE;
-                USBFS_Config(USBFS_TRUE);
-                requestHandled = USBFS_InitNoDataControlTransfer();
+                configurationN = CY_GET_REG8(USBFS_wValueLo);
+                if(configurationN > 0u)
+                {   /* Verify that configuration descriptor exists */
+                    pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);
+                }
+                /* Responds with a Request Error when configuration number is invalid */
+                if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))
+                {
+                    /* Set new configuration if it has been changed */
+                    if(configurationN != USBFS_configuration)
+                    {
+                        USBFS_configuration = configurationN;
+                        USBFS_configurationChanged = USBFS_TRUE;
+                        USBFS_Config(USBFS_TRUE);
+                    }
+                    requestHandled = USBFS_InitNoDataControlTransfer();
+                }
                 break;
             case USBFS_SET_INTERFACE:
                 if (USBFS_ValidateAlternateSetting() != 0u)
@@ -241,7 +262,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         USBFS_Config(USBFS_FALSE);
                     #else
                         USBFS_ConfigAltChanged();
-                    #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+                    #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
                     /* Update handled Alt setting changes status */
                     USBFS_interfaceSetting_last[interfaceNumber] =
                          USBFS_interfaceSetting[interfaceNumber];
@@ -342,7 +363,6 @@ uint8 USBFS_HandleStandardRqst(void)
         uint8 value;
         const char8 CYCODE hex[16u] = "0123456789ABCDEF";
 
-
         /* Check descriptor validation */
         if( descr != NULL)
         {
@@ -360,7 +380,7 @@ uint8 USBFS_HandleStandardRqst(void)
         }
     }
 
-#endif /* End USBFS_ENABLE_IDSN_STRING */
+#endif /*  USBFS_ENABLE_IDSN_STRING */
 
 
 /*******************************************************************************
@@ -384,20 +404,18 @@ void USBFS_ConfigReg(void)
     uint8 ep;
     uint8 i;
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-        uint8 ep_type = 0u;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        uint8 epType = 0u;
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     /* Set the endpoint buffer addresses */
     ep = USBFS_EP1;
     for (i = 0u; i < 0x80u; i+= 0x10u)
     {
-        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |
-                                                          USBFS_ARB_EPX_CFG_RESET);
-
+        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */
             CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)
         {
@@ -410,8 +428,8 @@ void USBFS_ConfigReg(void)
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);
                 /* Prepare EP type mask for automatic memory allocation */
                 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-                    ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                    epType |= (uint8)(0x01u << (ep - USBFS_EP1));
+                #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
         }
         else
@@ -427,7 +445,7 @@ void USBFS_ConfigReg(void)
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i),     USBFS_EP[ep].buffOffset & 0xFFu);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         ep++;
     }
@@ -438,13 +456,13 @@ void USBFS_ConfigReg(void)
         USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST;   /* DMA burst threshold */
         USBFS_DMA_THRES_MSB_REG = 0u;
         USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;
-        USBFS_EP_TYPE_REG = ep_type;
+        USBFS_EP_TYPE_REG = epType;
         /* Cfg_cmp bit set to 1 once configuration is complete. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |
                                        USBFS_ARB_CFG_CFG_CPM;
         /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);
 }
@@ -477,11 +495,11 @@ void USBFS_Config(uint8 clearAltSetting)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     const uint8 *pDescr;
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 buffCount = 0u;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     const T_USBFS_LUT CYCODE *pTmp;
     const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;
@@ -534,56 +552,56 @@ void USBFS_Config(uint8 clearAltSetting)
             pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;
             for (i = 0u; i < ep; i++)
             {
-                /* Compare current Alternate setting with EP Alt*/
+                /* Compare current Alternate setting with EP Alt */
                 if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                 {
                     cur_ep = pEP->addr & USBFS_DIR_UNUSED;
-                    ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                    epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                     if (pEP->addr & USBFS_DIR_IN)
                     {
                         /* IN Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     else
                     {
                         /* OUT Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                      (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;
                     USBFS_EP[cur_ep].addr = pEP->addr;
@@ -591,7 +609,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 }
                 pEP = &pEP[1u];
             }
-        #else /* Config for static EP memory allocation  */
+        #else /* Configure for static EP memory allocation  */
             for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)
             {
                 /* p_list points the endpoint setting table. */
@@ -610,67 +628,67 @@ void USBFS_Config(uint8 clearAltSetting)
                         /* Compare current Alternate setting with EP Alt*/
                         if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                         {
-                            ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                            epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                             if ((pEP->addr & USBFS_DIR_IN) != 0u)
                             {
                                 /* IN Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             else
                             {
                                 /* OUT Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             USBFS_EP[i].addr = pEP->addr;
                             USBFS_EP[i].attrib = pEP->attributes;
 
                             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                                 break;      /* use first EP setting in Auto memory managment */
-                            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
                         }
                     }
                     pEP = &pEP[1u];
                 }
             }
-        #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+        #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
 
         /* Init class array for each interface and interface number for each EP.
         *  It is used for handling Class specific requests directed to either an
@@ -694,7 +712,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 USBFS_EP[ep].buffOffset = buffCount;
                  buffCount += USBFS_EP[ep].bufferSize;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Configure hardware registers */
         USBFS_ConfigReg();
@@ -725,7 +743,7 @@ void USBFS_ConfigAltChanged(void)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     uint8 ri;
 
     const T_USBFS_LUT CYCODE *pTmp;
@@ -753,19 +771,19 @@ void USBFS_ConfigAltChanged(void)
             {
                 cur_ep = pEP->addr & USBFS_DIR_UNUSED;
                 ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-                ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                 if ((pEP->addr & USBFS_DIR_IN) != 0u)
                 {
                     /* IN Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                 }
                 else
                 {
                     /* OUT Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                 }
                  /* Change the SIE mode for the selected EP to NAK ALL */
@@ -823,7 +841,7 @@ void USBFS_ConfigAltChanged(void)
                                                                 USBFS_EP[cur_ep].buffOffset & 0xFFu);
                 CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),
                                                                 USBFS_EP[cur_ep].buffOffset >> 8u);
-            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
             /* Get next EP element */
             pEP = &pEP[1u];
@@ -840,13 +858,13 @@ void USBFS_ConfigAltChanged(void)
 *  This routine returns a pointer a configuration table entry
 *
 * Parameters:
-*  c:  Configuration Index
+*  confIndex:  Configuration Index
 *
 * Return:
-*  Device Descriptor pointer.
+*  Device Descriptor pointer or NULL when descriptor isn't exists.
 *
 *******************************************************************************/
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                         
 {
     /* Device Table */
@@ -856,8 +874,20 @@ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
 
     /* The first entry points to the Device Descriptor,
     *  the rest configuration entries.
-	*/
-    return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );
+    *  Set pointer to the first Configuration Descriptor
+    */
+    pTmp = &pTmp[1u];
+    /* For this table, c is the number of configuration descriptors  */
+    if(confIndex >= pTmp->c)   /* Verify that required configuration descriptor exists */
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) NULL;
+    }
+    else
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;
+    }
+
+    return( pTmp );
 }
 
 
@@ -902,14 +932,24 @@ const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void)
                                                         
 {
     const T_USBFS_LUT CYCODE *pTmp;
+    const uint8 CYCODE *pInterfaceClass;
     uint8 currentInterfacesNum;
 
     pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
-    currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
-    /* Third entry in the LUT starts the Interface Table pointers */
-    /* The INTERFACE_CLASS table is located after all interfaces */
-    pTmp = &pTmp[currentInterfacesNum + 2u];
-    return( (const uint8 CYCODE *) pTmp->p_list );
+    if( pTmp != NULL )
+    {
+        currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
+        /* Third entry in the LUT starts the Interface Table pointers */
+        /* The INTERFACE_CLASS table is located after all interfaces */
+        pTmp = &pTmp[currentInterfacesNum + 2u];
+        pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;
+    }
+    else
+    {
+        pInterfaceClass = (const uint8 CYCODE *) NULL;
+    }
+
+    return( pInterfaceClass );
 }
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
index 6543a676..2565e8fb 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_vnd.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB vendor request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -34,7 +34,7 @@
 ********************************************************************************
 *
 * Summary:
-*  This routine provide users with a method to implement vendor specifc
+*  This routine provide users with a method to implement vendor specific
 *  requests.
 *
 *  To implement vendor specific requests, add your code in this function to
@@ -66,7 +66,7 @@ uint8 USBFS_HandleVendorRqst(void)
                     USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     requestHandled  = USBFS_InitControlRead();
-                #endif /* End USBFS_ENABLE_MSOS_STRING */
+                #endif /*  USBFS_ENABLE_MSOS_STRING */
                 break;
             default:
                 break;
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
index 784e93eb..e9b62e09 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
@@ -45,10 +45,10 @@ CY_METADATA_SIZE    = 64;
  */
 EXTERN(Reset)
 
-/* Bring in the interrupt routines & vector */
+/* Bring in interrupt routines & vector */
 EXTERN(main)
 
-/* Bring in the meta data */
+/* Bring in meta data */
 EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
 EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 
@@ -56,7 +56,7 @@ EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 PROVIDE(__cy_heap_start = _end);
 PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);
 PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));
-PROVIDE(__cy_heap_end = __cy_stack - 0x4000);
+PROVIDE(__cy_heap_end = __cy_stack - 0x1000);
 
 
 SECTIONS
@@ -90,7 +90,7 @@ SECTIONS
     /* Make sure we pulled in some reset code.  */
     ASSERT (. != __cy_reset, "No reset code");
 
-	/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
+	/* Place DMA initialization before text to ensure it gets placed in first 64K of flash */
     *(.dma_init)
     ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
 		
@@ -217,14 +217,14 @@ SECTIONS
   .heap (NOLOAD) :
   {
     . = _end;
-    . += 0x1000;
+    . += 0x0400;
     __cy_heap_limit = .;
   } >ram
 
-  .stack (__cy_stack - 0x4000) (NOLOAD) :
+  .stack (__cy_stack - 0x1000) (NOLOAD) :
   {
     __cy_stack_limit = .;
-    . += 0x4000;
+    . += 0x1000;
   } >ram
   
   /* Check if data + heap + stack exceeds RAM limit */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
index cb5d1655..011f0576 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: core_cm3_psoc5.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides important type information for the PSoC5.  This includes types
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
index 9906255c..4780df06 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the power management.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,8 @@
 
 
 /*******************************************************************
-* Place your includes, defines and code here. Do not use merge
-* region below unless any component datasheet suggest to do so.
+* Place your includes, defines, and code here. Do not use the merge
+* region below unless any component datasheet suggests doing so.
 *******************************************************************/
 /* `#START CY_PM_HEADER_INCLUDE` */
 
@@ -51,8 +51,8 @@ static void CyPmHviLviRestore(void) ;
 *
 * Summary:
 *  This function is called in preparation for entering sleep or hibernate low
-*  power modes. Saves all state of the clocking system that does not persist
-*  during sleep/hibernate or that needs to be altered in preparation for
+*  power modes. Saves all the states of the clocking system that do not persist
+*  during sleep/hibernate or that need to be altered in preparation for
 *  sleep/hibernate. Shutdowns all the digital and analog clock dividers for the
 *  active power mode configuration.
 *
@@ -105,6 +105,45 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imo2x = CY_PM_DISABLED;
     }
 
+    /* Master clock - save source */
+    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+
+    /* Switch Master clock's source from PLL's output to PLL's source */
+    if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)
+    {
+        switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)
+        {
+        case CY_PM_CLKDIST_PLL_SRC_IMO:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_XTAL:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_DSI:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);
+            break;
+
+        default:
+            CYASSERT(0u != 0u);
+            break;
+        }
+    }
+
+    /* PLL - check enable state, disable if needed */
+    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
+    {
+        /* PLL is enabled - save state and disable */
+        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
+        CyPLL_OUT_Stop();
+    }
+    else
+    {
+        /* PLL is disabled - save state */
+        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
+    }
+
     /* IMO - set appropriate frequency for LPM */
     CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);
 
@@ -119,8 +158,11 @@ void CyPmSaveClocks(void)
         /* IMO - save disabled state */
         cyPmClockBackup.imoEnable = CY_PM_DISABLED;
 
-        /* IMO - enable */
+        /* Enable the IMO. Use software delay instead of the FTW-based inside */
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
+
+        /* Settling time of the IMO is of the order of less than 6us */
+        CyDelayUs(6u);
     }
 
     /* IMO - save the current IMOCLK source and set to IMO if not yet */
@@ -130,7 +172,7 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imoClkSrc =
             (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;
 
-        /* IMO -  set IMOCLK source to MHz OSC */
+        /* IMO -  set IMOCLK source to IMO */
         CyIMO_SetSource(CY_IMO_SOURCE_IMO);
     }
     else
@@ -161,16 +203,13 @@ void CyPmSaveClocks(void)
     if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)
     {
         CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);
-    }    /* Need to change nothing if master clock divider is 1 */
-
-    /* Master clock - save current source */
-    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+    }    /* No change if master clock divider is 1 */
 
     /* Master clock source - set it to IMO if not yet. */
     if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)
     {
         CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
-    }    /* Need to change nothing if master clock source is IMO */
+    }    /* No change if master clock source is IMO */
 
     /* Bus clock - save divider and set it, if needed, to divide-by-one */
     cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
@@ -180,22 +219,9 @@ void CyPmSaveClocks(void)
         CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);
     }    /* Do nothing if saved and actual values are equal */
 
-    /* Set number of wait cycles for the flash according CPU frequency in MHz */
+    /* Set number of wait cycles for flash according to CPU frequency in MHz */
     CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);
 
-    /* PLL - check enable state, disable if needed */
-    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
-    {
-        /* PLL is enabled - save state and disable */
-        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
-        CyPLL_OUT_Stop();
-    }
-    else
-    {
-        /* PLL is disabled - save state */
-        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
-    }
-
     /* MHz ECO - check enable state and disable if needed */
     if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))
     {
@@ -211,8 +237,8 @@ void CyPmSaveClocks(void)
 
 
     /***************************************************************************
-    * Save enable state of delay between the system bus clock and each of the
-    * 4 individual analog clocks. This bit non-retention and it's value should
+    * Save the enable state of delay between the system bus clock and each of the
+    * 4 individual analog clocks. This bit non-retention and its value should
     * be restored on wakeup.
     ***************************************************************************/
     if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))
@@ -240,11 +266,11 @@ void CyPmSaveClocks(void)
 *
 *  PSoC 3 and PSoC 5LP:
 *  The merge region could be used to process state when the megahertz crystal is
-*  not ready after the hold-off timeout.
+*  not ready after a hold-off timeout.
 *
 *  PSoC 5:
-*  The 130 ms is given for the megahertz crystal to stabilize. It's readiness is
-*  not verified after the hold-off timeout.
+*  The 130 ms is given for the megahertz crystal to stabilize. Its readiness is
+*  not verified after a hold-off timeout.
 *
 * Parameters:
 *  None
@@ -265,10 +291,10 @@ void CyPmRestoreClocks(void)
         CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ,  CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,
         CY_IMO_FREQ_48MHZ, 5u, 6u};
 
-    /* Restore enable state of delay between the system bus clock and ACLKs. */
+    /* Restore enable state of delay between system bus clock and ACLKs. */
     if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)
     {
-        /* Delay for both the bandgap and the delay line to settle out */
+        /* Delay for both bandgap and delay line to settle out */
         CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *
                         CY_PM_GET_CPU_FREQ_MHZ);
 
@@ -279,7 +305,7 @@ void CyPmRestoreClocks(void)
     if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)
     {
         /***********************************************************************
-        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait
+        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait
         * period uses FTW for period measurement. This could cause a problem
         * if CTW/FTW is used as a wake up time in the low power modes APIs.
         * So, the XTAL wait procedure is implemented with a software delay.
@@ -309,7 +335,7 @@ void CyPmRestoreClocks(void)
         {
             /*******************************************************************
             * Process the situation when megahertz crystal is not ready.
-            * Time to stabialize value is crystal specific.
+            * Time to stabilize the value is crystal specific.
             *******************************************************************/
            /* `#START_MHZ_ECO_TIMEOUT` */
 
@@ -318,10 +344,10 @@ void CyPmRestoreClocks(void)
     }   /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */
 
 
-    /* Temprorary set the maximum flash wait cycles */
+    /* Temprorary set maximum flash wait cycles */
     CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);
 
-    /* The XTAL and DSI clocks are ready to be source for Master clock. */
+    /* XTAL and DSI clocks are ready to be source for Master clock. */
     if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||
        (CY_PM_MASTER_CLK_SRC_DSI  == cyPmClockBackup.masterClkSrc))
     {
@@ -366,13 +392,6 @@ void CyPmRestoreClocks(void)
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
     }
 
-    /* IMO - restore disable state if needed */
-    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
-       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
-    {
-        CyIMO_Stop();
-    }
-
     /* IMO - restore IMOCLK source */
     CyIMO_SetSource(cyPmClockBackup.imoClkSrc);
 
@@ -389,6 +408,7 @@ void CyPmRestoreClocks(void)
                                 cyPmClockBackup.clkImoSrc;
     }
 
+
     /* PLL restore state */
     if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)
     {
@@ -398,12 +418,38 @@ void CyPmRestoreClocks(void)
         * as a wakeup time in the low power modes APIs. To omit this issue PLL
         * wait procedure is implemented with a software delay.
         ***********************************************************************/
+        status = CYRET_TIMEOUT;
 
         /* Enable PLL */
         (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);
 
-        /* Make a 250 us delay */
-        CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);
+        /* Read to clear lock status after delay */
+        CyDelayUs((uint32)80u);
+        (void) CY_PM_FASTCLK_PLL_SR_REG;
+
+        /* It should take 250 us lock: 251-80 = 171 */
+        for(i = 171u; i > 0u; i--)
+        {
+            CyDelayUs((uint32)1u);
+
+            /* Accept PLL is OK after two consecutive polls indicate PLL lock */
+            if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&
+               (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))
+            {
+                status = CYRET_SUCCESS;
+                break;
+            }
+        }
+
+        if(CYRET_TIMEOUT == status)
+        {
+            /*******************************************************************
+            * Process the situation when PLL is not ready.
+            *******************************************************************/
+           /* `#START_PLL_TIMEOUT` */
+
+           /* `#END` */
+        }
     }   /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */
 
 
@@ -421,6 +467,13 @@ void CyPmRestoreClocks(void)
         CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);
     }
 
+    /* IMO - disable if it was originally disabled */
+    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
+       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
+    {
+        CyIMO_Stop();
+    }
+
     /* Bus clock - restore divider, if needed */
     clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
     clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;
@@ -490,7 +543,7 @@ void CyPmRestoreClocks(void)
 *  Sleep Timer component and one second interval should be configured with the
 *  RTC component.
 *
-*  The wakeup behavior depends on wakeupSource parameter in the following
+*  The wakeup behavior depends on the wakeupSource parameter in the following
 *  manner: upon function execution the device will be switched from Active to
 *  Alternate Active mode and then the CPU will be halted. When an enabled wakeup
 *  event occurs the device will return to Active mode.  Similarly when an
@@ -534,7 +587,7 @@ void CyPmRestoreClocks(void)
             For PSoC 3 silicon the valid range of  values is 1 to 256.
 *
 *  wakeUpSource:    Specifies a bitwise mask of wakeup sources. In addition, if
-*                   a wakeupTime has been specified the associated timer will be
+*                   a wakeupTime has been specified, the associated timer will be
 *                   included as a wakeup source.
 *
 *           Define                      Source
@@ -556,13 +609,13 @@ void CyPmRestoreClocks(void)
 *  *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.
 *  **Note: CTW and One PPS wakeup signals are in the same mask bit.
 *
-*  When specifying a Comparator as the wakeupSource an instance specific define
-*  should be used that will track with the specific comparator that the instance
-*  is placed into. As an example, for a Comparator instance named MyComp the
+*  When specifying a Comparator as the wakeupSource, an instance specific define
+*  that will track with the specific comparator that the instance
+*  is placed into should be used. As an example, for a Comparator instance named MyComp the
 *  value to OR into the mask is: MyComp_ctComp__CMP_MASK.
 *
 *  When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()
-*  function must be called upon wakeup with corresponding parameter. Please
+*  function must be called upon wakeup with a corresponding parameter. Please
 *  refer to the CyPmReadStatus() API in the System Reference Guide for more
 *  information.
 *
@@ -576,7 +629,7 @@ void CyPmRestoreClocks(void)
 *  If a wakeupTime other than NONE is specified, then upon exit the state of the
 *  specified timer will be left as specified by wakeupTime with the timer
 *  enabled and the interrupt disabled.  Also, the ILO 1 KHz (if CTW timer is
-*  used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)
+*  used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)
 *  will be left started.
 *
 *******************************************************************************/
@@ -602,7 +655,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
         {
             CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_FTW;
         }
 
@@ -612,7 +665,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current CTW configuration and set new one */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_CTW;
         }
 
@@ -622,7 +675,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current 1PPS configuration and set new one */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;
         }
 
@@ -674,7 +727,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  Puts the part into the Sleep state.
 *
 *  Note Before calling this function, you must manually configure the power
-*  mode of the source clocks for the timer that is used as wakeup timer.
+*  mode of the source clocks for the timer that is used as the wakeup timer.
 *
 *  Note Before calling this function, you must prepare clock tree configuration
 *  for the low power mode by calling CyPmSaveClocks(). And restore clock
@@ -685,7 +738,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  PSoC 3:
 *  Before switching to Sleep, if a wakeupTime other than NONE is specified,
 *  then the appropriate timer state is configured as specified with the
-*  interrupt for that timer disabled.  The wakeup source will be the combination
+*  interrupt for that timer disabled.  The wakeup source will be a combination
 *  of the values specified in the wakeupSource and any timer specified in the
 *  wakeupTime argument.  Once the wakeup condition is satisfied, then all saved
 *  state is restored and the function returns in the Active state.
@@ -706,7 +759,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  The wakeupTime parameter is not used and the only NONE can be specified.
 *  The wakeup time must be configured with the component, SleepTimer for CTW
 *  intervals and RTC for 1PPS interval. The component must be configured to
-*  generate an interrrupt.
+*  generate interrupt.
 *
 * Parameters:
 *  wakeupTime:      Specifies a timer wakeup source and the frequency of that
@@ -780,7 +833,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  detect (power supply supervising capabilities) are required in a design
 *  during sleep, use the Central Time Wheel (CTW) to periodically wake the
 *  device, perform software buzz, and refresh the supervisory services. If LVI,
-*  HVI, or Brown Out is not required, then use of the CTW is not required.
+*  HVI, or Brown Out is not required, then CTW is not required.
 *  Refer to the device errata for more information.
 *
 *******************************************************************************/
@@ -816,13 +869,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
     /***********************************************************************
     * PSoC3 < TO6:
-    * - Hardware buzz must be disabled before sleep mode entry.
+    * - Hardware buzz must be disabled before the sleep mode entry.
     * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must
-    *   be aslo disabled.
+    *   be also disabled.
     *
     * PSoC3 >= TO6:
-    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be
-    *   enabled before sleep mode entry and restored on wakeup.
+    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware
+    *   buzz must be enabled before the sleep mode entry and restored on
+    *   the wakeup.
     ***********************************************************************/
     #if(CY_PSOC3)
 
@@ -860,9 +914,9 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************************
-    * For ARM-based devices, an interrupt is required for the CPU to wake up. The
+    * For ARM-based devices,interrupt is required for the CPU to wake up. The
     * Power Management implementation assumes that wakeup time is configured with a
-    * separate component (component-based wakeup time configuration) for an
+    * separate component (component-based wakeup time configuration) for
     * interrupt to be issued on terminal count. For more information, refer to the
     * Wakeup Time Configuration section of System Reference Guide.
     *******************************************************************************/
@@ -887,10 +941,10 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         /* CTW - save current and set new configuration */
         if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))
         {
-            /* Save current and set new configuration of the CTW */
+            /* Save current and set new configuration of CTW */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_CTW;
         }
 
@@ -900,7 +954,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
             /* Save current and set new configuration of the 1PPS */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_ONE_PPS;
         }
 
@@ -923,8 +977,8 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************
-    * Do not use merge region below unless any component datasheet
-    * suggest to do so.
+    * Do not use the merge region below unless any component datasheet
+    * suggests doing so.
     *******************************************************************/
     /* `#START CY_PM_JUST_BEFORE_SLEEP` */
 
@@ -949,13 +1003,13 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));
     }
 
-    /* Switch to the Sleep mode */
+    /* Switch to Sleep mode */
     CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);
 
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1023,7 +1077,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  PSoC 3 and PSoC 5LP:
 *  Before switching to Hibernate, the current status of the PICU wakeup source
 *  bit is saved and then set. This configures the device to wake up from the
-*  PICU. Make sure you have at least one pin configured to generate a PICU
+*  PICU. Make sure you have at least one pin configured to generate PICU
 *  interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls
 *  the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."
 *  In the Pins component datasheet, this register is referred to as the IRQ
@@ -1046,14 +1100,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  requirement begins when the device wakes up. There is no hardware check that
 *  this requirement is met. The specified delay should be done on ISR entry.
 *
-*  After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
+*  After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
 *  instance name of the Pins component) function must be called to clear the
-*  latched pin events to allow proper Hibernate mode entry andd to enable
+*  latched pin events to allow the proper Hibernate mode entry and to enable
 *  detection of future events.
 *
 *  The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to
 *  measure Hibernate/Sleep regulator settling time after a reset. The holdoff
-*  delay is measured using rising edges of the 1 kHz ILO.
+*  delay is measured using the rising edges of the 1 kHz ILO.
 *
 *******************************************************************************/
 void CyPmHibernate(void) 
@@ -1065,8 +1119,8 @@ void CyPmHibernate(void)
 
         /***********************************************************************
         * The Hibernate/Sleep regulator has a settling time after a reset.
-        * During this time, the system ignores requests to enter Sleep and
-        * Hibernate modes. The holdoff delay is measured using rising edges of
+        * During this time, the system ignores requests to enter the Sleep and
+        * Hibernate modes. The holdoff delay is measured using the rising edges of
         * the 1 kHz ILO.
         ***********************************************************************/
         if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))
@@ -1123,7 +1177,7 @@ void CyPmHibernate(void)
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1193,7 +1247,7 @@ uint8 CyPmReadStatus(uint8 mask)
     /* Enter critical section */
     interruptState = CyEnterCriticalSection();
 
-    /* Save value of the register, copy it and clear desired bit */
+    /* Save value of register, copy it and clear desired bit */
     interruptStatus |= CY_PM_INT_SR_REG;
     tmpStatus = interruptStatus;
     interruptStatus &= ((uint8)(~mask));
@@ -1234,11 +1288,11 @@ static void CyPmHibSaveSet(void)
     if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))
     {
         /***********************************************************************
-        * If I2C backup regulator is enabled, all the fixed-function registers
-        * store their values while device is in low power mode, otherwise their
+        * If the I2C backup regulator is enabled, all the fixed-function registers
+        * store their values while the device is in the low power mode, otherwise their
         * configuration is lost. The I2C API makes a decision to restore or not
         * to restore I2C registers based on this. If this regulator will be
-        * disabled and then enabled, I2C API will suppose that I2C block
+        * disabled and then enabled, I2C API will suppose that the I2C block
         * registers preserved their values, while this is not true. So, the
         * backup regulator is disabled. The I2C sleep APIs is responsible for
         * restoration.
@@ -1289,7 +1343,7 @@ static void CyPmHibSaveSet(void)
 
 
     /***************************************************************************
-    * Save and set power mode wakeup trim registers
+    * Save and set the power mode wakeup trim registers
     ***************************************************************************/
     cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;
     cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;
@@ -1304,12 +1358,12 @@ static void CyPmHibSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Restore device for proper Hibernate mode exit:
-*  - Restore LVI/HVI configuration - call CyPmHviLviRestore()
+*  Restores the device for the proper Hibernate mode exit:
+*  - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()
 *  - CyPmHibSlpSaveRestore() function is called
-*  - Restores ILO power down mode state and enable it
-*  - Restores state of 1 kHz and 100 kHz ILO and disable them
-*  - Restores sleep regulator settings
+*  - Restores ILO power down mode state and enables it
+*  - Restores the state of 1 kHz and 100 kHz ILO and disables them
+*  - Restores the sleep regulator settings
 *
 * Parameters:
 *  None
@@ -1352,7 +1406,7 @@ static void CyPmHibRestore(void)
 
 
     /***************************************************************************
-    * Restore power mode wakeup trim registers
+    * Restore the power mode wakeup trim registers
     ***************************************************************************/
     CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;
     CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;
@@ -1364,10 +1418,10 @@ static void CyPmHibRestore(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs CTW configuration:
-*  - Disables CTW interrupt
+*  Performs the CTW configuration:
+*  - Disables the CTW interrupt
 *  - Enables 1 kHz ILO
-*  - Sets new CTW interval
+*  - Sets a new CTW interval
 *
 * Parameters:
 *  ctwInterval: the CTW interval to be set.
@@ -1404,11 +1458,11 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
         /* Set CTW interval if needed */
         if(CY_PM_TW_CFG1_REG != ctwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG1_REG = ctwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the CTW */
+        /* Enable CTW */
         CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;
     }
 }
@@ -1421,7 +1475,7 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
 * Summary:
 *  Performs 1PPS configuration:
 *  - Starts 32 KHz XTAL
-*  - Disables 1PPS interupts
+*  - Disables 1PPS interrupts
 *  - Enables 1PPS
 *
 * Parameters:
@@ -1453,10 +1507,10 @@ void CyPmOppsSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs FTW configuration:
-*  - Disables FTW interrupt
+*  Performs the FTW configuration:
+*  - Disables the FTW interrupt
 *  - Enables 100 kHz ILO
-*  - Sets new FTW interval.
+*  - Sets a new FTW interval.
 *
 * Parameters:
 *  ftwInterval - FTW counter interval.
@@ -1465,7 +1519,7 @@ void CyPmOppsSet(void)
 *  None
 *
 * Side Effects:
-*  Enables ILO 100 KHz clock and leaves it enabled.
+*  Enables the ILO 100 KHz clock and leaves it enabled.
 *
 *******************************************************************************/
 void CyPmFtwSetInterval(uint8 ftwInterval) 
@@ -1476,13 +1530,13 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
     /* Enable 100kHz ILO */
     CyILO_Start100K();
 
-    /* Iterval could be set only while FTW is disabled */
+    /* Interval could be set only while FTW is disabled */
     if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))
     {
         /* Disable FTW, set new FTW interval if needed and enable it again */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Disable the CTW, set new CTW interval and enable it again */
+            /* Disable CTW, set new CTW interval and enable it again */
             CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));
             CY_PM_TW_CFG0_REG = ftwInterval;
             CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
@@ -1493,11 +1547,11 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
         /* Set new FTW counter interval if needed. FTW is disabled. */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG0_REG = ftwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the FTW */
+        /* Enable FTW */
         CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
     }
 }
@@ -1508,12 +1562,12 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for preparing device for Sleep and Hibernate low power
+*  This API is used for preparing the device for the Sleep and Hibernate low power
 *  modes entry:
-*  - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)
-*  - Saves SC/CT routing connections (PSoC 3/5/5LP)
-*  - Disables Serial Wire Viewer (SWV) (PSoC 3)
-*  - Save boost reference selection and set it to internal
+*  - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)
+*  - Saves the SC/CT routing connections (PSoC 3/5/5LP)
+*  - Disables the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Saves the boost reference selection and sets it to internal
 *
 * Parameters:
 *  None
@@ -1643,11 +1697,11 @@ static void CyPmHibSlpSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for restoring device configurations after wakeup from Sleep
+*  This API is used for restoring the device configurations after wakeup from the Sleep
 *  and Hibernate low power modes:
-*  - Restores SC/CT routing connections
-*  - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)
-*  - Restore boost reference selection
+*  - Restores the SC/CT routing connections
+*  - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Restores the  boost reference selection
 *
 * Parameters:
 *  None
@@ -1740,7 +1794,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lvidEn = CY_PM_ENABLED;
         cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;
 
-        /* Save state of reset device at a specified Vddd threshold */
+        /* Save state of reset device at specified Vddd threshold */
         cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1756,7 +1810,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lviaEn = CY_PM_ENABLED;
         cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;
 
-        /* Save state of reset device at a specified Vdda threshold */
+        /* Save state of reset device at specified Vdda threshold */
         cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1784,7 +1838,7 @@ static void CyPmHviLviSaveDisable(void)
 ********************************************************************************
 *
 * Summary:
-*  Restores analog and digital LVI and HVI configuration.
+*  Restores the analog and digital LVI and HVI configuration.
 *
 * Parameters:
 *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
index 327908be..6ea9bd60 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the power management API.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -54,7 +54,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC3)
 
-    /* Wake up time for the Sleep mode */
+    /* Wake up time for Sleep mode */
     #define PM_SLEEP_TIME_ONE_PPS           (0x01u)
     #define PM_SLEEP_TIME_CTW_2MS           (0x02u)
     #define PM_SLEEP_TIME_CTW_4MS           (0x03u)
@@ -72,7 +72,7 @@ void CyPmOppsSet(void) ;
     /* Difference between parameter's value and register's one */
     #define CY_PM_FTW_INTERVAL_SHIFT        (0x000Eu)
 
-    /* Wake up time for the Alternate Active mode */
+    /* Wake up time for Alternate Active mode */
     #define PM_ALT_ACT_TIME_ONE_PPS         (0x0001u)
     #define PM_ALT_ACT_TIME_CTW_2MS         (0x0002u)
     #define PM_ALT_ACT_TIME_CTW_4MS         (0x0003u)
@@ -91,7 +91,7 @@ void CyPmOppsSet(void) ;
 #endif  /* (CY_PSOC3) */
 
 
-/* Wake up sources for the Sleep mode */
+/* Wake up sources for Sleep mode */
 #define PM_SLEEP_SRC_COMPARATOR0        (0x0001u)
 #define PM_SLEEP_SRC_COMPARATOR1        (0x0002u)
 #define PM_SLEEP_SRC_COMPARATOR2        (0x0004u)
@@ -104,7 +104,7 @@ void CyPmOppsSet(void) ;
 #define PM_SLEEP_SRC_ONE_PPS            (0x0800u)
 #define PM_SLEEP_SRC_LCD                (0x1000u)
 
-/* Wake up sources for the Alternate Active mode */
+/* Wake up sources for Alternate Active mode */
 #define PM_ALT_ACT_SRC_COMPARATOR0      (0x0001u)
 #define PM_ALT_ACT_SRC_COMPARATOR1      (0x0002u)
 #define PM_ALT_ACT_SRC_COMPARATOR2      (0x0004u)
@@ -145,7 +145,7 @@ void CyPmOppsSet(void) ;
 #define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (5u)
 
 
-/* Delay line bandgap current settling time starting from a wakeup event */
+/* Delay line bandgap current settling time starting from wakeup event */
 #define     CY_PM_CLK_DELAY_BANDGAP_SETTLE_US       (50u)
 
 /* Delay line internal bias settling */
@@ -177,7 +177,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC5)
 
-    /* The CPU clock is directly derived from bus clock */
+    /* CPU clock is directly derived from bus clock */
     #define     CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])
 
 #endif  /* (CY_PSOC5) */
@@ -186,7 +186,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low
 * power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI
 * instruction into the instruction stream generated by the compiler. The GCC
 * compiler has to execute assembly language instruction.
 *******************************************************************************/
@@ -219,7 +219,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * This macro defines the IMO frequency that will be set by CyPmSaveClocks()
 * function based on Enable Fast IMO during Startup option from the DWR file.
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the
 * low power mode and restore IMO back to the value set by CyPmSaveClocks()
 * immediately on wakeup.
 *******************************************************************************/
@@ -243,7 +243,7 @@ typedef struct cyPmClockBackupStruct
     /* CyPmSaveClocks()/CyPmRestoreClocks() */
     uint8  enClkA;              /* Analog clocks enable         */
     uint8  enClkD;              /* Digital clocks enable        */
-    uint8  masterClkSrc;        /* The Master clock source      */
+    uint8  masterClkSrc;        /* Master clock source          */
     uint8  imoFreq;             /* IMO frequency (reg's value)  */
     uint8  imoUsbClk;           /* IMO USB CLK (reg's value)    */
     uint8  flashWaitCycles;     /* Flash wait cycles            */
@@ -252,7 +252,7 @@ typedef struct cyPmClockBackupStruct
     uint8  clkImoSrc;
     uint8  imo2x;               /* IMO doubler enable state     */
     uint8  clkSyncDiv;          /* Master clk divider           */
-    uint16 clkBusDiv;           /* The clk_bus divider          */
+    uint16 clkBusDiv;           /* clk_bus divider              */
     uint8  pllEnableState;      /* PLL enable state             */
     uint8  xmhzEnableState;     /* XM HZ enable state           */
     uint8  clkDistDelay;        /* Delay for clk_bus and ACLKs  */
@@ -472,6 +472,14 @@ typedef struct cyPmBackupStruct
 #define CY_PM_BOOST_CR2_REG           (* (reg8 *) CYREG_BOOST_CR2 )
 #define CY_PM_BOOST_CR2_PTR           (  (reg8 *) CYREG_BOOST_CR2 )
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_REG           (* (reg8 *) CYREG_INTC_CSR_EN )
+    #define CY_PM_INTC_CSR_EN_PTR           (  (reg8 *) CYREG_INTC_CSR_EN )
+
+#endif  /* (CY_PSOC3) */
+
 
 /***************************************
 * Register Constants
@@ -521,7 +529,12 @@ typedef struct cyPmBackupStruct
 #define CY_PM_CLKDIST_IMO_OUT_IMO       (0x00u)
 #define CY_PM_CLKDIST_IMO2X_SRC         (0x40u)
 
-/* Waiting for the hibernate/sleep regulator to stabilize */
+#define CY_PM_CLKDIST_PLL_SRC_MASK      (0x03u)
+#define CY_PM_CLKDIST_PLL_SRC_IMO       (0x00u)
+#define CY_PM_CLKDIST_PLL_SRC_XTAL      (0x01u)
+#define CY_PM_CLKDIST_PLL_SRC_DSI       (0x02u)
+
+/* Waiting for hibernate/sleep regulator to stabilize */
 #define CY_PM_MODE_CSR_PWRUP_PULSE_Q    (0x08u)
 
 #define CY_PM_MODE_CSR_ACTIVE           (0x00u)     /* Active power mode      */
@@ -533,10 +546,10 @@ typedef struct cyPmBackupStruct
 /* I2C regulator backup enable */
 #define CY_PM_PWRSYS_CR1_I2CREG_BACKUP  (0x04u)
 
-/* When set, prepares the system to disable the LDO-A */
+/* When set, prepares system to disable LDO-A */
 #define CY_PM_PWRSYS_CR1_LDOA_ISO       (0x01u)
 
-/* When set, disables the analog LDO regulator */
+/* When set, disables analog LDO regulator */
 #define CY_PM_PWRSYS_CR1_LDOA_DIS       (0x02u)
 
 #define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET  (0x04u)
@@ -554,19 +567,19 @@ typedef struct cyPmBackupStruct
 /* Bus Clock divider to divide-by-one */
 #define CY_PM_BUS_CLK_DIV_BY_ONE        (0x00u)
 
-/* HVI/LVI feature on the external analog and digital supply mask */
+/* HVI/LVI feature on external analog and digital supply mask */
 #define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)
 
-/* The high-voltage-interrupt feature on the external analog supply */
+/* High-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_HVIA_EN         (0x04u)
 
-/* The low-voltage-interrupt feature on the external analog supply */
+/* Low-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_LVIA_EN         (0x02u)
 
-/* The low-voltage-interrupt feature on the external digital supply */
+/* Low-voltage-interrupt feature on external digital supply */
 #define CY_PM_RESET_CR1_LVID_EN         (0x01u)
 
-/* Allows the system to program delays on clk_sync_d */
+/* Allows system to program delays on clk_sync_d */
 #define CY_PM_CLKDIST_DELAY_EN          (0x04u)
 
 
@@ -595,7 +608,7 @@ typedef struct cyPmBackupStruct
 #endif  /* (CY_PSOC3) */
 
 
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+/* Disables sleep regulator and shorts vccd to vpwrsleep */
 #define CY_PM_PWRSYS_SLP_TR_BYPASS          (0x10u)
 
 /* Boost Control 2: Select external precision reference */
@@ -615,9 +628,37 @@ typedef struct cyPmBackupStruct
 
 #endif  /* (CY_PSOC5) */
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_CLK       (0x01u)
+
+#endif  /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of
+* whether lock is subsequently lost) until it is read. Upon reading it will
+* clear. If lock is still true then the bit will simply set again. If lock
+* happens to be false when the clear on read occurs then the bit will stay
+* cleared until the next lock event.
+*******************************************************************************/
+#define CY_PM_FASTCLK_PLL_LOCKED       (0x01u)
+
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #if(CY_PSOC3)
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
index 1faf25ba..b2ce74e4 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c
@@ -30,47 +30,47 @@ __attribute__ ((__section__(".cybootloader"), used))
 const uint8 cy_bootloader[] = {
     0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u,
     0x59u, 0x01u, 0x00u, 0x00u, 0x59u, 0x01u, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u,
-    0x02u, 0x60u, 0x00u, 0xF0u, 0x87u, 0xFCu, 0x00u, 0xF0u,
-    0x9Du, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,
-    0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
-    0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u,
-    0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u,
-    0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x24u, 0x20u, 0x00u, 0x00u,
+    0x08u, 0xB5u, 0x05u, 0x4Bu, 0x1Au, 0x68u, 0x03u, 0xF5u,
+    0x3Fu, 0x53u, 0x02u, 0x33u, 0x1Au, 0x60u, 0x00u, 0xF0u,
+    0x51u, 0xFAu, 0x00u, 0xF0u, 0x9Bu, 0xF8u, 0x00u, 0xBFu,
+    0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
+    0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x4Bu, 0x13u, 0xB1u,
+    0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x23u,
+    0x23u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xE4u, 0x20u, 0x00u, 0x00u,
     0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u,
     0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u,
-    0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u,
-    0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x24u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
+    0x03u, 0x68u, 0x13u, 0xB1u, 0x05u, 0x4Bu, 0x03u, 0xB1u,
+    0x98u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xE4u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
     0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x34u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x7Au, 0x10u,
-    0x01u, 0xF0u, 0xFEu, 0x02u, 0x83u, 0xF8u, 0x7Au, 0x20u,
-    0x2Fu, 0x33u, 0x18u, 0x78u, 0x00u, 0xF0u, 0xFEu, 0x01u,
-    0x19u, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x03u, 0xF8u, 0x01u, 0x0Cu, 0x13u, 0xF8u,
-    0x0Cu, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
-    0x0Cu, 0x2Cu, 0x13u, 0xF8u, 0x2Au, 0x0Cu, 0x00u, 0xF0u,
-    0xFEu, 0x01u, 0x03u, 0xF8u, 0x2Au, 0x1Cu, 0x13u, 0xF8u,
-    0x2Eu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u,
-    0x2Eu, 0x0Cu, 0x13u, 0xF8u, 0x0Du, 0x1Cu, 0x01u, 0xF0u,
-    0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Du, 0x2Cu, 0x13u, 0xF8u,
-    0x2Bu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u,
-    0x2Bu, 0x1Cu, 0x13u, 0xF8u, 0x08u, 0x2Cu, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x03u, 0xF8u, 0x08u, 0x0Cu, 0x0Cu, 0x3Bu,
-    0x03u, 0x33u, 0x19u, 0x78u, 0x01u, 0xF0u, 0xFEu, 0x02u,
-    0x1Au, 0x70u, 0x58u, 0x7Bu, 0x00u, 0xF0u, 0xFEu, 0x01u,
-    0x59u, 0x73u, 0x1Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x00u,
-    0x18u, 0x73u, 0x13u, 0xF8u, 0x11u, 0x1Cu, 0x01u, 0xF0u,
+    0x08u, 0xB5u, 0x34u, 0x4Bu, 0x1Au, 0x78u, 0x2Fu, 0x33u,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x2Fu, 0x2Cu,
+    0x93u, 0xF8u, 0x4Bu, 0x20u, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x83u, 0xF8u, 0x4Bu, 0x20u, 0x1Au, 0x78u, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x1Au, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x01u, 0x2Cu,
+    0x13u, 0xF8u, 0x0Cu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x03u, 0xF8u, 0x0Cu, 0x2Cu, 0x13u, 0xF8u, 0x2Au, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x2Au, 0x2Cu,
+    0x13u, 0xF8u, 0x2Eu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x03u, 0xF8u, 0x2Eu, 0x2Cu, 0x13u, 0xF8u, 0x0Du, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Du, 0x2Cu,
+    0x13u, 0xF8u, 0x2Bu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x03u, 0xF8u, 0x2Bu, 0x2Cu, 0x13u, 0xF8u, 0x08u, 0x2Cu,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x08u, 0x2Cu,
+    0x09u, 0x3Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x1Au, 0x70u, 0x5Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x5Au, 0x73u, 0x1Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+    0x1Au, 0x73u, 0x13u, 0xF8u, 0x11u, 0x2Cu, 0x02u, 0xF0u,
     0xFEu, 0x02u, 0x03u, 0xF8u, 0x11u, 0x2Cu, 0x13u, 0xF8u,
-    0x12u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u,
-    0x12u, 0x1Cu, 0x13u, 0xF8u, 0x15u, 0x2Cu, 0x02u, 0xF0u,
-    0xFEu, 0x00u, 0x03u, 0xF8u, 0x15u, 0x0Cu, 0x13u, 0xF8u,
-    0x16u, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
-    0x16u, 0x2Cu, 0x93u, 0xF8u, 0x55u, 0x00u, 0x00u, 0xF0u,
-    0xFEu, 0x01u, 0x83u, 0xF8u, 0x55u, 0x10u, 0x00u, 0xF0u,
-    0xADu, 0xFBu, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u,
+    0x12u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+    0x12u, 0x2Cu, 0x13u, 0xF8u, 0x15u, 0x2Cu, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x03u, 0xF8u, 0x15u, 0x2Cu, 0x13u, 0xF8u,
+    0x16u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+    0x16u, 0x2Cu, 0x93u, 0xF8u, 0x55u, 0x20u, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x83u, 0xF8u, 0x55u, 0x20u, 0x00u, 0xF0u,
+    0xF1u, 0xFBu, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u,
     0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u,
     0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u,
     0x10u, 0x6Cu, 0x53u, 0xF8u, 0x0Cu, 0x0Cu, 0x53u, 0xF8u,
@@ -78,985 +78,1009 @@ const uint8 cy_bootloader[] = {
     0x02u, 0x04u, 0x03u, 0xD0u, 0xB4u, 0x58u, 0x84u, 0x50u,
     0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu,
     0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u,
-    0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u,
-    0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0x06u, 0xFFu,
+    0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x10u, 0x33u,
+    0x01u, 0x39u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0x66u, 0xFFu,
     0xFFu, 0xF7u, 0x6Eu, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u,
-    0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,
-    0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au,
-    0x0Du, 0x49u, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Du, 0x4Au,
-    0x42u, 0xF8u, 0x23u, 0x10u, 0x01u, 0x33u, 0x30u, 0x2Bu,
-    0xF3u, 0xD1u, 0x0Bu, 0x49u, 0x0Bu, 0x4Bu, 0x08u, 0x78u,
-    0x0Bu, 0x49u, 0x18u, 0x70u, 0x0Au, 0x60u, 0x00u, 0xF0u,
-    0x17u, 0xF8u, 0x0Au, 0x48u, 0x00u, 0x22u, 0x02u, 0x60u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x04u, 0xFAu, 0x05u,
-    0x0Cu, 0xEDu, 0x00u, 0xE0u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x59u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,
-    0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu,
-    0xF8u, 0xB5u, 0x72u, 0xB6u, 0x67u, 0x4Bu, 0x01u, 0x22u,
-    0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u,
-    0x06u, 0x20u, 0x52u, 0x24u, 0x64u, 0x4Eu, 0x1Au, 0x70u,
-    0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x63u, 0x4Bu,
-    0x63u, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u,
-    0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u,
-    0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x5Fu, 0x4Eu,
-    0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u,
-    0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,
-    0x7Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
-    0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x58u, 0x48u,
-    0x58u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,
-    0x57u, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,
-    0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u,
-    0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu,
-    0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u,
-    0x00u, 0xE0u, 0xFEu, 0xE7u, 0x4Fu, 0x4Fu, 0x06u, 0x21u,
-    0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u,
-    0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0xADu, 0xFEu,
-    0x07u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u,
-    0x49u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,
-    0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu,
-    0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u,
-    0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u,
-    0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u,
-    0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u,
-    0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x3Du, 0x4Cu,
-    0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u,
-    0x21u, 0x7Cu, 0x3Bu, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u,
-    0x3Au, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u,
-    0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x38u, 0x4Au,
-    0x43u, 0xF0u, 0x10u, 0x04u, 0x37u, 0x4Bu, 0x04u, 0x70u,
-    0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x18u, 0x89u,
-    0x54u, 0x60u, 0x10u, 0x81u, 0x1Au, 0x46u, 0x34u, 0x48u,
-    0x52u, 0xF8u, 0x0Au, 0x4Fu, 0x04u, 0x60u, 0x54u, 0x68u,
-    0x12u, 0x89u, 0x44u, 0x60u, 0x02u, 0x81u, 0x1Au, 0x46u,
-    0x52u, 0xF8u, 0x14u, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u,
-    0xCEu, 0x4Cu, 0x40u, 0xF8u, 0xCAu, 0x2Cu, 0x1Au, 0x46u,
-    0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u,
-    0xBEu, 0x4Cu, 0x40u, 0xF8u, 0xBAu, 0x2Cu, 0x1Au, 0x46u,
-    0x52u, 0xF8u, 0x24u, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u,
-    0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu, 0x1Au, 0x46u,
-    0x52u, 0xF8u, 0x2Cu, 0x4Fu, 0x40u, 0xF8u, 0x9Eu, 0x4Cu,
-    0x52u, 0x68u, 0x40u, 0xF8u, 0x9Au, 0x2Cu, 0x53u, 0xF8u,
-    0x34u, 0x0Fu, 0x20u, 0x4Au, 0x5Bu, 0x68u, 0x10u, 0x60u,
-    0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u, 0x42u, 0xF0u,
-    0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u, 0x1Eu, 0x4Au,
-    0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u, 0x1Bu, 0x09u,
-    0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au, 0x44u, 0x20u,
-    0x10u, 0x70u, 0x1Bu, 0x4Au, 0x0Bu, 0x46u, 0x0Cu, 0x31u,
-    0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u, 0x42u, 0xF8u,
-    0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u, 0x11u, 0x80u,
-    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x48u, 0x00u, 0x40u,
-    0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x23u, 0x00u, 0x00u,
+    0x08u, 0xB5u, 0x11u, 0x4Au, 0x11u, 0x4Bu, 0x1Au, 0x60u,
+    0x9Au, 0x68u, 0x42u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,
+    0x00u, 0x23u, 0x03u, 0x2Bu, 0x98u, 0xBFu, 0x0Eu, 0x4Au,
+    0x4Fu, 0xEAu, 0x83u, 0x00u, 0x94u, 0xBFu, 0x52u, 0xF8u,
+    0x23u, 0x10u, 0x0Cu, 0x49u, 0x0Cu, 0x4Au, 0x01u, 0x33u,
+    0x30u, 0x2Bu, 0x11u, 0x50u, 0xF1u, 0xD1u, 0x0Bu, 0x4Bu,
+    0x19u, 0x78u, 0x0Bu, 0x4Bu, 0x19u, 0x70u, 0x0Bu, 0x4Bu,
+    0x1Au, 0x60u, 0x00u, 0xF0u, 0x17u, 0xF8u, 0x0Au, 0x4Bu,
+    0x00u, 0x22u, 0x1Au, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+    0x00u, 0x04u, 0xFAu, 0x05u, 0x0Cu, 0xEDu, 0x00u, 0xE0u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x59u, 0x01u, 0x00u, 0x00u,
+    0x00u, 0xC0u, 0xFFu, 0x1Fu, 0xBCu, 0x76u, 0x00u, 0x40u,
+    0x04u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xEDu, 0x00u, 0xE0u,
+    0x00u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0x72u, 0xB6u,
+    0x63u, 0x4Bu, 0x01u, 0x22u, 0x1Au, 0x70u, 0x06u, 0x22u,
+    0xA3u, 0xF5u, 0xA0u, 0x63u, 0x1Au, 0x70u, 0x52u, 0x22u,
+    0xA3u, 0xF5u, 0x80u, 0x73u, 0x1Au, 0x70u, 0x5Fu, 0x4Bu,
+    0x19u, 0x25u, 0x1Au, 0x78u, 0x5Eu, 0x4Bu, 0xD2u, 0xB2u,
+    0x1Au, 0x70u, 0x40u, 0xF6u, 0x18u, 0x02u, 0xA3u, 0xF2u,
+    0x7Fu, 0x43u, 0x1Au, 0x80u, 0x41u, 0xF2u, 0x51u, 0x22u,
+    0x23u, 0xF8u, 0x02u, 0x2Cu, 0x00u, 0x24u, 0x59u, 0x4Bu,
+    0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+    0x01u, 0x03u, 0x43u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,
+    0x9Bu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
+    0x18u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x52u, 0x4Bu,
+    0x4Fu, 0xF4u, 0x80u, 0x72u, 0x1Au, 0x80u, 0x07u, 0x22u,
+    0x1Au, 0x70u, 0x50u, 0x4Au, 0x00u, 0x24u, 0x48u, 0x21u,
+    0x14u, 0x70u, 0x91u, 0x70u, 0x02u, 0x22u, 0x1Cu, 0x70u,
+    0x5Cu, 0x71u, 0x03u, 0xF8u, 0x03u, 0x2Cu, 0x93u, 0xF8u,
+    0xE4u, 0x26u, 0x42u, 0xF0u, 0x04u, 0x02u, 0x83u, 0xF8u,
+    0xE4u, 0x26u, 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x48u, 0x4Bu,
+    0x00u, 0x21u, 0x23u, 0x44u, 0x18u, 0x68u, 0x9Au, 0x88u,
+    0x06u, 0x34u, 0x01u, 0xF0u, 0x0Au, 0xFFu, 0x2Au, 0x2Cu,
+    0xF5u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u, 0x43u, 0x4Cu,
+    0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u, 0x20u, 0xF0u,
+    0xFFu, 0x06u, 0xC0u, 0xB2u, 0x45u, 0x00u, 0x04u, 0xEBu,
+    0x41u, 0x04u, 0xAAu, 0x42u, 0x08u, 0xD0u, 0x04u, 0xEBu,
+    0x02u, 0x0Cu, 0xA7u, 0x5Cu, 0x9Cu, 0xF8u, 0x01u, 0xC0u,
+    0x02u, 0x32u, 0x07u, 0xF8u, 0x06u, 0xC0u, 0xF4u, 0xE7u,
+    0x04u, 0x33u, 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE6u, 0xD1u,
+    0x37u, 0x4Bu, 0x38u, 0x4Cu, 0x1Au, 0x78u, 0x42u, 0xF0u,
+    0x02u, 0x02u, 0x1Au, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u,
+    0x02u, 0x02u, 0x1Au, 0x74u, 0x34u, 0x4Au, 0x13u, 0x78u,
+    0x43u, 0xF0u, 0x40u, 0x03u, 0x13u, 0x70u, 0x33u, 0x4Bu,
+    0x19u, 0x78u, 0x41u, 0xF0u, 0x10u, 0x01u, 0x19u, 0x70u,
+    0x31u, 0x4Bu, 0x18u, 0x68u, 0x59u, 0x68u, 0x1Du, 0x46u,
+    0x03u, 0xC4u, 0x19u, 0x89u, 0x55u, 0xF8u, 0x0Au, 0x0Fu,
+    0x21u, 0x80u, 0x69u, 0x68u, 0xE8u, 0x34u, 0x03u, 0xC4u,
+    0x29u, 0x89u, 0x18u, 0x46u, 0x21u, 0x80u, 0x50u, 0xF8u,
+    0x14u, 0x1Fu, 0xA4u, 0xF6u, 0x48u, 0x64u, 0xC4u, 0xF8u,
+    0x72u, 0x1Du, 0x41u, 0x68u, 0x18u, 0x46u, 0xC4u, 0xF8u,
+    0x76u, 0x1Du, 0x50u, 0xF8u, 0x1Cu, 0x1Fu, 0xC4u, 0xF8u,
+    0x82u, 0x1Du, 0x41u, 0x68u, 0x18u, 0x46u, 0xC4u, 0xF8u,
+    0x86u, 0x1Du, 0x50u, 0xF8u, 0x24u, 0x1Fu, 0xC4u, 0xF8u,
+    0x92u, 0x1Du, 0x41u, 0x68u, 0x18u, 0x46u, 0xC4u, 0xF8u,
+    0x96u, 0x1Du, 0x50u, 0xF8u, 0x2Cu, 0x1Fu, 0xC4u, 0xF8u,
+    0xA2u, 0x1Du, 0x41u, 0x68u, 0x1Bu, 0x48u, 0xC4u, 0xF8u,
+    0xA6u, 0x1Du, 0x53u, 0xF8u, 0x34u, 0x1Fu, 0x01u, 0x60u,
+    0x59u, 0x68u, 0x19u, 0x4Bu, 0x41u, 0x60u, 0x19u, 0x78u,
+    0x41u, 0xF0u, 0x08u, 0x01u, 0x19u, 0x70u, 0x17u, 0x4Bu,
+    0x17u, 0x49u, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x03u, 0xF0u,
+    0x07u, 0x00u, 0x1Bu, 0x09u, 0x08u, 0x70u, 0x4Bu, 0x70u,
+    0x14u, 0x4Bu, 0x44u, 0x21u, 0x19u, 0x70u, 0x0Fu, 0xCAu,
+    0x07u, 0xC4u, 0x23u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0xBFu,
+    0x00u, 0x48u, 0x00u, 0x40u, 0x0Fu, 0x01u, 0x00u, 0x49u,
     0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u,
     0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u,
-    0xE8u, 0x46u, 0x00u, 0x40u, 0x28u, 0x20u, 0x00u, 0x00u,
-    0x54u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,
-    0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u,
-    0x00u, 0x51u, 0x00u, 0x40u, 0xB2u, 0x20u, 0x00u, 0x00u,
-    0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u,
+    0xE8u, 0x20u, 0x00u, 0x00u, 0x14u, 0x21u, 0x00u, 0x00u,
+    0x03u, 0x50u, 0x01u, 0x40u, 0x00u, 0x51u, 0x00u, 0x40u,
+    0xA0u, 0x43u, 0x00u, 0x40u, 0xC2u, 0x43u, 0x00u, 0x40u,
+    0x72u, 0x21u, 0x00u, 0x00u, 0x62u, 0x51u, 0x00u, 0x40u,
     0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u,
     0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u,
-    0xB0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x00u,
-    0x43u, 0x1Eu, 0x10u, 0xB5u, 0x02u, 0x46u, 0x06u, 0x2Bu,
-    0x0Du, 0xD8u, 0xDFu, 0xE8u, 0x03u, 0xF0u, 0x06u, 0x0Eu,
-    0x23u, 0x04u, 0x08u, 0x0Au, 0x21u, 0x00u, 0x16u, 0x48u,
-    0x08u, 0xE0u, 0x16u, 0x4Bu, 0x1Bu, 0xE0u, 0x16u, 0x48u,
-    0x04u, 0xE0u, 0x16u, 0x48u, 0x02u, 0xE0u, 0x00u, 0x20u,
-    0x00u, 0xE0u, 0x15u, 0x48u, 0x41u, 0x78u, 0x00u, 0x78u,
-    0x41u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x2Au, 0x04u, 0xD0u,
-    0x03u, 0x2Au, 0x07u, 0xD0u, 0x01u, 0x2Au, 0x15u, 0xD1u,
-    0x04u, 0xE0u, 0x02u, 0x02u, 0x42u, 0xEAu, 0x10u, 0x23u,
-    0x98u, 0xB2u, 0x10u, 0xBDu, 0x00u, 0xBAu, 0x10u, 0xBDu,
-    0x0Cu, 0x4Bu, 0x00u, 0xE0u, 0x0Cu, 0x4Bu, 0xD8u, 0x78u,
-    0x9Cu, 0x78u, 0x59u, 0x78u, 0x1Bu, 0x78u, 0x40u, 0xEAu,
-    0x03u, 0x60u, 0x40u, 0xEAu, 0x04u, 0x23u, 0x43u, 0xEAu,
-    0x01u, 0x40u, 0xE3u, 0xE7u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0xD2u, 0xFFu, 0x01u, 0x00u, 0xC1u, 0xFFu, 0x01u, 0x00u,
-    0xD6u, 0xFFu, 0x01u, 0x00u, 0xD4u, 0xFFu, 0x01u, 0x00u,
-    0xC5u, 0xFFu, 0x01u, 0x00u, 0xD8u, 0xFFu, 0x01u, 0x00u,
-    0xC9u, 0xFFu, 0x01u, 0x00u, 0x70u, 0xB5u, 0x02u, 0x20u,
-    0xFFu, 0xF7u, 0xB6u, 0xFFu, 0x06u, 0x46u, 0x03u, 0x20u,
-    0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x71u, 0x1Cu, 0x00u, 0xEBu,
-    0x01u, 0x26u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xACu, 0xFFu,
-    0x00u, 0x24u, 0x01u, 0x30u, 0x01u, 0x02u, 0x25u, 0x46u,
-    0xB1u, 0x42u, 0x09u, 0xD2u, 0x11u, 0xF8u, 0x01u, 0x0Bu,
-    0x42u, 0x1Eu, 0xD3u, 0xB2u, 0x04u, 0x19u, 0xFDu, 0x2Bu,
-    0x98u, 0xBFu, 0x01u, 0x25u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,
-    0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x0Fu, 0x49u,
-    0x42u, 0x1Cu, 0x13u, 0x02u, 0xDBu, 0x08u, 0x8Eu, 0x42u,
-    0x01u, 0xD0u, 0xF6u, 0x08u, 0x01u, 0xE0u, 0x4Fu, 0xF4u,
-    0x80u, 0x46u, 0xB3u, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,
-    0x90u, 0x41u, 0x08u, 0x78u, 0x01u, 0x33u, 0x02u, 0x19u,
-    0xD4u, 0xB2u, 0xF6u, 0xE7u, 0x05u, 0x48u, 0x64u, 0x42u,
-    0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u,
-    0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u,
-    0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u,
-    0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du,
-    0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u,
-    0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u,
-    0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u,
-    0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u,
+    0x00u, 0x47u, 0x10u, 0xB5u, 0x00u, 0x23u, 0x2Au, 0xB1u,
+    0x01u, 0x3Au, 0x44u, 0x18u, 0xA4u, 0x5Cu, 0x23u, 0x44u,
+    0xDBu, 0xB2u, 0xF8u, 0xE7u, 0x18u, 0x46u, 0x10u, 0xBDu,
+    0x01u, 0x38u, 0x09u, 0x28u, 0x42u, 0xD8u, 0xDFu, 0xE8u,
+    0x00u, 0xF0u, 0x05u, 0x0Bu, 0x11u, 0x17u, 0x1Du, 0x23u,
+    0x2Fu, 0x29u, 0x35u, 0x3Bu, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF5u, 0xE0u, 0x71u, 0x3Bu, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+    0xC1u, 0x11u, 0x38u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF2u, 0xC5u, 0x11u, 0x2Au, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+    0xC9u, 0x11u, 0x2Cu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF5u, 0xE8u, 0x71u, 0x23u, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+    0xD1u, 0x11u, 0x1Du, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF5u, 0xEBu, 0x71u, 0x12u, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+    0xE9u, 0x71u, 0x0Cu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+    0xFFu, 0x31u, 0x01u, 0xF5u, 0xEAu, 0x71u, 0x06u, 0xE0u,
+    0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+    0xECu, 0x71u, 0x08u, 0xE0u, 0x00u, 0x21u, 0x0Bu, 0x78u,
+    0x48u, 0x78u, 0x43u, 0xEAu, 0x00u, 0x20u, 0x70u, 0x47u,
+    0x08u, 0x78u, 0xC0u, 0xB2u, 0x70u, 0x47u, 0x0Bu, 0x78u,
+    0x4Au, 0x78u, 0x88u, 0x78u, 0x00u, 0x04u, 0x40u, 0xEAu,
+    0x02u, 0x20u, 0x18u, 0x43u, 0xCBu, 0x78u, 0x40u, 0xEAu,
+    0x03u, 0x60u, 0x70u, 0x47u, 0x10u, 0xB5u, 0x0Bu, 0x4Bu,
+    0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x02u, 0x80u, 0x2Au,
+    0x0Eu, 0xD1u, 0x00u, 0x24u, 0x1Cu, 0x70u, 0x02u, 0x20u,
+    0x21u, 0x46u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x38u, 0xB1u,
+    0x21u, 0x46u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0x94u, 0xFFu,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x84u, 0xBFu,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,
+    0xF8u, 0xB5u, 0x05u, 0x46u, 0x29u, 0x46u, 0x03u, 0x20u,
+    0xFFu, 0xF7u, 0x86u, 0xFFu, 0x29u, 0x46u, 0x07u, 0x46u,
+    0x04u, 0x20u, 0xFFu, 0xF7u, 0x81u, 0xFFu, 0x01u, 0x37u,
+    0x00u, 0xEBu, 0x07u, 0x27u, 0x29u, 0x46u, 0x03u, 0x20u,
+    0xFFu, 0xF7u, 0x7Au, 0xFFu, 0x00u, 0x24u, 0x01u, 0x30u,
+    0x00u, 0x02u, 0x26u, 0x46u, 0xB8u, 0x42u, 0x09u, 0xD2u,
+    0x10u, 0xF8u, 0x01u, 0x3Bu, 0x5Au, 0x1Eu, 0xD2u, 0xB2u,
+    0xFDu, 0x2Au, 0x1Cu, 0x44u, 0x98u, 0xBFu, 0x01u, 0x26u,
+    0xE4u, 0xB2u, 0xF3u, 0xE7u, 0x03u, 0x20u, 0x29u, 0x46u,
+    0xFFu, 0xF7u, 0x66u, 0xFFu, 0x11u, 0x4Au, 0x01u, 0x30u,
+    0x97u, 0x42u, 0x4Fu, 0xEAu, 0x00u, 0x23u, 0x4Fu, 0xEAu,
+    0xD3u, 0x03u, 0x14u, 0xBFu, 0xFFu, 0x08u, 0x4Fu, 0xF4u,
+    0x80u, 0x47u, 0xBBu, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,
+    0x90u, 0x42u, 0x12u, 0x78u, 0x01u, 0x33u, 0x14u, 0x44u,
+    0xE4u, 0xB2u, 0xF6u, 0xE7u, 0x01u, 0x20u, 0x29u, 0x46u,
+    0xFFu, 0xF7u, 0x4Eu, 0xFFu, 0x64u, 0x42u, 0xE4u, 0xB2u,
+    0x84u, 0x42u, 0x04u, 0xD1u, 0x00u, 0x2Eu, 0x14u, 0xBFu,
+    0x00u, 0x20u, 0x06u, 0x20u, 0xF8u, 0xBDu, 0x06u, 0x20u,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0xC0u, 0xFFu, 0x01u, 0x00u,
+    0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x1Bu, 0x7Du,
+    0x80u, 0x46u, 0x00u, 0xF0u, 0x15u, 0xFAu, 0x10u, 0xB1u,
+    0x00u, 0x20u, 0x00u, 0xF0u, 0xE1u, 0xFAu, 0x00u, 0xF0u,
+    0x3Bu, 0xFCu, 0x62u, 0xB6u, 0x00u, 0x26u, 0x4Fu, 0xF0u,
+    0x0Au, 0x09u, 0x35u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
+    0x14u, 0xBFu, 0x43u, 0x46u, 0xFFu, 0x23u, 0x04u, 0xA8u,
     0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u,
-    0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,
+    0x5Bu, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,
     0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u,
     0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u,
-    0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u,
+    0xE8u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x78u, 0xD1u,
     0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u,
-    0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu,
-    0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u,
-    0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu,
-    0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u,
-    0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u,
-    0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u,
-    0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,
-    0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu,
-    0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,
-    0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u,
-    0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u,
-    0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du,
-    0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u,
-    0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u,
-    0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u,
-    0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u,
-    0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u,
-    0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u,
-    0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u,
-    0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u,
-    0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu,
-    0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u,
-    0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u,
-    0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u,
-    0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u,
-    0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u,
-    0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u,
-    0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
-    0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u,
-    0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u,
-    0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u,
-    0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u,
-    0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu,
-    0xB5u, 0x06u, 0x00u, 0x00u, 0xD9u, 0x05u, 0x00u, 0x00u,
-    0x6Fu, 0x08u, 0x00u, 0x00u, 0xD3u, 0x06u, 0x00u, 0x00u,
-    0x85u, 0x07u, 0x00u, 0x00u, 0x6Fu, 0x08u, 0x00u, 0x00u,
-    0x8Bu, 0x07u, 0x00u, 0x00u, 0xA9u, 0x07u, 0x00u, 0x00u,
-    0xD3u, 0x06u, 0x00u, 0x00u, 0xC3u, 0x07u, 0x00u, 0x00u,
-    0x4Fu, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
-    0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u,
-    0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u,
-    0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u,
-    0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,
-    0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u,
-    0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu,
-    0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u,
-    0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u,
-    0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
-    0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u,
-    0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u,
-    0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu,
-    0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u,
-    0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u,
-    0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u,
-    0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,
-    0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u,
-    0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u,
-    0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u,
-    0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u,
-    0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu,
-    0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u,
-    0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u,
-    0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u,
-    0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u,
-    0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,
-    0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u,
-    0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u,
-    0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u,
-    0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u,
-    0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu,
-    0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u,
-    0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u,
-    0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du,
-    0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u,
-    0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au,
-    0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u,
-    0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u,
-    0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u,
-    0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u,
-    0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u,
-    0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u,
-    0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu,
-    0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu,
-    0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u,
-    0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u,
-    0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du,
-    0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u,
-    0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u,
-    0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u,
-    0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u,
-    0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u,
-    0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u,
-    0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u,
-    0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u,
-    0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u,
-    0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u,
-    0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u,
-    0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u,
-    0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,
-    0xF0u, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,
-    0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,
-    0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u,
-    0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u,
-    0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u,
-    0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,
-    0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,
-    0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u,
-    0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u,
-    0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u,
-    0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,
-    0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu,
-    0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,
-    0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,
-    0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,
-    0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,
-    0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
-    0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u,
-    0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,
-    0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,
+    0x89u, 0x81u, 0x9Du, 0xF8u, 0x10u, 0x30u, 0x01u, 0x2Bu,
+    0x40u, 0xF0u, 0x84u, 0x81u, 0x9Du, 0xF8u, 0x12u, 0x30u,
+    0x9Du, 0xF8u, 0x13u, 0x40u, 0x43u, 0xEAu, 0x04u, 0x24u,
+    0xE7u, 0x1Du, 0x04u, 0xABu, 0x23u, 0x44u, 0x97u, 0x42u,
+    0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x74u, 0x81u,
+    0x9Bu, 0x79u, 0x17u, 0x2Bu, 0x40u, 0xF0u, 0x72u, 0x81u,
+    0x23u, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,
+    0x0Du, 0xF1u, 0x0Fu, 0x07u, 0xFFu, 0x5Cu, 0x01u, 0x3Bu,
+    0x3Au, 0x44u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,
+    0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x23u, 0x92u, 0xB2u,
+    0x93u, 0x42u, 0x40u, 0xF0u, 0x61u, 0x81u, 0x51u, 0xE0u,
+    0x00u, 0x2Eu, 0x00u, 0xF0u, 0x5Bu, 0x81u, 0x01u, 0x2Cu,
+    0x40u, 0xF0u, 0x58u, 0x81u, 0x01u, 0x2Fu, 0x00u, 0xF2u,
+    0x55u, 0x81u, 0xB2u, 0x4Bu, 0x1Bu, 0x68u, 0x1Bu, 0x68u,
+    0xC3u, 0xF3u, 0x07u, 0x42u, 0x97u, 0x42u, 0x73u, 0xD1u,
+    0xC3u, 0xF3u, 0x07u, 0x23u, 0x8Du, 0xF8u, 0x14u, 0x30u,
+    0x1Bu, 0x0Au, 0x8Du, 0xF8u, 0x15u, 0x30u, 0x00u, 0x24u,
+    0xFFu, 0x23u, 0x8Du, 0xF8u, 0x16u, 0x30u, 0x8Du, 0xF8u,
+    0x17u, 0x40u, 0x04u, 0x21u, 0x01u, 0x23u, 0x8Du, 0xF8u,
+    0x10u, 0x30u, 0x00u, 0x22u, 0x0Bu, 0x1Du, 0xADu, 0xF8u,
+    0x06u, 0x10u, 0x8Du, 0xF8u, 0x11u, 0x40u, 0x8Du, 0xF8u,
+    0x12u, 0x10u, 0x8Du, 0xF8u, 0x13u, 0x20u, 0x9Bu, 0xB2u,
+    0x0Du, 0xF1u, 0x0Fu, 0x00u, 0xC0u, 0x5Cu, 0x01u, 0x3Bu,
+    0x02u, 0x44u, 0x9Bu, 0xB2u, 0x92u, 0xB2u, 0x00u, 0x2Bu,
+    0xF6u, 0xD1u, 0x52u, 0x42u, 0x92u, 0xB2u, 0x05u, 0xABu,
+    0x5Au, 0x54u, 0x12u, 0x0Au, 0x0Du, 0xF1u, 0x15u, 0x03u,
+    0x5Au, 0x54u, 0x17u, 0x22u, 0x0Du, 0xF1u, 0x16u, 0x03u,
+    0x5Au, 0x54u, 0x07u, 0x31u, 0x04u, 0xA8u, 0x89u, 0xB2u,
+    0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u, 0x00u, 0xF0u,
+    0xB2u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x3Fu, 0xF4u,
+    0x69u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x19u, 0x81u,
+    0x01u, 0x26u, 0x63u, 0xE7u, 0x9Du, 0xF8u, 0x11u, 0x20u,
+    0x9Du, 0xF8u, 0x14u, 0x70u, 0xA2u, 0xF1u, 0x31u, 0x03u,
+    0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xFEu, 0x80u, 0x01u, 0xA1u,
+    0x51u, 0xF8u, 0x23u, 0xF0u, 0x31u, 0x07u, 0x00u, 0x00u,
+    0x49u, 0x06u, 0x00u, 0x00u, 0xFBu, 0x08u, 0x00u, 0x00u,
+    0x5Bu, 0x07u, 0x00u, 0x00u, 0x0Bu, 0x08u, 0x00u, 0x00u,
+    0xFBu, 0x08u, 0x00u, 0x00u, 0x11u, 0x08u, 0x00u, 0x00u,
+    0x2Fu, 0x08u, 0x00u, 0x00u, 0x5Bu, 0x07u, 0x00u, 0x00u,
+    0x4Bu, 0x08u, 0x00u, 0x00u, 0xD9u, 0x08u, 0x00u, 0x00u,
+    0x00u, 0x2Eu, 0x00u, 0xF0u, 0xE7u, 0x80u, 0x00u, 0x2Cu,
+    0x40u, 0xF0u, 0xE4u, 0x80u, 0x20u, 0x46u, 0xFFu, 0xF7u,
+    0xDBu, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x00u, 0x38u, 0xBFu,
+    0x00u, 0x20u, 0x8Du, 0xF8u, 0x14u, 0x00u, 0xC1u, 0xE0u,
+    0x8Cu, 0xBFu, 0x00u, 0x23u, 0x4Fu, 0xF4u, 0x80u, 0x73u,
+    0x88u, 0xE7u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,
+    0x00u, 0xF0u, 0xD0u, 0x80u, 0x03u, 0x2Cu, 0x40u, 0xF0u,
+    0xCDu, 0x80u, 0xA7u, 0xF1u, 0x40u, 0x03u, 0x3Fu, 0x2Bu,
+    0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x75u, 0x10u, 0x25u,
+    0x4Fu, 0xA8u, 0x00u, 0x21u, 0x2Au, 0x46u, 0x01u, 0xF0u,
+    0xA4u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
+    0xBDu, 0x80u, 0x02u, 0x2Cu, 0x40u, 0xF2u, 0xBAu, 0x80u,
+    0x03u, 0x3Cu, 0x4Fu, 0xA8u, 0x28u, 0x44u, 0x0Du, 0xF1u,
+    0x17u, 0x01u, 0x22u, 0x46u, 0x01u, 0xF0u, 0x8Cu, 0xFCu,
+    0xA7u, 0xF1u, 0x40u, 0x03u, 0x25u, 0x44u, 0x3Fu, 0x2Bu,
+    0xADu, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xB6u, 0xF9u,
+    0x10u, 0x23u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x73u,
+    0x9Du, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,
+    0x16u, 0x10u, 0x9Du, 0xF8u, 0x15u, 0x30u, 0x3Fu, 0x2Fu,
+    0x43u, 0xEAu, 0x01u, 0x21u, 0x0Fu, 0xD8u, 0x55u, 0x4Bu,
+    0x01u, 0xEBu, 0x07u, 0x22u, 0x1Bu, 0x68u, 0x92u, 0xB2u,
+    0x1Bu, 0x68u, 0xC3u, 0xF3u, 0x0Fu, 0x20u, 0x13u, 0xF0u,
+    0xFFu, 0x0Fu, 0x1Cu, 0xBFu, 0x01u, 0x30u, 0x80u, 0xB2u,
+    0x82u, 0x42u, 0xC0u, 0xF0u, 0x82u, 0x80u, 0x2Bu, 0x46u,
+    0x4Fu, 0xAAu, 0x38u, 0x46u, 0x00u, 0xF0u, 0x30u, 0xF9u,
+    0x00u, 0x28u, 0x0Cu, 0xBFu, 0x00u, 0x24u, 0x0Au, 0x24u,
+    0x01u, 0x26u, 0x00u, 0xF0u, 0xD7u, 0xF9u, 0x00u, 0x25u,
+    0x78u, 0xE0u, 0x00u, 0x2Eu, 0x7Au, 0xD0u, 0x7Du, 0xE0u,
+    0x00u, 0x2Eu, 0x77u, 0xD0u, 0x2Fu, 0x19u, 0xB7u, 0xF5u,
+    0x96u, 0x7Fu, 0x71u, 0xD8u, 0x4Fu, 0xA8u, 0x28u, 0x44u,
+    0x22u, 0x46u, 0x05u, 0xA9u, 0x01u, 0xF0u, 0x48u, 0xFCu,
+    0xBDu, 0xB2u, 0x00u, 0x24u, 0x66u, 0xE0u, 0x00u, 0x2Cu,
+    0x68u, 0xD1u, 0x3Du, 0x4Au, 0x02u, 0xABu, 0x92u, 0xE8u,
+    0x03u, 0x00u, 0x05u, 0xAAu, 0x83u, 0xE8u, 0x03u, 0x00u,
+    0x82u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x21u,
+    0x1Cu, 0xE7u, 0x00u, 0x2Eu, 0x5Au, 0xD0u, 0x03u, 0x2Cu,
+    0x58u, 0xD1u, 0x9Du, 0xF8u, 0x15u, 0x30u, 0x9Du, 0xF8u,
+    0x16u, 0xA0u, 0x43u, 0xEAu, 0x0Au, 0x2Au, 0xA7u, 0xF1u,
+    0x40u, 0x03u, 0x3Fu, 0x2Bu, 0x07u, 0xD8u, 0x31u, 0x48u,
+    0x4Fu, 0xEAu, 0x0Au, 0x11u, 0x10u, 0x22u, 0xFFu, 0xF7u,
+    0xC4u, 0xFDu, 0x04u, 0x46u, 0x2Au, 0xE0u, 0x4Fu, 0xEAu,
+    0x07u, 0x2Bu, 0x0Au, 0xEBu, 0x0Bu, 0x01u, 0x00u, 0x20u,
+    0x09u, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0xFFu, 0xF7u,
+    0xB8u, 0xFDu, 0x3Fu, 0x2Fu, 0x04u, 0x46u, 0x1Du, 0xD8u,
+    0x0Bu, 0xF1u, 0x10u, 0x7Bu, 0xD3u, 0x44u, 0x4Fu, 0xEAu,
+    0x4Bu, 0x1Bu, 0x00u, 0x23u, 0x13u, 0xF8u, 0x0Bu, 0x20u,
+    0x01u, 0x33u, 0x14u, 0x44u, 0x20u, 0x2Bu, 0xE4u, 0xB2u,
+    0xF8u, 0xD1u, 0x01u, 0x2Fu, 0x0Eu, 0xD1u, 0xBAu, 0xF1u,
+    0xFFu, 0x0Fu, 0x0Bu, 0xD1u, 0x00u, 0x21u, 0x05u, 0x20u,
+    0xFFu, 0xF7u, 0xAAu, 0xFDu, 0x20u, 0x1Au, 0xC4u, 0xB2u,
+    0x00u, 0x21u, 0x06u, 0x20u, 0xFFu, 0xF7u, 0xA4u, 0xFDu,
+    0x20u, 0x1Au, 0xC4u, 0xB2u, 0x64u, 0x42u, 0x8Du, 0xF8u,
+    0x14u, 0x40u, 0x00u, 0x24u, 0x01u, 0x21u, 0xD5u, 0xE6u,
+    0x00u, 0x20u, 0xFFu, 0xF7u, 0x0Du, 0xFEu, 0x10u, 0xB9u,
+    0x13u, 0x4Bu, 0x80u, 0x22u, 0x1Au, 0x70u, 0x00u, 0xF0u,
+    0x41u, 0xF9u, 0x0Bu, 0xE0u, 0x01u, 0x26u, 0x00u, 0x25u,
+    0x06u, 0xE0u, 0x01u, 0x26u, 0x00u, 0x25u, 0x0Au, 0x24u,
+    0x00u, 0xE0u, 0x05u, 0x24u, 0x00u, 0x21u, 0xC1u, 0xE6u,
+    0x03u, 0x24u, 0xFBu, 0xE7u, 0x04u, 0x24u, 0xF9u, 0xE7u,
+    0x08u, 0x24u, 0xF7u, 0xE7u, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
+    0x01u, 0xD1u, 0x45u, 0x46u, 0x4Eu, 0xE6u, 0x00u, 0x25u,
+    0xE6u, 0xE6u, 0x0Du, 0xF5u, 0x1Bu, 0x7Du, 0xBDu, 0xE8u,
+    0xF0u, 0x8Fu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
+    0xB0u, 0x21u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x40u,
+    0xFAu, 0x46u, 0x00u, 0x40u, 0x70u, 0xB5u, 0x00u, 0x20u,
+    0xFFu, 0xF7u, 0xDEu, 0xFDu, 0x15u, 0x4Du, 0x00u, 0x28u,
+    0x2Bu, 0x68u, 0x4Fu, 0xF0u, 0x00u, 0x00u, 0x1Cu, 0x68u,
+    0x01u, 0x46u, 0x22u, 0x46u, 0x0Cu, 0xBFu, 0x00u, 0x26u,
+    0x06u, 0x26u, 0xFFu, 0xF7u, 0x52u, 0xFDu, 0x6Bu, 0x68u,
+    0x1Bu, 0x78u, 0x18u, 0x1Au, 0x00u, 0xF0u, 0xFFu, 0x00u,
+    0x98u, 0x42u, 0x00u, 0xD1u, 0x14u, 0xB9u, 0x00u, 0x20u,
+    0x00u, 0xF0u, 0xFEu, 0xF8u, 0x0Au, 0x4Cu, 0x23u, 0x78u,
+    0x03u, 0xF0u, 0xC0u, 0x03u, 0x40u, 0x2Bu, 0x00u, 0xD0u,
+    0x1Eu, 0xB1u, 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u,
+    0x07u, 0xFEu, 0x14u, 0x20u, 0xFFu, 0xF7u, 0x04u, 0xFEu,
+    0x80u, 0x23u, 0x23u, 0x70u, 0xBDu, 0xE8u, 0x70u, 0x40u,
+    0x00u, 0xF0u, 0xECu, 0xB8u, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
     0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u,
     0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u,
     0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u,
     0x72u, 0xB6u, 0x70u, 0x47u, 0x80u, 0xF3u, 0x10u, 0x88u,
     0x70u, 0x47u, 0x00u, 0xBFu, 0xAFu, 0xF3u, 0x00u, 0x80u,
-    0x01u, 0x20u, 0x10u, 0xB5u, 0x00u, 0xF0u, 0x60u, 0xF9u,
-    0x07u, 0x28u, 0x09u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
-    0x17u, 0xE0u, 0x0Eu, 0x4Bu, 0x18u, 0x78u, 0x00u, 0xF0u,
-    0x02u, 0x01u, 0xCAu, 0xB2u, 0x00u, 0x2Au, 0xF5u, 0xD1u,
-    0x02u, 0x21u, 0x0Bu, 0x48u, 0x00u, 0xF0u, 0xECu, 0xF8u,
-    0x02u, 0x28u, 0xF2u, 0xD1u, 0x07u, 0x4Cu, 0x23u, 0x78u,
-    0x03u, 0xF0u, 0x02u, 0x00u, 0xC1u, 0xB2u, 0x19u, 0xB9u,
-    0x01u, 0x20u, 0x00u, 0xF0u, 0xAFu, 0xF8u, 0xF5u, 0xE7u,
-    0x00u, 0x24u, 0x00u, 0xF0u, 0x7Fu, 0xF9u, 0x20u, 0x46u,
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
-    0x57u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x00u, 0xF0u,
-    0xC1u, 0xF8u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x58u, 0xB9u,
-    0xFFu, 0xF7u, 0xCEu, 0xFFu, 0x48u, 0xB9u, 0x00u, 0xF0u,
-    0xB9u, 0xF8u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x18u, 0xB9u,
-    0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xC4u, 0xBFu,
-    0x04u, 0x20u, 0x08u, 0xBDu, 0x38u, 0xB5u, 0x04u, 0x46u,
-    0x00u, 0xF0u, 0xACu, 0xF8u, 0x4Cu, 0xB1u, 0x00u, 0xF0u,
-    0x3Du, 0xF9u, 0x05u, 0x46u, 0x38u, 0xB9u, 0x05u, 0x4Bu,
-    0x1Cu, 0x60u, 0x00u, 0xF0u, 0x57u, 0xF9u, 0x28u, 0x46u,
-    0x38u, 0xBDu, 0x01u, 0x20u, 0x38u, 0xBDu, 0x04u, 0x20u,
-    0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,
-    0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u, 0x17u, 0x46u,
-    0x1Cu, 0x46u, 0x00u, 0xF0u, 0x27u, 0xF9u, 0xF0u, 0xB9u,
-    0x22u, 0x46u, 0x28u, 0x46u, 0x39u, 0x46u, 0x00u, 0xF0u,
-    0xB9u, 0xF8u, 0x07u, 0x28u, 0x04u, 0x46u, 0x13u, 0xD1u,
-    0x1Du, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u,
-    0xC1u, 0xB2u, 0x19u, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u,
-    0x61u, 0xF8u, 0xF5u, 0xE7u, 0x1Cu, 0x78u, 0x04u, 0xF0u,
-    0x02u, 0x02u, 0xD0u, 0xB2u, 0x10u, 0xB1u, 0x1Bu, 0x78u,
-    0x9Bu, 0x08u, 0x06u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
-    0x00u, 0xF0u, 0x28u, 0xF9u, 0x22u, 0xE0u, 0x04u, 0x24u,
-    0x20u, 0xE0u, 0x12u, 0x4Cu, 0x28u, 0x46u, 0x22u, 0x78u,
-    0x63u, 0x78u, 0x31u, 0x46u, 0x00u, 0xF0u, 0xBCu, 0xF8u,
-    0x07u, 0x28u, 0x04u, 0x46u, 0xF0u, 0xD1u, 0x0Cu, 0x49u,
-    0x0Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u, 0xC3u, 0xB2u,
-    0x1Bu, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF8u,
-    0xF5u, 0xE7u, 0x0Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x02u,
-    0xD0u, 0xB2u, 0x00u, 0x28u, 0xDEu, 0xD0u, 0x09u, 0x78u,
-    0x8Bu, 0x08u, 0x14u, 0xBFu, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
-    0x00u, 0x24u, 0xD9u, 0xE7u, 0x20u, 0x46u, 0xF8u, 0xBDu,
-    0x22u, 0x47u, 0x00u, 0x40u, 0x57u, 0xC1u, 0xFFu, 0x1Fu,
-    0x04u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u, 0x10u, 0x00u,
-    0x18u, 0x70u, 0x19u, 0x7Cu, 0x41u, 0xF0u, 0x10u, 0x02u,
-    0x1Au, 0x74u, 0x70u, 0x47u, 0xACu, 0x43u, 0x00u, 0x40u,
+    0x38u, 0xB5u, 0x00u, 0xF0u, 0x2Du, 0xF9u, 0x00u, 0xF0u,
+    0xD9u, 0xF9u, 0x00u, 0x28u, 0x38u, 0xD1u, 0x00u, 0xF0u,
+    0x0Fu, 0xFAu, 0x07u, 0x28u, 0x04u, 0x46u, 0x0Fu, 0xD1u,
+    0x1Bu, 0x4Bu, 0x1Au, 0x78u, 0x90u, 0x07u, 0x03u, 0xD4u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0xDBu, 0xF8u, 0xF7u, 0xE7u,
+    0x1Au, 0x78u, 0x91u, 0x07u, 0x04u, 0xD5u, 0x1Bu, 0x78u,
+    0x9Bu, 0x08u, 0x14u, 0xBFu, 0x07u, 0x24u, 0x00u, 0x24u,
+    0x00u, 0xF0u, 0xE0u, 0xF9u, 0x0Cu, 0xBBu, 0x00u, 0xF0u,
+    0x0Fu, 0xF9u, 0x00u, 0xF0u, 0xBBu, 0xF9u, 0xD8u, 0xB9u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0x9Du, 0xF9u, 0x07u, 0x28u,
+    0x05u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u, 0x10u, 0xE0u,
+    0x2Bu, 0x78u, 0x9Bu, 0x07u, 0xF9u, 0xD4u, 0x0Bu, 0x48u,
+    0x02u, 0x21u, 0x00u, 0xF0u, 0x0Fu, 0xF9u, 0x02u, 0x28u,
+    0x07u, 0x4Du, 0xF5u, 0xD1u, 0x2Bu, 0x78u, 0x9Au, 0x07u,
+    0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0xB2u, 0xF8u,
+    0xF8u, 0xE7u, 0x00u, 0xF0u, 0xBFu, 0xF9u, 0x00u, 0xE0u,
+    0x04u, 0x24u, 0x20u, 0x46u, 0x38u, 0xBDu, 0x00u, 0xBFu,
+    0x22u, 0x47u, 0x00u, 0x40u, 0x50u, 0xC1u, 0xFFu, 0x1Fu,
+    0x41u, 0x28u, 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u,
+    0x17u, 0x46u, 0x1Cu, 0x46u, 0x0Au, 0xD8u, 0xC1u, 0x1Eu,
+    0x3Cu, 0x29u, 0x8Cu, 0xBFu, 0x00u, 0x21u, 0x01u, 0x21u,
+    0x3Fu, 0x28u, 0x04u, 0xD8u, 0xB6u, 0xF5u, 0x80u, 0x7Fu,
+    0x29u, 0xD8u, 0x05u, 0xE0u, 0x01u, 0x21u, 0x81u, 0x2Eu,
+    0x28u, 0xBFu, 0x01u, 0x21u, 0x10u, 0x2Cu, 0x22u, 0xD1u,
+    0x0Fu, 0xB3u, 0x01u, 0xBBu, 0x00u, 0xF0u, 0x7Au, 0xF9u,
+    0xF8u, 0xB9u, 0x23u, 0x46u, 0x28u, 0x46u, 0x31u, 0x46u,
+    0x3Au, 0x46u, 0x00u, 0xF0u, 0xF1u, 0xF8u, 0x07u, 0x28u,
+    0x04u, 0x46u, 0x11u, 0xD1u, 0x1Bu, 0x4Bu, 0x1Au, 0x78u,
+    0x1Fu, 0x46u, 0x12u, 0xF0u, 0x02u, 0x0Fu, 0x03u, 0xD1u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0x77u, 0xF8u, 0xF5u, 0xE7u,
+    0x1Au, 0x78u, 0x90u, 0x07u, 0x02u, 0xD5u, 0x1Bu, 0x78u,
+    0x9Bu, 0x08u, 0x08u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
+    0x00u, 0xF0u, 0x7Cu, 0xF9u, 0x1Fu, 0xE0u, 0x01u, 0x24u,
+    0x1Du, 0xE0u, 0x04u, 0x24u, 0x1Bu, 0xE0u, 0x10u, 0x4Bu,
+    0x28u, 0x46u, 0x1Au, 0x78u, 0x31u, 0x46u, 0x5Bu, 0x78u,
+    0x00u, 0xF0u, 0x16u, 0xF9u, 0x07u, 0x28u, 0x04u, 0x46u,
+    0xEEu, 0xD1u, 0x3Au, 0x78u, 0x09u, 0x4Bu, 0x91u, 0x07u,
+    0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x56u, 0xF8u,
+    0xF7u, 0xE7u, 0x1Au, 0x78u, 0x92u, 0x07u, 0xE1u, 0xD5u,
+    0x1Bu, 0x78u, 0x9Bu, 0x08u, 0x0Cu, 0xBFu, 0x00u, 0x24u,
+    0x6Fu, 0xF0u, 0x00u, 0x04u, 0xDCu, 0xE7u, 0x20u, 0x46u,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
+    0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,
+    0x49u, 0xFFu, 0x0Fu, 0x4Bu, 0x1Au, 0x78u, 0x0Cu, 0x33u,
+    0x42u, 0xF0u, 0x08u, 0x02u, 0x03u, 0xF8u, 0x0Cu, 0x2Cu,
+    0x1Au, 0x79u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x71u,
+    0xC8u, 0x22u, 0x83u, 0xF8u, 0x55u, 0x23u, 0x1Au, 0x78u,
+    0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x70u, 0x1Au, 0x7Cu,
+    0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x74u, 0x05u, 0x4Bu,
+    0x1Bu, 0x78u, 0x9Bu, 0x06u, 0xFBu, 0xD5u, 0xBDu, 0xE8u,
+    0x08u, 0x40u, 0xFFu, 0xF7u, 0x2Fu, 0xBFu, 0x00u, 0xBFu,
+    0xA0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x40u,
     0x01u, 0xBEu, 0x70u, 0x47u, 0x02u, 0x4Bu, 0x1Au, 0x78u,
-    0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u, 0x70u, 0x47u,
+    0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,
     0xF6u, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x04u, 0x46u,
     0xB4u, 0xF5u, 0x00u, 0x4Fu, 0x06u, 0x4Bu, 0x05u, 0xD9u,
-    0x18u, 0x68u, 0xFFu, 0xF7u, 0x29u, 0xFFu, 0xA4u, 0xF5u,
+    0x18u, 0x68u, 0xFFu, 0xF7u, 0x09u, 0xFFu, 0xA4u, 0xF5u,
     0x00u, 0x44u, 0xF5u, 0xE7u, 0x58u, 0x68u, 0x60u, 0x43u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x20u, 0xBFu,
-    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x19u, 0x7Au,
-    0x48u, 0x43u, 0xFFu, 0xF7u, 0x19u, 0xBFu, 0x00u, 0xBFu,
-    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x00u, 0xF0u,
-    0x1Fu, 0x00u, 0x1Bu, 0x68u, 0x00u, 0xF1u, 0x10u, 0x02u,
-    0x53u, 0xF8u, 0x22u, 0x00u, 0x43u, 0xF8u, 0x22u, 0x10u,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x08u, 0xEDu, 0x00u, 0xE0u,
-    0x00u, 0xF0u, 0x1Fu, 0x00u, 0x00u, 0xF1u, 0x60u, 0x43u,
-    0x49u, 0x01u, 0x03u, 0xF5u, 0x64u, 0x42u, 0xC8u, 0xB2u,
-    0x10u, 0x70u, 0x70u, 0x47u, 0x08u, 0xB5u, 0xFFu, 0xF7u,
-    0x05u, 0xFFu, 0x06u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,
-    0x08u, 0x01u, 0x19u, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u,
-    0x08u, 0x01u, 0x19u, 0x74u, 0xBDu, 0xE8u, 0x08u, 0x40u,
-    0xFFu, 0xF7u, 0xFCu, 0xBEu, 0xA0u, 0x43u, 0x00u, 0x40u,
-    0x70u, 0xB5u, 0x06u, 0x46u, 0x0Du, 0x46u, 0x00u, 0x24u,
-    0xE3u, 0xB2u, 0xABu, 0x42u, 0x0Cu, 0xD2u, 0x07u, 0x48u,
-    0x01u, 0x78u, 0xCBu, 0x07u, 0x03u, 0xD4u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0xC0u, 0xFFu, 0xF7u, 0xE7u, 0x04u, 0x4Au,
-    0x13u, 0x78u, 0x33u, 0x55u, 0x01u, 0x34u, 0xEFu, 0xE7u,
-    0x28u, 0x46u, 0x70u, 0xBDu, 0x22u, 0x47u, 0x00u, 0x40u,
-    0x20u, 0x47u, 0x00u, 0x40u, 0x30u, 0xB5u, 0x10u, 0x4Bu,
-    0x1Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x04u, 0xE4u, 0xB2u,
-    0xACu, 0xB1u, 0x0Eu, 0x4Cu, 0xB6u, 0x25u, 0x25u, 0x70u,
-    0xD5u, 0x25u, 0x25u, 0x70u, 0x02u, 0x25u, 0x25u, 0x70u,
-    0x1Bu, 0x78u, 0x2Bu, 0x40u, 0xDBu, 0xB2u, 0x63u, 0xB9u,
-    0x20u, 0x70u, 0x98u, 0xB2u, 0x90u, 0x42u, 0x04u, 0xD2u,
-    0xCCu, 0x5Cu, 0x06u, 0x48u, 0x01u, 0x33u, 0x04u, 0x70u,
-    0xF7u, 0xE7u, 0x07u, 0x20u, 0x30u, 0xBDu, 0x04u, 0x20u,
-    0x30u, 0xBDu, 0x09u, 0x20u, 0x30u, 0xBDu, 0x00u, 0xBFu,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x00u, 0xBFu,
+    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x1Bu, 0x7Au,
+    0x58u, 0x43u, 0xFFu, 0xF7u, 0xF9u, 0xBEu, 0x00u, 0xBFu,
+    0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,
+    0xFDu, 0xFEu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+    0x00u, 0xBFu, 0x06u, 0x4Bu, 0x1Au, 0x88u, 0x92u, 0xB2u,
+    0x42u, 0xF0u, 0x04u, 0x02u, 0x1Au, 0x80u, 0x1Bu, 0x88u,
+    0xBFu, 0xF3u, 0x6Fu, 0x8Fu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+    0xFFu, 0xF7u, 0xE4u, 0xBEu, 0x00u, 0x48u, 0x00u, 0x40u,
+    0x05u, 0x4Bu, 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x1Bu, 0x68u,
+    0x00u, 0xF1u, 0x10u, 0x02u, 0x53u, 0xF8u, 0x22u, 0x00u,
+    0x43u, 0xF8u, 0x22u, 0x10u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xF0u, 0x1Fu, 0x00u,
+    0x00u, 0xF1u, 0x60u, 0x40u, 0x49u, 0x01u, 0x00u, 0xF5u,
+    0x64u, 0x40u, 0xC9u, 0xB2u, 0x01u, 0x70u, 0x70u, 0x47u,
+    0x08u, 0xB5u, 0xFFu, 0xF7u, 0xC3u, 0xFEu, 0x06u, 0x4Bu,
+    0x1Au, 0x78u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x70u,
+    0x1Au, 0x7Cu, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x74u,
+    0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xBAu, 0xBEu,
+    0xA0u, 0x43u, 0x00u, 0x40u, 0x70u, 0xB5u, 0x06u, 0x46u,
+    0x0Du, 0x46u, 0x00u, 0x24u, 0xE3u, 0xB2u, 0xABu, 0x42u,
+    0x0Cu, 0xD2u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0x07u,
+    0x03u, 0xD4u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x9Eu, 0xFFu,
+    0xF7u, 0xE7u, 0x04u, 0x4Bu, 0x1Bu, 0x78u, 0x33u, 0x55u,
+    0x01u, 0x34u, 0xEFu, 0xE7u, 0x28u, 0x46u, 0x70u, 0xBDu,
+    0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
+    0xF0u, 0xB5u, 0x21u, 0x4Du, 0x2Cu, 0x78u, 0xA4u, 0x07u,
+    0x39u, 0xD5u, 0x20u, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,
+    0xD5u, 0x26u, 0x26u, 0x70u, 0x02u, 0x26u, 0x26u, 0x70u,
+    0x2Eu, 0x78u, 0x06u, 0xF0u, 0x02u, 0x06u, 0x06u, 0xF0u,
+    0xFFu, 0x05u, 0x76u, 0xBBu, 0x20u, 0x2Bu, 0x20u, 0x70u,
+    0x01u, 0xD0u, 0x00u, 0x25u, 0x0Cu, 0xE0u, 0x3Fu, 0x28u,
+    0xFBu, 0xD8u, 0x01u, 0xEBu, 0x00u, 0x27u, 0x3Fu, 0x02u,
+    0xEEu, 0x5Du, 0x01u, 0x35u, 0xF6u, 0xB2u, 0xB5u, 0xF5u,
+    0x80u, 0x7Fu, 0x26u, 0x70u, 0xF8u, 0xD1u, 0xF0u, 0xE7u,
+    0xAEu, 0xB2u, 0x9Eu, 0x42u, 0x03u, 0xD2u, 0x56u, 0x5Du,
+    0x01u, 0x35u, 0x26u, 0x70u, 0xF8u, 0xE7u, 0xB3u, 0xF5u,
+    0x80u, 0x7Fu, 0x01u, 0xD0u, 0x07u, 0x20u, 0xF0u, 0xBDu,
+    0x3Fu, 0x28u, 0xFBu, 0xD8u, 0x00u, 0xF5u, 0x10u, 0x30u,
+    0x01u, 0xEBu, 0x00u, 0x21u, 0x49u, 0x01u, 0x00u, 0x23u,
+    0x5Au, 0x5Cu, 0x01u, 0x33u, 0xD2u, 0xB2u, 0x20u, 0x2Bu,
+    0x22u, 0x70u, 0xF9u, 0xD1u, 0xEEu, 0xE7u, 0x04u, 0x20u,
+    0xF0u, 0xBDu, 0x09u, 0x20u, 0xF0u, 0xBDu, 0x00u, 0xBFu,
     0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
-    0x70u, 0xB5u, 0x0Fu, 0x4Du, 0x2Cu, 0x78u, 0x04u, 0xF0u,
-    0x02u, 0x04u, 0xE4u, 0xB2u, 0xA4u, 0xB1u, 0x0Du, 0x4Cu,
-    0xB6u, 0x26u, 0x26u, 0x70u, 0xD8u, 0x26u, 0x26u, 0x70u,
-    0x05u, 0x26u, 0x26u, 0x70u, 0x2Du, 0x78u, 0x05u, 0xF0u,
-    0x02u, 0x05u, 0xEDu, 0xB2u, 0x55u, 0xB9u, 0x20u, 0x70u,
+    0x70u, 0xB5u, 0x0Du, 0x4Du, 0x2Cu, 0x78u, 0xA6u, 0x07u,
+    0x12u, 0xD5u, 0x0Cu, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,
+    0xD8u, 0x26u, 0x26u, 0x70u, 0x05u, 0x26u, 0x26u, 0x70u,
+    0x2Du, 0x78u, 0xADu, 0x07u, 0x0Au, 0xD4u, 0x20u, 0x70u,
     0x08u, 0x0Au, 0xC9u, 0xB2u, 0x20u, 0x70u, 0x21u, 0x70u,
-    0x07u, 0x20u, 0x22u, 0x70u, 0x23u, 0x70u, 0x70u, 0xBDu,
+    0x22u, 0x70u, 0x23u, 0x70u, 0x07u, 0x20u, 0x70u, 0xBDu,
     0x04u, 0x20u, 0x70u, 0xBDu, 0x09u, 0x20u, 0x70u, 0xBDu,
     0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
-    0x0Cu, 0x4Au, 0x13u, 0x78u, 0x03u, 0xF0u, 0x02u, 0x01u,
-    0xCBu, 0xB2u, 0x73u, 0xB1u, 0x0Au, 0x4Bu, 0xB6u, 0x21u,
-    0x19u, 0x70u, 0xE1u, 0x21u, 0x19u, 0x70u, 0x0Eu, 0x21u,
-    0x19u, 0x70u, 0x12u, 0x78u, 0x02u, 0xF0u, 0x02u, 0x01u,
-    0xCAu, 0xB2u, 0x22u, 0xB9u, 0x18u, 0x70u, 0x07u, 0x20u,
+    0x0Au, 0x4Au, 0x13u, 0x78u, 0x99u, 0x07u, 0x0Cu, 0xD5u,
+    0x09u, 0x4Bu, 0xB6u, 0x21u, 0x19u, 0x70u, 0xE1u, 0x21u,
+    0x19u, 0x70u, 0x0Eu, 0x21u, 0x19u, 0x70u, 0x12u, 0x78u,
+    0x92u, 0x07u, 0x04u, 0xD4u, 0x18u, 0x70u, 0x07u, 0x20u,
     0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x09u, 0x20u,
     0x70u, 0x47u, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
     0x20u, 0x47u, 0x00u, 0x40u, 0x38u, 0xB5u, 0xFFu, 0xF7u,
-    0x71u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,
+    0x15u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,
     0x01u, 0x25u, 0x0Bu, 0x4Au, 0x1Du, 0x70u, 0x14u, 0x68u,
     0x2Cu, 0x40u, 0x0Au, 0xD0u, 0x14u, 0x68u, 0x24u, 0xF0u,
     0x01u, 0x04u, 0x14u, 0x60u, 0x00u, 0xBFu, 0x00u, 0xBFu,
     0x00u, 0xBFu, 0x5Du, 0x60u, 0x0Cu, 0x46u, 0x00u, 0xE0u,
-    0x04u, 0x24u, 0xFFu, 0xF7u, 0x5Fu, 0xFEu, 0x20u, 0x46u,
-    0x38u, 0xBDu, 0x00u, 0xBFu, 0x48u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x24u, 0xFFu, 0xF7u, 0x03u, 0xFEu, 0x20u, 0x46u,
+    0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,
     0x04u, 0x00u, 0x08u, 0x40u, 0x10u, 0xB5u, 0xFFu, 0xF7u,
-    0x51u, 0xFEu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,
+    0xF5u, 0xFDu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,
     0x1Au, 0x70u, 0x01u, 0x29u, 0x08u, 0xD1u, 0x07u, 0x49u,
     0x0Cu, 0x68u, 0x44u, 0xF0u, 0x01u, 0x04u, 0x0Cu, 0x60u,
     0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x5Au, 0x60u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x42u, 0xBEu,
-    0x48u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xE6u, 0xBDu,
+    0x44u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,
+    0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x9Bu, 0x07u, 0x08u, 0xD5u,
+    0x06u, 0x4Bu, 0xB6u, 0x22u, 0x1Au, 0x70u, 0xE0u, 0x22u,
+    0x1Au, 0x70u, 0x0Du, 0x22u, 0x1Au, 0x70u, 0x07u, 0x20u,
+    0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
     0x08u, 0xB5u, 0x62u, 0xB6u, 0x00u, 0x20u, 0x02u, 0x21u,
-    0x00u, 0xF0u, 0x62u, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,
-    0x1Au, 0x70u, 0x08u, 0xBDu, 0x50u, 0xC1u, 0xFFu, 0x1Fu,
-    0x01u, 0x20u, 0x00u, 0xF0u, 0x03u, 0xBAu, 0x00u, 0x00u,
-    0xF8u, 0xB5u, 0x07u, 0x46u, 0x0Eu, 0x46u, 0x02u, 0x20u,
-    0x15u, 0x46u, 0x39u, 0x46u, 0x40u, 0x22u, 0x1Cu, 0x46u,
-    0x00u, 0xF0u, 0xBAu, 0xF9u, 0x0Au, 0x23u, 0x5Cu, 0x43u,
-    0x0Du, 0x48u, 0x44u, 0x80u, 0x00u, 0x24u, 0x02u, 0x20u,
-    0x00u, 0xF0u, 0x94u, 0xF9u, 0x50u, 0xB9u, 0x0Au, 0x49u,
-    0x67u, 0x1Cu, 0x4Au, 0x88u, 0xBFu, 0xB2u, 0xA2u, 0x42u,
-    0x04u, 0xD9u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0xD2u, 0xFEu,
-    0x3Cu, 0x46u, 0xF0u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,
-    0x85u, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,
-    0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu,
-    0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x2Du, 0xE9u, 0xF0u, 0x41u,
-    0x15u, 0x46u, 0x0Au, 0x22u, 0x53u, 0x43u, 0x28u, 0x4Cu,
-    0x80u, 0x46u, 0x63u, 0x80u, 0x24u, 0x78u, 0x0Fu, 0x46u,
-    0xD4u, 0xB1u, 0x00u, 0x24u, 0x00u, 0xF0u, 0x5Eu, 0xF9u,
-    0x58u, 0xB9u, 0x23u, 0x4Bu, 0x66u, 0x1Cu, 0x58u, 0x88u,
-    0xB6u, 0xB2u, 0xA0u, 0x42u, 0x04u, 0xD9u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0xACu, 0xFEu, 0x34u, 0x46u, 0xF1u, 0xE7u,
-    0x34u, 0x46u, 0x00u, 0xF0u, 0x4Fu, 0xF9u, 0xE0u, 0xB1u,
-    0x00u, 0xF0u, 0x52u, 0xF9u, 0xFFu, 0xF7u, 0xB0u, 0xFFu,
-    0x19u, 0x4Au, 0x00u, 0x21u, 0x11u, 0x70u, 0x14u, 0xE0u,
-    0x00u, 0xF0u, 0x4Au, 0xF9u, 0x08u, 0xB9u, 0x00u, 0x24u,
-    0x0Fu, 0xE0u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x00u, 0x28u,
-    0xF9u, 0xD0u, 0xFFu, 0xF7u, 0xA1u, 0xFFu, 0x08u, 0xE0u,
-    0x11u, 0x4Bu, 0x66u, 0x1Cu, 0x59u, 0x88u, 0xB6u, 0xB2u,
-    0xA1u, 0x42u, 0x09u, 0xD9u, 0xFFu, 0xF7u, 0x8Au, 0xFEu,
-    0x34u, 0x46u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF9u,
-    0x01u, 0x28u, 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xEFu, 0xD1u,
-    0x00u, 0xF0u, 0x38u, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u,
-    0x41u, 0x46u, 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u,
-    0x40u, 0x22u, 0x00u, 0xF0u, 0x9Fu, 0xF9u, 0x28u, 0x80u,
-    0x00u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u, 0x00u, 0x20u,
-    0x28u, 0x80u, 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u,
-    0x50u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,
-    0xA5u, 0xFDu, 0x38u, 0x4Bu, 0x07u, 0x46u, 0x1Au, 0x78u,
-    0x01u, 0x25u, 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u,
-    0x19u, 0x7Cu, 0x02u, 0x26u, 0x41u, 0xF0u, 0x01u, 0x04u,
-    0x1Cu, 0x74u, 0x33u, 0x4Bu, 0x33u, 0x4Cu, 0x1Du, 0x70u,
-    0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u, 0x8Du, 0x2Cu,
-    0x02u, 0xF0u, 0x7Fu, 0x00u, 0x03u, 0xF8u, 0x8Du, 0x0Cu,
-    0x00u, 0x20u, 0xFFu, 0xF7u, 0x63u, 0xFEu, 0x21u, 0x78u,
-    0x2Du, 0x48u, 0x01u, 0xF0u, 0xF9u, 0x03u, 0x23u, 0x70u,
-    0x02u, 0x78u, 0x02u, 0xF0u, 0xDFu, 0x01u, 0x01u, 0x70u,
-    0x23u, 0x78u, 0x28u, 0x46u, 0x2Bu, 0x43u, 0x23u, 0x70u,
-    0xFFu, 0xF7u, 0x54u, 0xFEu, 0x28u, 0x20u, 0xFFu, 0xF7u,
-    0x51u, 0xFEu, 0x26u, 0x48u, 0x02u, 0x78u, 0x02u, 0xF0u,
-    0x7Fu, 0x01u, 0x01u, 0x70u, 0x03u, 0x78u, 0x03u, 0xF0u,
-    0xBFu, 0x02u, 0x02u, 0x70u, 0x20u, 0x78u, 0x30u, 0x43u,
-    0x20u, 0x70u, 0x30u, 0x46u, 0xFFu, 0xF7u, 0x42u, 0xFEu,
-    0x21u, 0x78u, 0x1Fu, 0x4Au, 0x41u, 0xF0u, 0x04u, 0x03u,
-    0x23u, 0x70u, 0x00u, 0x24u, 0x14u, 0x70u, 0x38u, 0x46u,
-    0x54u, 0x70u, 0xFFu, 0xF7u, 0x63u, 0xFDu, 0x17u, 0x20u,
-    0x1Au, 0x49u, 0xFFu, 0xF7u, 0x3Bu, 0xFEu, 0x17u, 0x20u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x45u, 0xFEu, 0x15u, 0x20u,
-    0x17u, 0x49u, 0xFFu, 0xF7u, 0x33u, 0xFEu, 0x15u, 0x20u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x3Du, 0xFEu, 0x18u, 0x20u,
-    0x14u, 0x49u, 0xFFu, 0xF7u, 0x2Bu, 0xFEu, 0x18u, 0x20u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x35u, 0xFEu, 0x20u, 0x46u,
-    0x11u, 0x49u, 0xFFu, 0xF7u, 0x23u, 0xFEu, 0x20u, 0x46u,
-    0x07u, 0x21u, 0xFFu, 0xF7u, 0x2Du, 0xFEu, 0x28u, 0x46u,
-    0x0Eu, 0x49u, 0xFFu, 0xF7u, 0x1Bu, 0xFEu, 0x28u, 0x46u,
-    0x07u, 0x21u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,
-    0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u,
-    0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
+    0x00u, 0xF0u, 0x4Eu, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x70u, 0x08u, 0xBDu, 0x4Cu, 0xC1u, 0xFFu, 0x1Fu,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0xF1u, 0xB9u, 0xF8u, 0xB5u,
+    0x07u, 0x46u, 0x0Eu, 0x46u, 0x15u, 0x46u, 0x03u, 0xEBu,
+    0x83u, 0x03u, 0x02u, 0x20u, 0x39u, 0x46u, 0x40u, 0x22u,
+    0x5Cu, 0x00u, 0x00u, 0xF0u, 0xA7u, 0xF9u, 0x02u, 0x20u,
+    0x00u, 0xF0u, 0x86u, 0xF9u, 0x30u, 0xB9u, 0x2Cu, 0xB1u,
+    0x01u, 0x20u, 0x01u, 0x3Cu, 0xFFu, 0xF7u, 0x8Au, 0xFEu,
+    0xA4u, 0xB2u, 0xF4u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,
+    0x7Bu, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,
+    0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0x00u,
+    0x2Du, 0xE9u, 0xF8u, 0x43u, 0x03u, 0xEBu, 0x83u, 0x03u,
+    0x5Cu, 0x00u, 0x23u, 0x4Bu, 0x16u, 0x46u, 0x1Au, 0x78u,
+    0x80u, 0x46u, 0x0Fu, 0x46u, 0x99u, 0x46u, 0xAAu, 0xB1u,
+    0x25u, 0x46u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x30u, 0xB9u,
+    0x2Du, 0xB1u, 0x01u, 0x20u, 0x01u, 0x3Du, 0xFFu, 0xF7u,
+    0x69u, 0xFEu, 0xADu, 0xB2u, 0xF5u, 0xE7u, 0x00u, 0xF0u,
+    0x49u, 0xF9u, 0xA8u, 0xB1u, 0x00u, 0xF0u, 0x4Cu, 0xF9u,
+    0xFFu, 0xF7u, 0xBEu, 0xFFu, 0x00u, 0x23u, 0x89u, 0xF8u,
+    0x00u, 0x30u, 0x0Du, 0xE0u, 0x00u, 0xF0u, 0x44u, 0xF9u,
+    0x50u, 0xB1u, 0x00u, 0xF0u, 0x3Bu, 0xF9u, 0x38u, 0xB1u,
+    0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x04u, 0xE0u, 0x54u, 0xB1u,
+    0xFFu, 0xF7u, 0x50u, 0xFEu, 0x01u, 0x3Cu, 0xA4u, 0xB2u,
+    0x01u, 0x20u, 0x00u, 0xF0u, 0x41u, 0xF9u, 0x01u, 0x28u,
+    0x4Fu, 0xF0u, 0x01u, 0x00u, 0xF3u, 0xD1u, 0x00u, 0xF0u,
+    0x3Bu, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u, 0x41u, 0x46u,
+    0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u, 0x40u, 0x22u,
+    0x00u, 0xF0u, 0xA4u, 0xF9u, 0x30u, 0x80u, 0x00u, 0x20u,
+    0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0x23u, 0x33u, 0x80u,
+    0x10u, 0x20u, 0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0xBFu,
+    0x4Cu, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,
+    0x49u, 0xFDu, 0x39u, 0x4Bu, 0x01u, 0x25u, 0x1Au, 0x78u,
+    0x02u, 0x26u, 0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u,
+    0x1Au, 0x7Cu, 0x36u, 0x4Cu, 0x42u, 0xF0u, 0x01u, 0x02u,
+    0x1Au, 0x74u, 0x03u, 0xF5u, 0xE7u, 0x53u, 0x18u, 0x33u,
+    0x1Du, 0x70u, 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u,
+    0x8Du, 0x2Cu, 0x07u, 0x46u, 0x02u, 0xF0u, 0x7Fu, 0x02u,
+    0x03u, 0xF8u, 0x8Du, 0x2Cu, 0x00u, 0x20u, 0xFFu, 0xF7u,
+    0x25u, 0xFEu, 0x23u, 0x78u, 0x28u, 0x46u, 0x03u, 0xF0u,
+    0xF9u, 0x03u, 0x23u, 0x70u, 0x2Au, 0x4Bu, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xDFu, 0x02u, 0x1Au, 0x70u, 0x23u, 0x78u,
+    0x2Bu, 0x43u, 0x23u, 0x70u, 0xFFu, 0xF7u, 0x16u, 0xFEu,
+    0x28u, 0x20u, 0xFFu, 0xF7u, 0x13u, 0xFEu, 0x25u, 0x4Bu,
+    0x30u, 0x46u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x7Fu, 0x02u,
+    0x1Au, 0x70u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xBFu, 0x02u,
+    0x1Au, 0x70u, 0x23u, 0x78u, 0x33u, 0x43u, 0x23u, 0x70u,
+    0xFFu, 0xF7u, 0x04u, 0xFEu, 0x23u, 0x78u, 0x38u, 0x46u,
+    0x43u, 0xF0u, 0x04u, 0x03u, 0x23u, 0x70u, 0x1Cu, 0x4Bu,
+    0x00u, 0x24u, 0x1Cu, 0x70u, 0x5Cu, 0x70u, 0xFFu, 0xF7u,
+    0x05u, 0xFDu, 0x1Au, 0x49u, 0x17u, 0x20u, 0xFFu, 0xF7u,
+    0x1Fu, 0xFEu, 0x17u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x29u, 0xFEu, 0x17u, 0x49u, 0x15u, 0x20u, 0xFFu, 0xF7u,
+    0x17u, 0xFEu, 0x15u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x21u, 0xFEu, 0x14u, 0x49u, 0x18u, 0x20u, 0xFFu, 0xF7u,
+    0x0Fu, 0xFEu, 0x18u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x19u, 0xFEu, 0x20u, 0x46u, 0x10u, 0x49u, 0xFFu, 0xF7u,
+    0x07u, 0xFEu, 0x20u, 0x46u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+    0x11u, 0xFEu, 0x28u, 0x46u, 0x0Du, 0x49u, 0xFFu, 0xF7u,
+    0xFFu, 0xFDu, 0x28u, 0x46u, 0x07u, 0x21u, 0xBDu, 0xE8u,
+    0xF8u, 0x40u, 0xFFu, 0xF7u, 0x07u, 0xBEu, 0x00u, 0xBFu,
+    0xA5u, 0x43u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
     0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u,
-    0x84u, 0x60u, 0x00u, 0x40u, 0x23u, 0x16u, 0x00u, 0x00u,
-    0x21u, 0x16u, 0x00u, 0x00u, 0x61u, 0x14u, 0x00u, 0x00u,
-    0xB9u, 0x15u, 0x00u, 0x00u, 0xEDu, 0x15u, 0x00u, 0x00u,
+    0x84u, 0x60u, 0x00u, 0x40u, 0x13u, 0x17u, 0x00u, 0x00u,
+    0x11u, 0x17u, 0x00u, 0x00u, 0x65u, 0x15u, 0x00u, 0x00u,
+    0xA9u, 0x16u, 0x00u, 0x00u, 0xDDu, 0x16u, 0x00u, 0x00u,
     0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u,
     0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u,
     0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u,
     0x02u, 0x22u, 0x1Au, 0x60u, 0x13u, 0x4Bu, 0x00u, 0x24u,
     0x1Cu, 0x70u, 0x13u, 0x4Bu, 0x01u, 0xB1u, 0x03u, 0x22u,
-    0x12u, 0x49u, 0x1Au, 0x70u, 0x12u, 0x4Bu, 0x08u, 0x70u,
-    0x12u, 0x4Au, 0x00u, 0x20u, 0x12u, 0x49u, 0x18u, 0x70u,
-    0x12u, 0x4Bu, 0x10u, 0x70u, 0x08u, 0x70u, 0x12u, 0x4Au,
-    0x12u, 0x49u, 0x18u, 0x70u, 0x12u, 0x4Bu, 0x10u, 0x70u,
-    0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,
-    0x01u, 0x20u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,
-    0xE7u, 0xFCu, 0x0Eu, 0x48u, 0x04u, 0x21u, 0x01u, 0x70u,
-    0x10u, 0xBDu, 0x00u, 0xBFu, 0xECu, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0xE1u, 0x00u, 0xE0u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x09u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
+    0x1Au, 0x70u, 0x12u, 0x4Bu, 0x12u, 0x4Au, 0x18u, 0x70u,
+    0x00u, 0x23u, 0x13u, 0x70u, 0x11u, 0x4Au, 0x01u, 0x20u,
+    0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,
+    0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,
+    0x13u, 0x70u, 0x11u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+    0x80u, 0x22u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,
+    0x8Bu, 0xFCu, 0x0Eu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0xE1u, 0x00u, 0xE0u, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x09u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+    0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+    0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
     0x28u, 0x60u, 0x00u, 0x40u, 0x12u, 0x60u, 0x00u, 0x40u,
     0x70u, 0xB5u, 0x07u, 0x4Cu, 0x06u, 0x46u, 0x23u, 0x78u,
     0x0Du, 0x46u, 0x1Bu, 0xB9u, 0xFFu, 0xF7u, 0x22u, 0xFFu,
-    0x01u, 0x20u, 0x20u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,
+    0x01u, 0x23u, 0x23u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,
     0xBDu, 0xE8u, 0x70u, 0x40u, 0xFFu, 0xF7u, 0xA4u, 0xBFu,
-    0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,
-    0x0Cu, 0x49u, 0x1Au, 0x70u, 0x00u, 0x20u, 0x0Cu, 0x4Au,
-    0x0Cu, 0x4Bu, 0x08u, 0x70u, 0x0Cu, 0x49u, 0x10u, 0x70u,
-    0x18u, 0x70u, 0x0Cu, 0x4Au, 0x0Cu, 0x4Bu, 0x08u, 0x70u,
-    0x0Cu, 0x49u, 0x10u, 0x70u, 0x18u, 0x70u, 0x0Cu, 0x4Bu,
-    0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,
+    0x4Du, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x70u, 0x0Cu, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,
+    0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+    0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+    0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+    0x0Bu, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x80u, 0x22u,
     0x03u, 0xF8u, 0x20u, 0x2Cu, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
+    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+    0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+    0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
     0x28u, 0x60u, 0x00u, 0x40u, 0x01u, 0x4Bu, 0x18u, 0x78u,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
-    0x03u, 0x4Bu, 0x18u, 0x78u, 0x10u, 0xB1u, 0x00u, 0x22u,
-    0x18u, 0x78u, 0x1Au, 0x70u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x0Cu, 0x22u,
-    0x02u, 0xFBu, 0x00u, 0x30u, 0x40u, 0x78u, 0x70u, 0x47u,
-    0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x38u, 0xC3u, 0xB2u,
-    0x07u, 0x2Bu, 0x0Cu, 0xD8u, 0x19u, 0x01u, 0x07u, 0x4Au,
-    0xCBu, 0xB2u, 0x98u, 0x5Cu, 0x51u, 0x1Cu, 0x5Bu, 0x5Cu,
-    0x00u, 0xF0u, 0x0Fu, 0x02u, 0x43u, 0xEAu, 0x02u, 0x20u,
-    0x81u, 0x1Eu, 0x88u, 0xB2u, 0x70u, 0x47u, 0x00u, 0x20u,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0xF0u, 0xB5u,
-    0x2Fu, 0xD8u, 0x18u, 0x4Eu, 0x1Cu, 0x01u, 0x0Cu, 0x27u,
-    0xE3u, 0xB2u, 0x07u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,
-    0x15u, 0x4Du, 0xBFu, 0xB2u, 0xC7u, 0xF5u, 0x00u, 0x77u,
-    0xBAu, 0x42u, 0x1Du, 0x44u, 0x03u, 0xD9u, 0xE2u, 0x88u,
-    0xC2u, 0xF5u, 0x00u, 0x74u, 0xA2u, 0xB2u, 0x0Cu, 0x24u,
-    0x04u, 0xFBu, 0x00u, 0x66u, 0xF4u, 0x78u, 0x44u, 0xEAu,
-    0x12u, 0x26u, 0x0Eu, 0x4Cu, 0x1Eu, 0x55u, 0xD6u, 0xB2u,
-    0x01u, 0x34u, 0x1Eu, 0x55u, 0x49u, 0xB9u, 0x09u, 0x4Au,
-    0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u,
-    0x41u, 0x70u, 0x40u, 0x79u, 0x08u, 0x4Au, 0x98u, 0x54u,
-    0xF0u, 0xBDu, 0x00u, 0x24u, 0xA6u, 0xB2u, 0x96u, 0x42u,
-    0xF1u, 0xD2u, 0x0Eu, 0x5Du, 0x01u, 0x34u, 0x2Eu, 0x70u,
-    0xF8u, 0xE7u, 0xF0u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x88u, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,
-    0x07u, 0x2Bu, 0x0Au, 0xD8u, 0x05u, 0x4Au, 0x0Cu, 0x21u,
-    0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u, 0x41u, 0x70u,
-    0x1Bu, 0x01u, 0x40u, 0x79u, 0x02u, 0x4Au, 0xDBu, 0xB2u,
-    0x98u, 0x54u, 0x70u, 0x47u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFFu, 0x00u,
+    0x1Au, 0xB1u, 0x18u, 0x78u, 0x00u, 0x22u, 0xC0u, 0xB2u,
+    0x1Au, 0x70u, 0x70u, 0x47u, 0x68u, 0xC1u, 0xFFu, 0x1Fu,
+    0x02u, 0x4Bu, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x30u,
+    0x40u, 0x78u, 0x70u, 0x47u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x01u, 0x38u, 0xC3u, 0xB2u, 0x07u, 0x2Bu, 0x0Cu, 0xD8u,
+    0x07u, 0x4Au, 0x1Bu, 0x01u, 0xDBu, 0xB2u, 0x98u, 0x5Cu,
+    0x01u, 0x32u, 0x9Bu, 0x5Cu, 0x00u, 0xF0u, 0x0Fu, 0x00u,
+    0x43u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x38u, 0x80u, 0xB2u,
+    0x70u, 0x47u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0x0Cu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,
+    0x07u, 0x2Bu, 0xF0u, 0xB5u, 0x2Fu, 0xD8u, 0x18u, 0x4Eu,
+    0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,
+    0x1Bu, 0x01u, 0xBFu, 0xB2u, 0x15u, 0x4Du, 0xC7u, 0xF5u,
+    0x00u, 0x77u, 0xDBu, 0xB2u, 0xBAu, 0x42u, 0x1Du, 0x44u,
+    0x03u, 0xD9u, 0xE2u, 0x88u, 0xC2u, 0xF5u, 0x00u, 0x72u,
+    0x92u, 0xB2u, 0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u,
+    0xE7u, 0x78u, 0x0Fu, 0x4Cu, 0x47u, 0xEAu, 0x12u, 0x27u,
+    0x1Fu, 0x55u, 0xD7u, 0xB2u, 0x01u, 0x34u, 0x1Fu, 0x55u,
+    0x49u, 0xB9u, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x60u,
+    0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x09u, 0x4Au,
+    0xC9u, 0xB2u, 0x99u, 0x54u, 0xF0u, 0xBDu, 0x00u, 0x24u,
+    0xA7u, 0xB2u, 0x97u, 0x42u, 0xF1u, 0xD2u, 0x0Fu, 0x5Du,
+    0x01u, 0x34u, 0x2Fu, 0x70u, 0xF8u, 0xE7u, 0xF0u, 0xBDu,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x88u, 0x60u, 0x00u, 0x40u,
+    0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,
+    0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x0Bu, 0xD8u,
+    0x06u, 0x4Au, 0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u,
+    0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x1Bu, 0x01u,
+    0x03u, 0x4Au, 0xDBu, 0xB2u, 0xC9u, 0xB2u, 0x99u, 0x54u,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
     0x0Eu, 0x60u, 0x00u, 0x40u, 0xF8u, 0xB5u, 0x43u, 0x1Eu,
-    0x0Du, 0x46u, 0xD9u, 0xB2u, 0x07u, 0x29u, 0x07u, 0x46u,
-    0x14u, 0x46u, 0x16u, 0xD8u, 0xBDu, 0xB1u, 0x0Au, 0x01u,
-    0x0Cu, 0x4Eu, 0xD3u, 0xB2u, 0x9Eu, 0x19u, 0xFFu, 0xF7u,
-    0x89u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,
-    0x84u, 0xB2u, 0x00u, 0x22u, 0x90u, 0xB2u, 0xA0u, 0x42u,
-    0x03u, 0xD2u, 0x31u, 0x78u, 0xA9u, 0x54u, 0x01u, 0x32u,
-    0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCEu, 0xFFu,
-    0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x2Cu, 0x46u,
+    0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x07u, 0x46u, 0x0Du, 0x46u,
+    0x14u, 0x46u, 0x16u, 0xD8u, 0xB9u, 0xB1u, 0x1Bu, 0x01u,
+    0x0Cu, 0x4Eu, 0xDBu, 0xB2u, 0x1Eu, 0x44u, 0xFFu, 0xF7u,
+    0x87u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,
+    0x84u, 0xB2u, 0x00u, 0x23u, 0x9Au, 0xB2u, 0xA2u, 0x42u,
+    0x03u, 0xD2u, 0x32u, 0x78u, 0xEAu, 0x54u, 0x01u, 0x33u,
+    0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCCu, 0xFFu,
+    0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x0Cu, 0x46u,
     0x20u, 0x46u, 0xF8u, 0xBDu, 0x88u, 0x60u, 0x00u, 0x40u,
-    0x1Bu, 0x4Bu, 0x1Cu, 0x49u, 0x1Au, 0x88u, 0x08u, 0x78u,
-    0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u, 0x1Au, 0x49u,
-    0x1Au, 0x4Bu, 0xCAu, 0xB2u, 0x18u, 0x88u, 0x80u, 0xB2u,
-    0x78u, 0xB1u, 0x19u, 0x4Au, 0x91u, 0x42u, 0x0Bu, 0xD0u,
-    0x5Au, 0x68u, 0x10u, 0x78u, 0x01u, 0xF8u, 0x01u, 0x0Bu,
-    0x5Au, 0x68u, 0x50u, 0x1Cu, 0x58u, 0x60u, 0x1Au, 0x88u,
-    0x50u, 0x1Eu, 0x82u, 0xB2u, 0x1Au, 0x80u, 0xEBu, 0xE7u,
-    0x08u, 0x22u, 0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x08u, 0x2Bu,
-    0x00u, 0xD0u, 0x5Au, 0xB1u, 0x0Fu, 0x48u, 0x01u, 0x78u,
-    0x81u, 0xF0u, 0x80u, 0x03u, 0x0Eu, 0x49u, 0x03u, 0x70u,
-    0x0Fu, 0x20u, 0x0Eu, 0x4Bu, 0x08u, 0x70u, 0x02u, 0x20u,
-    0x18u, 0x70u, 0x04u, 0xE0u, 0x0Au, 0x49u, 0x0Bu, 0x4Bu,
-    0x02u, 0x20u, 0x08u, 0x70u, 0x18u, 0x70u, 0x03u, 0x49u,
-    0x09u, 0x48u, 0x0Au, 0x70u, 0x02u, 0x70u, 0x70u, 0x47u,
-    0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0x60u, 0x00u, 0x40u, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x02u, 0x22u,
-    0x1Au, 0x70u, 0x07u, 0x49u, 0x07u, 0x4Bu, 0x80u, 0x20u,
-    0x0Fu, 0x22u, 0x08u, 0x70u, 0x1Au, 0x70u, 0x06u, 0x49u,
-    0x06u, 0x4Au, 0x00u, 0x20u, 0x08u, 0x70u, 0x10u, 0x70u,
-    0x01u, 0x20u, 0x70u, 0x47u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
-    0xE5u, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
-    0x10u, 0xB5u, 0x15u, 0x4Bu, 0x1Au, 0x78u, 0x15u, 0x4Bu,
-    0x02u, 0xF0u, 0x0Fu, 0x00u, 0x81u, 0x1Eu, 0x18u, 0x88u,
-    0xCAu, 0xB2u, 0x11u, 0x18u, 0x88u, 0xB2u, 0x12u, 0x49u,
-    0x18u, 0x80u, 0x12u, 0x4Bu, 0x18u, 0x88u, 0x80u, 0xB2u,
-    0x70u, 0xB1u, 0x6Au, 0xB1u, 0x58u, 0x68u, 0x11u, 0xF8u,
-    0x01u, 0x4Bu, 0x01u, 0x3Au, 0x04u, 0x70u, 0x58u, 0x68u,
-    0xD2u, 0xB2u, 0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u,
-    0x01u, 0x38u, 0x80u, 0xB2u, 0x18u, 0x80u, 0xECu, 0xE7u,
-    0x09u, 0x49u, 0x0Au, 0x4Bu, 0x0Au, 0x70u, 0x1Au, 0x78u,
-    0x0Bu, 0x21u, 0x82u, 0xF0u, 0x80u, 0x00u, 0x18u, 0x70u,
-    0x07u, 0x4Bu, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0x29u, 0x60u, 0x00u, 0x40u, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,
-    0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x06u, 0x4Au, 0x07u, 0x48u,
-    0x06u, 0x23u, 0x13u, 0x70u, 0x03u, 0x70u, 0x06u, 0x4Bu,
-    0x06u, 0x48u, 0x80u, 0x21u, 0x00u, 0x22u, 0x19u, 0x70u,
-    0x02u, 0x70u, 0x01u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
-    0x05u, 0x4Bu, 0x9Au, 0x68u, 0x3Au, 0xB1u, 0x99u, 0x68u,
-    0x04u, 0x4Au, 0x08u, 0x70u, 0x98u, 0x68u, 0x11u, 0x88u,
-    0x41u, 0x80u, 0x00u, 0x20u, 0x98u, 0x60u, 0x70u, 0x47u,
-    0x60u, 0xC1u, 0xFFu, 0x1Fu, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x32u, 0xB1u,
-    0x19u, 0x78u, 0x09u, 0x4Au, 0x41u, 0xF0u, 0x80u, 0x00u,
-    0x00u, 0x21u, 0x10u, 0x70u, 0x19u, 0x70u, 0x07u, 0x4Bu,
-    0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u, 0xFFu, 0xF7u,
-    0xDFu, 0xFFu, 0x05u, 0x49u, 0x03u, 0x22u, 0x0Au, 0x70u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0x60u, 0x00u, 0x40u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,
+    0x30u, 0xB5u, 0x1Au, 0x4Bu, 0x1Au, 0x48u, 0x1Au, 0x88u,
+    0x01u, 0x78u, 0x0Au, 0x44u, 0x92u, 0xB2u, 0x19u, 0x49u,
+    0x1Au, 0x80u, 0x19u, 0x4Bu, 0xCAu, 0xB2u, 0x1Cu, 0x88u,
+    0xA4u, 0xB2u, 0x84u, 0xB1u, 0x17u, 0x4Au, 0x91u, 0x42u,
+    0x0Cu, 0xD0u, 0x5Au, 0x68u, 0x12u, 0x78u, 0xD2u, 0xB2u,
+    0x01u, 0xF8u, 0x01u, 0x2Bu, 0x5Au, 0x68u, 0x01u, 0x32u,
+    0x5Au, 0x60u, 0x1Au, 0x88u, 0x01u, 0x3Au, 0x92u, 0xB2u,
+    0x1Au, 0x80u, 0xEAu, 0xE7u, 0x08u, 0x22u, 0x03u, 0x78u,
+    0x0Fu, 0x4Cu, 0x08u, 0x2Bu, 0x0Fu, 0x4Bu, 0x00u, 0xD0u,
+    0x42u, 0xB1u, 0x0Fu, 0x49u, 0x0Du, 0x78u, 0x85u, 0xF0u,
+    0x80u, 0x05u, 0x0Du, 0x70u, 0x0Fu, 0x21u, 0x21u, 0x70u,
+    0x02u, 0x21u, 0x01u, 0xE0u, 0x02u, 0x21u, 0x21u, 0x70u,
+    0x19u, 0x70u, 0x0Au, 0x4Bu, 0x02u, 0x70u, 0x1Au, 0x70u,
+    0x30u, 0xBDu, 0x00u, 0xBFu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,
+    0x07u, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x07u, 0x4Bu,
+    0x80u, 0x22u, 0x1Au, 0x70u, 0x06u, 0x4Bu, 0x0Fu, 0x22u,
+    0x1Au, 0x70u, 0x06u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,
+    0x05u, 0x4Au, 0x01u, 0x20u, 0x13u, 0x70u, 0x70u, 0x47u,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
+    0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x15u, 0x4Bu,
+    0x1Au, 0x78u, 0x15u, 0x4Bu, 0x02u, 0xF0u, 0x0Fu, 0x02u,
+    0x19u, 0x88u, 0x02u, 0x3Au, 0xD2u, 0xB2u, 0x11u, 0x44u,
+    0x89u, 0xB2u, 0x19u, 0x80u, 0x11u, 0x49u, 0x12u, 0x4Bu,
+    0x18u, 0x88u, 0x80u, 0xB2u, 0x78u, 0xB1u, 0x72u, 0xB1u,
+    0x58u, 0x68u, 0x11u, 0xF8u, 0x01u, 0x4Bu, 0x01u, 0x3Au,
+    0xE4u, 0xB2u, 0x04u, 0x70u, 0x58u, 0x68u, 0xD2u, 0xB2u,
+    0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u, 0x01u, 0x38u,
+    0x80u, 0xB2u, 0x18u, 0x80u, 0xEBu, 0xE7u, 0x09u, 0x4Bu,
+    0x1Au, 0x70u, 0x09u, 0x4Bu, 0x1Au, 0x78u, 0x82u, 0xF0u,
+    0x80u, 0x02u, 0x1Au, 0x70u, 0x07u, 0x4Bu, 0x0Bu, 0x22u,
+    0x1Au, 0x70u, 0x10u, 0xBDu, 0x29u, 0x60u, 0x00u, 0x40u,
+    0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x06u, 0x4Au, 0x06u, 0x23u, 0x13u, 0x70u, 0x06u, 0x4Au,
+    0x01u, 0x20u, 0x13u, 0x70u, 0x05u, 0x4Bu, 0x80u, 0x22u,
+    0x1Au, 0x70u, 0x05u, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x70u,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x9Au, 0x68u,
+    0x3Au, 0xB1u, 0x9Au, 0x68u, 0x04u, 0x49u, 0x10u, 0x70u,
+    0x9Au, 0x68u, 0x09u, 0x88u, 0x51u, 0x80u, 0x00u, 0x22u,
+    0x9Au, 0x60u, 0x70u, 0x47u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x12u, 0x4Bu,
+    0x1Au, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x1Bu, 0x78u,
+    0xDBu, 0xB2u, 0x1Au, 0x06u, 0x02u, 0xD5u, 0x0Fu, 0x4Au,
+    0x13u, 0x70u, 0x08u, 0xBDu, 0x02u, 0x20u, 0xFFu, 0xF7u,
+    0xE1u, 0xFFu, 0x0Du, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+    0x60u, 0x03u, 0x20u, 0x2Bu, 0x05u, 0xD0u, 0x40u, 0x2Bu,
+    0x06u, 0xD0u, 0x43u, 0xB9u, 0x00u, 0xF0u, 0x94u, 0xFCu,
+    0x04u, 0xE0u, 0x00u, 0xF0u, 0xE1u, 0xFDu, 0x01u, 0xE0u,
+    0x00u, 0xF0u, 0xD2u, 0xFDu, 0x10u, 0xB9u, 0x03u, 0x4Bu,
+    0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+    0x28u, 0x60u, 0x00u, 0x40u, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x08u, 0x49u,
+    0x08u, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x88u, 0x09u, 0x78u,
+    0x0Au, 0x44u, 0x92u, 0xB2u, 0x1Au, 0x80u, 0x06u, 0x4Bu,
+    0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xB6u, 0xFFu,
+    0x04u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu,
+    0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u,
+    0x04u, 0x2Bu, 0x07u, 0xD0u, 0x06u, 0x2Bu, 0x09u, 0xD0u,
+    0x02u, 0x2Bu, 0x0Du, 0xD1u, 0xBDu, 0xE8u, 0x08u, 0x40u,
+    0xFFu, 0xF7u, 0xD8u, 0xBFu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+    0xFFu, 0xF7u, 0x48u, 0xBFu, 0x03u, 0x20u, 0xFFu, 0xF7u,
+    0x95u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+    0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,
     0x00u, 0x22u, 0x01u, 0x20u, 0x1Au, 0x70u, 0xFFu, 0xF7u,
-    0xCBu, 0xFFu, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x18u, 0x78u,
-    0x04u, 0x28u, 0x05u, 0xD0u, 0x06u, 0x28u, 0x05u, 0xD0u,
-    0x02u, 0x28u, 0x05u, 0xD1u, 0xFFu, 0xF7u, 0x04u, 0xBFu,
-    0xFFu, 0xF7u, 0xE4u, 0xBFu, 0xFFu, 0xF7u, 0xC4u, 0xBFu,
-    0x70u, 0x47u, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x08u, 0x49u, 0x08u, 0x4Bu, 0x1Au, 0x88u,
-    0x08u, 0x78u, 0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u,
-    0x06u, 0x4Bu, 0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u,
-    0xFFu, 0xF7u, 0xA2u, 0xFFu, 0x04u, 0x49u, 0x03u, 0x22u,
-    0x0Au, 0x70u, 0x08u, 0xBDu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
-    0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Bu, 0x4Bu,
-    0x18u, 0x78u, 0x04u, 0x28u, 0x07u, 0xD0u, 0x06u, 0x28u,
-    0x09u, 0xD0u, 0x02u, 0x28u, 0x0Du, 0xD1u, 0xBDu, 0xE8u,
-    0x08u, 0x40u, 0xFFu, 0xF7u, 0xD9u, 0xBFu, 0xBDu, 0xE8u,
-    0x08u, 0x40u, 0xFFu, 0xF7u, 0x35u, 0xBFu, 0x03u, 0x20u,
-    0xFFu, 0xF7u, 0x82u, 0xFFu, 0x02u, 0x49u, 0x03u, 0x22u,
-    0x0Au, 0x70u, 0x08u, 0xBDu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x11u, 0x4Bu,
-    0x1Au, 0x78u, 0x1Au, 0x70u, 0x18u, 0x78u, 0x02u, 0x06u,
-    0x02u, 0xD5u, 0x0Fu, 0x4Bu, 0x18u, 0x70u, 0x08u, 0xBDu,
-    0x02u, 0x20u, 0xFFu, 0xF7u, 0x6Du, 0xFFu, 0x0Du, 0x49u,
-    0x0Bu, 0x78u, 0x03u, 0xF0u, 0x60u, 0x02u, 0x20u, 0x2Au,
-    0x05u, 0xD0u, 0x40u, 0x2Au, 0x06u, 0xD0u, 0x42u, 0xB9u,
-    0x00u, 0xF0u, 0x4Au, 0xFCu, 0x04u, 0xE0u, 0x00u, 0xF0u,
-    0x8Du, 0xFDu, 0x01u, 0xE0u, 0x00u, 0xF0u, 0x7Eu, 0xFDu,
-    0x10u, 0xB9u, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,
-    0x08u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x08u, 0xB5u, 0x22u, 0x4Bu, 0x1Au, 0x78u, 0xD0u, 0xB2u,
-    0x00u, 0xF0u, 0x10u, 0x01u, 0xCBu, 0xB2u, 0x00u, 0x2Bu,
-    0x3Bu, 0xD0u, 0x52u, 0xB2u, 0x00u, 0x2Au, 0x0Au, 0xDAu,
-    0x00u, 0xF0u, 0x0Fu, 0x01u, 0x01u, 0x29u, 0x34u, 0xD1u,
-    0xFFu, 0xF7u, 0xC4u, 0xFFu, 0x1Au, 0x4Bu, 0x18u, 0x78u,
-    0x00u, 0x06u, 0x0Du, 0xD5u, 0x08u, 0xBDu, 0x00u, 0xF0u,
-    0x40u, 0x01u, 0xCBu, 0xB2u, 0x13u, 0xB1u, 0xFFu, 0xF7u,
-    0x71u, 0xFFu, 0x05u, 0xE0u, 0x00u, 0xF0u, 0x20u, 0x00u,
-    0xC2u, 0xB2u, 0x12u, 0xB3u, 0xFFu, 0xF7u, 0x96u, 0xFFu,
-    0x10u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x06u, 0x1Cu, 0xD4u,
-    0x10u, 0x4Bu, 0x11u, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u,
-    0x41u, 0xEAu, 0x00u, 0x03u, 0x0Fu, 0x48u, 0x03u, 0x70u,
-    0x02u, 0x78u, 0x93u, 0x42u, 0x11u, 0xD1u, 0x0Au, 0x49u,
-    0x08u, 0x4Bu, 0x0Au, 0x78u, 0x18u, 0x78u, 0x00u, 0xF0u,
-    0x80u, 0x00u, 0xC0u, 0xB2u, 0x20u, 0xB9u, 0x0Au, 0x78u,
-    0x1Au, 0x70u, 0x19u, 0x78u, 0x01u, 0xF0u, 0x0Fu, 0x02u,
-    0x03u, 0x4Bu, 0x18u, 0x78u, 0x82u, 0x42u, 0xEEu, 0xD1u,
-    0x08u, 0xBDu, 0x08u, 0xBDu, 0x28u, 0x60u, 0x00u, 0x40u,
-    0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,
+    0x85u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+    0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
+    0x1Au, 0x78u, 0x32u, 0xB1u, 0x19u, 0x78u, 0x09u, 0x4Au,
+    0x41u, 0xF0u, 0x80u, 0x01u, 0x11u, 0x70u, 0x00u, 0x22u,
+    0x1Au, 0x70u, 0x07u, 0x4Bu, 0x00u, 0x22u, 0x01u, 0x20u,
+    0x1Au, 0x70u, 0xFFu, 0xF7u, 0x6Bu, 0xFFu, 0x05u, 0x4Bu,
+    0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+    0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x04u, 0x2Bu,
+    0x05u, 0xD0u, 0x06u, 0x2Bu, 0x05u, 0xD0u, 0x02u, 0x2Bu,
+    0x05u, 0xD1u, 0xFFu, 0xF7u, 0xA1u, 0xBEu, 0xFFu, 0xF7u,
+    0xC5u, 0xBFu, 0xFFu, 0xF7u, 0xD3u, 0xBFu, 0x70u, 0x47u,
+    0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x1Du, 0x4Cu,
+    0x23u, 0x78u, 0xDBu, 0xB2u, 0xDAu, 0x06u, 0x33u, 0xD5u,
+    0x18u, 0x06u, 0x0Au, 0xD5u, 0x03u, 0xF0u, 0x0Fu, 0x03u,
+    0x01u, 0x2Bu, 0x2Du, 0xD1u, 0xFFu, 0xF7u, 0x4Eu, 0xFFu,
+    0x17u, 0x4Bu, 0x1Bu, 0x78u, 0x19u, 0x06u, 0x09u, 0xD5u,
+    0x10u, 0xBDu, 0x5Au, 0x06u, 0x02u, 0xD5u, 0xFFu, 0xF7u,
+    0xD7u, 0xFFu, 0x03u, 0xE0u, 0x9Bu, 0x06u, 0x1Fu, 0xD5u,
+    0xFFu, 0xF7u, 0x86u, 0xFFu, 0x23u, 0x78u, 0x1Bu, 0x06u,
+    0x1Au, 0xD4u, 0x10u, 0x4Bu, 0x10u, 0x4Au, 0x1Bu, 0x78u,
+    0x12u, 0x78u, 0x13u, 0x43u, 0x0Fu, 0x4Au, 0x13u, 0x70u,
+    0x12u, 0x78u, 0x93u, 0x42u, 0x10u, 0xD1u, 0x0Au, 0x4Bu,
+    0x08u, 0x49u, 0x1Au, 0x78u, 0x20u, 0x78u, 0xD2u, 0xB2u,
+    0x00u, 0x06u, 0x05u, 0xD4u, 0x1Au, 0x78u, 0xD2u, 0xB2u,
+    0x0Au, 0x70u, 0x0Au, 0x78u, 0x02u, 0xF0u, 0x0Fu, 0x02u,
+    0x1Bu, 0x78u, 0x9Au, 0x42u, 0xEFu, 0xD1u, 0x10u, 0xBDu,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,
+    0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,
     0x05u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x80u, 0x05u, 0x4Au,
     0x91u, 0x68u, 0x19u, 0xB1u, 0x91u, 0x68u, 0x0Bu, 0x70u,
-    0x90u, 0x68u, 0x43u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x0Cu, 0x49u, 0x0Cu, 0x4Bu, 0x04u, 0x22u,
-    0x80u, 0x20u, 0x1Au, 0x70u, 0x08u, 0x70u, 0xFFu, 0xF7u,
-    0xE7u, 0xFFu, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x58u, 0x1Eu,
-    0x09u, 0x4Bu, 0x01u, 0x78u, 0x18u, 0x88u, 0x41u, 0xEAu,
-    0x02u, 0x22u, 0x81u, 0xB2u, 0x91u, 0x42u, 0x88u, 0xBFu,
-    0x1Au, 0x80u, 0x06u, 0x4Bu, 0x0Bu, 0x22u, 0x1Au, 0x70u,
-    0x01u, 0x20u, 0x08u, 0xBDu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
-    0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
-    0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x98u, 0xB2u,
-    0x10u, 0xB9u, 0xFFu, 0xF7u, 0x5Bu, 0xFEu, 0x14u, 0xE0u,
-    0x0Cu, 0x49u, 0x0Du, 0x4Bu, 0x02u, 0x22u, 0x00u, 0x20u,
-    0x0Au, 0x70u, 0x18u, 0x70u, 0xFFu, 0xF7u, 0xBCu, 0xFFu,
-    0x0Au, 0x49u, 0x48u, 0x1Eu, 0x0Au, 0x78u, 0x03u, 0x78u,
-    0x43u, 0xEAu, 0x02u, 0x21u, 0x22u, 0x88u, 0x90u, 0xB2u,
-    0x88u, 0x42u, 0x88u, 0xBFu, 0x21u, 0x80u, 0xFFu, 0xF7u,
-    0xFBu, 0xFDu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
-    0x09u, 0x4Bu, 0x0Au, 0x48u, 0x1Bu, 0x78u, 0x02u, 0x7Bu,
-    0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x03u, 0xD0u,
-    0xC3u, 0x7Bu, 0x83u, 0xF0u, 0x80u, 0x02u, 0xC2u, 0x73u,
-    0x01u, 0x21u, 0x41u, 0x73u, 0x04u, 0x48u, 0x03u, 0x78u,
-    0x03u, 0xF0u, 0xFEu, 0x02u, 0x02u, 0x70u, 0x70u, 0x47u,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x0Au, 0x48u,
-    0x1Bu, 0x78u, 0x02u, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x01u,
-    0x01u, 0x29u, 0x03u, 0xD0u, 0xC3u, 0x7Eu, 0x83u, 0xF0u,
-    0x80u, 0x02u, 0xC2u, 0x76u, 0x01u, 0x21u, 0x41u, 0x76u,
-    0x04u, 0x48u, 0x03u, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x02u,
-    0x02u, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,
-    0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,
-    0x70u, 0x47u, 0xFFu, 0xF7u, 0xE7u, 0xBCu, 0x00u, 0x00u,
-    0x08u, 0xB5u, 0x0Bu, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,
-    0xC8u, 0xB2u, 0x00u, 0xF0u, 0x59u, 0xF9u, 0x09u, 0x4Au,
-    0x09u, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x68u, 0x06u, 0x4Bu, 0x50u, 0x6Au, 0x01u, 0x78u,
-    0x19u, 0x80u, 0x58u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x08u, 0xB5u, 0x0Du, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,
-    0xC8u, 0xB2u, 0x00u, 0xF0u, 0x39u, 0xF9u, 0x0Bu, 0x4Au,
-    0x0Bu, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,
-    0x42u, 0x68u, 0xD3u, 0x69u, 0x07u, 0x4Au, 0x59u, 0x78u,
-    0x13u, 0xF8u, 0x02u, 0x0Bu, 0x40u, 0xEAu, 0x01u, 0x21u,
-    0x11u, 0x80u, 0x53u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x10u, 0xB5u, 0x16u, 0x4Cu, 0x00u, 0x23u, 0x16u, 0x48u,
-    0x23u, 0x80u, 0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,
-    0x00u, 0xF0u, 0x12u, 0xF9u, 0x13u, 0x49u, 0x14u, 0x4Bu,
-    0x1Bu, 0x78u, 0x0Au, 0x78u, 0x00u, 0xEBu, 0xC2u, 0x00u,
-    0x41u, 0x69u, 0xD2u, 0xB9u, 0x11u, 0x4Au, 0x01u, 0x3Bu,
-    0x10u, 0x78u, 0xDAu, 0xB2u, 0x01u, 0xEBu, 0xC0u, 0x01u,
-    0x02u, 0x2Au, 0x49u, 0x68u, 0x11u, 0xD8u, 0x0Eu, 0x4Au,
-    0x01u, 0xEBu, 0xC3u, 0x00u, 0x12u, 0x78u, 0x11u, 0xF8u,
-    0x33u, 0x10u, 0x91u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u,
-    0x5Au, 0x43u, 0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u,
-    0x8Au, 0x5Au, 0x99u, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u,
-    0xA1u, 0x60u, 0x10u, 0xBDu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x03u, 0x60u, 0x00u, 0x40u, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Au, 0x4Bu,
-    0x3Au, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u, 0x09u, 0x06u,
-    0x34u, 0xD5u, 0x51u, 0x1Cu, 0x0Bu, 0x78u, 0x5Au, 0x1Eu,
-    0x05u, 0x2Au, 0x67u, 0xD8u, 0xDFu, 0xE8u, 0x02u, 0xF0u,
-    0x10u, 0x18u, 0x27u, 0x66u, 0x66u, 0x03u, 0x34u, 0x48u,
-    0x01u, 0x78u, 0x21u, 0x29u, 0x02u, 0xD1u, 0xFFu, 0xF7u,
-    0x6Bu, 0xFFu, 0x07u, 0xE0u, 0x03u, 0x78u, 0x22u, 0x2Bu,
-    0x58u, 0xD1u, 0xFFu, 0xF7u, 0x85u, 0xFFu, 0x01u, 0xE0u,
-    0xFFu, 0xF7u, 0xA6u, 0xFFu, 0x2Du, 0x49u, 0x0Bu, 0x88u,
-    0x98u, 0xB2u, 0x00u, 0x28u, 0x4Eu, 0xD0u, 0x0Au, 0xE0u,
-    0x00u, 0x28u, 0x4Bu, 0xD1u, 0x2Au, 0x4Bu, 0x18u, 0x78u,
-    0x00u, 0x28u, 0x47u, 0xD1u, 0x27u, 0x48u, 0x01u, 0x22u,
-    0x28u, 0x49u, 0x02u, 0x80u, 0x41u, 0x60u, 0xBDu, 0xE8u,
-    0x10u, 0x40u, 0xFFu, 0xF7u, 0xEDu, 0xBEu, 0x00u, 0x28u,
-    0x3Cu, 0xD1u, 0x22u, 0x48u, 0x01u, 0x22u, 0x02u, 0x80u,
-    0x23u, 0x49u, 0xF3u, 0xE7u, 0x13u, 0x78u, 0x1Au, 0x06u,
-    0x34u, 0xD4u, 0x22u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x29u,
-    0x05u, 0xD0u, 0x2Fu, 0xD3u, 0x0Au, 0x29u, 0x0Du, 0xD0u,
-    0x0Bu, 0x29u, 0x2Bu, 0xD1u, 0x22u, 0xE0u, 0xFFu, 0xF7u,
-    0x7Bu, 0xFFu, 0x18u, 0x4Bu, 0x1Au, 0x88u, 0x90u, 0xB2u,
-    0x00u, 0x28u, 0x23u, 0xD0u, 0xBDu, 0xE8u, 0x10u, 0x40u,
-    0xFFu, 0xF7u, 0xAAu, 0xBEu, 0xF0u, 0xB9u, 0x14u, 0x48u,
-    0x01u, 0x78u, 0xD9u, 0xB9u, 0x44u, 0x1Cu, 0x23u, 0x78u,
-    0x12u, 0x4Au, 0x13u, 0x70u, 0x14u, 0x4Bu, 0x14u, 0x78u,
-    0x18u, 0x78u, 0x84u, 0x42u, 0x01u, 0xD2u, 0x19u, 0x70u,
-    0x04u, 0xE0u, 0x19u, 0x78u, 0x01u, 0x29u, 0x01u, 0xD9u,
-    0x12u, 0x78u, 0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u,
-    0xFFu, 0xF7u, 0x6Cu, 0xBDu, 0x30u, 0xB9u, 0x08u, 0x48u,
-    0x03u, 0x78u, 0x01u, 0x2Bu, 0x02u, 0xD8u, 0x02u, 0x78u,
-    0x07u, 0x4Bu, 0xF2u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,
+    0x92u, 0x68u, 0x53u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,
+    0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x9Bu, 0xB2u,
+    0x13u, 0xB9u, 0xFFu, 0xF7u, 0x85u, 0xFEu, 0x14u, 0xE0u,
+    0x0Cu, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x0Cu, 0x4Bu,
+    0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xE0u, 0xFFu,
+    0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x3Bu, 0x1Bu, 0x78u,
+    0x43u, 0xEAu, 0x02u, 0x23u, 0x22u, 0x88u, 0x92u, 0xB2u,
+    0x9Au, 0x42u, 0x88u, 0xBFu, 0x23u, 0x80u, 0xFFu, 0xF7u,
+    0x27u, 0xFEu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
+    0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,
+    0x0Bu, 0x4Bu, 0x80u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u,
+    0xBFu, 0xFFu, 0x0Au, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x78u,
+    0x01u, 0x3Bu, 0x1Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x22u,
+    0x07u, 0x4Bu, 0x19u, 0x88u, 0x89u, 0xB2u, 0x91u, 0x42u,
+    0x88u, 0xBFu, 0x1Au, 0x80u, 0x05u, 0x4Bu, 0x0Bu, 0x22u,
+    0x1Au, 0x70u, 0x08u, 0xBDu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+    0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+    0x09u, 0x4Bu, 0x1Bu, 0x78u, 0x09u, 0x4Bu, 0x1Au, 0x7Bu,
+    0x02u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au, 0x03u, 0xD0u,
+    0xDAu, 0x7Bu, 0x82u, 0xF0u, 0x80u, 0x02u, 0xDAu, 0x73u,
+    0x01u, 0x22u, 0x5Au, 0x73u, 0x04u, 0x4Bu, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,
+    0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x1Bu, 0x78u,
+    0x09u, 0x4Bu, 0x1Au, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x02u,
+    0x01u, 0x2Au, 0x03u, 0xD0u, 0xDAu, 0x7Eu, 0x82u, 0xF0u,
+    0x80u, 0x02u, 0xDAu, 0x76u, 0x01u, 0x22u, 0x5Au, 0x76u,
+    0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFDu, 0x02u,
+    0x1Au, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,
+    0x70u, 0x47u, 0xFFu, 0xF7u, 0xEBu, 0xBCu, 0x00u, 0x00u,
+    0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,
+    0xC0u, 0xB2u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x0Au, 0x4Bu,
+    0x0Au, 0x49u, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xEBu,
+    0xC3u, 0x00u, 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu,
+    0xC3u, 0x03u, 0x5Bu, 0x68u, 0x5Au, 0x6Au, 0x06u, 0x4Bu,
+    0x11u, 0x78u, 0xC9u, 0xB2u, 0x19u, 0x80u, 0x5Au, 0x60u,
+    0x08u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Du, 0x4Bu,
+    0x18u, 0x78u, 0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u,
+    0x29u, 0xF9u, 0x0Bu, 0x4Bu, 0x0Bu, 0x49u, 0x1Bu, 0x78u,
+    0xDBu, 0xB2u, 0x00u, 0xEBu, 0xC3u, 0x00u, 0x42u, 0x69u,
+    0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x03u, 0x5Bu, 0x68u,
+    0xDBu, 0x69u, 0x59u, 0x78u, 0x13u, 0xF8u, 0x02u, 0x2Bu,
+    0x42u, 0xEAu, 0x01u, 0x21u, 0x04u, 0x4Au, 0x11u, 0x80u,
+    0x53u, 0x60u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x19u, 0x4Cu,
+    0x00u, 0x23u, 0x23u, 0x80u, 0x18u, 0x4Bu, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u, 0x02u, 0xF9u,
+    0x16u, 0x4Bu, 0x17u, 0x4Au, 0x1Bu, 0x78u, 0x12u, 0x78u,
+    0xDBu, 0xB2u, 0xD2u, 0xB2u, 0x00u, 0xEBu, 0xC2u, 0x00u,
+    0x41u, 0x69u, 0xEAu, 0xB9u, 0x13u, 0x4Au, 0x12u, 0x78u,
+    0x01u, 0xEBu, 0xC2u, 0x02u, 0x51u, 0x68u, 0x5Au, 0x1Eu,
+    0x02u, 0x2Au, 0x15u, 0xD8u, 0x10u, 0x4Au, 0x03u, 0xF1u,
+    0x00u, 0x53u, 0x01u, 0x3Bu, 0x12u, 0x78u, 0x01u, 0xEBu,
+    0xC3u, 0x00u, 0x11u, 0xF8u, 0x33u, 0x30u, 0xD2u, 0xB2u,
+    0x93u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u, 0x5Au, 0x43u,
+    0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u, 0x8Au, 0x5Au,
+    0x9Bu, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u, 0xA3u, 0x60u,
+    0x10u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x03u, 0x60u, 0x00u, 0x40u,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Cu, 0x4Bu,
+    0x3Cu, 0x4Au, 0x1Bu, 0x78u, 0x11u, 0x78u, 0xDBu, 0xB2u,
+    0x09u, 0x06u, 0x34u, 0xD5u, 0x01u, 0x32u, 0x12u, 0x78u,
+    0x01u, 0x3Au, 0x05u, 0x2Au, 0x6Au, 0xD8u, 0xDFu, 0xE8u,
+    0x02u, 0xF0u, 0x10u, 0x18u, 0x27u, 0x69u, 0x69u, 0x03u,
+    0x35u, 0x4Bu, 0x1Au, 0x78u, 0x21u, 0x2Au, 0x02u, 0xD1u,
+    0xFFu, 0xF7u, 0x62u, 0xFFu, 0x07u, 0xE0u, 0x1Bu, 0x78u,
+    0x22u, 0x2Bu, 0x5Bu, 0xD1u, 0xFFu, 0xF7u, 0x7Eu, 0xFFu,
+    0x01u, 0xE0u, 0xFFu, 0xF7u, 0x9Fu, 0xFFu, 0x2Fu, 0x4Bu,
+    0x1Bu, 0x88u, 0x9Bu, 0xB2u, 0x00u, 0x2Bu, 0x51u, 0xD0u,
+    0x0Au, 0xE0u, 0x00u, 0x2Bu, 0x4Eu, 0xD1u, 0x2Cu, 0x4Bu,
+    0x1Bu, 0x78u, 0x00u, 0x2Bu, 0x4Au, 0xD1u, 0x29u, 0x4Bu,
+    0x01u, 0x22u, 0x1Au, 0x80u, 0x29u, 0x4Au, 0x5Au, 0x60u,
+    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xC0u, 0xBEu,
+    0x00u, 0x2Bu, 0x3Fu, 0xD1u, 0x23u, 0x4Bu, 0x01u, 0x22u,
+    0x1Au, 0x80u, 0x25u, 0x4Au, 0xF3u, 0xE7u, 0x12u, 0x78u,
+    0x12u, 0x06u, 0x37u, 0xD4u, 0x23u, 0x4Au, 0x12u, 0x78u,
+    0xD2u, 0xB2u, 0x0Au, 0x2Au, 0x0Du, 0xD0u, 0x0Bu, 0x2Au,
+    0x27u, 0xD0u, 0x09u, 0x2Au, 0x2Eu, 0xD1u, 0xFFu, 0xF7u,
+    0x75u, 0xFFu, 0x1Au, 0x4Bu, 0x1Bu, 0x88u, 0x9Bu, 0xB2u,
+    0x43u, 0xB3u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
+    0xCBu, 0xBEu, 0x1Bu, 0xBBu, 0x16u, 0x4Bu, 0x1Bu, 0x78u,
+    0x03u, 0xF0u, 0xFFu, 0x01u, 0xF3u, 0xB9u, 0x12u, 0x4Bu,
+    0x14u, 0x4Au, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x13u, 0x70u,
+    0x15u, 0x4Bu, 0x14u, 0x78u, 0x18u, 0x78u, 0x84u, 0x42u,
+    0x01u, 0xD2u, 0x19u, 0x70u, 0x05u, 0xE0u, 0x19u, 0x78u,
+    0x01u, 0x29u, 0x02u, 0xD9u, 0x12u, 0x78u, 0xD2u, 0xB2u,
+    0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
+    0x67u, 0xBDu, 0x3Bu, 0xB9u, 0x08u, 0x4Bu, 0x1Au, 0x78u,
+    0x01u, 0x2Au, 0x03u, 0xD8u, 0x1Au, 0x78u, 0x08u, 0x4Bu,
+    0xD2u, 0xB2u, 0xF1u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,
     0x04u, 0x60u, 0x00u, 0x40u, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x03u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
-    0x02u, 0x60u, 0x00u, 0x40u, 0xEAu, 0xC1u, 0xFFu, 0x1Fu,
-    0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,
-    0xEBu, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x01u, 0x22u,
-    0x02u, 0xF1u, 0x0Fu, 0x03u, 0x18u, 0x01u, 0x09u, 0x2Au,
-    0xC3u, 0xB2u, 0x3Bu, 0xD0u, 0x1Fu, 0x49u, 0x03u, 0xF1u,
-    0x80u, 0x44u, 0x0Cu, 0x20u, 0x04u, 0xF5u, 0xC1u, 0x45u,
-    0x00u, 0xFBu, 0x02u, 0x14u, 0x28u, 0x70u, 0x1Cu, 0x49u,
-    0x65u, 0x79u, 0x59u, 0x18u, 0x25u, 0xB1u, 0x24u, 0x79u,
-    0x24u, 0x06u, 0x58u, 0xBFu, 0x08u, 0x20u, 0x00u, 0xE0u,
-    0x80u, 0x20u, 0x08u, 0x70u, 0x17u, 0x49u, 0x0Cu, 0x24u,
-    0x58u, 0x18u, 0x14u, 0x49u, 0x04u, 0xFBu, 0x02u, 0x11u,
-    0x0Cu, 0x89u, 0x01u, 0x32u, 0xC4u, 0xF3u, 0x07u, 0x24u,
-    0x04u, 0x70u, 0x0Cu, 0x89u, 0x12u, 0x48u, 0xE4u, 0xB2u,
-    0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u, 0x11u, 0x48u,
-    0xE4u, 0xB2u, 0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u,
-    0x0Fu, 0x48u, 0xC4u, 0xF3u, 0x07u, 0x24u, 0x18u, 0x18u,
-    0x04u, 0x70u, 0xCCu, 0x88u, 0x0Du, 0x48u, 0xE4u, 0xB2u,
-    0x18u, 0x18u, 0x04u, 0x70u, 0x0Cu, 0x48u, 0xD2u, 0xB2u,
-    0x18u, 0x18u, 0xCBu, 0x88u, 0xC3u, 0xF3u, 0x07u, 0x21u,
-    0x01u, 0x70u, 0xBDu, 0xE7u, 0x09u, 0x49u, 0xFFu, 0x22u,
-    0x0Au, 0x70u, 0x30u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,
-    0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,
-    0x85u, 0x60u, 0x00u, 0x40u, 0x0Au, 0x60u, 0x00u, 0x40u,
-    0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu,
-    0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u,
-    0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0xF8u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,
-    0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u,
-    0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu,
-    0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u,
-    0xA8u, 0x42u, 0x69u, 0xD0u, 0x13u, 0xF8u, 0x08u, 0x2Cu,
-    0x35u, 0x49u, 0x36u, 0x4Cu, 0x8Eu, 0x5Cu, 0xA4u, 0x5Cu,
-    0xA6u, 0x42u, 0x5Du, 0xD0u, 0x89u, 0x5Cu, 0x13u, 0xF8u,
-    0x07u, 0x4Cu, 0x8Cu, 0x42u, 0x58u, 0xD1u, 0x32u, 0x49u,
-    0x09u, 0x78u, 0x8Au, 0x42u, 0x54u, 0xD1u, 0x13u, 0xF8u,
-    0x06u, 0x7Cu, 0x07u, 0xF0u, 0x7Fu, 0x02u, 0x56u, 0x1Eu,
-    0x34u, 0x01u, 0xE1u, 0xB2u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
-    0x2Cu, 0x4Cu, 0x17u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,
-    0x0Cu, 0x07u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu,
-    0x02u, 0x44u, 0x06u, 0xD0u, 0x01u, 0x27u, 0x67u, 0x70u,
-    0xBEu, 0x42u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,
-    0x05u, 0xE0u, 0x00u, 0x27u, 0x67u, 0x70u, 0x01u, 0x2Eu,
-    0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x66u, 0x71u,
-    0x21u, 0x4Cu, 0x01u, 0x26u, 0x0Fu, 0x19u, 0x0Cu, 0x24u,
-    0x54u, 0x43u, 0x3Eu, 0x70u, 0x1Du, 0x4Eu, 0x33u, 0xF8u,
-    0x04u, 0x7Cu, 0x32u, 0x19u, 0x17u, 0x81u, 0x13u, 0xF8u,
-    0x06u, 0x7Cu, 0x17u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x7Cu,
-    0x37u, 0x55u, 0x00u, 0x26u, 0xD6u, 0x70u, 0x16u, 0x89u,
-    0x18u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,
-    0x26u, 0x70u, 0x16u, 0x89u, 0x16u, 0x4Cu, 0xF6u, 0xB2u,
-    0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u, 0x15u, 0x4Cu,
-    0xF6u, 0xB2u, 0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u,
-    0x13u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,
-    0x26u, 0x70u, 0xD6u, 0x88u, 0x11u, 0x4Cu, 0xF6u, 0xB2u,
-    0x0Cu, 0x19u, 0x26u, 0x70u, 0x10u, 0x4Cu, 0x0Cu, 0x19u,
-    0xD1u, 0x88u, 0xC1u, 0xF3u, 0x07u, 0x22u, 0x22u, 0x70u,
-    0x01u, 0x30u, 0xC0u, 0xB2u, 0x08u, 0x33u, 0x93u, 0xE7u,
-    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
+    0x03u, 0x60u, 0x00u, 0x40u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x02u, 0x60u, 0x00u, 0x40u, 0xE2u, 0xC1u, 0xFFu, 0x1Fu,
+    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,
+    0xE3u, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x1Cu, 0x4Bu,
+    0x01u, 0x21u, 0x1Cu, 0x4Au, 0x0Cu, 0x20u, 0x00u, 0xFBu,
+    0x01u, 0x24u, 0x83u, 0xF8u, 0x72u, 0x00u, 0x65u, 0x79u,
+    0x25u, 0xB1u, 0x24u, 0x79u, 0x24u, 0x06u, 0x58u, 0xBFu,
+    0x08u, 0x20u, 0x00u, 0xE0u, 0x80u, 0x20u, 0x18u, 0x70u,
+    0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x22u, 0x10u, 0x89u,
+    0x01u, 0x31u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x03u, 0xF8u,
+    0x02u, 0x0Cu, 0x10u, 0x89u, 0x09u, 0x29u, 0xC0u, 0xB2u,
+    0x03u, 0xF8u, 0x01u, 0x0Cu, 0xD0u, 0x88u, 0x03u, 0xF1u,
+    0x10u, 0x03u, 0xC0u, 0xB2u, 0x83u, 0xF8u, 0x68u, 0x00u,
+    0xD0u, 0x88u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x83u, 0xF8u,
+    0x69u, 0x00u, 0xD0u, 0x88u, 0xC0u, 0xB2u, 0x83u, 0xF8u,
+    0x66u, 0x00u, 0xD2u, 0x88u, 0xC2u, 0xF3u, 0x07u, 0x22u,
+    0x83u, 0xF8u, 0x67u, 0x20u, 0xCDu, 0xD1u, 0x04u, 0x4Bu,
+    0xFFu, 0x22u, 0x1Au, 0x70u, 0x30u, 0xBDu, 0x00u, 0xBFu,
+    0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x0Au, 0x60u, 0x00u, 0x40u, 0x07u, 0x4Bu, 0x1Au, 0x78u,
+    0x07u, 0x4Bu, 0x03u, 0xEBu, 0xC2u, 0x03u, 0x5Bu, 0x68u,
+    0x03u, 0xF1u, 0x08u, 0x02u, 0x1Bu, 0x7Au, 0x83u, 0x42u,
+    0x86u, 0xBFu, 0x02u, 0xEBu, 0xC0u, 0x00u, 0x40u, 0x68u,
+    0x00u, 0x20u, 0x70u, 0x47u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+    0xB8u, 0x21u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x39u, 0x4Bu,
+    0x1Au, 0x78u, 0x00u, 0x2Au, 0x6Cu, 0xD0u, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0xE2u, 0xFFu,
+    0xC3u, 0x68u, 0x04u, 0x7Au, 0x08u, 0x33u, 0x03u, 0xEBu,
+    0xC4u, 0x04u, 0xA3u, 0x42u, 0x60u, 0xD0u, 0x13u, 0xF8u,
+    0x08u, 0x2Cu, 0x31u, 0x49u, 0x31u, 0x48u, 0x8Du, 0x5Cu,
+    0x80u, 0x5Cu, 0x85u, 0x42u, 0x56u, 0xD0u, 0x89u, 0x5Cu,
+    0x13u, 0xF8u, 0x07u, 0x0Cu, 0x88u, 0x42u, 0x51u, 0xD1u,
+    0x2Du, 0x49u, 0x09u, 0x78u, 0x8Au, 0x42u, 0x4Du, 0xD1u,
+    0x13u, 0xF8u, 0x06u, 0x0Cu, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+    0x00u, 0xF0u, 0x7Fu, 0x02u, 0x51u, 0x1Eu, 0x10u, 0xF0u,
+    0x80u, 0x0Fu, 0x28u, 0x48u, 0x4Fu, 0xEAu, 0x01u, 0x11u,
+    0x4Fu, 0xF0u, 0x0Cu, 0x05u, 0xC9u, 0xB2u, 0x06u, 0xF0u,
+    0x03u, 0x06u, 0x05u, 0xFBu, 0x02u, 0x05u, 0x06u, 0xD0u,
+    0x01u, 0x27u, 0xBEu, 0x42u, 0x6Fu, 0x70u, 0x14u, 0xBFu,
+    0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u, 0x00u, 0x27u,
+    0x01u, 0x2Eu, 0x6Fu, 0x70u, 0x14u, 0xBFu, 0x09u, 0x26u,
+    0x05u, 0x26u, 0x6Eu, 0x71u, 0x1Cu, 0x4Du, 0x01u, 0x26u,
+    0x6Eu, 0x54u, 0x0Cu, 0x25u, 0x55u, 0x43u, 0x33u, 0xF8u,
+    0x04u, 0x6Cu, 0x42u, 0x19u, 0x16u, 0x81u, 0x13u, 0xF8u,
+    0x06u, 0x6Cu, 0x16u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+    0x46u, 0x55u, 0x00u, 0x20u, 0xD0u, 0x70u, 0x15u, 0x89u,
+    0x14u, 0x48u, 0xC5u, 0xF3u, 0x07u, 0x25u, 0x45u, 0x54u,
+    0x15u, 0x89u, 0x01u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,
+    0xD5u, 0x88u, 0x79u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,
+    0xD5u, 0x88u, 0x01u, 0x30u, 0xC5u, 0xF3u, 0x07u, 0x25u,
+    0x45u, 0x54u, 0xD5u, 0x88u, 0x03u, 0x38u, 0xEDu, 0xB2u,
+    0x45u, 0x54u, 0xD2u, 0x88u, 0x01u, 0x30u, 0xC2u, 0xF3u,
+    0x07u, 0x22u, 0x42u, 0x54u, 0x08u, 0x33u, 0x9Cu, 0xE7u,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
     0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
-    0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,
-    0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,
-    0x85u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x06u, 0x4Bu,
-    0x18u, 0x78u, 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u,
-    0x57u, 0xFFu, 0x42u, 0x68u, 0x13u, 0x79u, 0x00u, 0xEBu,
-    0xC3u, 0x00u, 0x40u, 0x69u, 0x08u, 0xBDu, 0x00u, 0xBFu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0x00u, 0x21u,
-    0x0Cu, 0x24u, 0x4Cu, 0x43u, 0x51u, 0x4Du, 0x01u, 0x31u,
-    0x00u, 0x23u, 0x2Au, 0x19u, 0x09u, 0x29u, 0x2Bu, 0x55u,
-    0x93u, 0x70u, 0x02u, 0xF1u, 0x08u, 0x04u, 0x53u, 0x70u,
+    0x08u, 0xB5u, 0x06u, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,
+    0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x63u, 0xFFu, 0x20u, 0xB1u,
+    0x43u, 0x68u, 0x1Bu, 0x79u, 0x00u, 0xEBu, 0xC3u, 0x00u,
+    0x40u, 0x69u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0xF8u, 0xB5u, 0x00u, 0x21u, 0x0Cu, 0x25u, 0x4Du, 0x43u,
+    0x4Cu, 0x4Cu, 0x01u, 0x31u, 0x00u, 0x23u, 0x62u, 0x19u,
+    0x09u, 0x29u, 0x63u, 0x55u, 0x93u, 0x70u, 0x53u, 0x70u,
     0xD3u, 0x70u, 0x53u, 0x71u, 0x13u, 0x81u, 0x93u, 0x72u,
-    0xEEu, 0xD1u, 0x18u, 0xB1u, 0x4Au, 0x48u, 0x4Bu, 0x4Au,
-    0x03u, 0x70u, 0x13u, 0x70u, 0x4Au, 0x4Bu, 0x19u, 0x78u,
-    0x00u, 0x29u, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x1Cu, 0x78u,
-    0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x2Cu, 0xFFu,
-    0x42u, 0x68u, 0xD3u, 0x79u, 0x03u, 0xF0u, 0x40u, 0x01u,
-    0xCCu, 0xB2u, 0x44u, 0x4Bu, 0x1Cu, 0xB1u, 0x1Cu, 0x78u,
-    0x44u, 0xF0u, 0x01u, 0x01u, 0x02u, 0xE0u, 0x1Au, 0x78u,
-    0x02u, 0xF0u, 0xFEu, 0x01u, 0x04u, 0x7Au, 0x19u, 0x70u,
-    0x01u, 0x22u, 0xC3u, 0x68u, 0x00u, 0x21u, 0x08u, 0x33u,
-    0xA1u, 0x42u, 0x43u, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,
-    0x05u, 0xF0u, 0x7Fu, 0x06u, 0xB2u, 0x42u, 0x39u, 0xD1u,
-    0x34u, 0x4Eu, 0x0Cu, 0x27u, 0x07u, 0xFBu, 0x02u, 0x66u,
-    0xB6u, 0xF8u, 0x08u, 0xE0u, 0x33u, 0xF8u, 0x04u, 0x7Cu,
-    0x1Fu, 0xFAu, 0x8Eu, 0xFCu, 0xBCu, 0x45u, 0x38u, 0xBFu,
-    0x37u, 0x81u, 0x13u, 0xF8u, 0x08u, 0x6Cu, 0x2Eu, 0x4Fu,
-    0xBEu, 0x5Du, 0x13u, 0xF8u, 0x07u, 0x7Cu, 0xB7u, 0x42u,
-    0x24u, 0xD1u, 0x13u, 0xF8u, 0x05u, 0x6Cu, 0x15u, 0xF0u,
-    0x80u, 0x0Fu, 0x28u, 0x4Du, 0x4Fu, 0xF0u, 0x0Cu, 0x07u,
-    0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu, 0x02u, 0x55u,
-    0x06u, 0xD0u, 0x01u, 0x27u, 0x6Fu, 0x70u, 0xBEu, 0x42u,
-    0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u,
-    0x00u, 0x27u, 0x6Fu, 0x70u, 0x01u, 0x2Eu, 0x14u, 0xBFu,
-    0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u, 0x0Cu, 0x25u,
-    0x55u, 0x43u, 0x1Cu, 0x4Eu, 0x13u, 0xF8u, 0x06u, 0xECu,
-    0x77u, 0x19u, 0x87u, 0xF8u, 0x04u, 0xE0u, 0x13u, 0xF8u,
-    0x05u, 0x7Cu, 0x77u, 0x55u, 0x01u, 0x31u, 0xC9u, 0xB2u,
-    0x08u, 0x33u, 0xB9u, 0xE7u, 0x01u, 0x32u, 0x09u, 0x2Au,
-    0xB3u, 0xD1u, 0xC3u, 0x68u, 0x00u, 0x22u, 0x08u, 0x33u,
-    0xA2u, 0x42u, 0x0Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,
-    0x0Cu, 0x26u, 0x05u, 0xF0u, 0x7Fu, 0x01u, 0x0Fu, 0x4Du,
-    0x13u, 0xF8u, 0x08u, 0x0Cu, 0x06u, 0xFBu, 0x01u, 0x51u,
-    0x01u, 0x32u, 0x88u, 0x72u, 0xD2u, 0xB2u, 0xEEu, 0xE7u,
-    0xFFu, 0xF7u, 0x5Cu, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,
-    0x18u, 0x60u, 0x01u, 0x23u, 0x07u, 0x49u, 0x0Cu, 0x20u,
-    0x00u, 0xFBu, 0x03u, 0x10u, 0xC2u, 0x80u, 0x01u, 0x89u,
-    0x01u, 0x33u, 0x52u, 0x18u, 0x09u, 0x2Bu, 0x92u, 0xB2u,
-    0xF4u, 0xD1u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,
-    0x4Du, 0xBEu, 0xF8u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Fu, 0xC1u, 0xFFu, 0x1Fu,
-    0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x12u, 0x4Bu, 0x19u, 0x78u,
-    0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,
-    0x07u, 0x28u, 0x1Au, 0xD8u, 0x03u, 0x01u, 0xDAu, 0xB2u,
-    0x0Eu, 0x4Bu, 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x30u,
-    0x81u, 0x78u, 0x41u, 0xF0u, 0x01u, 0x03u, 0x00u, 0x21u,
-    0x83u, 0x70u, 0xC1u, 0x70u, 0x43u, 0x78u, 0x43u, 0xF0u,
-    0x02u, 0x01u, 0x41u, 0x70u, 0x00u, 0x79u, 0x08u, 0x4Bu,
-    0x10u, 0xF0u, 0x80u, 0x0Fu, 0x01u, 0xD0u, 0x8Du, 0x21u,
-    0x00u, 0xE0u, 0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u,
-    0x6Du, 0xBBu, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x1Au, 0x4Bu,
-    0x18u, 0x78u, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x5Au, 0x1Eu,
-    0xD2u, 0xB2u, 0x07u, 0x2Au, 0x2Au, 0xD8u, 0x17u, 0x49u,
-    0x0Cu, 0x20u, 0x00u, 0xFBu, 0x03u, 0x13u, 0x9Cu, 0x78u,
-    0x12u, 0x01u, 0x04u, 0xF0u, 0xFEu, 0x01u, 0x99u, 0x70u,
-    0x00u, 0x24u, 0x13u, 0x49u, 0xDCu, 0x70u, 0xD2u, 0xB2u,
-    0x54u, 0x5Cu, 0x04u, 0xF0u, 0x7Fu, 0x04u, 0x54u, 0x54u,
-    0x59u, 0x78u, 0x01u, 0xF0u, 0xFDu, 0x01u, 0x59u, 0x70u,
-    0x19u, 0x79u, 0x5Bu, 0x78u, 0x11u, 0xF0u, 0x80u, 0x0Fu,
-    0x0Cu, 0x49u, 0x05u, 0xD0u, 0x01u, 0x2Bu, 0x01u, 0xD1u,
-    0x50u, 0x54u, 0x07u, 0xE0u, 0x0Du, 0x20u, 0x04u, 0xE0u,
-    0x01u, 0x2Bu, 0x01u, 0xD1u, 0x08u, 0x20u, 0x00u, 0xE0u,
-    0x09u, 0x20u, 0x50u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u,
-    0xFFu, 0xF7u, 0x30u, 0xBBu, 0x00u, 0x20u, 0x10u, 0xBDu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,
-    0x10u, 0xB5u, 0x0Cu, 0x4Bu, 0x0Cu, 0x48u, 0x1Cu, 0x78u,
-    0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u, 0xFFu, 0xF7u,
-    0x27u, 0xFEu, 0x43u, 0x68u, 0x18u, 0x79u, 0xA0u, 0x42u,
-    0x09u, 0xD9u, 0x44u, 0xB9u, 0x07u, 0x4Bu, 0x08u, 0x4Au,
-    0x19u, 0x78u, 0x08u, 0x48u, 0x11u, 0x70u, 0x01u, 0x78u,
-    0x01u, 0x20u, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0x20u,
+    0xF0u, 0xD1u, 0x18u, 0xB1u, 0x46u, 0x4Au, 0x13u, 0x70u,
+    0x46u, 0x4Au, 0x13u, 0x70u, 0x46u, 0x4Bu, 0x1Au, 0x78u,
+    0x00u, 0x2Au, 0x00u, 0xF0u, 0x81u, 0x80u, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Au, 0xFFu,
+    0x43u, 0x68u, 0x01u, 0x7Au, 0xDBu, 0x79u, 0xC9u, 0x00u,
+    0x13u, 0xF0u, 0x40u, 0x0Fu, 0x3Fu, 0x4Bu, 0x1Au, 0x78u,
+    0x14u, 0xBFu, 0x42u, 0xF0u, 0x01u, 0x02u, 0x02u, 0xF0u,
+    0xFEu, 0x02u, 0x1Au, 0x70u, 0x01u, 0x22u, 0xC3u, 0x68u,
+    0x08u, 0x33u, 0x03u, 0xEBu, 0x01u, 0x0Eu, 0x73u, 0x45u,
+    0x3Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu, 0x05u, 0xF0u,
+    0x7Fu, 0x06u, 0xB2u, 0x42u, 0x35u, 0xD1u, 0x0Cu, 0x26u,
+    0x06u, 0xFBu, 0x02u, 0x46u, 0xB6u, 0xF8u, 0x08u, 0xC0u,
+    0x33u, 0xF8u, 0x04u, 0x7Cu, 0x1Fu, 0xFAu, 0x8Cu, 0xFCu,
+    0xBCu, 0x45u, 0x38u, 0xBFu, 0x37u, 0x81u, 0x13u, 0xF8u,
+    0x08u, 0x6Cu, 0x2Bu, 0x4Fu, 0xBEu, 0x5Du, 0x13u, 0xF8u,
+    0x07u, 0x7Cu, 0xB7u, 0x42u, 0x21u, 0xD1u, 0x13u, 0xF8u,
+    0x05u, 0x6Cu, 0x15u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,
+    0x0Cu, 0x05u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x05u, 0xFBu,
+    0x02u, 0x45u, 0x06u, 0xD0u, 0x01u, 0x27u, 0xBEu, 0x42u,
+    0x6Fu, 0x70u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,
+    0x05u, 0xE0u, 0x00u, 0x27u, 0x01u, 0x2Eu, 0x6Fu, 0x70u,
+    0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u,
+    0x0Cu, 0x25u, 0x55u, 0x43u, 0x13u, 0xF8u, 0x06u, 0x7Cu,
+    0x66u, 0x19u, 0x37u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+    0x66u, 0x55u, 0x08u, 0x33u, 0xBFu, 0xE7u, 0x01u, 0x32u,
+    0x09u, 0x2Au, 0xB8u, 0xD1u, 0xC3u, 0x68u, 0x03u, 0xF1u,
+    0x08u, 0x02u, 0x11u, 0x44u, 0x08u, 0x33u, 0x8Bu, 0x42u,
+    0x0Au, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x2Cu, 0x0Cu, 0x25u,
+    0x02u, 0xF0u, 0x7Fu, 0x02u, 0x05u, 0xFBu, 0x02u, 0x42u,
+    0x13u, 0xF8u, 0x08u, 0x0Cu, 0x90u, 0x72u, 0xF1u, 0xE7u,
+    0xFFu, 0xF7u, 0x66u, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,
+    0x18u, 0x60u, 0x01u, 0x23u, 0x0Cu, 0x21u, 0x01u, 0xFBu,
+    0x03u, 0x41u, 0xCAu, 0x80u, 0x09u, 0x89u, 0x01u, 0x33u,
+    0x0Au, 0x44u, 0x09u, 0x2Bu, 0x92u, 0xB2u, 0xF5u, 0xD1u,
+    0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u, 0x7Eu, 0xBEu,
+    0xF8u, 0xBDu, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x67u, 0xC1u, 0xFFu, 0x1Fu,
+    0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x11u, 0x4Bu, 0x19u, 0x78u,
+    0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD2u, 0xB2u,
+    0x07u, 0x2Au, 0x19u, 0xD8u, 0x0Eu, 0x4Bu, 0x0Cu, 0x20u,
+    0x00u, 0xFBu, 0x01u, 0x33u, 0x99u, 0x78u, 0x12u, 0x01u,
+    0x41u, 0xF0u, 0x01u, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u,
+    0xD9u, 0x70u, 0x59u, 0x78u, 0xD2u, 0xB2u, 0x41u, 0xF0u,
+    0x02u, 0x01u, 0x59u, 0x70u, 0x1Bu, 0x79u, 0x13u, 0xF0u,
+    0x80u, 0x0Fu, 0x06u, 0x4Bu, 0x14u, 0xBFu, 0x8Du, 0x21u,
+    0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u, 0x98u, 0xBBu,
+    0x00u, 0x20u, 0x70u, 0x47u, 0x04u, 0x60u, 0x00u, 0x40u,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Eu, 0x60u, 0x00u, 0x40u,
+    0x10u, 0xB5u, 0x1Au, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+    0x7Fu, 0x03u, 0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0x07u, 0x2Au,
+    0x29u, 0xD8u, 0x17u, 0x49u, 0x0Cu, 0x20u, 0x00u, 0xFBu,
+    0x03u, 0x13u, 0x99u, 0x78u, 0x12u, 0x01u, 0x01u, 0xF0u,
+    0xFEu, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u, 0xD9u, 0x70u,
+    0x12u, 0x49u, 0xD2u, 0xB2u, 0x54u, 0x5Cu, 0x04u, 0xF0u,
+    0x7Fu, 0x04u, 0x54u, 0x54u, 0x59u, 0x78u, 0x01u, 0xF0u,
+    0xFDu, 0x01u, 0x59u, 0x70u, 0x19u, 0x79u, 0x5Bu, 0x78u,
+    0x11u, 0xF0u, 0x80u, 0x0Fu, 0x0Cu, 0x49u, 0x05u, 0xD0u,
+    0x01u, 0x2Bu, 0x01u, 0xD1u, 0x50u, 0x54u, 0x06u, 0xE0u,
+    0x0Du, 0x23u, 0x03u, 0xE0u, 0x01u, 0x2Bu, 0x0Cu, 0xBFu,
+    0x08u, 0x23u, 0x09u, 0x23u, 0x53u, 0x54u, 0xBDu, 0xE8u,
+    0x10u, 0x40u, 0xFFu, 0xF7u, 0x5Du, 0xBBu, 0x00u, 0x20u,
     0x10u, 0xBDu, 0x00u, 0xBFu, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,
-    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,
-    0x10u, 0xB5u, 0x7Cu, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x80u,
-    0x7Bu, 0x4Au, 0x7Cu, 0x48u, 0x11u, 0x78u, 0x11u, 0xF0u,
-    0x80u, 0x0Fu, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x01u, 0x78u,
-    0x0Au, 0x29u, 0x00u, 0xF2u, 0x22u, 0x81u, 0xDFu, 0xE8u,
-    0x11u, 0xF0u, 0x58u, 0x00u, 0x20u, 0x01u, 0x20u, 0x01u,
-    0x20u, 0x01u, 0x20u, 0x01u, 0x20u, 0x01u, 0x0Bu, 0x00u,
-    0x20u, 0x01u, 0x78u, 0x00u, 0x20u, 0x01u, 0x7Cu, 0x00u,
-    0x71u, 0x4Bu, 0x19u, 0x78u, 0x01u, 0x29u, 0x0Au, 0xD1u,
-    0x70u, 0x48u, 0x71u, 0x49u, 0x02u, 0x78u, 0x01u, 0xEBu,
-    0xC2u, 0x03u, 0x58u, 0x68u, 0x12u, 0x23u, 0x42u, 0x68u,
-    0x68u, 0x48u, 0x42u, 0x60u, 0x0Fu, 0xE0u, 0x18u, 0x78u,
-    0x02u, 0x28u, 0x11u, 0xD1u, 0x6Bu, 0x4Bu, 0x18u, 0x78u,
-    0xFFu, 0xF7u, 0xDAu, 0xFDu, 0x42u, 0x68u, 0x63u, 0x48u,
-    0x42u, 0x60u, 0x41u, 0x68u, 0xCBu, 0x78u, 0x42u, 0x68u,
-    0x91u, 0x78u, 0x41u, 0xEAu, 0x03u, 0x23u, 0x03u, 0x80u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x0Cu, 0xBCu,
-    0x1Au, 0x78u, 0x03u, 0x2Au, 0x21u, 0xD1u, 0x62u, 0x4Bu,
-    0x00u, 0x22u, 0x60u, 0x49u, 0x08u, 0x78u, 0x90u, 0x42u,
-    0x0Au, 0xD8u, 0x0Au, 0x78u, 0x82u, 0xB1u, 0x5Du, 0x49u,
-    0x5Eu, 0x48u, 0x09u, 0x78u, 0x5Eu, 0x4Au, 0x00u, 0x7Cu,
-    0x88u, 0x42u, 0x08u, 0xBFu, 0x13u, 0x46u, 0x07u, 0xE0u,
-    0x18u, 0x78u, 0x00u, 0x28u, 0xF1u, 0xD0u, 0x19u, 0x78u,
-    0x50u, 0x1Cu, 0x5Bu, 0x18u, 0xC2u, 0xB2u, 0xE8u, 0xE7u,
-    0x19u, 0x78u, 0x00u, 0x29u, 0x00u, 0xF0u, 0xD1u, 0x80u,
-    0x18u, 0x78u, 0x4Cu, 0x4Au, 0x10u, 0x80u, 0x53u, 0x60u,
-    0xD6u, 0xE7u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0x00u, 0xF0u,
-    0xDDu, 0xB8u, 0x11u, 0x78u, 0x11u, 0xF0u, 0x03u, 0x02u,
-    0x11u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xC1u, 0x80u,
-    0x44u, 0x49u, 0x4Eu, 0x4Bu, 0x0Au, 0x80u, 0x18u, 0x78u,
-    0x4Du, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x20u,
-    0x00u, 0xFBu, 0x03u, 0x23u, 0x98u, 0x78u, 0x4Bu, 0x4Bu,
-    0x00u, 0x22u, 0x18u, 0x70u, 0x06u, 0xE0u, 0x3Du, 0x49u,
-    0x02u, 0x23u, 0x49u, 0x48u, 0x0Bu, 0x80u, 0x00u, 0x78u,
-    0x46u, 0x4Bu, 0x18u, 0x70u, 0x5Au, 0x70u, 0x4Bu, 0x60u,
-    0xB2u, 0xE7u, 0x01u, 0x22u, 0x1Au, 0x80u, 0x45u, 0x48u,
-    0x05u, 0xE0u, 0x01u, 0x22u, 0x3Fu, 0x48u, 0x1Au, 0x80u,
-    0x02u, 0x78u, 0x43u, 0x49u, 0x88u, 0x18u, 0x58u, 0x60u,
-    0xA6u, 0xE7u, 0x03u, 0x78u, 0x58u, 0x1Eu, 0x0Au, 0x28u,
-    0x00u, 0xF2u, 0x97u, 0x80u, 0xDFu, 0xE8u, 0x10u, 0xF0u,
-    0x2Bu, 0x00u, 0x95u, 0x00u, 0x44u, 0x00u, 0x95u, 0x00u,
-    0x0Bu, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u,
-    0x0Fu, 0x00u, 0x95u, 0x00u, 0x19u, 0x00u, 0x2Fu, 0x4Bu,
-    0x38u, 0x49u, 0x18u, 0x78u, 0x4Cu, 0xE0u, 0x2Du, 0x4Bu,
-    0x34u, 0x4Au, 0x18u, 0x78u, 0x36u, 0x49u, 0x10u, 0x70u,
-    0x01u, 0x20u, 0x08u, 0x70u, 0xFFu, 0xF7u, 0x0Au, 0xFEu,
-    0x77u, 0xE0u, 0xFFu, 0xF7u, 0x25u, 0xFFu, 0x00u, 0x28u,
-    0x77u, 0xD0u, 0x2Au, 0x4Cu, 0x31u, 0x4Au, 0x24u, 0x78u,
-    0x2Fu, 0x4Bu, 0x01u, 0x21u, 0x14u, 0x70u, 0x19u, 0x70u,
-    0xFFu, 0xF7u, 0x58u, 0xFDu, 0x2Au, 0x48u, 0x2Eu, 0x49u,
-    0x02u, 0x5Du, 0x0Au, 0x55u, 0x65u, 0xE0u, 0x12u, 0x78u,
-    0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x55u, 0xD0u,
-    0x09u, 0xD3u, 0x02u, 0x29u, 0x61u, 0xD1u, 0x1Bu, 0x4Bu,
-    0x18u, 0x78u, 0x00u, 0x28u, 0x5Du, 0xD1u, 0xBDu, 0xE8u,
-    0x10u, 0x40u, 0xFFu, 0xF7u, 0xC7u, 0xBEu, 0x17u, 0x4Au,
-    0x11u, 0x78u, 0x01u, 0x29u, 0x55u, 0xD1u, 0x1Cu, 0x49u,
-    0x0Bu, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x00u, 0x17u, 0xE0u,
-    0x10u, 0x78u, 0x00u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au,
-    0x3Cu, 0xD0u, 0x09u, 0xD3u, 0x02u, 0x2Au, 0x48u, 0xD1u,
-    0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x00u, 0x2Bu, 0x44u, 0xD1u,
-    0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x82u, 0xBEu,
-    0x0Au, 0x48u, 0x02u, 0x78u, 0x01u, 0x2Au, 0x3Cu, 0xD1u,
-    0x0Fu, 0x49u, 0x0Bu, 0x78u, 0x43u, 0xF0u, 0x02u, 0x00u,
-    0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x60u, 0x00u, 0x40u,
+    0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x0Du, 0x4Bu,
+    0x1Cu, 0x78u, 0x0Du, 0x4Bu, 0xE4u, 0xB2u, 0x18u, 0x78u,
+    0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Eu, 0xFEu,
+    0x43u, 0x68u, 0x1Bu, 0x79u, 0xA3u, 0x42u, 0x0Bu, 0xD9u,
+    0x54u, 0xB9u, 0x08u, 0x4Bu, 0x08u, 0x4Au, 0x19u, 0x78u,
+    0x01u, 0x20u, 0xC9u, 0xB2u, 0x11u, 0x70u, 0x07u, 0x4Au,
+    0x12u, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x10u, 0xBDu,
+    0x00u, 0x20u, 0x10u, 0xBDu, 0x04u, 0x60u, 0x00u, 0x40u,
+    0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,
+    0x38u, 0xB5u, 0x8Cu, 0x4Cu, 0x00u, 0x23u, 0x23u, 0x80u,
+    0x8Bu, 0x4Bu, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x80u, 0x0Fu,
+    0x8Au, 0x4Au, 0x12u, 0x78u, 0x00u, 0xF0u, 0x88u, 0x80u,
+    0x0Au, 0x2Au, 0x00u, 0xF2u, 0x08u, 0x81u, 0xDFu, 0xE8u,
+    0x12u, 0xF0u, 0x58u, 0x00u, 0x06u, 0x01u, 0x06u, 0x01u,
+    0x06u, 0x01u, 0x06u, 0x01u, 0x06u, 0x01u, 0x0Bu, 0x00u,
+    0x06u, 0x01u, 0x78u, 0x00u, 0x06u, 0x01u, 0x7Cu, 0x00u,
+    0x81u, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x2Au, 0x09u, 0xD1u,
+    0x80u, 0x4Bu, 0x1Au, 0x78u, 0x80u, 0x4Bu, 0x03u, 0xEBu,
+    0xC2u, 0x03u, 0x5Bu, 0x68u, 0x5Bu, 0x68u, 0x63u, 0x60u,
+    0x12u, 0x23u, 0x11u, 0xE0u, 0x1Au, 0x78u, 0x02u, 0x2Au,
+    0x13u, 0xD1u, 0x7Cu, 0x4Bu, 0x18u, 0x78u, 0xFFu, 0xF7u,
+    0xF1u, 0xFDu, 0x00u, 0x28u, 0x00u, 0xF0u, 0xE3u, 0x80u,
+    0x43u, 0x68u, 0x63u, 0x60u, 0x63u, 0x68u, 0xDAu, 0x78u,
+    0x63u, 0x68u, 0x9Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x23u,
+    0x23u, 0x80u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,
+    0x0Bu, 0xBCu, 0x1Bu, 0x78u, 0x03u, 0x2Bu, 0x20u, 0xD1u,
+    0x71u, 0x4Bu, 0x00u, 0x22u, 0x6Fu, 0x49u, 0xD0u, 0xB2u,
+    0x0Du, 0x78u, 0x85u, 0x42u, 0x0Au, 0xD8u, 0x0Au, 0x78u,
+    0x7Au, 0xB1u, 0x6Cu, 0x4Au, 0x6Du, 0x48u, 0x11u, 0x78u,
+    0x00u, 0x7Cu, 0x6Du, 0x4Au, 0x88u, 0x42u, 0x08u, 0xBFu,
+    0x13u, 0x46u, 0x06u, 0xE0u, 0x18u, 0x78u, 0x01u, 0x32u,
+    0x00u, 0x28u, 0xF0u, 0xD0u, 0x19u, 0x78u, 0x0Bu, 0x44u,
+    0xE8u, 0xE7u, 0x1Au, 0x78u, 0x00u, 0x2Au, 0x00u, 0xF0u,
+    0xB6u, 0x80u, 0x1Au, 0x78u, 0xD2u, 0xB2u, 0x22u, 0x80u,
+    0x19u, 0xE0u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0x00u, 0xF0u,
+    0xE7u, 0xB8u, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x03u, 0x02u,
+    0x13u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xA7u, 0x80u,
+    0x5Eu, 0x4Bu, 0x22u, 0x80u, 0x1Bu, 0x78u, 0x5Eu, 0x4Au,
+    0x03u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x21u, 0x01u, 0xFBu,
+    0x03u, 0x23u, 0x9Au, 0x78u, 0x5Bu, 0x4Bu, 0xD2u, 0xB2u,
+    0x1Au, 0x70u, 0x00u, 0x22u, 0x5Au, 0x70u, 0x63u, 0x60u,
+    0xBBu, 0xE7u, 0x02u, 0x23u, 0x23u, 0x80u, 0x58u, 0x4Bu,
+    0x19u, 0x78u, 0x56u, 0x4Bu, 0xC9u, 0xB2u, 0x19u, 0x70u,
+    0xF4u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x55u, 0x4Bu,
+    0xF1u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x4Fu, 0x4Bu,
+    0x53u, 0x4Au, 0x1Bu, 0x78u, 0x13u, 0x44u, 0xEAu, 0xE7u,
+    0x01u, 0x3Au, 0x0Au, 0x2Au, 0x7Fu, 0xD8u, 0xDFu, 0xE8u,
+    0x02u, 0xF0u, 0x36u, 0x7Eu, 0x52u, 0x7Eu, 0x06u, 0x7Eu,
+    0x7Eu, 0x7Eu, 0x0Bu, 0x7Eu, 0x22u, 0x00u, 0x43u, 0x4Bu,
+    0x1Au, 0x78u, 0x4Cu, 0x4Bu, 0xD2u, 0xB2u, 0x60u, 0xE0u,
+    0x40u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0xFFu, 0x04u,
+    0x53u, 0xB9u, 0x46u, 0x4Bu, 0x1Au, 0x78u, 0x94u, 0x42u,
+    0x65u, 0xD0u, 0x1Cu, 0x70u, 0x46u, 0x4Bu, 0x01u, 0x20u,
+    0x18u, 0x70u, 0xFFu, 0xF7u, 0x15u, 0xFEu, 0x5Eu, 0xE0u,
+    0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x6Au, 0xFDu,
+    0x00u, 0x28u, 0xEEu, 0xD1u, 0x5Bu, 0xE0u, 0xFFu, 0xF7u,
+    0x1Du, 0xFFu, 0x00u, 0x28u, 0x57u, 0xD0u, 0x37u, 0x4Bu,
+    0x01u, 0x22u, 0x1Cu, 0x78u, 0x3Du, 0x4Bu, 0xE4u, 0xB2u,
+    0x1Cu, 0x70u, 0x3Bu, 0x4Bu, 0x1Au, 0x70u, 0xFFu, 0xF7u,
+    0x6Du, 0xFDu, 0x37u, 0x4Bu, 0x1Au, 0x5Du, 0x3Au, 0x4Bu,
+    0xD2u, 0xB2u, 0x1Au, 0x55u, 0x43u, 0xE0u, 0x1Bu, 0x78u,
+    0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x32u, 0xD0u,
+    0x0Cu, 0xD3u, 0x02u, 0x2Bu, 0x3Fu, 0xD1u, 0x03u, 0xF1u,
+    0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,
+    0x00u, 0x2Bu, 0x38u, 0xD1u, 0xBDu, 0xE8u, 0x38u, 0x40u,
+    0xFFu, 0xF7u, 0xBAu, 0xBEu, 0x21u, 0x4Bu, 0x1Bu, 0x78u,
+    0x01u, 0x2Bu, 0x30u, 0xD1u, 0x26u, 0x4Bu, 0x1Au, 0x78u,
+    0x02u, 0xF0u, 0xFDu, 0x02u, 0x19u, 0xE0u, 0x1Bu, 0x78u,
+    0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x16u, 0xD0u,
+    0x0Bu, 0xD3u, 0x02u, 0x2Bu, 0x23u, 0xD1u, 0x03u, 0xF1u,
+    0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,
+    0xEBu, 0xB9u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,
+    0x75u, 0xBEu, 0x14u, 0x4Bu, 0x1Bu, 0x78u, 0x01u, 0x2Bu,
+    0x15u, 0xD1u, 0x19u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,
+    0x02u, 0x02u, 0x1Au, 0x70u, 0x0Bu, 0xE0u, 0x13u, 0x4Bu,
+    0x1Au, 0x78u, 0x62u, 0xB9u, 0x1Bu, 0x78u, 0x1Bu, 0x4Au,
+    0x0Cu, 0x48u, 0xDBu, 0xB2u, 0xD1u, 0x5Cu, 0x00u, 0x78u,
+    0x21u, 0xEAu, 0x00u, 0x01u, 0xD1u, 0x54u, 0xBDu, 0xE8u,
+    0x38u, 0x40u, 0xFFu, 0xF7u, 0x15u, 0xBAu, 0x00u, 0x20u,
+    0x38u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+    0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
+    0x03u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+    0xB8u, 0x21u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
+    0x7Eu, 0x22u, 0x00u, 0x00u, 0xFAu, 0x22u, 0x00u, 0x00u,
+    0x74u, 0x22u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
+    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x4Eu, 0xC1u, 0xFFu, 0x1Fu,
+    0x67u, 0xC1u, 0xFFu, 0x1Fu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+    0x56u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+    0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+    0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x6Bu, 0xC1u, 0xFFu, 0x1Fu,
+    0x03u, 0x4Bu, 0x00u, 0x20u, 0x1Bu, 0x78u, 0x1Bu, 0x06u,
+    0x44u, 0xBFu, 0x02u, 0x4Bu, 0x1Bu, 0x78u, 0x70u, 0x47u,
     0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
-    0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0xF8u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
-    0xBEu, 0x21u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u,
-    0xB4u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
-    0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
-    0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
-    0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
-    0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
-    0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x48u, 0x02u, 0x78u,
-    0x5Au, 0xB9u, 0x03u, 0x78u, 0x07u, 0x4Au, 0x08u, 0x48u,
-    0xD1u, 0x5Cu, 0x00u, 0x78u, 0x21u, 0xEAu, 0x00u, 0x01u,
-    0xD1u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
-    0xD1u, 0xB9u, 0x00u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x73u, 0xC1u, 0xFFu, 0x1Fu,
-    0x02u, 0x60u, 0x00u, 0x40u, 0x03u, 0x4Bu, 0x18u, 0x78u,
-    0x01u, 0x06u, 0x44u, 0xBFu, 0x02u, 0x49u, 0x09u, 0x78u,
-    0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x01u, 0x60u, 0x00u, 0x40u, 0x0Fu, 0x4Bu, 0x18u, 0x78u,
-    0x00u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x0Cu, 0xD0u,
-    0x02u, 0x29u, 0x0Du, 0xD1u, 0x0Cu, 0x4Au, 0x0Cu, 0x21u,
-    0x10u, 0x78u, 0x0Cu, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u,
-    0x01u, 0xFBu, 0x03u, 0x20u, 0x08u, 0x30u, 0x83u, 0x78u,
-    0x03u, 0xE0u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x00u, 0xE0u,
-    0x00u, 0x23u, 0x07u, 0x49u, 0x0Au, 0x68u, 0xD0u, 0x5Cu,
-    0x03u, 0x28u, 0x01u, 0xD1u, 0xFFu, 0xF7u, 0xC6u, 0xBBu,
-    0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,
-    0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
-    0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x38u, 0xB5u, 0x0Eu, 0x4Du,
-    0x0Eu, 0x4Bu, 0x00u, 0x24u, 0xE8u, 0x1Au, 0x85u, 0x10u,
-    0xACu, 0x42u, 0x05u, 0xD0u, 0x0Bu, 0x49u, 0x51u, 0xF8u,
-    0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u,
-    0x00u, 0xF0u, 0x40u, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au,
-    0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u,
-    0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u,
-    0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu,
-    0x58u, 0x22u, 0x00u, 0x00u, 0x58u, 0x22u, 0x00u, 0x00u,
-    0x58u, 0x22u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u,
+    0x10u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0x03u, 0x03u,
+    0x01u, 0x2Bu, 0x0Cu, 0xD0u, 0x02u, 0x2Bu, 0x0Eu, 0xD1u,
+    0x0Du, 0x4Bu, 0x0Eu, 0x4Au, 0x1Bu, 0x78u, 0x0Cu, 0x21u,
+    0x03u, 0xF0u, 0x7Fu, 0x03u, 0x01u, 0xFBu, 0x03u, 0x23u,
+    0x08u, 0x33u, 0x9Bu, 0x78u, 0x01u, 0xE0u, 0x08u, 0x4Bu,
+    0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xE0u, 0x00u, 0x23u,
+    0x07u, 0x4Au, 0x12u, 0x68u, 0xD3u, 0x5Cu, 0x03u, 0x2Bu,
+    0x01u, 0xD1u, 0xFFu, 0xF7u, 0xE7u, 0xBBu, 0x00u, 0x20u,
+    0x70u, 0x47u, 0x00u, 0xBFu, 0x00u, 0x60u, 0x00u, 0x40u,
+    0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+    0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x70u, 0xB5u, 0x0Eu, 0x4Bu,
+    0x0Eu, 0x4Du, 0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u,
+    0x1Eu, 0x46u, 0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u,
+    0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u,
+    0x00u, 0xF0u, 0x40u, 0xF9u, 0x08u, 0x4Du, 0x09u, 0x4Bu,
+    0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u, 0x1Eu, 0x46u,
+    0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u, 0x24u, 0x20u,
+    0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u, 0x70u, 0xBDu,
+    0x18u, 0x23u, 0x00u, 0x00u, 0x18u, 0x23u, 0x00u, 0x00u,
+    0x20u, 0x23u, 0x00u, 0x00u, 0x18u, 0x23u, 0x00u, 0x00u,
     0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u,
     0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u,
-    0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,
+    0x10u, 0xBDu, 0x02u, 0x44u, 0x03u, 0x46u, 0x93u, 0x42u,
     0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
-    0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u,
-    0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x70u, 0x47u, 0x00u, 0x00u, 0x60u, 0x23u, 0x00u, 0x00u,
+    0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u,
     0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u,
     0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u,
@@ -1082,26 +1106,26 @@ const uint8 cy_bootloader[] = {
     0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u,
     0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x33u,
     0x33u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x14u, 0x01u, 0x01u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x21u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x21u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x11u, 0x22u, 0x00u, 0x00u,
-    0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x21u, 0x00u, 0x00u,
-    0x01u, 0x00u, 0x00u, 0x00u, 0x44u, 0x21u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x21u, 0x00u, 0x00u,
+    0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x1Eu, 0x01u, 0x01u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x21u, 0x00u, 0x00u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xFAu, 0x22u, 0x00u, 0x00u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x21u, 0x00u, 0x00u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xD1u, 0x22u, 0x00u, 0x00u,
+    0x02u, 0x00u, 0x00u, 0x00u, 0xF2u, 0x21u, 0x00u, 0x00u,
+    0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x22u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x21u, 0x00u, 0x00u,
     0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x03u, 0x40u, 0x00u,
     0x03u, 0x00u, 0x00u, 0x00u, 0x82u, 0x03u, 0x40u, 0x00u,
     0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0x4Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x80u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x74u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x0Cu, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x40u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x34u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0x8Cu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
-    0x23u, 0x22u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,
-    0x33u, 0xC2u, 0xFFu, 0x1Fu, 0x74u, 0xC2u, 0xFFu, 0x1Fu,
-    0x41u, 0x00u, 0x00u, 0x00u, 0xF2u, 0xC1u, 0xFFu, 0x1Fu,
-    0xEEu, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u,
+    0x4Cu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xE3u, 0x22u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,
+    0x2Bu, 0xC2u, 0xFFu, 0x1Fu, 0x6Cu, 0xC2u, 0xFFu, 0x1Fu,
+    0x41u, 0x00u, 0x00u, 0x00u, 0xEAu, 0xC1u, 0xFFu, 0x1Fu,
+    0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u,
     0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0xA1u, 0x00u,
     0x09u, 0x00u, 0x15u, 0x00u, 0x25u, 0xFFu, 0x75u, 0x08u,
     0x95u, 0x40u, 0x91u, 0x02u, 0x09u, 0x00u, 0x15u, 0x00u,
@@ -1130,10 +1154,10 @@ const uint8 cy_bootloader[] = {
     0x51u, 0x00u, 0x00u, 0x00u, 0xB1u, 0x01u, 0x00u, 0x00u,
     0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,
     0x9Eu, 0x46u, 0x70u, 0x47u, 0x2Du, 0x00u, 0x00u, 0x00u,
-    0x80u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,
-    0x20u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x20u, 0x00u, 0x00u,
-    0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
+    0x40u, 0x23u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,
+    0x20u, 0x00u, 0x00u, 0x00u, 0x48u, 0x01u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xDCu, 0x20u, 0x00u, 0x00u,
+    0xE0u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
     0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
@@ -1147,6 +1171,14 @@ const uint8 cy_bootloader[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
 
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
@@ -1158,7 +1190,7 @@ __attribute__ ((__section__(".cymeta"), used))
 #endif
 const uint8 cy_metadata[] = {
     0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,
-    0x2Eu, 0x1Fu, 0x9Au, 0x6Bu};
+    0x2Eu, 0x20u, 0x36u, 0x6Bu};
 
 #if defined(__GNUC__) || defined(__ARMCC_VERSION)
 __attribute__ ((__section__(".cycustnvl"), used))
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf
index a1d4bde7..abf1c525 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf
@@ -1,3 +1,3 @@
 /* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */
 
-define symbol CYDEV_BTLDR_SIZE = 0x00002300;
+define symbol CYDEV_BTLDR_SIZE = 0x00002400;
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
index 2514d9aa..eb881789 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
index 27a4bffb..d36e44e6 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
index dc11e6db..28f802c8 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
index ede64b20..0de4ccb6 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
index 8f6fcc72..75b02a6f 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
index 9ce82ff8..2fef27b2 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
index b5f7a51f..244d4d53 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
index 790c65b5..e3bfe5d0 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index f05524a5..ae0e2a06 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -3,83 +3,111 @@
 #include <cydevice.h>
 #include <cydevice_trm.h>
 
-/* Debug_Timer_Interrupt */
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+/* LED1 */
+#define LED1__0__MASK 0x02u
+#define LED1__0__PC CYREG_PRT0_PC1
+#define LED1__0__PORT 0u
+#define LED1__0__SHIFT 1
+#define LED1__AG CYREG_PRT0_AG
+#define LED1__AMUX CYREG_PRT0_AMUX
+#define LED1__BIE CYREG_PRT0_BIE
+#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK
+#define LED1__BYP CYREG_PRT0_BYP
+#define LED1__CTL CYREG_PRT0_CTL
+#define LED1__DM0 CYREG_PRT0_DM0
+#define LED1__DM1 CYREG_PRT0_DM1
+#define LED1__DM2 CYREG_PRT0_DM2
+#define LED1__DR CYREG_PRT0_DR
+#define LED1__INP_DIS CYREG_PRT0_INP_DIS
+#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define LED1__LCD_EN CYREG_PRT0_LCD_EN
+#define LED1__MASK 0x02u
+#define LED1__PORT 0u
+#define LED1__PRT CYREG_PRT0_PRT
+#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define LED1__PS CYREG_PRT0_PS
+#define LED1__SHIFT 1
+#define LED1__SLW CYREG_PRT0_SLW
 
-/* SD_RX_DMA_COMPLETE */
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SD_CD */
+#define SD_CD__0__MASK 0x20u
+#define SD_CD__0__PC CYREG_PRT3_PC5
+#define SD_CD__0__PORT 3u
+#define SD_CD__0__SHIFT 5
+#define SD_CD__AG CYREG_PRT3_AG
+#define SD_CD__AMUX CYREG_PRT3_AMUX
+#define SD_CD__BIE CYREG_PRT3_BIE
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CD__BYP CYREG_PRT3_BYP
+#define SD_CD__CTL CYREG_PRT3_CTL
+#define SD_CD__DM0 CYREG_PRT3_DM0
+#define SD_CD__DM1 CYREG_PRT3_DM1
+#define SD_CD__DM2 CYREG_PRT3_DM2
+#define SD_CD__DR CYREG_PRT3_DR
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CD__MASK 0x20u
+#define SD_CD__PORT 3u
+#define SD_CD__PRT CYREG_PRT3_PRT
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CD__PS CYREG_PRT3_PS
+#define SD_CD__SHIFT 5
+#define SD_CD__SLW CYREG_PRT3_SLW
 
-/* SD_TX_DMA_COMPLETE */
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SD_CS */
+#define SD_CS__0__MASK 0x10u
+#define SD_CS__0__PC CYREG_PRT3_PC4
+#define SD_CS__0__PORT 3u
+#define SD_CS__0__SHIFT 4
+#define SD_CS__AG CYREG_PRT3_AG
+#define SD_CS__AMUX CYREG_PRT3_AMUX
+#define SD_CS__BIE CYREG_PRT3_BIE
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CS__BYP CYREG_PRT3_BYP
+#define SD_CS__CTL CYREG_PRT3_CTL
+#define SD_CS__DM0 CYREG_PRT3_DM0
+#define SD_CS__DM1 CYREG_PRT3_DM1
+#define SD_CS__DM2 CYREG_PRT3_DM2
+#define SD_CS__DR CYREG_PRT3_DR
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CS__MASK 0x10u
+#define SD_CS__PORT 3u
+#define SD_CS__PRT CYREG_PRT3_PRT
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CS__PS CYREG_PRT3_PS
+#define SD_CS__SHIFT 4
+#define SD_CS__SLW CYREG_PRT3_SLW
 
-/* SCSI_Parity_Error */
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
+/* USBFS_arb_int */
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_arb_int__INTC_MASK 0x400000u
+#define USBFS_arb_int__INTC_NUMBER 22u
+#define USBFS_arb_int__INTC_PRIOR_NUM 7u
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* USBFS_bus_reset */
 #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -91,95 +119,131 @@
 #define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_PHASE */
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+/* USBFS_Dm */
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
 
-/* SCSI_Filtered */
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Filtered_sts_sts_reg__0__POS 0
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
-#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
-#define SCSI_Filtered_sts_sts_reg__2__POS 2
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
-#define SCSI_Filtered_sts_sts_reg__3__POS 3
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
-#define SCSI_Filtered_sts_sts_reg__4__POS 4
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB00_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB00_ST
+/* USBFS_Dp */
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
 
-/* SCSI_Out_Bits */
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+/* USBFS_dp_int */
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* USBFS_arb_int */
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_arb_int__INTC_MASK 0x400000u
-#define USBFS_arb_int__INTC_NUMBER 22u
-#define USBFS_arb_int__INTC_PRIOR_NUM 7u
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* USBFS_ep_0 */
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x40u
+#define USBFS_ep_1__INTC_NUMBER 6u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x80u
+#define USBFS_ep_2__INTC_NUMBER 7u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_3__INTC_MASK 0x100u
+#define USBFS_ep_3__INTC_NUMBER 8u
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_4__INTC_MASK 0x200u
+#define USBFS_ep_4__INTC_NUMBER 9u
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 #define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -191,2186 +255,266 @@
 #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_Ctl */
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+/* USBFS_USB */
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
+#define USBFS_USB__CR0 CYREG_USB_CR0
+#define USBFS_USB__CR1 CYREG_USB_CR1
+#define USBFS_USB__CWA CYREG_USB_CWA
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
+#define USBFS_USB__PM_ACT_MSK 0x01u
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
+#define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
+#define USBFS_USB__SOF0 CYREG_USB_SOF0
+#define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
 
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x02u
-#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__0__PORT 5u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__0__SHIFT 1
-#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x01u
-#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__1__PORT 5u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__1__SHIFT 0
-#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__2__MASK 0x20u
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__2__PORT 6u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__2__SHIFT 5
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x10u
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__3__PORT 6u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__3__SHIFT 4
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x80u
-#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__4__PORT 2u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__4__SHIFT 7
-#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x40u
-#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__5__PORT 2u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__5__SHIFT 6
-#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x08u
-#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__6__PORT 2u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__6__SHIFT 3
-#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x04u
-#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__7__PORT 2u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__7__SHIFT 2
-#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x02u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__DB0__PORT 5u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB0__SHIFT 1
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x01u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__DB1__PORT 5u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB1__SHIFT 0
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB2__MASK 0x20u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__DB2__PORT 6u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB2__SHIFT 5
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x10u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__DB3__PORT 6u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB3__SHIFT 4
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x80u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__DB4__PORT 2u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB4__SHIFT 7
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x40u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__DB5__PORT 2u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB5__SHIFT 6
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x08u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__DB6__PORT 2u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB6__SHIFT 3
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x04u
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__DB7__PORT 2u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB7__SHIFT 2
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* SCSI_RST_ISR */
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x04u
-#define SCSI_RST_ISR__INTC_NUMBER 2u
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB09_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_RxStsReg__4__POS 4
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
-#define SDCard_BSPIM_RxStsReg__5__POS 5
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
-#define SDCard_BSPIM_RxStsReg__6__POS 6
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB11_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB11_ST
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
-#define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
-#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
-#define SDCard_BSPIM_TxStsReg__2__POS 2
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
-#define SDCard_BSPIM_TxStsReg__3__POS 3
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_TxStsReg__4__POS 4
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB10_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-#define SCSI_In_DBx__0__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__0__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__0__MASK 0x08u
-#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3
-#define SCSI_In_DBx__0__PORT 5u
-#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__0__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__0__SHIFT 3
-#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__1__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__1__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__1__MASK 0x04u
-#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2
-#define SCSI_In_DBx__1__PORT 5u
-#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__1__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__1__SHIFT 2
-#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__2__MASK 0x80u
-#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7
-#define SCSI_In_DBx__2__PORT 6u
-#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__2__SHIFT 7
-#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__3__MASK 0x40u
-#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6
-#define SCSI_In_DBx__3__PORT 6u
-#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__3__SHIFT 6
-#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__4__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__4__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__4__MASK 0x20u
-#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5
-#define SCSI_In_DBx__4__PORT 12u
-#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__4__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__4__SHIFT 5
-#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__5__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__5__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__5__MASK 0x10u
-#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__5__PORT 12u
-#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__5__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__5__SHIFT 4
-#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__6__MASK 0x20u
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__6__PORT 2u
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__6__SHIFT 5
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__7__MASK 0x10u
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__7__PORT 2u
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__7__SHIFT 4
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__DB0__MASK 0x08u
-#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3
-#define SCSI_In_DBx__DB0__PORT 5u
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__DB0__SHIFT 3
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__DB1__MASK 0x04u
-#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2
-#define SCSI_In_DBx__DB1__PORT 5u
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__DB1__SHIFT 2
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB2__MASK 0x80u
-#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7
-#define SCSI_In_DBx__DB2__PORT 6u
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB2__SHIFT 7
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB3__MASK 0x40u
-#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6
-#define SCSI_In_DBx__DB3__PORT 6u
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB3__SHIFT 6
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__DB4__MASK 0x20u
-#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5
-#define SCSI_In_DBx__DB4__PORT 12u
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__DB4__SHIFT 5
-#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__DB5__MASK 0x10u
-#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__DB5__PORT 12u
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__DB5__SHIFT 4
-#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB6__MASK 0x20u
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__DB6__PORT 2u
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB6__SHIFT 5
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB7__MASK 0x10u
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__DB7__PORT 2u
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB7__SHIFT 4
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_RX_DMA__DRQ_NUMBER 0u
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u
-#define SCSI_RX_DMA__PRIORITY 2u
-#define SCSI_RX_DMA__TERMIN_EN 0u
-#define SCSI_RX_DMA__TERMIN_SEL 0u
-#define SCSI_RX_DMA__TERMOUT0_EN 1u
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u
-#define SCSI_RX_DMA__TERMOUT1_EN 0u
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u
-
-/* SCSI_TX_DMA */
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_TX_DMA__DRQ_NUMBER 1u
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u
-#define SCSI_TX_DMA__PRIORITY 2u
-#define SCSI_TX_DMA__TERMIN_EN 0u
-#define SCSI_TX_DMA__TERMIN_SEL 0u
-#define SCSI_TX_DMA__TERMOUT0_EN 1u
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u
-#define SCSI_TX_DMA__TERMOUT1_EN 0u
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u
-
-/* SD_Data_Clk */
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
-#define SD_Data_Clk__INDEX 0x00u
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SD_Data_Clk__PM_ACT_MSK 0x01u
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SD_Data_Clk__PM_STBY_MSK 0x01u
-
-/* timer_clock */
-#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
-#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
-#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
-#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
-#define timer_clock__INDEX 0x02u
-#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define timer_clock__PM_ACT_MSK 0x04u
-#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define timer_clock__PM_STBY_MSK 0x04u
-
-/* SCSI_Noise */
-#define SCSI_Noise__0__AG CYREG_PRT2_AG
-#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX
-#define SCSI_Noise__0__BIE CYREG_PRT2_BIE
-#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Noise__0__BYP CYREG_PRT2_BYP
-#define SCSI_Noise__0__CTL CYREG_PRT2_CTL
-#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0
-#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1
-#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2
-#define SCSI_Noise__0__DR CYREG_PRT2_DR
-#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Noise__0__MASK 0x01u
-#define SCSI_Noise__0__PC CYREG_PRT2_PC0
-#define SCSI_Noise__0__PORT 2u
-#define SCSI_Noise__0__PRT CYREG_PRT2_PRT
-#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Noise__0__PS CYREG_PRT2_PS
-#define SCSI_Noise__0__SHIFT 0
-#define SCSI_Noise__0__SLW CYREG_PRT2_SLW
-#define SCSI_Noise__1__AG CYREG_PRT6_AG
-#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__1__DR CYREG_PRT6_DR
-#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__1__MASK 0x08u
-#define SCSI_Noise__1__PC CYREG_PRT6_PC3
-#define SCSI_Noise__1__PORT 6u
-#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__1__PS CYREG_PRT6_PS
-#define SCSI_Noise__1__SHIFT 3
-#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__2__AG CYREG_PRT4_AG
-#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__2__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__2__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__2__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__2__DR CYREG_PRT4_DR
-#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__2__MASK 0x08u
-#define SCSI_Noise__2__PC CYREG_PRT4_PC3
-#define SCSI_Noise__2__PORT 4u
-#define SCSI_Noise__2__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__2__PS CYREG_PRT4_PS
-#define SCSI_Noise__2__SHIFT 3
-#define SCSI_Noise__2__SLW CYREG_PRT4_SLW
-#define SCSI_Noise__3__AG CYREG_PRT4_AG
-#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__3__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__3__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__3__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__3__DR CYREG_PRT4_DR
-#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__3__MASK 0x80u
-#define SCSI_Noise__3__PC CYREG_PRT4_PC7
-#define SCSI_Noise__3__PORT 4u
-#define SCSI_Noise__3__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__3__PS CYREG_PRT4_PS
-#define SCSI_Noise__3__SHIFT 7
-#define SCSI_Noise__3__SLW CYREG_PRT4_SLW
-#define SCSI_Noise__4__AG CYREG_PRT6_AG
-#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__4__DR CYREG_PRT6_DR
-#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__4__MASK 0x04u
-#define SCSI_Noise__4__PC CYREG_PRT6_PC2
-#define SCSI_Noise__4__PORT 6u
-#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__4__PS CYREG_PRT6_PS
-#define SCSI_Noise__4__SHIFT 2
-#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
-#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
-#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__ACK__MASK 0x04u
-#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2
-#define SCSI_Noise__ACK__PORT 6u
-#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
-#define SCSI_Noise__ACK__SHIFT 2
-#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__ATN__AG CYREG_PRT2_AG
-#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX
-#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE
-#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP
-#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL
-#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0
-#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1
-#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2
-#define SCSI_Noise__ATN__DR CYREG_PRT2_DR
-#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Noise__ATN__MASK 0x01u
-#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0
-#define SCSI_Noise__ATN__PORT 2u
-#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT
-#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Noise__ATN__PS CYREG_PRT2_PS
-#define SCSI_Noise__ATN__SHIFT 0
-#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW
-#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
-#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
-#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__BSY__MASK 0x08u
-#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3
-#define SCSI_Noise__BSY__PORT 6u
-#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
-#define SCSI_Noise__BSY__SHIFT 3
-#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__RST__AG CYREG_PRT4_AG
-#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__RST__DR CYREG_PRT4_DR
-#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__RST__MASK 0x80u
-#define SCSI_Noise__RST__PC CYREG_PRT4_PC7
-#define SCSI_Noise__RST__PORT 4u
-#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__RST__PS CYREG_PRT4_PS
-#define SCSI_Noise__RST__SHIFT 7
-#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW
-#define SCSI_Noise__SEL__AG CYREG_PRT4_AG
-#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__SEL__DR CYREG_PRT4_DR
-#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__SEL__MASK 0x08u
-#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3
-#define SCSI_Noise__SEL__PORT 4u
-#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__SEL__PS CYREG_PRT4_PS
-#define SCSI_Noise__SEL__SHIFT 3
-#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
-
-/* scsiTarget */
-#define scsiTarget_StatusReg__0__MASK 0x01u
-#define scsiTarget_StatusReg__0__POS 0
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
-#define scsiTarget_StatusReg__1__MASK 0x02u
-#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__2__MASK 0x04u
-#define scsiTarget_StatusReg__2__POS 2
-#define scsiTarget_StatusReg__3__MASK 0x08u
-#define scsiTarget_StatusReg__3__POS 3
-#define scsiTarget_StatusReg__4__MASK 0x10u
-#define scsiTarget_StatusReg__4__POS 4
-#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x40u
-#define USBFS_ep_1__INTC_NUMBER 6u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x80u
-#define USBFS_ep_2__INTC_NUMBER 7u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x100u
-#define USBFS_ep_3__INTC_NUMBER 8u
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x200u
-#define USBFS_ep_4__INTC_NUMBER 9u
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_RX_DMA__DRQ_NUMBER 2u
-#define SD_RX_DMA__NUMBEROF_TDS 0u
-#define SD_RX_DMA__PRIORITY 2u
-#define SD_RX_DMA__TERMIN_EN 0u
-#define SD_RX_DMA__TERMIN_SEL 0u
-#define SD_RX_DMA__TERMOUT0_EN 1u
-#define SD_RX_DMA__TERMOUT0_SEL 2u
-#define SD_RX_DMA__TERMOUT1_EN 0u
-#define SD_RX_DMA__TERMOUT1_SEL 0u
-
-/* SD_TX_DMA */
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_TX_DMA__DRQ_NUMBER 3u
-#define SD_TX_DMA__NUMBEROF_TDS 0u
-#define SD_TX_DMA__PRIORITY 2u
-#define SD_TX_DMA__TERMIN_EN 0u
-#define SD_TX_DMA__TERMIN_SEL 0u
-#define SD_TX_DMA__TERMOUT0_EN 1u
-#define SD_TX_DMA__TERMOUT0_SEL 3u
-#define SD_TX_DMA__TERMOUT1_EN 0u
-#define SD_TX_DMA__TERMOUT1_SEL 0u
-
-/* USBFS_USB */
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
-#define USBFS_USB__CR0 CYREG_USB_CR0
-#define USBFS_USB__CR1 CYREG_USB_CR1
-#define USBFS_USB__CWA CYREG_USB_CWA
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
-#define USBFS_USB__PM_ACT_MSK 0x01u
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
-#define USBFS_USB__PM_STBY_MSK 0x01u
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
-#define USBFS_USB__SOF0 CYREG_USB_SOF0
-#define USBFS_USB__SOF1 CYREG_USB_SOF1
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
-#define SCSI_CLK__INDEX 0x01u
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SCSI_CLK__PM_ACT_MSK 0x02u
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SCSI_CLK__PM_STBY_MSK 0x02u
-
-/* SCSI_Out */
-#define SCSI_Out__0__AG CYREG_PRT15_AG
-#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__0__BIE CYREG_PRT15_BIE
-#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__0__BYP CYREG_PRT15_BYP
-#define SCSI_Out__0__CTL CYREG_PRT15_CTL
-#define SCSI_Out__0__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__0__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__0__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__0__DR CYREG_PRT15_DR
-#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__0__MASK 0x20u
-#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5
-#define SCSI_Out__0__PORT 15u
-#define SCSI_Out__0__PRT CYREG_PRT15_PRT
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__0__PS CYREG_PRT15_PS
-#define SCSI_Out__0__SHIFT 5
-#define SCSI_Out__0__SLW CYREG_PRT15_SLW
-#define SCSI_Out__1__AG CYREG_PRT15_AG
-#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__1__BIE CYREG_PRT15_BIE
-#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__1__BYP CYREG_PRT15_BYP
-#define SCSI_Out__1__CTL CYREG_PRT15_CTL
-#define SCSI_Out__1__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__1__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__1__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__1__DR CYREG_PRT15_DR
-#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__1__MASK 0x10u
-#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4
-#define SCSI_Out__1__PORT 15u
-#define SCSI_Out__1__PRT CYREG_PRT15_PRT
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__1__PS CYREG_PRT15_PS
-#define SCSI_Out__1__SHIFT 4
-#define SCSI_Out__1__SLW CYREG_PRT15_SLW
-#define SCSI_Out__2__AG CYREG_PRT6_AG
-#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__2__DR CYREG_PRT6_DR
-#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__2__MASK 0x02u
-#define SCSI_Out__2__PC CYREG_PRT6_PC1
-#define SCSI_Out__2__PORT 6u
-#define SCSI_Out__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__2__PS CYREG_PRT6_PS
-#define SCSI_Out__2__SHIFT 1
-#define SCSI_Out__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out__3__AG CYREG_PRT6_AG
-#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__3__DR CYREG_PRT6_DR
-#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__3__MASK 0x01u
-#define SCSI_Out__3__PC CYREG_PRT6_PC0
-#define SCSI_Out__3__PORT 6u
-#define SCSI_Out__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__3__PS CYREG_PRT6_PS
-#define SCSI_Out__3__SHIFT 0
-#define SCSI_Out__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out__4__AG CYREG_PRT4_AG
-#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__4__BIE CYREG_PRT4_BIE
-#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__4__BYP CYREG_PRT4_BYP
-#define SCSI_Out__4__CTL CYREG_PRT4_CTL
-#define SCSI_Out__4__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__4__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__4__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__4__DR CYREG_PRT4_DR
-#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__4__MASK 0x20u
-#define SCSI_Out__4__PC CYREG_PRT4_PC5
-#define SCSI_Out__4__PORT 4u
-#define SCSI_Out__4__PRT CYREG_PRT4_PRT
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__4__PS CYREG_PRT4_PS
-#define SCSI_Out__4__SHIFT 5
-#define SCSI_Out__4__SLW CYREG_PRT4_SLW
-#define SCSI_Out__5__AG CYREG_PRT4_AG
-#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__5__BIE CYREG_PRT4_BIE
-#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__5__BYP CYREG_PRT4_BYP
-#define SCSI_Out__5__CTL CYREG_PRT4_CTL
-#define SCSI_Out__5__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__5__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__5__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__5__DR CYREG_PRT4_DR
-#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__5__MASK 0x10u
-#define SCSI_Out__5__PC CYREG_PRT4_PC4
-#define SCSI_Out__5__PORT 4u
-#define SCSI_Out__5__PRT CYREG_PRT4_PRT
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__5__PS CYREG_PRT4_PS
-#define SCSI_Out__5__SHIFT 4
-#define SCSI_Out__5__SLW CYREG_PRT4_SLW
-#define SCSI_Out__6__AG CYREG_PRT0_AG
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__6__DR CYREG_PRT0_DR
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__6__MASK 0x80u
-#define SCSI_Out__6__PC CYREG_PRT0_PC7
-#define SCSI_Out__6__PORT 0u
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__6__PS CYREG_PRT0_PS
-#define SCSI_Out__6__SHIFT 7
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW
-#define SCSI_Out__7__AG CYREG_PRT0_AG
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__7__DR CYREG_PRT0_DR
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__7__MASK 0x40u
-#define SCSI_Out__7__PC CYREG_PRT0_PC6
-#define SCSI_Out__7__PORT 0u
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__7__PS CYREG_PRT0_PS
-#define SCSI_Out__7__SHIFT 6
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW
-#define SCSI_Out__8__AG CYREG_PRT0_AG
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__8__DR CYREG_PRT0_DR
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__8__MASK 0x08u
-#define SCSI_Out__8__PC CYREG_PRT0_PC3
-#define SCSI_Out__8__PORT 0u
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__8__PS CYREG_PRT0_PS
-#define SCSI_Out__8__SHIFT 3
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW
-#define SCSI_Out__9__AG CYREG_PRT0_AG
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__9__DR CYREG_PRT0_DR
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__9__MASK 0x04u
-#define SCSI_Out__9__PC CYREG_PRT0_PC2
-#define SCSI_Out__9__PORT 0u
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__9__PS CYREG_PRT0_PS
-#define SCSI_Out__9__SHIFT 2
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW
-#define SCSI_Out__ACK__AG CYREG_PRT6_AG
-#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP
-#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL
-#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__ACK__DR CYREG_PRT6_DR
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__ACK__MASK 0x01u
-#define SCSI_Out__ACK__PC CYREG_PRT6_PC0
-#define SCSI_Out__ACK__PORT 6u
-#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__ACK__PS CYREG_PRT6_PS
-#define SCSI_Out__ACK__SHIFT 0
-#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_Out__ATN__AG CYREG_PRT15_AG
-#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP
-#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL
-#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__ATN__DR CYREG_PRT15_DR
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__ATN__MASK 0x10u
-#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4
-#define SCSI_Out__ATN__PORT 15u
-#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__ATN__PS CYREG_PRT15_PS
-#define SCSI_Out__ATN__SHIFT 4
-#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW
-#define SCSI_Out__BSY__AG CYREG_PRT6_AG
-#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP
-#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL
-#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__BSY__DR CYREG_PRT6_DR
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__BSY__MASK 0x02u
-#define SCSI_Out__BSY__PC CYREG_PRT6_PC1
-#define SCSI_Out__BSY__PORT 6u
-#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__BSY__PS CYREG_PRT6_PS
-#define SCSI_Out__BSY__SHIFT 1
-#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__CD_raw__MASK 0x40u
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6
-#define SCSI_Out__CD_raw__PORT 0u
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__CD_raw__SHIFT 6
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__DBP_raw__MASK 0x20u
-#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5
-#define SCSI_Out__DBP_raw__PORT 15u
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS
-#define SCSI_Out__DBP_raw__SHIFT 5
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__IO_raw__MASK 0x04u
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2
-#define SCSI_Out__IO_raw__PORT 0u
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__IO_raw__SHIFT 2
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__MSG_raw__MASK 0x10u
-#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4
-#define SCSI_Out__MSG_raw__PORT 4u
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS
-#define SCSI_Out__MSG_raw__SHIFT 4
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__REQ__MASK 0x08u
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC3
-#define SCSI_Out__REQ__PORT 0u
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS
-#define SCSI_Out__REQ__SHIFT 3
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
-#define SCSI_Out__RST__AG CYREG_PRT4_AG
-#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__RST__BIE CYREG_PRT4_BIE
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__RST__BYP CYREG_PRT4_BYP
-#define SCSI_Out__RST__CTL CYREG_PRT4_CTL
-#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__RST__DR CYREG_PRT4_DR
-#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__RST__MASK 0x20u
-#define SCSI_Out__RST__PC CYREG_PRT4_PC5
-#define SCSI_Out__RST__PORT 4u
-#define SCSI_Out__RST__PRT CYREG_PRT4_PRT
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__RST__PS CYREG_PRT4_PS
-#define SCSI_Out__RST__SHIFT 5
-#define SCSI_Out__RST__SLW CYREG_PRT4_SLW
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__SEL__MASK 0x80u
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC7
-#define SCSI_Out__SEL__PORT 0u
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS
-#define SCSI_Out__SEL__SHIFT 7
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
+/* EXTLED */
+#define EXTLED__0__MASK 0x01u
+#define EXTLED__0__PC CYREG_PRT0_PC0
+#define EXTLED__0__PORT 0u
+#define EXTLED__0__SHIFT 0
+#define EXTLED__AG CYREG_PRT0_AG
+#define EXTLED__AMUX CYREG_PRT0_AMUX
+#define EXTLED__BIE CYREG_PRT0_BIE
+#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK
+#define EXTLED__BYP CYREG_PRT0_BYP
+#define EXTLED__CTL CYREG_PRT0_CTL
+#define EXTLED__DM0 CYREG_PRT0_DM0
+#define EXTLED__DM1 CYREG_PRT0_DM1
+#define EXTLED__DM2 CYREG_PRT0_DM2
+#define EXTLED__DR CYREG_PRT0_DR
+#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS
+#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN
+#define EXTLED__MASK 0x01u
+#define EXTLED__PORT 0u
+#define EXTLED__PRT CYREG_PRT0_PRT
+#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define EXTLED__PS CYREG_PRT0_PS
+#define EXTLED__SHIFT 0
+#define EXTLED__SLW CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB10_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB10_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB10_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB10_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_RxStsReg__4__POS 4
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
+#define SDCard_BSPIM_RxStsReg__5__POS 5
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
+#define SDCard_BSPIM_RxStsReg__6__POS 6
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB11_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB08_09_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB08_09_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB08_09_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB08_09_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB08_09_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB08_09_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB08_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB08_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB08_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB08_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB08_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB08_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB08_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB08_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB08_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB08_F1
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
+#define SDCard_BSPIM_TxStsReg__0__POS 0
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
+#define SDCard_BSPIM_TxStsReg__1__POS 1
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
+#define SDCard_BSPIM_TxStsReg__2__POS 2
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
+#define SDCard_BSPIM_TxStsReg__3__POS 3
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_TxStsReg__4__POS 4
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST
 
-/* USBFS_Dp */
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+#define SD_SCK__0__MASK 0x04u
+#define SD_SCK__0__PC CYREG_PRT3_PC2
+#define SD_SCK__0__PORT 3u
+#define SD_SCK__0__SHIFT 2
+#define SD_SCK__AG CYREG_PRT3_AG
+#define SD_SCK__AMUX CYREG_PRT3_AMUX
+#define SD_SCK__BIE CYREG_PRT3_BIE
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_SCK__BYP CYREG_PRT3_BYP
+#define SD_SCK__CTL CYREG_PRT3_CTL
+#define SD_SCK__DM0 CYREG_PRT3_DM0
+#define SD_SCK__DM1 CYREG_PRT3_DM1
+#define SD_SCK__DM2 CYREG_PRT3_DM2
+#define SD_SCK__DR CYREG_PRT3_DR
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_SCK__MASK 0x04u
+#define SD_SCK__PORT 3u
+#define SD_SCK__PRT CYREG_PRT3_PRT
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_SCK__PS CYREG_PRT3_PS
+#define SD_SCK__SHIFT 2
+#define SD_SCK__SLW CYREG_PRT3_SLW
 
 /* SCSI_In */
 #define SCSI_In__0__AG CYREG_PRT2_AG
@@ -2644,304 +788,2151 @@
 #define SCSI_In__REQ__SHIFT 5
 #define SCSI_In__REQ__SLW CYREG_PRT0_SLW
 
-/* SD_MISO */
-#define SD_MISO__0__MASK 0x02u
-#define SD_MISO__0__PC CYREG_PRT3_PC1
-#define SD_MISO__0__PORT 3u
-#define SD_MISO__0__SHIFT 1
-#define SD_MISO__AG CYREG_PRT3_AG
-#define SD_MISO__AMUX CYREG_PRT3_AMUX
-#define SD_MISO__BIE CYREG_PRT3_BIE
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MISO__BYP CYREG_PRT3_BYP
-#define SD_MISO__CTL CYREG_PRT3_CTL
-#define SD_MISO__DM0 CYREG_PRT3_DM0
-#define SD_MISO__DM1 CYREG_PRT3_DM1
-#define SD_MISO__DM2 CYREG_PRT3_DM2
-#define SD_MISO__DR CYREG_PRT3_DR
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MISO__MASK 0x02u
-#define SD_MISO__PORT 3u
-#define SD_MISO__PRT CYREG_PRT3_PRT
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MISO__PS CYREG_PRT3_PS
-#define SD_MISO__SHIFT 1
-#define SD_MISO__SLW CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+#define SCSI_In_DBx__0__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__0__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__0__MASK 0x08u
+#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3
+#define SCSI_In_DBx__0__PORT 5u
+#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__0__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__0__SHIFT 3
+#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__1__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__1__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__1__MASK 0x04u
+#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2
+#define SCSI_In_DBx__1__PORT 5u
+#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__1__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__1__SHIFT 2
+#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__2__MASK 0x80u
+#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7
+#define SCSI_In_DBx__2__PORT 6u
+#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__2__SHIFT 7
+#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__3__MASK 0x40u
+#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6
+#define SCSI_In_DBx__3__PORT 6u
+#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__3__SHIFT 6
+#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__4__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__4__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__4__MASK 0x20u
+#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5
+#define SCSI_In_DBx__4__PORT 12u
+#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__4__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__4__SHIFT 5
+#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__5__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__5__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__5__MASK 0x10u
+#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__5__PORT 12u
+#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__5__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__5__SHIFT 4
+#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__6__MASK 0x20u
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__6__PORT 2u
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__6__SHIFT 5
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__7__MASK 0x10u
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__7__PORT 2u
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__7__SHIFT 4
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__DB0__MASK 0x08u
+#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3
+#define SCSI_In_DBx__DB0__PORT 5u
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__DB0__SHIFT 3
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__DB1__MASK 0x04u
+#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2
+#define SCSI_In_DBx__DB1__PORT 5u
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__DB1__SHIFT 2
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB2__MASK 0x80u
+#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7
+#define SCSI_In_DBx__DB2__PORT 6u
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB2__SHIFT 7
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB3__MASK 0x40u
+#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6
+#define SCSI_In_DBx__DB3__PORT 6u
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB3__SHIFT 6
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__DB4__MASK 0x20u
+#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5
+#define SCSI_In_DBx__DB4__PORT 12u
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__DB4__SHIFT 5
+#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__DB5__MASK 0x10u
+#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__DB5__PORT 12u
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__DB5__SHIFT 4
+#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB6__MASK 0x20u
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__DB6__PORT 2u
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB6__SHIFT 5
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB7__MASK 0x10u
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__DB7__PORT 2u
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB7__SHIFT 4
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
+
+/* SD_MISO */
+#define SD_MISO__0__MASK 0x02u
+#define SD_MISO__0__PC CYREG_PRT3_PC1
+#define SD_MISO__0__PORT 3u
+#define SD_MISO__0__SHIFT 1
+#define SD_MISO__AG CYREG_PRT3_AG
+#define SD_MISO__AMUX CYREG_PRT3_AMUX
+#define SD_MISO__BIE CYREG_PRT3_BIE
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MISO__BYP CYREG_PRT3_BYP
+#define SD_MISO__CTL CYREG_PRT3_CTL
+#define SD_MISO__DM0 CYREG_PRT3_DM0
+#define SD_MISO__DM1 CYREG_PRT3_DM1
+#define SD_MISO__DM2 CYREG_PRT3_DM2
+#define SD_MISO__DR CYREG_PRT3_DR
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MISO__MASK 0x02u
+#define SD_MISO__PORT 3u
+#define SD_MISO__PRT CYREG_PRT3_PRT
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MISO__PS CYREG_PRT3_PS
+#define SD_MISO__SHIFT 1
+#define SD_MISO__SLW CYREG_PRT3_SLW
+
+/* SD_MOSI */
+#define SD_MOSI__0__MASK 0x08u
+#define SD_MOSI__0__PC CYREG_PRT3_PC3
+#define SD_MOSI__0__PORT 3u
+#define SD_MOSI__0__SHIFT 3
+#define SD_MOSI__AG CYREG_PRT3_AG
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX
+#define SD_MOSI__BIE CYREG_PRT3_BIE
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MOSI__BYP CYREG_PRT3_BYP
+#define SD_MOSI__CTL CYREG_PRT3_CTL
+#define SD_MOSI__DM0 CYREG_PRT3_DM0
+#define SD_MOSI__DM1 CYREG_PRT3_DM1
+#define SD_MOSI__DM2 CYREG_PRT3_DM2
+#define SD_MOSI__DR CYREG_PRT3_DR
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MOSI__MASK 0x08u
+#define SD_MOSI__PORT 3u
+#define SD_MOSI__PRT CYREG_PRT3_PRT
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MOSI__PS CYREG_PRT3_PS
+#define SD_MOSI__SHIFT 3
+#define SD_MOSI__SLW CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
+#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SCSI_CLK__PM_STBY_MSK 0x02u
+
+/* SCSI_Out */
+#define SCSI_Out__0__AG CYREG_PRT15_AG
+#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__0__BIE CYREG_PRT15_BIE
+#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__0__BYP CYREG_PRT15_BYP
+#define SCSI_Out__0__CTL CYREG_PRT15_CTL
+#define SCSI_Out__0__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__0__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__0__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__0__DR CYREG_PRT15_DR
+#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__0__MASK 0x20u
+#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5
+#define SCSI_Out__0__PORT 15u
+#define SCSI_Out__0__PRT CYREG_PRT15_PRT
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__0__PS CYREG_PRT15_PS
+#define SCSI_Out__0__SHIFT 5
+#define SCSI_Out__0__SLW CYREG_PRT15_SLW
+#define SCSI_Out__1__AG CYREG_PRT15_AG
+#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__1__BIE CYREG_PRT15_BIE
+#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__1__BYP CYREG_PRT15_BYP
+#define SCSI_Out__1__CTL CYREG_PRT15_CTL
+#define SCSI_Out__1__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__1__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__1__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__1__DR CYREG_PRT15_DR
+#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__1__MASK 0x10u
+#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4
+#define SCSI_Out__1__PORT 15u
+#define SCSI_Out__1__PRT CYREG_PRT15_PRT
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__1__PS CYREG_PRT15_PS
+#define SCSI_Out__1__SHIFT 4
+#define SCSI_Out__1__SLW CYREG_PRT15_SLW
+#define SCSI_Out__2__AG CYREG_PRT6_AG
+#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__2__DR CYREG_PRT6_DR
+#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__2__MASK 0x02u
+#define SCSI_Out__2__PC CYREG_PRT6_PC1
+#define SCSI_Out__2__PORT 6u
+#define SCSI_Out__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__2__PS CYREG_PRT6_PS
+#define SCSI_Out__2__SHIFT 1
+#define SCSI_Out__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out__3__AG CYREG_PRT6_AG
+#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__3__DR CYREG_PRT6_DR
+#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__3__MASK 0x01u
+#define SCSI_Out__3__PC CYREG_PRT6_PC0
+#define SCSI_Out__3__PORT 6u
+#define SCSI_Out__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__3__PS CYREG_PRT6_PS
+#define SCSI_Out__3__SHIFT 0
+#define SCSI_Out__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out__4__AG CYREG_PRT4_AG
+#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__4__BIE CYREG_PRT4_BIE
+#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__4__BYP CYREG_PRT4_BYP
+#define SCSI_Out__4__CTL CYREG_PRT4_CTL
+#define SCSI_Out__4__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__4__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__4__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__4__DR CYREG_PRT4_DR
+#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__4__MASK 0x20u
+#define SCSI_Out__4__PC CYREG_PRT4_PC5
+#define SCSI_Out__4__PORT 4u
+#define SCSI_Out__4__PRT CYREG_PRT4_PRT
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__4__PS CYREG_PRT4_PS
+#define SCSI_Out__4__SHIFT 5
+#define SCSI_Out__4__SLW CYREG_PRT4_SLW
+#define SCSI_Out__5__AG CYREG_PRT4_AG
+#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__5__BIE CYREG_PRT4_BIE
+#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__5__BYP CYREG_PRT4_BYP
+#define SCSI_Out__5__CTL CYREG_PRT4_CTL
+#define SCSI_Out__5__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__5__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__5__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__5__DR CYREG_PRT4_DR
+#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__5__MASK 0x10u
+#define SCSI_Out__5__PC CYREG_PRT4_PC4
+#define SCSI_Out__5__PORT 4u
+#define SCSI_Out__5__PRT CYREG_PRT4_PRT
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__5__PS CYREG_PRT4_PS
+#define SCSI_Out__5__SHIFT 4
+#define SCSI_Out__5__SLW CYREG_PRT4_SLW
+#define SCSI_Out__6__AG CYREG_PRT0_AG
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__6__DR CYREG_PRT0_DR
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__6__MASK 0x80u
+#define SCSI_Out__6__PC CYREG_PRT0_PC7
+#define SCSI_Out__6__PORT 0u
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__6__PS CYREG_PRT0_PS
+#define SCSI_Out__6__SHIFT 7
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW
+#define SCSI_Out__7__AG CYREG_PRT0_AG
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__7__DR CYREG_PRT0_DR
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__7__MASK 0x40u
+#define SCSI_Out__7__PC CYREG_PRT0_PC6
+#define SCSI_Out__7__PORT 0u
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__7__PS CYREG_PRT0_PS
+#define SCSI_Out__7__SHIFT 6
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW
+#define SCSI_Out__8__AG CYREG_PRT0_AG
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__8__DR CYREG_PRT0_DR
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__8__MASK 0x08u
+#define SCSI_Out__8__PC CYREG_PRT0_PC3
+#define SCSI_Out__8__PORT 0u
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__8__PS CYREG_PRT0_PS
+#define SCSI_Out__8__SHIFT 3
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW
+#define SCSI_Out__9__AG CYREG_PRT0_AG
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__9__DR CYREG_PRT0_DR
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__9__MASK 0x04u
+#define SCSI_Out__9__PC CYREG_PRT0_PC2
+#define SCSI_Out__9__PORT 0u
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__9__PS CYREG_PRT0_PS
+#define SCSI_Out__9__SHIFT 2
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW
+#define SCSI_Out__ACK__AG CYREG_PRT6_AG
+#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP
+#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL
+#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__ACK__DR CYREG_PRT6_DR
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__ACK__MASK 0x01u
+#define SCSI_Out__ACK__PC CYREG_PRT6_PC0
+#define SCSI_Out__ACK__PORT 6u
+#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__ACK__PS CYREG_PRT6_PS
+#define SCSI_Out__ACK__SHIFT 0
+#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW
+#define SCSI_Out__ATN__AG CYREG_PRT15_AG
+#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP
+#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL
+#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__ATN__DR CYREG_PRT15_DR
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__ATN__MASK 0x10u
+#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4
+#define SCSI_Out__ATN__PORT 15u
+#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__ATN__PS CYREG_PRT15_PS
+#define SCSI_Out__ATN__SHIFT 4
+#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW
+#define SCSI_Out__BSY__AG CYREG_PRT6_AG
+#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP
+#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL
+#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__BSY__DR CYREG_PRT6_DR
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__BSY__MASK 0x02u
+#define SCSI_Out__BSY__PC CYREG_PRT6_PC1
+#define SCSI_Out__BSY__PORT 6u
+#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__BSY__PS CYREG_PRT6_PS
+#define SCSI_Out__BSY__SHIFT 1
+#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__CD_raw__MASK 0x40u
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6
+#define SCSI_Out__CD_raw__PORT 0u
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__CD_raw__SHIFT 6
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__DBP_raw__MASK 0x20u
+#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5
+#define SCSI_Out__DBP_raw__PORT 15u
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS
+#define SCSI_Out__DBP_raw__SHIFT 5
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__IO_raw__MASK 0x04u
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2
+#define SCSI_Out__IO_raw__PORT 0u
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__IO_raw__SHIFT 2
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__MSG_raw__MASK 0x10u
+#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4
+#define SCSI_Out__MSG_raw__PORT 4u
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS
+#define SCSI_Out__MSG_raw__SHIFT 4
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__REQ__MASK 0x08u
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC3
+#define SCSI_Out__REQ__PORT 0u
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS
+#define SCSI_Out__REQ__SHIFT 3
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
+#define SCSI_Out__RST__AG CYREG_PRT4_AG
+#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__RST__BIE CYREG_PRT4_BIE
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__RST__BYP CYREG_PRT4_BYP
+#define SCSI_Out__RST__CTL CYREG_PRT4_CTL
+#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__RST__DR CYREG_PRT4_DR
+#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__RST__MASK 0x20u
+#define SCSI_Out__RST__PC CYREG_PRT4_PC5
+#define SCSI_Out__RST__PORT 4u
+#define SCSI_Out__RST__PRT CYREG_PRT4_PRT
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__RST__PS CYREG_PRT4_PS
+#define SCSI_Out__RST__SHIFT 5
+#define SCSI_Out__RST__SLW CYREG_PRT4_SLW
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__SEL__MASK 0x80u
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC7
+#define SCSI_Out__SEL__PORT 0u
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS
+#define SCSI_Out__SEL__SHIFT 7
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
+
+/* SCSI_Out_Ctl */
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
+
+/* SCSI_Out_DBx */
+#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x02u
+#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__0__PORT 5u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__0__SHIFT 1
+#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x01u
+#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__1__PORT 5u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__1__SHIFT 0
+#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__2__MASK 0x20u
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__2__PORT 6u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__2__SHIFT 5
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x10u
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__3__PORT 6u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__3__SHIFT 4
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x80u
+#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__4__PORT 2u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__4__SHIFT 7
+#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x40u
+#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__5__PORT 2u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__5__SHIFT 6
+#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x08u
+#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__6__PORT 2u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__6__SHIFT 3
+#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x04u
+#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__7__PORT 2u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__7__SHIFT 2
+#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x02u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__DB0__PORT 5u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB0__SHIFT 1
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x01u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__DB1__PORT 5u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB1__SHIFT 0
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB2__MASK 0x20u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__DB2__PORT 6u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB2__SHIFT 5
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x10u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__DB3__PORT 6u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB3__SHIFT 4
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x80u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__DB4__PORT 2u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB4__SHIFT 7
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x40u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__DB5__PORT 2u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB5__SHIFT 6
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x08u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__DB6__PORT 2u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB6__SHIFT 3
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x04u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__DB7__PORT 2u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB7__SHIFT 2
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
+
+/* SD_RX_DMA */
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_RX_DMA__DRQ_NUMBER 2u
+#define SD_RX_DMA__NUMBEROF_TDS 0u
+#define SD_RX_DMA__PRIORITY 2u
+#define SD_RX_DMA__TERMIN_EN 0u
+#define SD_RX_DMA__TERMIN_SEL 0u
+#define SD_RX_DMA__TERMOUT0_EN 1u
+#define SD_RX_DMA__TERMOUT0_SEL 2u
+#define SD_RX_DMA__TERMOUT1_EN 0u
+#define SD_RX_DMA__TERMOUT1_SEL 0u
+
+/* SD_RX_DMA_COMPLETE */
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_TX_DMA__DRQ_NUMBER 3u
+#define SD_TX_DMA__NUMBEROF_TDS 0u
+#define SD_TX_DMA__PRIORITY 2u
+#define SD_TX_DMA__TERMIN_EN 0u
+#define SD_TX_DMA__TERMIN_SEL 0u
+#define SD_TX_DMA__TERMOUT0_EN 1u
+#define SD_TX_DMA__TERMOUT0_SEL 3u
+#define SD_TX_DMA__TERMOUT1_EN 0u
+#define SD_TX_DMA__TERMOUT1_SEL 0u
+
+/* SD_TX_DMA_COMPLETE */
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+#define SCSI_Noise__0__AG CYREG_PRT2_AG
+#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX
+#define SCSI_Noise__0__BIE CYREG_PRT2_BIE
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Noise__0__BYP CYREG_PRT2_BYP
+#define SCSI_Noise__0__CTL CYREG_PRT2_CTL
+#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0
+#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1
+#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2
+#define SCSI_Noise__0__DR CYREG_PRT2_DR
+#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Noise__0__MASK 0x01u
+#define SCSI_Noise__0__PC CYREG_PRT2_PC0
+#define SCSI_Noise__0__PORT 2u
+#define SCSI_Noise__0__PRT CYREG_PRT2_PRT
+#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Noise__0__PS CYREG_PRT2_PS
+#define SCSI_Noise__0__SHIFT 0
+#define SCSI_Noise__0__SLW CYREG_PRT2_SLW
+#define SCSI_Noise__1__AG CYREG_PRT6_AG
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__1__DR CYREG_PRT6_DR
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__1__MASK 0x08u
+#define SCSI_Noise__1__PC CYREG_PRT6_PC3
+#define SCSI_Noise__1__PORT 6u
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__1__PS CYREG_PRT6_PS
+#define SCSI_Noise__1__SHIFT 3
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__2__AG CYREG_PRT4_AG
+#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__2__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__2__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__2__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__2__DR CYREG_PRT4_DR
+#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__2__MASK 0x08u
+#define SCSI_Noise__2__PC CYREG_PRT4_PC3
+#define SCSI_Noise__2__PORT 4u
+#define SCSI_Noise__2__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__2__PS CYREG_PRT4_PS
+#define SCSI_Noise__2__SHIFT 3
+#define SCSI_Noise__2__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__3__AG CYREG_PRT4_AG
+#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__3__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__3__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__3__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__3__DR CYREG_PRT4_DR
+#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__3__MASK 0x80u
+#define SCSI_Noise__3__PC CYREG_PRT4_PC7
+#define SCSI_Noise__3__PORT 4u
+#define SCSI_Noise__3__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__3__PS CYREG_PRT4_PS
+#define SCSI_Noise__3__SHIFT 7
+#define SCSI_Noise__3__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__4__AG CYREG_PRT6_AG
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__4__DR CYREG_PRT6_DR
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__4__MASK 0x04u
+#define SCSI_Noise__4__PC CYREG_PRT6_PC2
+#define SCSI_Noise__4__PORT 6u
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__4__PS CYREG_PRT6_PS
+#define SCSI_Noise__4__SHIFT 2
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__ACK__MASK 0x04u
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2
+#define SCSI_Noise__ACK__PORT 6u
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
+#define SCSI_Noise__ACK__SHIFT 2
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ATN__AG CYREG_PRT2_AG
+#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX
+#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP
+#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL
+#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0
+#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1
+#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2
+#define SCSI_Noise__ATN__DR CYREG_PRT2_DR
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Noise__ATN__MASK 0x01u
+#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0
+#define SCSI_Noise__ATN__PORT 2u
+#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT
+#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Noise__ATN__PS CYREG_PRT2_PS
+#define SCSI_Noise__ATN__SHIFT 0
+#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__BSY__MASK 0x08u
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3
+#define SCSI_Noise__BSY__PORT 6u
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
+#define SCSI_Noise__BSY__SHIFT 3
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__RST__AG CYREG_PRT4_AG
+#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__RST__DR CYREG_PRT4_DR
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__RST__MASK 0x80u
+#define SCSI_Noise__RST__PC CYREG_PRT4_PC7
+#define SCSI_Noise__RST__PORT 4u
+#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__RST__PS CYREG_PRT4_PS
+#define SCSI_Noise__RST__SHIFT 7
+#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__SEL__AG CYREG_PRT4_AG
+#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__SEL__DR CYREG_PRT4_DR
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__SEL__MASK 0x08u
+#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3
+#define SCSI_Noise__SEL__PORT 4u
+#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__SEL__PS CYREG_PRT4_PS
+#define SCSI_Noise__SEL__SHIFT 3
+#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
+
+/* scsiTarget */
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_StatusReg__0__MASK 0x01u
+#define scsiTarget_StatusReg__0__POS 0
+#define scsiTarget_StatusReg__1__MASK 0x02u
+#define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
+#define scsiTarget_StatusReg__2__MASK 0x04u
+#define scsiTarget_StatusReg__2__POS 2
+#define scsiTarget_StatusReg__3__MASK 0x08u
+#define scsiTarget_StatusReg__3__POS 3
+#define scsiTarget_StatusReg__4__MASK 0x10u
+#define scsiTarget_StatusReg__4__POS 4
+#define scsiTarget_StatusReg__MASK 0x1Fu
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST
 
-/* SD_MOSI */
-#define SD_MOSI__0__MASK 0x08u
-#define SD_MOSI__0__PC CYREG_PRT3_PC3
-#define SD_MOSI__0__PORT 3u
-#define SD_MOSI__0__SHIFT 3
-#define SD_MOSI__AG CYREG_PRT3_AG
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX
-#define SD_MOSI__BIE CYREG_PRT3_BIE
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MOSI__BYP CYREG_PRT3_BYP
-#define SD_MOSI__CTL CYREG_PRT3_CTL
-#define SD_MOSI__DM0 CYREG_PRT3_DM0
-#define SD_MOSI__DM1 CYREG_PRT3_DM1
-#define SD_MOSI__DM2 CYREG_PRT3_DM2
-#define SD_MOSI__DR CYREG_PRT3_DR
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MOSI__MASK 0x08u
-#define SD_MOSI__PORT 3u
-#define SD_MOSI__PRT CYREG_PRT3_PRT
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MOSI__PS CYREG_PRT3_PS
-#define SD_MOSI__SHIFT 3
-#define SD_MOSI__SLW CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define Debug_Timer_Interrupt__INTC_MASK 0x02u
+#define Debug_Timer_Interrupt__INTC_NUMBER 1u
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_RX_DMA__DRQ_NUMBER 0u
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u
+#define SCSI_RX_DMA__PRIORITY 2u
+#define SCSI_RX_DMA__TERMIN_EN 0u
+#define SCSI_RX_DMA__TERMIN_SEL 0u
+#define SCSI_RX_DMA__TERMOUT0_EN 1u
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u
+#define SCSI_RX_DMA__TERMOUT1_EN 0u
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u
+
+/* SCSI_RX_DMA_COMPLETE */
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_TX_DMA__DRQ_NUMBER 1u
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u
+#define SCSI_TX_DMA__PRIORITY 2u
+#define SCSI_TX_DMA__TERMIN_EN 0u
+#define SCSI_TX_DMA__TERMIN_SEL 0u
+#define SCSI_TX_DMA__TERMOUT0_EN 1u
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u
+#define SCSI_TX_DMA__TERMOUT1_EN 0u
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u
+
+/* SCSI_TX_DMA_COMPLETE */
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
+#define SD_Data_Clk__INDEX 0x00u
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SD_Data_Clk__PM_ACT_MSK 0x01u
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SD_Data_Clk__PM_STBY_MSK 0x01u
 
-/* EXTLED */
-#define EXTLED__0__MASK 0x01u
-#define EXTLED__0__PC CYREG_PRT0_PC0
-#define EXTLED__0__PORT 0u
-#define EXTLED__0__SHIFT 0
-#define EXTLED__AG CYREG_PRT0_AG
-#define EXTLED__AMUX CYREG_PRT0_AMUX
-#define EXTLED__BIE CYREG_PRT0_BIE
-#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK
-#define EXTLED__BYP CYREG_PRT0_BYP
-#define EXTLED__CTL CYREG_PRT0_CTL
-#define EXTLED__DM0 CYREG_PRT0_DM0
-#define EXTLED__DM1 CYREG_PRT0_DM1
-#define EXTLED__DM2 CYREG_PRT0_DM2
-#define EXTLED__DR CYREG_PRT0_DR
-#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS
-#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN
-#define EXTLED__MASK 0x01u
-#define EXTLED__PORT 0u
-#define EXTLED__PRT CYREG_PRT0_PRT
-#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define EXTLED__PS CYREG_PRT0_PS
-#define EXTLED__SHIFT 0
-#define EXTLED__SLW CYREG_PRT0_SLW
+/* timer_clock */
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
+#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
+#define timer_clock__INDEX 0x02u
+#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define timer_clock__PM_ACT_MSK 0x04u
+#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define timer_clock__PM_STBY_MSK 0x04u
 
-/* SD_SCK */
-#define SD_SCK__0__MASK 0x04u
-#define SD_SCK__0__PC CYREG_PRT3_PC2
-#define SD_SCK__0__PORT 3u
-#define SD_SCK__0__SHIFT 2
-#define SD_SCK__AG CYREG_PRT3_AG
-#define SD_SCK__AMUX CYREG_PRT3_AMUX
-#define SD_SCK__BIE CYREG_PRT3_BIE
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_SCK__BYP CYREG_PRT3_BYP
-#define SD_SCK__CTL CYREG_PRT3_CTL
-#define SD_SCK__DM0 CYREG_PRT3_DM0
-#define SD_SCK__DM1 CYREG_PRT3_DM1
-#define SD_SCK__DM2 CYREG_PRT3_DM2
-#define SD_SCK__DR CYREG_PRT3_DR
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_SCK__MASK 0x04u
-#define SD_SCK__PORT 3u
-#define SD_SCK__PRT CYREG_PRT3_PRT
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_SCK__PS CYREG_PRT3_PS
-#define SD_SCK__SHIFT 2
-#define SD_SCK__SLW CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RST_ISR__INTC_MASK 0x04u
+#define SCSI_RST_ISR__INTC_NUMBER 2u
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SD_CD */
-#define SD_CD__0__MASK 0x20u
-#define SD_CD__0__PC CYREG_PRT3_PC5
-#define SD_CD__0__PORT 3u
-#define SD_CD__0__SHIFT 5
-#define SD_CD__AG CYREG_PRT3_AG
-#define SD_CD__AMUX CYREG_PRT3_AMUX
-#define SD_CD__BIE CYREG_PRT3_BIE
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CD__BYP CYREG_PRT3_BYP
-#define SD_CD__CTL CYREG_PRT3_CTL
-#define SD_CD__DM0 CYREG_PRT3_DM0
-#define SD_CD__DM1 CYREG_PRT3_DM1
-#define SD_CD__DM2 CYREG_PRT3_DM2
-#define SD_CD__DR CYREG_PRT3_DR
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CD__MASK 0x20u
-#define SD_CD__PORT 3u
-#define SD_CD__PRT CYREG_PRT3_PRT
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CD__PS CYREG_PRT3_PS
-#define SD_CD__SHIFT 5
-#define SD_CD__SLW CYREG_PRT3_SLW
+/* SCSI_Filtered */
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Filtered_sts_sts_reg__0__POS 0
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
+#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
+#define SCSI_Filtered_sts_sts_reg__2__POS 2
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
+#define SCSI_Filtered_sts_sts_reg__3__POS 3
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
+#define SCSI_Filtered_sts_sts_reg__4__POS 4
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
 
-/* SD_CS */
-#define SD_CS__0__MASK 0x10u
-#define SD_CS__0__PC CYREG_PRT3_PC4
-#define SD_CS__0__PORT 3u
-#define SD_CS__0__SHIFT 4
-#define SD_CS__AG CYREG_PRT3_AG
-#define SD_CS__AMUX CYREG_PRT3_AMUX
-#define SD_CS__BIE CYREG_PRT3_BIE
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CS__BYP CYREG_PRT3_BYP
-#define SD_CS__CTL CYREG_PRT3_CTL
-#define SD_CS__DM0 CYREG_PRT3_DM0
-#define SD_CS__DM1 CYREG_PRT3_DM1
-#define SD_CS__DM2 CYREG_PRT3_DM2
-#define SD_CS__DR CYREG_PRT3_DR
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CS__MASK 0x10u
-#define SD_CS__PORT 3u
-#define SD_CS__PRT CYREG_PRT3_PRT
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CS__PS CYREG_PRT3_PS
-#define SD_CS__SHIFT 4
-#define SD_CS__SLW CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
 
-/* LED1 */
-#define LED1__0__MASK 0x02u
-#define LED1__0__PC CYREG_PRT0_PC1
-#define LED1__0__PORT 0u
-#define LED1__0__SHIFT 1
-#define LED1__AG CYREG_PRT0_AG
-#define LED1__AMUX CYREG_PRT0_AMUX
-#define LED1__BIE CYREG_PRT0_BIE
-#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK
-#define LED1__BYP CYREG_PRT0_BYP
-#define LED1__CTL CYREG_PRT0_CTL
-#define LED1__DM0 CYREG_PRT0_DM0
-#define LED1__DM1 CYREG_PRT0_DM1
-#define LED1__DM2 CYREG_PRT0_DM2
-#define LED1__DR CYREG_PRT0_DR
-#define LED1__INP_DIS CYREG_PRT0_INP_DIS
-#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define LED1__LCD_EN CYREG_PRT0_LCD_EN
-#define LED1__MASK 0x02u
-#define LED1__PORT 0u
-#define LED1__PRT CYREG_PRT0_PRT
-#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define LED1__PS CYREG_PRT0_PS
-#define LED1__SHIFT 1
-#define LED1__SLW CYREG_PRT0_SLW
+/* SCSI_Parity_Error */
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB03_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB03_ST
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
-#define CYDEV_CHIP_MEMBER_5B 4u
-#define CYDEV_CHIP_FAMILY_PSOC5 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 4u
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
 #define BCLK__BUS_CLK__HZ 50000000U
 #define BCLK__BUS_CLK__KHZ 50000U
 #define BCLK__BUS_CLK__MHZ 50U
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CY_VERSION "PSoC Creator  3.1"
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 3u
-#define CYDEV_CHIP_DIE_PSOC4A 2u
+#define CYDEV_CHIP_DIE_PANTHER 6u
+#define CYDEV_CHIP_DIE_PSOC4A 3u
+#define CYDEV_CHIP_DIE_PSOC5LP 5u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
+#define CYDEV_CHIP_FAMILY_PSOC5 3u
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 2u
-#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_4A 3u
+#define CYDEV_CHIP_MEMBER_4D 2u
+#define CYDEV_CHIP_MEMBER_4F 4u
+#define CYDEV_CHIP_MEMBER_5A 6u
+#define CYDEV_CHIP_MEMBER_5B 5u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_3A_ES1 0u
 #define CYDEV_CHIP_REVISION_3A_ES2 1u
 #define CYDEV_CHIP_REVISION_3A_ES3 3u
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
 #define CYDEV_CHIP_REVISION_5B_ES0 0u
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
 #define CYDEV_CONFIGURATION_COMPRESSED 1
 #define CYDEV_CONFIGURATION_DMA 0
 #define CYDEV_CONFIGURATION_ECC 0
 #define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
 #define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
 #define CYDEV_CONFIGURATION_MODE_DMA 2
 #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DEBUGGING_DPS_Disable 3
 #define CYDEV_DEBUGGING_DPS_JTAG_4 1
 #define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
 #define CYDEV_DEBUGGING_ENABLE 1
 #define CYDEV_DEBUGGING_XRES 0
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DMA_CHANNELS_AVAILABLE 24u
 #define CYDEV_ECC_ENABLE 0
-#define CYDEV_HEAP_SIZE 0x1000
+#define CYDEV_HEAP_SIZE 0x0400
 #define CYDEV_INSTRUCT_CACHE_ENABLED 1
 #define CYDEV_INTR_RISING 0x0000003Eu
 #define CYDEV_PROJ_TYPE 2
@@ -2950,7 +2941,7 @@
 #define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
 #define CYDEV_PROJ_TYPE_STANDARD 0
 #define CYDEV_PROTECTION_ENABLE 0
-#define CYDEV_STACK_SIZE 0x4000
+#define CYDEV_STACK_SIZE 0x1000
 #define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP 
 #define CYDEV_USE_BUNDLED_CMSIS 1
 #define CYDEV_VARIABLE_VDDA 0
@@ -2966,14 +2957,34 @@
 #define CYDEV_VDDIO2_MV 5000
 #define CYDEV_VDDIO3 3.3
 #define CYDEV_VDDIO3_MV 3300
-#define CYDEV_VIO0 5
+#define CYDEV_VIO0 5.0
 #define CYDEV_VIO0_MV 5000
-#define CYDEV_VIO1 5
+#define CYDEV_VIO1 5.0
 #define CYDEV_VIO1_MV 5000
-#define CYDEV_VIO2 5
+#define CYDEV_VIO2 5.0
 #define CYDEV_VIO2_MV 5000
 #define CYDEV_VIO3 3.3
 #define CYDEV_VIO3_MV 3300
+#define CYIPBLOCK_ARM_CM3_VERSION 0
+#define CYIPBLOCK_P3_ANAIF_VERSION 0
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
+#define CYIPBLOCK_P3_COMP_VERSION 0
+#define CYIPBLOCK_P3_DMA_VERSION 0
+#define CYIPBLOCK_P3_DRQ_VERSION 0
+#define CYIPBLOCK_P3_EMIF_VERSION 0
+#define CYIPBLOCK_P3_I2C_VERSION 0
+#define CYIPBLOCK_P3_LCD_VERSION 0
+#define CYIPBLOCK_P3_LPF_VERSION 0
+#define CYIPBLOCK_P3_PM_VERSION 0
+#define CYIPBLOCK_P3_TIMER_VERSION 0
+#define CYIPBLOCK_P3_USB_VERSION 0
+#define CYIPBLOCK_P3_VIDAC_VERSION 0
+#define CYIPBLOCK_P3_VREF_VERSION 0
+#define CYIPBLOCK_S8_GPIO_VERSION 0
+#define CYIPBLOCK_S8_IRQ_VERSION 0
+#define CYIPBLOCK_S8_SAR_VERSION 0
+#define CYIPBLOCK_S8_SIO_VERSION 0
+#define CYIPBLOCK_S8_UDB_VERSION 0
 #define DMA_CHANNELS_USED__MASK0 0x0000000Fu
 #define CYDEV_BOOTLOADER_ENABLE 0
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 6937f9ee..81a8b880 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator with device 
@@ -380,43 +380,43 @@ void cyfitter_cfg(void)
 		static const uint32 CYCODE cy_cfg_addr_table[] = {
 			0x40004501u, /* Base address: 0x40004500 Count: 1 */
 			0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
-			0x40005210u, /* Base address: 0x40005200 Count: 16 */
+			0x4000520Fu, /* Base address: 0x40005200 Count: 15 */
 			0x40006401u, /* Base address: 0x40006400 Count: 1 */
 			0x40006501u, /* Base address: 0x40006500 Count: 1 */
-			0x40010046u, /* Base address: 0x40010000 Count: 70 */
-			0x4001013Bu, /* Base address: 0x40010100 Count: 59 */
-			0x40010249u, /* Base address: 0x40010200 Count: 73 */
-			0x4001035Bu, /* Base address: 0x40010300 Count: 91 */
-			0x4001044Fu, /* Base address: 0x40010400 Count: 79 */
-			0x40010551u, /* Base address: 0x40010500 Count: 81 */
-			0x40010715u, /* Base address: 0x40010700 Count: 21 */
-			0x4001081Bu, /* Base address: 0x40010800 Count: 27 */
-			0x40010955u, /* Base address: 0x40010900 Count: 85 */
-			0x40010A48u, /* Base address: 0x40010A00 Count: 72 */
-			0x40010B56u, /* Base address: 0x40010B00 Count: 86 */
-			0x40010C42u, /* Base address: 0x40010C00 Count: 66 */
-			0x40010D59u, /* Base address: 0x40010D00 Count: 89 */
-			0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */
-			0x40010F33u, /* Base address: 0x40010F00 Count: 51 */
-			0x4001150Du, /* Base address: 0x40011500 Count: 13 */
-			0x4001170Au, /* Base address: 0x40011700 Count: 10 */
-			0x40011858u, /* Base address: 0x40011800 Count: 88 */
-			0x40011949u, /* Base address: 0x40011900 Count: 73 */
-			0x40011A53u, /* Base address: 0x40011A00 Count: 83 */
-			0x40011B4Bu, /* Base address: 0x40011B00 Count: 75 */
-			0x40014019u, /* Base address: 0x40014000 Count: 25 */
+			0x40010050u, /* Base address: 0x40010000 Count: 80 */
+			0x4001013Eu, /* Base address: 0x40010100 Count: 62 */
+			0x4001024Eu, /* Base address: 0x40010200 Count: 78 */
+			0x40010358u, /* Base address: 0x40010300 Count: 88 */
+			0x40010450u, /* Base address: 0x40010400 Count: 80 */
+			0x4001054Eu, /* Base address: 0x40010500 Count: 78 */
+			0x4001070Fu, /* Base address: 0x40010700 Count: 15 */
+			0x4001084Bu, /* Base address: 0x40010800 Count: 75 */
+			0x40010942u, /* Base address: 0x40010900 Count: 66 */
+			0x40010A39u, /* Base address: 0x40010A00 Count: 57 */
+			0x40010B50u, /* Base address: 0x40010B00 Count: 80 */
+			0x40010C52u, /* Base address: 0x40010C00 Count: 82 */
+			0x40010D54u, /* Base address: 0x40010D00 Count: 84 */
+			0x40010E46u, /* Base address: 0x40010E00 Count: 70 */
+			0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */
+			0x40011505u, /* Base address: 0x40011500 Count: 5 */
+			0x40011703u, /* Base address: 0x40011700 Count: 3 */
+			0x40011857u, /* Base address: 0x40011800 Count: 87 */
+			0x40011941u, /* Base address: 0x40011900 Count: 65 */
+			0x40011A4Bu, /* Base address: 0x40011A00 Count: 75 */
+			0x40011B48u, /* Base address: 0x40011B00 Count: 72 */
+			0x40014014u, /* Base address: 0x40014000 Count: 20 */
 			0x4001411Bu, /* Base address: 0x40014100 Count: 27 */
-			0x4001420Fu, /* Base address: 0x40014200 Count: 15 */
-			0x40014308u, /* Base address: 0x40014300 Count: 8 */
+			0x40014217u, /* Base address: 0x40014200 Count: 23 */
+			0x4001430Au, /* Base address: 0x40014300 Count: 10 */
 			0x40014414u, /* Base address: 0x40014400 Count: 20 */
-			0x4001451Cu, /* Base address: 0x40014500 Count: 28 */
+			0x40014519u, /* Base address: 0x40014500 Count: 25 */
 			0x4001460Fu, /* Base address: 0x40014600 Count: 15 */
-			0x40014715u, /* Base address: 0x40014700 Count: 21 */
-			0x40014805u, /* Base address: 0x40014800 Count: 5 */
-			0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
-			0x40014C03u, /* Base address: 0x40014C00 Count: 3 */
-			0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */
-			0x40015002u, /* Base address: 0x40015000 Count: 2 */
+			0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
+			0x40014809u, /* Base address: 0x40014800 Count: 9 */
+			0x4001490Eu, /* Base address: 0x40014900 Count: 14 */
+			0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
+			0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */
+			0x40015004u, /* Base address: 0x40015000 Count: 4 */
 			0x40015104u, /* Base address: 0x40015100 Count: 4 */
 		};
 
@@ -424,952 +424,979 @@ void cyfitter_cfg(void)
 			{0x7Eu, 0x02u},
 			{0x01u, 0x20u},
 			{0x0Au, 0x4Bu},
-			{0x00u, 0x08u},
-			{0x01u, 0x44u},
+			{0x00u, 0x01u},
+			{0x01u, 0x48u},
 			{0x04u, 0x31u},
-			{0x10u, 0xC0u},
-			{0x11u, 0x88u},
-			{0x18u, 0x08u},
-			{0x19u, 0x04u},
+			{0x10u, 0xC8u},
+			{0x11u, 0x48u},
+			{0x18u, 0x04u},
+			{0x19u, 0x08u},
 			{0x1Cu, 0x30u},
 			{0x20u, 0x10u},
-			{0x21u, 0x10u},
 			{0x24u, 0x44u},
-			{0x28u, 0x01u},
-			{0x30u, 0x10u},
-			{0x31u, 0x30u},
+			{0x28u, 0x03u},
+			{0x29u, 0x02u},
+			{0x31u, 0x20u},
 			{0x78u, 0x20u},
 			{0x7Cu, 0x40u},
-			{0x2Cu, 0x02u},
-			{0x89u, 0x0Fu},
-			{0x01u, 0x02u},
-			{0x03u, 0x01u},
-			{0x05u, 0x02u},
-			{0x07u, 0x01u},
+			{0x2Bu, 0x02u},
+			{0x8Au, 0x0Fu},
+			{0x01u, 0x50u},
+			{0x03u, 0xA0u},
+			{0x05u, 0x06u},
+			{0x06u, 0x02u},
+			{0x07u, 0x09u},
+			{0x09u, 0x05u},
 			{0x0Au, 0x04u},
-			{0x0Du, 0x04u},
-			{0x0Fu, 0x08u},
-			{0x12u, 0x08u},
-			{0x16u, 0x01u},
-			{0x17u, 0x08u},
-			{0x19u, 0x01u},
-			{0x1Bu, 0x02u},
-			{0x1Fu, 0x04u},
-			{0x21u, 0x02u},
+			{0x0Bu, 0x0Au},
+			{0x12u, 0x01u},
+			{0x15u, 0x60u},
+			{0x17u, 0x90u},
+			{0x1Bu, 0xFFu},
+			{0x1Cu, 0x04u},
+			{0x1Du, 0x30u},
+			{0x1Fu, 0xC0u},
+			{0x20u, 0x01u},
+			{0x21u, 0x03u},
 			{0x22u, 0x02u},
-			{0x23u, 0x21u},
-			{0x2Cu, 0x02u},
-			{0x2Du, 0x02u},
-			{0x2Eu, 0x04u},
-			{0x2Fu, 0x11u},
-			{0x30u, 0x01u},
-			{0x31u, 0x20u},
-			{0x33u, 0x10u},
-			{0x34u, 0x08u},
-			{0x35u, 0x03u},
-			{0x36u, 0x06u},
-			{0x37u, 0x0Cu},
-			{0x3Bu, 0x20u},
-			{0x3Eu, 0x40u},
-			{0x3Fu, 0x40u},
+			{0x23u, 0x0Cu},
+			{0x24u, 0x04u},
+			{0x27u, 0xFFu},
+			{0x29u, 0xFFu},
+			{0x2Au, 0x04u},
+			{0x2Cu, 0x04u},
+			{0x2Du, 0x0Fu},
+			{0x2Fu, 0xF0u},
+			{0x30u, 0x03u},
+			{0x33u, 0xFFu},
+			{0x36u, 0x04u},
+			{0x39u, 0x20u},
+			{0x3Eu, 0x41u},
+			{0x3Fu, 0x14u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
-			{0x5Cu, 0x99u},
 			{0x5Fu, 0x01u},
-			{0x80u, 0x33u},
-			{0x82u, 0xCCu},
-			{0x83u, 0x10u},
-			{0x87u, 0x10u},
-			{0x88u, 0x0Fu},
-			{0x89u, 0x19u},
-			{0x8Au, 0xF0u},
-			{0x8Bu, 0x02u},
-			{0x8Du, 0x14u},
-			{0x8Fu, 0x08u},
-			{0x90u, 0x96u},
-			{0x92u, 0x69u},
-			{0x93u, 0x08u},
-			{0x94u, 0x55u},
-			{0x96u, 0xAAu},
-			{0x98u, 0xFFu},
-			{0x9Eu, 0xFFu},
-			{0x9Fu, 0x07u},
-			{0xA2u, 0xFFu},
-			{0xA4u, 0xFFu},
-			{0xA9u, 0x1Au},
+			{0x81u, 0x0Fu},
+			{0x83u, 0xF0u},
+			{0x87u, 0xFFu},
+			{0x88u, 0x09u},
+			{0x89u, 0xFFu},
+			{0x8Au, 0x06u},
+			{0x8Cu, 0x03u},
+			{0x8Du, 0x90u},
+			{0x8Eu, 0x0Cu},
+			{0x8Fu, 0x60u},
+			{0x90u, 0x50u},
+			{0x91u, 0x03u},
+			{0x92u, 0xA0u},
+			{0x93u, 0x0Cu},
+			{0x94u, 0x90u},
+			{0x96u, 0x60u},
+			{0x98u, 0x05u},
+			{0x99u, 0x05u},
+			{0x9Au, 0x0Au},
+			{0x9Bu, 0x0Au},
+			{0x9Cu, 0x30u},
+			{0x9Du, 0x50u},
+			{0x9Eu, 0xC0u},
+			{0x9Fu, 0xA0u},
+			{0xA0u, 0x0Fu},
+			{0xA1u, 0x30u},
+			{0xA2u, 0xF0u},
+			{0xA3u, 0xC0u},
+			{0xA5u, 0xFFu},
+			{0xA6u, 0xFFu},
+			{0xA9u, 0x09u},
 			{0xAAu, 0xFFu},
-			{0xABu, 0x05u},
-			{0xB1u, 0x0Fu},
-			{0xB2u, 0xFFu},
-			{0xB7u, 0x10u},
-			{0xBAu, 0x08u},
-			{0xBFu, 0x40u},
+			{0xABu, 0x06u},
+			{0xAEu, 0xFFu},
+			{0xB1u, 0xFFu},
+			{0xB4u, 0xFFu},
+			{0xBEu, 0x10u},
+			{0xBFu, 0x01u},
 			{0xD6u, 0x08u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDBu, 0x04u},
-			{0xDCu, 0x11u},
 			{0xDDu, 0x90u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x20u},
-			{0x04u, 0x10u},
-			{0x06u, 0x40u},
-			{0x09u, 0x08u},
+			{0x03u, 0x18u},
+			{0x05u, 0x20u},
+			{0x06u, 0x06u},
+			{0x07u, 0x02u},
+			{0x09u, 0x80u},
 			{0x0Au, 0x80u},
-			{0x0Cu, 0x01u},
-			{0x0Du, 0x20u},
-			{0x0Eu, 0x21u},
-			{0x10u, 0x80u},
-			{0x11u, 0x40u},
-			{0x16u, 0xA4u},
-			{0x19u, 0x01u},
-			{0x1Au, 0x0Au},
-			{0x1Cu, 0x10u},
-			{0x1Fu, 0x04u},
-			{0x21u, 0x0Du},
+			{0x0Cu, 0x90u},
+			{0x0Du, 0x19u},
+			{0x0Eu, 0x02u},
+			{0x0Fu, 0x08u},
+			{0x10u, 0x24u},
+			{0x12u, 0x41u},
+			{0x15u, 0x04u},
+			{0x16u, 0x68u},
+			{0x17u, 0x40u},
+			{0x18u, 0x80u},
+			{0x19u, 0x40u},
+			{0x1Fu, 0x20u},
 			{0x22u, 0x10u},
-			{0x23u, 0x02u},
-			{0x26u, 0x80u},
-			{0x27u, 0x40u},
-			{0x29u, 0x41u},
-			{0x2Eu, 0x20u},
-			{0x30u, 0x08u},
-			{0x32u, 0x10u},
-			{0x33u, 0x40u},
-			{0x36u, 0x02u},
-			{0x37u, 0x40u},
-			{0x39u, 0x4Au},
-			{0x3Du, 0x21u},
-			{0x3Eu, 0x84u},
-			{0x3Fu, 0x02u},
-			{0x5Au, 0x61u},
-			{0x5Bu, 0x08u},
-			{0x5Fu, 0x80u},
-			{0x63u, 0x02u},
+			{0x23u, 0x10u},
+			{0x26u, 0x02u},
+			{0x2Au, 0x6Au},
+			{0x2Cu, 0x80u},
+			{0x2Du, 0x24u},
+			{0x30u, 0x80u},
+			{0x31u, 0x08u},
+			{0x32u, 0x20u},
+			{0x34u, 0x90u},
+			{0x37u, 0x02u},
+			{0x39u, 0x22u},
+			{0x3Au, 0x04u},
+			{0x3Cu, 0x10u},
+			{0x3Du, 0x81u},
+			{0x3Eu, 0x08u},
+			{0x58u, 0x04u},
+			{0x59u, 0x04u},
+			{0x5Au, 0x41u},
+			{0x5Bu, 0x20u},
+			{0x5Cu, 0x40u},
+			{0x61u, 0x40u},
 			{0x67u, 0x02u},
-			{0x6Cu, 0x04u},
-			{0x6Du, 0x04u},
-			{0x6Fu, 0x22u},
-			{0x80u, 0x02u},
-			{0x82u, 0x40u},
-			{0x83u, 0x01u},
-			{0x86u, 0x01u},
-			{0x87u, 0xA2u},
-			{0x89u, 0x80u},
-			{0x8Au, 0x40u},
-			{0x8Bu, 0x08u},
-			{0x8Cu, 0x44u},
-			{0xC0u, 0x52u},
-			{0xC2u, 0xFCu},
-			{0xC4u, 0x79u},
-			{0xCAu, 0x29u},
-			{0xCCu, 0x9Eu},
-			{0xCEu, 0xFBu},
+			{0x80u, 0x90u},
+			{0x82u, 0x20u},
+			{0x83u, 0x51u},
+			{0x85u, 0x01u},
+			{0x86u, 0x40u},
+			{0x8Au, 0x01u},
+			{0x8Bu, 0x04u},
+			{0x8Cu, 0x42u},
+			{0x8Eu, 0x70u},
+			{0x8Fu, 0x02u},
+			{0xC0u, 0xC6u},
+			{0xC2u, 0xF9u},
+			{0xC4u, 0xFFu},
+			{0xCAu, 0xEFu},
+			{0xCCu, 0xBEu},
+			{0xCEu, 0xF7u},
 			{0xD6u, 0x1Fu},
 			{0xD8u, 0x18u},
-			{0xE2u, 0x16u},
-			{0xE4u, 0x0Eu},
-			{0xE6u, 0x11u},
-			{0x01u, 0x04u},
-			{0x04u, 0x36u},
-			{0x06u, 0x49u},
+			{0xE2u, 0x4Cu},
+			{0xE4u, 0x04u},
+			{0xE6u, 0x01u},
+			{0x01u, 0x03u},
+			{0x02u, 0x01u},
+			{0x03u, 0x0Cu},
+			{0x09u, 0xFFu},
 			{0x0Au, 0x02u},
-			{0x0Bu, 0x01u},
-			{0x0Cu, 0x03u},
-			{0x0Eu, 0x0Cu},
-			{0x10u, 0x25u},
-			{0x12u, 0x5Au},
-			{0x14u, 0x10u},
-			{0x16u, 0x60u},
-			{0x17u, 0x02u},
-			{0x18u, 0x10u},
-			{0x1Bu, 0x08u},
-			{0x1Eu, 0x13u},
-			{0x20u, 0x27u},
-			{0x22u, 0x58u},
-			{0x24u, 0x01u},
-			{0x30u, 0x0Fu},
-			{0x31u, 0x04u},
-			{0x32u, 0x70u},
-			{0x33u, 0x01u},
-			{0x35u, 0x02u},
-			{0x37u, 0x08u},
-			{0x3Au, 0x0Au},
-			{0x56u, 0x08u},
-			{0x58u, 0x04u},
-			{0x59u, 0x04u},
-			{0x5Bu, 0x04u},
-			{0x5Cu, 0x91u},
-			{0x5Du, 0x90u},
-			{0x5Fu, 0x01u},
-			{0x81u, 0x03u},
-			{0x82u, 0x08u},
-			{0x83u, 0x0Cu},
-			{0x84u, 0x04u},
-			{0x86u, 0x03u},
-			{0x8Cu, 0x02u},
-			{0x8Du, 0x0Fu},
-			{0x8Eu, 0x04u},
-			{0x8Fu, 0xF0u},
-			{0x90u, 0x04u},
-			{0x91u, 0x30u},
-			{0x92u, 0x02u},
-			{0x93u, 0xC0u},
-			{0x95u, 0x50u},
-			{0x97u, 0xA0u},
-			{0x98u, 0x04u},
-			{0x99u, 0x60u},
-			{0x9Au, 0x02u},
-			{0x9Bu, 0x90u},
-			{0x9Du, 0x05u},
-			{0x9Eu, 0x10u},
-			{0x9Fu, 0x0Au},
-			{0xA1u, 0x06u},
-			{0xA3u, 0x09u},
-			{0xA8u, 0x04u},
-			{0xAAu, 0x02u},
-			{0xACu, 0x08u},
-			{0xAEu, 0x10u},
-			{0xB0u, 0x01u},
-			{0xB4u, 0x18u},
-			{0xB5u, 0xFFu},
-			{0xB6u, 0x06u},
-			{0xB9u, 0x08u},
-			{0xBAu, 0x80u},
-			{0xBEu, 0x10u},
-			{0xBFu, 0x14u},
-			{0xD8u, 0x04u},
-			{0xD9u, 0x04u},
-			{0xDBu, 0x04u},
-			{0xDCu, 0x09u},
-			{0xDFu, 0x01u},
-			{0x00u, 0x04u},
-			{0x01u, 0x80u},
-			{0x03u, 0x80u},
-			{0x04u, 0x40u},
-			{0x06u, 0x24u},
-			{0x0Au, 0x88u},
-			{0x0Bu, 0x01u},
-			{0x0Du, 0x20u},
-			{0x0Eu, 0x51u},
-			{0x10u, 0x04u},
-			{0x11u, 0x40u},
-			{0x15u, 0x04u},
-			{0x16u, 0x80u},
-			{0x19u, 0xA0u},
-			{0x1Au, 0x80u},
-			{0x1Cu, 0x40u},
-			{0x1Eu, 0x10u},
-			{0x1Fu, 0x08u},
-			{0x21u, 0x08u},
-			{0x23u, 0x04u},
-			{0x24u, 0x84u},
-			{0x27u, 0x22u},
-			{0x29u, 0x02u},
-			{0x30u, 0x08u},
-			{0x31u, 0x11u},
-			{0x33u, 0x40u},
-			{0x34u, 0x04u},
-			{0x37u, 0x20u},
-			{0x38u, 0x02u},
-			{0x39u, 0x40u},
-			{0x3Eu, 0x01u},
-			{0x3Fu, 0x10u},
-			{0x44u, 0x10u},
-			{0x45u, 0x04u},
-			{0x58u, 0x12u},
-			{0x5Au, 0x04u},
-			{0x5Bu, 0x80u},
-			{0x5Cu, 0x20u},
-			{0x5Eu, 0x80u},
-			{0x5Fu, 0x08u},
-			{0x62u, 0x80u},
-			{0x64u, 0x04u},
-			{0x65u, 0x40u},
-			{0x67u, 0x10u},
-			{0x69u, 0x40u},
-			{0x81u, 0x24u},
-			{0x82u, 0x80u},
-			{0x86u, 0x04u},
-			{0x89u, 0x10u},
-			{0x8Au, 0x02u},
-			{0x8Bu, 0x08u},
-			{0x8Cu, 0x40u},
-			{0x8Fu, 0x80u},
-			{0x91u, 0x04u},
-			{0x92u, 0x08u},
-			{0x93u, 0x08u},
-			{0x94u, 0x80u},
-			{0x95u, 0x40u},
-			{0x96u, 0x85u},
-			{0x98u, 0x22u},
-			{0x9Au, 0x20u},
-			{0x9Bu, 0x40u},
-			{0x9Du, 0xC0u},
-			{0x9Eu, 0xC0u},
-			{0xA1u, 0x20u},
-			{0xA2u, 0xC0u},
-			{0xA3u, 0x20u},
-			{0xA4u, 0xD8u},
-			{0xA6u, 0x12u},
-			{0xA8u, 0x20u},
-			{0xA9u, 0x10u},
-			{0xAAu, 0x04u},
-			{0xACu, 0x40u},
-			{0xAEu, 0x20u},
-			{0xAFu, 0x02u},
-			{0xB0u, 0x01u},
-			{0xB1u, 0x21u},
-			{0xC0u, 0xEDu},
-			{0xC2u, 0xFBu},
-			{0xC4u, 0x33u},
-			{0xCAu, 0x01u},
-			{0xCCu, 0x6Fu},
-			{0xCEu, 0xA9u},
-			{0xD6u, 0x7Fu},
-			{0xD8u, 0x78u},
-			{0xE2u, 0x47u},
-			{0xE4u, 0x01u},
-			{0xE6u, 0x90u},
-			{0xE8u, 0x02u},
-			{0xEAu, 0x09u},
-			{0xECu, 0x02u},
-			{0x01u, 0x06u},
-			{0x03u, 0x09u},
-			{0x05u, 0x30u},
-			{0x06u, 0xFFu},
-			{0x07u, 0xC0u},
-			{0x08u, 0x30u},
-			{0x09u, 0x50u},
-			{0x0Au, 0xC0u},
-			{0x0Bu, 0xA0u},
-			{0x0Cu, 0x09u},
-			{0x0Du, 0x0Fu},
-			{0x0Eu, 0x06u},
-			{0x0Fu, 0xF0u},
-			{0x10u, 0x0Fu},
-			{0x11u, 0x60u},
-			{0x12u, 0xF0u},
-			{0x13u, 0x90u},
-			{0x14u, 0xFFu},
-			{0x15u, 0xFFu},
-			{0x18u, 0xFFu},
-			{0x1Bu, 0xFFu},
-			{0x1Cu, 0x03u},
-			{0x1Du, 0x03u},
-			{0x1Eu, 0x0Cu},
-			{0x1Fu, 0x0Cu},
-			{0x20u, 0x05u},
-			{0x21u, 0x05u},
-			{0x22u, 0x0Au},
-			{0x23u, 0x0Au},
+			{0x0Du, 0x60u},
+			{0x0Fu, 0x90u},
+			{0x11u, 0x30u},
+			{0x12u, 0x04u},
+			{0x13u, 0xC0u},
+			{0x19u, 0x06u},
+			{0x1Au, 0x10u},
+			{0x1Bu, 0x09u},
+			{0x1Du, 0x50u},
+			{0x1Fu, 0xA0u},
+			{0x20u, 0x02u},
+			{0x21u, 0x0Fu},
+			{0x22u, 0x04u},
+			{0x23u, 0xF0u},
 			{0x27u, 0xFFu},
-			{0x28u, 0x50u},
-			{0x2Au, 0xA0u},
-			{0x2Cu, 0x90u},
-			{0x2Eu, 0x60u},
-			{0x32u, 0xFFu},
+			{0x29u, 0x05u},
+			{0x2Au, 0x08u},
+			{0x2Bu, 0x0Au},
+			{0x2Fu, 0xFFu},
+			{0x30u, 0x10u},
+			{0x32u, 0x06u},
 			{0x33u, 0xFFu},
+			{0x34u, 0x01u},
+			{0x36u, 0x08u},
 			{0x3Eu, 0x04u},
 			{0x3Fu, 0x04u},
 			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
+			{0x5Cu, 0x09u},
 			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x89u, 0x20u},
-			{0x8Bu, 0x4Fu},
-			{0x8Cu, 0x02u},
-			{0x8Du, 0x40u},
+			{0x80u, 0x50u},
+			{0x82u, 0xA0u},
+			{0x86u, 0x08u},
+			{0x89u, 0x0Fu},
+			{0x8Au, 0x07u},
+			{0x8Bu, 0xF0u},
+			{0x8Cu, 0x0Au},
+			{0x8Du, 0x69u},
 			{0x8Eu, 0x05u},
-			{0x8Fu, 0x1Fu},
-			{0x94u, 0x02u},
-			{0x95u, 0x03u},
-			{0x96u, 0x01u},
-			{0x97u, 0x0Cu},
-			{0x98u, 0x02u},
-			{0x99u, 0x05u},
-			{0x9Au, 0x01u},
-			{0x9Bu, 0x0Au},
-			{0x9Cu, 0x01u},
+			{0x8Fu, 0x96u},
+			{0x91u, 0xFFu},
+			{0x92u, 0x40u},
+			{0x95u, 0x33u},
+			{0x97u, 0xCCu},
+			{0x9Au, 0x80u},
+			{0x9Bu, 0xFFu},
+			{0x9Cu, 0x09u},
 			{0x9Eu, 0x02u},
-			{0x9Fu, 0x70u},
-			{0xA5u, 0x0Fu},
-			{0xA8u, 0x02u},
-			{0xA9u, 0x06u},
-			{0xAAu, 0x01u},
-			{0xABu, 0x09u},
-			{0xADu, 0x10u},
-			{0xAFu, 0x2Fu},
-			{0xB1u, 0x7Fu},
-			{0xB4u, 0x04u},
-			{0xB6u, 0x03u},
-			{0xBAu, 0x80u},
+			{0x9Fu, 0xFFu},
+			{0xA1u, 0xFFu},
+			{0xA2u, 0x10u},
+			{0xA4u, 0x04u},
+			{0xA6u, 0x08u},
+			{0xA9u, 0x55u},
+			{0xAAu, 0x20u},
+			{0xABu, 0xAAu},
+			{0xAFu, 0xFFu},
+			{0xB0u, 0x30u},
+			{0xB2u, 0x0Fu},
+			{0xB4u, 0xC0u},
+			{0xB5u, 0xFFu},
+			{0xBBu, 0x20u},
+			{0xBEu, 0x11u},
 			{0xD4u, 0x01u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDBu, 0x04u},
-			{0xDCu, 0x19u},
+			{0xDCu, 0x11u},
 			{0xDDu, 0x10u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x20u},
+			{0x01u, 0x09u},
 			{0x02u, 0x01u},
-			{0x03u, 0x20u},
-			{0x07u, 0x02u},
-			{0x08u, 0x50u},
-			{0x09u, 0x08u},
-			{0x0Bu, 0x84u},
-			{0x0Eu, 0x09u},
-			{0x0Fu, 0x10u},
-			{0x11u, 0x10u},
-			{0x12u, 0x82u},
+			{0x03u, 0x08u},
+			{0x04u, 0x20u},
+			{0x06u, 0x80u},
+			{0x09u, 0x82u},
+			{0x0Bu, 0x08u},
+			{0x0Du, 0x01u},
+			{0x0Eu, 0x04u},
+			{0x10u, 0x28u},
+			{0x11u, 0x02u},
+			{0x15u, 0x01u},
 			{0x17u, 0x20u},
-			{0x18u, 0x20u},
-			{0x1Eu, 0x09u},
-			{0x22u, 0x08u},
-			{0x24u, 0x40u},
-			{0x27u, 0x40u},
-			{0x28u, 0x10u},
-			{0x29u, 0x02u},
-			{0x2Fu, 0x26u},
-			{0x30u, 0xC0u},
-			{0x32u, 0x02u},
-			{0x33u, 0x25u},
-			{0x34u, 0x08u},
-			{0x35u, 0x20u},
-			{0x37u, 0x40u},
-			{0x39u, 0x5Au},
-			{0x3Au, 0x01u},
-			{0x3Bu, 0x80u},
-			{0x3Eu, 0xA0u},
-			{0x58u, 0x80u},
+			{0x18u, 0xA0u},
+			{0x1Bu, 0x1Cu},
+			{0x1Cu, 0x22u},
+			{0x1Du, 0x01u},
+			{0x1Eu, 0x04u},
+			{0x1Fu, 0x02u},
+			{0x21u, 0x10u},
+			{0x26u, 0x08u},
+			{0x28u, 0x02u},
+			{0x29u, 0x50u},
+			{0x2Au, 0x01u},
+			{0x2Cu, 0x02u},
+			{0x2Du, 0x01u},
+			{0x2Eu, 0x08u},
+			{0x2Fu, 0x08u},
+			{0x30u, 0x24u},
+			{0x32u, 0x01u},
+			{0x33u, 0x41u},
+			{0x34u, 0x80u},
+			{0x36u, 0x01u},
+			{0x37u, 0x10u},
+			{0x39u, 0xA0u},
+			{0x3Cu, 0x10u},
+			{0x3Du, 0x80u},
+			{0x3Eu, 0x02u},
+			{0x46u, 0x44u},
+			{0x47u, 0x11u},
+			{0x5Bu, 0x80u},
 			{0x5Cu, 0x40u},
-			{0x62u, 0x40u},
-			{0x68u, 0x50u},
-			{0x69u, 0x18u},
-			{0x6Au, 0x80u},
-			{0x6Bu, 0x01u},
-			{0x70u, 0x08u},
-			{0x71u, 0x11u},
-			{0x72u, 0x40u},
-			{0x73u, 0x01u},
-			{0x81u, 0x18u},
-			{0x82u, 0x40u},
-			{0x83u, 0x04u},
-			{0x86u, 0x0Au},
-			{0x8Cu, 0x90u},
-			{0x8Du, 0x40u},
-			{0x91u, 0x40u},
-			{0x93u, 0x1Cu},
-			{0x95u, 0x10u},
-			{0x96u, 0x01u},
-			{0x97u, 0x01u},
-			{0x9Au, 0xA0u},
-			{0x9Bu, 0x22u},
-			{0x9Du, 0x11u},
-			{0x9Eu, 0x40u},
-			{0xA3u, 0x22u},
-			{0xA4u, 0xD8u},
-			{0xA6u, 0x10u},
-			{0xA7u, 0x80u},
-			{0xA9u, 0x02u},
-			{0xAAu, 0x40u},
-			{0xABu, 0x02u},
-			{0xADu, 0x08u},
+			{0x5Du, 0x10u},
+			{0x66u, 0xA0u},
+			{0x80u, 0x40u},
+			{0x84u, 0x01u},
+			{0x87u, 0x20u},
+			{0x8Du, 0x54u},
+			{0x90u, 0x10u},
+			{0x91u, 0x03u},
+			{0x92u, 0x02u},
+			{0x93u, 0x18u},
+			{0x98u, 0x80u},
+			{0x9Au, 0x02u},
+			{0x9Du, 0x04u},
+			{0x9Eu, 0x0Du},
+			{0xA0u, 0x02u},
+			{0xA1u, 0x41u},
+			{0xA2u, 0x03u},
+			{0xA3u, 0x20u},
+			{0xA4u, 0x20u},
+			{0xA5u, 0x80u},
+			{0xA7u, 0x04u},
+			{0xA9u, 0x01u},
+			{0xACu, 0x80u},
+			{0xADu, 0x01u},
+			{0xAFu, 0x20u},
+			{0xB1u, 0x48u},
+			{0xB2u, 0x01u},
 			{0xB3u, 0x08u},
-			{0xB4u, 0x01u},
-			{0xB6u, 0x04u},
-			{0xC0u, 0x87u},
-			{0xC2u, 0xEFu},
-			{0xC4u, 0x4Bu},
-			{0xCAu, 0x73u},
-			{0xCCu, 0x7Fu},
-			{0xCEu, 0x3Fu},
-			{0xD6u, 0x18u},
-			{0xD8u, 0x08u},
-			{0xE0u, 0x0Eu},
-			{0xE2u, 0x01u},
-			{0xE4u, 0x04u},
-			{0xEAu, 0x0Cu},
-			{0xECu, 0x80u},
-			{0xEEu, 0x24u},
-			{0x86u, 0x10u},
-			{0x88u, 0x08u},
-			{0x91u, 0x50u},
-			{0x92u, 0x80u},
-			{0x93u, 0x04u},
-			{0x95u, 0x02u},
-			{0x9Cu, 0x08u},
-			{0xA0u, 0x10u},
-			{0xA4u, 0x80u},
-			{0xA6u, 0x10u},
-			{0xA7u, 0x80u},
-			{0xABu, 0x81u},
-			{0xACu, 0x40u},
-			{0xADu, 0x20u},
-			{0xAEu, 0x01u},
-			{0xB1u, 0x02u},
-			{0xB2u, 0x80u},
-			{0xE6u, 0x8Cu},
-			{0xE8u, 0x0Bu},
-			{0xECu, 0x04u},
+			{0xB4u, 0x40u},
+			{0xB6u, 0x40u},
+			{0xC0u, 0x5Fu},
+			{0xC2u, 0x5Bu},
+			{0xC4u, 0x5Eu},
+			{0xCAu, 0xFDu},
+			{0xCCu, 0xBFu},
+			{0xCEu, 0xBCu},
+			{0xD6u, 0x38u},
+			{0xD8u, 0x30u},
+			{0xE0u, 0x01u},
+			{0xE2u, 0x02u},
+			{0xE4u, 0x08u},
+			{0xE6u, 0x02u},
+			{0xE8u, 0x40u},
+			{0xEAu, 0x08u},
+			{0xECu, 0x40u},
 			{0xEEu, 0x03u},
-			{0x07u, 0x70u},
-			{0x08u, 0x32u},
-			{0x0Au, 0x01u},
-			{0x0Bu, 0x08u},
-			{0x0Fu, 0x07u},
-			{0x10u, 0x01u},
-			{0x12u, 0x1Au},
-			{0x14u, 0x06u},
-			{0x15u, 0x99u},
-			{0x17u, 0x22u},
-			{0x19u, 0xAAu},
-			{0x1Au, 0x08u},
-			{0x1Bu, 0x55u},
-			{0x27u, 0x80u},
-			{0x28u, 0x01u},
-			{0x2Au, 0x2Cu},
-			{0x2Du, 0x44u},
-			{0x2Fu, 0x88u},
-			{0x32u, 0x07u},
-			{0x33u, 0xF0u},
-			{0x34u, 0x38u},
-			{0x37u, 0x0Fu},
-			{0x38u, 0x08u},
+			{0x00u, 0x02u},
+			{0x02u, 0x04u},
+			{0x05u, 0x06u},
+			{0x07u, 0x09u},
+			{0x09u, 0x05u},
+			{0x0Bu, 0x0Au},
+			{0x13u, 0x70u},
+			{0x18u, 0x04u},
+			{0x19u, 0x40u},
+			{0x1Au, 0x02u},
+			{0x1Bu, 0x1Fu},
+			{0x1Cu, 0x04u},
+			{0x1Du, 0x10u},
+			{0x1Eu, 0x0Au},
+			{0x1Fu, 0x2Fu},
+			{0x21u, 0x20u},
+			{0x23u, 0x4Fu},
+			{0x24u, 0x04u},
+			{0x25u, 0x0Fu},
+			{0x26u, 0x03u},
+			{0x29u, 0x03u},
+			{0x2Bu, 0x0Cu},
+			{0x2Cu, 0x04u},
+			{0x2Eu, 0x02u},
+			{0x30u, 0x06u},
+			{0x31u, 0x7Fu},
+			{0x34u, 0x08u},
+			{0x36u, 0x01u},
+			{0x3Au, 0x02u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
-			{0x5Cu, 0x10u},
+			{0x5Bu, 0x04u},
+			{0x5Cu, 0x19u},
 			{0x5Fu, 0x01u},
-			{0x01u, 0x10u},
-			{0x03u, 0x21u},
-			{0x05u, 0x20u},
-			{0x0Au, 0x45u},
-			{0x0Eu, 0x58u},
-			{0x10u, 0x20u},
-			{0x11u, 0x01u},
-			{0x13u, 0x50u},
-			{0x16u, 0x08u},
-			{0x1Au, 0x05u},
-			{0x1Bu, 0x40u},
-			{0x1Eu, 0x18u},
-			{0x20u, 0x02u},
-			{0x22u, 0x40u},
-			{0x25u, 0x44u},
-			{0x28u, 0x02u},
-			{0x2Bu, 0x94u},
-			{0x2Du, 0x04u},
-			{0x2Eu, 0x80u},
-			{0x30u, 0x04u},
-			{0x32u, 0x60u},
-			{0x36u, 0x28u},
-			{0x37u, 0x20u},
-			{0x38u, 0x60u},
-			{0x3Au, 0x80u},
-			{0x3Cu, 0x20u},
-			{0x3Du, 0xC8u},
-			{0x3Fu, 0x04u},
-			{0x42u, 0x48u},
-			{0x43u, 0x08u},
-			{0x48u, 0x80u},
-			{0x49u, 0xA5u},
-			{0x4Bu, 0x12u},
-			{0x50u, 0x08u},
-			{0x51u, 0x08u},
-			{0x52u, 0x10u},
-			{0x53u, 0x40u},
-			{0x58u, 0x50u},
-			{0x5Au, 0x10u},
-			{0x62u, 0x80u},
-			{0x82u, 0x04u},
-			{0x86u, 0x80u},
-			{0x88u, 0x01u},
-			{0x90u, 0x62u},
-			{0x91u, 0x04u},
-			{0x95u, 0x40u},
-			{0x96u, 0x40u},
-			{0x98u, 0x46u},
-			{0x9Au, 0x21u},
-			{0x9Bu, 0x04u},
-			{0x9Cu, 0x90u},
-			{0x9Du, 0x20u},
-			{0x9Eu, 0x08u},
-			{0xA0u, 0x10u},
-			{0xA1u, 0x02u},
-			{0xA2u, 0x28u},
-			{0xA3u, 0x94u},
-			{0xA4u, 0xC0u},
-			{0xA5u, 0x80u},
-			{0xA6u, 0x91u},
-			{0xA8u, 0x01u},
-			{0xABu, 0x01u},
-			{0xACu, 0x04u},
-			{0xADu, 0x01u},
-			{0xAEu, 0x05u},
-			{0xAFu, 0x04u},
-			{0xB0u, 0x44u},
-			{0xB2u, 0x11u},
-			{0xB3u, 0x20u},
-			{0xB5u, 0x08u},
-			{0xC0u, 0x47u},
-			{0xC2u, 0x7Bu},
-			{0xC4u, 0x4Fu},
-			{0xCAu, 0x5Fu},
-			{0xCCu, 0x6Eu},
-			{0xCEu, 0x7Cu},
-			{0xD0u, 0x07u},
-			{0xD2u, 0x0Cu},
-			{0xD6u, 0x08u},
-			{0xD8u, 0x08u},
-			{0xE2u, 0x80u},
-			{0xE6u, 0x80u},
-			{0xEAu, 0x80u},
-			{0xECu, 0x08u},
-			{0xEEu, 0x01u},
-			{0x00u, 0xFFu},
-			{0x03u, 0x04u},
-			{0x04u, 0x33u},
-			{0x06u, 0xCCu},
-			{0x0Au, 0xFFu},
-			{0x0Bu, 0x10u},
-			{0x0Eu, 0xFFu},
-			{0x0Fu, 0x02u},
-			{0x10u, 0x69u},
-			{0x12u, 0x96u},
-			{0x14u, 0x55u},
-			{0x16u, 0xAAu},
-			{0x18u, 0xFFu},
-			{0x19u, 0x0Au},
-			{0x1Bu, 0x14u},
-			{0x1Cu, 0x0Fu},
-			{0x1Eu, 0xF0u},
-			{0x1Fu, 0x08u},
-			{0x22u, 0xFFu},
-			{0x29u, 0x01u},
-			{0x33u, 0x18u},
-			{0x35u, 0x06u},
-			{0x36u, 0xFFu},
-			{0x37u, 0x01u},
-			{0x3Au, 0x80u},
-			{0x3Fu, 0x54u},
-			{0x56u, 0x08u},
-			{0x58u, 0x04u},
-			{0x59u, 0x04u},
-			{0x5Bu, 0x04u},
-			{0x5Cu, 0x01u},
-			{0x5Du, 0x90u},
-			{0x5Fu, 0x01u},
-			{0x80u, 0x10u},
-			{0x81u, 0x10u},
-			{0x83u, 0x20u},
-			{0x85u, 0x20u},
-			{0x87u, 0x10u},
-			{0x88u, 0x09u},
+			{0x82u, 0x10u},
+			{0x85u, 0x04u},
+			{0x87u, 0x02u},
 			{0x89u, 0x08u},
-			{0x8Au, 0x02u},
-			{0x8Bu, 0x04u},
 			{0x8Cu, 0x04u},
-			{0x8Eu, 0x08u},
-			{0x8Fu, 0x80u},
-			{0x96u, 0x07u},
-			{0x97u, 0x40u},
-			{0x98u, 0x0Au},
-			{0x9Au, 0x05u},
-			{0x9Cu, 0x10u},
-			{0x9Du, 0x02u},
-			{0xA3u, 0x01u},
-			{0xA4u, 0x10u},
-			{0xA5u, 0x4Cu},
-			{0xA7u, 0xB0u},
-			{0xA8u, 0x10u},
+			{0x8Du, 0x04u},
+			{0x8Eu, 0x02u},
+			{0x8Fu, 0x02u},
+			{0x91u, 0x08u},
+			{0x94u, 0x02u},
+			{0x95u, 0x08u},
+			{0x96u, 0x04u},
+			{0x98u, 0x04u},
+			{0x99u, 0x02u},
+			{0x9Au, 0x02u},
+			{0x9Bu, 0x04u},
+			{0x9Fu, 0x10u},
+			{0xA0u, 0x04u},
+			{0xA1u, 0x04u},
+			{0xA2u, 0x0Au},
+			{0xA3u, 0x02u},
+			{0xA4u, 0x04u},
+			{0xA5u, 0x08u},
+			{0xA6u, 0x03u},
+			{0xABu, 0x01u},
 			{0xADu, 0x04u},
-			{0xAEu, 0x08u},
-			{0xAFu, 0x08u},
-			{0xB1u, 0x3Cu},
-			{0xB2u, 0x0Fu},
-			{0xB3u, 0x02u},
-			{0xB5u, 0x01u},
+			{0xAFu, 0x02u},
+			{0xB0u, 0x08u},
+			{0xB1u, 0x08u},
+			{0xB2u, 0x06u},
+			{0xB3u, 0x06u},
+			{0xB4u, 0x01u},
+			{0xB5u, 0x10u},
 			{0xB6u, 0x10u},
-			{0xB7u, 0xC0u},
-			{0xB8u, 0x80u},
-			{0xBEu, 0x40u},
-			{0xBFu, 0x45u},
+			{0xB7u, 0x01u},
+			{0xB9u, 0x02u},
+			{0xBAu, 0x08u},
+			{0xBBu, 0x08u},
+			{0xBFu, 0x01u},
+			{0xD6u, 0x08u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
-			{0xDCu, 0x01u},
+			{0xDBu, 0x04u},
+			{0xDCu, 0x99u},
+			{0xDDu, 0x90u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x44u},
-			{0x02u, 0x08u},
-			{0x03u, 0x80u},
-			{0x04u, 0x60u},
+			{0x01u, 0x02u},
+			{0x04u, 0x40u},
 			{0x05u, 0x01u},
-			{0x09u, 0x20u},
-			{0x0Au, 0x02u},
-			{0x0Bu, 0x90u},
-			{0x0Du, 0x20u},
-			{0x0Eu, 0x12u},
-			{0x11u, 0x01u},
-			{0x17u, 0x68u},
-			{0x1Au, 0x02u},
-			{0x1Eu, 0x11u},
-			{0x20u, 0x08u},
-			{0x22u, 0x04u},
-			{0x23u, 0x01u},
-			{0x24u, 0x08u},
-			{0x25u, 0x0Au},
-			{0x26u, 0x40u},
-			{0x28u, 0x08u},
-			{0x2Cu, 0x80u},
-			{0x2Fu, 0x21u},
-			{0x31u, 0x8Cu},
-			{0x33u, 0x20u},
-			{0x36u, 0x84u},
-			{0x39u, 0x60u},
-			{0x3Au, 0x02u},
-			{0x3Cu, 0x01u},
-			{0x3Eu, 0x10u},
-			{0x3Fu, 0x84u},
-			{0x58u, 0x80u},
-			{0x59u, 0x08u},
-			{0x5Au, 0x20u},
-			{0x60u, 0x0Eu},
-			{0x63u, 0x20u},
-			{0x79u, 0x08u},
-			{0x7Au, 0x10u},
-			{0x81u, 0x02u},
+			{0x0Au, 0x09u},
+			{0x0Eu, 0x28u},
+			{0x10u, 0x01u},
+			{0x12u, 0x20u},
+			{0x16u, 0x20u},
+			{0x17u, 0x02u},
+			{0x19u, 0x02u},
+			{0x1Au, 0x09u},
+			{0x1Cu, 0x40u},
+			{0x1Eu, 0x28u},
+			{0x1Fu, 0x40u},
+			{0x21u, 0x02u},
+			{0x23u, 0x80u},
+			{0x26u, 0x21u},
+			{0x27u, 0x22u},
+			{0x2Au, 0x09u},
+			{0x2Bu, 0x08u},
+			{0x2Du, 0x10u},
+			{0x2Fu, 0x62u},
+			{0x30u, 0x20u},
+			{0x31u, 0x82u},
+			{0x35u, 0x80u},
+			{0x36u, 0x0Au},
+			{0x37u, 0x20u},
+			{0x38u, 0x04u},
+			{0x39u, 0x20u},
+			{0x3Eu, 0x84u},
+			{0x3Fu, 0x10u},
+			{0x58u, 0x0Au},
+			{0x59u, 0x40u},
+			{0x5Bu, 0x20u},
+			{0x5Fu, 0x40u},
+			{0x62u, 0x40u},
+			{0x64u, 0x01u},
+			{0x65u, 0x80u},
+			{0x79u, 0x10u},
+			{0x7Au, 0x04u},
+			{0x82u, 0x01u},
+			{0x87u, 0x40u},
+			{0x89u, 0x08u},
+			{0x90u, 0x04u},
+			{0x91u, 0x20u},
+			{0x92u, 0x04u},
+			{0x93u, 0x10u},
+			{0x98u, 0x02u},
+			{0x99u, 0x01u},
+			{0x9Au, 0xE8u},
+			{0x9Du, 0x08u},
+			{0x9Eu, 0x05u},
+			{0x9Fu, 0xC0u},
+			{0xA0u, 0x30u},
+			{0xA2u, 0x0Au},
+			{0xA3u, 0x22u},
+			{0xA5u, 0x80u},
+			{0xA8u, 0x44u},
+			{0xACu, 0x24u},
+			{0xADu, 0x10u},
+			{0xB0u, 0x08u},
+			{0xB1u, 0x40u},
+			{0xB2u, 0x08u},
+			{0xB5u, 0x02u},
+			{0xB7u, 0x10u},
+			{0xC0u, 0x98u},
+			{0xC2u, 0x63u},
+			{0xC4u, 0x35u},
+			{0xCAu, 0xF7u},
+			{0xCCu, 0xFDu},
+			{0xCEu, 0x76u},
+			{0xD6u, 0x1Fu},
+			{0xD8u, 0x18u},
+			{0xE2u, 0x48u},
+			{0xE4u, 0x01u},
+			{0xE6u, 0x20u},
+			{0xEAu, 0x2Fu},
+			{0xEEu, 0x0Cu},
+			{0x8Fu, 0x08u},
+			{0x9Eu, 0x04u},
+			{0xA7u, 0x08u},
+			{0xAAu, 0x01u},
+			{0xACu, 0x10u},
+			{0xADu, 0x40u},
+			{0xAEu, 0x10u},
+			{0xB4u, 0x08u},
+			{0xB5u, 0x82u},
+			{0xB7u, 0x40u},
+			{0xE2u, 0x04u},
+			{0xE6u, 0x04u},
+			{0xE8u, 0x08u},
+			{0xEAu, 0x84u},
+			{0xEEu, 0x40u},
+			{0x04u, 0x02u},
+			{0x05u, 0xFFu},
+			{0x06u, 0x0Du},
+			{0x0Au, 0x10u},
+			{0x0Bu, 0xFFu},
+			{0x0Cu, 0x0Du},
+			{0x10u, 0x0Du},
+			{0x13u, 0xFFu},
+			{0x14u, 0x0Du},
+			{0x17u, 0xFFu},
+			{0x18u, 0x0Du},
+			{0x19u, 0xFFu},
+			{0x1Du, 0x0Fu},
+			{0x1Fu, 0xF0u},
+			{0x20u, 0x0Du},
+			{0x21u, 0x33u},
+			{0x23u, 0xCCu},
+			{0x24u, 0xE2u},
+			{0x25u, 0x55u},
+			{0x26u, 0x08u},
+			{0x27u, 0xAAu},
+			{0x28u, 0x82u},
+			{0x29u, 0x69u},
+			{0x2Au, 0x54u},
+			{0x2Bu, 0x96u},
+			{0x2Cu, 0x81u},
+			{0x2Eu, 0x32u},
+			{0x31u, 0xFFu},
+			{0x32u, 0x0Fu},
+			{0x34u, 0x70u},
+			{0x36u, 0x80u},
+			{0x3Au, 0x08u},
+			{0x3Bu, 0x02u},
+			{0x3Eu, 0x40u},
+			{0x58u, 0x04u},
+			{0x59u, 0x04u},
+			{0x5Cu, 0x10u},
+			{0x5Fu, 0x01u},
+			{0x80u, 0x09u},
 			{0x82u, 0x02u},
-			{0x83u, 0x40u},
-			{0x85u, 0x10u},
-			{0x87u, 0x08u},
+			{0x83u, 0x12u},
+			{0x85u, 0x20u},
+			{0x88u, 0x3Eu},
+			{0x89u, 0x04u},
+			{0x8Bu, 0x03u},
+			{0x8Fu, 0x0Cu},
+			{0x94u, 0x22u},
+			{0x95u, 0x08u},
+			{0x96u, 0x01u},
+			{0x97u, 0x03u},
+			{0x9Bu, 0x01u},
+			{0x9Du, 0x01u},
+			{0x9Fu, 0x02u},
+			{0xA1u, 0x40u},
+			{0xA2u, 0x38u},
+			{0xA3u, 0x80u},
+			{0xA4u, 0x01u},
+			{0xA6u, 0x14u},
+			{0xABu, 0x40u},
+			{0xAFu, 0x80u},
+			{0xB0u, 0x38u},
+			{0xB1u, 0xC0u},
+			{0xB3u, 0x20u},
+			{0xB4u, 0x07u},
+			{0xB5u, 0x10u},
+			{0xB7u, 0x0Fu},
+			{0xB8u, 0x20u},
+			{0xBEu, 0x01u},
+			{0xBFu, 0x05u},
+			{0xD6u, 0x08u},
+			{0xD8u, 0x04u},
+			{0xD9u, 0x04u},
+			{0xDBu, 0x04u},
+			{0xDDu, 0x90u},
+			{0xDFu, 0x01u},
+			{0x01u, 0x20u},
+			{0x03u, 0x40u},
+			{0x04u, 0x80u},
+			{0x05u, 0x14u},
+			{0x09u, 0x08u},
+			{0x0Cu, 0x2Au},
+			{0x11u, 0x08u},
+			{0x12u, 0x80u},
+			{0x15u, 0x29u},
+			{0x17u, 0x40u},
+			{0x19u, 0x20u},
+			{0x1Au, 0x80u},
+			{0x1Du, 0x54u},
+			{0x21u, 0x60u},
+			{0x22u, 0x81u},
+			{0x23u, 0x20u},
+			{0x25u, 0x01u},
+			{0x27u, 0x80u},
+			{0x29u, 0x01u},
+			{0x2Au, 0x80u},
+			{0x2Bu, 0x08u},
+			{0x2Cu, 0x84u},
+			{0x2Du, 0x04u},
+			{0x31u, 0x28u},
+			{0x33u, 0x40u},
+			{0x36u, 0x08u},
+			{0x37u, 0x91u},
+			{0x39u, 0xA4u},
+			{0x3Au, 0x01u},
+			{0x3Bu, 0x04u},
+			{0x3Cu, 0x08u},
+			{0x3Du, 0x20u},
+			{0x5Au, 0x60u},
+			{0x5Bu, 0x08u},
+			{0x60u, 0x22u},
+			{0x63u, 0x04u},
+			{0x81u, 0x10u},
 			{0x8Du, 0x01u},
-			{0x8Fu, 0x20u},
-			{0x90u, 0x62u},
+			{0x90u, 0x02u},
+			{0x92u, 0x49u},
+			{0x95u, 0x40u},
+			{0x97u, 0x20u},
+			{0x98u, 0x04u},
+			{0x99u, 0x01u},
+			{0x9Au, 0x8Au},
+			{0x9Bu, 0x15u},
+			{0x9Cu, 0x22u},
+			{0x9Fu, 0x20u},
+			{0xA0u, 0x84u},
+			{0xA1u, 0x10u},
+			{0xA2u, 0x08u},
+			{0xA7u, 0x10u},
+			{0xABu, 0x10u},
+			{0xB4u, 0x14u},
+			{0xC0u, 0xEAu},
+			{0xC2u, 0x74u},
+			{0xC4u, 0xFCu},
+			{0xCAu, 0xEDu},
+			{0xCCu, 0xFEu},
+			{0xCEu, 0x6Fu},
+			{0xD6u, 0x0Eu},
+			{0xD8u, 0x0Eu},
+			{0xE2u, 0x14u},
+			{0xE8u, 0x08u},
+			{0xEAu, 0x90u},
+			{0xEEu, 0x40u},
+			{0x25u, 0x01u},
+			{0x2Du, 0x02u},
+			{0x31u, 0x02u},
+			{0x33u, 0x01u},
+			{0x3Fu, 0x05u},
+			{0x59u, 0x04u},
+			{0x5Fu, 0x01u},
+			{0x85u, 0x08u},
+			{0x87u, 0x03u},
+			{0x89u, 0x37u},
+			{0x8Bu, 0x40u},
+			{0x93u, 0x2Cu},
+			{0x94u, 0x08u},
+			{0x97u, 0x7Fu},
+			{0x98u, 0x02u},
+			{0x99u, 0x4Fu},
+			{0x9Bu, 0x30u},
+			{0x9Cu, 0x04u},
+			{0xA1u, 0x02u},
+			{0xA5u, 0x10u},
+			{0xA7u, 0x01u},
+			{0xA8u, 0x01u},
+			{0xA9u, 0x03u},
+			{0xADu, 0x80u},
+			{0xB0u, 0x04u},
+			{0xB1u, 0x80u},
+			{0xB2u, 0x01u},
+			{0xB3u, 0x0Fu},
+			{0xB4u, 0x08u},
+			{0xB5u, 0x70u},
+			{0xB6u, 0x02u},
+			{0xBEu, 0x55u},
+			{0xBFu, 0x01u},
+			{0xC0u, 0x42u},
+			{0xC1u, 0x06u},
+			{0xC2u, 0x50u},
+			{0xC5u, 0xDEu},
+			{0xC6u, 0xF0u},
+			{0xC7u, 0x2Cu},
+			{0xC8u, 0x3Bu},
+			{0xC9u, 0xFFu},
+			{0xCAu, 0xFFu},
+			{0xCBu, 0xFFu},
+			{0xCFu, 0x2Cu},
+			{0xD6u, 0x01u},
+			{0xD8u, 0x04u},
+			{0xD9u, 0x04u},
+			{0xDAu, 0x04u},
+			{0xDBu, 0x04u},
+			{0xDCu, 0x10u},
+			{0xDDu, 0x01u},
+			{0xDFu, 0x01u},
+			{0xE2u, 0xC0u},
+			{0xE6u, 0x80u},
+			{0xE8u, 0x40u},
+			{0xE9u, 0x40u},
+			{0xEEu, 0x08u},
+			{0x0Cu, 0x84u},
+			{0x0Fu, 0x0Au},
+			{0x16u, 0x04u},
+			{0x1Du, 0x40u},
+			{0x1Eu, 0x88u},
+			{0x1Fu, 0x04u},
+			{0x23u, 0x50u},
+			{0x24u, 0x08u},
+			{0x25u, 0x14u},
+			{0x26u, 0x01u},
+			{0x27u, 0x14u},
+			{0x28u, 0x32u},
+			{0x2Du, 0xA6u},
+			{0x2Fu, 0x08u},
+			{0x30u, 0x02u},
+			{0x31u, 0x01u},
+			{0x36u, 0x08u},
+			{0x37u, 0x11u},
+			{0x3Cu, 0x08u},
+			{0x3Du, 0x20u},
+			{0x47u, 0x11u},
+			{0x4Cu, 0x14u},
+			{0x4Du, 0x03u},
+			{0x4Eu, 0x02u},
+			{0x55u, 0x01u},
+			{0x56u, 0x10u},
+			{0x57u, 0x08u},
+			{0x5Eu, 0x8Au},
+			{0x5Fu, 0x20u},
+			{0x65u, 0x40u},
+			{0x67u, 0x58u},
+			{0x6Cu, 0x21u},
+			{0x6Du, 0x10u},
+			{0x6Eu, 0x01u},
+			{0x74u, 0x08u},
+			{0x76u, 0x4Au},
+			{0x89u, 0x10u},
+			{0x8Au, 0x10u},
 			{0x91u, 0x04u},
-			{0x92u, 0x20u},
-			{0x93u, 0x90u},
+			{0x92u, 0x48u},
 			{0x94u, 0x08u},
-			{0x95u, 0x49u},
-			{0x96u, 0x50u},
-			{0x97u, 0x01u},
-			{0x98u, 0x40u},
-			{0x9Au, 0x21u},
-			{0x9Bu, 0x44u},
+			{0x95u, 0x41u},
+			{0x97u, 0x20u},
+			{0x98u, 0x04u},
+			{0x99u, 0x80u},
+			{0x9Au, 0x84u},
+			{0x9Bu, 0x01u},
 			{0x9Cu, 0x12u},
-			{0x9Du, 0x24u},
-			{0x9Eu, 0x08u},
-			{0xA0u, 0x10u},
-			{0xA1u, 0x20u},
-			{0xA2u, 0x2Cu},
-			{0xA3u, 0x84u},
-			{0xA4u, 0x80u},
-			{0xA6u, 0x40u},
-			{0xA7u, 0x30u},
-			{0xA9u, 0x44u},
-			{0xACu, 0x40u},
-			{0xAEu, 0x40u},
-			{0xB4u, 0x20u},
-			{0xB6u, 0x04u},
-			{0xC0u, 0xDFu},
-			{0xC2u, 0xEFu},
-			{0xC4u, 0xE8u},
-			{0xCAu, 0xD4u},
-			{0xCCu, 0x5Cu},
-			{0xCEu, 0xFDu},
-			{0xD6u, 0x0Eu},
-			{0xD8u, 0x0Eu},
-			{0xE0u, 0x40u},
-			{0xE2u, 0x10u},
-			{0xE4u, 0x40u},
-			{0xE8u, 0x02u},
-			{0xEAu, 0x48u},
-			{0xECu, 0x02u},
-			{0xEEu, 0x30u},
-			{0x03u, 0x7Eu},
-			{0x05u, 0x80u},
-			{0x06u, 0x01u},
-			{0x08u, 0x88u},
-			{0x0Au, 0x03u},
-			{0x10u, 0x21u},
-			{0x11u, 0x02u},
-			{0x12u, 0x02u},
-			{0x13u, 0x28u},
-			{0x14u, 0x10u},
-			{0x15u, 0x32u},
-			{0x17u, 0x44u},
-			{0x19u, 0x4Cu},
-			{0x1Au, 0xECu},
-			{0x1Bu, 0x32u},
-			{0x1Eu, 0x02u},
-			{0x24u, 0xE0u},
-			{0x27u, 0x04u},
-			{0x28u, 0x04u},
-			{0x29u, 0x10u},
-			{0x2Au, 0x43u},
-			{0x2Du, 0x01u},
-			{0x30u, 0x10u},
-			{0x31u, 0x0Eu},
-			{0x33u, 0x70u},
-			{0x34u, 0x0Fu},
-			{0x35u, 0x80u},
-			{0x36u, 0xE0u},
-			{0x37u, 0x01u},
-			{0x3Eu, 0x41u},
-			{0x3Fu, 0x50u},
-			{0x40u, 0x52u},
-			{0x41u, 0x03u},
-			{0x42u, 0x40u},
-			{0x45u, 0xE2u},
-			{0x46u, 0xDCu},
-			{0x47u, 0xF0u},
-			{0x48u, 0x2Fu},
-			{0x49u, 0xFFu},
-			{0x4Au, 0xFFu},
-			{0x4Bu, 0xFFu},
-			{0x4Fu, 0x2Cu},
-			{0x56u, 0x01u},
+			{0x9Du, 0x20u},
+			{0x9Eu, 0x40u},
+			{0x9Fu, 0x10u},
+			{0xA0u, 0x06u},
+			{0xA2u, 0x0Au},
+			{0xA3u, 0x05u},
+			{0xA4u, 0x28u},
+			{0xA5u, 0x15u},
+			{0xA7u, 0x10u},
+			{0xA8u, 0x10u},
+			{0xAAu, 0x40u},
+			{0xABu, 0x20u},
+			{0xADu, 0x80u},
+			{0xAFu, 0x01u},
+			{0xB1u, 0x04u},
+			{0xB2u, 0x14u},
+			{0xB6u, 0x50u},
+			{0xC2u, 0xE0u},
+			{0xC4u, 0x40u},
+			{0xCAu, 0xFAu},
+			{0xCCu, 0xE0u},
+			{0xCEu, 0x60u},
+			{0xD0u, 0xA0u},
+			{0xD2u, 0x30u},
+			{0xD6u, 0xF0u},
+			{0xD8u, 0xF0u},
+			{0xE2u, 0xC8u},
+			{0xE4u, 0x01u},
+			{0xE6u, 0x20u},
+			{0xE8u, 0x10u},
+			{0xEAu, 0xA0u},
+			{0xEEu, 0x3Du},
+			{0x03u, 0x22u},
+			{0x05u, 0x66u},
+			{0x07u, 0x19u},
+			{0x08u, 0x60u},
+			{0x09u, 0x15u},
+			{0x0Au, 0x90u},
+			{0x0Bu, 0x2Au},
+			{0x10u, 0x0Fu},
+			{0x11u, 0x17u},
+			{0x12u, 0xF0u},
+			{0x13u, 0x48u},
+			{0x14u, 0x03u},
+			{0x16u, 0x0Cu},
+			{0x17u, 0x73u},
+			{0x19u, 0x03u},
+			{0x1Bu, 0x0Cu},
+			{0x1Cu, 0x05u},
+			{0x1Eu, 0x0Au},
+			{0x24u, 0x50u},
+			{0x25u, 0x01u},
+			{0x26u, 0xA0u},
+			{0x28u, 0x30u},
+			{0x2Au, 0xC0u},
+			{0x2Cu, 0x06u},
+			{0x2Eu, 0x09u},
+			{0x30u, 0xFFu},
+			{0x33u, 0x0Fu},
+			{0x35u, 0x70u},
+			{0x37u, 0x70u},
+			{0x3Bu, 0x08u},
+			{0x3Eu, 0x01u},
+			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
-			{0x5Au, 0x04u},
 			{0x5Bu, 0x04u},
 			{0x5Cu, 0x10u},
-			{0x5Du, 0x01u},
+			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x62u, 0xC0u},
-			{0x66u, 0x80u},
-			{0x68u, 0x40u},
-			{0x69u, 0x40u},
-			{0x6Eu, 0x08u},
-			{0x80u, 0x02u},
-			{0x90u, 0x01u},
-			{0xA5u, 0x01u},
-			{0xB4u, 0x02u},
+			{0x80u, 0x33u},
+			{0x82u, 0xCCu},
+			{0x83u, 0x40u},
+			{0x84u, 0xFFu},
+			{0x87u, 0x04u},
+			{0x88u, 0x0Fu},
+			{0x89u, 0x10u},
+			{0x8Au, 0xF0u},
+			{0x8Bu, 0x08u},
+			{0x8Fu, 0x02u},
+			{0x90u, 0x96u},
+			{0x91u, 0x22u},
+			{0x92u, 0x69u},
+			{0x93u, 0x44u},
+			{0x94u, 0xFFu},
+			{0x95u, 0x08u},
+			{0x97u, 0x10u},
+			{0x99u, 0x10u},
+			{0x9Au, 0xFFu},
+			{0x9Bu, 0x08u},
+			{0xA1u, 0x10u},
+			{0xA3u, 0x08u},
+			{0xA4u, 0x55u},
+			{0xA6u, 0xAAu},
+			{0xA7u, 0x20u},
+			{0xAAu, 0xFFu},
+			{0xADu, 0x10u},
+			{0xAEu, 0xFFu},
+			{0xAFu, 0x09u},
+			{0xB1u, 0x60u},
+			{0xB2u, 0xFFu},
+			{0xB3u, 0x18u},
 			{0xB5u, 0x01u},
-			{0xB6u, 0x01u},
-			{0xBEu, 0x50u},
-			{0xBFu, 0x10u},
+			{0xB7u, 0x06u},
+			{0xBAu, 0x08u},
+			{0xBBu, 0x08u},
+			{0xBFu, 0x41u},
+			{0xD6u, 0x08u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
+			{0xDBu, 0x04u},
+			{0xDCu, 0x91u},
+			{0xDDu, 0x90u},
 			{0xDFu, 0x01u},
+			{0x00u, 0x18u},
 			{0x02u, 0x80u},
-			{0x04u, 0x08u},
-			{0x05u, 0x20u},
+			{0x06u, 0x08u},
 			{0x08u, 0x02u},
-			{0x0Cu, 0x80u},
-			{0x0Eu, 0x44u},
-			{0x0Fu, 0x10u},
-			{0x14u, 0x10u},
-			{0x16u, 0x08u},
-			{0x19u, 0x90u},
-			{0x1Eu, 0x05u},
-			{0x1Fu, 0x01u},
+			{0x09u, 0x04u},
+			{0x0Au, 0x08u},
+			{0x0Cu, 0x02u},
+			{0x0Eu, 0x12u},
+			{0x10u, 0x10u},
+			{0x11u, 0xA0u},
+			{0x14u, 0x08u},
+			{0x15u, 0x40u},
+			{0x16u, 0x10u},
+			{0x18u, 0x30u},
+			{0x1Du, 0x01u},
+			{0x20u, 0x82u},
+			{0x22u, 0x1Cu},
 			{0x23u, 0x04u},
-			{0x24u, 0x60u},
-			{0x25u, 0x8Cu},
-			{0x26u, 0x1Au},
+			{0x25u, 0x60u},
+			{0x27u, 0x21u},
+			{0x29u, 0x48u},
+			{0x2Au, 0x02u},
 			{0x2Bu, 0x10u},
-			{0x2Cu, 0x20u},
-			{0x2Eu, 0xA0u},
-			{0x2Fu, 0x04u},
-			{0x36u, 0x2Au},
-			{0x3Du, 0x01u},
-			{0x3Fu, 0x08u},
-			{0x41u, 0x80u},
-			{0x42u, 0x02u},
-			{0x44u, 0x80u},
-			{0x45u, 0x28u},
-			{0x4Cu, 0x60u},
-			{0x4Eu, 0x02u},
-			{0x55u, 0x50u},
-			{0x57u, 0x02u},
-			{0x5Du, 0x80u},
+			{0x2Du, 0x04u},
+			{0x30u, 0x02u},
+			{0x32u, 0x14u},
+			{0x36u, 0x08u},
+			{0x37u, 0x21u},
+			{0x39u, 0x50u},
+			{0x3Au, 0x09u},
+			{0x3Du, 0x2Au},
+			{0x59u, 0x10u},
+			{0x5Au, 0x80u},
 			{0x5Eu, 0x20u},
-			{0x5Fu, 0x05u},
-			{0x65u, 0x14u},
-			{0x66u, 0x02u},
-			{0x67u, 0x02u},
-			{0x6Cu, 0x01u},
+			{0x5Fu, 0x48u},
+			{0x63u, 0x0Au},
+			{0x64u, 0x04u},
+			{0x65u, 0x80u},
+			{0x66u, 0x04u},
 			{0x6Du, 0x04u},
-			{0x6Fu, 0x44u},
-			{0x74u, 0x1Au},
-			{0x76u, 0x01u},
-			{0x7Eu, 0x80u},
-			{0x7Fu, 0x40u},
-			{0x82u, 0x02u},
-			{0x83u, 0x02u},
-			{0x84u, 0x40u},
-			{0x85u, 0x40u},
-			{0x86u, 0x01u},
-			{0x88u, 0x88u},
-			{0x89u, 0x40u},
-			{0x8Au, 0x01u},
-			{0x8Cu, 0x40u},
-			{0x8Eu, 0x10u},
-			{0x93u, 0x18u},
-			{0x95u, 0x09u},
-			{0x96u, 0x12u},
-			{0x9Au, 0x80u},
-			{0x9Du, 0x40u},
-			{0xA0u, 0x40u},
-			{0xA1u, 0x20u},
-			{0xA2u, 0xA4u},
-			{0xA3u, 0x84u},
-			{0xA4u, 0x02u},
-			{0xA5u, 0x5Cu},
-			{0xA6u, 0x02u},
-			{0xA7u, 0x20u},
-			{0xA9u, 0x08u},
-			{0xACu, 0x01u},
-			{0xADu, 0x20u},
-			{0xB0u, 0x80u},
+			{0x6Fu, 0x0Au},
+			{0x81u, 0x10u},
+			{0x85u, 0x10u},
+			{0x87u, 0x0Cu},
+			{0x88u, 0x41u},
+			{0x8Du, 0x20u},
+			{0x8Eu, 0x04u},
+			{0x8Fu, 0x0Cu},
+			{0x92u, 0x10u},
+			{0x93u, 0x40u},
+			{0x94u, 0x08u},
+			{0x95u, 0x01u},
+			{0x97u, 0x20u},
+			{0x98u, 0x08u},
+			{0x99u, 0x40u},
+			{0x9Au, 0x9Bu},
+			{0x9Du, 0x09u},
+			{0x9Eu, 0x40u},
+			{0x9Fu, 0x10u},
+			{0xA0u, 0x06u},
+			{0xA2u, 0x93u},
+			{0xA4u, 0x28u},
+			{0xA5u, 0x60u},
+			{0xA6u, 0x08u},
+			{0xA7u, 0x02u},
+			{0xAAu, 0x01u},
+			{0xAFu, 0x0Au},
+			{0xB0u, 0x04u},
 			{0xB2u, 0x80u},
-			{0xB3u, 0x40u},
+			{0xB3u, 0x01u},
 			{0xB5u, 0x80u},
-			{0xC0u, 0x68u},
-			{0xC2u, 0xF8u},
-			{0xC4u, 0x60u},
-			{0xCAu, 0x72u},
-			{0xCCu, 0xE0u},
-			{0xCEu, 0xC0u},
-			{0xD0u, 0xE0u},
-			{0xD2u, 0x10u},
-			{0xD6u, 0xF0u},
-			{0xD8u, 0xF0u},
-			{0xE0u, 0xA0u},
-			{0xE4u, 0x01u},
-			{0xE6u, 0xBAu},
-			{0xECu, 0x02u},
-			{0xEEu, 0xA0u},
-			{0x01u, 0x10u},
-			{0x03u, 0x09u},
-			{0x04u, 0x02u},
-			{0x06u, 0x04u},
-			{0x07u, 0x02u},
-			{0x0Au, 0x08u},
-			{0x15u, 0x10u},
-			{0x16u, 0x02u},
-			{0x17u, 0x08u},
-			{0x19u, 0x08u},
-			{0x1Au, 0x01u},
-			{0x1Bu, 0x10u},
-			{0x1Fu, 0x04u},
-			{0x21u, 0x10u},
-			{0x23u, 0x08u},
+			{0xC0u, 0x4Eu},
+			{0xC2u, 0xBEu},
+			{0xC4u, 0xE7u},
+			{0xCAu, 0x4Bu},
+			{0xCCu, 0xE7u},
+			{0xCEu, 0xEFu},
+			{0xD6u, 0x7Cu},
+			{0xD8u, 0x7Cu},
+			{0xE0u, 0x01u},
+			{0xE2u, 0x50u},
+			{0xE6u, 0x14u},
+			{0xEAu, 0x20u},
+			{0xEEu, 0x20u},
+			{0x02u, 0x01u},
+			{0x04u, 0x10u},
+			{0x05u, 0x02u},
+			{0x06u, 0x20u},
+			{0x07u, 0x09u},
+			{0x09u, 0x02u},
+			{0x0Bu, 0x01u},
+			{0x0Cu, 0x40u},
+			{0x0Eu, 0x80u},
+			{0x14u, 0x20u},
+			{0x16u, 0x12u},
+			{0x19u, 0x01u},
+			{0x1Bu, 0x02u},
+			{0x1Du, 0x02u},
+			{0x1Fu, 0x01u},
+			{0x20u, 0x80u},
+			{0x22u, 0x44u},
 			{0x25u, 0x02u},
-			{0x27u, 0x04u},
-			{0x29u, 0x10u},
-			{0x2Bu, 0x08u},
-			{0x2Eu, 0x04u},
+			{0x27u, 0x05u},
+			{0x2Au, 0x08u},
+			{0x2Cu, 0x32u},
+			{0x2Eu, 0xC4u},
 			{0x30u, 0x06u},
-			{0x31u, 0x06u},
-			{0x33u, 0x01u},
-			{0x34u, 0x01u},
-			{0x35u, 0x18u},
-			{0x36u, 0x08u},
+			{0x32u, 0x08u},
+			{0x33u, 0x08u},
+			{0x34u, 0xF0u},
+			{0x35u, 0x03u},
+			{0x36u, 0x01u},
+			{0x37u, 0x04u},
 			{0x3Bu, 0x20u},
-			{0x3Eu, 0x01u},
-			{0x3Fu, 0x01u},
+			{0x3Eu, 0x11u},
 			{0x56u, 0x08u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
@@ -1377,629 +1404,604 @@ void cyfitter_cfg(void)
 			{0x5Cu, 0x99u},
 			{0x5Du, 0x90u},
 			{0x5Fu, 0x01u},
-			{0x80u, 0x08u},
-			{0x82u, 0x04u},
-			{0x83u, 0x0Fu},
-			{0x85u, 0x97u},
-			{0x87u, 0x20u},
-			{0x89u, 0x02u},
-			{0x8Du, 0x03u},
-			{0x91u, 0x40u},
-			{0x93u, 0x8Cu},
-			{0x94u, 0x08u},
-			{0x96u, 0x05u},
-			{0x97u, 0x70u},
-			{0x98u, 0x08u},
-			{0x99u, 0xAFu},
-			{0x9Au, 0x14u},
-			{0x9Bu, 0x50u},
-			{0x9Cu, 0x04u},
-			{0x9Eu, 0x08u},
-			{0xA1u, 0x08u},
-			{0xA3u, 0x03u},
-			{0xABu, 0x01u},
-			{0xACu, 0x08u},
-			{0xAEu, 0x06u},
-			{0xAFu, 0x80u},
-			{0xB0u, 0x10u},
-			{0xB2u, 0x02u},
-			{0xB3u, 0xF0u},
-			{0xB4u, 0x01u},
-			{0xB5u, 0x0Fu},
-			{0xB6u, 0x0Cu},
-			{0xBAu, 0x80u},
-			{0xD6u, 0x08u},
+			{0x82u, 0x80u},
+			{0x83u, 0x38u},
+			{0x84u, 0x99u},
+			{0x85u, 0x01u},
+			{0x86u, 0x22u},
+			{0x89u, 0x4Au},
+			{0x8Au, 0x70u},
+			{0x8Bu, 0x15u},
+			{0x8Du, 0x22u},
+			{0x8Fu, 0x45u},
+			{0x91u, 0x01u},
+			{0x93u, 0x06u},
+			{0x96u, 0x08u},
+			{0x97u, 0x01u},
+			{0x98u, 0x44u},
+			{0x99u, 0x53u},
+			{0x9Au, 0x88u},
+			{0x9Bu, 0x2Cu},
+			{0x9Eu, 0x07u},
+			{0xA7u, 0x40u},
+			{0xA8u, 0xAAu},
+			{0xAAu, 0x55u},
+			{0xB1u, 0x07u},
+			{0xB2u, 0xF0u},
+			{0xB6u, 0x0Fu},
+			{0xB7u, 0x78u},
+			{0xBBu, 0x02u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDBu, 0x04u},
-			{0xDCu, 0x19u},
-			{0xDDu, 0x90u},
+			{0xDCu, 0x11u},
 			{0xDFu, 0x01u},
-			{0x01u, 0x20u},
-			{0x03u, 0x20u},
-			{0x05u, 0x01u},
-			{0x0Au, 0x18u},
-			{0x0Eu, 0x26u},
-			{0x10u, 0x01u},
-			{0x16u, 0x02u},
-			{0x19u, 0x22u},
-			{0x1Bu, 0x40u},
-			{0x1Du, 0x01u},
-			{0x1Eu, 0x26u},
-			{0x1Fu, 0xC0u},
-			{0x20u, 0x80u},
-			{0x22u, 0x14u},
-			{0x23u, 0x08u},
-			{0x25u, 0x20u},
-			{0x26u, 0x2Cu},
-			{0x29u, 0x20u},
-			{0x2Bu, 0x60u},
-			{0x2Cu, 0x02u},
-			{0x2Fu, 0x84u},
-			{0x31u, 0x40u},
-			{0x32u, 0x14u},
-			{0x36u, 0x2Au},
-			{0x39u, 0x08u},
-			{0x3Au, 0x01u},
-			{0x3Du, 0xA9u},
-			{0x3Fu, 0x20u},
-			{0x58u, 0x84u},
-			{0x59u, 0x10u},
-			{0x5Au, 0x02u},
-			{0x5Du, 0x80u},
-			{0x62u, 0x81u},
-			{0x63u, 0x18u},
-			{0x66u, 0x80u},
+			{0x01u, 0x08u},
+			{0x02u, 0x01u},
+			{0x03u, 0x80u},
+			{0x04u, 0x18u},
+			{0x06u, 0x60u},
+			{0x0Bu, 0x20u},
+			{0x0Cu, 0x08u},
+			{0x0Du, 0x20u},
+			{0x0Eu, 0x02u},
+			{0x10u, 0x82u},
+			{0x13u, 0x10u},
+			{0x17u, 0x10u},
+			{0x18u, 0x80u},
+			{0x19u, 0x64u},
+			{0x1Cu, 0x10u},
+			{0x1Eu, 0x12u},
+			{0x20u, 0x08u},
+			{0x22u, 0x50u},
+			{0x23u, 0x10u},
+			{0x24u, 0x01u},
+			{0x25u, 0x80u},
+			{0x26u, 0x02u},
+			{0x29u, 0x04u},
+			{0x2Cu, 0x20u},
+			{0x32u, 0x50u},
+			{0x36u, 0x0Au},
+			{0x37u, 0x10u},
+			{0x3Bu, 0x14u},
+			{0x3Cu, 0x09u},
+			{0x3Du, 0x80u},
+			{0x3Eu, 0x20u},
+			{0x59u, 0x90u},
+			{0x62u, 0x80u},
+			{0x63u, 0x04u},
+			{0x68u, 0x02u},
+			{0x6Cu, 0x90u},
+			{0x6Fu, 0x09u},
+			{0x75u, 0x02u},
+			{0x76u, 0x19u},
+			{0x80u, 0x50u},
+			{0x81u, 0x20u},
 			{0x82u, 0x02u},
-			{0x83u, 0x18u},
-			{0x87u, 0x04u},
-			{0x88u, 0x04u},
-			{0x89u, 0x02u},
-			{0x8Du, 0x10u},
-			{0xC0u, 0x16u},
-			{0xC2u, 0xE6u},
-			{0xC4u, 0x81u},
-			{0xCAu, 0xB7u},
-			{0xCCu, 0xEEu},
-			{0xCEu, 0xF3u},
-			{0xD6u, 0x1Fu},
-			{0xD8u, 0x1Fu},
-			{0xE2u, 0x22u},
-			{0xE4u, 0x02u},
-			{0x81u, 0x40u},
-			{0x82u, 0x40u},
-			{0x89u, 0x10u},
-			{0x8Bu, 0x04u},
-			{0x91u, 0x50u},
-			{0x92u, 0x80u},
-			{0x93u, 0x04u},
-			{0xABu, 0x80u},
-			{0xADu, 0x01u},
-			{0xE2u, 0x04u},
-			{0xE4u, 0x05u},
-			{0xE6u, 0x40u},
-			{0xEEu, 0x06u},
-			{0x88u, 0x10u},
-			{0x91u, 0x50u},
-			{0x92u, 0x80u},
-			{0x93u, 0x04u},
-			{0x95u, 0x02u},
-			{0xA0u, 0x10u},
-			{0xA7u, 0x80u},
-			{0xA8u, 0x80u},
-			{0xE8u, 0x10u},
-			{0xEAu, 0x04u},
-			{0x01u, 0x41u},
-			{0x05u, 0x41u},
-			{0x08u, 0x99u},
-			{0x09u, 0x40u},
-			{0x0Au, 0x22u},
+			{0x83u, 0x80u},
+			{0x84u, 0x02u},
+			{0x86u, 0x10u},
+			{0x88u, 0x08u},
+			{0x89u, 0x03u},
+			{0x8Bu, 0x40u},
+			{0x8Du, 0x91u},
+			{0xC0u, 0x7Du},
+			{0xC2u, 0xE4u},
+			{0xC4u, 0x4Bu},
+			{0xCAu, 0x42u},
+			{0xCCu, 0xECu},
+			{0xCEu, 0xF6u},
+			{0xD6u, 0x0Cu},
+			{0xD8u, 0x0Cu},
+			{0xE0u, 0x01u},
+			{0xE2u, 0x90u},
+			{0xE4u, 0x10u},
+			{0xE6u, 0xC8u},
+			{0xAAu, 0x04u},
+			{0xE0u, 0x08u},
+			{0xE6u, 0x02u},
+			{0xEAu, 0x01u},
+			{0xEEu, 0x02u},
+			{0x9Eu, 0x04u},
+			{0xE2u, 0x08u},
+			{0xEEu, 0x01u},
+			{0x02u, 0x08u},
+			{0x03u, 0x08u},
+			{0x07u, 0x80u},
+			{0x0Bu, 0x07u},
 			{0x0Cu, 0x44u},
-			{0x0Du, 0x47u},
 			{0x0Eu, 0x88u},
-			{0x0Fu, 0x98u},
-			{0x11u, 0x01u},
-			{0x13u, 0x40u},
-			{0x16u, 0x70u},
-			{0x19u, 0xE2u},
-			{0x1Au, 0x07u},
-			{0x1Bu, 0x08u},
-			{0x1Du, 0x81u},
-			{0x1Fu, 0x40u},
-			{0x21u, 0x41u},
-			{0x25u, 0x88u},
-			{0x26u, 0x80u},
-			{0x27u, 0x61u},
+			{0x0Fu, 0x70u},
+			{0x11u, 0x44u},
+			{0x13u, 0x88u},
+			{0x15u, 0x99u},
+			{0x16u, 0x07u},
+			{0x17u, 0x22u},
+			{0x19u, 0xAAu},
+			{0x1Au, 0x70u},
+			{0x1Bu, 0x55u},
+			{0x1Eu, 0x80u},
+			{0x24u, 0x99u},
+			{0x26u, 0x22u},
 			{0x28u, 0xAAu},
-			{0x29u, 0x04u},
 			{0x2Au, 0x55u},
-			{0x2Du, 0x10u},
-			{0x2Eu, 0x08u},
-			{0x31u, 0xC0u},
-			{0x32u, 0xF0u},
-			{0x34u, 0x0Fu},
-			{0x37u, 0x3Fu},
-			{0x39u, 0x80u},
-			{0x3Bu, 0x02u},
-			{0x3Fu, 0x40u},
+			{0x32u, 0x0Fu},
+			{0x34u, 0xF0u},
+			{0x35u, 0x0Fu},
+			{0x37u, 0xF0u},
+			{0x40u, 0x36u},
+			{0x41u, 0x01u},
+			{0x42u, 0x50u},
+			{0x44u, 0x04u},
+			{0x45u, 0x0Eu},
+			{0x46u, 0xFCu},
+			{0x47u, 0xBDu},
+			{0x48u, 0x3Du},
+			{0x49u, 0xFFu},
+			{0x4Au, 0xFFu},
+			{0x4Bu, 0xFFu},
+			{0x4Cu, 0x22u},
+			{0x4Eu, 0xF0u},
+			{0x4Fu, 0x08u},
+			{0x50u, 0x04u},
+			{0x54u, 0x09u},
+			{0x56u, 0x04u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
-			{0x5Cu, 0x01u},
+			{0x5Au, 0x04u},
+			{0x5Bu, 0x04u},
+			{0x5Cu, 0x11u},
 			{0x5Fu, 0x01u},
-			{0x80u, 0x07u},
-			{0x81u, 0xC0u},
-			{0x82u, 0x10u},
-			{0x83u, 0x02u},
-			{0x84u, 0x03u},
-			{0x85u, 0xC0u},
-			{0x86u, 0x70u},
-			{0x87u, 0x04u},
-			{0x88u, 0x80u},
-			{0x89u, 0xC0u},
-			{0x8Au, 0x64u},
-			{0x8Bu, 0x08u},
-			{0x8Cu, 0x64u},
-			{0x8Du, 0xC0u},
-			{0x8Eu, 0x80u},
-			{0x8Fu, 0x01u},
-			{0x90u, 0x24u},
-			{0x91u, 0x90u},
-			{0x93u, 0x40u},
-			{0x96u, 0x75u},
-			{0x98u, 0xA4u},
-			{0x9Au, 0x40u},
-			{0x9Bu, 0x60u},
-			{0x9Cu, 0xE4u},
+			{0x62u, 0xC0u},
+			{0x64u, 0x40u},
+			{0x65u, 0x01u},
+			{0x66u, 0x10u},
+			{0x67u, 0x11u},
+			{0x68u, 0xC0u},
+			{0x69u, 0x01u},
+			{0x6Bu, 0x11u},
+			{0x6Cu, 0x40u},
+			{0x6Du, 0x01u},
+			{0x6Eu, 0x40u},
+			{0x6Fu, 0x01u},
+			{0x81u, 0x0Cu},
+			{0x85u, 0xB8u},
+			{0x87u, 0x45u},
+			{0x89u, 0x73u},
+			{0x8Bu, 0x88u},
+			{0x8Du, 0x0Cu},
+			{0x91u, 0x04u},
+			{0x93u, 0x08u},
+			{0x95u, 0x08u},
+			{0x97u, 0x04u},
+			{0x98u, 0x01u},
+			{0x99u, 0x14u},
+			{0x9Bu, 0x08u},
 			{0x9Du, 0x80u},
-			{0xA0u, 0xE4u},
-			{0xA3u, 0x9Fu},
-			{0xA4u, 0x08u},
-			{0xA7u, 0xFFu},
-			{0xA8u, 0x40u},
-			{0xA9u, 0x7Fu},
-			{0xAAu, 0x02u},
-			{0xABu, 0x80u},
-			{0xACu, 0x08u},
-			{0xADu, 0x1Fu},
-			{0xAFu, 0x20u},
-			{0xB0u, 0x71u},
-			{0xB2u, 0x08u},
-			{0xB4u, 0x07u},
-			{0xB5u, 0xFFu},
-			{0xB6u, 0x80u},
-			{0xB8u, 0x08u},
-			{0xBAu, 0x30u},
-			{0xBEu, 0x40u},
-			{0xBFu, 0x10u},
-			{0xD6u, 0x02u},
-			{0xD7u, 0x2Cu},
+			{0x9Fu, 0x60u},
+			{0xA3u, 0x02u},
+			{0xA9u, 0x0Cu},
+			{0xADu, 0x2Fu},
+			{0xAFu, 0xD0u},
+			{0xB3u, 0x07u},
+			{0xB5u, 0x18u},
+			{0xB6u, 0x01u},
+			{0xB7u, 0xE0u},
+			{0xBBu, 0xACu},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
-			{0xDBu, 0x04u},
+			{0xDCu, 0x09u},
 			{0xDFu, 0x01u},
-			{0x01u, 0x12u},
-			{0x03u, 0x21u},
-			{0x04u, 0x60u},
-			{0x08u, 0x04u},
-			{0x09u, 0x01u},
-			{0x0Au, 0x05u},
-			{0x0Eu, 0x28u},
-			{0x10u, 0x08u},
-			{0x11u, 0x81u},
-			{0x13u, 0x08u},
-			{0x16u, 0x01u},
-			{0x17u, 0x24u},
-			{0x18u, 0x04u},
-			{0x19u, 0xA2u},
-			{0x1Au, 0x62u},
-			{0x1Bu, 0x0Au},
-			{0x1Eu, 0x28u},
-			{0x23u, 0x08u},
-			{0x25u, 0x41u},
-			{0x27u, 0x40u},
-			{0x28u, 0x04u},
-			{0x29u, 0x21u},
-			{0x2Bu, 0x22u},
-			{0x2Eu, 0x09u},
-			{0x2Fu, 0x29u},
-			{0x32u, 0x10u},
-			{0x33u, 0x41u},
-			{0x35u, 0x20u},
-			{0x37u, 0x41u},
-			{0x38u, 0x80u},
-			{0x39u, 0x15u},
-			{0x3Bu, 0x40u},
-			{0x3Du, 0x15u},
-			{0x3Eu, 0x40u},
-			{0x63u, 0x80u},
-			{0x68u, 0x20u},
-			{0x69u, 0x55u},
-			{0x6Au, 0x04u},
-			{0x6Bu, 0x01u},
-			{0x70u, 0x40u},
-			{0x72u, 0x01u},
-			{0x8Au, 0x40u},
-			{0x90u, 0x62u},
-			{0x93u, 0x86u},
-			{0x95u, 0x11u},
-			{0x96u, 0x40u},
-			{0x97u, 0x40u},
-			{0x99u, 0x05u},
-			{0x9Au, 0x31u},
-			{0x9Bu, 0x24u},
-			{0x9Cu, 0x80u},
-			{0x9Du, 0xA0u},
-			{0x9Eu, 0x08u},
-			{0x9Fu, 0x01u},
-			{0xA0u, 0x08u},
-			{0xA1u, 0x0Au},
-			{0xA2u, 0x20u},
-			{0xA3u, 0x40u},
-			{0xA4u, 0x60u},
-			{0xA5u, 0x80u},
-			{0xA6u, 0x11u},
-			{0xA7u, 0x20u},
-			{0xA9u, 0x04u},
-			{0xB7u, 0x08u},
-			{0xC0u, 0xCFu},
-			{0xC2u, 0x6Fu},
-			{0xC4u, 0xEFu},
-			{0xCAu, 0xFFu},
-			{0xCCu, 0xBDu},
+			{0x04u, 0x02u},
+			{0x07u, 0x01u},
+			{0x0Au, 0x08u},
+			{0x0Eu, 0x19u},
+			{0x17u, 0x14u},
+			{0x1Au, 0x02u},
+			{0x1Eu, 0x18u},
+			{0x1Fu, 0x18u},
+			{0x20u, 0x04u},
+			{0x21u, 0x0Cu},
+			{0x22u, 0x90u},
+			{0x23u, 0x10u},
+			{0x25u, 0x50u},
+			{0x28u, 0x01u},
+			{0x29u, 0x10u},
+			{0x2Bu, 0x40u},
+			{0x30u, 0x0Au},
+			{0x32u, 0x90u},
+			{0x37u, 0x15u},
+			{0x38u, 0x80u},
+			{0x39u, 0x29u},
+			{0x3Du, 0xE0u},
+			{0x3Eu, 0x0Au},
+			{0x3Fu, 0x20u},
+			{0x44u, 0x01u},
+			{0x45u, 0x04u},
+			{0x46u, 0x40u},
+			{0x47u, 0x40u},
+			{0x4Du, 0x84u},
+			{0x4Fu, 0x10u},
+			{0x56u, 0x25u},
+			{0x57u, 0xC0u},
+			{0x5Du, 0x04u},
+			{0x5Eu, 0x62u},
+			{0x65u, 0x40u},
+			{0x67u, 0x80u},
+			{0x87u, 0x40u},
+			{0x90u, 0x02u},
+			{0x92u, 0x09u},
+			{0x94u, 0x80u},
+			{0x95u, 0x69u},
+			{0x97u, 0x20u},
+			{0x99u, 0x40u},
+			{0x9Au, 0x0Au},
+			{0x9Bu, 0x15u},
+			{0x9Eu, 0x01u},
+			{0x9Fu, 0x40u},
+			{0xA4u, 0x2Au},
+			{0xA5u, 0x0Cu},
+			{0xA7u, 0x18u},
+			{0xAAu, 0x50u},
+			{0xABu, 0x08u},
+			{0xB2u, 0x01u},
+			{0xC0u, 0x90u},
+			{0xC2u, 0xE2u},
+			{0xC4u, 0x60u},
+			{0xCAu, 0x0Du},
+			{0xCCu, 0xEFu},
 			{0xCEu, 0xFFu},
-			{0xD8u, 0x01u},
-			{0xE4u, 0x80u},
-			{0xE8u, 0x10u},
-			{0x00u, 0x16u},
-			{0x03u, 0x08u},
-			{0x04u, 0x01u},
-			{0x06u, 0x0Eu},
-			{0x08u, 0x10u},
-			{0x09u, 0x09u},
-			{0x0Au, 0x06u},
-			{0x0Bu, 0x02u},
-			{0x0Cu, 0x07u},
-			{0x0Du, 0x04u},
-			{0x0Eu, 0x08u},
-			{0x0Fu, 0x08u},
-			{0x12u, 0x10u},
-			{0x14u, 0x04u},
-			{0x18u, 0x09u},
-			{0x19u, 0x0Au},
-			{0x1Au, 0x06u},
-			{0x1Bu, 0x05u},
-			{0x1Cu, 0x16u},
-			{0x1Fu, 0x07u},
-			{0x20u, 0x02u},
-			{0x24u, 0x12u},
-			{0x26u, 0x04u},
-			{0x2Cu, 0x06u},
-			{0x2Eu, 0x10u},
-			{0x30u, 0x08u},
-			{0x32u, 0x10u},
-			{0x34u, 0x0Fu},
-			{0x36u, 0x01u},
-			{0x37u, 0x0Fu},
-			{0x38u, 0x20u},
-			{0x3Eu, 0x45u},
-			{0x54u, 0x09u},
-			{0x56u, 0x04u},
+			{0xD0u, 0xD0u},
+			{0xD2u, 0x30u},
+			{0xD6u, 0xF0u},
+			{0xD8u, 0x90u},
+			{0xEAu, 0x04u},
+			{0xEEu, 0x04u},
+			{0x00u, 0x01u},
+			{0x01u, 0xC0u},
+			{0x03u, 0x02u},
+			{0x05u, 0x80u},
+			{0x0Bu, 0xFFu},
+			{0x0Du, 0xC0u},
+			{0x0Fu, 0x01u},
+			{0x11u, 0x90u},
+			{0x13u, 0x40u},
+			{0x15u, 0xC0u},
+			{0x17u, 0x08u},
+			{0x18u, 0x01u},
+			{0x19u, 0xC0u},
+			{0x1Bu, 0x04u},
+			{0x1Du, 0x1Fu},
+			{0x1Fu, 0x20u},
+			{0x23u, 0x9Fu},
+			{0x25u, 0x7Fu},
+			{0x27u, 0x80u},
+			{0x2Fu, 0x60u},
+			{0x30u, 0x01u},
+			{0x37u, 0xFFu},
+			{0x38u, 0x02u},
+			{0x3Fu, 0x40u},
+			{0x56u, 0x02u},
+			{0x57u, 0x20u},
 			{0x58u, 0x04u},
 			{0x59u, 0x04u},
 			{0x5Bu, 0x04u},
-			{0x5Cu, 0x10u},
 			{0x5Fu, 0x01u},
-			{0x80u, 0x90u},
-			{0x82u, 0x60u},
-			{0x85u, 0xFFu},
-			{0x86u, 0xFFu},
-			{0x88u, 0x0Fu},
-			{0x8Au, 0xF0u},
-			{0x8Cu, 0x50u},
-			{0x8Eu, 0xA0u},
-			{0x8Fu, 0xFFu},
-			{0x91u, 0x06u},
-			{0x92u, 0xFFu},
-			{0x93u, 0x09u},
-			{0x94u, 0x05u},
-			{0x95u, 0x0Fu},
-			{0x96u, 0x0Au},
-			{0x97u, 0xF0u},
-			{0x98u, 0x03u},
-			{0x99u, 0x05u},
-			{0x9Au, 0x0Cu},
-			{0x9Bu, 0x0Au},
-			{0x9Du, 0x30u},
-			{0x9Fu, 0xC0u},
-			{0xA0u, 0x30u},
-			{0xA1u, 0x50u},
-			{0xA2u, 0xC0u},
-			{0xA3u, 0xA0u},
-			{0xA5u, 0x03u},
-			{0xA6u, 0xFFu},
-			{0xA7u, 0x0Cu},
-			{0xABu, 0xFFu},
-			{0xACu, 0x09u},
-			{0xADu, 0x60u},
-			{0xAEu, 0x06u},
-			{0xAFu, 0x90u},
-			{0xB0u, 0xFFu},
-			{0xB1u, 0xFFu},
-			{0xBEu, 0x01u},
-			{0xBFu, 0x01u},
+			{0x80u, 0x07u},
+			{0x81u, 0x6Cu},
+			{0x82u, 0x18u},
+			{0x84u, 0x01u},
+			{0x85u, 0x24u},
+			{0x89u, 0x91u},
+			{0x8Au, 0x80u},
+			{0x8Bu, 0x6Eu},
+			{0x8Cu, 0xC1u},
+			{0x8Du, 0x48u},
+			{0x90u, 0x01u},
+			{0x92u, 0xC0u},
+			{0x94u, 0xC0u},
+			{0x98u, 0x08u},
+			{0x99u, 0x24u},
+			{0x9Au, 0x21u},
+			{0x9Bu, 0x48u},
+			{0x9Cu, 0x04u},
+			{0x9Du, 0x71u},
+			{0x9Fu, 0x82u},
+			{0xA0u, 0xC1u},
+			{0xA1u, 0x6Cu},
+			{0xA4u, 0x22u},
+			{0xA5u, 0x10u},
+			{0xA6u, 0x08u},
+			{0xA7u, 0xEFu},
+			{0xA8u, 0xC1u},
+			{0xABu, 0x6Cu},
+			{0xACu, 0x10u},
+			{0xADu, 0x6Cu},
+			{0xB0u, 0x08u},
+			{0xB1u, 0x0Fu},
+			{0xB2u, 0x80u},
+			{0xB3u, 0xF0u},
+			{0xB4u, 0x3Fu},
+			{0xB6u, 0x40u},
+			{0xB8u, 0x20u},
+			{0xB9u, 0x08u},
+			{0xBEu, 0x55u},
 			{0xD4u, 0x40u},
 			{0xD6u, 0x04u},
 			{0xD8u, 0x04u},
 			{0xD9u, 0x04u},
 			{0xDBu, 0x04u},
 			{0xDFu, 0x01u},
-			{0x00u, 0x04u},
-			{0x01u, 0x11u},
-			{0x03u, 0x02u},
-			{0x05u, 0x10u},
-			{0x06u, 0x82u},
-			{0x07u, 0x60u},
-			{0x08u, 0x02u},
-			{0x09u, 0x08u},
-			{0x0Au, 0x19u},
-			{0x0Bu, 0x80u},
-			{0x0Du, 0x02u},
-			{0x0Eu, 0x24u},
-			{0x0Fu, 0x84u},
-			{0x11u, 0x46u},
-			{0x14u, 0x41u},
-			{0x15u, 0x80u},
-			{0x16u, 0x60u},
-			{0x18u, 0x01u},
-			{0x19u, 0x08u},
-			{0x1Au, 0x48u},
-			{0x1Bu, 0x20u},
-			{0x1Cu, 0x80u},
-			{0x21u, 0xC0u},
-			{0x26u, 0x01u},
-			{0x2Eu, 0xA6u},
-			{0x31u, 0x80u},
-			{0x32u, 0x20u},
-			{0x34u, 0x49u},
-			{0x36u, 0x10u},
-			{0x38u, 0x62u},
-			{0x3Eu, 0x08u},
+			{0x00u, 0x02u},
+			{0x04u, 0x04u},
+			{0x06u, 0x06u},
+			{0x07u, 0x40u},
+			{0x0Au, 0x04u},
+			{0x0Cu, 0x0Au},
+			{0x0Eu, 0x08u},
+			{0x0Fu, 0x02u},
+			{0x14u, 0x10u},
+			{0x15u, 0x09u},
+			{0x16u, 0x01u},
+			{0x17u, 0x20u},
+			{0x1Bu, 0x01u},
+			{0x1Du, 0x44u},
+			{0x1Eu, 0x46u},
+			{0x20u, 0x02u},
+			{0x24u, 0x10u},
+			{0x25u, 0x04u},
+			{0x26u, 0x04u},
+			{0x27u, 0x40u},
+			{0x28u, 0x10u},
+			{0x2Au, 0x01u},
+			{0x2Bu, 0x01u},
+			{0x2Cu, 0x1Au},
+			{0x2Eu, 0x02u},
+			{0x30u, 0x2Au},
+			{0x31u, 0x10u},
+			{0x33u, 0x40u},
+			{0x37u, 0x60u},
+			{0x38u, 0x94u},
+			{0x39u, 0x21u},
+			{0x3Cu, 0x14u},
+			{0x3Du, 0x01u},
 			{0x3Fu, 0x80u},
-			{0x46u, 0x08u},
-			{0x47u, 0x20u},
-			{0x59u, 0x04u},
-			{0x5Au, 0x52u},
-			{0x60u, 0x01u},
-			{0x61u, 0x01u},
-			{0x64u, 0x02u},
-			{0x65u, 0x08u},
-			{0x66u, 0x11u},
-			{0x80u, 0x08u},
-			{0x81u, 0x11u},
-			{0x83u, 0x40u},
-			{0x8Au, 0x02u},
-			{0x8Bu, 0x20u},
-			{0x8Cu, 0x80u},
-			{0x8Eu, 0x01u},
-			{0x90u, 0x66u},
-			{0x91u, 0x55u},
-			{0x92u, 0x03u},
-			{0x93u, 0x84u},
-			{0x99u, 0x04u},
-			{0x9Au, 0x70u},
-			{0x9Cu, 0x80u},
-			{0xA1u, 0x0Bu},
-			{0xA2u, 0x30u},
-			{0xA3u, 0x02u},
-			{0xA4u, 0x40u},
-			{0xA5u, 0x80u},
+			{0x59u, 0xC0u},
+			{0x62u, 0x80u},
+			{0x65u, 0x04u},
+			{0x66u, 0xA0u},
+			{0x67u, 0x40u},
+			{0x68u, 0x2Au},
+			{0x69u, 0x01u},
+			{0x6Bu, 0x20u},
+			{0x70u, 0x40u},
+			{0x72u, 0x02u},
+			{0x86u, 0x40u},
+			{0x87u, 0x40u},
+			{0x8Eu, 0x84u},
+			{0x90u, 0x04u},
+			{0x91u, 0x08u},
+			{0x94u, 0x80u},
+			{0x95u, 0x21u},
+			{0x96u, 0x40u},
+			{0x9Au, 0x25u},
+			{0x9Du, 0x90u},
+			{0x9Eu, 0x40u},
+			{0x9Fu, 0x40u},
+			{0xA2u, 0x80u},
+			{0xA3u, 0x40u},
+			{0xA4u, 0x2Au},
+			{0xA5u, 0x04u},
 			{0xA6u, 0x01u},
-			{0xA7u, 0x20u},
-			{0xAAu, 0x04u},
-			{0xADu, 0x80u},
-			{0xC0u, 0xFFu},
-			{0xC2u, 0x7Fu},
-			{0xC4u, 0xBDu},
-			{0xCAu, 0xF0u},
-			{0xCCu, 0xFCu},
-			{0xCEu, 0x5Du},
-			{0xD6u, 0x0Fu},
-			{0xD8u, 0xF9u},
-			{0xE0u, 0x80u},
-			{0xE4u, 0x20u},
-			{0xE6u, 0x40u},
-			{0x04u, 0x40u},
-			{0x0Cu, 0x80u},
-			{0x13u, 0x10u},
+			{0xAAu, 0x10u},
+			{0xAEu, 0x01u},
+			{0xB2u, 0x10u},
+			{0xB3u, 0x80u},
+			{0xC0u, 0xF8u},
+			{0xC2u, 0xF2u},
+			{0xC4u, 0xF0u},
+			{0xCAu, 0xFBu},
+			{0xCCu, 0x3Fu},
+			{0xCEu, 0xFFu},
+			{0xD8u, 0xF8u},
+			{0x06u, 0x08u},
+			{0x0Fu, 0x08u},
+			{0x13u, 0x40u},
 			{0x17u, 0x48u},
-			{0x32u, 0x02u},
+			{0x33u, 0x08u},
 			{0x36u, 0x80u},
 			{0x37u, 0x08u},
-			{0x3Bu, 0x11u},
-			{0x3Du, 0x08u},
-			{0x3Eu, 0x40u},
-			{0x43u, 0x10u},
-			{0x67u, 0x80u},
-			{0x85u, 0x40u},
-			{0x87u, 0x40u},
-			{0x8Cu, 0x10u},
-			{0x8Eu, 0x02u},
+			{0x3Au, 0x01u},
+			{0x3Bu, 0x40u},
+			{0x3Du, 0x84u},
+			{0x42u, 0x01u},
+			{0x5Du, 0x01u},
+			{0x8Cu, 0x08u},
 			{0xC0u, 0x80u},
 			{0xC2u, 0x80u},
 			{0xC4u, 0xE0u},
 			{0xCCu, 0xE0u},
 			{0xCEu, 0xF0u},
 			{0xD0u, 0x10u},
-			{0xD8u, 0x80u},
-			{0xE2u, 0x10u},
-			{0xE6u, 0x10u},
-			{0x31u, 0x04u},
+			{0xD6u, 0x80u},
+			{0x32u, 0x08u},
 			{0x33u, 0x40u},
-			{0x35u, 0x80u},
-			{0x37u, 0x08u},
-			{0x3Au, 0x10u},
-			{0x57u, 0x04u},
-			{0x59u, 0x40u},
-			{0x60u, 0x10u},
-			{0x82u, 0x40u},
-			{0x88u, 0x10u},
-			{0x8Fu, 0x05u},
-			{0x90u, 0x10u},
-			{0x96u, 0x40u},
-			{0x97u, 0x01u},
-			{0x99u, 0x40u},
+			{0x35u, 0x88u},
+			{0x38u, 0x40u},
+			{0x52u, 0x20u},
+			{0x5Bu, 0x20u},
+			{0x63u, 0x40u},
+			{0x87u, 0x40u},
+			{0x95u, 0x04u},
+			{0x96u, 0x01u},
+			{0x98u, 0x08u},
+			{0x9Au, 0x08u},
 			{0x9Bu, 0x40u},
-			{0x9Fu, 0x10u},
-			{0xA0u, 0x80u},
-			{0xA5u, 0x04u},
+			{0x9Eu, 0x01u},
+			{0xA5u, 0x40u},
 			{0xA6u, 0x80u},
-			{0xA8u, 0x40u},
+			{0xA7u, 0x08u},
+			{0xADu, 0x41u},
+			{0xB6u, 0x01u},
+			{0xB7u, 0x04u},
 			{0xCCu, 0xF0u},
 			{0xCEu, 0x10u},
-			{0xD4u, 0xC0u},
+			{0xD4u, 0xA0u},
 			{0xD8u, 0x40u},
-			{0xE2u, 0x20u},
-			{0xECu, 0x20u},
+			{0xE6u, 0x40u},
+			{0xE8u, 0x40u},
+			{0xEAu, 0x10u},
 			{0x12u, 0x80u},
-			{0x5Au, 0x04u},
-			{0x92u, 0x04u},
-			{0x9Du, 0x04u},
-			{0x9Fu, 0x18u},
-			{0xA0u, 0x10u},
-			{0xA5u, 0x04u},
-			{0xA6u, 0x80u},
-			{0xADu, 0x80u},
-			{0xAEu, 0x04u},
-			{0xB0u, 0x80u},
-			{0xB2u, 0x10u},
+			{0x58u, 0x08u},
+			{0x85u, 0x80u},
+			{0x86u, 0x08u},
+			{0x89u, 0x40u},
+			{0x8Cu, 0x40u},
+			{0x94u, 0x40u},
+			{0x95u, 0x04u},
+			{0x96u, 0x01u},
+			{0x98u, 0x08u},
+			{0x9Au, 0x08u},
+			{0x9Du, 0x88u},
+			{0x9Eu, 0x01u},
+			{0xA5u, 0x40u},
+			{0xA6u, 0x88u},
+			{0xA7u, 0x08u},
+			{0xABu, 0x20u},
+			{0xB2u, 0x20u},
 			{0xC4u, 0x10u},
 			{0xD6u, 0x40u},
-			{0xEAu, 0x50u},
-			{0x83u, 0x01u},
-			{0x8Bu, 0x08u},
-			{0x9Fu, 0x18u},
-			{0xA0u, 0x10u},
-			{0xA5u, 0x04u},
-			{0xA9u, 0x04u},
+			{0xE2u, 0x10u},
+			{0xE4u, 0x40u},
+			{0xEAu, 0x80u},
+			{0x82u, 0x08u},
+			{0x83u, 0x20u},
+			{0x95u, 0x04u},
+			{0x96u, 0x01u},
+			{0xA6u, 0x08u},
+			{0xA7u, 0x08u},
+			{0xB1u, 0x08u},
+			{0xB6u, 0x01u},
+			{0xE2u, 0x20u},
 			{0xE6u, 0x20u},
-			{0xEEu, 0x80u},
-			{0x02u, 0x02u},
-			{0x05u, 0x20u},
-			{0x0Bu, 0x02u},
-			{0x0Eu, 0x08u},
-			{0x10u, 0x10u},
-			{0x15u, 0x08u},
-			{0x63u, 0x40u},
-			{0x67u, 0x08u},
-			{0x86u, 0x02u},
-			{0x87u, 0x40u},
-			{0x89u, 0x24u},
-			{0x8Bu, 0x04u},
+			{0x01u, 0x40u},
+			{0x05u, 0x10u},
+			{0x08u, 0x80u},
+			{0x0Fu, 0x02u},
+			{0x10u, 0x80u},
+			{0x14u, 0x20u},
+			{0x5Bu, 0x04u},
+			{0x62u, 0x04u},
+			{0x83u, 0x04u},
+			{0x87u, 0x01u},
+			{0x88u, 0x80u},
 			{0x8Du, 0x40u},
+			{0x8Eu, 0x04u},
 			{0xC0u, 0x03u},
 			{0xC2u, 0x03u},
 			{0xC4u, 0x0Cu},
-			{0xD8u, 0x03u},
-			{0xE0u, 0x01u},
+			{0xD6u, 0x02u},
+			{0xD8u, 0x02u},
 			{0xE2u, 0x06u},
-			{0xE6u, 0x01u},
-			{0x00u, 0x08u},
-			{0x04u, 0x08u},
-			{0x0Au, 0x40u},
-			{0x0Eu, 0x20u},
-			{0x51u, 0x01u},
-			{0x52u, 0x20u},
-			{0x5Cu, 0x02u},
-			{0x65u, 0x20u},
-			{0x81u, 0x20u},
-			{0x84u, 0x04u},
-			{0x86u, 0x10u},
-			{0x8Fu, 0x01u},
-			{0x91u, 0x02u},
-			{0x93u, 0x02u},
-			{0x95u, 0x40u},
-			{0x96u, 0x40u},
-			{0xA2u, 0x04u},
-			{0xADu, 0x01u},
-			{0xB0u, 0x10u},
-			{0xB6u, 0x40u},
+			{0xE4u, 0x08u},
+			{0x01u, 0x02u},
+			{0x05u, 0x01u},
+			{0x09u, 0x04u},
+			{0x0Eu, 0x40u},
+			{0x50u, 0x04u},
+			{0x5Fu, 0x20u},
+			{0x64u, 0x09u},
+			{0x80u, 0x20u},
+			{0x83u, 0x20u},
+			{0x88u, 0x09u},
+			{0x8Cu, 0x80u},
+			{0x98u, 0x20u},
+			{0x99u, 0x10u},
+			{0x9Du, 0x01u},
+			{0xA0u, 0x80u},
+			{0xB5u, 0x01u},
 			{0xC0u, 0x0Cu},
 			{0xC2u, 0x0Cu},
-			{0xD4u, 0x05u},
-			{0xD6u, 0x01u},
+			{0xD4u, 0x04u},
+			{0xD6u, 0x05u},
 			{0xD8u, 0x01u},
-			{0xE2u, 0x02u},
-			{0xEAu, 0x04u},
+			{0xE0u, 0x01u},
+			{0xE4u, 0x04u},
+			{0xE6u, 0x02u},
 			{0xEEu, 0x02u},
-			{0x55u, 0x20u},
-			{0x8Cu, 0x04u},
-			{0x90u, 0x08u},
-			{0x95u, 0x40u},
-			{0x96u, 0x04u},
-			{0x97u, 0x10u},
-			{0x9Au, 0x10u},
-			{0x9Cu, 0x02u},
-			{0xA2u, 0x04u},
-			{0xAEu, 0x30u},
-			{0xAFu, 0x10u},
-			{0xB2u, 0x04u},
+			{0x57u, 0x08u},
+			{0x83u, 0x08u},
+			{0x87u, 0x10u},
+			{0x8Fu, 0x04u},
+			{0x92u, 0x40u},
+			{0x94u, 0x10u},
+			{0xA8u, 0x10u},
+			{0xA9u, 0x10u},
+			{0xADu, 0x02u},
+			{0xB4u, 0x04u},
+			{0xB5u, 0x04u},
 			{0xD4u, 0x02u},
-			{0xE2u, 0x08u},
-			{0xEEu, 0x04u},
-			{0x09u, 0x20u},
+			{0xE2u, 0x02u},
+			{0xE8u, 0x08u},
+			{0xEEu, 0x02u},
+			{0x0Au, 0x08u},
 			{0x0Bu, 0x10u},
-			{0x0Eu, 0x04u},
-			{0x0Fu, 0x20u},
-			{0x89u, 0x20u},
-			{0x93u, 0x08u},
-			{0x95u, 0x40u},
-			{0x96u, 0x04u},
+			{0x0Fu, 0x88u},
+			{0x83u, 0x40u},
+			{0x92u, 0x40u},
+			{0x94u, 0x10u},
+			{0x96u, 0x08u},
 			{0x97u, 0x10u},
-			{0x9Au, 0x10u},
-			{0xA7u, 0x10u},
-			{0xABu, 0x10u},
-			{0xAFu, 0x04u},
-			{0xB0u, 0x02u},
-			{0xB1u, 0x20u},
-			{0xB6u, 0x04u},
-			{0xC2u, 0x0Fu},
-			{0xE6u, 0x01u},
-			{0xE8u, 0x04u},
-			{0xEAu, 0x02u},
-			{0xECu, 0x01u},
-			{0x93u, 0x02u},
-			{0x9Fu, 0x50u},
-			{0xA0u, 0x10u},
-			{0xA5u, 0x04u},
-			{0xB7u, 0x40u},
-			{0x07u, 0x40u},
-			{0x53u, 0x01u},
-			{0x54u, 0x10u},
-			{0x83u, 0x10u},
-			{0x8Du, 0x04u},
-			{0x93u, 0x02u},
-			{0x9Fu, 0x50u},
 			{0xA0u, 0x10u},
-			{0xA5u, 0x04u},
+			{0xA7u, 0x04u},
+			{0xACu, 0x10u},
+			{0xB2u, 0x04u},
+			{0xC2u, 0x0Fu},
+			{0xEAu, 0x01u},
+			{0x86u, 0x01u},
+			{0x92u, 0x80u},
+			{0x95u, 0x04u},
+			{0x96u, 0x01u},
+			{0xA3u, 0x20u},
+			{0xA7u, 0x08u},
+			{0xAAu, 0x40u},
+			{0xE2u, 0x10u},
+			{0xEEu, 0x80u},
+			{0x06u, 0x40u},
+			{0x57u, 0x20u},
+			{0x5Au, 0x80u},
+			{0x85u, 0x04u},
+			{0x86u, 0x40u},
+			{0x92u, 0x80u},
+			{0x95u, 0x04u},
+			{0xA3u, 0x20u},
+			{0xAFu, 0x08u},
 			{0xC0u, 0x20u},
 			{0xD4u, 0xC0u},
-			{0xE2u, 0x20u},
-			{0x93u, 0x08u},
-			{0x95u, 0x40u},
-			{0x9Au, 0x10u},
-			{0x01u, 0x40u},
+			{0xE0u, 0x10u},
+			{0xE6u, 0x40u},
+			{0xEEu, 0x40u},
+			{0x94u, 0x50u},
+			{0x99u, 0x20u},
+			{0xA0u, 0x10u},
+			{0xA8u, 0x40u},
+			{0xAAu, 0x40u},
+			{0xB1u, 0x20u},
+			{0xE8u, 0x04u},
+			{0x00u, 0x40u},
 			{0x04u, 0x10u},
-			{0x53u, 0x04u},
-			{0x56u, 0x10u},
-			{0x8Cu, 0x10u},
-			{0x93u, 0x08u},
-			{0x95u, 0x40u},
-			{0x9Au, 0x10u},
+			{0x54u, 0x10u},
+			{0x5Du, 0x20u},
+			{0x94u, 0x50u},
+			{0x99u, 0x20u},
+			{0xA0u, 0x10u},
 			{0xC0u, 0x03u},
-			{0xD4u, 0x06u},
-			{0xE2u, 0x08u},
+			{0xD4u, 0x02u},
+			{0xD6u, 0x04u},
 			{0x10u, 0x03u},
+			{0x11u, 0x01u},
 			{0x1Cu, 0x03u},
+			{0x1Du, 0x01u},
 			{0x00u, 0xFDu},
 			{0x01u, 0xAFu},
 			{0x02u, 0x0Au},
@@ -2024,32 +2026,19 @@ void cyfitter_cfg(void)
 			/* address, size */
 			{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
 			{(void CYFAR *)(CYREG_PRT1_DR), 16u},
-			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2176u},
-			{(void CYFAR *)(CYDEV_UCFG_B0_P4_ROUTE_BASE), 1792u},
+			{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
 			{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
 			{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
 			{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
 		};
 
-		/* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */
-		static const uint8 CYCODE BS_UDB_0_2_0_CONFIG_VAL[] = {
-			0x00u, 0x00u, 0x00u, 0x00u, 0x13u, 0x00u, 0x24u, 0x00u, 0x68u, 0x00u, 0x00u, 0xFFu, 0x68u, 0x00u, 0x00u, 0xFFu, 
-			0x09u, 0x00u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x10u, 0xFFu, 0x68u, 0x00u, 0x04u, 0x0Fu, 0x03u, 0xF0u, 
-			0x68u, 0xFFu, 0x00u, 0x00u, 0x68u, 0x69u, 0x00u, 0x96u, 0x15u, 0x55u, 0x42u, 0xAAu, 0x68u, 0x33u, 0x00u, 0xCCu, 
-			0x00u, 0x00u, 0x00u, 0x00u, 0x78u, 0x00u, 0x07u, 0xFFu, 0x00u, 0x00u, 0xA0u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 
-			0x26u, 0x04u, 0x50u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, 
-			0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x90u, 0x00u, 0x01u, 
-			0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 
-			0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
-
 		/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
 		static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
-			0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u};
+			0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
 
 		static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
 			/* dest, src, size */
-			{(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), BS_UDB_0_2_0_CONFIG_VAL, 128u},
 			{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
 		};
 
@@ -2059,7 +2048,7 @@ void cyfitter_cfg(void)
 		for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
 		{
 			const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
-			CYMEMZERO(ms->address, (uint32)(ms->size));
+			CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
 		}
 
 		/* Copy device configuration data into registers */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
index 191ee788..3e3d4993 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 8c8315a4..be56b151 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -3,83 +3,111 @@
 .include "cydevicegnu.inc"
 .include "cydevicegnu_trm.inc"
 
-/* Debug_Timer_Interrupt */
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+/* LED1 */
+.set LED1__0__MASK, 0x02
+.set LED1__0__PC, CYREG_PRT0_PC1
+.set LED1__0__PORT, 0
+.set LED1__0__SHIFT, 1
+.set LED1__AG, CYREG_PRT0_AG
+.set LED1__AMUX, CYREG_PRT0_AMUX
+.set LED1__BIE, CYREG_PRT0_BIE
+.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set LED1__BYP, CYREG_PRT0_BYP
+.set LED1__CTL, CYREG_PRT0_CTL
+.set LED1__DM0, CYREG_PRT0_DM0
+.set LED1__DM1, CYREG_PRT0_DM1
+.set LED1__DM2, CYREG_PRT0_DM2
+.set LED1__DR, CYREG_PRT0_DR
+.set LED1__INP_DIS, CYREG_PRT0_INP_DIS
+.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set LED1__LCD_EN, CYREG_PRT0_LCD_EN
+.set LED1__MASK, 0x02
+.set LED1__PORT, 0
+.set LED1__PRT, CYREG_PRT0_PRT
+.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set LED1__PS, CYREG_PRT0_PS
+.set LED1__SHIFT, 1
+.set LED1__SLW, CYREG_PRT0_SLW
 
-/* SD_RX_DMA_COMPLETE */
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SD_CD */
+.set SD_CD__0__MASK, 0x20
+.set SD_CD__0__PC, CYREG_PRT3_PC5
+.set SD_CD__0__PORT, 3
+.set SD_CD__0__SHIFT, 5
+.set SD_CD__AG, CYREG_PRT3_AG
+.set SD_CD__AMUX, CYREG_PRT3_AMUX
+.set SD_CD__BIE, CYREG_PRT3_BIE
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CD__BYP, CYREG_PRT3_BYP
+.set SD_CD__CTL, CYREG_PRT3_CTL
+.set SD_CD__DM0, CYREG_PRT3_DM0
+.set SD_CD__DM1, CYREG_PRT3_DM1
+.set SD_CD__DM2, CYREG_PRT3_DM2
+.set SD_CD__DR, CYREG_PRT3_DR
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CD__MASK, 0x20
+.set SD_CD__PORT, 3
+.set SD_CD__PRT, CYREG_PRT3_PRT
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CD__PS, CYREG_PRT3_PS
+.set SD_CD__SHIFT, 5
+.set SD_CD__SLW, CYREG_PRT3_SLW
 
-/* SD_TX_DMA_COMPLETE */
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SD_CS */
+.set SD_CS__0__MASK, 0x10
+.set SD_CS__0__PC, CYREG_PRT3_PC4
+.set SD_CS__0__PORT, 3
+.set SD_CS__0__SHIFT, 4
+.set SD_CS__AG, CYREG_PRT3_AG
+.set SD_CS__AMUX, CYREG_PRT3_AMUX
+.set SD_CS__BIE, CYREG_PRT3_BIE
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CS__BYP, CYREG_PRT3_BYP
+.set SD_CS__CTL, CYREG_PRT3_CTL
+.set SD_CS__DM0, CYREG_PRT3_DM0
+.set SD_CS__DM1, CYREG_PRT3_DM1
+.set SD_CS__DM2, CYREG_PRT3_DM2
+.set SD_CS__DR, CYREG_PRT3_DR
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CS__MASK, 0x10
+.set SD_CS__PORT, 3
+.set SD_CS__PRT, CYREG_PRT3_PRT
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CS__PS, CYREG_PRT3_PS
+.set SD_CS__SHIFT, 4
+.set SD_CS__SLW, CYREG_PRT3_SLW
 
-/* SCSI_Parity_Error */
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
+/* USBFS_arb_int */
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_arb_int__INTC_MASK, 0x400000
+.set USBFS_arb_int__INTC_NUMBER, 22
+.set USBFS_arb_int__INTC_PRIOR_NUM, 7
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* USBFS_bus_reset */
 .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -91,95 +119,131 @@
 .set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_PHASE */
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+/* USBFS_Dm */
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
 
-/* SCSI_Filtered */
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB00_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB00_ST
+/* USBFS_Dp */
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
 
-/* SCSI_Out_Bits */
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+/* USBFS_dp_int */
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* USBFS_arb_int */
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_arb_int__INTC_MASK, 0x400000
-.set USBFS_arb_int__INTC_NUMBER, 22
-.set USBFS_arb_int__INTC_PRIOR_NUM, 7
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* USBFS_ep_0 */
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x40
+.set USBFS_ep_1__INTC_NUMBER, 6
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x80
+.set USBFS_ep_2__INTC_NUMBER, 7
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_3__INTC_MASK, 0x100
+.set USBFS_ep_3__INTC_NUMBER, 8
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_4__INTC_MASK, 0x200
+.set USBFS_ep_4__INTC_NUMBER, 9
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -191,2186 +255,266 @@
 .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_Ctl */
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+/* USBFS_USB */
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
+.set USBFS_USB__CR0, CYREG_USB_CR0
+.set USBFS_USB__CR1, CYREG_USB_CR1
+.set USBFS_USB__CWA, CYREG_USB_CWA
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
+.set USBFS_USB__PM_ACT_MSK, 0x01
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
+.set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
+.set USBFS_USB__SOF0, CYREG_USB_SOF0
+.set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
 
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x02
-.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__0__PORT, 5
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__0__SHIFT, 1
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x01
-.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__1__PORT, 5
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__1__SHIFT, 0
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__2__MASK, 0x20
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__2__PORT, 6
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__2__SHIFT, 5
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x10
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__3__PORT, 6
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__3__SHIFT, 4
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x80
-.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__4__PORT, 2
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__4__SHIFT, 7
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x40
-.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__5__PORT, 2
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__5__SHIFT, 6
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x08
-.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__6__PORT, 2
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__6__SHIFT, 3
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x04
-.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__7__PORT, 2
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__7__SHIFT, 2
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x02
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__DB0__PORT, 5
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 1
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x01
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__DB1__PORT, 5
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 0
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB2__MASK, 0x20
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__DB2__PORT, 6
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 5
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x10
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__DB3__PORT, 6
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 4
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x80
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__DB4__PORT, 2
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 7
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x40
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__DB5__PORT, 2
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 6
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x08
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__DB6__PORT, 2
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 3
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x04
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__DB7__PORT, 2
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 2
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* SCSI_RST_ISR */
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RST_ISR__INTC_MASK, 0x04
-.set SCSI_RST_ISR__INTC_NUMBER, 2
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB09_10_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB09_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_RxStsReg__4__POS, 4
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
-.set SDCard_BSPIM_RxStsReg__5__POS, 5
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
-.set SDCard_BSPIM_RxStsReg__6__POS, 6
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
-.set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
-.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
-.set SDCard_BSPIM_TxStsReg__2__POS, 2
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
-.set SDCard_BSPIM_TxStsReg__3__POS, 3
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_TxStsReg__4__POS, 4
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__0__MASK, 0x08
-.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3
-.set SCSI_In_DBx__0__PORT, 5
-.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__0__SHIFT, 3
-.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__1__MASK, 0x04
-.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2
-.set SCSI_In_DBx__1__PORT, 5
-.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__1__SHIFT, 2
-.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__2__MASK, 0x80
-.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7
-.set SCSI_In_DBx__2__PORT, 6
-.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__2__SHIFT, 7
-.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__3__MASK, 0x40
-.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6
-.set SCSI_In_DBx__3__PORT, 6
-.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__3__SHIFT, 6
-.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__4__MASK, 0x20
-.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5
-.set SCSI_In_DBx__4__PORT, 12
-.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__4__SHIFT, 5
-.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__5__MASK, 0x10
-.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__5__PORT, 12
-.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__5__SHIFT, 4
-.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__6__MASK, 0x20
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__6__PORT, 2
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__6__SHIFT, 5
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__7__MASK, 0x10
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__7__PORT, 2
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__7__SHIFT, 4
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__DB0__MASK, 0x08
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3
-.set SCSI_In_DBx__DB0__PORT, 5
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__DB0__SHIFT, 3
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__DB1__MASK, 0x04
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2
-.set SCSI_In_DBx__DB1__PORT, 5
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__DB1__SHIFT, 2
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB2__MASK, 0x80
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7
-.set SCSI_In_DBx__DB2__PORT, 6
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB2__SHIFT, 7
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB3__MASK, 0x40
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6
-.set SCSI_In_DBx__DB3__PORT, 6
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB3__SHIFT, 6
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__DB4__MASK, 0x20
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5
-.set SCSI_In_DBx__DB4__PORT, 12
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__DB4__SHIFT, 5
-.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__DB5__MASK, 0x10
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__DB5__PORT, 12
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__DB5__SHIFT, 4
-.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB6__MASK, 0x20
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__DB6__PORT, 2
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB6__SHIFT, 5
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB7__MASK, 0x10
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__DB7__PORT, 2
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB7__SHIFT, 4
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_RX_DMA__DRQ_NUMBER, 0
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0
-.set SCSI_RX_DMA__PRIORITY, 2
-.set SCSI_RX_DMA__TERMIN_EN, 0
-.set SCSI_RX_DMA__TERMIN_SEL, 0
-.set SCSI_RX_DMA__TERMOUT0_EN, 1
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0
-.set SCSI_RX_DMA__TERMOUT1_EN, 0
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0
-
-/* SCSI_TX_DMA */
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_TX_DMA__DRQ_NUMBER, 1
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0
-.set SCSI_TX_DMA__PRIORITY, 2
-.set SCSI_TX_DMA__TERMIN_EN, 0
-.set SCSI_TX_DMA__TERMIN_SEL, 0
-.set SCSI_TX_DMA__TERMOUT0_EN, 1
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1
-.set SCSI_TX_DMA__TERMOUT1_EN, 0
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0
-
-/* SD_Data_Clk */
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
-.set SD_Data_Clk__INDEX, 0x00
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SD_Data_Clk__PM_ACT_MSK, 0x01
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SD_Data_Clk__PM_STBY_MSK, 0x01
-
-/* timer_clock */
-.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
-.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
-.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
-.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
-.set timer_clock__INDEX, 0x02
-.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set timer_clock__PM_ACT_MSK, 0x04
-.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set timer_clock__PM_STBY_MSK, 0x04
-
-/* SCSI_Noise */
-.set SCSI_Noise__0__AG, CYREG_PRT2_AG
-.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE
-.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP
-.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL
-.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0
-.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1
-.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2
-.set SCSI_Noise__0__DR, CYREG_PRT2_DR
-.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Noise__0__MASK, 0x01
-.set SCSI_Noise__0__PC, CYREG_PRT2_PC0
-.set SCSI_Noise__0__PORT, 2
-.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT
-.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Noise__0__PS, CYREG_PRT2_PS
-.set SCSI_Noise__0__SHIFT, 0
-.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW
-.set SCSI_Noise__1__AG, CYREG_PRT6_AG
-.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__1__DR, CYREG_PRT6_DR
-.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__1__MASK, 0x08
-.set SCSI_Noise__1__PC, CYREG_PRT6_PC3
-.set SCSI_Noise__1__PORT, 6
-.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__1__PS, CYREG_PRT6_PS
-.set SCSI_Noise__1__SHIFT, 3
-.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__2__AG, CYREG_PRT4_AG
-.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__2__DR, CYREG_PRT4_DR
-.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__2__MASK, 0x08
-.set SCSI_Noise__2__PC, CYREG_PRT4_PC3
-.set SCSI_Noise__2__PORT, 4
-.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__2__PS, CYREG_PRT4_PS
-.set SCSI_Noise__2__SHIFT, 3
-.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW
-.set SCSI_Noise__3__AG, CYREG_PRT4_AG
-.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__3__DR, CYREG_PRT4_DR
-.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__3__MASK, 0x80
-.set SCSI_Noise__3__PC, CYREG_PRT4_PC7
-.set SCSI_Noise__3__PORT, 4
-.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__3__PS, CYREG_PRT4_PS
-.set SCSI_Noise__3__SHIFT, 7
-.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW
-.set SCSI_Noise__4__AG, CYREG_PRT6_AG
-.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__4__DR, CYREG_PRT6_DR
-.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__4__MASK, 0x04
-.set SCSI_Noise__4__PC, CYREG_PRT6_PC2
-.set SCSI_Noise__4__PORT, 6
-.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__4__PS, CYREG_PRT6_PS
-.set SCSI_Noise__4__SHIFT, 2
-.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
-.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
-.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__ACK__MASK, 0x04
-.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2
-.set SCSI_Noise__ACK__PORT, 6
-.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
-.set SCSI_Noise__ACK__SHIFT, 2
-.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG
-.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE
-.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP
-.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL
-.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0
-.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1
-.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2
-.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR
-.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Noise__ATN__MASK, 0x01
-.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0
-.set SCSI_Noise__ATN__PORT, 2
-.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT
-.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS
-.set SCSI_Noise__ATN__SHIFT, 0
-.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW
-.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
-.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
-.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__BSY__MASK, 0x08
-.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3
-.set SCSI_Noise__BSY__PORT, 6
-.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
-.set SCSI_Noise__BSY__SHIFT, 3
-.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__RST__AG, CYREG_PRT4_AG
-.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__RST__DR, CYREG_PRT4_DR
-.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__RST__MASK, 0x80
-.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7
-.set SCSI_Noise__RST__PORT, 4
-.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__RST__PS, CYREG_PRT4_PS
-.set SCSI_Noise__RST__SHIFT, 7
-.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW
-.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG
-.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR
-.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__SEL__MASK, 0x08
-.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3
-.set SCSI_Noise__SEL__PORT, 4
-.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS
-.set SCSI_Noise__SEL__SHIFT, 3
-.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
-
-/* scsiTarget */
-.set scsiTarget_StatusReg__0__MASK, 0x01
-.set scsiTarget_StatusReg__0__POS, 0
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
-.set scsiTarget_StatusReg__1__MASK, 0x02
-.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__2__MASK, 0x04
-.set scsiTarget_StatusReg__2__POS, 2
-.set scsiTarget_StatusReg__3__MASK, 0x08
-.set scsiTarget_StatusReg__3__POS, 3
-.set scsiTarget_StatusReg__4__MASK, 0x10
-.set scsiTarget_StatusReg__4__POS, 4
-.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x40
-.set USBFS_ep_1__INTC_NUMBER, 6
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x80
-.set USBFS_ep_2__INTC_NUMBER, 7
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x100
-.set USBFS_ep_3__INTC_NUMBER, 8
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_4__INTC_MASK, 0x200
-.set USBFS_ep_4__INTC_NUMBER, 9
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_RX_DMA__DRQ_NUMBER, 2
-.set SD_RX_DMA__NUMBEROF_TDS, 0
-.set SD_RX_DMA__PRIORITY, 2
-.set SD_RX_DMA__TERMIN_EN, 0
-.set SD_RX_DMA__TERMIN_SEL, 0
-.set SD_RX_DMA__TERMOUT0_EN, 1
-.set SD_RX_DMA__TERMOUT0_SEL, 2
-.set SD_RX_DMA__TERMOUT1_EN, 0
-.set SD_RX_DMA__TERMOUT1_SEL, 0
-
-/* SD_TX_DMA */
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_TX_DMA__DRQ_NUMBER, 3
-.set SD_TX_DMA__NUMBEROF_TDS, 0
-.set SD_TX_DMA__PRIORITY, 2
-.set SD_TX_DMA__TERMIN_EN, 0
-.set SD_TX_DMA__TERMIN_SEL, 0
-.set SD_TX_DMA__TERMOUT0_EN, 1
-.set SD_TX_DMA__TERMOUT0_SEL, 3
-.set SD_TX_DMA__TERMOUT1_EN, 0
-.set SD_TX_DMA__TERMOUT1_SEL, 0
-
-/* USBFS_USB */
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
-.set USBFS_USB__CR0, CYREG_USB_CR0
-.set USBFS_USB__CR1, CYREG_USB_CR1
-.set USBFS_USB__CWA, CYREG_USB_CWA
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
-.set USBFS_USB__PM_ACT_MSK, 0x01
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
-.set USBFS_USB__PM_STBY_MSK, 0x01
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
-.set USBFS_USB__SOF0, CYREG_USB_SOF0
-.set USBFS_USB__SOF1, CYREG_USB_SOF1
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
-.set SCSI_CLK__INDEX, 0x01
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SCSI_CLK__PM_ACT_MSK, 0x02
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SCSI_CLK__PM_STBY_MSK, 0x02
-
-/* SCSI_Out */
-.set SCSI_Out__0__AG, CYREG_PRT15_AG
-.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__0__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__0__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__0__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__0__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__0__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__0__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__0__DR, CYREG_PRT15_DR
-.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__0__MASK, 0x20
-.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5
-.set SCSI_Out__0__PORT, 15
-.set SCSI_Out__0__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__0__PS, CYREG_PRT15_PS
-.set SCSI_Out__0__SHIFT, 5
-.set SCSI_Out__0__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__1__AG, CYREG_PRT15_AG
-.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__1__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__1__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__1__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__1__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__1__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__1__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__1__DR, CYREG_PRT15_DR
-.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__1__MASK, 0x10
-.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4
-.set SCSI_Out__1__PORT, 15
-.set SCSI_Out__1__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__1__PS, CYREG_PRT15_PS
-.set SCSI_Out__1__SHIFT, 4
-.set SCSI_Out__1__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__2__AG, CYREG_PRT6_AG
-.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__2__DR, CYREG_PRT6_DR
-.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__2__MASK, 0x02
-.set SCSI_Out__2__PC, CYREG_PRT6_PC1
-.set SCSI_Out__2__PORT, 6
-.set SCSI_Out__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__2__PS, CYREG_PRT6_PS
-.set SCSI_Out__2__SHIFT, 1
-.set SCSI_Out__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__3__AG, CYREG_PRT6_AG
-.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__3__DR, CYREG_PRT6_DR
-.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__3__MASK, 0x01
-.set SCSI_Out__3__PC, CYREG_PRT6_PC0
-.set SCSI_Out__3__PORT, 6
-.set SCSI_Out__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__3__PS, CYREG_PRT6_PS
-.set SCSI_Out__3__SHIFT, 0
-.set SCSI_Out__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__4__AG, CYREG_PRT4_AG
-.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__4__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__4__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__4__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__4__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__4__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__4__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__4__DR, CYREG_PRT4_DR
-.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__4__MASK, 0x20
-.set SCSI_Out__4__PC, CYREG_PRT4_PC5
-.set SCSI_Out__4__PORT, 4
-.set SCSI_Out__4__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__4__PS, CYREG_PRT4_PS
-.set SCSI_Out__4__SHIFT, 5
-.set SCSI_Out__4__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__5__AG, CYREG_PRT4_AG
-.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__5__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__5__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__5__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__5__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__5__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__5__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__5__DR, CYREG_PRT4_DR
-.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__5__MASK, 0x10
-.set SCSI_Out__5__PC, CYREG_PRT4_PC4
-.set SCSI_Out__5__PORT, 4
-.set SCSI_Out__5__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__5__PS, CYREG_PRT4_PS
-.set SCSI_Out__5__SHIFT, 4
-.set SCSI_Out__5__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__6__AG, CYREG_PRT0_AG
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__6__DR, CYREG_PRT0_DR
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__6__MASK, 0x80
-.set SCSI_Out__6__PC, CYREG_PRT0_PC7
-.set SCSI_Out__6__PORT, 0
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__6__PS, CYREG_PRT0_PS
-.set SCSI_Out__6__SHIFT, 7
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__7__AG, CYREG_PRT0_AG
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__7__DR, CYREG_PRT0_DR
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__7__MASK, 0x40
-.set SCSI_Out__7__PC, CYREG_PRT0_PC6
-.set SCSI_Out__7__PORT, 0
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__7__PS, CYREG_PRT0_PS
-.set SCSI_Out__7__SHIFT, 6
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__8__AG, CYREG_PRT0_AG
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__8__DR, CYREG_PRT0_DR
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__8__MASK, 0x08
-.set SCSI_Out__8__PC, CYREG_PRT0_PC3
-.set SCSI_Out__8__PORT, 0
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__8__PS, CYREG_PRT0_PS
-.set SCSI_Out__8__SHIFT, 3
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__9__AG, CYREG_PRT0_AG
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__9__DR, CYREG_PRT0_DR
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__9__MASK, 0x04
-.set SCSI_Out__9__PC, CYREG_PRT0_PC2
-.set SCSI_Out__9__PORT, 0
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__9__PS, CYREG_PRT0_PS
-.set SCSI_Out__9__SHIFT, 2
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__ACK__AG, CYREG_PRT6_AG
-.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__ACK__DR, CYREG_PRT6_DR
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__ACK__MASK, 0x01
-.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0
-.set SCSI_Out__ACK__PORT, 6
-.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__ACK__PS, CYREG_PRT6_PS
-.set SCSI_Out__ACK__SHIFT, 0
-.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__ATN__AG, CYREG_PRT15_AG
-.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__ATN__DR, CYREG_PRT15_DR
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__ATN__MASK, 0x10
-.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4
-.set SCSI_Out__ATN__PORT, 15
-.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__ATN__PS, CYREG_PRT15_PS
-.set SCSI_Out__ATN__SHIFT, 4
-.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__BSY__AG, CYREG_PRT6_AG
-.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__BSY__DR, CYREG_PRT6_DR
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__BSY__MASK, 0x02
-.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1
-.set SCSI_Out__BSY__PORT, 6
-.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__BSY__PS, CYREG_PRT6_PS
-.set SCSI_Out__BSY__SHIFT, 1
-.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__CD_raw__MASK, 0x40
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6
-.set SCSI_Out__CD_raw__PORT, 0
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__CD_raw__SHIFT, 6
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__DBP_raw__MASK, 0x20
-.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5
-.set SCSI_Out__DBP_raw__PORT, 15
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS
-.set SCSI_Out__DBP_raw__SHIFT, 5
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__IO_raw__MASK, 0x04
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2
-.set SCSI_Out__IO_raw__PORT, 0
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__IO_raw__SHIFT, 2
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__MSG_raw__MASK, 0x10
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4
-.set SCSI_Out__MSG_raw__PORT, 4
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS
-.set SCSI_Out__MSG_raw__SHIFT, 4
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__REQ__MASK, 0x08
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3
-.set SCSI_Out__REQ__PORT, 0
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS
-.set SCSI_Out__REQ__SHIFT, 3
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__RST__AG, CYREG_PRT4_AG
-.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__RST__DR, CYREG_PRT4_DR
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__RST__MASK, 0x20
-.set SCSI_Out__RST__PC, CYREG_PRT4_PC5
-.set SCSI_Out__RST__PORT, 4
-.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__RST__PS, CYREG_PRT4_PS
-.set SCSI_Out__RST__SHIFT, 5
-.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__SEL__MASK, 0x80
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7
-.set SCSI_Out__SEL__PORT, 0
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
-.set SCSI_Out__SEL__SHIFT, 7
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
+/* EXTLED */
+.set EXTLED__0__MASK, 0x01
+.set EXTLED__0__PC, CYREG_PRT0_PC0
+.set EXTLED__0__PORT, 0
+.set EXTLED__0__SHIFT, 0
+.set EXTLED__AG, CYREG_PRT0_AG
+.set EXTLED__AMUX, CYREG_PRT0_AMUX
+.set EXTLED__BIE, CYREG_PRT0_BIE
+.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set EXTLED__BYP, CYREG_PRT0_BYP
+.set EXTLED__CTL, CYREG_PRT0_CTL
+.set EXTLED__DM0, CYREG_PRT0_DM0
+.set EXTLED__DM1, CYREG_PRT0_DM1
+.set EXTLED__DM2, CYREG_PRT0_DM2
+.set EXTLED__DR, CYREG_PRT0_DR
+.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS
+.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN
+.set EXTLED__MASK, 0x01
+.set EXTLED__PORT, 0
+.set EXTLED__PRT, CYREG_PRT0_PRT
+.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set EXTLED__PS, CYREG_PRT0_PS
+.set EXTLED__SHIFT, 0
+.set EXTLED__SLW, CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB10_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB10_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB10_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB10_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_RxStsReg__4__POS, 4
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
+.set SDCard_BSPIM_RxStsReg__5__POS, 5
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
+.set SDCard_BSPIM_RxStsReg__6__POS, 6
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB08_09_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB08_09_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB08_09_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB08_09_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB08_09_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB08_09_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB08_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB08_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB08_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB08_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB08_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB08_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB08_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB08_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB08_F1
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
+.set SDCard_BSPIM_TxStsReg__0__POS, 0
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
+.set SDCard_BSPIM_TxStsReg__1__POS, 1
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
+.set SDCard_BSPIM_TxStsReg__2__POS, 2
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
+.set SDCard_BSPIM_TxStsReg__3__POS, 3
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_TxStsReg__4__POS, 4
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
 
-/* USBFS_Dp */
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+.set SD_SCK__0__MASK, 0x04
+.set SD_SCK__0__PC, CYREG_PRT3_PC2
+.set SD_SCK__0__PORT, 3
+.set SD_SCK__0__SHIFT, 2
+.set SD_SCK__AG, CYREG_PRT3_AG
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX
+.set SD_SCK__BIE, CYREG_PRT3_BIE
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_SCK__BYP, CYREG_PRT3_BYP
+.set SD_SCK__CTL, CYREG_PRT3_CTL
+.set SD_SCK__DM0, CYREG_PRT3_DM0
+.set SD_SCK__DM1, CYREG_PRT3_DM1
+.set SD_SCK__DM2, CYREG_PRT3_DM2
+.set SD_SCK__DR, CYREG_PRT3_DR
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_SCK__MASK, 0x04
+.set SD_SCK__PORT, 3
+.set SD_SCK__PRT, CYREG_PRT3_PRT
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_SCK__PS, CYREG_PRT3_PS
+.set SD_SCK__SHIFT, 2
+.set SD_SCK__SLW, CYREG_PRT3_SLW
 
 /* SCSI_In */
 .set SCSI_In__0__AG, CYREG_PRT2_AG
@@ -2644,304 +788,2150 @@
 .set SCSI_In__REQ__SHIFT, 5
 .set SCSI_In__REQ__SLW, CYREG_PRT0_SLW
 
-/* SD_MISO */
-.set SD_MISO__0__MASK, 0x02
-.set SD_MISO__0__PC, CYREG_PRT3_PC1
-.set SD_MISO__0__PORT, 3
-.set SD_MISO__0__SHIFT, 1
-.set SD_MISO__AG, CYREG_PRT3_AG
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX
-.set SD_MISO__BIE, CYREG_PRT3_BIE
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MISO__BYP, CYREG_PRT3_BYP
-.set SD_MISO__CTL, CYREG_PRT3_CTL
-.set SD_MISO__DM0, CYREG_PRT3_DM0
-.set SD_MISO__DM1, CYREG_PRT3_DM1
-.set SD_MISO__DM2, CYREG_PRT3_DM2
-.set SD_MISO__DR, CYREG_PRT3_DR
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MISO__MASK, 0x02
-.set SD_MISO__PORT, 3
-.set SD_MISO__PRT, CYREG_PRT3_PRT
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MISO__PS, CYREG_PRT3_PS
-.set SD_MISO__SHIFT, 1
-.set SD_MISO__SLW, CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__0__MASK, 0x08
+.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3
+.set SCSI_In_DBx__0__PORT, 5
+.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__0__SHIFT, 3
+.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__1__MASK, 0x04
+.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2
+.set SCSI_In_DBx__1__PORT, 5
+.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__1__SHIFT, 2
+.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__2__MASK, 0x80
+.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7
+.set SCSI_In_DBx__2__PORT, 6
+.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__2__SHIFT, 7
+.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__3__MASK, 0x40
+.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6
+.set SCSI_In_DBx__3__PORT, 6
+.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__3__SHIFT, 6
+.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__4__MASK, 0x20
+.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5
+.set SCSI_In_DBx__4__PORT, 12
+.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__4__SHIFT, 5
+.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__5__MASK, 0x10
+.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__5__PORT, 12
+.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__5__SHIFT, 4
+.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__6__MASK, 0x20
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__6__PORT, 2
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__6__SHIFT, 5
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__7__MASK, 0x10
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__7__PORT, 2
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__7__SHIFT, 4
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__DB0__MASK, 0x08
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3
+.set SCSI_In_DBx__DB0__PORT, 5
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__DB0__SHIFT, 3
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__DB1__MASK, 0x04
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2
+.set SCSI_In_DBx__DB1__PORT, 5
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__DB1__SHIFT, 2
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB2__MASK, 0x80
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7
+.set SCSI_In_DBx__DB2__PORT, 6
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB2__SHIFT, 7
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB3__MASK, 0x40
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6
+.set SCSI_In_DBx__DB3__PORT, 6
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB3__SHIFT, 6
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__DB4__MASK, 0x20
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5
+.set SCSI_In_DBx__DB4__PORT, 12
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__DB4__SHIFT, 5
+.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__DB5__MASK, 0x10
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__DB5__PORT, 12
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__DB5__SHIFT, 4
+.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB6__MASK, 0x20
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__DB6__PORT, 2
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB6__SHIFT, 5
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB7__MASK, 0x10
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__DB7__PORT, 2
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB7__SHIFT, 4
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
+
+/* SD_MISO */
+.set SD_MISO__0__MASK, 0x02
+.set SD_MISO__0__PC, CYREG_PRT3_PC1
+.set SD_MISO__0__PORT, 3
+.set SD_MISO__0__SHIFT, 1
+.set SD_MISO__AG, CYREG_PRT3_AG
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX
+.set SD_MISO__BIE, CYREG_PRT3_BIE
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MISO__BYP, CYREG_PRT3_BYP
+.set SD_MISO__CTL, CYREG_PRT3_CTL
+.set SD_MISO__DM0, CYREG_PRT3_DM0
+.set SD_MISO__DM1, CYREG_PRT3_DM1
+.set SD_MISO__DM2, CYREG_PRT3_DM2
+.set SD_MISO__DR, CYREG_PRT3_DR
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MISO__MASK, 0x02
+.set SD_MISO__PORT, 3
+.set SD_MISO__PRT, CYREG_PRT3_PRT
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MISO__PS, CYREG_PRT3_PS
+.set SD_MISO__SHIFT, 1
+.set SD_MISO__SLW, CYREG_PRT3_SLW
+
+/* SD_MOSI */
+.set SD_MOSI__0__MASK, 0x08
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3
+.set SD_MOSI__0__PORT, 3
+.set SD_MOSI__0__SHIFT, 3
+.set SD_MOSI__AG, CYREG_PRT3_AG
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
+.set SD_MOSI__BIE, CYREG_PRT3_BIE
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MOSI__BYP, CYREG_PRT3_BYP
+.set SD_MOSI__CTL, CYREG_PRT3_CTL
+.set SD_MOSI__DM0, CYREG_PRT3_DM0
+.set SD_MOSI__DM1, CYREG_PRT3_DM1
+.set SD_MOSI__DM2, CYREG_PRT3_DM2
+.set SD_MOSI__DR, CYREG_PRT3_DR
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MOSI__MASK, 0x08
+.set SD_MOSI__PORT, 3
+.set SD_MOSI__PRT, CYREG_PRT3_PRT
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MOSI__PS, CYREG_PRT3_PS
+.set SD_MOSI__SHIFT, 3
+.set SD_MOSI__SLW, CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
+.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SCSI_CLK__PM_STBY_MSK, 0x02
+
+/* SCSI_Out */
+.set SCSI_Out__0__AG, CYREG_PRT15_AG
+.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__0__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__0__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__0__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__0__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__0__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__0__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__0__DR, CYREG_PRT15_DR
+.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__0__MASK, 0x20
+.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5
+.set SCSI_Out__0__PORT, 15
+.set SCSI_Out__0__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__0__PS, CYREG_PRT15_PS
+.set SCSI_Out__0__SHIFT, 5
+.set SCSI_Out__0__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__1__AG, CYREG_PRT15_AG
+.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__1__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__1__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__1__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__1__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__1__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__1__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__1__DR, CYREG_PRT15_DR
+.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__1__MASK, 0x10
+.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4
+.set SCSI_Out__1__PORT, 15
+.set SCSI_Out__1__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__1__PS, CYREG_PRT15_PS
+.set SCSI_Out__1__SHIFT, 4
+.set SCSI_Out__1__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__2__AG, CYREG_PRT6_AG
+.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__2__DR, CYREG_PRT6_DR
+.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__2__MASK, 0x02
+.set SCSI_Out__2__PC, CYREG_PRT6_PC1
+.set SCSI_Out__2__PORT, 6
+.set SCSI_Out__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__2__PS, CYREG_PRT6_PS
+.set SCSI_Out__2__SHIFT, 1
+.set SCSI_Out__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__3__AG, CYREG_PRT6_AG
+.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__3__DR, CYREG_PRT6_DR
+.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__3__MASK, 0x01
+.set SCSI_Out__3__PC, CYREG_PRT6_PC0
+.set SCSI_Out__3__PORT, 6
+.set SCSI_Out__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__3__PS, CYREG_PRT6_PS
+.set SCSI_Out__3__SHIFT, 0
+.set SCSI_Out__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__4__AG, CYREG_PRT4_AG
+.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__4__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__4__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__4__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__4__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__4__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__4__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__4__DR, CYREG_PRT4_DR
+.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__4__MASK, 0x20
+.set SCSI_Out__4__PC, CYREG_PRT4_PC5
+.set SCSI_Out__4__PORT, 4
+.set SCSI_Out__4__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__4__PS, CYREG_PRT4_PS
+.set SCSI_Out__4__SHIFT, 5
+.set SCSI_Out__4__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__5__AG, CYREG_PRT4_AG
+.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__5__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__5__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__5__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__5__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__5__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__5__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__5__DR, CYREG_PRT4_DR
+.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__5__MASK, 0x10
+.set SCSI_Out__5__PC, CYREG_PRT4_PC4
+.set SCSI_Out__5__PORT, 4
+.set SCSI_Out__5__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__5__PS, CYREG_PRT4_PS
+.set SCSI_Out__5__SHIFT, 4
+.set SCSI_Out__5__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__6__AG, CYREG_PRT0_AG
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__6__DR, CYREG_PRT0_DR
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__6__MASK, 0x80
+.set SCSI_Out__6__PC, CYREG_PRT0_PC7
+.set SCSI_Out__6__PORT, 0
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__6__PS, CYREG_PRT0_PS
+.set SCSI_Out__6__SHIFT, 7
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__7__AG, CYREG_PRT0_AG
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__7__DR, CYREG_PRT0_DR
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__7__MASK, 0x40
+.set SCSI_Out__7__PC, CYREG_PRT0_PC6
+.set SCSI_Out__7__PORT, 0
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__7__PS, CYREG_PRT0_PS
+.set SCSI_Out__7__SHIFT, 6
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__8__AG, CYREG_PRT0_AG
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__8__DR, CYREG_PRT0_DR
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__8__MASK, 0x08
+.set SCSI_Out__8__PC, CYREG_PRT0_PC3
+.set SCSI_Out__8__PORT, 0
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__8__PS, CYREG_PRT0_PS
+.set SCSI_Out__8__SHIFT, 3
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__9__AG, CYREG_PRT0_AG
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__9__DR, CYREG_PRT0_DR
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__9__MASK, 0x04
+.set SCSI_Out__9__PC, CYREG_PRT0_PC2
+.set SCSI_Out__9__PORT, 0
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__9__PS, CYREG_PRT0_PS
+.set SCSI_Out__9__SHIFT, 2
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__ACK__AG, CYREG_PRT6_AG
+.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__ACK__DR, CYREG_PRT6_DR
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__ACK__MASK, 0x01
+.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0
+.set SCSI_Out__ACK__PORT, 6
+.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__ACK__PS, CYREG_PRT6_PS
+.set SCSI_Out__ACK__SHIFT, 0
+.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__ATN__AG, CYREG_PRT15_AG
+.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__ATN__DR, CYREG_PRT15_DR
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__ATN__MASK, 0x10
+.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4
+.set SCSI_Out__ATN__PORT, 15
+.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__ATN__PS, CYREG_PRT15_PS
+.set SCSI_Out__ATN__SHIFT, 4
+.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__BSY__AG, CYREG_PRT6_AG
+.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__BSY__DR, CYREG_PRT6_DR
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__BSY__MASK, 0x02
+.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1
+.set SCSI_Out__BSY__PORT, 6
+.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__BSY__PS, CYREG_PRT6_PS
+.set SCSI_Out__BSY__SHIFT, 1
+.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__CD_raw__MASK, 0x40
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6
+.set SCSI_Out__CD_raw__PORT, 0
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__CD_raw__SHIFT, 6
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__DBP_raw__MASK, 0x20
+.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5
+.set SCSI_Out__DBP_raw__PORT, 15
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS
+.set SCSI_Out__DBP_raw__SHIFT, 5
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__IO_raw__MASK, 0x04
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2
+.set SCSI_Out__IO_raw__PORT, 0
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__IO_raw__SHIFT, 2
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__MSG_raw__MASK, 0x10
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4
+.set SCSI_Out__MSG_raw__PORT, 4
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS
+.set SCSI_Out__MSG_raw__SHIFT, 4
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__REQ__MASK, 0x08
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3
+.set SCSI_Out__REQ__PORT, 0
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS
+.set SCSI_Out__REQ__SHIFT, 3
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__RST__AG, CYREG_PRT4_AG
+.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__RST__DR, CYREG_PRT4_DR
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__RST__MASK, 0x20
+.set SCSI_Out__RST__PC, CYREG_PRT4_PC5
+.set SCSI_Out__RST__PORT, 4
+.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__RST__PS, CYREG_PRT4_PS
+.set SCSI_Out__RST__SHIFT, 5
+.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__SEL__MASK, 0x80
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7
+.set SCSI_Out__SEL__PORT, 0
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
+.set SCSI_Out__SEL__SHIFT, 7
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
+
+/* SCSI_Out_Ctl */
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
+
+/* SCSI_Out_DBx */
+.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x02
+.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__0__PORT, 5
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__0__SHIFT, 1
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x01
+.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__1__PORT, 5
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__1__SHIFT, 0
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__2__MASK, 0x20
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__2__PORT, 6
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__2__SHIFT, 5
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x10
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__3__PORT, 6
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__3__SHIFT, 4
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x80
+.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__4__PORT, 2
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__4__SHIFT, 7
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x40
+.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__5__PORT, 2
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__5__SHIFT, 6
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x08
+.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__6__PORT, 2
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__6__SHIFT, 3
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x04
+.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__7__PORT, 2
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__7__SHIFT, 2
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x02
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__DB0__PORT, 5
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 1
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x01
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__DB1__PORT, 5
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 0
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB2__MASK, 0x20
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__DB2__PORT, 6
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 5
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x10
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__DB3__PORT, 6
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 4
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x80
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__DB4__PORT, 2
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 7
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x40
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__DB5__PORT, 2
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 6
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x08
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__DB6__PORT, 2
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 3
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x04
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__DB7__PORT, 2
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 2
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
+
+/* SD_RX_DMA */
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_RX_DMA__DRQ_NUMBER, 2
+.set SD_RX_DMA__NUMBEROF_TDS, 0
+.set SD_RX_DMA__PRIORITY, 2
+.set SD_RX_DMA__TERMIN_EN, 0
+.set SD_RX_DMA__TERMIN_SEL, 0
+.set SD_RX_DMA__TERMOUT0_EN, 1
+.set SD_RX_DMA__TERMOUT0_SEL, 2
+.set SD_RX_DMA__TERMOUT1_EN, 0
+.set SD_RX_DMA__TERMOUT1_SEL, 0
+
+/* SD_RX_DMA_COMPLETE */
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_TX_DMA__DRQ_NUMBER, 3
+.set SD_TX_DMA__NUMBEROF_TDS, 0
+.set SD_TX_DMA__PRIORITY, 2
+.set SD_TX_DMA__TERMIN_EN, 0
+.set SD_TX_DMA__TERMIN_SEL, 0
+.set SD_TX_DMA__TERMOUT0_EN, 1
+.set SD_TX_DMA__TERMOUT0_SEL, 3
+.set SD_TX_DMA__TERMOUT1_EN, 0
+.set SD_TX_DMA__TERMOUT1_SEL, 0
+
+/* SD_TX_DMA_COMPLETE */
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+.set SCSI_Noise__0__AG, CYREG_PRT2_AG
+.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP
+.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL
+.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0
+.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1
+.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2
+.set SCSI_Noise__0__DR, CYREG_PRT2_DR
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Noise__0__MASK, 0x01
+.set SCSI_Noise__0__PC, CYREG_PRT2_PC0
+.set SCSI_Noise__0__PORT, 2
+.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT
+.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Noise__0__PS, CYREG_PRT2_PS
+.set SCSI_Noise__0__SHIFT, 0
+.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__1__MASK, 0x08
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC3
+.set SCSI_Noise__1__PORT, 6
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS
+.set SCSI_Noise__1__SHIFT, 3
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__2__AG, CYREG_PRT4_AG
+.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__2__DR, CYREG_PRT4_DR
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__2__MASK, 0x08
+.set SCSI_Noise__2__PC, CYREG_PRT4_PC3
+.set SCSI_Noise__2__PORT, 4
+.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__2__PS, CYREG_PRT4_PS
+.set SCSI_Noise__2__SHIFT, 3
+.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__3__AG, CYREG_PRT4_AG
+.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__3__DR, CYREG_PRT4_DR
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__3__MASK, 0x80
+.set SCSI_Noise__3__PC, CYREG_PRT4_PC7
+.set SCSI_Noise__3__PORT, 4
+.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__3__PS, CYREG_PRT4_PS
+.set SCSI_Noise__3__SHIFT, 7
+.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__4__MASK, 0x04
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC2
+.set SCSI_Noise__4__PORT, 6
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS
+.set SCSI_Noise__4__SHIFT, 2
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__ACK__MASK, 0x04
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2
+.set SCSI_Noise__ACK__PORT, 6
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
+.set SCSI_Noise__ACK__SHIFT, 2
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG
+.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP
+.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL
+.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0
+.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1
+.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2
+.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Noise__ATN__MASK, 0x01
+.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0
+.set SCSI_Noise__ATN__PORT, 2
+.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT
+.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS
+.set SCSI_Noise__ATN__SHIFT, 0
+.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__BSY__MASK, 0x08
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3
+.set SCSI_Noise__BSY__PORT, 6
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
+.set SCSI_Noise__BSY__SHIFT, 3
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__RST__AG, CYREG_PRT4_AG
+.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__RST__DR, CYREG_PRT4_DR
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__RST__MASK, 0x80
+.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7
+.set SCSI_Noise__RST__PORT, 4
+.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__RST__PS, CYREG_PRT4_PS
+.set SCSI_Noise__RST__SHIFT, 7
+.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__SEL__MASK, 0x08
+.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3
+.set SCSI_Noise__SEL__PORT, 4
+.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS
+.set SCSI_Noise__SEL__SHIFT, 3
+.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
+
+/* scsiTarget */
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_StatusReg__0__MASK, 0x01
+.set scsiTarget_StatusReg__0__POS, 0
+.set scsiTarget_StatusReg__1__MASK, 0x02
+.set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
+.set scsiTarget_StatusReg__2__MASK, 0x04
+.set scsiTarget_StatusReg__2__POS, 2
+.set scsiTarget_StatusReg__3__MASK, 0x08
+.set scsiTarget_StatusReg__3__POS, 3
+.set scsiTarget_StatusReg__4__MASK, 0x10
+.set scsiTarget_StatusReg__4__POS, 4
+.set scsiTarget_StatusReg__MASK, 0x1F
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST
 
-/* SD_MOSI */
-.set SD_MOSI__0__MASK, 0x08
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3
-.set SD_MOSI__0__PORT, 3
-.set SD_MOSI__0__SHIFT, 3
-.set SD_MOSI__AG, CYREG_PRT3_AG
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
-.set SD_MOSI__BIE, CYREG_PRT3_BIE
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MOSI__BYP, CYREG_PRT3_BYP
-.set SD_MOSI__CTL, CYREG_PRT3_CTL
-.set SD_MOSI__DM0, CYREG_PRT3_DM0
-.set SD_MOSI__DM1, CYREG_PRT3_DM1
-.set SD_MOSI__DM2, CYREG_PRT3_DM2
-.set SD_MOSI__DR, CYREG_PRT3_DR
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MOSI__MASK, 0x08
-.set SD_MOSI__PORT, 3
-.set SD_MOSI__PRT, CYREG_PRT3_PRT
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MOSI__PS, CYREG_PRT3_PS
-.set SD_MOSI__SHIFT, 3
-.set SD_MOSI__SLW, CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_RX_DMA__DRQ_NUMBER, 0
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0
+.set SCSI_RX_DMA__PRIORITY, 2
+.set SCSI_RX_DMA__TERMIN_EN, 0
+.set SCSI_RX_DMA__TERMIN_SEL, 0
+.set SCSI_RX_DMA__TERMOUT0_EN, 1
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0
+.set SCSI_RX_DMA__TERMOUT1_EN, 0
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0
+
+/* SCSI_RX_DMA_COMPLETE */
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_TX_DMA__DRQ_NUMBER, 1
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0
+.set SCSI_TX_DMA__PRIORITY, 2
+.set SCSI_TX_DMA__TERMIN_EN, 0
+.set SCSI_TX_DMA__TERMIN_SEL, 0
+.set SCSI_TX_DMA__TERMOUT0_EN, 1
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1
+.set SCSI_TX_DMA__TERMOUT1_EN, 0
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0
+
+/* SCSI_TX_DMA_COMPLETE */
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
+.set SD_Data_Clk__INDEX, 0x00
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SD_Data_Clk__PM_ACT_MSK, 0x01
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SD_Data_Clk__PM_STBY_MSK, 0x01
 
-/* EXTLED */
-.set EXTLED__0__MASK, 0x01
-.set EXTLED__0__PC, CYREG_PRT0_PC0
-.set EXTLED__0__PORT, 0
-.set EXTLED__0__SHIFT, 0
-.set EXTLED__AG, CYREG_PRT0_AG
-.set EXTLED__AMUX, CYREG_PRT0_AMUX
-.set EXTLED__BIE, CYREG_PRT0_BIE
-.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set EXTLED__BYP, CYREG_PRT0_BYP
-.set EXTLED__CTL, CYREG_PRT0_CTL
-.set EXTLED__DM0, CYREG_PRT0_DM0
-.set EXTLED__DM1, CYREG_PRT0_DM1
-.set EXTLED__DM2, CYREG_PRT0_DM2
-.set EXTLED__DR, CYREG_PRT0_DR
-.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS
-.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN
-.set EXTLED__MASK, 0x01
-.set EXTLED__PORT, 0
-.set EXTLED__PRT, CYREG_PRT0_PRT
-.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set EXTLED__PS, CYREG_PRT0_PS
-.set EXTLED__SHIFT, 0
-.set EXTLED__SLW, CYREG_PRT0_SLW
+/* timer_clock */
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
+.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
+.set timer_clock__INDEX, 0x02
+.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set timer_clock__PM_ACT_MSK, 0x04
+.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set timer_clock__PM_STBY_MSK, 0x04
 
-/* SD_SCK */
-.set SD_SCK__0__MASK, 0x04
-.set SD_SCK__0__PC, CYREG_PRT3_PC2
-.set SD_SCK__0__PORT, 3
-.set SD_SCK__0__SHIFT, 2
-.set SD_SCK__AG, CYREG_PRT3_AG
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX
-.set SD_SCK__BIE, CYREG_PRT3_BIE
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_SCK__BYP, CYREG_PRT3_BYP
-.set SD_SCK__CTL, CYREG_PRT3_CTL
-.set SD_SCK__DM0, CYREG_PRT3_DM0
-.set SD_SCK__DM1, CYREG_PRT3_DM1
-.set SD_SCK__DM2, CYREG_PRT3_DM2
-.set SD_SCK__DR, CYREG_PRT3_DR
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_SCK__MASK, 0x04
-.set SD_SCK__PORT, 3
-.set SD_SCK__PRT, CYREG_PRT3_PRT
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_SCK__PS, CYREG_PRT3_PS
-.set SD_SCK__SHIFT, 2
-.set SD_SCK__SLW, CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RST_ISR__INTC_MASK, 0x04
+.set SCSI_RST_ISR__INTC_NUMBER, 2
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SD_CD */
-.set SD_CD__0__MASK, 0x20
-.set SD_CD__0__PC, CYREG_PRT3_PC5
-.set SD_CD__0__PORT, 3
-.set SD_CD__0__SHIFT, 5
-.set SD_CD__AG, CYREG_PRT3_AG
-.set SD_CD__AMUX, CYREG_PRT3_AMUX
-.set SD_CD__BIE, CYREG_PRT3_BIE
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CD__BYP, CYREG_PRT3_BYP
-.set SD_CD__CTL, CYREG_PRT3_CTL
-.set SD_CD__DM0, CYREG_PRT3_DM0
-.set SD_CD__DM1, CYREG_PRT3_DM1
-.set SD_CD__DM2, CYREG_PRT3_DM2
-.set SD_CD__DR, CYREG_PRT3_DR
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CD__MASK, 0x20
-.set SD_CD__PORT, 3
-.set SD_CD__PRT, CYREG_PRT3_PRT
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CD__PS, CYREG_PRT3_PS
-.set SD_CD__SHIFT, 5
-.set SD_CD__SLW, CYREG_PRT3_SLW
+/* SCSI_Filtered */
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
 
-/* SD_CS */
-.set SD_CS__0__MASK, 0x10
-.set SD_CS__0__PC, CYREG_PRT3_PC4
-.set SD_CS__0__PORT, 3
-.set SD_CS__0__SHIFT, 4
-.set SD_CS__AG, CYREG_PRT3_AG
-.set SD_CS__AMUX, CYREG_PRT3_AMUX
-.set SD_CS__BIE, CYREG_PRT3_BIE
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CS__BYP, CYREG_PRT3_BYP
-.set SD_CS__CTL, CYREG_PRT3_CTL
-.set SD_CS__DM0, CYREG_PRT3_DM0
-.set SD_CS__DM1, CYREG_PRT3_DM1
-.set SD_CS__DM2, CYREG_PRT3_DM2
-.set SD_CS__DR, CYREG_PRT3_DR
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CS__MASK, 0x10
-.set SD_CS__PORT, 3
-.set SD_CS__PRT, CYREG_PRT3_PRT
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CS__PS, CYREG_PRT3_PS
-.set SD_CS__SHIFT, 4
-.set SD_CS__SLW, CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
 
-/* LED1 */
-.set LED1__0__MASK, 0x02
-.set LED1__0__PC, CYREG_PRT0_PC1
-.set LED1__0__PORT, 0
-.set LED1__0__SHIFT, 1
-.set LED1__AG, CYREG_PRT0_AG
-.set LED1__AMUX, CYREG_PRT0_AMUX
-.set LED1__BIE, CYREG_PRT0_BIE
-.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set LED1__BYP, CYREG_PRT0_BYP
-.set LED1__CTL, CYREG_PRT0_CTL
-.set LED1__DM0, CYREG_PRT0_DM0
-.set LED1__DM1, CYREG_PRT0_DM1
-.set LED1__DM2, CYREG_PRT0_DM2
-.set LED1__DR, CYREG_PRT0_DR
-.set LED1__INP_DIS, CYREG_PRT0_INP_DIS
-.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set LED1__LCD_EN, CYREG_PRT0_LCD_EN
-.set LED1__MASK, 0x02
-.set LED1__PORT, 0
-.set LED1__PRT, CYREG_PRT0_PRT
-.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set LED1__PS, CYREG_PRT0_PS
-.set LED1__SHIFT, 1
-.set LED1__SLW, CYREG_PRT0_SLW
+/* SCSI_Parity_Error */
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB03_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB03_ST
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
-.set CYDEV_CHIP_MEMBER_5B, 4
-.set CYDEV_CHIP_FAMILY_PSOC5, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 4
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
 .set BCLK__BUS_CLK__HZ, 50000000
 .set BCLK__BUS_CLK__KHZ, 50000
 .set BCLK__BUS_CLK__MHZ, 50
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 3
-.set CYDEV_CHIP_DIE_PSOC4A, 2
+.set CYDEV_CHIP_DIE_PANTHER, 6
+.set CYDEV_CHIP_DIE_PSOC4A, 3
+.set CYDEV_CHIP_DIE_PSOC5LP, 5
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
+.set CYDEV_CHIP_FAMILY_PSOC5, 3
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 2
-.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_4A, 3
+.set CYDEV_CHIP_MEMBER_4D, 2
+.set CYDEV_CHIP_MEMBER_4F, 4
+.set CYDEV_CHIP_MEMBER_5A, 6
+.set CYDEV_CHIP_MEMBER_5B, 5
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_3A_ES1, 0
 .set CYDEV_CHIP_REVISION_3A_ES2, 1
 .set CYDEV_CHIP_REVISION_3A_ES3, 3
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
 .set CYDEV_CHIP_REVISION_5B_ES0, 0
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
 .set CYDEV_CONFIGURATION_COMPRESSED, 1
 .set CYDEV_CONFIGURATION_DMA, 0
 .set CYDEV_CONFIGURATION_ECC, 0
 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
 .set CYDEV_CONFIGURATION_MODE_DMA, 2
 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DEBUGGING_DPS_Disable, 3
 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1
 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
 .set CYDEV_DEBUGGING_ENABLE, 1
 .set CYDEV_DEBUGGING_XRES, 0
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24
 .set CYDEV_ECC_ENABLE, 0
-.set CYDEV_HEAP_SIZE, 0x1000
+.set CYDEV_HEAP_SIZE, 0x0400
 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1
 .set CYDEV_INTR_RISING, 0x0000003E
 .set CYDEV_PROJ_TYPE, 2
@@ -2950,7 +2940,7 @@
 .set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
 .set CYDEV_PROJ_TYPE_STANDARD, 0
 .set CYDEV_PROTECTION_ENABLE, 0
-.set CYDEV_STACK_SIZE, 0x4000
+.set CYDEV_STACK_SIZE, 0x1000
 .set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1
 .set CYDEV_USE_BUNDLED_CMSIS, 1
 .set CYDEV_VARIABLE_VDDA, 0
@@ -2960,13 +2950,30 @@
 .set CYDEV_VDDIO1_MV, 5000
 .set CYDEV_VDDIO2_MV, 5000
 .set CYDEV_VDDIO3_MV, 3300
-.set CYDEV_VIO0, 5
 .set CYDEV_VIO0_MV, 5000
-.set CYDEV_VIO1, 5
 .set CYDEV_VIO1_MV, 5000
-.set CYDEV_VIO2, 5
 .set CYDEV_VIO2_MV, 5000
 .set CYDEV_VIO3_MV, 3300
+.set CYIPBLOCK_ARM_CM3_VERSION, 0
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
+.set CYIPBLOCK_P3_COMP_VERSION, 0
+.set CYIPBLOCK_P3_DMA_VERSION, 0
+.set CYIPBLOCK_P3_DRQ_VERSION, 0
+.set CYIPBLOCK_P3_EMIF_VERSION, 0
+.set CYIPBLOCK_P3_I2C_VERSION, 0
+.set CYIPBLOCK_P3_LCD_VERSION, 0
+.set CYIPBLOCK_P3_LPF_VERSION, 0
+.set CYIPBLOCK_P3_PM_VERSION, 0
+.set CYIPBLOCK_P3_TIMER_VERSION, 0
+.set CYIPBLOCK_P3_USB_VERSION, 0
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0
+.set CYIPBLOCK_P3_VREF_VERSION, 0
+.set CYIPBLOCK_S8_GPIO_VERSION, 0
+.set CYIPBLOCK_S8_IRQ_VERSION, 0
+.set CYIPBLOCK_S8_SAR_VERSION, 0
+.set CYIPBLOCK_S8_SIO_VERSION, 0
+.set CYIPBLOCK_S8_UDB_VERSION, 0
 .set DMA_CHANNELS_USED__MASK0, 0x0000000F
 .set CYDEV_BOOTLOADER_ENABLE, 0
 .endif
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index 03e4e159..a59ad0e6 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -3,83 +3,111 @@
     INCLUDE cydeviceiar.inc
     INCLUDE cydeviceiar_trm.inc
 
-/* Debug_Timer_Interrupt */
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+/* LED1 */
+LED1__0__MASK EQU 0x02
+LED1__0__PC EQU CYREG_PRT0_PC1
+LED1__0__PORT EQU 0
+LED1__0__SHIFT EQU 1
+LED1__AG EQU CYREG_PRT0_AG
+LED1__AMUX EQU CYREG_PRT0_AMUX
+LED1__BIE EQU CYREG_PRT0_BIE
+LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED1__BYP EQU CYREG_PRT0_BYP
+LED1__CTL EQU CYREG_PRT0_CTL
+LED1__DM0 EQU CYREG_PRT0_DM0
+LED1__DM1 EQU CYREG_PRT0_DM1
+LED1__DM2 EQU CYREG_PRT0_DM2
+LED1__DR EQU CYREG_PRT0_DR
+LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED1__MASK EQU 0x02
+LED1__PORT EQU 0
+LED1__PRT EQU CYREG_PRT0_PRT
+LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED1__PS EQU CYREG_PRT0_PS
+LED1__SHIFT EQU 1
+LED1__SLW EQU CYREG_PRT0_SLW
 
-/* SD_RX_DMA_COMPLETE */
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SD_CD */
+SD_CD__0__MASK EQU 0x20
+SD_CD__0__PC EQU CYREG_PRT3_PC5
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 5
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x20
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 5
+SD_CD__SLW EQU CYREG_PRT3_SLW
 
-/* SD_TX_DMA_COMPLETE */
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SD_CS */
+SD_CS__0__MASK EQU 0x10
+SD_CS__0__PC EQU CYREG_PRT3_PC4
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 4
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x10
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 4
+SD_CS__SLW EQU CYREG_PRT3_SLW
 
-/* SCSI_Parity_Error */
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
+/* USBFS_arb_int */
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* USBFS_bus_reset */
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -91,95 +119,131 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_CTL_PHASE */
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+/* USBFS_Dm */
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
 
-/* SCSI_Filtered */
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST
+/* USBFS_Dp */
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
 
-/* SCSI_Out_Bits */
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+/* USBFS_dp_int */
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* USBFS_arb_int */
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* USBFS_ep_0 */
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x200
+USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 /* USBFS_sof_int */
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -191,2186 +255,266 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_Ctl */
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+/* USBFS_USB */
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* SCSI_RST_ISR */
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__0__MASK EQU 0x08
-SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__0__PORT EQU 5
-SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__0__SHIFT EQU 3
-SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x04
-SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__1__PORT EQU 5
-SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__1__SHIFT EQU 2
-SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__2__MASK EQU 0x80
-SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__2__PORT EQU 6
-SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__2__SHIFT EQU 7
-SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x40
-SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__3__PORT EQU 6
-SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__3__SHIFT EQU 6
-SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__4__MASK EQU 0x20
-SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__4__PORT EQU 12
-SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__4__SHIFT EQU 5
-SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__5__MASK EQU 0x10
-SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__5__PORT EQU 12
-SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__5__SHIFT EQU 4
-SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x20
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 5
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x10
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__7__PORT EQU 2
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__7__SHIFT EQU 4
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB0__MASK EQU 0x08
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__DB0__PORT EQU 5
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB0__SHIFT EQU 3
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x04
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__DB1__PORT EQU 5
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB1__SHIFT EQU 2
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB2__MASK EQU 0x80
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__DB2__PORT EQU 6
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB2__SHIFT EQU 7
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x40
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__DB3__PORT EQU 6
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB3__SHIFT EQU 6
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB4__MASK EQU 0x20
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__DB4__PORT EQU 12
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB4__SHIFT EQU 5
-SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB5__MASK EQU 0x10
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB5__PORT EQU 12
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB5__SHIFT EQU 4
-SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x20
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 5
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x10
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB7__PORT EQU 2
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB7__SHIFT EQU 4
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SCSI_TX_DMA */
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_Data_Clk */
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-/* timer_clock */
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
-
-/* SCSI_Noise */
-SCSI_Noise__0__AG EQU CYREG_PRT2_AG
-SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__0__DR EQU CYREG_PRT2_DR
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__0__MASK EQU 0x01
-SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__0__PORT EQU 2
-SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__0__PS EQU CYREG_PRT2_PS
-SCSI_Noise__0__SHIFT EQU 0
-SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__1__MASK EQU 0x08
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__1__PORT EQU 6
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS
-SCSI_Noise__1__SHIFT EQU 3
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__2__AG EQU CYREG_PRT4_AG
-SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__2__DR EQU CYREG_PRT4_DR
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__2__MASK EQU 0x08
-SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__2__PORT EQU 4
-SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__2__PS EQU CYREG_PRT4_PS
-SCSI_Noise__2__SHIFT EQU 3
-SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__3__AG EQU CYREG_PRT4_AG
-SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__3__DR EQU CYREG_PRT4_DR
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__3__MASK EQU 0x80
-SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__3__PORT EQU 4
-SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__3__PS EQU CYREG_PRT4_PS
-SCSI_Noise__3__SHIFT EQU 7
-SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__4__MASK EQU 0x04
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__4__PORT EQU 6
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS
-SCSI_Noise__4__SHIFT EQU 2
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__ACK__MASK EQU 0x04
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__ACK__PORT EQU 6
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Noise__ACK__SHIFT EQU 2
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
-SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__ATN__MASK EQU 0x01
-SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__ATN__PORT EQU 2
-SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
-SCSI_Noise__ATN__SHIFT EQU 0
-SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__BSY__MASK EQU 0x08
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__BSY__PORT EQU 6
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Noise__BSY__SHIFT EQU 3
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
-SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__RST__MASK EQU 0x80
-SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__RST__PORT EQU 4
-SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
-SCSI_Noise__RST__SHIFT EQU 7
-SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__SEL__MASK EQU 0x08
-SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__SEL__PORT EQU 4
-SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
-SCSI_Noise__SEL__SHIFT EQU 3
-SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
-
-/* scsiTarget */
-scsiTarget_StatusReg__0__MASK EQU 0x01
-scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
-scsiTarget_StatusReg__1__MASK EQU 0x02
-scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__2__MASK EQU 0x04
-scsiTarget_StatusReg__2__POS EQU 2
-scsiTarget_StatusReg__3__MASK EQU 0x08
-scsiTarget_StatusReg__3__POS EQU 3
-scsiTarget_StatusReg__4__MASK EQU 0x10
-scsiTarget_StatusReg__4__POS EQU 4
-scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 2
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_TX_DMA */
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* USBFS_USB */
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-/* SCSI_Out */
-SCSI_Out__0__AG EQU CYREG_PRT15_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__0__DR EQU CYREG_PRT15_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__0__MASK EQU 0x20
-SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__0__PORT EQU 15
-SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT15_PS
-SCSI_Out__0__SHIFT EQU 5
-SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__1__AG EQU CYREG_PRT15_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__1__DR EQU CYREG_PRT15_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__1__MASK EQU 0x10
-SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__1__PORT EQU 15
-SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT15_PS
-SCSI_Out__1__SHIFT EQU 4
-SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__2__AG EQU CYREG_PRT6_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__2__DR EQU CYREG_PRT6_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__2__MASK EQU 0x02
-SCSI_Out__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out__2__PORT EQU 6
-SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT6_PS
-SCSI_Out__2__SHIFT EQU 1
-SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__3__AG EQU CYREG_PRT6_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__3__DR EQU CYREG_PRT6_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__3__MASK EQU 0x01
-SCSI_Out__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out__3__PORT EQU 6
-SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT6_PS
-SCSI_Out__3__SHIFT EQU 0
-SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__4__AG EQU CYREG_PRT4_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__4__DR EQU CYREG_PRT4_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__4__MASK EQU 0x20
-SCSI_Out__4__PC EQU CYREG_PRT4_PC5
-SCSI_Out__4__PORT EQU 4
-SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT4_PS
-SCSI_Out__4__SHIFT EQU 5
-SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__5__AG EQU CYREG_PRT4_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__5__DR EQU CYREG_PRT4_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__5__MASK EQU 0x10
-SCSI_Out__5__PC EQU CYREG_PRT4_PC4
-SCSI_Out__5__PORT EQU 4
-SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT4_PS
-SCSI_Out__5__SHIFT EQU 4
-SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__6__AG EQU CYREG_PRT0_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__6__DR EQU CYREG_PRT0_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__6__MASK EQU 0x80
-SCSI_Out__6__PC EQU CYREG_PRT0_PC7
-SCSI_Out__6__PORT EQU 0
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT0_PS
-SCSI_Out__6__SHIFT EQU 7
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__7__AG EQU CYREG_PRT0_AG
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__7__DR EQU CYREG_PRT0_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__7__MASK EQU 0x40
-SCSI_Out__7__PC EQU CYREG_PRT0_PC6
-SCSI_Out__7__PORT EQU 0
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT0_PS
-SCSI_Out__7__SHIFT EQU 6
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__8__AG EQU CYREG_PRT0_AG
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__8__DR EQU CYREG_PRT0_DR
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__8__MASK EQU 0x08
-SCSI_Out__8__PC EQU CYREG_PRT0_PC3
-SCSI_Out__8__PORT EQU 0
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__8__PS EQU CYREG_PRT0_PS
-SCSI_Out__8__SHIFT EQU 3
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__9__AG EQU CYREG_PRT0_AG
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__9__DR EQU CYREG_PRT0_DR
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__9__MASK EQU 0x04
-SCSI_Out__9__PC EQU CYREG_PRT0_PC2
-SCSI_Out__9__PORT EQU 0
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__9__PS EQU CYREG_PRT0_PS
-SCSI_Out__9__SHIFT EQU 2
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__ACK__MASK EQU 0x01
-SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
-SCSI_Out__ACK__PORT EQU 6
-SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Out__ACK__SHIFT EQU 0
-SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
-SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__ATN__MASK EQU 0x10
-SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__ATN__PORT EQU 15
-SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
-SCSI_Out__ATN__SHIFT EQU 4
-SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x02
-SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
-SCSI_Out__BSY__PORT EQU 6
-SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Out__BSY__SHIFT EQU 1
-SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x40
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 6
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x20
-SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__DBP_raw__PORT EQU 15
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
-SCSI_Out__DBP_raw__SHIFT EQU 5
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__IO_raw__MASK EQU 0x04
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
-SCSI_Out__IO_raw__PORT EQU 0
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__IO_raw__SHIFT EQU 2
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x10
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
-SCSI_Out__MSG_raw__PORT EQU 4
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
-SCSI_Out__MSG_raw__SHIFT EQU 4
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x08
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
-SCSI_Out__REQ__PORT EQU 0
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
-SCSI_Out__REQ__SHIFT EQU 3
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT4_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT4_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__RST__MASK EQU 0x20
-SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
-SCSI_Out__RST__PORT EQU 4
-SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT4_PS
-SCSI_Out__RST__SHIFT EQU 5
-SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x80
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 7
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+/* EXTLED */
+EXTLED__0__MASK EQU 0x01
+EXTLED__0__PC EQU CYREG_PRT0_PC0
+EXTLED__0__PORT EQU 0
+EXTLED__0__SHIFT EQU 0
+EXTLED__AG EQU CYREG_PRT0_AG
+EXTLED__AMUX EQU CYREG_PRT0_AMUX
+EXTLED__BIE EQU CYREG_PRT0_BIE
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+EXTLED__BYP EQU CYREG_PRT0_BYP
+EXTLED__CTL EQU CYREG_PRT0_CTL
+EXTLED__DM0 EQU CYREG_PRT0_DM0
+EXTLED__DM1 EQU CYREG_PRT0_DM1
+EXTLED__DM2 EQU CYREG_PRT0_DM2
+EXTLED__DR EQU CYREG_PRT0_DR
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
+EXTLED__MASK EQU 0x01
+EXTLED__PORT EQU 0
+EXTLED__PRT EQU CYREG_PRT0_PRT
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+EXTLED__PS EQU CYREG_PRT0_PS
+EXTLED__SHIFT EQU 0
+EXTLED__SLW EQU CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB08_09_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB08_09_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB08_09_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB08_09_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB08_09_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB08_09_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB08_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB08_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB08_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB08_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB08_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB08_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB08_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB08_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB08_F1
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
 
-/* USBFS_Dp */
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+SD_SCK__0__MASK EQU 0x04
+SD_SCK__0__PC EQU CYREG_PRT3_PC2
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 2
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x04
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 2
+SD_SCK__SLW EQU CYREG_PRT3_SLW
 
 /* SCSI_In */
 SCSI_In__0__AG EQU CYREG_PRT2_AG
@@ -2644,304 +788,2150 @@ SCSI_In__REQ__PS EQU CYREG_PRT0_PS
 SCSI_In__REQ__SHIFT EQU 5
 SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW
 
-/* SD_MISO */
-SD_MISO__0__MASK EQU 0x02
-SD_MISO__0__PC EQU CYREG_PRT3_PC1
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 1
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x02
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 1
-SD_MISO__SLW EQU CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__0__MASK EQU 0x08
+SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__0__PORT EQU 5
+SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__0__SHIFT EQU 3
+SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x04
+SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__1__PORT EQU 5
+SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__1__SHIFT EQU 2
+SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__2__MASK EQU 0x80
+SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__2__PORT EQU 6
+SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__2__SHIFT EQU 7
+SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x40
+SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__3__PORT EQU 6
+SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__3__SHIFT EQU 6
+SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__4__MASK EQU 0x20
+SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__4__PORT EQU 12
+SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__4__SHIFT EQU 5
+SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__5__MASK EQU 0x10
+SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__5__PORT EQU 12
+SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__5__SHIFT EQU 4
+SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x20
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 5
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x10
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__7__SHIFT EQU 4
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB0__MASK EQU 0x08
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__DB0__PORT EQU 5
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB0__SHIFT EQU 3
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x04
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__DB1__PORT EQU 5
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB1__SHIFT EQU 2
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB2__MASK EQU 0x80
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__DB2__PORT EQU 6
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB2__SHIFT EQU 7
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x40
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__DB3__PORT EQU 6
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB3__SHIFT EQU 6
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB4__MASK EQU 0x20
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__DB4__PORT EQU 12
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB4__SHIFT EQU 5
+SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB5__MASK EQU 0x10
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB5__PORT EQU 12
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB5__SHIFT EQU 4
+SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x20
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 5
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x10
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB7__SHIFT EQU 4
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+/* SD_MISO */
+SD_MISO__0__MASK EQU 0x02
+SD_MISO__0__PC EQU CYREG_PRT3_PC1
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 1
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x02
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 1
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MOSI */
+SD_MOSI__0__MASK EQU 0x08
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 3
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x08
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 3
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
+/* SCSI_Out */
+SCSI_Out__0__AG EQU CYREG_PRT15_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__0__DR EQU CYREG_PRT15_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__0__MASK EQU 0x20
+SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__0__PORT EQU 15
+SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT15_PS
+SCSI_Out__0__SHIFT EQU 5
+SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__1__AG EQU CYREG_PRT15_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__1__DR EQU CYREG_PRT15_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__1__MASK EQU 0x10
+SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__1__PORT EQU 15
+SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT15_PS
+SCSI_Out__1__SHIFT EQU 4
+SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__2__AG EQU CYREG_PRT6_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__2__DR EQU CYREG_PRT6_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__2__MASK EQU 0x02
+SCSI_Out__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out__2__PORT EQU 6
+SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT6_PS
+SCSI_Out__2__SHIFT EQU 1
+SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__3__AG EQU CYREG_PRT6_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__3__DR EQU CYREG_PRT6_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__3__MASK EQU 0x01
+SCSI_Out__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out__3__PORT EQU 6
+SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT6_PS
+SCSI_Out__3__SHIFT EQU 0
+SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__4__AG EQU CYREG_PRT4_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__4__DR EQU CYREG_PRT4_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__4__MASK EQU 0x20
+SCSI_Out__4__PC EQU CYREG_PRT4_PC5
+SCSI_Out__4__PORT EQU 4
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT4_PS
+SCSI_Out__4__SHIFT EQU 5
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__5__AG EQU CYREG_PRT4_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__5__DR EQU CYREG_PRT4_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__5__MASK EQU 0x10
+SCSI_Out__5__PC EQU CYREG_PRT4_PC4
+SCSI_Out__5__PORT EQU 4
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT4_PS
+SCSI_Out__5__SHIFT EQU 4
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__6__AG EQU CYREG_PRT0_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__6__DR EQU CYREG_PRT0_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__6__MASK EQU 0x80
+SCSI_Out__6__PC EQU CYREG_PRT0_PC7
+SCSI_Out__6__PORT EQU 0
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT0_PS
+SCSI_Out__6__SHIFT EQU 7
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__7__AG EQU CYREG_PRT0_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__7__DR EQU CYREG_PRT0_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__7__MASK EQU 0x40
+SCSI_Out__7__PC EQU CYREG_PRT0_PC6
+SCSI_Out__7__PORT EQU 0
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT0_PS
+SCSI_Out__7__SHIFT EQU 6
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__8__AG EQU CYREG_PRT0_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__8__DR EQU CYREG_PRT0_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__8__MASK EQU 0x08
+SCSI_Out__8__PC EQU CYREG_PRT0_PC3
+SCSI_Out__8__PORT EQU 0
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT0_PS
+SCSI_Out__8__SHIFT EQU 3
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__9__AG EQU CYREG_PRT0_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__9__DR EQU CYREG_PRT0_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__9__MASK EQU 0x04
+SCSI_Out__9__PC EQU CYREG_PRT0_PC2
+SCSI_Out__9__PORT EQU 0
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT0_PS
+SCSI_Out__9__SHIFT EQU 2
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x01
+SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
+SCSI_Out__ACK__PORT EQU 6
+SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Out__ACK__SHIFT EQU 0
+SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x10
+SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__ATN__PORT EQU 15
+SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
+SCSI_Out__ATN__SHIFT EQU 4
+SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x02
+SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
+SCSI_Out__BSY__PORT EQU 6
+SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Out__BSY__SHIFT EQU 1
+SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x40
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 6
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x20
+SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__DBP_raw__PORT EQU 15
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
+SCSI_Out__DBP_raw__SHIFT EQU 5
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x04
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__IO_raw__PORT EQU 0
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__IO_raw__SHIFT EQU 2
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
+SCSI_Out__MSG_raw__PORT EQU 4
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x08
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
+SCSI_Out__REQ__PORT EQU 0
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
+SCSI_Out__REQ__SHIFT EQU 3
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__RST__MASK EQU 0x20
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
+SCSI_Out__RST__PORT EQU 4
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS
+SCSI_Out__RST__SHIFT EQU 5
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x80
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 7
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+
+/* SCSI_Out_Ctl */
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
+
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+/* SD_RX_DMA */
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+
+/* SD_RX_DMA_COMPLETE */
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+
+/* SD_TX_DMA_COMPLETE */
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+SCSI_Noise__0__AG EQU CYREG_PRT2_AG
+SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT2_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__0__MASK EQU 0x01
+SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__0__PORT EQU 2
+SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT2_PS
+SCSI_Noise__0__SHIFT EQU 0
+SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x08
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 3
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT4_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT4_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__2__MASK EQU 0x08
+SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__2__PORT EQU 4
+SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT4_PS
+SCSI_Noise__2__SHIFT EQU 3
+SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT4_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT4_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__3__MASK EQU 0x80
+SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__3__PORT EQU 4
+SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT4_PS
+SCSI_Noise__3__SHIFT EQU 7
+SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x04
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 2
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x04
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 2
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
+SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__ATN__MASK EQU 0x01
+SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__ATN__PORT EQU 2
+SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
+SCSI_Noise__ATN__SHIFT EQU 0
+SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x08
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 3
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x80
+SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__RST__PORT EQU 4
+SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
+SCSI_Noise__RST__SHIFT EQU 7
+SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x08
+SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__SEL__PORT EQU 4
+SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
+SCSI_Noise__SEL__SHIFT EQU 3
+SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
+
+/* scsiTarget */
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__4__MASK EQU 0x10
+scsiTarget_StatusReg__4__POS EQU 4
+scsiTarget_StatusReg__MASK EQU 0x1F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
 
-/* SD_MOSI */
-SD_MOSI__0__MASK EQU 0x08
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 3
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x08
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 3
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+
+/* SCSI_RX_DMA_COMPLETE */
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+
+/* SCSI_TX_DMA_COMPLETE */
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
 
-/* EXTLED */
-EXTLED__0__MASK EQU 0x01
-EXTLED__0__PC EQU CYREG_PRT0_PC0
-EXTLED__0__PORT EQU 0
-EXTLED__0__SHIFT EQU 0
-EXTLED__AG EQU CYREG_PRT0_AG
-EXTLED__AMUX EQU CYREG_PRT0_AMUX
-EXTLED__BIE EQU CYREG_PRT0_BIE
-EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-EXTLED__BYP EQU CYREG_PRT0_BYP
-EXTLED__CTL EQU CYREG_PRT0_CTL
-EXTLED__DM0 EQU CYREG_PRT0_DM0
-EXTLED__DM1 EQU CYREG_PRT0_DM1
-EXTLED__DM2 EQU CYREG_PRT0_DM2
-EXTLED__DR EQU CYREG_PRT0_DR
-EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
-EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
-EXTLED__MASK EQU 0x01
-EXTLED__PORT EQU 0
-EXTLED__PRT EQU CYREG_PRT0_PRT
-EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-EXTLED__PS EQU CYREG_PRT0_PS
-EXTLED__SHIFT EQU 0
-EXTLED__SLW EQU CYREG_PRT0_SLW
+/* timer_clock */
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
+timer_clock__INDEX EQU 0x02
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+timer_clock__PM_STBY_MSK EQU 0x04
 
-/* SD_SCK */
-SD_SCK__0__MASK EQU 0x04
-SD_SCK__0__PC EQU CYREG_PRT3_PC2
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 2
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x04
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 2
-SD_SCK__SLW EQU CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SD_CD */
-SD_CD__0__MASK EQU 0x20
-SD_CD__0__PC EQU CYREG_PRT3_PC5
-SD_CD__0__PORT EQU 3
-SD_CD__0__SHIFT EQU 5
-SD_CD__AG EQU CYREG_PRT3_AG
-SD_CD__AMUX EQU CYREG_PRT3_AMUX
-SD_CD__BIE EQU CYREG_PRT3_BIE
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CD__BYP EQU CYREG_PRT3_BYP
-SD_CD__CTL EQU CYREG_PRT3_CTL
-SD_CD__DM0 EQU CYREG_PRT3_DM0
-SD_CD__DM1 EQU CYREG_PRT3_DM1
-SD_CD__DM2 EQU CYREG_PRT3_DM2
-SD_CD__DR EQU CYREG_PRT3_DR
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CD__MASK EQU 0x20
-SD_CD__PORT EQU 3
-SD_CD__PRT EQU CYREG_PRT3_PRT
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CD__PS EQU CYREG_PRT3_PS
-SD_CD__SHIFT EQU 5
-SD_CD__SLW EQU CYREG_PRT3_SLW
+/* SCSI_Filtered */
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
 
-/* SD_CS */
-SD_CS__0__MASK EQU 0x10
-SD_CS__0__PC EQU CYREG_PRT3_PC4
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 4
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x10
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 4
-SD_CS__SLW EQU CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
-/* LED1 */
-LED1__0__MASK EQU 0x02
-LED1__0__PC EQU CYREG_PRT0_PC1
-LED1__0__PORT EQU 0
-LED1__0__SHIFT EQU 1
-LED1__AG EQU CYREG_PRT0_AG
-LED1__AMUX EQU CYREG_PRT0_AMUX
-LED1__BIE EQU CYREG_PRT0_BIE
-LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED1__BYP EQU CYREG_PRT0_BYP
-LED1__CTL EQU CYREG_PRT0_CTL
-LED1__DM0 EQU CYREG_PRT0_DM0
-LED1__DM1 EQU CYREG_PRT0_DM1
-LED1__DM2 EQU CYREG_PRT0_DM2
-LED1__DR EQU CYREG_PRT0_DR
-LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED1__MASK EQU 0x02
-LED1__PORT EQU 0
-LED1__PRT EQU CYREG_PRT0_PRT
-LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED1__PS EQU CYREG_PRT0_PS
-LED1__SHIFT EQU 1
-LED1__SLW EQU CYREG_PRT0_SLW
+/* SCSI_Parity_Error */
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
-CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_HEAP_SIZE EQU 0x0400
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x0000003E
 CYDEV_PROJ_TYPE EQU 2
@@ -2950,7 +2940,7 @@ CYDEV_PROJ_TYPE_LOADABLE EQU 2
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_STACK_SIZE EQU 0x1000
 CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
 CYDEV_USE_BUNDLED_CMSIS EQU 1
 CYDEV_VARIABLE_VDDA EQU 0
@@ -2960,13 +2950,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 3300
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
 CYDEV_VIO3_MV EQU 3300
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
 CYDEV_BOOTLOADER_ENABLE EQU 0
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index 128b55c6..f2b9e4cc 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -3,83 +3,111 @@ INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc
     GET cydevicerv_trm.inc
 
-; Debug_Timer_Interrupt
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_RX_DMA_COMPLETE
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_TX_DMA_COMPLETE
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; Debug_Timer_TimerHW
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+; LED1
+LED1__0__MASK EQU 0x02
+LED1__0__PC EQU CYREG_PRT0_PC1
+LED1__0__PORT EQU 0
+LED1__0__SHIFT EQU 1
+LED1__AG EQU CYREG_PRT0_AG
+LED1__AMUX EQU CYREG_PRT0_AMUX
+LED1__BIE EQU CYREG_PRT0_BIE
+LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED1__BYP EQU CYREG_PRT0_BYP
+LED1__CTL EQU CYREG_PRT0_CTL
+LED1__DM0 EQU CYREG_PRT0_DM0
+LED1__DM1 EQU CYREG_PRT0_DM1
+LED1__DM2 EQU CYREG_PRT0_DM2
+LED1__DR EQU CYREG_PRT0_DR
+LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED1__MASK EQU 0x02
+LED1__PORT EQU 0
+LED1__PRT EQU CYREG_PRT0_PRT
+LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED1__PS EQU CYREG_PRT0_PS
+LED1__SHIFT EQU 1
+LED1__SLW EQU CYREG_PRT0_SLW
 
-; SD_RX_DMA_COMPLETE
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SD_CD
+SD_CD__0__MASK EQU 0x20
+SD_CD__0__PC EQU CYREG_PRT3_PC5
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 5
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x20
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 5
+SD_CD__SLW EQU CYREG_PRT3_SLW
 
-; SD_TX_DMA_COMPLETE
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SD_CS
+SD_CS__0__MASK EQU 0x10
+SD_CS__0__PC EQU CYREG_PRT3_PC4
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 4
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x10
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 4
+SD_CS__SLW EQU CYREG_PRT3_SLW
 
-; SCSI_Parity_Error
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
+; USBFS_arb_int
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; USBFS_bus_reset
 USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -91,95 +119,131 @@ USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
 USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_CTL_PHASE
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+; USBFS_Dm
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
 
-; SCSI_Filtered
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST
+; USBFS_Dp
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
 
-; SCSI_Out_Bits
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+; USBFS_dp_int
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; USBFS_arb_int
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; USBFS_ep_0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_1
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_2
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_3
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_4
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x200
+USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
 ; USBFS_sof_int
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -191,2186 +255,266 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_Out_Ctl
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+; USBFS_USB
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
 
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; SCSI_RST_ISR
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_In_DBx
-SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__0__MASK EQU 0x08
-SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__0__PORT EQU 5
-SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__0__SHIFT EQU 3
-SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x04
-SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__1__PORT EQU 5
-SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__1__SHIFT EQU 2
-SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__2__MASK EQU 0x80
-SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__2__PORT EQU 6
-SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__2__SHIFT EQU 7
-SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x40
-SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__3__PORT EQU 6
-SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__3__SHIFT EQU 6
-SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__4__MASK EQU 0x20
-SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__4__PORT EQU 12
-SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__4__SHIFT EQU 5
-SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__5__MASK EQU 0x10
-SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__5__PORT EQU 12
-SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__5__SHIFT EQU 4
-SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x20
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 5
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x10
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__7__PORT EQU 2
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__7__SHIFT EQU 4
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB0__MASK EQU 0x08
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__DB0__PORT EQU 5
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB0__SHIFT EQU 3
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x04
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__DB1__PORT EQU 5
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB1__SHIFT EQU 2
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB2__MASK EQU 0x80
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__DB2__PORT EQU 6
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB2__SHIFT EQU 7
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x40
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__DB3__PORT EQU 6
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB3__SHIFT EQU 6
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB4__MASK EQU 0x20
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__DB4__PORT EQU 12
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB4__SHIFT EQU 5
-SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB5__MASK EQU 0x10
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB5__PORT EQU 12
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB5__SHIFT EQU 4
-SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x20
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 5
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x10
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB7__PORT EQU 2
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB7__SHIFT EQU 4
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; SCSI_RX_DMA
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SCSI_TX_DMA
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_Data_Clk
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-; timer_clock
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
-
-; SCSI_Noise
-SCSI_Noise__0__AG EQU CYREG_PRT2_AG
-SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__0__DR EQU CYREG_PRT2_DR
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__0__MASK EQU 0x01
-SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__0__PORT EQU 2
-SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__0__PS EQU CYREG_PRT2_PS
-SCSI_Noise__0__SHIFT EQU 0
-SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__1__MASK EQU 0x08
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__1__PORT EQU 6
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS
-SCSI_Noise__1__SHIFT EQU 3
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__2__AG EQU CYREG_PRT4_AG
-SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__2__DR EQU CYREG_PRT4_DR
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__2__MASK EQU 0x08
-SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__2__PORT EQU 4
-SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__2__PS EQU CYREG_PRT4_PS
-SCSI_Noise__2__SHIFT EQU 3
-SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__3__AG EQU CYREG_PRT4_AG
-SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__3__DR EQU CYREG_PRT4_DR
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__3__MASK EQU 0x80
-SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__3__PORT EQU 4
-SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__3__PS EQU CYREG_PRT4_PS
-SCSI_Noise__3__SHIFT EQU 7
-SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__4__MASK EQU 0x04
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__4__PORT EQU 6
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS
-SCSI_Noise__4__SHIFT EQU 2
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__ACK__MASK EQU 0x04
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__ACK__PORT EQU 6
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Noise__ACK__SHIFT EQU 2
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
-SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__ATN__MASK EQU 0x01
-SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__ATN__PORT EQU 2
-SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
-SCSI_Noise__ATN__SHIFT EQU 0
-SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__BSY__MASK EQU 0x08
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__BSY__PORT EQU 6
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Noise__BSY__SHIFT EQU 3
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
-SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__RST__MASK EQU 0x80
-SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__RST__PORT EQU 4
-SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
-SCSI_Noise__RST__SHIFT EQU 7
-SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__SEL__MASK EQU 0x08
-SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__SEL__PORT EQU 4
-SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
-SCSI_Noise__SEL__SHIFT EQU 3
-SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
-
-; scsiTarget
-scsiTarget_StatusReg__0__MASK EQU 0x01
-scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
-scsiTarget_StatusReg__1__MASK EQU 0x02
-scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__2__MASK EQU 0x04
-scsiTarget_StatusReg__2__POS EQU 2
-scsiTarget_StatusReg__3__MASK EQU 0x08
-scsiTarget_StatusReg__3__POS EQU 3
-scsiTarget_StatusReg__4__MASK EQU 0x10
-scsiTarget_StatusReg__4__POS EQU 4
-scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_3
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_4
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_RX_DMA
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 2
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_TX_DMA
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-; USBFS_USB
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-
-; SCSI_CLK
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-; SCSI_Out
-SCSI_Out__0__AG EQU CYREG_PRT15_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__0__DR EQU CYREG_PRT15_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__0__MASK EQU 0x20
-SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__0__PORT EQU 15
-SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT15_PS
-SCSI_Out__0__SHIFT EQU 5
-SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__1__AG EQU CYREG_PRT15_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__1__DR EQU CYREG_PRT15_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__1__MASK EQU 0x10
-SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__1__PORT EQU 15
-SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT15_PS
-SCSI_Out__1__SHIFT EQU 4
-SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__2__AG EQU CYREG_PRT6_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__2__DR EQU CYREG_PRT6_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__2__MASK EQU 0x02
-SCSI_Out__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out__2__PORT EQU 6
-SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT6_PS
-SCSI_Out__2__SHIFT EQU 1
-SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__3__AG EQU CYREG_PRT6_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__3__DR EQU CYREG_PRT6_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__3__MASK EQU 0x01
-SCSI_Out__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out__3__PORT EQU 6
-SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT6_PS
-SCSI_Out__3__SHIFT EQU 0
-SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__4__AG EQU CYREG_PRT4_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__4__DR EQU CYREG_PRT4_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__4__MASK EQU 0x20
-SCSI_Out__4__PC EQU CYREG_PRT4_PC5
-SCSI_Out__4__PORT EQU 4
-SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT4_PS
-SCSI_Out__4__SHIFT EQU 5
-SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__5__AG EQU CYREG_PRT4_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__5__DR EQU CYREG_PRT4_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__5__MASK EQU 0x10
-SCSI_Out__5__PC EQU CYREG_PRT4_PC4
-SCSI_Out__5__PORT EQU 4
-SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT4_PS
-SCSI_Out__5__SHIFT EQU 4
-SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__6__AG EQU CYREG_PRT0_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__6__DR EQU CYREG_PRT0_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__6__MASK EQU 0x80
-SCSI_Out__6__PC EQU CYREG_PRT0_PC7
-SCSI_Out__6__PORT EQU 0
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT0_PS
-SCSI_Out__6__SHIFT EQU 7
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__7__AG EQU CYREG_PRT0_AG
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__7__DR EQU CYREG_PRT0_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__7__MASK EQU 0x40
-SCSI_Out__7__PC EQU CYREG_PRT0_PC6
-SCSI_Out__7__PORT EQU 0
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT0_PS
-SCSI_Out__7__SHIFT EQU 6
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__8__AG EQU CYREG_PRT0_AG
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__8__DR EQU CYREG_PRT0_DR
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__8__MASK EQU 0x08
-SCSI_Out__8__PC EQU CYREG_PRT0_PC3
-SCSI_Out__8__PORT EQU 0
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__8__PS EQU CYREG_PRT0_PS
-SCSI_Out__8__SHIFT EQU 3
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__9__AG EQU CYREG_PRT0_AG
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__9__DR EQU CYREG_PRT0_DR
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__9__MASK EQU 0x04
-SCSI_Out__9__PC EQU CYREG_PRT0_PC2
-SCSI_Out__9__PORT EQU 0
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__9__PS EQU CYREG_PRT0_PS
-SCSI_Out__9__SHIFT EQU 2
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__ACK__MASK EQU 0x01
-SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
-SCSI_Out__ACK__PORT EQU 6
-SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Out__ACK__SHIFT EQU 0
-SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
-SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__ATN__MASK EQU 0x10
-SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__ATN__PORT EQU 15
-SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
-SCSI_Out__ATN__SHIFT EQU 4
-SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x02
-SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
-SCSI_Out__BSY__PORT EQU 6
-SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Out__BSY__SHIFT EQU 1
-SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x40
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 6
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x20
-SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__DBP_raw__PORT EQU 15
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
-SCSI_Out__DBP_raw__SHIFT EQU 5
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__IO_raw__MASK EQU 0x04
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
-SCSI_Out__IO_raw__PORT EQU 0
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__IO_raw__SHIFT EQU 2
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x10
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
-SCSI_Out__MSG_raw__PORT EQU 4
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
-SCSI_Out__MSG_raw__SHIFT EQU 4
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x08
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
-SCSI_Out__REQ__PORT EQU 0
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
-SCSI_Out__REQ__SHIFT EQU 3
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT4_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT4_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__RST__MASK EQU 0x20
-SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
-SCSI_Out__RST__PORT EQU 4
-SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT4_PS
-SCSI_Out__RST__SHIFT EQU 5
-SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x80
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 7
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+; EXTLED
+EXTLED__0__MASK EQU 0x01
+EXTLED__0__PC EQU CYREG_PRT0_PC0
+EXTLED__0__PORT EQU 0
+EXTLED__0__SHIFT EQU 0
+EXTLED__AG EQU CYREG_PRT0_AG
+EXTLED__AMUX EQU CYREG_PRT0_AMUX
+EXTLED__BIE EQU CYREG_PRT0_BIE
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+EXTLED__BYP EQU CYREG_PRT0_BYP
+EXTLED__CTL EQU CYREG_PRT0_CTL
+EXTLED__DM0 EQU CYREG_PRT0_DM0
+EXTLED__DM1 EQU CYREG_PRT0_DM1
+EXTLED__DM2 EQU CYREG_PRT0_DM2
+EXTLED__DR EQU CYREG_PRT0_DR
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
+EXTLED__MASK EQU 0x01
+EXTLED__PORT EQU 0
+EXTLED__PRT EQU CYREG_PRT0_PRT
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+EXTLED__PS EQU CYREG_PRT0_PS
+EXTLED__SHIFT EQU 0
+EXTLED__SLW EQU CYREG_PRT0_SLW
 
-; USBFS_Dm
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+; SDCard_BSPIM
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB08_09_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB08_09_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB08_09_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB08_09_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB08_09_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB08_09_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB08_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB08_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB08_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB08_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB08_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB08_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB08_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB08_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB08_F1
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
 
-; USBFS_Dp
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+; SD_SCK
+SD_SCK__0__MASK EQU 0x04
+SD_SCK__0__PC EQU CYREG_PRT3_PC2
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 2
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x04
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 2
+SD_SCK__SLW EQU CYREG_PRT3_SLW
 
 ; SCSI_In
 SCSI_In__0__AG EQU CYREG_PRT2_AG
@@ -2644,304 +788,2150 @@ SCSI_In__REQ__PS EQU CYREG_PRT0_PS
 SCSI_In__REQ__SHIFT EQU 5
 SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW
 
-; SD_MISO
-SD_MISO__0__MASK EQU 0x02
-SD_MISO__0__PC EQU CYREG_PRT3_PC1
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 1
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x02
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 1
-SD_MISO__SLW EQU CYREG_PRT3_SLW
+; SCSI_In_DBx
+SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__0__MASK EQU 0x08
+SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__0__PORT EQU 5
+SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__0__SHIFT EQU 3
+SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x04
+SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__1__PORT EQU 5
+SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__1__SHIFT EQU 2
+SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__2__MASK EQU 0x80
+SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__2__PORT EQU 6
+SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__2__SHIFT EQU 7
+SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x40
+SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__3__PORT EQU 6
+SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__3__SHIFT EQU 6
+SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__4__MASK EQU 0x20
+SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__4__PORT EQU 12
+SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__4__SHIFT EQU 5
+SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__5__MASK EQU 0x10
+SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__5__PORT EQU 12
+SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__5__SHIFT EQU 4
+SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x20
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 5
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x10
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__7__SHIFT EQU 4
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB0__MASK EQU 0x08
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__DB0__PORT EQU 5
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB0__SHIFT EQU 3
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x04
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__DB1__PORT EQU 5
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB1__SHIFT EQU 2
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB2__MASK EQU 0x80
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__DB2__PORT EQU 6
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB2__SHIFT EQU 7
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x40
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__DB3__PORT EQU 6
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB3__SHIFT EQU 6
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB4__MASK EQU 0x20
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__DB4__PORT EQU 12
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB4__SHIFT EQU 5
+SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB5__MASK EQU 0x10
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB5__PORT EQU 12
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB5__SHIFT EQU 4
+SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x20
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 5
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x10
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB7__SHIFT EQU 4
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+; SD_MISO
+SD_MISO__0__MASK EQU 0x02
+SD_MISO__0__PC EQU CYREG_PRT3_PC1
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 1
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x02
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 1
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+; SD_MOSI
+SD_MOSI__0__MASK EQU 0x08
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 3
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x08
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 3
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+; SCSI_CLK
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
+; SCSI_Out
+SCSI_Out__0__AG EQU CYREG_PRT15_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__0__DR EQU CYREG_PRT15_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__0__MASK EQU 0x20
+SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__0__PORT EQU 15
+SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT15_PS
+SCSI_Out__0__SHIFT EQU 5
+SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__1__AG EQU CYREG_PRT15_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__1__DR EQU CYREG_PRT15_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__1__MASK EQU 0x10
+SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__1__PORT EQU 15
+SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT15_PS
+SCSI_Out__1__SHIFT EQU 4
+SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__2__AG EQU CYREG_PRT6_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__2__DR EQU CYREG_PRT6_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__2__MASK EQU 0x02
+SCSI_Out__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out__2__PORT EQU 6
+SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT6_PS
+SCSI_Out__2__SHIFT EQU 1
+SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__3__AG EQU CYREG_PRT6_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__3__DR EQU CYREG_PRT6_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__3__MASK EQU 0x01
+SCSI_Out__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out__3__PORT EQU 6
+SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT6_PS
+SCSI_Out__3__SHIFT EQU 0
+SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__4__AG EQU CYREG_PRT4_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__4__DR EQU CYREG_PRT4_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__4__MASK EQU 0x20
+SCSI_Out__4__PC EQU CYREG_PRT4_PC5
+SCSI_Out__4__PORT EQU 4
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT4_PS
+SCSI_Out__4__SHIFT EQU 5
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__5__AG EQU CYREG_PRT4_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__5__DR EQU CYREG_PRT4_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__5__MASK EQU 0x10
+SCSI_Out__5__PC EQU CYREG_PRT4_PC4
+SCSI_Out__5__PORT EQU 4
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT4_PS
+SCSI_Out__5__SHIFT EQU 4
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__6__AG EQU CYREG_PRT0_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__6__DR EQU CYREG_PRT0_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__6__MASK EQU 0x80
+SCSI_Out__6__PC EQU CYREG_PRT0_PC7
+SCSI_Out__6__PORT EQU 0
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT0_PS
+SCSI_Out__6__SHIFT EQU 7
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__7__AG EQU CYREG_PRT0_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__7__DR EQU CYREG_PRT0_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__7__MASK EQU 0x40
+SCSI_Out__7__PC EQU CYREG_PRT0_PC6
+SCSI_Out__7__PORT EQU 0
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT0_PS
+SCSI_Out__7__SHIFT EQU 6
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__8__AG EQU CYREG_PRT0_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__8__DR EQU CYREG_PRT0_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__8__MASK EQU 0x08
+SCSI_Out__8__PC EQU CYREG_PRT0_PC3
+SCSI_Out__8__PORT EQU 0
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT0_PS
+SCSI_Out__8__SHIFT EQU 3
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__9__AG EQU CYREG_PRT0_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__9__DR EQU CYREG_PRT0_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__9__MASK EQU 0x04
+SCSI_Out__9__PC EQU CYREG_PRT0_PC2
+SCSI_Out__9__PORT EQU 0
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT0_PS
+SCSI_Out__9__SHIFT EQU 2
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x01
+SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
+SCSI_Out__ACK__PORT EQU 6
+SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Out__ACK__SHIFT EQU 0
+SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x10
+SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__ATN__PORT EQU 15
+SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
+SCSI_Out__ATN__SHIFT EQU 4
+SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x02
+SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
+SCSI_Out__BSY__PORT EQU 6
+SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Out__BSY__SHIFT EQU 1
+SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x40
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 6
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x20
+SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__DBP_raw__PORT EQU 15
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
+SCSI_Out__DBP_raw__SHIFT EQU 5
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x04
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__IO_raw__PORT EQU 0
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__IO_raw__SHIFT EQU 2
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
+SCSI_Out__MSG_raw__PORT EQU 4
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x08
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
+SCSI_Out__REQ__PORT EQU 0
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
+SCSI_Out__REQ__SHIFT EQU 3
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__RST__MASK EQU 0x20
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
+SCSI_Out__RST__PORT EQU 4
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS
+SCSI_Out__RST__SHIFT EQU 5
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x80
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 7
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+
+; SCSI_Out_Bits
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+
+; SCSI_Out_Ctl
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
+
+; SCSI_Out_DBx
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+; SD_RX_DMA
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+
+; SD_RX_DMA_COMPLETE
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_TX_DMA
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+
+; SD_TX_DMA_COMPLETE
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_Noise
+SCSI_Noise__0__AG EQU CYREG_PRT2_AG
+SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT2_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__0__MASK EQU 0x01
+SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__0__PORT EQU 2
+SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT2_PS
+SCSI_Noise__0__SHIFT EQU 0
+SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x08
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 3
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT4_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT4_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__2__MASK EQU 0x08
+SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__2__PORT EQU 4
+SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT4_PS
+SCSI_Noise__2__SHIFT EQU 3
+SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT4_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT4_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__3__MASK EQU 0x80
+SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__3__PORT EQU 4
+SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT4_PS
+SCSI_Noise__3__SHIFT EQU 7
+SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x04
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 2
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x04
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 2
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
+SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__ATN__MASK EQU 0x01
+SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__ATN__PORT EQU 2
+SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
+SCSI_Noise__ATN__SHIFT EQU 0
+SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x08
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 3
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x80
+SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__RST__PORT EQU 4
+SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
+SCSI_Noise__RST__SHIFT EQU 7
+SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x08
+SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__SEL__PORT EQU 4
+SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
+SCSI_Noise__SEL__SHIFT EQU 3
+SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
+
+; scsiTarget
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__4__MASK EQU 0x10
+scsiTarget_StatusReg__4__POS EQU 4
+scsiTarget_StatusReg__MASK EQU 0x1F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
 
-; SD_MOSI
-SD_MOSI__0__MASK EQU 0x08
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 3
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x08
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 3
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
+; Debug_Timer_Interrupt
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; Debug_Timer_TimerHW
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
+; SCSI_RX_DMA
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+
+; SCSI_RX_DMA_COMPLETE
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_TX_DMA
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+
+; SCSI_TX_DMA_COMPLETE
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_Data_Clk
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
 
-; EXTLED
-EXTLED__0__MASK EQU 0x01
-EXTLED__0__PC EQU CYREG_PRT0_PC0
-EXTLED__0__PORT EQU 0
-EXTLED__0__SHIFT EQU 0
-EXTLED__AG EQU CYREG_PRT0_AG
-EXTLED__AMUX EQU CYREG_PRT0_AMUX
-EXTLED__BIE EQU CYREG_PRT0_BIE
-EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-EXTLED__BYP EQU CYREG_PRT0_BYP
-EXTLED__CTL EQU CYREG_PRT0_CTL
-EXTLED__DM0 EQU CYREG_PRT0_DM0
-EXTLED__DM1 EQU CYREG_PRT0_DM1
-EXTLED__DM2 EQU CYREG_PRT0_DM2
-EXTLED__DR EQU CYREG_PRT0_DR
-EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
-EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
-EXTLED__MASK EQU 0x01
-EXTLED__PORT EQU 0
-EXTLED__PRT EQU CYREG_PRT0_PRT
-EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-EXTLED__PS EQU CYREG_PRT0_PS
-EXTLED__SHIFT EQU 0
-EXTLED__SLW EQU CYREG_PRT0_SLW
+; timer_clock
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
+timer_clock__INDEX EQU 0x02
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+timer_clock__PM_STBY_MSK EQU 0x04
 
-; SD_SCK
-SD_SCK__0__MASK EQU 0x04
-SD_SCK__0__PC EQU CYREG_PRT3_PC2
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 2
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x04
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 2
-SD_SCK__SLW EQU CYREG_PRT3_SLW
+; SCSI_RST_ISR
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SD_CD
-SD_CD__0__MASK EQU 0x20
-SD_CD__0__PC EQU CYREG_PRT3_PC5
-SD_CD__0__PORT EQU 3
-SD_CD__0__SHIFT EQU 5
-SD_CD__AG EQU CYREG_PRT3_AG
-SD_CD__AMUX EQU CYREG_PRT3_AMUX
-SD_CD__BIE EQU CYREG_PRT3_BIE
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CD__BYP EQU CYREG_PRT3_BYP
-SD_CD__CTL EQU CYREG_PRT3_CTL
-SD_CD__DM0 EQU CYREG_PRT3_DM0
-SD_CD__DM1 EQU CYREG_PRT3_DM1
-SD_CD__DM2 EQU CYREG_PRT3_DM2
-SD_CD__DR EQU CYREG_PRT3_DR
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CD__MASK EQU 0x20
-SD_CD__PORT EQU 3
-SD_CD__PRT EQU CYREG_PRT3_PRT
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CD__PS EQU CYREG_PRT3_PS
-SD_CD__SHIFT EQU 5
-SD_CD__SLW EQU CYREG_PRT3_SLW
+; SCSI_Filtered
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
 
-; SD_CS
-SD_CS__0__MASK EQU 0x10
-SD_CS__0__PC EQU CYREG_PRT3_PC4
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 4
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x10
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 4
-SD_CS__SLW EQU CYREG_PRT3_SLW
+; SCSI_CTL_PHASE
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
 
-; LED1
-LED1__0__MASK EQU 0x02
-LED1__0__PC EQU CYREG_PRT0_PC1
-LED1__0__PORT EQU 0
-LED1__0__SHIFT EQU 1
-LED1__AG EQU CYREG_PRT0_AG
-LED1__AMUX EQU CYREG_PRT0_AMUX
-LED1__BIE EQU CYREG_PRT0_BIE
-LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED1__BYP EQU CYREG_PRT0_BYP
-LED1__CTL EQU CYREG_PRT0_CTL
-LED1__DM0 EQU CYREG_PRT0_DM0
-LED1__DM1 EQU CYREG_PRT0_DM1
-LED1__DM2 EQU CYREG_PRT0_DM2
-LED1__DR EQU CYREG_PRT0_DR
-LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED1__MASK EQU 0x02
-LED1__PORT EQU 0
-LED1__PRT EQU CYREG_PRT0_PRT
-LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED1__PS EQU CYREG_PRT0_PS
-LED1__SHIFT EQU 1
-LED1__SLW EQU CYREG_PRT0_SLW
+; SCSI_Parity_Error
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
 
 ; Miscellaneous
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
 BCLK__BUS_CLK__HZ EQU 50000000
 BCLK__BUS_CLK__KHZ EQU 50000
 BCLK__BUS_CLK__MHZ EQU 50
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
-CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_HEAP_SIZE EQU 0x0400
 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
 CYDEV_INTR_RISING EQU 0x0000003E
 CYDEV_PROJ_TYPE EQU 2
@@ -2950,7 +2940,7 @@ CYDEV_PROJ_TYPE_LOADABLE EQU 2
 CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
 CYDEV_PROJ_TYPE_STANDARD EQU 0
 CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_STACK_SIZE EQU 0x1000
 CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
 CYDEV_USE_BUNDLED_CMSIS EQU 1
 CYDEV_VARIABLE_VDDA EQU 0
@@ -2960,13 +2950,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 3300
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
 CYDEV_VIO3_MV EQU 3300
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
 CYDEV_BOOTLOADER_ENABLE EQU 0
     ENDIF
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
index cbc85a92..dfaca9db 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cymetadata.c
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file defines all extra memory spaces that need to be included.
@@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used))
 const uint8 cy_meta_loadable[] = {
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
-    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x03u, 0x04u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x10u, 0x04u,
     0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
     0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
index 6caced2f..b7525d13 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
@@ -1,9 +1,9 @@
 /*******************************************************************************
 * File Name: cypins.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   This file contains the function prototypes and constants used for port/pin
+*   This file contains the function prototypes and constants used for a port/pin
 *   in access and control.
 *
 *  Note:
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -103,6 +103,13 @@
 *  Note that this only has an effect for pins configured as software pins that
 *  are not driven by hardware.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16).
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -123,7 +130,14 @@
 ********************************************************************************
 *
 * Summary:
-*  This macro sets the state of the specified pin to 0
+*  This macro sets the state of the specified pin to 0.
+*
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
 *
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
@@ -147,6 +161,13 @@
 * Summary:
 *  Sets the drive mode for the pin (DM).
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16)
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -193,7 +214,7 @@
 *
 *
 * Return:
-*   mode:  Current drive mode for the pin
+*   mode:  The current drive mode for the pin
 *
 *   Define                Source
 *   PIN_DM_ALG_HIZ        Analog HiZ
@@ -214,10 +235,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to fast edge rate.
+*  Set the slew rate for the pin to fast the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -239,10 +267,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to slow edge rate.
+*  Set the slew rate for the pin to slow the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -259,7 +294,18 @@
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)
 #define PC_DRIVE_MODE_MASK  (CY_PINS_PC_DRIVE_MODE_MASK)
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
index 24db0621..528f949f 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cytypes.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  CyTypes provides register access macros and approved types for use in
@@ -12,12 +12,12 @@
 *  data the correct way.
 *
 *  Register Access macros and functions perform their operations on an
-*  input of type pointer to void.  The arguments passed to it should be
+*  input of the type pointer to void.  The arguments passed to it should be
 *  pointers to the type associated with the register size.
 *  (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -40,7 +40,7 @@
 
 #if defined( __ICCARM__ )
     /* Suppress warning for multiple volatile variables in an expression. */
-    /* This is common in component code and the usage is not order dependent. */
+    /* This is common in component code and usage is not order dependent. */
     #pragma diag_suppress=Pa082
 #endif  /* defined( __ICCARM__ ) */
 
@@ -61,28 +61,98 @@
 /*******************************************************************************
 * MEMBER encodes both the family and the detailed architecture
 *******************************************************************************/
-#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
 #ifdef CYDEV_CHIP_MEMBER_4D
-    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
 #else
-    #define CY_PSOC4D   (0u != 0u)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (0u != 0u)
 #endif  /* CYDEV_CHIP_MEMBER_4D */
 
-#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
-#ifdef CYDEV_CHIP_MEMBER_5B
-    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#define CY_PSOC4_4100       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#define CY_PSOC4_4200       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+
+#ifdef CYDEV_CHIP_MEMBER_4F
+    #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
+    #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
 #else
-    #define CY_PSOC5LP  (0u != 0u)
-#endif  /* CYDEV_CHIP_MEMBER_5B */
+    #define CY_PSOC4_4100BL (0u != 0u)
+    #define CY_PSOC4_4200BL (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_4F */
 
 
 /*******************************************************************************
-* UDB revisions
+* IP blocks
 *******************************************************************************/
-#define CY_UDB_V0 (CY_PSOC5A)
-#define CY_UDB_V1 (!CY_UDB_V0)
+#if (CY_PSOC4)
+
+    /* Using SRSSv2 or SRS-Lite */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_SRSSV2            (0u == 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #else
+        #define CY_IP_SRSSV2            (0u != 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (0u == 0u)
+    #else
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (!CY_IP_CPUSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Product uses FLASH-Lite or regular FLASH */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FMLT              (0u != 0u)          /* FLASH-Lite */
+        #define CY_IP_FM                (!CY_IP_FMLT)       /* Regular FLASH */
+    #else
+        #define CY_IP_FMLT              (-1u != 0u)
+        #define CY_IP_FM                (!CY_IP_FMLT)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of interrupt request inputs to CM0 */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_INT_NR            (32u)
+    #else
+        #define CY_IP_INT_NR            (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FLASH_MACROS      (1u)
+    #else
+        #define CY_IP_FLASH_MACROS      (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_BLESS             (0u != 0u)
+    #else
+        #define CY_IP_BLESS             (0u != 0u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Watch Crystal Oscillator (WCO) is present (32kHz) */
+    #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_WCO               (0u != 0u)
+    #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)
+        #define CY_IP_WCO               (0u == 0u)
+    #elif (CY_IP_SRSSV2)
+        #define CY_IP_WCO               (-1u)
+    #else
+        #define CY_IP_WCO               (0u != 0u)
+    #endif  /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* The components version defines. Available started from cy_boot 4.20
+* Use the following construction in order to identify cy_boot version:
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)
+*******************************************************************************/
+#define CY_BOOT_4_20            (420u)
+#define CY_BOOT_VERSION         (CY_BOOT_4_20)
 
 
 /*******************************************************************************
@@ -104,7 +174,7 @@ typedef          float  float32;
 
 #endif  /* (!CY_PSOC3) */
 
-/* Signed or unsigned depending on the compiler selection */
+/* Signed or unsigned depending on compiler selection */
 typedef          char   char8;
 
 
@@ -154,7 +224,7 @@ typedef          char   char8;
 
 #else
 
-    /* Prototype for function to set a 24-bit register. Located at cyutils.c */
+    /* Prototype for function to set 24-bit register. Located at cyutils.c */
     extern void     CySetReg24(uint32 volatile * addr, uint32 value);
 
     #if(CY_PSOC4)
@@ -204,18 +274,39 @@ typedef          char   char8;
     #define XDATA
 
     #if defined(__ARMCC_VERSION)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit"), zero_init))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
+
+        /* Specifies a minimum alignment (in bytes) for variables of the
+        *  specified type.
+        */
         #define CY_ALIGN(align)     __align(align)
+
+
+        /* Attached to an enum, struct, or union type definition, specified that
+        *  the minimum required memory be used to represent the type.
+        */
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           __inline
     #elif defined (__GNUC__)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit")))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
         #define CY_ALIGN(align)     __attribute__ ((aligned(align)))
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           inline
     #elif defined (__ICCARM__)
+
         #define CY_NOINIT           __no_init
         #define CY_NORETURN         __noreturn
+        #define CY_PACKED           __packed
+        #define CY_PACKED_ATTR
+        #define CY_INLINE           inline
     #endif  /* (__ARMCC_VERSION) */
 
 #endif  /* (CY_PSOC3) */
@@ -223,12 +314,12 @@ typedef          char   char8;
 
 #if(CY_PSOC3)
 
-    /* 8051 naturally returns an 8 bit value. */
+    /* 8051 naturally returns 8 bit value. */
     typedef unsigned char cystatus;
 
 #else
 
-    /* ARM naturally returns a 32 bit value. */
+    /* ARM naturally returns 32 bit value. */
     typedef unsigned long cystatus;
 
 #endif  /* (CY_PSOC3) */
@@ -274,7 +365,7 @@ typedef volatile uint32 CYXDATA reg32;
     * KEIL for the 8051 is a big endian compiler This causes problems as the on chip
     * registers are little endian.  Byte swapping for two and four byte registers is
     * implemented in the functions below.  This will require conditional compilation
-    * of function prototypes in code.
+    * of function prototypes in the code.
     *******************************************************************************/
 
     /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
@@ -347,24 +438,24 @@ typedef volatile uint32 CYXDATA reg32;
 *  Data manipulation defines
 *******************************************************************************/
 
-/* Get 8 bits of a 16 bit value. */
+/* Get 8 bits of 16 bit value. */
 #define LO8(x)                  ((uint8) ((x) & 0xFFu))
 #define HI8(x)                  ((uint8) ((uint16)(x) >> 8))
 
-/* Get 16 bits of a 32 bit value. */
+/* Get 16 bits of 32 bit value. */
 #define LO16(x)                 ((uint16) ((x) & 0xFFFFu))
 #define HI16(x)                 ((uint16) ((uint32)(x) >> 16))
 
-/* Swap the byte ordering of a 32 bit value */
+/* Swap the byte ordering of 32 bit value */
 #define CYSWAP_ENDIAN32(x)  \
         ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))
 
-/* Swap the byte ordering of a 16 bit value */
+/* Swap the byte ordering of 16 bit value */
 #define CYSWAP_ENDIAN16(x)      ((uint16)(((x) << 8) | ((x) >> 8)))
 
 
 /*******************************************************************************
-* Defines the standard return values used PSoC content. A function is
+* Defines the standard return values used in PSoC content. A function is
 * not limited to these return values but can use them when returning standard
 * error values. Return values can be overloaded if documented in the function
 * header. On the 8051 a function can use a larger return type but still use the
@@ -413,24 +504,55 @@ typedef volatile uint32 CYXDATA reg32;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+#define CY_UDB_V0           (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#define CY_UDB_V1           (!CY_UDB_V0)
+#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#else
+    #define CY_PSOC4D   (0u != 0u)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#endif  /* CYDEV_CHIP_MEMBER_4D */
+#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#ifdef CYDEV_CHIP_MEMBER_5B
+    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#else
+    #define CY_PSOC5LP  (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_5B */
+
+#if (!CY_PSOC4)
+
+    /* Device is PSoC 3 and the revision is ES2 or earlier */
+    #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
 
-/* Device is PSoC 3 and the revision is ES2 or earlier */
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
+    /* Device is PSoC 3 and the revision is ES3 or later */
+    #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
 
-/* Device is PSoC 3 and the revision is ES3 or later */
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
+    /* Device is PSoC 5 and the revision is ES1 or earlier */
+    #define CY_PSOC5_ES1 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES1 or earlier */
-#define CY_PSOC5_ES1 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
+    /* Device is PSoC 5 and the revision is ES2 or later */
+    #define CY_PSOC5_ES2 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES2 or later */
-#define CY_PSOC5_ES2 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
+#endif  /* (!CY_PSOC4) */
 
 #endif  /* CY_BOOT_CYTYPES_H */
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
index 6d42579a..dcfe346e 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * FILENAME: cyutils.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   CyUtils provides function to handle 24-bit value writes.
+*   CyUtils provides a function to handle 24-bit value writes.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,11 +21,11 @@
     ****************************************************************************
     *
     * Summary:
-    *  Writes the 24-bit value to the specified register.
+    *  Writes a 24-bit value to the specified register.
     *
     * Parameters:
-    *  addr : adress where data must be written
-    *  value: data that must be written
+    *  addr : the address where data must be written.
+    *  value: the data that must be written.
     *
     * Return:
     *  None
@@ -56,7 +56,7 @@
         *  Reads the 24-bit value from the specified register.
         *
         * Parameters:
-        *  addr : adress where data must be read
+        *  addr : the address where data must be read.
         *
         * Return:
         *  None
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
index 44d99933..758b561c 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
  * File Name: project.h
- * PSoC Creator 3.0 Component Pack 7
+ * PSoC Creator  3.1
  *
  *  Description:
  *  This file is automatically generated by PSoC Creator and should not 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c
index b4c30ae2..81727948 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: timer_clock.c
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   This file provides the source code to the API for the clock component.
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h
index 6690d480..7fbbb4cc 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: timer_clock.h
-* Version 2.10
+* Version 2.20
 *
 *  Description:
 *   Provides the function and constant definitions for the clock component.
@@ -28,7 +28,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+    #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
index d63a6c6e..5cdfca1e 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
@@ -18,7 +18,7 @@
       <Tool Name="postbuild" Command="" Options="" />
     </Toolchain>
   </Toolchains>
-  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
+  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
     <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
     <Datasheet />
     <LinkerFiles>
@@ -27,8 +27,8 @@
       <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
     </LinkerFiles>
     <Folders>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\src">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\src">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
@@ -60,19 +60,19 @@
           <File BuildType="BUILD" Toolchain="">..\..\src\cdrom.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">.\device.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\include">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\include">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">..\..\..\include\scsi2sd.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\..\include\hidpacket.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
@@ -217,41 +217,41 @@
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
         </Files>
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\codegentemp">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\DP8051">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\CortexM0">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\CortexM3">
-        <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-cache\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
     </Folders>
   </Project>
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
index 6b7b5a02..082e13f0 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
@@ -7,10 +7,10 @@
   <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />
   </block>
   <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
+    <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />
   </block>
   <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
     <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -81,9 +81,9 @@
   <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" />
-    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">
+    <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006463" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_MASK_REG" address="0x40006483" bitWidth="8" desc="" />
+    <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006493" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -112,9 +112,9 @@
   </block>
   <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_Filtered_STATUS_REG" address="0x40006460" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_MASK_REG" address="0x40006480" bitWidth="8" desc="" />
-    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006490" bitWidth="8" desc="">
+    <register name="SCSI_Filtered_STATUS_REG" address="0x40006464" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_MASK_REG" address="0x40006484" bitWidth="8" desc="" />
+    <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="">
       <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
         <value name="ENABLED" value="1" desc="Enable counter" />
         <value name="DISABLED" value="0" desc="Disable counter" />
@@ -151,7 +151,7 @@
   <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
-    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
+    <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
   </block>
   <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
@@ -164,19 +164,35 @@
     <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   </block>
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
-    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
@@ -209,7 +225,7 @@
     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
-      <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />
+      <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
     </register>
     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr
index 496f18d5..805706bb 100755
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr differ
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
index efc74839..1dbc822a 100644
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
index 5bdf1f94..15c22fe2 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -259,6 +259,13 @@
 <build_action v="NONE" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="debug.h" persistent="..\..\src\debug.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -2326,14 +2333,14 @@
 <GlobalPages />
 <GlobalTools name="Code Generation">
 <GlobalPages>
+<name_val_pair name="General@Application Type" v="Bootloadable" />
+<name_val_pair name="General@Custom Code Gen Options" v="" />
+<name_val_pair name="General@Skip Code Generation" v="False" />
+<name_val_pair name="General@Custom Synthesis Options" v="" />
+<name_val_pair name="General@Quiet Output" v="True" />
 <name_val_pair name="General@Synthesis Goal" v="Speed" />
 <name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />
-<name_val_pair name="General@Quiet Output" v="True" />
-<name_val_pair name="General@Custom Synthesis Options" v="" />
-<name_val_pair name="General@Skip Code Generation" v="False" />
-<name_val_pair name="General@Custom Code Gen Options" v="" />
 <name_val_pair name="General@Virtual Node Substitution" v="3" />
-<name_val_pair name="General@Application Type" v="Bootloadable" />
 <name_val_pair name="General@Custom Fitter Options" v="" />
 </GlobalPages>
 </GlobalTools>
@@ -2344,9 +2351,9 @@
 </GlobalTools>
 <GlobalTools name="Customizer">
 <GlobalPages>
-<name_val_pair name="General@Customizer Build Mode" v="Release" />
-<name_val_pair name="General@Command Line Options" v="" />
 <name_val_pair name="General@Assembly References" v="" />
+<name_val_pair name="General@Command Line Options" v="" />
+<name_val_pair name="General@Customizer Build Mode" v="Release" />
 </GlobalPages>
 </GlobalTools>
 </name>
@@ -2354,465 +2361,498 @@
 <platform>
 <name v="c9323d49-d323-40b8-9b59-cc008d68a989">
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
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 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
 <name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+</name>
+</platform>
+<platform>
+<name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M&lt;&gt; -w+ -r -DNDEBUG --fpu None" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --vfe" />
 </name>
 </platform>
 </platforms>
@@ -2821,18 +2861,9 @@
 <component_generation v="PSoC Creator  2.2 Component Pack 6" />
 <last_selected_tab v="Cypress" />
 <component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
-<WriteAppVersionLastSavedWith v="3.0.0.1539" />
-<WriteAppMarketingVersionLastSavedWith v=" 3.0 Component Pack 7" />
-<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />
-<custom_data>
-<CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">
-<CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2">
-<userData />
-</CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997>
-<properties />
-</CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111>
-</custom_data>
-</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
+<WriteAppVersionLastSavedWith v="3.1.0.1570" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
 </CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
 <top_block v="TopDesign" />
 <selected_device v="CY8C5267AXI-LP051" />
@@ -2844,8 +2875,8 @@
 <CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
 <ignored_deps />
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
-<boot_component v="cy_boot_v4_0" />
+<boot_component v="cy_boot_v4_20" />
 <BootloaderTag hexFile="" elfFile="" />
 <current_generation v="2" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
-</CyXmlSerializer>
+</CyXmlSerializer>
\ No newline at end of file
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
index 06915cfa..7066aba9 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
@@ -9,10 +9,10 @@
     <peripheral>
       <name>SCSI_Out_Ctl</name>
       <description>No description available</description>
-      <baseAddress>0x40006473</baseAddress>
+      <baseAddress>0x4000647E</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -30,10 +30,10 @@
     <peripheral>
       <name>SCSI_Out_Bits</name>
       <description>No description available</description>
-      <baseAddress>0x40006474</baseAddress>
+      <baseAddress>0x4000647F</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -51,17 +51,17 @@
     <peripheral>
       <name>Debug_Timer</name>
       <description>No description available</description>
-      <baseAddress>0x400043A3</baseAddress>
+      <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0xB64</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
         <register>
           <name>Debug_Timer_GLOBAL_ENABLE</name>
           <description>PM.ACT.CFG</description>
-          <addressOffset>0x0</addressOffset>
+          <addressOffset>0x400043A3</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -79,7 +79,7 @@
         <register>
           <name>Debug_Timer_CONTROL</name>
           <description>TMRx.CFG0</description>
-          <addressOffset>0xB5D</addressOffset>
+          <addressOffset>0x40004F00</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -163,7 +163,7 @@
         <register>
           <name>Debug_Timer_CONTROL2</name>
           <description>TMRx.CFG1</description>
-          <addressOffset>0xB5E</addressOffset>
+          <addressOffset>0x40004F01</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -228,7 +228,7 @@
         <register>
           <name>Debug_Timer_CONTROL3_</name>
           <description>TMRx.CFG2</description>
-          <addressOffset>0xB5F</addressOffset>
+          <addressOffset>0x40004F02</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -323,7 +323,7 @@
         <register>
           <name>Debug_Timer_PERIOD</name>
           <description>TMRx.PER0 - Assigned Period</description>
-          <addressOffset>0xB61</addressOffset>
+          <addressOffset>0x40004F04</addressOffset>
           <size>16</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -332,7 +332,7 @@
         <register>
           <name>Debug_Timer_COUNTER</name>
           <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
-          <addressOffset>0xB63</addressOffset>
+          <addressOffset>0x40004F06</addressOffset>
           <size>16</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -343,10 +343,10 @@
     <peripheral>
       <name>SCSI_Parity_Error</name>
       <description>No description available</description>
-      <baseAddress>0x40006465</baseAddress>
+      <baseAddress>0x40006463</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x31</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -498,10 +498,10 @@
     <peripheral>
       <name>SCSI_Filtered</name>
       <description>No description available</description>
-      <baseAddress>0x40006460</baseAddress>
+      <baseAddress>0x40006464</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x31</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -653,10 +653,10 @@
     <peripheral>
       <name>SCSI_CTL_PHASE</name>
       <description>No description available</description>
-      <baseAddress>0x40006471</baseAddress>
+      <baseAddress>0x4000647C</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
@@ -674,17 +674,17 @@
     <peripheral>
       <name>USBFS</name>
       <description>USBFS</description>
-      <baseAddress>0x40004394</baseAddress>
+      <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1D0A</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
         <register>
           <name>USBFS_PM_USB_CR0</name>
           <description>USB Power Mode Control Register 0</description>
-          <addressOffset>0x0</addressOffset>
+          <addressOffset>0x40004394</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -716,7 +716,7 @@
         <register>
           <name>USBFS_PM_ACT_CFG</name>
           <description>Active Power Mode Configuration Register</description>
-          <addressOffset>0x11</addressOffset>
+          <addressOffset>0x400043A5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -725,7 +725,7 @@
         <register>
           <name>USBFS_PM_STBY_CFG</name>
           <description>Standby Power Mode Configuration Register</description>
-          <addressOffset>0x21</addressOffset>
+          <addressOffset>0x400043B5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -734,7 +734,7 @@
         <register>
           <name>USBFS_PRT_PS</name>
           <description>Port Pin State Register</description>
-          <addressOffset>0xE5D</addressOffset>
+          <addressOffset>0x400051F1</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -759,7 +759,7 @@
         <register>
           <name>USBFS_PRT_DM0</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5E</addressOffset>
+          <addressOffset>0x400051F2</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -784,7 +784,7 @@
         <register>
           <name>USBFS_PRT_DM1</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5F</addressOffset>
+          <addressOffset>0x400051F3</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -809,7 +809,7 @@
         <register>
           <name>USBFS_PRT_INP_DIS</name>
           <description>Input buffer disable override</description>
-          <addressOffset>0xE64</addressOffset>
+          <addressOffset>0x400051F8</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -834,7 +834,7 @@
         <register>
           <name>USBFS_EP0_DR0</name>
           <description>bmRequestType</description>
-          <addressOffset>0x1C6C</addressOffset>
+          <addressOffset>0x40006000</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -843,7 +843,7 @@
         <register>
           <name>USBFS_EP0_DR1</name>
           <description>bRequest</description>
-          <addressOffset>0x1C6D</addressOffset>
+          <addressOffset>0x40006001</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -852,7 +852,7 @@
         <register>
           <name>USBFS_EP0_DR2</name>
           <description>wValueLo</description>
-          <addressOffset>0x1C6E</addressOffset>
+          <addressOffset>0x40006002</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -861,7 +861,7 @@
         <register>
           <name>USBFS_EP0_DR3</name>
           <description>wValueHi</description>
-          <addressOffset>0x1C6F</addressOffset>
+          <addressOffset>0x40006003</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -870,7 +870,7 @@
         <register>
           <name>USBFS_EP0_DR4</name>
           <description>wIndexLo</description>
-          <addressOffset>0x1C70</addressOffset>
+          <addressOffset>0x40006004</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -879,7 +879,7 @@
         <register>
           <name>USBFS_EP0_DR5</name>
           <description>wIndexHi</description>
-          <addressOffset>0x1C71</addressOffset>
+          <addressOffset>0x40006005</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -888,7 +888,7 @@
         <register>
           <name>USBFS_EP0_DR6</name>
           <description>lengthLo</description>
-          <addressOffset>0x1C72</addressOffset>
+          <addressOffset>0x40006006</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -897,7 +897,7 @@
         <register>
           <name>USBFS_EP0_DR7</name>
           <description>lengthHi</description>
-          <addressOffset>0x1C73</addressOffset>
+          <addressOffset>0x40006007</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -906,7 +906,7 @@
         <register>
           <name>USBFS_CR0</name>
           <description>USB Control Register 0</description>
-          <addressOffset>0x1C74</addressOffset>
+          <addressOffset>0x40006008</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -915,8 +915,8 @@
             <field>
               <name>device_address</name>
               <description>No description available</description>
-              <lsb>6</lsb>
-              <msb>0</msb>
+              <lsb>0</lsb>
+              <msb>6</msb>
               <access>read-only</access>
             </field>
             <field>
@@ -931,7 +931,7 @@
         <register>
           <name>USBFS_CR1</name>
           <description>USB Control Register 1</description>
-          <addressOffset>0x1C75</addressOffset>
+          <addressOffset>0x40006009</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -970,7 +970,7 @@
         <register>
           <name>USBFS_SIE_EP1_CR0</name>
           <description>The Endpoint1 Control Register</description>
-          <addressOffset>0x1C7A</addressOffset>
+          <addressOffset>0x4000600E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -979,7 +979,7 @@
         <register>
           <name>USBFS_USBIO_CR0</name>
           <description>USBIO Control Register 0</description>
-          <addressOffset>0x1C7C</addressOffset>
+          <addressOffset>0x40006010</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1018,7 +1018,7 @@
         <register>
           <name>USBFS_USBIO_CR1</name>
           <description>USBIO Control Register 1</description>
-          <addressOffset>0x1C7E</addressOffset>
+          <addressOffset>0x40006012</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1057,7 +1057,7 @@
         <register>
           <name>USBFS_SIE_EP2_CR0</name>
           <description>The Endpoint2 Control Register</description>
-          <addressOffset>0x1C8A</addressOffset>
+          <addressOffset>0x4000601E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1066,7 +1066,7 @@
         <register>
           <name>USBFS_SIE_EP3_CR0</name>
           <description>The Endpoint3 Control Register</description>
-          <addressOffset>0x1C9A</addressOffset>
+          <addressOffset>0x4000602E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1075,7 +1075,7 @@
         <register>
           <name>USBFS_SIE_EP4_CR0</name>
           <description>The Endpoint4 Control Register</description>
-          <addressOffset>0x1CAA</addressOffset>
+          <addressOffset>0x4000603E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1084,7 +1084,7 @@
         <register>
           <name>USBFS_SIE_EP5_CR0</name>
           <description>The Endpoint5 Control Register</description>
-          <addressOffset>0x1CBA</addressOffset>
+          <addressOffset>0x4000604E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1093,7 +1093,7 @@
         <register>
           <name>USBFS_SIE_EP6_CR0</name>
           <description>The Endpoint6 Control Register</description>
-          <addressOffset>0x1CCA</addressOffset>
+          <addressOffset>0x4000605E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1102,7 +1102,7 @@
         <register>
           <name>USBFS_SIE_EP7_CR0</name>
           <description>The Endpoint7 Control Register</description>
-          <addressOffset>0x1CDA</addressOffset>
+          <addressOffset>0x4000606E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1111,7 +1111,7 @@
         <register>
           <name>USBFS_SIE_EP8_CR0</name>
           <description>The Endpoint8 Control Register</description>
-          <addressOffset>0x1CEA</addressOffset>
+          <addressOffset>0x4000607E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1120,7 +1120,7 @@
         <register>
           <name>USBFS_BUF_SIZE</name>
           <description>Dedicated Endpoint Buffer Size Register</description>
-          <addressOffset>0x1CF8</addressOffset>
+          <addressOffset>0x4000608C</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1129,7 +1129,7 @@
         <register>
           <name>USBFS_EP_ACTIVE</name>
           <description>Endpoint Active Indication Register</description>
-          <addressOffset>0x1CFA</addressOffset>
+          <addressOffset>0x4000608E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1138,7 +1138,7 @@
         <register>
           <name>USBFS_EP_TYPE</name>
           <description>Endpoint Type (IN/OUT) Indication</description>
-          <addressOffset>0x1CFB</addressOffset>
+          <addressOffset>0x4000608F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -1147,7 +1147,7 @@
         <register>
           <name>USBFS_USB_CLK_EN</name>
           <description>USB Block Clock Enable Register</description>
-          <addressOffset>0x1D09</addressOffset>
+          <addressOffset>0x4000609D</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
index f9d8dc13..a69b5535 100755
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c
index 3f24c96e..a013f3f7 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: BL.c
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloader component. The API includes functions
@@ -8,7 +8,7 @@
 *   jumping to the application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -24,22 +24,26 @@
 * The Checksum and SizeBytes are forcefully set in code. We then post process
 * the hex file from the linker and inject their values then. When the hex file
 * is loaded onto the device these two variables should have valid values.
-* Because the compiler can do optimizations remove the constant
+* Because the compiler can do optimizations to remove the constant
 * accesses, these should not be accessed directly. Instead, the variables
 * CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the
 * proper values at runtime.
 *******************************************************************************/
 #if defined(__ARMCC_VERSION) || defined (__GNUC__)
-    __attribute__((section (".bootloader")))
+    __attribute__((section (".bootloader"), used))
 #elif defined (__ICCARM__)
     #pragma location=".bootloader"
 #endif  /* defined(__ARMCC_VERSION) || defined (__GNUC__) */
 
-const uint8  CYCODE BL_Checksum = 0u;
+#if defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__)
+           const uint8  CYCODE BL_Checksum = 0u;
+#elif defined (__ICCARM__)
+    __root const uint8  CYCODE BL_Checksum = 0u;
+#endif  /* defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__) */
 const uint8  CYCODE *BL_ChecksumAccess  = (const uint8  CYCODE *)(&BL_Checksum);
 
 #if defined(__ARMCC_VERSION) || defined (__GNUC__)
-    __attribute__((section (".bootloader")))
+    __attribute__((section (".bootloader"), used))
 #elif defined (__ICCARM__)
     #pragma location=".bootloader"
 #endif  /* defined(__ARMCC_VERSION) || defined (__GNUC__) */
@@ -64,25 +68,12 @@ static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMAL
 static uint16   BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \
                                     ;
 
-static uint8    BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \
-                                    ;
-#if(!CY_PSOC4)
-static uint8    BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \
-                                    ;
-#endif /* (!CY_PSOC4) */
-
 static void     BL_HostLink(uint8 timeOut) \
                                     ;
 
 static void     BL_LaunchApplication(void) CYSMALL \
                                     ;
 
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
-                                    ;
-
-static uint32   BL_GetMetadata(uint8 fieldName, uint8 appId)\
-                                    ;
-
 #if(!CY_PSOC3)
     /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file.  */
     static void     BL_LaunchBootloadable(uint32 appAddr);
@@ -101,7 +92,7 @@ static uint32   BL_GetMetadata(uint8 fieldName, uint8 appId)\
 *  buffer:
 *     The buffer containing the data to compute the checksum for
 *  size:
-*     The number of bytes in buffer to compute the checksum for
+*     The number of bytes in the buffer to compute the checksum for
 *
 * Returns:
 *  16 bit checksum for the provided data
@@ -169,14 +160,19 @@ static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \
 
 
 /*******************************************************************************
-* Function Name: BL_Calc8BitFlashSum
+* Function Name: BL_Calc8BitSum
 ********************************************************************************
 *
 * Summary:
 *  This computes the 8 bit sum for the provided number of bytes contained in
-*  flash.
+*  FLASH (if baseAddr equals CY_FLASH_BASE) or EEPROM (if baseAddr equals
+*  CY_EEPROM_BASE).
 *
 * Parameters:
+* baseAddr:
+*   CY_FLASH_BASE
+*   CY_EEPROM_BASE - applicable only for PSoC 3 / PSoC 5LP devices.
+*
 *  start:
 *     The starting address to start summing data for
 *  size:
@@ -186,87 +182,62 @@ static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \
 *   8 bit sum for the provided data
 *
 *******************************************************************************/
-static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) \
                 CYSMALL 
 {
     uint8 CYDATA sum = 0u;
 
+    #if(!CY_PSOC4)
+        CYASSERT((baseAddr == CY_EEPROM_BASE) || (baseAddr == CY_FLASH_BASE));
+    #else
+        CYASSERT(baseAddr == CY_FLASH_BASE);
+    #endif  /* (!CY_PSOC4) */
+
     while (size > 0u)
     {
         size--;
-        sum += BL_GET_CODE_BYTE(start + size);
+        sum += (*((uint8  *)(baseAddr + start + size)));
     }
 
     return(sum);
 }
 
 
-#if(!CY_PSOC4)
-
-    /*******************************************************************************
-    * Function Name: BL_Calc8BitEepromSum
-    ********************************************************************************
-    *
-    * Summary:
-    *  This computes the 8 bit sum for the provided number of bytes contained in
-    *  EEPROM.
-    *
-    * Parameters:
-    *  start:
-    *     The starting address to start summing data for
-    *  size:
-    *     The number of bytes to read and compute the sum for
-    *
-    * Returns:
-    *   8 bit sum for the provided data
-    *
-    *******************************************************************************/
-    static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \
-                    CYSMALL 
-    {
-        uint8 CYDATA sum = 0u;
-
-        while (size > 0u)
-        {
-            size--;
-            sum += BL_GET_EEPROM_BYTE(start + size);
-        }
-
-        return(sum);
-    }
-
-#endif  /* (!CY_PSOC4) */
-
-
 /*******************************************************************************
 * Function Name: BL_Start
 ********************************************************************************
 * Summary:
-*  This function is called in order executing following algorithm:
+*  This function is called in order to execute the following algorithm:
 *
-*  - Identify active bootloadable application (applicable only to
-*    Multi-application bootloader)
+*  - Identify the active bootloadable application (applicable only to
+*    the Multi-application bootloader)
 *
-*  - Validate bootloader application (desing-time configurable, Bootloader
+*  - Validate the bootloader application (design-time configurable, Bootloader
 *    application validation option of the component customizer)
 *
-*  - Validate active bootloadable application
+*  - Validate the active bootloadable application. If active bootloadable
+*    application is not valid, and the other bootloadable application (inactive)
+*    is valid, the last one is started.
 *
-*  - Run communication subroutine (desing-time configurable, Wait for command
+*  - Run a communication subroutine (design-time configurable, Wait for command
 *    option of the component customizer)
 *
-*  - Schedule bootloadable and reset device
+*  - Schedule the bootloadable and reset the device
 *
 * Parameters:
 *  None
 *
 * Return:
 *  This method will never return. It will either load a new application and
-*  reset the device or it will jump directly to the existing application.
+*  reset the device or jump directly to the existing application. The CPU is
+*  halted, if validation failed when "Bootloader application validation" option
+*  is enabled.
+*  PSoC 3/PSoC 5: The CPU is halted if Flash initialization fails.
 *
 * Side Effects:
-*  If this method determines that the bootloader appliation itself is corrupt,
-*  this method will not return, instead it will simply hang the application.
+*  If Bootloader application validation option is enabled and this method
+*  determines that the bootloader application itself is corrupt, this method
+*  will not return, instead it will simply hang the application.
 *
 *******************************************************************************/
 void BL_Start(void) CYSMALL 
@@ -276,60 +247,149 @@ void BL_Start(void) CYSMALL
     #endif    /* (0u != BL_BOOTLOADER_APP_VALIDATION) */
 
     #if(!CY_PSOC4)
-        uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+        #if(0u != BL_FAST_APP_VALIDATION)
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required starting from cy_boot 4.20 */
+                uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u != BL_FAST_APP_VALIDATION) */
     #endif  /* (!CY_PSOC4) */
 
-    cystatus tmpStatus;
+    cystatus validApp  = CYRET_BAD_DATA;
 
 
     /* Identify active bootloadable application */
     #if(0u != BL_DUAL_APP_BOOTLOADER)
 
-        if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE)
+        /* Assumes no active bootloadable application. Bootloader is active. */
+        BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;
+
+        /* Bootloadable # A is active */
+        if(BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 0u) == BL_MD_BTLDB_IS_ACTIVE)
         {
-            BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+            /*******************************************************************
+            * -----------------------------------------------------------
+            * |      | Bootloadable A | Bootloadable B |                |
+            * | Case |---------------------------------|     Action     |
+            * |      | Active | Valid | Active | Valid |                |
+            * |------|--------------------------------------------------|
+            * |  9   |    1   |   0   |   0    |   0   | Bootloader     |
+            * |  10  |    1   |   0   |   0    |   1   | Bootloadable B |
+            * |  11  |    1   |   0   |   1    |   0   | Bootloader     |
+            * |  12  |    1   |   0   |   1    |   1   | Bootloadable B |
+            * |  13  |    1   |   1   |   0    |   0   | Bootloadable A |
+            * |  14  |    1   |   1   |   0    |   1   | Bootloadable A |
+            * |  15  |    1   |   1   |   1    |   0   | Bootloadable A |
+            * |  16  |    1   |   1   |   1    |   1   | Bootloadable A |
+            * -----------------------------------------------------------
+            *******************************************************************/
+            if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
+            {
+                /* Cases # 13,  14, 15, and 16 */
+                BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+                validApp = CYRET_SUCCESS;
+            }
+            else
+            {
+                if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))
+                {
+                    /* Cases # 10 and 12 */
+                    BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+                    validApp = CYRET_SUCCESS;
+                }
+            }
         }
-        else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE)
+
+        /*  Active bootloadable application is not identified */
+        if(BL_activeApp == BL_MD_BTLDB_ACTIVE_NONE)
         {
-            BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+            /*******************************************************************
+            * -----------------------------------------------------------
+            * |      | Bootloadable A | Bootloadable B |                |
+            * | Case |---------------------------------|     Action     |
+            * |      | Active | Valid | Active | Valid |                |
+            * |------|--------------------------------------------------|
+            * |  1   |    0   |   0   |   0    |   0   | Bootloader     |
+            * |  2   |    0   |   0   |   0    |   1   | Bootloader     |
+            * |  3   |    0   |   0   |   1    |   0   | Bootloader     |
+            * |  4   |    0   |   0   |   1    |   1   | Bootloadable B |
+            * |  5   |    0   |   1   |   0    |   0   | Bootloader     |
+            * |  6   |    0   |   1   |   0    |   1   | Bootloader     |
+            * |  7   |    0   |   1   |   1    |   0   | Bootloadable A |
+            * |  8   |    0   |   1   |   1    |   1   | Bootloadable B |
+            * -----------------------------------------------------------
+            *******************************************************************/
+            if (BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 1u) ==
+                    BL_MD_BTLDB_IS_ACTIVE)
+            {
+                /* Cases # 3, 4, 7, and 8 */
+                if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))
+                {
+                    /* Cases # 4 and 8 */
+                    BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+                    validApp = CYRET_SUCCESS;
+                }
+                else
+                {
+                    if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
+                    {
+                        /* Cases # 7 */
+                        BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+                        validApp = CYRET_SUCCESS;
+                    }
+                }
+            }
         }
-        else
+    #else
+        if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
         {
-            BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;
+            validApp = CYRET_SUCCESS;
         }
-
     #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
 
 
     /* Initialize Flash subsystem for non-PSoC 4 devices */
     #if(!CY_PSOC4)
-        if (CYRET_SUCCESS != CySetTemp())
-        {
-            CyHalt(0x00u);
-        }
+        #if(0u != BL_FAST_APP_VALIDATION)
 
-        if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
-        {
-            CyHalt(0x00u);
-        }
+            if (CYRET_SUCCESS != CySetTemp())
+            {
+                CyHalt(0x00u);
+            }
+
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required with cy_boot 4.20 */
+                if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
+                {
+                    CyHalt(0x00u);
+                }
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u != BL_FAST_APP_VALIDATION) */
     #endif  /* (CY_PSOC4) */
 
 
     /***********************************************************************
     * Bootloader Application Validation
     *
-    * Halt device if:
-    *  - Calculated checksum does not much one stored in metadata section
-    *  - Invalid pointer to the place where bootloader application ends
-    *  - Flash subsystem where not initialized correctly
+    * Halt the device if:
+    *  - A calculated checksum does not match the one stored in the metadata
+    *     section.
+    *  - There is an invalid pointer to the place where the bootloader
+    *    application ends.
+    *  - Flash subsystem was not initialized correctly
     ***********************************************************************/
     #if(0u != BL_BOOTLOADER_APP_VALIDATION)
 
         /* Calculate Bootloader application checksum */
-        calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR,
+        calcedChecksum = BL_Calc8BitSum(CY_FLASH_BASE,
+                BL_MD_BTLDR_ADDR_PTR,
                 *BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR);
 
-        /* we actually included the checksum, so remove it */
+        /* we included checksum, so remove it */
         calcedChecksum -= *BL_ChecksumAccess;
         calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);
 
@@ -344,17 +404,14 @@ void BL_Start(void) CYSMALL
 
 
     /***********************************************************************
-    * Active Bootloadable Application Validation
-    *
-    * If active bootloadable application is invalid or bootloader
+    * If the active bootloadable application is invalid or a bootloader
     * application is scheduled - do the following:
-    *  - schedule bootloader application to be run after software reset
-    *  - Go to the communication subroutine. Will wait for commands forever
+    *  - schedule the bootloader application to be run after software reset
+    *  - Go to the communication subroutine. The HostLink() will wait for
+    *    the commands forever.
     ***********************************************************************/
-    tmpStatus = BL_ValidateBootloadable(BL_activeApp);
-
     if ((BL_GET_RUN_TYPE == BL_START_BTLDR) ||
-        (CYRET_SUCCESS != tmpStatus))
+        (CYRET_SUCCESS != validApp))
     {
         BL_SET_RUN_TYPE(0u);
 
@@ -362,10 +419,10 @@ void BL_Start(void) CYSMALL
     }
 
 
-    /* Go to the communication subroutine. Will wait for commands specifed time */
+    /* Go to communication subroutine. Will wait for commands for specifed time */
     #if(0u != BL_WAIT_FOR_COMMAND)
 
-        /* Timeout is in 100s of miliseconds */
+        /* Timeout is in 100s of milliseconds */
         BL_HostLink(BL_WAIT_FOR_COMMAND_TIME);
 
     #endif  /* (0u != BL_WAIT_FOR_COMMAND) */
@@ -381,13 +438,13 @@ void BL_Start(void) CYSMALL
 ********************************************************************************
 *
 * Summary:
-*  Jumps the PC to the start address of the user application in flash.
+*  Schedules bootloadable application and resets device
 *
 * Parameters:
 *  None
 *
 * Returns:
-*  This method will never return if it succesfully goes to the user application.
+*  This method will never return.
 *
 *******************************************************************************/
 static void BL_LaunchApplication(void) CYSMALL 
@@ -399,21 +456,83 @@ static void BL_LaunchApplication(void) CYSMALL
 }
 
 
+/*******************************************************************************
+* Function Name: BL_Exit
+********************************************************************************
+*
+* Summary:
+*  Schedules the specified application and performs software reset to launch
+*  a specified application.
+*
+*  If the specified application is not valid, the Bootloader (the result of the
+*  ValidateBootloadable() function execution returns other than CYRET_SUCCESS,
+*  the bootloader application is launched.
+*
+* Parameters:
+*  appId: application to be started:
+*  BL_EXIT_TO_BTLDR   - Bootloader application will be started on
+*                                     software reset.
+*  BL_EXIT_TO_BTLDB,
+*  BL_EXIT_TO_BTLDB_1 - Bootloadable application # 1 will be
+*                                     started on software reset.
+*  BL_EXIT_TO_BTLDB_2 - Bootloadable application # 2 will be
+*                                     started on software reset. Available only
+*                                     if Multi-Application option is enabled in
+*                                     the component customizer.
+* Returns:
+*  This function never returns.
+*
+*******************************************************************************/
+void BL_Exit(uint8 appId) CYSMALL 
+{
+    if(BL_EXIT_TO_BTLDR == appId)
+    {
+        BL_SET_RUN_TYPE(0x0u);
+    }
+    else
+    {
+        if(CYRET_SUCCESS == BL_ValidateBootloadable(appId))
+        {
+            /* Set active application in metadata */
+            uint8 CYDATA idx;
+            for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++)
+            {
+                BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx),
+                                              (uint8 )(idx == appId));
+            }
+
+        #if(0u != BL_DUAL_APP_BOOTLOADER)
+            BL_activeApp = appId;
+        #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+            BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);
+        }
+        else
+        {
+            BL_SET_RUN_TYPE(0u);
+        }
+    }
+
+    CySoftwareReset();
+}
+
+
 /*******************************************************************************
 * Function Name: CyBtldr_CheckLaunch
 ********************************************************************************
 *
 * Summary:
-*  This routine checks to see if the bootloader or the bootloadable application
-*  should be run.  If the application is to be run, it will start executing.
-*  If the bootloader is to be run, it will return so the bootloader can
+*  This routine checks if the bootloader or the bootloadable application has to
+*  be run.  If the application has to be run, it will start executing.
+*  If the bootloader is to be run, it will return, so the bootloader can
 *  continue starting up.
 *
 * Parameters:
 *  None
 *
 * Returns:
-*  None
+*  It will not return if it determines that the bootloadable application should
+*  be run.
 *
 *******************************************************************************/
 void CyBtldr_CheckLaunch(void) CYSMALL 
@@ -422,7 +541,7 @@ void CyBtldr_CheckLaunch(void) CYSMALL
 #if(CY_PSOC4)
 
     /*******************************************************************************
-    * Set cyBtldrRunType to zero in case of non-software reset occured. This means
+    * Set cyBtldrRunType to zero in case of non-software reset occurred. This means
     * that bootloader application is scheduled - that is initial clean state. The
     * value of cyBtldrRunType is valid only in case of software reset.
     *******************************************************************************/
@@ -444,17 +563,17 @@ void CyBtldr_CheckLaunch(void) CYSMALL
         * application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS
         * is something other than 0.
         *******************************************************************************/
-        if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp))
+        if(0u != BL_GetMetadata(BL_GET_BTLDB_ADDR, BL_activeApp))
         {
             /* Never return from this method */
-            BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR,
+            BL_LaunchBootloadable(BL_GetMetadata(BL_GET_BTLDB_ADDR,
                                                                              BL_activeApp));
         }
     }
 }
 
 
-/* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */
+/* Moves argument appAddr (RO) into PC, moving execution to appAddr */
 #if defined (__ARMCC_VERSION)
 
     __asm static void BL_LaunchBootloadable(uint32 appAddr)
@@ -486,25 +605,37 @@ void CyBtldr_CheckLaunch(void) CYSMALL
 * Function Name: BL_ValidateBootloadable
 ********************************************************************************
 * Summary:
-*  This routine computes the checksum, zero check, 0xFF check of the
-*  application area to determine whether a valid application is loaded.
+*  Performs the bootloadable application validation by calculating the
+*  application image checksum and comparing it with the checksum value stored
+*  in the Bootloadable Application Checksum field of the metadata section.
+*
+*  If the Fast bootloadable application validation option is enabled in the
+*  component customizer and bootloadable application successfully passes
+*  validation, the Bootloadable Application Verification Status field of the
+*  metadata section is updated. Refer to the Metadata Layout section for the
+*  details.
+*
+*  If the Fast bootloadable application validation option is enabled and
+*  Bootloadable Application Verification Status field of the metadata section
+*  claims that bootloadable application is valid, the function returns
+*  CYRET_SUCCESS without further checksum calculation.
 *
 * Parameters:
 *  appId:
-*      The application number to verify
+*  The number of the bootloadable application should be 0 for the normal
+*  bootloader and 0 or 1 for the Multi-Application bootloader.
 *
 * Returns:
-*  CYRET_SUCCESS  - if successful
-*  CYRET_BAD_DATA - if the bootloadable is corrupt
+*  Returns CYRET_SUCCESS if the specified bootloadable application is valid.
 *
 *******************************************************************************/
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
+cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 
     {
         uint32 CYDATA idx;
 
         uint32 CYDATA end   = BL_FIRST_APP_BYTE(appId) +
-                                BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH,
+                                BL_GetMetadata(BL_GET_BTLDB_LENGTH,
                                                        appId);
 
         CYBIT         valid = 0u; /* Assume bad flash image */
@@ -523,7 +654,9 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 
         #if(0u != BL_FAST_APP_VALIDATION)
 
-            if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED)
+
+            if(BL_GetMetadata(BL_GET_BTLDB_STATUS, appId) ==
+               BL_MD_BTLDB_IS_VERIFIED)
             {
                 return(CYRET_SUCCESS);
             }
@@ -557,7 +690,7 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
             /* Add ECC data to checksum */
             idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u);
 
-            /* Flash may run into meta data, ECC does not so use full row */
+            /* Flash may run into meta data, so ECC does not use full row */
             end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF))
                 ? (CY_FLASH_SIZE >> 3u)
                 : (end >> 3u);
@@ -572,7 +705,8 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 
         calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);
 
-        if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) ||
+
+        if((calcedChecksum != BL_GetMetadata(BL_GET_BTLDB_CHECKSUM, appId)) ||
            (0u == valid))
         {
             return(CYRET_BAD_DATA);
@@ -601,7 +735,7 @@ static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
 * Parameters:
 *  timeOut:
 *   The amount of time to listen for data before giving up. Timeout is
-*   measured in 10s of ms.  Use 0 for infinite wait.
+*   measured in 10s of ms.  Use 0 for an infinite wait.
 *
 * Return:
 *   None
@@ -618,9 +752,9 @@ static void BL_HostLink(uint8 timeOut)
     uint16    CYDATA dataOffset = 0u;
     uint8     CYDATA timeOutCnt = 10u;
 
-    #if(0u == BL_DUAL_APP_BOOTLOADER)
+    #if(0u != BL_FAST_APP_VALIDATION)
         uint8 CYDATA clearedMetaData = 0u;
-    #endif  /* (0u == BL_DUAL_APP_BOOTLOADER) */
+    #endif  /* (0u != BL_FAST_APP_VALIDATION) */
 
     CYBIT     communicationState = BL_COMMUNICATION_STATE_IDLE;
 
@@ -628,6 +762,40 @@ static void BL_HostLink(uint8 timeOut)
     uint8     dataBuffer  [BL_SIZEOF_COMMAND_BUFFER];
 
 
+    #if(!CY_PSOC4)
+        #if(0u == BL_FAST_APP_VALIDATION)
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required with cy_boot 4.20 */
+                uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u == BL_FAST_APP_VALIDATION) */
+    #endif  /* (CY_PSOC4) */
+
+
+
+    #if(!CY_PSOC4)
+        #if(0u == BL_FAST_APP_VALIDATION)
+
+            /* Initialize Flash subsystem for non-PSoC 4 devices */
+            if (CYRET_SUCCESS != CySetTemp())
+            {
+                CyHalt(0x00u);
+            }
+
+            #if !defined(CY_BOOT_VERSION)
+
+                /* Not required with cy_boot 4.20 */
+                if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
+                {
+                    CyHalt(0x00u);
+                }
+
+            #endif /* !defined(CY_BOOT_VERSION) */
+        #endif  /* (0u == BL_FAST_APP_VALIDATION) */
+    #endif  /* (CY_PSOC4) */
+
     /* Initialize communications channel. */
     CyBtldrCommStart();
 
@@ -716,10 +884,12 @@ static void BL_HostLink(uint8 timeOut)
                         {
                             #if(CY_PSOC3)
                                 (void) memcpy(&packetBuffer[BL_DATA_ADDR],
-                                            ((uint8  CYCODE *) (BL_META_BASE(btldrData))), 56);
+                                            ((uint8  CYCODE *) (BL_META_BASE(btldrData))),
+                                            BL_GET_METADATA_RESPONSE_SIZE);
                             #else
                                 (void) memcpy(&packetBuffer[BL_DATA_ADDR],
-                                            (uint8 *) BL_META_BASE(btldrData), 56u);
+                                            (uint8 *) BL_META_BASE(btldrData),
+                                            BL_GET_METADATA_RESPONSE_SIZE);
                             #endif  /* (CY_PSOC3) */
 
                             rspSize = 56u;
@@ -754,25 +924,59 @@ static void BL_HostLink(uint8 timeOut)
             /***************************************************************************
             *   Get flash size
             ***************************************************************************/
+
+            /* Replace BL_NUM_OF_FLASH_ARRAYS with CY_FLASH_NUMBER_ARRAYS */
+
+
             #if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL)
 
                 case BL_COMMAND_REPORT_SIZE:
 
+                    /* btldrData - holds flash array ID sent by host */
+
                     if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u))
                     {
-                        /* btldrData holds flash array ID sent by host */
-                        if(btldrData < BL_NUM_OF_FLASH_ARRAYS)
+                        if(btldrData < CY_FLASH_NUMBER_ARRAYS)
                         {
-                            #if (1u == BL_NUM_OF_FLASH_ARRAYS)
-                                uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE;
-                            #else
-                                uint16 CYDATA startRow = 0u;
-                            #endif  /* (1u == BL_NUM_OF_FLASH_ARRAYS) */
+                            uint16 CYDATA startRow;
+                            uint8  CYDATA ArrayIdBtlderEnds;
+
+
+                            /*******************************************************************************
+                            * - For the flash array where bootloader application ends, return the first
+                            *   full row after the bootloader application.
+                            *
+                            * - For the fully occupied flash array, the number of rows in array is returned.
+                            *   As there is no space for the bootloadable application in this array.
+                            *
+                            * - For the arrays next to the occupied array, zero is returned.
+                            *   The bootloadable application can written from the their beginning.
+                            *
+                            *******************************************************************************/
+                            ArrayIdBtlderEnds = (uint8)  (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ARRAY);
+
+                            if (btldrData == ArrayIdBtlderEnds)
+                            {
+                                startRow = (uint16) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ROW) %
+                                            BL_NUMBER_OF_ROWS_IN_ARRAY;
+                            }
+                            else if (btldrData > ArrayIdBtlderEnds)
+                            {
+                                startRow = BL_FIRST_ROW_IN_ARRAY;
+                            }
+                            else /* (btldrData < ArrayIdBtlderEnds) */
+                            {
+                                startRow = BL_NUMBER_OF_ROWS_IN_ARRAY;
+                            }
 
                             packetBuffer[BL_DATA_ADDR]      = LO8(startRow);
                             packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow);
-                            packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u);
-                            packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u);
+
+                            packetBuffer[BL_DATA_ADDR + 2u] =
+                                        LO8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);
+
+                            packetBuffer[BL_DATA_ADDR + 3u] =
+                                        HI8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);
 
                             rspSize = 4u;
                             ackCode = CYRET_SUCCESS;
@@ -800,7 +1004,7 @@ static void BL_HostLink(uint8 timeOut)
                                 (uint8)BL_ValidateBootloadable(btldrData);
 
                             packetBuffer[BL_DATA_ADDR + 1u] =
-                                (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData);
+                                (uint8) BL_GetMetadata(BL_GET_BTLDB_ACTIVE, btldrData);
 
                             rspSize = 2u;
                             ackCode = CYRET_SUCCESS;
@@ -846,7 +1050,7 @@ static void BL_HostLink(uint8 timeOut)
                         #if(CY_PSOC3)
                             (void) memset(dataBuffer, (char8) 0, (int16) dataOffset);
                         #else
-                            (void) memset(dataBuffer, 0, dataOffset);
+                            (void) memset(dataBuffer, 0, (uint32) dataOffset);
                         #endif  /* (CY_PSOC3) */
                     }
                     else
@@ -865,11 +1069,11 @@ static void BL_HostLink(uint8 timeOut)
                     #if(CY_PSOC3)
                         (void) memcpy(&dataBuffer[dataOffset],
                                       &packetBuffer[BL_DATA_ADDR + 3u],
-                                      ( int16 )pktSize - 3);
+                                      (int16) pktSize - 3);
                     #else
                         (void) memcpy(&dataBuffer[dataOffset],
                                       &packetBuffer[BL_DATA_ADDR + 3u],
-                                      pktSize - 3u);
+                                      (uint32) pktSize - 3u);
                     #endif  /* (CY_PSOC3) */
 
                     dataOffset += (pktSize - 3u);
@@ -898,82 +1102,155 @@ static void BL_HostLink(uint8 timeOut)
                     /* Check if we have all data to program */
                     if(dataOffset == pktSize)
                     {
-                        /* Get FLASH/EEPROM row number */
+                        uint16 row;
+                        uint16 firstRow;
+
+                        /* Get FLASH/EEPROM row number inside of the array */
                         dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) |
                                               packetBuffer[BL_DATA_ADDR + 1u];
 
+
+                        /* Metadata section resides in Flash (cannot be in EEPROM). */
                         #if(!CY_PSOC4)
                             if(btldrData <= BL_LAST_FLASH_ARRAYID)
                             {
                         #endif  /* (!CY_PSOC4) */
 
-                        #if(0u == BL_DUAL_APP_BOOTLOADER)
 
-                            if(0u == clearedMetaData)
-                            {
-                                /* Metadata section must be filled with zeroes */
+                        /* btldrData  - holds flash array Id sent by host */
+                        /* dataOffset - holds flash row Id sent by host   */
+                        row = (uint16)(btldrData * BL_NUMBER_OF_ROWS_IN_ARRAY) + dataOffset;
 
-                                uint8 erase[BL_FROW_SIZE];
 
-                                #if(CY_PSOC3)
-                                    (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);
-                                #else
-                                    (void) memset(erase, 0, BL_FROW_SIZE);
-                                #endif  /* (CY_PSOC3) */
+                        /*******************************************************************************
+                        * Refuse to write to the row within range of the bootloader application
+                        *******************************************************************************/
 
-                                #if(CY_PSOC4)
-                                    (void) CySysFlashWriteRow(BL_MD_ROW, erase);
-                                #else
-                                    (void) CyWriteRowFull((uint8)  BL_MD_FLASH_ARRAY_NUM,
-                                                          (uint16) BL_MD_ROW,
-                                                                    erase,
-                                                                    BL_FROW_SIZE);
-                                #endif  /* (CY_PSOC4) */
+                        /* First empty flash row after bootloader application */
+                        firstRow = (uint16) (*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE);
+                        if ((*BL_SizeBytesAccess % CYDEV_FLS_ROW_SIZE) != 0u)
+                        {
+                            firstRow++;
+                        }
 
-                                /* Set up flag that metadata was cleared */
-                                clearedMetaData = 1u;
-                            }
+                        /* Check to see if the row to program will not corrupt the bootloader application */
+                        if(row < firstRow)
+                        {
+                            ackCode = BL_ERR_ROW;
+                            dataOffset = 0u;
+                            break;
+                        }
 
-                        #else
+
+                        #if(0u != BL_DUAL_APP_BOOTLOADER)
 
                             if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE)
                             {
-                                /* First active bootloadable application row */
-                                uint16 firstRow = (uint16) 1u +
-                                    (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW,
+                                uint16 lastRow;
+
+
+                                /*******************************************************************************
+                                * For the first bootloadable application gets the last flash row occupied by
+                                * the bootloader application image:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<--firstRow---|>
+                                *
+                                * For the second bootloadable application gets the last flash row occupied by
+                                * the first bootloadable application:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<-------------firstRow-----------------|>
+                                *
+                                * Incremented by 1 to get the first available row.
+                                *
+                                * Note: M1 and M2 stands for the metadata # 1 and metadata # 2, metadata
+                                * sections for the 1st and 2nd bootloadable applications.
+                                *******************************************************************************/
+                                firstRow = (uint16) 1u +
+                                    (uint16) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW,
                                                                           BL_activeApp);
 
-                                #if(CY_PSOC4)
-                                    uint16 row = dataOffset;
-                                #else
-                                    uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDEV_FLS_ROW_SIZE)) +
-                                                  dataOffset;
-                                #endif  /* (CY_PSOC4) */
+
+                                /*******************************************************************************
+                                * The number of flash rows available for the both bootloadable applications:
+                                *
+                                * First bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                *                |<-------------------lastRow -------------------->|
+                                *
+                                * Second bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                *                                         |<-------lastRow-------->|
+                                *******************************************************************************/
+                                lastRow = (uint16)(CY_FLASH_NUMBER_ROWS -
+                                                    BL_NUMBER_OF_METADATA_ROWS -
+                                                    firstRow);
 
 
                                 /*******************************************************************************
-                                * Last row is equal to the first row plus the number of rows available for each
-                                * app. To compute this, we first subtract the number of appliaction images from
-                                * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u).
+                                * The number of flash rows available for the active bootloadable application:
                                 *
-                                * Then subtract off the first row:
-                                * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow)
-                                * Then divide that number by the number of application that must fit within the
-                                * space, if we are app1 then that number is 2, if app2 then 1.  Our divisor is
-                                * then: (2u - BL_activeApp).
+                                * First bootloadable application is active: the number of flash rows available
+                                * for the both bootloadable applications should be divided by 2 - 2 bootloadable
+                                * applications should fit there.
                                 *
-                                * Adding this number to firstRow gives the address right beyond our valid range
-                                * so we subtract 1.
+                                * Second bootloadable application is active: the number of flash rows available
+                                * for the both bootloadable applications should be divided by 1 - 1 bootloadable
+                                * application should fit there.
                                 *******************************************************************************/
-                                uint16 lastRow = (firstRow - 1u) +
-                                                  ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 2u - firstRow) /
-                                                  ((uint16)2u - (uint16)BL_activeApp));
+                                lastRow = lastRow / (BL_NUMBER_OF_BTLDBLE_APPS -
+                                                BL_activeApp);
 
 
                                 /*******************************************************************************
-                                * Check to see if the row to program is within the range of the active
-                                * application, or if it maches the active application's metadata row.  If so,
-                                * refuse to program as it would corrupt the active app.
+                                * The last row equals to the first row plus the number of rows available for
+                                * the each bootloadable application. That gives the flash row number right
+                                * beyond the valid range, so we subtract 1.
+                                *
+                                * First bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<----------------lastRow ------------->|
+                                *
+                                * Second bootloadable application is active:
+                                *  ---------------------------------------------------------------------------
+                                * | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *  ---------------------------------------------------------------------------
+                                * |<-----------------------------lastRow-------------------------->|
+                                *******************************************************************************/
+                                lastRow = (firstRow + lastRow) - 1u;
+
+
+                                /*******************************************************************************
+                                * 1. Refuse to write row within the range of the active application
+                                *
+                                *  First bootloadable application is active:
+                                *   ---------------------------------------------------------------------------
+                                *  | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *   ---------------------------------------------------------------------------
+                                *  |<----------------lastRow ------------->|
+                                *  |<--firstRow---|>
+                                *                 |<-------protected------>|
+                                *
+                                *  Second bootloadable application is active:
+                                *   ---------------------------------------------------------------------------
+                                *  | Bootloader   | Bootloadable # 1 |     | Bootloadable # 2 |     | M2 | M1 |
+                                *   ---------------------------------------------------------------------------
+                                *  |<-------------firstRow-----------------|>
+                                *  |<-----------------------------lastRow-------------------------->|
+                                *                                          |<-------protected------>|
+                                *
+                                * 2. Refuse to write to the row that contains metadata of the active
+                                *    bootloadable application.
+                                *
                                 *******************************************************************************/
                                 if(((row >= firstRow) && (row <= lastRow)) ||
                                    ((btldrData == BL_MD_FLASH_ARRAY_NUM) &&
@@ -985,26 +1262,99 @@ static void BL_HostLink(uint8 timeOut)
                                 }
                             }
 
-                        #endif  /* (0u == BL_DUAL_APP_BOOTLOADER) */
+                        #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
 
-                        #if(!CY_PSOC4)
+
+
+                        /*******************************************************************************
+                        * Clear row that contains the metadata, when 'Fast bootloadable application
+                        * validation' option is enabled.
+                        *
+                        * If 'Fast bootloadable application validation' option is enabled, the
+                        * bootloader only computes the checksum the first time and assumes that it
+                        * remains valid in each future startup. The metadata row is cleared because the
+                        * bootloadable application might become corrupted during update, while
+                        * 'Bootloadable Application Verification Status' field will still report that
+                        * application is valid.
+                        *******************************************************************************/
+                        #if(0u != BL_FAST_APP_VALIDATION)
+
+                            if(0u == clearedMetaData)
+                            {
+                                /* Metadata section must be filled with zeros */
+
+                                uint8 erase[BL_FROW_SIZE];
+                                uint8 BL_notActiveApp;
+
+
+                                #if(CY_PSOC3)
+                                    (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);
+                                #else
+                                    (void) memset(erase, 0, BL_FROW_SIZE);
+                                #endif  /* (CY_PSOC3) */
+
+
+                                #if(0u != BL_DUAL_APP_BOOTLOADER)
+                                    if (BL_MD_BTLDB_ACTIVE_0 == BL_activeApp)
+                                    {
+                                        BL_notActiveApp = BL_MD_BTLDB_ACTIVE_1;
+                                    }
+                                    else
+                                    {
+                                        BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;
+                                    }
+                                #else
+                                    BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;
+                                #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+
+                                #if(CY_PSOC4)
+                                    (void) CySysFlashWriteRow(
+                                            BL_MD_ROW_NUM(BL_notActiveApp),
+                                            erase);
+                                #else
+                                    (void) CyWriteRowFull(
+                                            (uint8)  BL_MD_FLASH_ARRAY_NUM,
+                                            (uint16) BL_MD_ROW_NUM(BL_notActiveApp),
+                                            erase,
+                                            BL_FROW_SIZE);
+                                #endif  /* (CY_PSOC4) */
+
+                                /* PSoC 5: Do not care about flushing the cache as flash row has been erased. */
+
+                                /* Set up flag that metadata was cleared */
+                                clearedMetaData = 1u;
                             }
+
+                        #endif  /* (0u != BL_FAST_APP_VALIDATION) */
+
+
+                        #if(!CY_PSOC4)
+                            }   /* (btldrData <= BL_LAST_FLASH_ARRAYID) */
                         #endif  /* (!CY_PSOC4) */
 
-                        #if(CY_PSOC4)
 
-                            ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dataBuffer)) \
+                        #if(CY_PSOC4)
+                            ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) row, dataBuffer)) \
                                 ? BL_ERR_ROW \
                                 : CYRET_SUCCESS;
-
                         #else
-
                             ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \
                                 ? BL_ERR_ROW \
                                 : CYRET_SUCCESS;
-
                         #endif  /* (CY_PSOC4) */
 
+
+                        #if(CY_PSOC5)
+                            /***************************************************************************
+                            * When writing Flash, data in the instruction cache can become stale.
+                            * Therefore, the cache data does not correlate to the data just written to
+                            * Flash. A call to CyFlushCache() is required to invalidate the data in the
+                            * cache and force fresh information to be loaded from Flash.
+                            ***************************************************************************/
+                            CyFlushCache();
+                        #endif /* (CY_PSOC5) */
+
                     }
                     else
                     {
@@ -1028,7 +1378,7 @@ static void BL_HostLink(uint8 timeOut)
                     /* If something failed the host would send this command to reset the bootloader. */
                     dataOffset = 0u;
 
-                    /* Don't ack the packet, just get ready to accept the next one */
+                    /* Don't acknowledge the packet, just get ready to accept the next one */
                     continue;
                 }
                 break;
@@ -1037,7 +1387,7 @@ static void BL_HostLink(uint8 timeOut)
 
 
             /***************************************************************************
-            *   Set active application
+            *   Set an active application
             ***************************************************************************/
             #if(0u != BL_DUAL_APP_BOOTLOADER)
 
@@ -1088,7 +1438,7 @@ static void BL_HostLink(uint8 timeOut)
                             #else
                                 (void) memcpy(&dataBuffer[dataOffset],
                                               &packetBuffer[BL_DATA_ADDR],
-                                              pktSize);
+                                              (uint32) pktSize);
                             #endif  /* (CY_PSOC3) */
 
                             dataOffset += pktSize;
@@ -1134,7 +1484,7 @@ static void BL_HostLink(uint8 timeOut)
                     #else
                         (void) memcpy(&packetBuffer[BL_DATA_ADDR],
                                       &BtldrVersion,
-                                      rspSize);
+                                      (uint32) rspSize);
                     #endif  /* (CY_PSOC3) */
 
                     ackCode = CYRET_SUCCESS;
@@ -1145,6 +1495,8 @@ static void BL_HostLink(uint8 timeOut)
             /***************************************************************************
             *   Verify row
             ***************************************************************************/
+            #if (0u != BL_CMD_VERIFY_ROW_AVAIL)
+
             case BL_COMMAND_VERIFY:
 
                 if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u))
@@ -1165,7 +1517,7 @@ static void BL_HostLink(uint8 timeOut)
                             /* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */
                             rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE;
 
-                            checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE);
+                            checksum = BL_Calc8BitSum(CY_EEPROM_BASE, rowAddr, CYDEV_EEPROM_ROW_SIZE);
                         }
                         else
                         {
@@ -1173,7 +1525,7 @@ static void BL_HostLink(uint8 timeOut)
                             rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)
                                        + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);
 
-                            checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);
+                            checksum = BL_Calc8BitSum(CY_FLASH_BASE, rowAddr, CYDEV_FLS_ROW_SIZE);
                         }
 
                     #else
@@ -1181,7 +1533,9 @@ static void BL_HostLink(uint8 timeOut)
                         uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)
                                             + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);
 
-                        uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);
+                        uint8 CYDATA checksum = BL_Calc8BitSum(CY_FLASH_BASE,
+                                                                             rowAddr,
+                                                                             CYDEV_FLS_ROW_SIZE);
 
                     #endif  /* (!CY_PSOC4) */
 
@@ -1206,15 +1560,19 @@ static void BL_HostLink(uint8 timeOut)
 
 
                     /*******************************************************************************
-                    * App Verified & App Active are information that is updated in flash at runtime
-                    * remove these items from the checksum to allow the host to verify everything is
+                    * App Verified & App Active are information that is updated in Flash at runtime.
+                    * Remove these items from the checksum to allow the host to verify everything is
                     * correct.
                      ******************************************************************************/
                     if((BL_MD_FLASH_ARRAY_NUM == btldrData) &&
                        (BL_CONTAIN_METADATA(rowNum)))
                     {
-                        checksum -= BL_MD_BTLDB_ACTIVE_VALUE  (BL_GET_APP_ID(rowNum));
-                        checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum));
+
+                        checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_ACTIVE,
+                                                                 BL_GET_APP_ID(rowNum));
+
+                        checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_STATUS,
+                                                                 BL_GET_APP_ID(rowNum));
                     }
 
                     packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum);
@@ -1223,6 +1581,8 @@ static void BL_HostLink(uint8 timeOut)
                 }
                 break;
 
+            #endif /* (0u != BL_CMD_VERIFY_ROW_AVAIL) */
+
 
             /***************************************************************************
             *   Exit bootloader
@@ -1231,7 +1591,7 @@ static void BL_HostLink(uint8 timeOut)
 
                 if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp))
                 {
-                    BL_SET_RUN_TYPE(BL_START_APP);
+                    BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);
                 }
 
                 CySoftwareReset();
@@ -1249,7 +1609,7 @@ static void BL_HostLink(uint8 timeOut)
             }
         }
 
-        /* ?CK the packet and function. */
+        /* Reply with acknowledge or not acknowledge packet */
         (void) BL_WritePacket(ackCode, packetBuffer, rspSize);
 
     } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState));
@@ -1261,7 +1621,7 @@ static void BL_HostLink(uint8 timeOut)
 ********************************************************************************
 *
 * Summary:
-*  Creates a bootloader responce packet and transmits it back to the bootloader
+*  Creates a bootloader response packet and transmits it back to the bootloader
 *  host application over the already established communications protocol.
 *
 * Parameters:
@@ -1273,8 +1633,7 @@ static void BL_HostLink(uint8 timeOut)
 *      The number of bytes contained within the buffer to pass back
 *
 * Return:
-*   CYRET_SUCCESS if successful.
-*   CYRET_UNKNOWN if there was an error tranmitting the packet.
+*   CYRET_SUCCESS if successful. Any other non-zero value if failure occurred.
 *
 *******************************************************************************/
 static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \
@@ -1282,20 +1641,20 @@ static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMAL
 {
     uint16 CYDATA checksum;
 
-    /* Start of the packet. */
+    /* Start of packet. */
     buffer[BL_SOP_ADDR]      = BL_SOP;
     buffer[BL_CMD_ADDR]      = status;
     buffer[BL_SIZE_ADDR]     = LO8(size);
     buffer[BL_SIZE_ADDR + 1u] = HI8(size);
 
-    /* Compute the checksum. */
+    /* Compute checksum. */
     checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR);
 
     buffer[BL_CHK_ADDR(size)]     = LO8(checksum);
     buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum);
     buffer[BL_EOP_ADDR(size)]     = BL_EOP;
 
-    /* Start the packet transmit. */
+    /* Start packet transmit. */
     return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u));
 }
 
@@ -1305,11 +1664,11 @@ static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMAL
 ********************************************************************************
 *
 * Summary:
-*  Writes byte a flash memory location
+*  Writes a byte to the specified Flash memory location.
 *
 * Parameters:
 *  address:
-*      Address in Flash memory where data will be written
+*      The address in Flash memory where data will be written
 *
 *  runType:
 *      Byte to be written
@@ -1327,7 +1686,12 @@ void BL_SetFlashByte(uint32 address, uint8 runType)
         uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
     #endif  /* !(CY_PSOC4) */
 
-    uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #if (CY_PSOC4)
+        uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+    #else
+        uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+    #endif  /* (CY_PSOC4) */
+
     uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
     uint16 idx;
 
@@ -1343,6 +1707,16 @@ void BL_SetFlashByte(uint32 address, uint8 runType)
     #else
         (void) CyWriteRowData(arrayId, rowNum, rowData);
     #endif  /* (CY_PSOC4) */
+
+    #if(CY_PSOC5)
+        /***************************************************************************
+        * When writing Flash, data in the instruction cache can become stale.
+        * Therefore, the cache data does not correlate to the data just written to
+        * Flash. A call to CyFlushCache() is required to invalidate the data in the
+        * cache and force fresh information to be loaded from Flash.
+        ***************************************************************************/
+        CyFlushCache();
+    #endif /* (CY_PSOC5) */
 }
 
 
@@ -1351,69 +1725,90 @@ void BL_SetFlashByte(uint32 address, uint8 runType)
 ********************************************************************************
 *
 * Summary:
-*  Returns value of the multi-byte field.
+*  Returns the value of the specified field of the metadata section.
 *
 * Parameters:
-*  fieldName:
+*  field:
 *   The field to get data from:
-*     BL_GET_METADATA_BTLDB_ADDR
-*     BL_GET_METADATA_BTLDR_LAST_ROW
-*     BL_GET_METADATA_BTLDB_LENGTH
-*     BL_GET_METADATA_BTLDR_APP_VERSION
-*     BL_GET_METADATA_BTLDB_APP_VERSION
-*     BL_GET_METADATA_BTLDB_APP_ID
-*     BL_GET_METADATA_BTLDB_APP_CUST_ID
+*   BL_GET_BTLDB_CHECKSUM    - Bootloadable Application Checksum
+*   BL_GET_BTLDB_ADDR        - Bootloadable Application Start
+*                                            Routine Address
+*   BL_GET_BTLDR_LAST_ROW    - Bootloader Last Flash Row
+*   BL_GET_BTLDB_LENGTH      - Bootloadable Application Length
+*   BL_GET_BTLDB_ACTIVE      - Active Bootloadable Application
+*   BL_GET_BTLDB_STATUS      - Bootloadable Application
+*                                            Verification Status
+*   BL_GET_BTLDR_APP_VERSION - Bootloader Application Version
+*   BL_GET_BTLDB_APP_VERSION - Bootloadable Application Version
+*   BL_GET_BTLDB_APP_ID      - Bootloadable Application ID
+*   BL_GET_BTLDB_APP_CUST_ID - Bootloadable Application Custom ID
 *
 *  appId:
-*   Number of the bootlodable application.
+*   Number of the bootlodable application. Should be 0 for the normal
+*   bootloader and 0 or 1 for the Multi-Application bootloader.
 *
 * Return:
-*  None
+*  The value of the specified field of the specified application.
 *
 *******************************************************************************/
-static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)
+uint32 BL_GetMetadata(uint8 field, uint8 appId)
 {
     uint32 fieldPtr;
     uint8  fieldSize = 2u;
-    uint32 result;
+    uint32 result = 0u;
 
-    switch (fieldName)
+    switch (field)
     {
-    case BL_GET_METADATA_BTLDB_APP_CUST_ID:
-        fieldPtr  = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);
-        fieldSize = 4u;
-        break;
-
-    case BL_GET_METADATA_BTLDR_APP_VERSION:
-        fieldPtr  = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);
+    case BL_GET_BTLDB_CHECKSUM:
+        fieldPtr  = BL_MD_BTLDB_CHECKSUM_OFFSET(appId);
+        fieldSize = 1u;
         break;
 
-    case BL_GET_METADATA_BTLDB_ADDR:
+    case BL_GET_BTLDB_ADDR:
         fieldPtr  = BL_MD_BTLDB_ADDR_OFFSET(appId);
     #if(!CY_PSOC3)
         fieldSize = 4u;
     #endif  /* (!CY_PSOC3) */
         break;
 
-    case BL_GET_METADATA_BTLDR_LAST_ROW:
+    case BL_GET_BTLDR_LAST_ROW:
         fieldPtr  = BL_MD_BTLDR_LAST_ROW_OFFSET(appId);
         break;
 
-    case BL_GET_METADATA_BTLDB_LENGTH:
+    case BL_GET_BTLDB_LENGTH:
         fieldPtr  = BL_MD_BTLDB_LENGTH_OFFSET(appId);
     #if(!CY_PSOC3)
         fieldSize = 4u;
     #endif  /* (!CY_PSOC3) */
         break;
 
-    case BL_GET_METADATA_BTLDB_APP_VERSION:
+    case BL_GET_BTLDB_ACTIVE:
+        fieldPtr  = BL_MD_BTLDB_ACTIVE_OFFSET(appId);
+        fieldSize = 1u;
+        break;
+
+    case BL_GET_BTLDB_STATUS:
+        fieldPtr  = BL_MD_BTLDB_VERIFIED_OFFSET(appId);
+        fieldSize = 1u;
+        break;
+
+    case BL_GET_BTLDB_APP_VERSION:
         fieldPtr  = BL_MD_BTLDB_APP_VERSION_OFFSET(appId);
         break;
 
-    case BL_GET_METADATA_BTLDB_APP_ID:
+    case BL_GET_BTLDR_APP_VERSION:
+        fieldPtr  = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);
+        break;
+
+    case BL_GET_BTLDB_APP_ID:
         fieldPtr  = BL_MD_BTLDB_APP_ID_OFFSET(appId);
         break;
 
+    case BL_GET_BTLDB_APP_CUST_ID:
+        fieldPtr  = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);
+        fieldSize = 4u;
+        break;
+
     default:
         /* Should never be here */
         CYASSERT(0u != 0u);
@@ -1422,38 +1817,44 @@ static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)
     }
 
 
-    /* Read all fields as big-endian */
-    if (2u == fieldSize)
-    {
-        result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr      ) <<  8u;
-    }
-    else
+    if (1u == fieldSize)
     {
-        result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) <<  8u;
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;
-        result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     )) << 24u;
+        result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)fieldPtr);
     }
 
-    /* Following fields should be little-endian */
-#if(!CY_PSOC3)
-    switch (fieldName)
-    {
-    case BL_GET_METADATA_BTLDR_LAST_ROW:
-        result = CYSWAP_ENDIAN16(result);
-        break;
+    #if(CY_PSOC3)   /* Big-endian */
 
-    case BL_GET_METADATA_BTLDB_ADDR:
-    case BL_GET_METADATA_BTLDB_LENGTH:
-        result = CYSWAP_ENDIAN32(result);
-        break;
+        if (2u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     )) <<  8u;
+        }
 
-    default:
-        break;
-    }
+        if (4u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) <<  8u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     )) << 24u;
+        }
 
-#endif  /* (!CY_PSOC3) */
+    #else   /* PSoC 4 and PSoC 5: Little-endian */
+
+        if (2u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr     ));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr + 1u)) <<  8u;
+        }
+
+        if (4u == fieldSize)
+        {
+            result =  (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr     ));
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) <<  8u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 16u;
+            result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)) << 24u;
+        }
+
+    #endif /* (CY_PSOC3) */
 
     return (result);
 }
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h
index edb0301b..06b8f7d3 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: BL.h
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloader. The API includes functions for starting
@@ -8,7 +8,7 @@
 *   application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -18,14 +18,7 @@
 #define CY_BOOTLOADER_BL_H
 
 #include "cytypes.h"
-
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
-    #error Component Bootloader_v1_20 requires cy_boot v3.0 or later
-#endif /* (CY_ PSOC5X) */
-
+#include "CyFlash.h"
 
 #define BL_DUAL_APP_BOOTLOADER        (0u)
 #define BL_BOOTLOADER_APP_VERSION     (0u)
@@ -62,7 +55,6 @@
 #define BL_SCHEDULE_BTLDR             (0x40u)
 #define BL_SCHEDULE_MASK              (0xC0u)
 
-
 #if defined(__ARMCC_VERSION) || defined (__GNUC__)
     __attribute__((section (".bootloader")))
 #elif defined (__ICCARM__)
@@ -114,9 +106,9 @@ extern const uint32 CYCODE *BL_SizeBytesAccess;
 
 /*******************************************************************************
 * Get the reason of the device reset
-*  Return cyBtldrRunType in case if software reset was reset reason and
+*  Return cyBtldrRunType in the case if software reset was the reset reason and
 *  set cyBtldrRunType to zero (bootloader application is scheduled - that is
-*  initial clean state) and return zero.
+*  the initial clean state) and return zero.
 *******************************************************************************/
 #if(CY_PSOC4)
     #define BL_GET_RUN_TYPE           (cyBtldrRunType)
@@ -135,8 +127,10 @@ extern const uint32 CYCODE *BL_SizeBytesAccess;
 #endif  /* (CY_PSOC4) */
 
 
-/* Returns the number of Flash arrays availalbe in the device */
-#define BL_NUM_OF_FLASH_ARRAYS    (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
+/* Returns the number of Flash arrays available in the device */
+#ifndef CY_FLASH_NUMBER_ARRAYS
+    #define CY_FLASH_NUMBER_ARRAYS                  (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
+#endif /* CY_FLASH_NUMBER_ARRAYS */
 
 
 /*******************************************************************************
@@ -145,13 +139,20 @@ extern const uint32 CYCODE *BL_SizeBytesAccess;
 void BL_SetFlashByte(uint32 address, uint8 runType);
 void CyBtldr_CheckLaunch(void)  CYSMALL ;
 void BL_Start(void) CYSMALL ;
+cystatus BL_ValidateBootloadable(uint8 appId) \
+            CYSMALL ;
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) CYSMALL \
+                                    ;
+uint32   BL_GetMetadata(uint8 field, uint8 appId) \
+                                    ;
+void BL_Exit(uint8 appId) CYSMALL ;
 
 #if(CY_PSOC3)
     /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file.  */
-    extern void     BL_LaunchBootloadable(uint32 appAddr);
+    void     BL_LaunchBootloadable(uint32 appAddr);
 #endif  /* (CY_PSOC3) */
 
-/* If using custom interface as the IO Component, user must provide these functions */
+/* When using a custom interface as the IO Component, the user must provide these functions */
 #if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)
 
     extern void CyBtldrCommStart(void);
@@ -163,30 +164,55 @@ void BL_Start(void) CYSMALL ;
 #endif  /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */
 
 
+/*******************************************************************************
+* BL_GetMetadata()
+*******************************************************************************/
+#define BL_GET_BTLDB_CHECKSUM         (1u)
+#define BL_GET_BTLDB_ADDR             (2u)
+#define BL_GET_BTLDR_LAST_ROW         (3u)
+#define BL_GET_BTLDB_LENGTH           (4u)
+#define BL_GET_BTLDB_ACTIVE           (5u)
+#define BL_GET_BTLDB_STATUS           (6u)
+#define BL_GET_BTLDR_APP_VERSION      (7u)
+#define BL_GET_BTLDB_APP_VERSION      (8u)
+#define BL_GET_BTLDB_APP_ID           (9u)
+#define BL_GET_BTLDB_APP_CUST_ID      (10u)
+
+#define BL_GET_METADATA_RESPONSE_SIZE (56u)
+
+/*******************************************************************************
+* BL_Exit()
+*******************************************************************************/
+#define BL_EXIT_TO_BTLDR              (2u)
+#define BL_EXIT_TO_BTLDB              (0u)
+#if(0u != BL_DUAL_APP_BOOTLOADER)
+    #define BL_EXIT_TO_BTLDB_1        (0u)
+    #define BL_EXIT_TO_BTLDB_2        (1u)
+#endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+
 /*******************************************************************************
 * Kept for backward compatibility.
 *******************************************************************************/
 #if(0u != BL_DUAL_APP_BOOTLOADER)
     #define BL_ValidateApp(x)                 BL_ValidateBootloadable((x))
-    #define BL_ValidateApplication            \
+    #define BL_ValidateApplication()            \
                             BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)
 #else
-    #define BL_ValidateApplication            \
+    #define BL_ValidateApplication()            \
                             BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)
     #define BL_ValidateApp(x)                 BL_ValidateBootloadable((x))
 #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
+#define BL_Calc8BitFlashSum(start, size)      BL_Calc8BitSum(CY_FLASH_BASE, (start), (size))
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.10
+* The following code is DEPRECATED and must not be used.
 *******************************************************************************/
 #define BL_BOOTLOADABLE_APP_VALID     (BL_BOOTLOADER_APP_VALIDATION)
 #define CyBtldr_Start                               BL_Start
 
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.20
-*******************************************************************************/
+#define BL_NUM_OF_FLASH_ARRAYS            (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
 #define BL_META_BASE(x)                   (CYDEV_FLASH_BASE + \
                                                             (CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \
                                                             BL_META_DATA_SIZE))
@@ -215,8 +241,14 @@ void BL_Start(void) CYSMALL ;
                                                             BL_META_APP_CHECKSUM_OFFSET)
 #if(0u == BL_DUAL_APP_BOOTLOADER)
     #define BL_MD_BASE                    BL_META_BASE(0u)
-    #define BL_MD_ROW                     ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
-                                                           - 1u)
+
+    #if(!CY_PSOC4)
+        #define BL_MD_ROW                 ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
+                                                        - 1u)
+    #else
+        #define BL_MD_ROW                 (CY_FLASH_NUMBER_ROWS - 1u)
+    #endif /* (CY_PSOC4) */
+
     #define BL_MD_CHECKSUM_ADDR           BL_META_CHECKSUM_ADDR(0u)
     #define BL_MD_LAST_BLDR_ROW_ADDR      BL_META_LAST_BLDR_ROW_ADDR(0u)
     #define BL_MD_APP_BYTE_LEN            BL_META_APP_BYTE_LEN(0u)
@@ -224,8 +256,13 @@ void BL_Start(void) CYSMALL ;
     #define BL_MD_APP_ENTRY_POINT_ADDR    BL_META_APP_ENTRY_POINT_ADDR(0u)
     #define BL_MD_APP_RUN_ADDR            BL_META_APP_RUN_ADDR(0u)
 #else
-    #define BL_MD_ROW(x)                  ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
-                                                            - 1u - ( uint32 )(x))
+    #if(!CY_PSOC4)
+        #define BL_MD_ROW(x)              ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
+                                                        - 1u - ( uint32 )(x))
+    #else
+        #define BL_MD_ROW(x)              (CY_FLASH_NUMBER_ROWS - 1u - ( uint32 )(x))
+    #endif /* (CY_PSOC4) */
+
     #define BL_MD_CHECKSUM_ADDR           BL_META_CHECKSUM_ADDR(appId)
     #define BL_MD_LAST_BLDR_ROW_ADDR      BL_META_LAST_BLDR_ROW_ADDR(appId)
     #define BL_MD_APP_BYTE_LEN            BL_META_APP_BYTE_LEN(appId)
@@ -302,7 +339,7 @@ void BL_Start(void) CYSMALL ;
 #define BL_START_APP                  (BL_SCHEDULE_BTLDB)
 #define BL_START_BTLDR                (BL_SCHEDULE_BTLDR)
 
-/* Some PSoC Creator versions used to generate only one name types */
+/* Some PSoC Creator versions are used to generate only one name types */
 #if !defined (CYDEV_FLASH_BASE)
     #define CYDEV_FLASH_BASE                                (CYDEV_FLS_BASE)
 #endif /* !defined (CYDEV_FLASH_BASE) */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h
index 400edde5..015f378e 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: BL_PVT.h
-* Version 1.20
+* Version 1.30
 *
 *  Description:
 *   Provides an API for the Bootloader.
 *
 ********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -28,7 +28,7 @@ typedef struct
 
 
 #define BL_VERSION        {\
-                                            (uint8)20, \
+                                            (uint8)30, \
                                             (uint8)1, \
                                             (uint8)0x01u \
                                         }
@@ -38,7 +38,7 @@ typedef struct
 #define BL_EOP            (0x17u)    /* End of Packet */
 
 
-/* Bootloader command responces */
+/* Bootloader command responses */
 #define BL_ERR_KEY       (0x01u)  /* The provided key does not match the expected value          */
 #define BL_ERR_VERIFY    (0x02u)  /* The verification of flash failed                            */
 #define BL_ERR_LENGTH    (0x03u)  /* The amount of data available is outside the expected range  */
@@ -88,7 +88,7 @@ typedef struct
 BL_ValidateBootloadable()
 *******************************************************************************/
 #define BL_FIRST_APP_BYTE(appId)      ((uint32)CYDEV_FLS_ROW_SIZE * \
-        ((uint32) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, appId) + \
+        ((uint32) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW, appId) + \
          (uint32) 1u))
 
 #define BL_MD_BTLDB_IS_VERIFIED       (0x01u)
@@ -101,7 +101,7 @@ BL_ValidateBootloadable()
 #define BL_WAIT_FOR_COMMAND_FOREVER   (0x00u)
 
 
- /* Maximum number of bytes accepted in a packet plus some */
+ /* The maximum number of bytes accepted in a packet plus some */
 #define BL_SIZEOF_COMMAND_BUFFER      (300u)
 
 
@@ -136,18 +136,6 @@ BL_ValidateBootloadable()
 #endif /* (0u != BL_PACKET_CHECKSUM_CRC) */
 
 
-/*******************************************************************************
-* BL_GetMetadata()
-*******************************************************************************/
-#define BL_GET_METADATA_BTLDB_ADDR             (1u)
-#define BL_GET_METADATA_BTLDR_LAST_ROW         (2u)
-#define BL_GET_METADATA_BTLDB_LENGTH           (3u)
-#define BL_GET_METADATA_BTLDR_APP_VERSION      (4u)
-#define BL_GET_METADATA_BTLDB_APP_VERSION      (5u)
-#define BL_GET_METADATA_BTLDB_APP_ID           (6u)
-#define BL_GET_METADATA_BTLDB_APP_CUST_ID      (7u)
-
-
 /*******************************************************************************
 * CyBtldr_CheckLaunch()
 *******************************************************************************/
@@ -161,11 +149,11 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Metadata base address. In case of bootloader application, the metadata is
-* placed at row N-1; in case of multi-application bootloader, the bootloadable
-* application number 1 will use row N-1, and application number 2 will use row
-* N-2 to store its metadata, where N is the total number of rows for the
-* selected device.
+* The Metadata base address. In the case of the bootloader application, the
+* metadata is placed at row N-1; in the case of the multi-application
+* bootloader, the bootloadable application number 1 will use row N-1, and
+* application number 2 will use row N-2 to store its metadata, where N is the
+* total number of the rows for the selected device.
 *******************************************************************************/
 #define BL_MD_BASE_ADDR(appId)        (CYDEV_FLASH_BASE + \
                                                         (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \
@@ -173,8 +161,13 @@ BL_ValidateBootloadable()
 
 #define BL_MD_FLASH_ARRAY_NUM         (BL_NUM_OF_FLASH_ARRAYS - 1u)
 
-#define BL_MD_ROW_NUM(appId)          ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \
-                                                        1u - (uint32)(appId))
+#if(!CY_PSOC4)
+    #define BL_MD_ROW_NUM(appId)      ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \
+                                                    1u - (uint32)(appId))
+#else
+    #define BL_MD_ROW_NUM(appId)      (CY_FLASH_NUMBER_ROWS - 1u - (uint32)(appId))
+#endif /* (!CY_PSOC4) */
+
 
 #define     BL_MD_BTLDB_CHECKSUM_OFFSET(appId)       (BL_MD_BASE_ADDR(appId) + 0u)
 #if(CY_PSOC3)
@@ -194,50 +187,6 @@ BL_ValidateBootloadable()
 #define     BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId)    (BL_MD_BASE_ADDR(appId) + 24u)
 
 
-/*******************************************************************************
-* Macro for 1 byte long metadata fields
-*******************************************************************************/
-#define BL_MD_BTLDB_CHECKSUM_PTR  (appId)    \
-            ((reg8 *)(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))
-#define BL_MD_BTLDB_CHECKSUM_VALUE(appId)    \
-            (CY_GET_XTND_REG8(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))
-
-#define BL_MD_BTLDB_ACTIVE_PTR(appId)        \
-            ((reg8 *)(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))
-#define BL_MD_BTLDB_ACTIVE_VALUE(appId)      \
-            (CY_GET_XTND_REG8(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))
-
-#define BL_MD_BTLDB_VERIFIED_PTR(appId)      \
-            ((reg8 *)(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))
-#define BL_MD_BTLDB_VERIFIED_VALUE(appId)    \
-            (CY_GET_XTND_REG8(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))
-
-
-/*******************************************************************************
-* Macro for multiple bytes long metadata fields pointers 
-*******************************************************************************/
-#define BL_MD_BTLDB_ADDR_PTR  (appId)        \
-            ((reg8 *)(BL_MD_BTLDB_ADDR_OFFSET(appId)))
-
-#define BL_MD_BTLDR_LAST_ROW_PTR  (appId)    \
-            ((reg8 *)(BL_MD_BTLDR_LAST_ROW_OFFSET(appId)))
-
-#define BL_MD_BTLDB_LENGTH_PTR(appId)        \
-            ((reg8 *)(BL_MD_BTLDB_LENGTH_OFFSET(appId)))
-
-#define BL_MD_BTLDR_APP_VERSION_PTR(appId)    \
-            ((reg8 *)(BL_MD_BTLDR_APP_VERSION_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_ID_PTR(appId)         \
-            ((reg8 *)(BL_MD_BTLDB_APP_ID_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_VERSION_PTR(appId)    \
-            ((reg8 *)(BL_MD_BTLDB_APP_VERSION_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_CUST_ID_PTR(appId)    \
-            ((reg8 *)(BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId)))
-
-
 /*******************************************************************************
 * Get data byte from FLASH
 *******************************************************************************/
@@ -262,7 +211,8 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Offset of the Bootloader application in flash
+* Number of addresses remapped from Flash to RAM, when interrupt vectors are
+* configured to be stored in RAM (default setting, configured by cy_boot).
 *******************************************************************************/
 #if(CY_PSOC4)
     #define BL_MD_BTLDR_ADDR_PTR        (0xC0u)     /* Exclude the vector */
@@ -272,7 +222,7 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Maximum number of Bootloadable applications
+* The maximum number of Bootloadable applications
 *******************************************************************************/
 #if(1u == BL_DUAL_APP_BOOTLOADER)
     #define BL_MAX_NUM_OF_BTLDB       (0x02u)
@@ -282,7 +232,7 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Returns TRUE if row specified as parameter contains metadata section
+* Returns TRUE if the row specified as a parameter contains a metadata section
 *******************************************************************************/
 #if(0u != BL_DUAL_APP_BOOTLOADER)
     #define BL_CONTAIN_METADATA(row)  \
@@ -295,10 +245,10 @@ BL_ValidateBootloadable()
 
 
 /*******************************************************************************
-* Metadata section is located at the last flash row for the Boootloader, for the
-* Multi-Application Bootloader, metadata section of the Bootloadable application
-* # 0 is located at the last flash row, and metadata section of the Bootloadable
-* application # 1 is located in the flash row before last.
+* The Metadata section is located in the last flash row for the Boootloader, for
+* the Multi-Application Bootloader, the metadata section of the Bootloadable
+* application # 0 is located in the last flash row, and the metadata section of
+* the Bootloadable application # 1 is located in the flash row before last.
 *******************************************************************************/
 #if(0u != BL_DUAL_APP_BOOTLOADER)
     #define BL_GET_APP_ID(row)     \
@@ -309,6 +259,29 @@ BL_ValidateBootloadable()
     #define BL_GET_APP_ID(row)     (BL_MD_BTLDB_ACTIVE_0)
 #endif  /* (0u != BL_DUAL_APP_BOOTLOADER) */
 
+
+/*******************************************************************************
+* Defines the number of flash rows reserved for the metadata section
+*******************************************************************************/
+#if(0u == BL_DUAL_APP_BOOTLOADER)
+    #define BL_NUMBER_OF_METADATA_ROWS            (1u)
+#else
+    #define BL_NUMBER_OF_METADATA_ROWS            (2u)
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+
+
+/*******************************************************************************
+* Defines the number of possible bootloadable applications
+*******************************************************************************/
+#if(0u == BL_DUAL_APP_BOOTLOADER)
+    #define BL_NUMBER_OF_BTLDBLE_APPS            (1u)
+#else
+    #define BL_NUMBER_OF_BTLDBLE_APPS            (2u)
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+
+#define BL_NUMBER_OF_ROWS_IN_ARRAY                ((uint16)(CY_FLASH_SIZEOF_ARRAY/CY_FLASH_SIZEOF_ROW))
+#define BL_FIRST_ROW_IN_ARRAY                     (0u)
+
 #endif /* CY_BOOTLOADER_BL_PVT_H */
 
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
index c8b4bcc8..5d23335f 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf
@@ -40,7 +40,10 @@ define block CSTACK      with alignment = 8, size = __ICFEDIT_size_cstack__   {
 define block HEAP        with alignment = 8, size = __ICFEDIT_size_heap__     { };
 define block HSTACK      {block HEAP, last block CSTACK};
 
+if (CY_APPL_LOADABLE)
+{
 define block LOADER     { readonly section .cybootloader };
+}
 define block APPL       with fixed order {readonly section .romvectors, readonly};
 
 /* The address of Flash row next after Bootloader image */
@@ -83,7 +86,11 @@ do not initialize  { section .noinit };
 do not initialize  { readwrite section .ramvectors };
 
 /******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
 ".cybootloader"    : place at start of ROM_region {block LOADER};
+}
+
 "APPL"             : place at start of APPL_region {block APPL};
 
 "RAMVEC"           : place at start of RAM_region { readwrite section .ramvectors };
@@ -101,7 +108,10 @@ keep {  section .cybootloader,
         section .cymeta };
 
 ".cyloadermeta"   : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
 ".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
 ".cyconfigecc"    : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
 ".cycustnvl"      : place at address mem : 0x90000000 { readonly section .cycustnvl };
 ".cywolatch"      : place at address mem : 0x90100000 { readonly section .cywolatch };
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
index d3772112..951d2afa 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
@@ -4,7 +4,7 @@
 
 ;********************************************************************************
 ;* File Name: Cm3RealView.scat
-;* Version 4.0
+;* Version 4.20
 ;*
 ;*  Description:
 ;*  This Linker Descriptor file describes the memory layout of the PSoC5
@@ -14,7 +14,7 @@
 ;*
 ;*  Note:
 ;*
-;*  romvectors: Cypress default Interrupt sevice routine vector table.
+;*  romvectors: Cypress default Interrupt service routine vector table.
 ;*
 ;*      This is the ISR vector table at bootup. Used only for the reset vector.
 ;*
@@ -25,7 +25,7 @@
 ;*
 ;*
 ;********************************************************************************
-;* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+;* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ;* You may use this file only in accordance with the license, terms, conditions,
 ;* disclaimers, and limitations in the end user license agreement accompanying
 ;* the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c
index 14bcbf8d..55a20e28 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: Cm3Start.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  Startup code for the ARM CM3.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -52,6 +52,12 @@ CY_ISR(IntDefaultHandler);
     extern void __iar_data_init3 (void);
 #endif  /* (__ARMCC_VERSION) */
 
+#if defined(__GNUC__)
+    #include <errno.h>
+    extern int  errno;
+    extern int  end;
+#endif  /* defined(__GNUC__) */
+
 /* Global variables */
 #if !defined (__ICCARM__)
     CY_NOINIT static uint32 cySysNoInitDataValid;
@@ -76,7 +82,7 @@ cyisraddress CyRamVectors[CY_NUM_VECTORS];
 ********************************************************************************
 *
 * Summary:
-*  This function is called for all interrupts, other than reset, that get
+*  This function is called for all interrupts, other than a reset that gets
 *  called before the system is setup.
 *
 * Parameters:
@@ -95,7 +101,7 @@ CY_ISR(IntDefaultHandler)
     while(1)
     {
         /***********************************************************************
-        * We should never get here. If we do, a serious problem occured, so go
+        * We must not get here. If we do, a serious problem occurs, so go
         * into an infinite loop.
         ***********************************************************************/
     }
@@ -104,7 +110,7 @@ CY_ISR(IntDefaultHandler)
 
 #if defined(__ARMCC_VERSION)
 
-/* Local function for the device reset. */
+/* Local function for device reset. */
 extern void Reset(void);
 
 /* Application entry point. */
@@ -161,7 +167,7 @@ void Reset(void)
 ********************************************************************************
 *
 * Summary:
-*  This function is called imediatly before the users main
+*  This function is called immediately before the users main
 *
 * Parameters:
 *  None
@@ -179,7 +185,7 @@ void $Sub$$main(void)
 
     while (1)
     {
-        /* If main returns it is undefined what we should do. */
+        /* If main returns, it is undefined what we should do. */
     }
 }
 
@@ -193,7 +199,7 @@ extern void __cy_stack(void);
 /* Application entry point. */
 extern int main(void);
 
-/* The static objects constructors initializer */
+/* Static objects constructors initializer */
 extern void __libc_init_array(void);
 
 typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
@@ -211,6 +217,84 @@ extern const char __cy_region_num __attribute__((weak));
 #define __cy_region_num ((size_t)&__cy_region_num)
 
 
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+*  Exit a program without cleaning up files. If your system doesn't provide
+*  this, it is best to avoid linking with subroutines that require it (exit,
+*  system).
+*
+* Parameters:
+*  status: Status caused program exit.
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+    /* Cause divide by 0 exception */
+    int x = status / (int) INT_MAX;
+    x = 4 / x;
+
+    while(1)
+    {
+
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+*  Increase program data space. As malloc and related functions depend on this,
+*  it is useful to have a working implementation. The following suffices for a
+*  standalone system; it exploits the symbol end automatically defined by the
+*  GNU linker.
+*
+* Parameters:
+*  nbytes: The number of bytes requested (if the parameter value is positive)
+*  from the heap or returned back to the heap (if the parameter value is
+*  negative).
+*
+* Return:
+*  None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+    extern int  end;            /* Symbol defined by linker map. Start of free memory (as symbol). */
+    void *      returnValue;
+
+    /* The statically held previous end of the heap, with its initialization. */
+    static void *heapPointer = (void *) &end;                 /* Previous end */
+
+    if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+    {
+        returnValue  = heapPointer;
+        heapPointer += nbytes;
+    }
+    else
+    {
+        errno = ENOMEM;
+        returnValue = (void *) -1;
+    }
+
+    return (returnValue);
+}
+
+
 /*******************************************************************************
 * Function Name: Reset
 ********************************************************************************
@@ -249,17 +333,6 @@ void Reset(void)
     Start_c();
 }
 
-__attribute__((weak))
-void _exit(int status)
-{
-    /* Cause a divide by 0 exception */
-    int x = status / INT_MAX;
-    x = 4 / x;
-
-    while(1)
-    {
-    }
-}
 
 /*******************************************************************************
 * Function Name: Start_c
@@ -267,7 +340,7 @@ void _exit(int status)
 *
 * Summary:
 *  This function handles initializing the .data and .bss sections in
-*  preperation for running standard C code.  Once initialization is complete
+*  preparation for running the standard C code.  Once initialization is complete
 *  it will call main(). This function will never return.
 *
 * Parameters:
@@ -284,7 +357,7 @@ void Start_c(void)
     const struct __cy_region *rptr = __cy_regions;
 
     /* Initialize memory */
-    for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+    for (regions = __cy_region_num; regions != 0u; regions--)
     {
         uint32 *src = (uint32 *)rptr->init;
         uint32 *dst = (uint32 *)rptr->data;
@@ -293,13 +366,18 @@ void Start_c(void)
 
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = *src++;
+            *dst = *src;
+            dst++;
+            src++;
         }
         limit = rptr->zero_size;
         for (count = 0u; count != limit; count += sizeof (uint32))
         {
-            *dst++ = 0u;
+            *dst = 0u;
+            dst++;
         }
+
+        rptr++;
     }
 
     /* Invoke static objects constructors */
@@ -320,8 +398,8 @@ void Start_c(void)
 ********************************************************************************
 *
 * Summary:
-*  This function perform early initializations for the IAR Embedded
-*  Workbench IDE. It is executed in the context of reset interrupt handler
+*  This function performs early initializations for the IAR Embedded
+*  Workbench IDE. It is executed in the context of a reset interrupt handler
 *  before the data sections are initialized.
 *
 * Parameters:
@@ -383,14 +461,14 @@ int __low_level_init(void)
     const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
 #endif  /* defined (__ICCARM__) */
 {
-    INITIAL_STACK_POINTER,   /* The initial stack pointer  0 */
-    #if defined (__ICCARM__) /* The reset handler          1 */
+    INITIAL_STACK_POINTER,   /* Initial stack pointer  0 */
+    #if defined (__ICCARM__) /* Reset handler          1 */
         __iar_program_start,
     #else
         (cyisraddress)&Reset,
     #endif  /* defined (__ICCARM__) */
-    &IntDefaultHandler,      /* The NMI handler            2 */
-    &IntDefaultHandler,      /* The hard fault handler     3 */
+    &IntDefaultHandler,      /* NMI handler            2 */
+    &IntDefaultHandler,      /* Hard fault handler     3 */
 };
 
 #if defined(__ARMCC_VERSION)
@@ -438,7 +516,7 @@ void initialize_psoc(void)
     /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
     CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
 
-    /* Point NVIC at the RAM vector table. */
+    /* Point NVIC at RAM vector table. */
     *CYINT_VECT_TABLE = CyRamVectors;
 
     /* Initialize the configuration registers. */
@@ -446,7 +524,7 @@ void initialize_psoc(void)
 
     #if(0u != DMA_CHANNELS_USED__MASK0)
 
-        /* Setup DMA - only necessary if the design contains a DMA component. */
+        /* Setup DMA - only necessary if design contains DMA component. */
         CyDmacConfigure();
 
     #endif  /* (0u != DMA_CHANNELS_USED__MASK0) */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
index 5ac6ba97..f72c2559 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: CyBootAsmGnu.s
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Assembly routines for GNU as.
 *
 ********************************************************************************
-* Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
index f2e8f940..2c356b3e 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmIar.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for IAR Embedded Workbench IDE.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2013-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -30,7 +30,7 @@
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic. Therefore, to avoid corrupting processor state, it must be the policy 
+;  atomic. Therefore, to avoid a corrupting processor state, it must be the policy 
 ;  that all interrupt routines restore the interrupt enable bits as they were 
 ;  found on entry.
 ;
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
index c10181e7..8753fe17 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
@@ -1,12 +1,12 @@
 ;-------------------------------------------------------------------------------
 ; FILENAME: CyBootAsmRv.s
-; Version 4.0
+; Version 4.20
 ;
 ;  DESCRIPTION:
 ;    Assembly routines for RealView.
 ;
 ;-------------------------------------------------------------------------------
-; Copyright 2010-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2010-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
@@ -110,7 +110,7 @@ byte_4 DCB 0x09
 ;
 ;  Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
 ;  with interrupts still enabled. The test and set of the interrupt bits is not
-;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+;  atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
 ;  corrupting processor state, it must be the policy that all interrupt routines
 ;  restore the interrupt enable bits as they were found on entry.
 ;
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c
index e3858c62..c41fea02 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the DMAC component. The API includes functions for the
@@ -18,10 +18,10 @@
 *  not being used.
 *
 *  This code uses the first byte of each TD to manage the free list of TD's.
-*  The user can over write this once the TD is allocated.
+*  The user can overwrite this once the TD is allocated.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,8 +37,8 @@
 * are initialized. To avoid zeroing, these variables should be initialized
 * properly during segments initialization as well.
 *******************************************************************************/
-static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements in the list */
-static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint8  CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;           /* Current Number of free elements on list */
+static uint8  CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
 static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map of DMA channel ownership */
 
 
@@ -48,7 +48,7 @@ static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0;              /* Bit map
 *
 * Summary:
 *  Creates a linked list of all the TDs to be allocated. This function is called
-*  by the startup code; you do not normally need to call it. You could call this
+*  by the startup code; you do not normally need to call it. You can call this
 *  function if all of the DMA channels are inactive.
 *
 * Parameters:
@@ -72,7 +72,7 @@ void CyDmacConfigure(void)
         CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
     }
 
-    /* Make the last one point to zero. */
+    /* Make last one point to zero. */
     CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
 }
 
@@ -102,8 +102,8 @@ void CyDmacConfigure(void)
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 uint8 CyDmacError(void) 
@@ -131,15 +131,15 @@ uint8 CyDmacError(void)
 *   Set to 1 when an access is attempted to an invalid address.
 *
 *  DMAC_BUS_TIMEOUT:
-*   Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+*   Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
 *   are determined by the BUS_TIMEOUT field in the PHUBCFG register.
 *
 * Return:
 *  None
 *
 * Theory:
-*  Once an error occurs the error bits are sticky and are only cleared by a
-*  write 1 to the error register.
+*  Once an error occurs the error bits are sticky and are only cleared by 
+*  writing 1 to the error register.
 *
 *******************************************************************************/
 void CyDmacClearError(uint8 error) 
@@ -153,7 +153,7 @@ void CyDmacClearError(uint8 error)
 ********************************************************************************
 *
 * Summary:
-*  When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the
+*  When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
 *  address of the error is written to the error address register and can be read
 *  with this function.
 *
@@ -198,12 +198,12 @@ uint8 CyDmaChAlloc(void)
     /* Enter critical section! */
     interruptState = CyEnterCriticalSection();
 
-    /* Look for a free channel. */
+    /* Look for free channel. */
     for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
     {
         if(0uL == (CyDmaChannels & channel))
         {
-            /* Mark the channel as used. */
+            /* Mark channel as used. */
             CyDmaChannels |= channel;
             break;
         }
@@ -249,7 +249,7 @@ cystatus CyDmaChFree(uint8 chHandle)
         /* Enter critical section */
         interruptState = CyEnterCriticalSection();
 
-        /* Clear the bit mask that keeps track of ownership. */
+        /* Clear bit mask that keeps track of ownership. */
         CyDmaChannels &= ~(((uint32) 1u) << chHandle);
 
         /* Exit critical section */
@@ -277,10 +277,10 @@ cystatus CyDmaChFree(uint8 chHandle)
 *   Preserves the original TD state when the TD has completed. This parameter
 *   applies to all TDs in the channel.
 *
-*   0 - When a TD is completed, the DMAC leaves the TD configuration values in
+*   0 - When TD is completed, the DMAC leaves the TD configuration values in
 *   their current state, and does not restore them to their original state.
 *
-*   1 - When a TD is completed, the DMAC restores the original configuration
+*   1 - When TD is completed, the DMAC restores the original configuration
 *   values of the TD.
 *
 *  When preserveTds is set, the TD slot that equals the channel number becomes
@@ -309,14 +309,14 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds)
     {
         if (0u != preserveTds)
         {
-            /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
-            *  preserve the original TD chain
+            /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+            *  preserve original TD chain
             */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
         }
         else
         {
-            /* Store the intermediate and final TD states on top of the original TD chain */
+            /* Store intermediate and final TD states on top of original TD chain */
             CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
         }
 
@@ -365,7 +365,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
         /* Disable channel */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
 
-        /* Store the intermediate and final TD states on top of the original TD chain */
+        /* Store intermediate and final TD states on top of original TD chain */
         CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
         status = CYRET_SUCCESS;
     }
@@ -379,7 +379,7 @@ cystatus CyDmaChDisable(uint8 chHandle)
 ********************************************************************************
 *
 * Summary:
-*  Clears pending DMA data request.
+*  Clears pending the DMA data request.
 *
 * Parameters:
 *  uint8 chHandle:
@@ -518,7 +518,7 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
 *   A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
 *
 *  uint8 startTd:
-*   The index of TD to set as the first TD associated with the channel. Zero is
+*   Set the TD index as the first TD associated with the channel. Zero is
 *   a valid TD index.
 *
 * Return:
@@ -759,13 +759,13 @@ uint8 CyDmaTdAllocate(void)
 
     if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
     {
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         element = CyDmaTdFreeIndex;
 
         /* Decrement the count. */
         CyDmaTdCurrentNumber--;
 
-        /* Update the next available pointer. */
+        /* Update next available pointer. */
         CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
     }
 
@@ -798,7 +798,7 @@ void CyDmaTdFree(uint8 tdHandle)
         /* Enter critical section! */
         uint8 interruptState = CyEnterCriticalSection();
 
-        /* Get pointer to the Next available. */
+        /* Get pointer to Next available. */
         CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
 
         /* Set new Next Available. */
@@ -942,9 +942,9 @@ cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nex
 *  CYRET_BAD_PARAM if tdHandle is invalid.
 *
 * Side Effects:
-*  If a TD has a transfer count of N and is executed, the transfer count becomes
+*  If TD has a transfer count of N and is executed, the transfer count becomes
 *  0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-*  request for indefinite transfer. Be careful when requesting a TD with a
+*  request for indefinite transfer. Be careful when requesting TD with a
 *  transfer count of zero.
 *
 *******************************************************************************/
@@ -955,25 +955,25 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 *
 
     if(tdHandle < CY_DMA_NUMBEROF_TDS)
     {
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != transferCount)
         {
-            /* Get the 12 bits of the transfer count */
+            /* Get 12 bits of transfer count */
             reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
             *transferCount = 0x0FFFu & CY_GET_REG16(convert);
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != nextTd)
         {
-            /* Get the Next TD pointer */
+            /* Get Next TD pointer */
             *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
         }
 
-        /* If we have a pointer */
+        /* If we have pointer */
         if(NULL != configuration)
         {
-            /* Get the configuration the TD */
+            /* Get configuration TD */
             *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
         }
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h
index 5dfac11a..f78f3e32 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyDmac.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the DMA Controller.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -116,7 +116,7 @@ typedef struct dmac_tdmem2_struct
 
 #define CY_DMA_TD_SIZE              0x08u
 
-/* The "u" was removed as workaround for Keil compiler bug */
+/* "u" was removed as workaround for Keil compiler bug */
 #define CY_DMA_TD_SWAP_EN           0x80
 #define CY_DMA_TD_SWAP_SIZE4        0x40
 #define CY_DMA_TD_AUTO_EXEC_NEXT    0x20
@@ -178,7 +178,18 @@ typedef struct dmac_tdmem2_struct
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define DMA_INVALID_CHANNEL         (CY_DMA_INVALID_CHANNEL)
 #define DMA_INVALID_TD              (CY_DMA_INVALID_TD)
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c
index 6f27d8c0..fc1eee33 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the FLASH/EEPROM.
@@ -13,7 +13,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,9 +21,12 @@
 
 #include "CyFlash.h"
 
+/*  The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS                 (1u)
+
 
 /*******************************************************************************
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
 * The first byte is the sign of the temperature (0 = negative, 1 = positive).
 * The second byte is the magnitude.
 *******************************************************************************/
@@ -35,6 +38,7 @@ uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 
 
 static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
 
 
 /*******************************************************************************
@@ -53,13 +57,48 @@ static cystatus CySetTempInt(void);
 *******************************************************************************/
 void CyFlash_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or eeprom to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable flash. Active flash macros consume current, but re-enabling a
+    * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+    * macro during that time, it will be stalled. This bit allows the flash to
+    * be enabled even if the CPU is disabled, which allows a quicker return to
+    * code execution.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
 
-    CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -83,11 +122,14 @@ void CyFlash_Start(void)
 *******************************************************************************/
 void CyFlash_Stop(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -97,7 +139,7 @@ void CyFlash_Stop(void)
 *
 * Summary:
 *  Sends a command to the SPC to read the die temperature. Sets a global value
-*  used by the Write functions. This function must be called once before
+*  used by the Write function. This function must be called once before
 *  executing a series of Flash writing functions.
 *
 * Parameters:
@@ -153,13 +195,65 @@ static cystatus CySetTempInt(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS - if successful
+*   CYRET_LOCKED  - if Flash writing already in use
+*   CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void) 
+{
+    cystatus status;
+
+    /* Make sure SPC is powered */
+    CySpcStart();
+
+    if(CySpcLock() == CYRET_SUCCESS)
+    {
+        status = CySpcGetAlgorithm();
+
+        if(CYRET_STARTED == status)
+        {
+            while(CY_SPC_BUSY)
+            {
+                /* Spin until idle. */
+                CyDelayUs(1u);
+            }
+
+            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+            {
+                status = CYRET_SUCCESS;
+            }
+        }
+        CySpcUnlock();
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return (status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySetTemp
 ********************************************************************************
 *
 * Summary:
-*  This is a wraparound for CySetTempInt(). It is used to return second
-*  successful read of temperature value.
+*  This is a wraparound for CySetTempInt(). It is used to return the second
+*  successful read of the temperature value.
 *
 * Parameters:
 *  None
@@ -171,14 +265,14 @@ static cystatus CySetTempInt(void)
 *   CYRET_UNKNOWN if there was an SPC error.
 *
 *  uint8 dieTemperature[2]:
-*   Holds die temperature for the flash writting algorithm. The first byte is
+*   Holds the die temperature for the flash writing algorithm. The first byte is
 *   the sign of the temperature (0 = negative, 1 = positive). The second byte is
 *   the magnitude.
 *
 *******************************************************************************/
 cystatus CySetTemp(void) 
 {
-    cystatus status = CySetTempInt();
+    cystatus status = CyFlashGetSpcAlgorithm();
 
     if(status == CYRET_SUCCESS)
     {
@@ -195,12 +289,12 @@ cystatus CySetTemp(void)
 *
 * Summary:
 *  Sets the user supplied temporary buffer to store SPC data while performing
-*  flash and EEPROM commands. This buffer is only necessary when Flash ECC is
+*  Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
 *  disabled.
 *
 * Parameters:
 *  buffer:
-*   Address of block of memory to store temporary memory. The size of the block
+*   The address of a block of memory to store temporary memory. The size of the block
 *   of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
 *
 * Return:
@@ -219,10 +313,12 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
         if(NULL == buffer)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_BAD_PARAM;
         }
         else if(CySpcLock() != CYRET_SUCCESS)
         {
+            rowBuffer = rowBuffer;
             status = CYRET_LOCKED;
         }
         else
@@ -233,7 +329,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 
     #else
 
-        /* To supress the warning */
+        /* To suppress warning */
         buffer = buffer;
 
     #endif  /* (CYDEV_ECC_ENABLE == 0u) */
@@ -242,120 +338,48 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 }
 
 
-#if(CYDEV_ECC_ENABLE == 1)
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *  Sends a command to the SPC to load and program a row of data in
-    *  Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID:    ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress: rowAddress of flash row to program.
-    *  rowData:    Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint16 rowSize;
-        cystatus status;
-
-        rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
-        status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
-        return(status);
-    }
-
-#else
-
-    /*******************************************************************************
-    * Function Name: CyWriteRowData
-    ********************************************************************************
-    *
-    * Summary:
-    *   Sends a command to the SPC to load and program a row of data in
-    *   Flash or EEPROM.
-    *
-    * Parameters:
-    *  arrayID      : ID of the array to write.
-    *   The type of write, Flash or EEPROM, is determined from the array ID.
-    *   The arrays in the part are sequential starting at the first ID for the
-    *   specific memory type. The array ID for the Flash memory lasts from 0x00 to
-    *   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
-    *  rowAddress   : rowAddress of flash row to program.
-    *  rowData      : Array of bytes to write.
-    *
-    * Return:
-    *  status:
-    *   CYRET_SUCCESS if successful.
-    *   CYRET_LOCKED if the SPC is already in use.
-    *   CYRET_CANCELED if command not accepted
-    *   CYRET_UNKNOWN if there was an SPC error.
-    *
-    *******************************************************************************/
-    cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
-    {
-        uint8 i;
-        uint32 offset;
-        uint16 rowSize;
-        cystatus status;
-
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
-            {
-                rowSize = CYDEV_EEPROM_ROW_SIZE;
-            }
-            else
-            {
-                rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
-
-                /* Save the ECC area. */
-                offset = CYDEV_ECC_BASE +
-                        ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
-                        ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
-
-                for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
-                {
-                    *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-                }
-            }
-
-            /* Copy the rowdata to the temporary buffer. */
-        #if(CY_PSOC3)
-            (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
-        #else
-            (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
-        #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+*  Sends a command to the SPC to load and program a row of data in
+*  Flash or EEPROM.
+*
+* Parameters:
+*  arrayID:    ID of the array to write.
+*   The type of write, Flash or EEPROM, is determined from the array ID.
+*   The arrays in the part are sequential starting at the first ID for the
+*   specific memory type. The array ID for the Flash memory lasts from 0x00 to
+*   0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+*  rowAddress: rowAddress of flash row to program.
+*  rowData:    Array of bytes to write.
+*
+* Return:
+*  status:
+*   CYRET_SUCCESS if successful.
+*   CYRET_LOCKED if the SPC is already in use.
+*   CYRET_CANCELED if command not accepted
+*   CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) 
+{
+    uint16 rowSize;
+    cystatus status;
 
-        return(status);
-    }
+    rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+    status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
 
-#endif /* (CYDEV_ECC_ENABLE == 0u) */
+    return(status);
+}
 
 
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
 #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
 
     /*******************************************************************************
@@ -363,7 +387,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a command to the SPC to load and program a row of config data in flash.
+    *  Sends a command to the SPC to load and program a row of config data in the Flash.
     *  This function is only valid for Flash array IDs (not for EEPROM).
     *
     * Parameters:
@@ -371,8 +395,8 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     *   The arrays in the part are sequential starting at the first ID for the
     *   specific memory type. The array ID for the Flash memory lasts
     *   from 0x00 to 0x3F.
-    *  rowAddress:   Address of the sector to erase.
-    *  rowECC:       Array of bytes to write.
+    *  rowAddress:   The address of the sector to erase.
+    *  rowECC:       The array of bytes to write.
     *
     * Return:
     *  status:
@@ -385,42 +409,9 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
     cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
     
     {
-        uint32 offset;
-        uint16 i;
         cystatus status;
 
-        /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
-        if(NULL != rowBuffer)
-        {
-            /* Read the existing flash data. */
-            offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
-                     ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
-
-            #if (CYDEV_FLS_BASE != 0u)
-                offset += CYDEV_FLS_BASE;
-            #endif  /* (CYDEV_FLS_BASE != 0u) */
-
-            for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
-            {
-                rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
-            }
-
-            #if(CY_PSOC3)
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (void *)(uint32)rowECC,
-                              (int16)CYDEV_ECC_ROW_SIZE);
-            #else
-                (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
-                              (const void *)rowECC,
-                              CYDEV_ECC_ROW_SIZE);
-            #endif  /* (CY_PSOC3) */
-
-            status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
-        }
-        else
-        {
-            status = CYRET_UNKNOWN;
-        }
+        status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
 
         return (status);
     }
@@ -433,7 +424,7 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 * Function Name: CyWriteRowFull
 ********************************************************************************
 * Summary:
-*  Sends a command to the SPC to load and program a row of data in flash.
+*  Sends a command to the SPC to load and program a row of data in the Flash.
 *  rowData array is expected to contain Flash and ECC data if needed.
 *
 * Parameters:
@@ -452,63 +443,107 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
 cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
         
 {
-    cystatus status;
+    cystatus status = CYRET_SUCCESS;
 
-    if(CySpcLock() == CYRET_SUCCESS)
+    if((arrayId <=  CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS  + CY_SPC_FIRST_FLASH_ARRAYID)))
     {
-        /* Load row data into SPC internal latch */
-        status = CySpcLoadRow(arrayId, rowData, rowSize);
+        status = CYRET_BAD_PARAM;
+    }
 
-        if(CYRET_STARTED == status)
+    if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+    if(arrayId <=  CY_SPC_LAST_FLASH_ARRAYID)
+    {
+        /* Flash */
+        if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
         {
-            while(CY_SPC_BUSY)
-            {
-                /* Wait for SPC to finish and get SPC status */
-                CyDelayUs(1u);
-            }
+            status = CYRET_BAD_PARAM;
+        }
+    }
+    else
+    {
+        /* EEPROM */
+        if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+        {
+            status = CYRET_BAD_PARAM;
+        }
 
-            /* Hide SPC status */
-            if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-            {
-                status = CYRET_SUCCESS;
-            }
-            else
-            {
-                status = CYRET_UNKNOWN;
-            }
+        if(CY_EEPROM_SIZEOF_ROW != rowSize)
+        {
+            status = CYRET_BAD_PARAM;
+        }
+    }
 
-            if(CYRET_SUCCESS == status)
+    if(rowData == NULL)
+    {
+        status = CYRET_BAD_PARAM;
+    }
+
+
+    if(status == CYRET_SUCCESS)
+    {
+        if(CySpcLock() == CYRET_SUCCESS)
+        {
+            /* Load row data into SPC internal latch */
+            status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+            if(CYRET_STARTED == status)
             {
-                /* Erase and program flash with the data from SPC interval latch */
-                status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+                while(CY_SPC_BUSY)
+                {
+                    /* Wait for SPC to finish and get SPC status */
+                    CyDelayUs(1u);
+                }
 
-                if(CYRET_STARTED == status)
+                /* Hide SPC status */
+                if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
                 {
-                    while(CY_SPC_BUSY)
-                    {
-                        /* Wait for SPC to finish and get SPC status */
-                        CyDelayUs(1u);
-                    }
+                    status = CYRET_SUCCESS;
+                }
+                else
+                {
+                    status = CYRET_UNKNOWN;
+                }
 
-                    /* Hide SPC status */
-                    if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
-                    {
-                        status = CYRET_SUCCESS;
-                    }
-                    else
+                if(CYRET_SUCCESS == status)
+                {
+                    /* Erase and program flash with data from SPC interval latch */
+                    status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+                    if(CYRET_STARTED == status)
                     {
-                        status = CYRET_UNKNOWN;
+                        while(CY_SPC_BUSY)
+                        {
+                            /* Wait for SPC to finish and get SPC status */
+                            CyDelayUs(1u);
+                        }
+
+                        /* Hide SPC status */
+                        if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+                        {
+                            status = CYRET_SUCCESS;
+                        }
+                        else
+                        {
+                            status = CYRET_UNKNOWN;
+                        }
                     }
                 }
             }
-
+            CySpcUnlock();
+        }   /* if(CySpcLock() == CYRET_SUCCESS) */
+        else
+        {
+            status = CYRET_LOCKED;
         }
-
-        CySpcUnlock();
-    }
-    else
-    {
-        status = CYRET_LOCKED;
     }
 
     return(status);
@@ -521,9 +556,9 @@ cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, u
 *
 * Summary:
 *  Sets the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash. This function must be called before increasing CPU
-*  clock frequency. It can optionally be called after lowering CPU clock
-*  frequency in order to improve CPU performance.
+*  coming back from the Flash. This function must be called before increasing the CPU
+*  clock frequency. It can optionally be called after lowering the CPU clock
+*  frequency in order to improve the CPU performance.
 *
 * Parameters:
 *  uint8 freq:
@@ -542,55 +577,42 @@ void CyFlash_SetWaitCycles(uint8 freq)
 
     /***************************************************************************
     * The number of clock cycles the cache will wait before it samples data
-    * coming back from Flash must be equal or greater to to the CPU frequency
+    * coming back from the Flash must be equal or greater to to the CPU frequency
     * outlined in clock cycles.
     ***************************************************************************/
 
-    #if (CY_PSOC3)
-
-        if (freq <= 22u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 44u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC3) */
-
-
-    #if (CY_PSOC5)
-
-        if (freq <= 16u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 33u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else if (freq <= 50u)
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-        else
-        {
-            *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
-                ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
-        }
-
-    #endif  /* (CY_PSOC5) */
+    if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_1_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_2_VALUE_MASK;
+    }
+    else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_3_VALUE_MASK;
+    }
+#if (CY_PSOC5)
+    else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_4_VALUE_MASK;
+    }
+    else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+    {
+        CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+                                    CY_FLASH_CACHE_WS_5_VALUE_MASK;
+    }
+#endif  /* (CY_PSOC5) */
+    else
+    {
+        /* Halt CPU in debug mode if frequency is invalid */
+        CYASSERT(0u != 0u);
+    }
 
     /* Restore global interrupt enable state */
     CyExitCriticalSection(interruptState);
@@ -613,11 +635,45 @@ void CyFlash_SetWaitCycles(uint8 freq)
 *******************************************************************************/
 void CyEEPROM_Start(void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+    uint8 interruptState;
+
+    interruptState = CyEnterCriticalSection();
+
+
+    /***************************************************************************
+    * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+    * is required for the SPC to function.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG0_REG    |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+    CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+
+    /***************************************************************************
+    * The wake count defines the number of Bus Clock cycles it takes for the
+    * flash or EEPROM to wake up from a low power mode independent of the chip
+    * power mode. Wake up time for these blocks is 5 us.
+    * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+    * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+    * This register needs to be written with a value dependent on the Bus Clock
+    * frequency so that the duration of the cycles is equal to or greater than
+    * the 5 us delay required.
+    ***************************************************************************/
+    CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+    /***************************************************************************
+    * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+    * the EE will not acknowledge a PHUB request.
+    ***************************************************************************/
+    CY_FLASH_PM_ACT_CFG12_REG    |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+    CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+    while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+    {
+        /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+    }
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -637,11 +693,14 @@ void CyEEPROM_Start(void)
 *******************************************************************************/
 void CyEEPROM_Stop (void) 
 {
-    /* Active Power Mode */
-    *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    uint8 interruptState;
 
-    /* Standby Power Mode */
-    *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+    interruptState = CyEnterCriticalSection();
+
+    CY_FLASH_PM_ACT_CFG12_REG    &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+    CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+    CyExitCriticalSection(interruptState);
 }
 
 
@@ -661,12 +720,12 @@ void CyEEPROM_Stop (void)
 *******************************************************************************/
 void CyEEPROM_ReadReserve(void) 
 {
-    /* Make a request for PHUB to have access */
-    *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+    /* Make request for PHUB to have access */
+    CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
 
-    while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
+    while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
     {
-        /* Wait for acknowledgement from PHUB */
+        /* Wait for acknowledgment from PHUB */
     }
 }
 
@@ -687,7 +746,7 @@ void CyEEPROM_ReadReserve(void)
 *******************************************************************************/
 void CyEEPROM_ReadRelease(void) 
 {
-    *CY_FLASH_EE_SCR_PTR |= 0x00u;
+    CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
 }
 
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h
index 002b2ebf..b8a18c2f 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyFlash.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides the function definitions for the FLASH/EEPROM.
@@ -10,7 +10,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,13 +41,19 @@ extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];
 #define CY_FLASH_NUMBER_ROWS        (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
 #define CY_FLASH_NUMBER_ARRAYS      (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
 
+#if(CYDEV_ECC_ENABLE == 0)
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+    #define CY_FLASH_SIZEOF_FULL_ROW     (CY_FLASH_SIZEOF_ROW)
+#endif  /* (CYDEV_ECC_ENABLE == 0) */
 #define CY_EEPROM_BASE              (CYDEV_EE_BASE)
 #define CY_EEPROM_SIZE              (CYDEV_EE_SIZE)
 #define CY_EEPROM_SIZEOF_ARRAY      (CYDEV_EEPROM_SECTOR_SIZE)
 #define CY_EEPROM_SIZEOF_ROW        (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS       (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS       (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
 #define CY_EEPROM_NUMBER_ARRAYS     (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-
+#define CY_EEPROM_NUMBER_SECTORS    (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR     (CYDEV_EEPROM_SECTOR_SIZE)
 
 #if !defined(CYDEV_FLS_BASE)
     #define CYDEV_FLS_BASE    CYDEV_FLASH_BASE
@@ -85,13 +91,29 @@ void CyEEPROM_ReadRelease(void) ;
 /***************************************
 *     Registers
 ***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG             (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR             (  (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG          (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR          (  (reg8 *) CYREG_PM_STBY_CFG0)
+
 /* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_REG            (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR            (  (reg8 *) CYREG_PM_ACT_CFG12)
 
 /* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_REG         (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR         (  (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG      (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR      (  (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG            (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR            (  (reg8 *) CYREG_SPC_FM_EE_CR)
 
 
 /* Cache Control Register */
@@ -119,35 +141,64 @@ void CyEEPROM_ReadRelease(void) ;
 ***************************************/
 
 /* Power Mode Masks */
-#define CY_FLASH_PM_EE_MASK                 (0x10u)
-#define CY_FLASH_PM_FLASH_MASK              (0x01u)
 
-/* Frequency Constants */
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE             (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE          (0x10u)
+
+/* Enable Flash */
 #if (CY_PSOC3)
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x01u)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x01u)
+#else
+    #define CY_FLASH_PM_ACT_CFG12_EN_FM         (0x0Fu)
+    #define CY_FLASH_PM_ALTACT_CFG12_EN_FM      (0x0Fu)
+#endif  /* (CY_PSOC3) */
+
 
-    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
-    #define CY_FLASH_GREATER_44MHz              (0x03u)
 
+/* Frequency Constants */
+#if (CY_PSOC3)
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xC0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (22u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (44u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (67u)
 #endif  /* (CY_PSOC3) */
 
 #if (CY_PSOC5)
-
-    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
-    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
-    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
-    #define CY_FLASH_GREATER_51MHz              (0x00u)
-
+    #define CY_FLASH_CACHE_WS_VALUE_MASK        (0xE0u)
+    #define CY_FLASH_CACHE_WS_1_VALUE_MASK      (0x40u)
+    #define CY_FLASH_CACHE_WS_2_VALUE_MASK      (0x80u)
+    #define CY_FLASH_CACHE_WS_3_VALUE_MASK      (0xC0u)
+    #define CY_FLASH_CACHE_WS_4_VALUE_MASK      (0x00u)
+    #define CY_FLASH_CACHE_WS_5_VALUE_MASK      (0x20u)
+
+    #define CY_FLASH_CACHE_WS_1_FREQ_MAX        (16u)
+    #define CY_FLASH_CACHE_WS_2_FREQ_MAX        (33u)
+    #define CY_FLASH_CACHE_WS_3_FREQ_MAX        (50u)
+    #define CY_FLASH_CACHE_WS_4_FREQ_MAX        (67u)
+    #define CY_FLASH_CACHE_WS_5_FREQ_MAX        (83u)
 #endif  /* (CY_PSOC5) */
 
 #define CY_FLASH_CYCLES_MASK_SHIFT              (0x06u)
 #define CY_FLASH_CYCLES_MASK                    ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-#define CY_FLASH_EE_STARTUP_DELAY               (5u)
 
 #define CY_FLASH_EE_SCR_AHB_EE_REQ              (0x01u)
 #define CY_FLASH_EE_SCR_AHB_EE_ACK              (0x02u)
 
 
+#define CY_FLASH_EE_EE_AWAKE                    (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ       (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC         (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC      (0x08u)
 
 /* Default values for getting temperature. */
 
@@ -167,7 +218,42 @@ void CyEEPROM_ReadRelease(void) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+    #define CY_FLASH_LESSER_OR_EQUAL_16MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_33MHz      (0x02u)
+    #define CY_FLASH_LESSER_OR_EQUAL_50MHz      (0x03u)
+    #define CY_FLASH_GREATER_51MHz              (0x00u)
+#endif  /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+    #define CY_FLASH_LESSER_OR_EQUAL_22MHz      (0x01u)
+    #define CY_FLASH_LESSER_OR_EQUAL_44MHz      (0x02u)
+    #define CY_FLASH_GREATER_44MHz              (0x03u)
+#endif  /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG         (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR         (  (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG      (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR      (  (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK                 (0x10u)
+#define CY_FLASH_PM_FLASH_MASK              (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
 *******************************************************************************/
 #define FLASH_SIZE                  (CY_FLASH_SIZE)
 #define FLASH_SIZEOF_SECTOR         (CY_FLASH_SIZEOF_ARRAY)
@@ -177,12 +263,10 @@ void CyEEPROM_ReadRelease(void) ;
 #define EEPROM_SIZEOF_SECTOR        (CY_EEPROM_SIZEOF_ARRAY)
 #define EEPROM_NUMBER_ROWS          (CY_EEPROM_NUMBER_ROWS)
 #define EEPROM_NUMBER_SECTORS       (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_NUMBER_SECTORS    (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_SIZEOF_SECTOR     (CY_EEPROM_SIZEOF_ARRAY)
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
 *******************************************************************************/
 #define FLASH_CYCLES_PTR            (CY_FLASH_CONTROL_PTR)
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c
index 5278bdf1..8d3c1c4f 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c
@@ -1,16 +1,16 @@
 /*******************************************************************************
 * File Name: CyLib.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   Provides system API for the clocking, interrupts and watchdog timer.
+*   Provides a system API for the clocking, interrupts and watchdog timer.
 *
 *  Note:
 *   Documentation of the API's in this file is located in the
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -49,6 +49,12 @@ static uint8 CyUSB_PowerOnCheck(void)  ;
 static void CyIMO_SetTrimValue(uint8 freq) ;
 static void CyBusClk_Internal_SetDivider(uint16 divider);
 
+#if(CY_PSOC5)
+	static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+    static void CySysTickServiceCallbacks(void);
+    uint32 CySysTickInitVar = 0u;
+#endif  /* (CY_PSOC5) */
+
 
 /*******************************************************************************
 * Function Name: CyPLL_OUT_Start
@@ -72,7 +78,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider);
 *     clock can still be used.
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -95,7 +101,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
     uint8 pmTwCfg2State;
 
 
-    /* Enables the PLL circuit  */
+    /* Enables PLL circuit  */
     CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
 
     if(wait != 0u)
@@ -111,7 +117,7 @@ cystatus CyPLL_OUT_Start(uint8 wait)
 
         while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
             if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
             {
                 if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
@@ -180,11 +186,11 @@ void CyPLL_OUT_Stop(void)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -235,11 +241,11 @@ void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -279,7 +285,7 @@ void CyPLL_OUT_SetSource(uint8 source)
 *  None
 *
 * Side Effects:
-*  If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+*  If wait is enabled: This function uses the Fast Time Wheel to time the wait.
 *  Any other use of the Fast Time Wheel will be stopped during the period of
 *  this function and then restored. This function also uses the 100 KHz ILO.
 *  If not enabled, this function will enable the 100 KHz ILO for the period of
@@ -305,7 +311,7 @@ void CyIMO_Start(uint8 wait)
 
     if(0u != wait)
     {
-        /* Need to turn on the 100KHz ILO if it happens to not already be running.*/
+        /* Need to turn on 100KHz ILO if it happens to not already be running.*/
         ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
         pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
         pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
@@ -314,7 +320,7 @@ void CyIMO_Start(uint8 wait)
 
         while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
         {
-            /* Wait for the interrupt status */
+            /* Wait for interrupt status */
         }
 
         if(0u == ilo100KhzEnable)
@@ -442,7 +448,7 @@ static void CyIMO_SetTrimValue(uint8 freq)
         /* If USB is powered */
         if(usbPowerOn == 1u)
         {
-            /* Lock the USB Oscillator */
+            /* Lock USB Oscillator */
             CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
         }
         break;
@@ -477,11 +483,11 @@ static void CyIMO_SetTrimValue(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution results in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When the USB setting is chosen, the USB clock locking circuit is enabled.
@@ -495,15 +501,15 @@ void CyIMO_SetFreq(uint8 freq)
     uint8 nextFreq;
 
     /***************************************************************************
-    * When changing the IMO frequency the Trim values must also be set
+    * If the IMO frequency is changed,the Trim values must also be set
     * accordingly.This requires reading the current frequency. If the new
-    * frequency is faster, then set the new trim and then change the frequency,
-    * otherwise change the frequency and then set the new trim values.
+    * frequency is faster, then set a new trim and then change the frequency,
+    * otherwise change the frequency and then set new trim values.
     ***************************************************************************/
 
     currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
 
-    /* Check if the requested frequency is USB. */
+    /* Check if requested frequency is USB. */
     nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
 
     switch (currentFreq)
@@ -545,11 +551,11 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq >= currentFreq)
     {
-        /* Set the new trim first */
+        /* Set new trim first */
         CyIMO_SetTrimValue(freq);
     }
 
-    /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+    /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
     switch(freq)
     {
     case CY_IMO_FREQ_3MHZ:
@@ -599,7 +605,7 @@ void CyIMO_SetFreq(uint8 freq)
         break;
     }
 
-    /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */
+    /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
     if (freq == CY_IMO_FREQ_USB)
     {
         CyIMO_EnableDoubler();
@@ -611,7 +617,7 @@ void CyIMO_SetFreq(uint8 freq)
 
     if (nextFreq < currentFreq)
     {
-        /* Set the new trim after setting the frequency */
+        /* Set the trim after setting frequency */
         CyIMO_SetTrimValue(freq);
     }
 }
@@ -625,7 +631,7 @@ void CyIMO_SetFreq(uint8 freq)
 *  Sets the source of the clock output from the IMO block.
 *
 *  The output from the IMO is by default the IMO itself. Optionally the MHz
-*  Crystal or a DSI input can be the source of the IMO output instead.
+*  Crystal or DSI input can be the source of the IMO output instead.
 *
 * Parameters:
 *   source: CY_IMO_SOURCE_DSI to set the DSI as source.
@@ -636,11 +642,11 @@ void CyIMO_SetFreq(uint8 freq)
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -687,7 +693,7 @@ void CyIMO_SetSource(uint8 source)
 *******************************************************************************/
 void CyIMO_EnableDoubler(void) 
 {
-    /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */
+    /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
     CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
 }
 
@@ -733,11 +739,11 @@ void CyIMO_DisableDoubler(void)
 *  The current source and the new source must both be running and stable before
 *  calling this function.
 *
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -757,18 +763,18 @@ void CyMasterClk_SetSource(uint8 source)
 *
 * Parameters:
 *  uint8 divider:
-*   Valid range [0-255]. The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   The valid range is [0-255]. The clock will be divided by this value + 1.
+*   For example to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *  When changing the Master or Bus clock divider value from div-by-n to div-by-1
@@ -787,12 +793,12 @@ void CyMasterClk_SetDivider(uint8 divider)
 ********************************************************************************
 *
 * Summary:
-*  Function used by CyBusClk_SetDivider(). For internal use only.
+*  The function used by CyBusClk_SetDivider(). For internal use only.
 *
 * Parameters:
 *   divider: Valid range [0-65535].
 *   The clock will be divided by this value + 1.
-*   For example to divide by 2 this parameter should be set to 1.
+*   For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
@@ -807,7 +813,7 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
     /* Enable mask bits to enable shadow loads */
     CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
 
-    /* Update Shadow Divider Value Register with the new divider */
+    /* Update Shadow Divider Value Register with new divider */
     CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
     CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
 
@@ -827,21 +833,21 @@ static void CyBusClk_Internal_SetDivider(uint16 divider)
 ********************************************************************************
 *
 * Summary:
-*  Sets the divider value used to generate Bus Clock.
+*  Sets the divider value used to generate the Bus Clock.
 *
 * Parameters:
 *  divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-*  For example to divide by 2 this parameter should be set to 1.
+*  For example, to divide this parameter by two should be set to 1.
 *
 * Return:
 *  None
 *
 * Side Effects:
-*  If as result of this function execution the CPU clock frequency is increased
+*  If this function execution resulted in the CPU clock frequency increasing,
 *  then the number of clock cycles the cache will wait before it samples data
-*  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-*  with appropriate parameter. It can be optionally called if CPU clock
-*  frequency is lowered in order to improve CPU performance.
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
 *  See CyFlash_SetWaitCycles() description for more information.
 *
 *******************************************************************************/
@@ -853,13 +859,13 @@ void CyBusClk_SetDivider(uint16 divider)
 
     interruptState = CyEnterCriticalSection();
 
-    /* Work around to set the bus clock divider value */
+    /* Work around to set bus clock divider value */
     busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
     busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
 
     if ((divider == 0u) || (busClkDiv == 0u))
     {
-        /* Save away the master clock divider value */
+        /* Save away master clock divider value */
         masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
 
         if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
@@ -870,7 +876,7 @@ void CyBusClk_SetDivider(uint16 divider)
 
         if (divider == 0u)
         {
-            /* Set the SSS bit and the divider register desired value */
+            /* Set SSS bit and divider register desired value */
             CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
             CyBusClk_Internal_SetDivider(divider);
         }
@@ -880,7 +886,7 @@ void CyBusClk_SetDivider(uint16 divider)
             CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
         }
 
-        /* Restore the master clock */
+        /* Restore master clock */
         CyMasterClk_SetDivider(masterClkDiv);
     }
     else
@@ -904,17 +910,17 @@ void CyBusClk_SetDivider(uint16 divider)
     *
     * Parameters:
     *  divider: Valid range [0-15]. The clock will be divided by this value + 1.
-    *  For example to divide by 2 this parameter should be set to 1.
+    *  For example, to divide this parameter by two should be set to 1.
     *
     * Return:
     *  None
     *
     * Side Effects:
-    *  If as result of this function execution the CPU clock frequency is increased
-    *  then the number of clock cycles the cache will wait before it samples data
-    *  coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-    *  with appropriate parameter. It can be optionally called if CPU clock
-    *  frequency is lowered in order to improve CPU performance.
+    *  If this function execution resulted in the CPU clock frequency increasing,
+*  then the number of clock cycles the cache will wait before it samples data
+*  coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+*  with an appropriate parameter. It can be optionally called if the CPU clock
+*  frequency is lowered in order to improve the CPU performance.
     *  See CyFlash_SetWaitCycles() description for more information.
     *
     *******************************************************************************/
@@ -972,7 +978,7 @@ void CyUsbClk_SetSource(uint8 source)
 *******************************************************************************/
 void CyILO_Start1K(void) 
 {
-    /* Set the bit 1 of ILO RS */
+    /* Set bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
 }
 
@@ -984,7 +990,7 @@ void CyILO_Start1K(void)
 * Summary:
 *  Disables the ILO 1 KHz oscillator.
 *
-*  Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power
+*  Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
 *  mode APIs are expected to be used. For more information, refer to the Power
 *  Management section of this document.
 *
@@ -1000,7 +1006,7 @@ void CyILO_Start1K(void)
 *******************************************************************************/
 void CyILO_Stop1K(void) 
 {
-    /* Clear the bit 1 of ILO RS */
+    /* Clear bit 1 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
 }
 
@@ -1064,7 +1070,7 @@ void CyILO_Stop100K(void)
 *******************************************************************************/
 void CyILO_Enable33K(void) 
 {
-    /* Set the bit 5 of ILO RS */
+    /* Set bit 5 of ILO RS */
     CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
 }
 
@@ -1141,7 +1147,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
     /* Get current state. */
     state = CY_LIB_SLOWCLK_ILO_CR0_REG;
 
-    /* Set the the oscillator power mode. */
+    /* Set the oscillator power mode. */
     if(mode != CY_ILO_FAST_START)
     {
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
@@ -1151,7 +1157,7 @@ uint8 CyILO_SetPowerMode(uint8 mode)
         CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
     }
 
-    /* Return the old mode. */
+    /* Return old mode. */
     return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
 }
 
@@ -1183,14 +1189,14 @@ void CyXTAL_32KHZ_Start(void)
         CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
     #endif  /* (CY_PSOC3) */
 
-    /* Enable operation of the 32K Crystal Oscillator */
+    /* Enable operation of 32K Crystal Oscillator */
     CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
 
     for (i = 1000u; i > 0u; i--)
     {
         if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
         {
-            /* Ready - switch to the hign power mode */
+            /* Ready - switch to high power mode */
             (void) CyXTAL_32KHZ_SetPowerMode(0u);
 
             break;
@@ -1256,9 +1262,9 @@ uint8 CyXTAL_32KHZ_ReadStatus(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the power mode for the 32 KHz oscillator used during sleep mode.
+*  Sets the power mode for the 32 KHz oscillator used during the sleep mode.
 *  Allows for lower power during sleep when there are fewer sources of noise.
-*  During active mode the oscillator is always run in high power mode.
+*  During the active mode the oscillator is always run in the high power mode.
 *
 * Parameters:
 *  uint8 mode
@@ -1345,7 +1351,7 @@ cystatus CyXTAL_Start(uint8 wait)
     uint8 pmTwCfg2Tmp;
 
 
-    /* Enables the MHz crystal oscillator circuit  */
+    /* Enables MHz crystal oscillator circuit  */
     CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
 
 
@@ -1366,19 +1372,19 @@ cystatus CyXTAL_Start(uint8 wait)
             /* Read XERR bit to clear it */
             (void) CY_CLK_XMHZ_CSR_REG;
 
-            /* Wait for a millisecond - 4 x 250 us */
+            /* Wait for 1 millisecond - 4 x 250 us */
             for(count = 4u; count > 0u; count--)
             {
                 while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
                 {
-                    /* Wait for the FTW interrupt event */
+                    /* Wait for FTW interrupt event */
                 }
             }
 
 
             /*******************************************************************
-            * High output indicates oscillator failure.
-            * Only can be used after start-up interval (1 ms) is completed.
+            * High output indicates an oscillator failure.
+            * Only can be used after a start-up interval (1 ms) is completed.
             *******************************************************************/
             if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
             {
@@ -1417,7 +1423,7 @@ cystatus CyXTAL_Start(uint8 wait)
 *******************************************************************************/
 void CyXTAL_Stop(void) 
 {
-    /* Disable the the oscillator. */
+    /* Disable oscillator. */
     FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
 }
 
@@ -1472,7 +1478,7 @@ void CyXTAL_DisableErrStatus(void)
 *
 * Summary:
 *  Reads the XERR status bit for the megahertz crystal. This status bit is a
-*  sticky clear on read value. This function is not available for PSoC5.
+*  sticky, clear on read. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1486,8 +1492,8 @@ void CyXTAL_DisableErrStatus(void)
 uint8 CyXTAL_ReadStatus(void) 
 {
     /***************************************************************************
-    * High output indicates oscillator failure. Only use this after start-up
-    * interval is completed. This can be used for status and failure recovery.
+    * High output indicates an oscillator failure. Only use this after a start-up
+    * interval is completed. This can be used for the status and failure recovery.
     ***************************************************************************/
     return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
 }
@@ -1501,7 +1507,7 @@ uint8 CyXTAL_ReadStatus(void)
 *  Enables the fault recovery circuit which will switch to the IMO in the case
 *  of a fault in the megahertz crystal circuit. The crystal must be up and
 *  running with the XERR bit at 0, before calling this function to prevent
-*  immediate fault switchover. This function is not available for PSoC5.
+*  an immediate fault switchover. This function is not available for PSoC5.
 *
 * Parameters:
 *  None
@@ -1543,7 +1549,7 @@ void CyXTAL_DisableFaultRecovery(void)
 ********************************************************************************
 *
 * Summary:
-*  Sets the startup settings for the crystal. Logic model outputs a frequency
+*  Sets the startup settings for the crystal. The logic model outputs a frequency
 *  (setting + 4) MHz when enabled.
 *
 *  This is artificial as the actual frequency is determined by an attached
@@ -1551,7 +1557,7 @@ void CyXTAL_DisableFaultRecovery(void)
 *
 * Parameters:
 *  setting: Valid range [0-31].
-*   Value is dependent on the frequency and quality of the crystal being used.
+*   The value is dependent on the frequency and quality of the crystal being used.
 *   Refer to the device TRM and datasheet for more information.
 *
 * Return:
@@ -1648,7 +1654,7 @@ void CyHalt(uint8 reason) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Forces a software reset of the device.
+*  Forces a device software reset.
 *
 * Parameters:
 *  None
@@ -1672,9 +1678,9 @@ void CySoftwareReset(void)
 *
 *  Note:
 *  CyDelay has been implemented with the instruction cache assumed enabled. When
-*  instruction cache is disabled on PSoC5, CyDelay will be two times larger. For
-*  example, with instruction cache disabled CyDelay(100) would result in about
-*  200 ms delay instead of 100 ms.
+*  the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+*  For example, with instruction cache disabled CyDelay(100) would result in
+*  about 200 ms delay instead of 100 ms.
 *
 * Parameters:
 *  milliseconds: number of milliseconds to delay.
@@ -1724,8 +1730,8 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
     *
     * Side Effects:
     *  CyDelayUS has been implemented with the instruction cache assumed enabled.
-    *  When instruction cache is disabled on PSoC 5, CyDelayUs will be two times
-    *  larger. For example, with instruction cache disabled CyDelayUs(100) would
+    *  When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+    *  larger. For example, with the instruction cache disabled CyDelayUs(100) would
     *  result in about 200 us delay instead of 100 us.
     *
     *  If the bus clock frequency is a small non-integer number, the actual delay
@@ -1745,10 +1751,10 @@ void CyDelay(uint32 milliseconds) CYREENTRANT
 ********************************************************************************
 *
 * Summary:
-*  Sets clock frequency for CyDelay.
+*  Sets the clock frequency for CyDelay.
 *
 * Parameters:
-*  freq: Frequency of bus clock in Hertz.
+*  freq: The frequency of the bus clock in Hertz.
 *
 * Return:
 *  None
@@ -1779,7 +1785,7 @@ void CyDelayFreq(uint32 freq) CYREENTRANT
 *  Enables the watchdog timer.
 *
 *  The timer is configured for the specified count interval, the central
-*  timewheel is cleared, the setting for low power mode is configured and the
+*  timewheel is cleared, the setting for the low power mode is configured and the
 *  watchdog timer is enabled.
 *
 *  Once enabled the watchdog cannot be disabled. The watchdog counts each time
@@ -1826,11 +1832,11 @@ void CyWdtStart(uint8 ticks, uint8 lpMode)
     CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
     CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
 
-    /* Setting the low power mode */
+    /* Setting low power mode */
     CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
                        (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
 
-    /* Enables the watchdog reset */
+    /* Enables watchdog reset */
     CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
 }
 
@@ -1862,16 +1868,16 @@ void CyWdtClear(void)
 *
 * Summary:
 *  Enables the digital low voltage monitors to generate interrupt on Vddd
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vddd threshold:
+*  reset: The option to reset the device at a specified Vddd threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
 *  threshold: Sets the trip level for the voltage monitor.
-*  Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-*  interval.
+*  Values from 1.70 V to 5.45 V are accepted with an interval  of approximately
+*  250 mV.
 *
 * Return:
 *  None
@@ -1887,7 +1893,7 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
                             (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -1912,10 +1918,10 @@ void CyVdLvDigitEnable(uint8 reset, uint8 threshold)
 *
 * Summary:
 *  Enables the analog low voltage monitors to generate interrupt on Vdda
-*   archives specified threshold and optionally resets device.
+*   archives specified threshold and optionally resets the device.
 *
 * Parameters:
-*  reset: Option to reset device at a specified Vdda threshold:
+*  reset: The option to reset the device at a specified Vdda threshold:
 *           0 - Device is not reset.
 *           1 - Device is reset.
 *
@@ -1936,7 +1942,7 @@ void CyVdLvAnalogEnable(uint8 reset, uint8 threshold)
     CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
     CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
 
-    /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+    /* Timeout to eliminate glitches on LVI/HVI when enabling */
     CyDelayUs(1u);
 
     (void)CY_VD_PERSISTENT_STATUS_REG;
@@ -2258,31 +2264,14 @@ void CyEnableInts(uint32 mask)
         CY_NOP;
         CY_NOP;
 
-        /* All entries in the cache are invalidated on the next clock cycle. */
+        /* All entries in cache are invalidated on next clock cycle. */
         CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
 
+        /* Once this is executed it's guaranteed the cache has been flushed */
+        (void) CY_CACHE_CONTROL_REG;
 
-        /***********************************************************************
-        * The prefetch unit could/would be filled with the instructions that
-        * succeed the flush. Since a flush is desired then theoretically those
-        * instructions might be considered stale/invalid.
-        ***********************************************************************/
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
-        CY_NOP;
+        /* Flush the pipeline */
+        CY_SYS_ISB;
 
         /* Restore global interrupt enable state */
         CyExitCriticalSection(interruptState);
@@ -2298,8 +2287,18 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *  number: Interrupt number, valid range [0-15].
-       address: Pointer to an interrupt service routine.
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEM_MANAGE_IRQN         - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
+    *
+    *  address: Pointer to an interrupt service routine.
     *
     * Return:
     *   The old ISR vector at this location.
@@ -2332,7 +2331,16 @@ void CyEnableInts(uint32 mask)
     *  SysTick, PendSV and others.
     *
     * Parameters:
-    *   number: The interrupt number, valid range [0-15].
+    *  number: System interrupt number:
+    *    CY_INT_NMI_IRQN                - Non Maskable Interrupt
+    *    CY_INT_HARD_FAULT_IRQN         - Hard Fault Interrupt
+    *    CY_INT_MEMORY_MANAGEMENT_IRQN  - Memory Management Interrupt
+    *    CY_INT_BUS_FAULT_IRQN          - Bus Fault Interrupt
+    *    CY_INT_USAGE_FAULT_IRQN        - Usage Fault Interrupt
+    *    CY_INT_SVCALL_IRQN             - SV Call Interrupt
+    *    CY_INT_DEBUG_MONITOR_IRQN      - Debug Monitor Interrupt
+    *    CY_INT_PEND_SV_IRQN            - Pend SV Interrupt
+    *    CY_INT_SYSTICK_IRQN            - System Tick Interrupt
     *
     * Return:
     *   Address of the ISR in the interrupt vector table.
@@ -2390,7 +2398,7 @@ void CyEnableInts(uint32 mask)
     *  number: Valid range [0-31].  Interrupt number
     *
     * Return:
-    *  Address of the ISR in the interrupt vector table.
+    *  The address of the ISR in the interrupt vector table.
     *
     *******************************************************************************/
     cyisraddress CyIntGetVector(uint8 number)
@@ -2471,10 +2479,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR;
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
     }
 
@@ -2609,10 +2617,10 @@ void CyEnableInts(uint32 mask)
 
         CYASSERT(number <= CY_INT_NUMBER_MAX);
 
-        /* Get a pointer to the Interrupt enable register. */
+        /* Get pointer to Interrupt enable register. */
         stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
 
-        /* Get the state of the interrupt. */
+        /* Get state of interrupt. */
         return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
     }
 
@@ -2630,20 +2638,20 @@ void CyEnableInts(uint32 mask)
     *  If 1 is passed as a parameter:
     *   - if any of the SC blocks are used - enable pumps for the SC blocks and
     *     start boost clock.
-    *   - For the each enabled SC block set boost clock index and enable boost
+    *   - For each enabled SC block set a boost clock index and enable the boost
     *     clock.
     *
     *  If non-1 value is passed as a parameter:
     *   - If all SC blocks are not used - disable pumps for the SC blocks and
-    *     stop boost clock.
-    *   - For the each enabled SC block clear boost clock index and disable boost
+    *     stop the boost clock.
+    *   - For each enabled SC block clear the boost clock index and disable the  boost
     *     clock.
     *
-    *  The global variable CyScPumpEnabled is updated to be equal to passed
+    *  The global variable CyScPumpEnabled is updated to be equal to passed the
     *  parameter.
     *
     * Parameters:
-    *   uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.
+    *   uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
     *                 1 - Enable
     *                 0 - Disable
     *
@@ -2707,4 +2715,391 @@ void CyEnableInts(uint32 mask)
 #endif  /* (CYDEV_VARIABLE_VDDA == 1) */
 
 
+#if(CY_PSOC5)
+    /*******************************************************************************
+    * Function Name: CySysTickStart
+    ********************************************************************************
+    *
+    * Summary:
+    *  Configures the SysTick timer to generate interrupt every 1 ms by call to the
+    *  CySysTickInit() function and starts it by calling CySysTickEnable() function.
+    *  Refer to the corresponding function description for the details.
+
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStart(void)
+    {
+        if (0u == CySysTickInitVar)
+        {
+            CySysTickInit();
+            CySysTickInitVar = 1u;
+        }
+
+        CySysTickEnable();
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickInit
+    ********************************************************************************
+    *
+    * Summary:
+    *  Initializes the callback addresses with pointers to NULL, associates the
+    *  SysTick system vector with the function that is responsible for calling
+    *  registered callback functions, configures SysTick timer to generate interrupt
+    * every 1 ms.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set.
+    *
+    *  The 1 ms interrupt interval is configured based on the frequency determined
+    *  by PSoC Creator at build time. If System clock frequency is changed in
+    *  runtime, the CyDelayFreq() with the appropriate parameter should be called.
+    *
+    *******************************************************************************/
+    void CySysTickInit(void)
+    {
+        uint32 i;
+
+        for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+        {
+            CySysTickCallbacks[i] = (void *) 0;
+        }
+
+    	(void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+        CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+        CySysTickSetReload(cydelay_freq_hz/1000u);
+        CySysTickClear();
+        CyIntEnable(CY_INT_SYSTICK_IRQN);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnable
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick timer and its interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnable(void)
+    {
+        CySysTickEnableInterrupt();
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickStop
+    ********************************************************************************
+    *
+    * Summary:
+    *  Stops the system timer (SysTick).
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickStop(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickEnableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Enables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickEnableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickDisableInterrupt
+    ********************************************************************************
+    *
+    * Summary:
+    *  Disables the SysTick interrupt.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set
+    *
+    *******************************************************************************/
+    void CySysTickDisableInterrupt(void)
+    {
+        CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero. This
+    *  function do not change or reset current sysTick counter value, so it should
+    *  be cleared using CySysTickClear() API.
+    *
+    * Parameters:
+    *  value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickSetReload(uint32 value)
+    {
+        CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetReload
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets value the counter is set to on startup and after it reaches zero.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Counter reset value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetReload(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetValue
+    ********************************************************************************
+    *
+    * Summary:
+    *  Gets current SysTick counter value.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Current SysTick counter value
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetValue(void)
+    {
+        return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetClockSource
+    ********************************************************************************
+    *
+    * Summary:
+    *  Sets the clock source for the SysTick counter.
+    *
+    * Parameters:
+    *  clockSource: Clock source for SysTick counter
+    *         Define                     Clock Source
+    *   CY_SYS_SYST_CSR_CLK_SRC_SYSCLK     SysTick is clocked by CPU clock.
+    *   CY_SYS_SYST_CSR_CLK_SRC_LFCLK      SysTick is clocked by the low frequency
+    *                              clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+    *
+    * Return:
+    *  None
+    *
+    * Side Effects:
+    *  Clears SysTick count flag if it was set. If clock source is not ready this
+    *  function call will have no effect. After changing clock source to the low frequency
+    *  clock the counter and reload register values will remain unchanged so time to
+    *  the interrupt will be significantly bigger and vice versa.
+    *
+    *******************************************************************************/
+    void CySysTickSetClockSource(uint32 clockSource)
+    {
+        if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+        {
+            CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+        }
+        else
+        {
+            CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+        }
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCountFlag
+    ********************************************************************************
+    *
+    * Summary:
+    *  The count flag is set once SysTick counter reaches zero.
+    *   The flag cleared on read.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  Returns non-zero value if counter is set, otherwise zero is returned.
+    *
+    *******************************************************************************/
+    uint32 CySysTickGetCountFlag(void)
+    {
+        return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickClear
+    ********************************************************************************
+    *
+    * Summary:
+    *  Clears the SysTick counter for well-defined startup.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    void CySysTickClear(void)
+    {
+        CY_SYS_SYST_CVR_REG = 0u;
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickSetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function set the pointers to the functions that will be called on
+    *  SysTick interrupt.
+    *
+    * Parameters:
+    *  number:  The number of callback function address to be set.
+    *           The valid range is from 0 to 4.
+    *  CallbackFunction: Function address.
+    *
+    * Return:
+    *  Returns the address of the previous callback function.
+    *  The NULL is returned if the specified address in not set.
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+    {
+        cySysTickCallback retVal;
+
+        retVal = CySysTickCallbacks[number];
+        CySysTickCallbacks[number] = function;
+        return (retVal);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickGetCallback
+    ********************************************************************************
+    *
+    * Summary:
+    *  The function get the specified callback pointer.
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    cySysTickCallback CySysTickGetCallback(uint32 number)
+    {
+        return ((cySysTickCallback) CySysTickCallbacks[number]);
+    }
+
+
+    /*******************************************************************************
+    * Function Name: CySysTickServiceCallbacks
+    ********************************************************************************
+    *
+    * Summary:
+    *  System Tick timer interrupt routine
+    *
+    * Parameters:
+    *  None
+    *
+    * Return:
+    *  None
+    *
+    *******************************************************************************/
+    static void CySysTickServiceCallbacks(void)
+    {
+        uint32 i;
+
+        /* Verify that tick timer flag was set */
+        if (1u == CySysTickGetCountFlag())
+        {
+            for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+            {
+                if (CySysTickCallbacks[i] != (void *) 0)
+                {
+                    (void)(CySysTickCallbacks[i])();
+                }
+            }
+        }
+    }
+#endif /* (CY_PSOC5) */
+
+
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h
index 3bc638c7..2e2c66ad 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CyLib.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the system, clocking, interrupts and
@@ -11,7 +11,7 @@
 *  Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -163,6 +163,30 @@ uint8 CyVdRealTimeStatus(void) ;
 
 void CySetScPumps(uint8 enable) ;
 
+#if(CY_PSOC5)
+    /* Default interrupt handler */
+    CY_ISR_PROTO(IntDefaultHandler);
+#endif  /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+    /* System tick timer APIs */
+    typedef void (*cySysTickCallback)(void);
+
+    void CySysTickStart(void);
+    void CySysTickInit(void);
+    void CySysTickEnable(void);
+    void CySysTickStop(void);
+    void CySysTickEnableInterrupt(void);
+    void CySysTickDisableInterrupt(void);
+    void CySysTickSetReload(uint32 value);
+    uint32 CySysTickGetReload(void);
+    uint32 CySysTickGetValue(void);
+    cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+    cySysTickCallback CySysTickGetCallback(uint32 number);
+    void CySysTickSetClockSource(uint32 clockSource);
+    uint32 CySysTickGetCountFlag(void);
+    void CySysTickClear(void);
+#endif  /* (CY_PSOC5) */
 
 /***************************************
 * API Constants
@@ -400,6 +424,23 @@ void CySetScPumps(uint8 enable) ;
 #define CY_ALT_ACT_USB_ENABLED          (0x01u)
 
 
+#if(CY_PSOC5)
+
+    /***************************************************************************
+    * Instruction Synchronization Barrier flushes the pipeline in the processor,
+    * so that all instructions following the ISB are fetched from cache or
+    * memory, after the instruction has been completed.
+    ***************************************************************************/
+
+    #if defined(__ARMCC_VERSION)
+        #define CY_SYS_ISB       __isb(0x0f)
+    #else   /* ASM for GCC & IAR */
+        #define CY_SYS_ISB       asm volatile ("isb \n")
+    #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
 /***************************************
 * Registers
 ***************************************/
@@ -689,16 +730,29 @@ void CySetScPumps(uint8 enable) ;
     #define CY_CACHE_CONTROL_REG        (* (reg16 *) CYREG_CACHE_CC_CTL )
     #define CY_CACHE_CONTROL_PTR        (  (reg16 *) CYREG_CACHE_CC_CTL )
 
+    /* System tick registers */
+    #define CY_SYS_SYST_CSR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+    #define CY_SYS_SYST_CSR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+    #define CY_SYS_SYST_RVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+    #define CY_SYS_SYST_RVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+    #define CY_SYS_SYST_CVR_REG         (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+    #define CY_SYS_SYST_CVR_PTR         ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+    #define CY_SYS_SYST_CALIB_REG       (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+    #define CY_SYS_SYST_CALIB_PTR       ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
 #elif (CY_PSOC3)
 
     /* Interrupt Address Vector registers */
     #define CY_INT_VECT_TABLE           ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
 
-    /* Interrrupt Controller Priority Registers */
+    /* Interrupt Controller Priority Registers */
     #define CY_INT_PRIORITY_REG         (* (reg8 *) CYREG_INTC_PRIOR0)
     #define CY_INT_PRIORITY_PTR         (  (reg8 *) CYREG_INTC_PRIOR0)
 
-    /* Interrrupt Controller Set Enable Registers */
+    /* Interrupt Controller Set Enable Registers */
     #define CY_INT_ENABLE_REG           (* (reg8 *) CYREG_INTC_SET_EN0)
     #define CY_INT_ENABLE_PTR           (  (reg8 *) CYREG_INTC_SET_EN0)
 
@@ -714,7 +768,7 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_SET_EN3_REG          (* (reg8 *) CYREG_INTC_SET_EN3)
     #define CY_INT_SET_EN3_PTR          (  (reg8 *) CYREG_INTC_SET_EN3)
 
-    /* Interrrupt Controller Clear Enable Registers */
+    /* Interrupt Controller Clear Enable Registers */
     #define CY_INT_CLEAR_REG            (* (reg8 *) CYREG_INTC_CLR_EN0)
     #define CY_INT_CLEAR_PTR            (  (reg8 *) CYREG_INTC_CLR_EN0)
 
@@ -731,11 +785,11 @@ void CySetScPumps(uint8 enable) ;
     #define CY_INT_CLR_EN3_PTR          (  (reg8 *) CYREG_INTC_CLR_EN3)
 
 
-    /* Interrrupt Controller Set Pend Registers */
+    /* Interrupt Controller Set Pend Registers */
     #define CY_INT_SET_PEND_REG         (* (reg8 *) CYREG_INTC_SET_PD0)
     #define CY_INT_SET_PEND_PTR         (  (reg8 *) CYREG_INTC_SET_PD0)
 
-    /* Interrrupt Controller Clear Pend Registers */
+    /* Interrupt Controller Clear Pend Registers */
     #define CY_INT_CLR_PEND_REG         (* (reg8 *) CYREG_INTC_CLR_PD0)
     #define CY_INT_CLR_PEND_PTR         (  (reg8 *) CYREG_INTC_CLR_PD0)
 
@@ -753,8 +807,8 @@ void CySetScPumps(uint8 enable) ;
 * Macro Name: CyAssert
 ********************************************************************************
 * Summary:
-*  Macro that evaluates the expression and if it is false (evaluates to 0) then
-*  the processor is halted.
+*  The macro that evaluates the expression and if it is false (evaluates to 0)
+*  then the processor is halted.
 *
 *  This macro is evaluated unless NDEBUG is defined.
 *
@@ -791,7 +845,7 @@ void CySetScPumps(uint8 enable) ;
 #define CY_RESET_GPIO1              (0x80u)
 
 
-/* Interrrupt Controller Configuration and Status Register */
+/* Interrupt Controller Configuration and Status Register */
 #if(CY_PSOC3)
     #define INTERRUPT_CSR               ((reg8 *) CYREG_INTC_CSR_EN)
     #define DISABLE_IRQ_SET             ((uint8)(0x01u << 1u))    /* INTC_CSR_EN */
@@ -844,6 +898,19 @@ void CySetScPumps(uint8 enable) ;
 #define CY_CACHE_CONTROL_FLUSH          (0x0004u)
 #define CY_LIB_RESET_CR2_RESET          (0x01u)
 
+#if(CY_PSOC5)
+    /* System tick API constants */
+    #define CY_SYS_SYST_CSR_ENABLE              ((uint32) (0x01u))
+    #define CY_SYS_SYST_CSR_ENABLE_INT          ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT    ((uint32) (0x02u))
+    #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT     ((uint32) (16u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK      ((uint32) (1u))
+    #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK       ((uint32) (0u))
+    #define CY_SYS_SYST_RVR_CNT_MASK            ((uint32) (0x00FFFFFFu))
+    #define CY_SYS_SYST_NUM_OF_CALLBACKS        ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
 
 /*******************************************************************************
 * Interrupt API constants
@@ -876,6 +943,20 @@ void CySetScPumps(uint8 enable) ;
 /* Mask to get valid range of system interrupt 0-15 */
 #define CY_INT_SYS_NUMBER_MASK          (0xFu)
 
+#if(CY_PSOC5)
+
+    /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+    #define CY_INT_NMI_IRQN                  ( 2u)      /* Non Maskable Interrupt      */
+    #define CY_INT_HARD_FAULT_IRQN           ( 3u)      /* Hard Fault Interrupt        */
+    #define CY_INT_MEM_MANAGE_IRQN           ( 4u)      /* Memory Management Interrupt */
+    #define CY_INT_BUS_FAULT_IRQN            ( 5u)      /* Bus Fault Interrupt         */
+    #define CY_INT_USAGE_FAULT_IRQN          ( 6u)      /* Usage Fault Interrupt       */
+    #define CY_INT_SVCALL_IRQN               (11u)      /* SV Call Interrupt           */
+    #define CY_INT_DEBUG_MONITOR_IRQN        (12u)      /* Debug Monitor Interrupt     */
+    #define CY_INT_PEND_SV_IRQN              (14u)      /* Pend SV Interrupt           */
+    #define CY_INT_SYSTICK_IRQN              (15u)      /* System Tick Interrupt       */
+
+#endif  /* (CY_PSOC5) */
 
 /*******************************************************************************
 * Interrupt Macros
@@ -1027,18 +1108,26 @@ void CySetScPumps(uint8 enable) ;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used.
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+
 #define CYGlobalIntEnable       CyGlobalIntEnable
 #define CYGlobalIntDisable      CyGlobalIntDisable
 
 #define cymemset(s,c,n)         memset((s),(c),(n))
 #define cymemcpy(d,s,n)         memcpy((d),(s),(n))
 
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
-*******************************************************************************/
 #define MFGCFG_X32_TR_PTR               (CY_CLK_XTAL32_TR_PTR)
 #define MFGCFG_X32_TR                   (CY_CLK_XTAL32_TR_REG)
 #define SLOWCLK_X32_TST_PTR             (CY_CLK_XTAL32_TST_PTR)
@@ -1123,10 +1212,6 @@ void CySetScPumps(uint8 enable) ;
 #define CY_VD_PRESISTENT_STATUS_PTR    (CY_VD_PERSISTENT_STATUS_PTR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20
-*******************************************************************************/
-
 #if(CY_PSOC5)
 
     #define CYINT_IRQ_BASE      (CY_INT_IRQ_BASE)
@@ -1153,9 +1238,7 @@ void CySetScPumps(uint8 enable) ;
 #endif  /* (CY_PSOC5) */
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
-*******************************************************************************/
+
 #define BUS_AMASK_CLEAR                 (0xF0u)
 #define BUS_DMASK_CLEAR                 (0x00u)
 #define CLKDIST_LD_LOAD_SET             (0x01u)
@@ -1190,9 +1273,6 @@ void CySetScPumps(uint8 enable) ;
 #define CLKDIST_CR                     (*(reg8 *) CYREG_CLKDIST_CR)
 
 
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
-*******************************************************************************/
 #define IMO_PM_ENABLE                   (0x10u)
 #define PM_ACT_CFG0_PTR                ( (reg8 *) CYREG_PM_ACT_CFG0)
 #define PM_ACT_CFG0                    (*(reg8 *) CYREG_PM_ACT_CFG0)
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c
index 8ea15809..949b6752 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides an API for the System Performance Component.
@@ -8,7 +8,7 @@
 *   application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -231,6 +231,11 @@ cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], u
 * Summary:
 *  Loads a row of data into the row latch of a Flash/EEPROM array.
 *
+*  The buffer pointer should point to the data that should be written to the
+*  flash row directly (no data in ECC/flash will be preserved). It is Flash API
+*  responsibility to prepare data: the preserved data are copied from flash into
+*  array with the modified data.
+*
 * Parameters:
 *  uint8 array:
 *   Id of the array.
@@ -286,6 +291,149 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+*  Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+*  The only data that are going to be changed should be passed. The function
+*  will handle unmodified data preservation based on DWR settings and input
+*  parameters.
+*
+* Parameters:
+*  uint8 array:
+*   Id of the array.
+*
+*  uint16 row:
+*   Flash row number to be loaded.
+*
+*  uint8* buffer:
+*   Data to be loaded to the row latch
+*
+*  uint8 size:
+*   The number of data bytes that the SPC expects to be written. Depends on the
+*   type of the array and, if the array is Flash, whether ECC is being enabled
+*   or not. There are following values: flash row latch size with ECC enabled,
+*   flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_CANCELED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+    cystatus status = CYRET_STARTED;
+    uint16 i;
+
+    #if (CYDEV_ECC_ENABLE == 0)
+        uint32 offset;
+    #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+        /* Make sure the command was accepted */
+        if(CY_SPC_BUSY)
+        {
+            CY_SPC_CPU_DATA_REG = array;
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+            * Data in ECC" DWR options are disabled, ECC section is available
+            * for user data.
+            *******************************************************************/
+            #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+                /*******************************************************************
+                * If size parameter equals size of the ECC row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the ECC section.
+                * In this case flash data must be preserved. The flash data copied
+                * from flash data section to the SPC data register.
+                *******************************************************************/
+                if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_FLS_BASE +
+                             ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+                             ((uint32)   row * CYDEV_FLS_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+            for(i = 0u; i < size; i++)
+            {
+                CY_SPC_CPU_DATA_REG = buffer[i];
+            }
+
+
+            /*******************************************************************
+            * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+            * ECC section can be used for storing device configuration data
+            * ("Store Configuration Data in ECC" DWR option is enabled) or for
+            * storing user data in the ECC section ("Store Configuration Data in
+            * ECC" DWR option is enabled). In both cases, the data in the ECC
+            * section must be preserved if flash data is written.
+            *******************************************************************/
+            #if (CYDEV_ECC_ENABLE == 0)
+
+
+                /*******************************************************************
+                * If size parameter equals size of the flash row and selected array
+                * identification corresponds to the flash array (but not to EEPROM
+                * array) then data are going to be written to the flash data
+                * section. In this case, ECC section data must be preserved.
+                * The ECC section data copied from ECC section to the SPC data
+                * register.
+                *******************************************************************/
+                if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+                {
+                    offset = CYDEV_ECC_BASE +
+                            ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+                            ((uint32) row   * CYDEV_ECC_ROW_SIZE   );
+
+                    for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+                    {
+                        CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+                    }
+                }
+
+            #else
+
+                if(0u != row)
+                {
+                    /* To remove unreferenced local variable warning */
+                }
+
+            #endif /* (CYDEV_ECC_ENABLE == 0) */
+        }
+        else
+        {
+            status = CYRET_CANCELED;
+        }
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
+
 /*******************************************************************************
 * Function Name: CySpcWriteRow
 ********************************************************************************
@@ -551,4 +699,38 @@ void CySpcUnlock(void)
 }
 
 
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+*  Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+*  None
+*
+* Return:
+*  CYRET_STARTED
+*  CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+    cystatus status = CYRET_STARTED;
+
+    /* Make sure the SPC is ready to accept command */
+    if(CY_SPC_IDLE)
+    {
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+        CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+        CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+    }
+    else
+    {
+        status = CYRET_LOCKED;
+    }
+
+    return(status);
+}
+
 /* [] END OF FILE */
+
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h
index 3757e132..22827133 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: CySpc.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides definitions for the System Performance Component API.
@@ -8,7 +8,7 @@
 *  application.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -37,10 +37,13 @@ uint8    CySpcReadData(uint8 buffer[], uint8 size);
 cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
 ;
 cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
 cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
 ;
 cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
 cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
 cystatus CySpcLock(void);
 void     CySpcUnlock(void);
 
@@ -69,7 +72,7 @@ void     CySpcUnlock(void);
 #define CY_SPC_STATUS_CODE_MASK             (0xFCu)
 #define CY_SPC_STATUS_CODE_SHIFT            (0x02u)
 
-/* Status codes for the SPC. */
+/* Status codes for SPC. */
 #define CY_SPC_STATUS_SUCCESS               (0x00u)   /* Operation Successful */
 #define CY_SPC_STATUS_INVALID_ARRAY_ID      (0x01u)   /* Invalid Array ID for given command */
 #define CY_SPC_STATUS_INVALID_2BYTEKEY      (0x02u)   /* Invalid 2-byte key */
@@ -137,7 +140,18 @@ void     CySpcUnlock(void);
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define FIRST_FLASH_ARRAYID         (CY_SPC_FIRST_FLASH_ARRAYID)
 #define LAST_FLASH_ARRAYID          (CY_SPC_LAST_FLASH_ARRAYID)
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c
index 3991486a..2d221a83 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void LED_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  LED_DM_STRONG     Strong Drive 
+*  LED_DM_OD_HI      Open Drain, Drives High 
+*  LED_DM_OD_LO      Open Drain, Drives Low 
+*  LED_DM_RES_UP     Resistive Pull Up 
+*  LED_DM_RES_DWN    Resistive Pull Down 
+*  LED_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  LED_DM_DIG_HIZ    High Impedance Digital 
+*  LED_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h
index 103fc452..c834106b 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h
index 61edd82b..81da69da 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: LED.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define LED_0		LED__0__PC
+#define LED_0		(LED__0__PC)
 
 #endif /* End Pins LED_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
index cab58f9f..6fcc5f6a 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out_DBx.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,23 +25,23 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_DBx_0		SCSI_Out_DBx__0__PC
-#define SCSI_Out_DBx_1		SCSI_Out_DBx__1__PC
-#define SCSI_Out_DBx_2		SCSI_Out_DBx__2__PC
-#define SCSI_Out_DBx_3		SCSI_Out_DBx__3__PC
-#define SCSI_Out_DBx_4		SCSI_Out_DBx__4__PC
-#define SCSI_Out_DBx_5		SCSI_Out_DBx__5__PC
-#define SCSI_Out_DBx_6		SCSI_Out_DBx__6__PC
-#define SCSI_Out_DBx_7		SCSI_Out_DBx__7__PC
-
-#define SCSI_Out_DBx_DB0		SCSI_Out_DBx__DB0__PC
-#define SCSI_Out_DBx_DB1		SCSI_Out_DBx__DB1__PC
-#define SCSI_Out_DBx_DB2		SCSI_Out_DBx__DB2__PC
-#define SCSI_Out_DBx_DB3		SCSI_Out_DBx__DB3__PC
-#define SCSI_Out_DBx_DB4		SCSI_Out_DBx__DB4__PC
-#define SCSI_Out_DBx_DB5		SCSI_Out_DBx__DB5__PC
-#define SCSI_Out_DBx_DB6		SCSI_Out_DBx__DB6__PC
-#define SCSI_Out_DBx_DB7		SCSI_Out_DBx__DB7__PC
+#define SCSI_Out_DBx_0		(SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1		(SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2		(SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3		(SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4		(SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5		(SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6		(SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7		(SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0		(SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1		(SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2		(SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3		(SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4		(SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5		(SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6		(SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7		(SCSI_Out_DBx__DB7__PC)
 
 #endif /* End Pins SCSI_Out_DBx_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
index cd457bc8..b5c8136c 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SCSI_Out.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,27 +25,27 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SCSI_Out_0		SCSI_Out__0__PC
-#define SCSI_Out_1		SCSI_Out__1__PC
-#define SCSI_Out_2		SCSI_Out__2__PC
-#define SCSI_Out_3		SCSI_Out__3__PC
-#define SCSI_Out_4		SCSI_Out__4__PC
-#define SCSI_Out_5		SCSI_Out__5__PC
-#define SCSI_Out_6		SCSI_Out__6__PC
-#define SCSI_Out_7		SCSI_Out__7__PC
-#define SCSI_Out_8		SCSI_Out__8__PC
-#define SCSI_Out_9		SCSI_Out__9__PC
-
-#define SCSI_Out_DBP_raw		SCSI_Out__DBP_raw__PC
-#define SCSI_Out_ATN		SCSI_Out__ATN__PC
-#define SCSI_Out_BSY		SCSI_Out__BSY__PC
-#define SCSI_Out_ACK		SCSI_Out__ACK__PC
-#define SCSI_Out_RST		SCSI_Out__RST__PC
-#define SCSI_Out_MSG		SCSI_Out__MSG__PC
-#define SCSI_Out_SEL		SCSI_Out__SEL__PC
-#define SCSI_Out_CD		SCSI_Out__CD__PC
-#define SCSI_Out_REQ		SCSI_Out__REQ__PC
-#define SCSI_Out_IO_raw		SCSI_Out__IO_raw__PC
+#define SCSI_Out_0		(SCSI_Out__0__PC)
+#define SCSI_Out_1		(SCSI_Out__1__PC)
+#define SCSI_Out_2		(SCSI_Out__2__PC)
+#define SCSI_Out_3		(SCSI_Out__3__PC)
+#define SCSI_Out_4		(SCSI_Out__4__PC)
+#define SCSI_Out_5		(SCSI_Out__5__PC)
+#define SCSI_Out_6		(SCSI_Out__6__PC)
+#define SCSI_Out_7		(SCSI_Out__7__PC)
+#define SCSI_Out_8		(SCSI_Out__8__PC)
+#define SCSI_Out_9		(SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw		(SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN		(SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY		(SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK		(SCSI_Out__ACK__PC)
+#define SCSI_Out_RST		(SCSI_Out__RST__PC)
+#define SCSI_Out_MSG		(SCSI_Out__MSG__PC)
+#define SCSI_Out_SEL		(SCSI_Out__SEL__PC)
+#define SCSI_Out_CD		(SCSI_Out__CD__PC)
+#define SCSI_Out_REQ		(SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw		(SCSI_Out__IO_raw__PC)
 
 #endif /* End Pins SCSI_Out_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c
index a5aa27ee..7c54d5b7 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_PULLUP.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void SD_PULLUP_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  SD_PULLUP_DM_STRONG     Strong Drive 
+*  SD_PULLUP_DM_OD_HI      Open Drain, Drives High 
+*  SD_PULLUP_DM_OD_LO      Open Drain, Drives Low 
+*  SD_PULLUP_DM_RES_UP     Resistive Pull Up 
+*  SD_PULLUP_DM_RES_DWN    Resistive Pull Down 
+*  SD_PULLUP_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  SD_PULLUP_DM_DIG_HIZ    High Impedance Digital 
+*  SD_PULLUP_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h
index 07394f01..cf13ee94 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_PULLUP.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h
index bf8bd1df..2a5b9bb4 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: SD_PULLUP.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,11 +25,11 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define SD_PULLUP_0		SD_PULLUP__0__PC
-#define SD_PULLUP_1		SD_PULLUP__1__PC
-#define SD_PULLUP_2		SD_PULLUP__2__PC
-#define SD_PULLUP_3		SD_PULLUP__3__PC
-#define SD_PULLUP_4		SD_PULLUP__4__PC
+#define SD_PULLUP_0		(SD_PULLUP__0__PC)
+#define SD_PULLUP_1		(SD_PULLUP__1__PC)
+#define SD_PULLUP_2		(SD_PULLUP__2__PC)
+#define SD_PULLUP_3		(SD_PULLUP__3__PC)
+#define SD_PULLUP_4		(SD_PULLUP__4__PC)
 
 #endif /* End Pins SD_PULLUP_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c
index 0750c413..ef789c5a 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  API for USBFS Component.
@@ -11,7 +11,7 @@
 *  registers are indexed by variations of epNumber - 1.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -23,28 +23,33 @@
 #include "USBFS_hid.h"
 #if(USBFS_DMA1_REMOVE == 0u)
     #include "USBFS_ep1_dma.h"
-#endif   /* End USBFS_DMA1_REMOVE */
+#endif   /*  USBFS_DMA1_REMOVE */
 #if(USBFS_DMA2_REMOVE == 0u)
     #include "USBFS_ep2_dma.h"
-#endif   /* End USBFS_DMA2_REMOVE */
+#endif   /*  USBFS_DMA2_REMOVE */
 #if(USBFS_DMA3_REMOVE == 0u)
     #include "USBFS_ep3_dma.h"
-#endif   /* End USBFS_DMA3_REMOVE */
+#endif   /*  USBFS_DMA3_REMOVE */
 #if(USBFS_DMA4_REMOVE == 0u)
     #include "USBFS_ep4_dma.h"
-#endif   /* End USBFS_DMA4_REMOVE */
+#endif   /*  USBFS_DMA4_REMOVE */
 #if(USBFS_DMA5_REMOVE == 0u)
     #include "USBFS_ep5_dma.h"
-#endif   /* End USBFS_DMA5_REMOVE */
+#endif   /*  USBFS_DMA5_REMOVE */
 #if(USBFS_DMA6_REMOVE == 0u)
     #include "USBFS_ep6_dma.h"
-#endif   /* End USBFS_DMA6_REMOVE */
+#endif   /*  USBFS_DMA6_REMOVE */
 #if(USBFS_DMA7_REMOVE == 0u)
     #include "USBFS_ep7_dma.h"
-#endif   /* End USBFS_DMA7_REMOVE */
+#endif   /*  USBFS_DMA7_REMOVE */
 #if(USBFS_DMA8_REMOVE == 0u)
     #include "USBFS_ep8_dma.h"
-#endif   /* End USBFS_DMA8_REMOVE */
+#endif   /*  USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP_DMA_Done_isr.h"
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /***************************************
@@ -55,7 +60,25 @@ uint8 USBFS_initVar = 0u;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     uint8 USBFS_DmaChan[USBFS_MAX_EP];
     uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+    uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+    {   0u,
+        USBFS_ep1_TD_TERMOUT_EN,
+        USBFS_ep2_TD_TERMOUT_EN,
+        USBFS_ep3_TD_TERMOUT_EN,
+        USBFS_ep4_TD_TERMOUT_EN,
+        USBFS_ep5_TD_TERMOUT_EN,
+        USBFS_ep6_TD_TERMOUT_EN,
+        USBFS_ep7_TD_TERMOUT_EN,
+        USBFS_ep8_TD_TERMOUT_EN
+    };
+    volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -137,7 +160,7 @@ void USBFS_Init(void)
     uint8 enableInterrupts;
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         uint16 i;
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     enableInterrupts = CyEnterCriticalSection();
 
@@ -190,8 +213,11 @@ void USBFS_Init(void)
         for (i = 0u; i < USBFS_MAX_EP; i++)
         {
             USBFS_DmaTd[i] = DMA_INVALID_TD;
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
         }
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     CyExitCriticalSection(enableInterrupts);
 
@@ -204,7 +230,7 @@ void USBFS_Init(void)
     #if(USBFS_SOF_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_SOF_VECT_NUM,   &USBFS_SOF_ISR);
         CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
-    #endif   /* End USBFS_SOF_ISR_REMOVE */
+    #endif   /*  USBFS_SOF_ISR_REMOVE */
 
     /* Set the Control Endpoint Interrupt. */
     (void) CyIntSetVector(USBFS_EP_0_VECT_NUM,   &USBFS_EP_0_ISR);
@@ -214,55 +240,55 @@ void USBFS_Init(void)
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_1_VECT_NUM,   &USBFS_EP_1_ISR);
         CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
 
     /* Set the Data Endpoint 2 Interrupt. */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_2_VECT_NUM,   &USBFS_EP_2_ISR);
         CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
 
     /* Set the Data Endpoint 3 Interrupt. */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_3_VECT_NUM,   &USBFS_EP_3_ISR);
         CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
 
     /* Set the Data Endpoint 4 Interrupt. */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_4_VECT_NUM,   &USBFS_EP_4_ISR);
         CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
 
     /* Set the Data Endpoint 5 Interrupt. */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_5_VECT_NUM,   &USBFS_EP_5_ISR);
         CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
 
     /* Set the Data Endpoint 6 Interrupt. */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_6_VECT_NUM,   &USBFS_EP_6_ISR);
         CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
 
      /* Set the Data Endpoint 7 Interrupt. */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_7_VECT_NUM,   &USBFS_EP_7_ISR);
         CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
 
     /* Set the Data Endpoint 8 Interrupt. */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         (void) CyIntSetVector(USBFS_EP_8_VECT_NUM,   &USBFS_EP_8_ISR);
         CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* Set the ARB Interrupt. */
         (void) CyIntSetVector(USBFS_ARB_VECT_NUM,   &USBFS_ARB_ISR);
         CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
 }
 
@@ -339,45 +365,50 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
     CyIntEnable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntEnable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
     #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
         /* usb arb interrupt enable */
         USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
         CyIntEnable(USBFS_ARB_VECT_NUM);
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Arbiter configuration for DMA transfers */
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /*Set cfg cmplt this rises DMA request when the full configuration is done */
             USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-        #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+                /* Init interrupt which handles verification of the successful DMA transaction */
+                USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+                USBFS_EP17_DMA_Done_SR_InterruptEnable();
+                USBFS_EP8_DMA_Done_SR_InterruptEnable();
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+        #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     USBFS_transferState = USBFS_TRANS_STATE_IDLE;
 
@@ -395,7 +426,7 @@ void USBFS_InitComponent(uint8 device, uint8 mode)
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
             #else
                 USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
-            #endif /* End USBFS_VDDD_MV < USBFS_3500MV */
+            #endif /*  USBFS_VDDD_MV < USBFS_3500MV */
             break;
     }
 
@@ -535,7 +566,7 @@ void USBFS_Stop(void)
 
     #if(USBFS_EP_MM != USBFS__EP_MANUAL)
         USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-    #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+    #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
     /* Disable the SIE */
     USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
@@ -551,28 +582,28 @@ void USBFS_Stop(void)
     CyIntDisable(USBFS_EP_0_VECT_NUM);
     #if(USBFS_EP1_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_1_VECT_NUM);
-    #endif   /* End USBFS_EP1_ISR_REMOVE */
+    #endif   /*  USBFS_EP1_ISR_REMOVE */
     #if(USBFS_EP2_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_2_VECT_NUM);
-    #endif   /* End USBFS_EP2_ISR_REMOVE */
+    #endif   /*  USBFS_EP2_ISR_REMOVE */
     #if(USBFS_EP3_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_3_VECT_NUM);
-    #endif   /* End USBFS_EP3_ISR_REMOVE */
+    #endif   /*  USBFS_EP3_ISR_REMOVE */
     #if(USBFS_EP4_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_4_VECT_NUM);
-    #endif   /* End USBFS_EP4_ISR_REMOVE */
+    #endif   /*  USBFS_EP4_ISR_REMOVE */
     #if(USBFS_EP5_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_5_VECT_NUM);
-    #endif   /* End USBFS_EP5_ISR_REMOVE */
+    #endif   /*  USBFS_EP5_ISR_REMOVE */
     #if(USBFS_EP6_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_6_VECT_NUM);
-    #endif   /* End USBFS_EP6_ISR_REMOVE */
+    #endif   /*  USBFS_EP6_ISR_REMOVE */
     #if(USBFS_EP7_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_7_VECT_NUM);
-    #endif   /* End USBFS_EP7_ISR_REMOVE */
+    #endif   /*  USBFS_EP7_ISR_REMOVE */
     #if(USBFS_EP8_ISR_REMOVE == 0u)
         CyIntDisable(USBFS_EP_8_VECT_NUM);
-    #endif   /* End USBFS_EP8_ISR_REMOVE */
+    #endif   /*  USBFS_EP8_ISR_REMOVE */
 
     /* Clear all of the component data */
     USBFS_configuration = 0u;
@@ -768,7 +799,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
     *  No.
     *
     *******************************************************************************/
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                                     
     {
         uint16 src;
@@ -788,56 +819,56 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 src = HI16(CYDEV_PERIPH_BASE);
                 dst = HI16(pData);
             }
-        #endif  /* End C51 */
+        #endif  /*  C51 */
         switch(epNumber)
         {
             case USBFS_EP1:
                 #if(USBFS_DMA1_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA1_REMOVE */
+                #endif   /*  USBFS_DMA1_REMOVE */
                 break;
             case USBFS_EP2:
                 #if(USBFS_DMA2_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA2_REMOVE */
+                #endif   /*  USBFS_DMA2_REMOVE */
                 break;
             case USBFS_EP3:
                 #if(USBFS_DMA3_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA3_REMOVE */
+                #endif   /*  USBFS_DMA3_REMOVE */
                 break;
             case USBFS_EP4:
                 #if(USBFS_DMA4_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA4_REMOVE */
+                #endif   /*  USBFS_DMA4_REMOVE */
                 break;
             case USBFS_EP5:
                 #if(USBFS_DMA5_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA5_REMOVE */
+                #endif   /*  USBFS_DMA5_REMOVE */
                 break;
             case USBFS_EP6:
                 #if(USBFS_DMA6_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA6_REMOVE */
+                #endif   /*  USBFS_DMA6_REMOVE */
                 break;
             case USBFS_EP7:
                 #if(USBFS_DMA7_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA7_REMOVE */
+                #endif   /*  USBFS_DMA7_REMOVE */
                 break;
             case USBFS_EP8:
                 #if(USBFS_DMA8_REMOVE == 0u)
                     USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
                         USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
-                #endif   /* End USBFS_DMA8_REMOVE */
+                #endif   /*  USBFS_DMA8_REMOVE */
                 break;
             default:
                 /* Do not support EP0 DMA transfers */
@@ -846,6 +877,10 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
         if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
         {
             USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+            #endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
         }
     }
 
@@ -879,11 +914,74 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
                 CyDmaTdFree(USBFS_DmaTd[i]);
                 USBFS_DmaTd[i] = DMA_INVALID_TD;
             }
+            #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+                {
+                    CyDmaTdFree(USBFS_DmaNextTd[i]);
+                    USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+                }
+            #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
             i++;
         }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
     }
 
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+    /*******************************************************************************
+    * Function Name: USBFS_LoadNextInEP
+    ********************************************************************************
+    *
+    * Summary:
+    *  This internal function is used for IN endpoint DMA reconfiguration in
+    *  Auto DMA mode.
+    *
+    * Parameters:
+    *  epNumber: Contains the data endpoint number.
+    *  mode:   0 - Configure DMA to send the the rest of data.
+    *          1 - Configure DMA to repeat 2 last bytes of the first burst.
+    *
+    * Return:
+    *  None.
+    *
+    *******************************************************************************/
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) 
+    {
+        reg16 *convert;
+
+        if(mode == 0u)
+        {
+            /* Configure DMA to send the the rest of data */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                            USBFS_DMA_BYTES_PER_BURST));
+            USBFS_inBufFull[epNumber] = 1u;
+        }
+        else
+        {
+            /* Configure DMA to repeat 2 last bytes of the first burst. */
+            /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+            /* Set transfer length */
+            CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+            /* CyDmaTdSetAddress API is optimized to change only source address */
+            convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+            CY_SET_REG16(convert,  LO16((uint32)USBFS_inDataPointer[epNumber] +
+                                   USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+        }
+
+        /* CyDmaChSetInitialTd API is optimised to init TD */
+        CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /*******************************************************************************
@@ -891,8 +989,7 @@ uint16 USBFS_GetEPCount(uint8 epNumber)
 ********************************************************************************
 *
 * Summary:
-*  Loads and enables the specified USB data endpoint for an IN interrupt or bulk
-*  transfer.
+*  Loads and enables the specified USB data endpoint for an IN transfer.
 *
 * Parameters:
 *  epNumber: Contains the data endpoint number.
@@ -916,7 +1013,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
     {
@@ -929,7 +1026,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             {
                 length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Set the count and data toggle */
         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
@@ -950,15 +1047,15 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
             CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
         #else
             /* Init DMA if it was not initialized */
-            if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+            if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
-            if((pData != NULL) && (length > 0u))
+            if ((pData != NULL) && (length > 0u))
             {
                 /* Enable DMA in mode2 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
@@ -978,16 +1075,37 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 /* When zero-length packet - write the Mode register directly */
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-            if(pData != NULL)
+            if (pData != NULL)
             {
                 /* Enable DMA in mode3 for transferring data */
                 (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+            #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                USBFS_inLength[epNumber] = length;
+                USBFS_inDataPointer[epNumber] = pData;
+                /* Configure DMA to send the data only for the first burst */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+                    (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+                    USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+                (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+                /* The second TD will be executed only when the first one fails.
+                *  The intention of this TD is to generate NRQ interrupt
+                *  and repeat 2 last bytes of the first burst.
+                */
+                (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+                                               USBFS_DmaNextTd[epNumber],
+                                               USBFS_epX_TD_TERMOUT_EN[epNumber]);
+                /* Configure DmaNextTd to clear Data ready status */
+                (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber],  LO16((uint32)&clearInDataRdyStatus),
+                                                                LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+            #else /* Configure DMA to send all data*/
                 (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
                                                USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
                 (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],  LO16((uint32)pData), LO16((uint32)p));
+            #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
                 /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
                 (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
                 /* Enable the DMA */
@@ -999,8 +1117,28 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                 USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
                 if(length > 0u)
                 {
+                #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+                    USBFS_inLength[epNumber] = length;
+                    USBFS_inBufFull[epNumber] = 0u;
+                    (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+                    /* Configure DMA to send the data only for the first burst */
+                    (void) CyDmaTdSetConfiguration(
+                        USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+                        USBFS_DMA_BYTES_PER_BURST : length,
+                        USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+                    (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+                                             LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+                    /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+                    (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+                    /* Enable the DMA */
+                    (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+                    (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+                #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
                     /* Set Data ready status, This will generate DMA request */
-                    * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #ifndef USBFS_MANUAL_IN_EP_ARM
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    #endif  /* USBFS_MANUAL_IN_EP_ARM */
                     /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
                 }
                 else
@@ -1009,8 +1147,7 @@ void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)
                     CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
                 }
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
     }
 }
 
@@ -1047,10 +1184,10 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
     reg8 *p;
     #if(USBFS_EP_MM == USBFS__EP_MANUAL)
         uint16 i;
-    #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+    #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 xferCount;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
     {
@@ -1064,7 +1201,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 length = xferCount;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         #if(USBFS_EP_MM == USBFS__EP_MANUAL)
             /* Copy the data using the arbiter data register */
@@ -1081,7 +1218,8 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             {
                 USBFS_InitEP_DMA(epNumber, pData);
             }
-        #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+
+        #endif /*  USBFS_EP_MM == USBFS__EP_MANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
             /* Enable DMA in mode2 for transferring data */
@@ -1097,7 +1235,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
             * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 
         #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
             /* Enable DMA in mode3 for transferring data */
@@ -1112,7 +1250,7 @@ uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)
             (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
             (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
             /* Out EP will be (re)armed in arb ISR after transfer complete */
-        #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     }
     else
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h
index 41a8619d..2dde8d08 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * File Name: USBFS.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,6 +20,11 @@
 #include "cyfitter.h"
 #include "CyLib.h"
 
+/*  User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
 
 /***************************************
 * Conditional Compilation Parameters
@@ -28,7 +33,7 @@
 /* Check to see if required defines such as CY_PSOC5LP are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5LP)
-    #error Component USBFS_v2_60 requires cy_boot v3.0 or later
+    #error Component USBFS_v2_80 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5LP) */
 
 
@@ -47,7 +52,7 @@
 #else
     #define USBFS_DATA
     #define USBFS_XDATA
-#endif /* End __C51__ */
+#endif /*  __C51__ */
 #define USBFS_NULL       NULL
 
 
@@ -98,6 +103,7 @@
 #define USBFS_EP8_ISR_REMOVE                 (1u)
 #define USBFS_EP_MM                          (0u)
 #define USBFS_EP_MA                          (0u)
+#define USBFS_EP_DMA_AUTO_OPT                (0u)
 #define USBFS_DMA1_REMOVE                    (1u)
 #define USBFS_DMA2_REMOVE                    (1u)
 #define USBFS_DMA3_REMOVE                    (1u)
@@ -219,7 +225,7 @@ void   USBFS_Resume(void) ;
 #endif  /* USBFS_ENABLE_FWSN_STRING */
 #if (USBFS_MON_VBUS == 1u)
     uint8  USBFS_VBusPresent(void) ;
-#endif /* End USBFS_MON_VBUS */
+#endif /*  USBFS_MON_VBUS */
 
 #if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
@@ -227,19 +233,24 @@ void   USBFS_Resume(void) ;
     void USBFS_CyBtldrCommStart(void) ;
     void USBFS_CyBtldrCommStop(void) ;
     void USBFS_CyBtldrCommReset(void) ;
-    cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
-    cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+    cystatus USBFS_CyBtldrCommRead       (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                         ;
 
-    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER      (64u)    /* EP 1 OUT */
-    #define USBFS_BTLDR_SIZEOF_READ_BUFFER       (64u)    /* EP 2 IN */
-    #define USBFS_BTLDR_MAX_PACKET_SIZE          USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+    #define USBFS_BTLDR_OUT_EP      (0x01u)
+    #define USBFS_BTLDR_IN_EP       (0x02u)
+
+    #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER  (64u)   /* EP 1 OUT */
+    #define USBFS_BTLDR_SIZEOF_READ_BUFFER   (64u)   /* EP 2 IN  */
+    #define USBFS_BTLDR_MAX_PACKET_SIZE      USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+    #define USBFS_BTLDR_WAIT_1_MS            (1u)    /* Time Out quantity equal 1mS */
 
     /* These defines active if used USBFS interface as an
     *  IO Component for bootloading. When Custom_Interface selected
     *  in Bootloder configuration as the IO Component, user must
-    *  provide these functions
+    *  provide these functions.
     */
     #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
         #define CyBtldrCommStart        USBFS_CyBtldrCommStart
@@ -249,13 +260,13 @@ void   USBFS_Resume(void) ;
         #define CyBtldrCommRead         USBFS_CyBtldrCommRead
     #endif  /*End   CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP  */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP  */
 
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-    void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+    void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
                                                     ;
     void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */
+#endif /*  USBFS_EP_MM != USBFS__EP_MANUAL) */
 
 #if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
     void USBFS_MIDI_EP_Init(void) ;
@@ -270,7 +281,7 @@ void   USBFS_Resume(void) ;
         void USBFS_MIDI_OUT_EP_Service(void) ;
     #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
 
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */
+#endif /*  USBFS_ENABLE_MIDI_API != 0u */
 
 /* Renamed Functions for backward compatibility.
 *  Should not be used in new designs.
@@ -483,10 +494,10 @@ void   USBFS_Resume(void) ;
 #define USBFS_EP_USAGE_TYPE_RESERVED         (0x30u)
 #define USBFS_EP_USAGE_TYPE_MASK             (0x30u)
 
-/* Endpoint Status defines */
+/* point Status defines */
 #define USBFS_EP_STATUS_LENGTH               (0x02u)
 
-/* Endpoint Device defines */
+/* point Device defines */
 #define USBFS_DEVICE_STATUS_LENGTH           (0x02u)
 
 #define USBFS_STATUS_LENGTH_MAX \
@@ -513,14 +524,60 @@ void   USBFS_Resume(void) ;
     /* DMA manual mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (0u)
     #define USBFS_DMA_REQUEST_PER_BURST      (0u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
     /* DMA automatic mode defines */
     #define USBFS_DMA_BYTES_PER_BURST        (32u)
+    #define USBFS_DMA_BYTES_REPEAT           (2u)
     /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes  44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
     #define USBFS_DMA_BUF_SIZE               (0x55u)
     #define USBFS_DMA_REQUEST_PER_BURST      (1u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+    #if(USBFS_DMA1_REMOVE == 0u)
+        #define USBFS_ep1_TD_TERMOUT_EN      USBFS_ep1__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep1_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA1_REMOVE == 0u */
+    #if(USBFS_DMA2_REMOVE == 0u)
+        #define USBFS_ep2_TD_TERMOUT_EN      USBFS_ep2__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep2_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA2_REMOVE == 0u */
+    #if(USBFS_DMA3_REMOVE == 0u)
+        #define USBFS_ep3_TD_TERMOUT_EN      USBFS_ep3__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep3_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA3_REMOVE == 0u */
+    #if(USBFS_DMA4_REMOVE == 0u)
+        #define USBFS_ep4_TD_TERMOUT_EN      USBFS_ep4__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep4_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA4_REMOVE == 0u */
+    #if(USBFS_DMA5_REMOVE == 0u)
+        #define USBFS_ep5_TD_TERMOUT_EN      USBFS_ep5__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep5_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA5_REMOVE == 0u */
+    #if(USBFS_DMA6_REMOVE == 0u)
+        #define USBFS_ep6_TD_TERMOUT_EN      USBFS_ep6__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep6_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA6_REMOVE == 0u */
+    #if(USBFS_DMA7_REMOVE == 0u)
+        #define USBFS_ep7_TD_TERMOUT_EN      USBFS_ep7__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep7_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA7_REMOVE == 0u */
+    #if(USBFS_DMA8_REMOVE == 0u)
+        #define USBFS_ep8_TD_TERMOUT_EN      USBFS_ep8__TD_TERMOUT_EN
+    #else
+        #define USBFS_ep8_TD_TERMOUT_EN      (0u)
+    #endif /* USBFS_DMA8_REMOVE == 0u */
+
+    #define     USBFS_EP17_SR_MASK           (0x7fu)
+    #define     USBFS_EP8_SR_MASK            (0x03u)
+
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
 /* DIE ID string descriptor defines */
 #if defined(USBFS_ENABLE_IDSN_STRING)
@@ -805,7 +862,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #if(!CY_PSOC5LP)
     #define USBFS_USBIO_CR2_PTR      (  (reg8 *) USBFS_USB__USBIO_CR2)
     #define USBFS_USBIO_CR2_REG      (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /* End CY_PSOC5LP */
+#endif /*  CY_PSOC5LP */
 
 #define USBFS_DIE_ID             CYDEV_FLSHID_CUST_TABLES_BASE
 
@@ -831,8 +888,8 @@ extern volatile uint8 USBFS_deviceStatus;
     #else
         #define USBFS_VBUS_PS_PTR        (  (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
         #define USBFS_VBUS_MASK          (0x01u)
-    #endif /* End USBFS_EXTERN_VBUS == 0u */
-#endif /* End USBFS_MON_VBUS */
+    #endif /*  USBFS_EXTERN_VBUS == 0u */
+#endif /*  USBFS_MON_VBUS */
 
 /* Renamed Registers for backward compatibility.
 *  Should not be used in new designs.
@@ -1010,7 +1067,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
     #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
     #define USBFS_USB_ISR_VECT   ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /* End CYDEV_CHIP_DIE_EXPECT */
+#endif /*  CYDEV_CHIP_DIE_EXPECT */
 
 
 /***************************************
@@ -1131,6 +1188,8 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_ARB_EPX_CFG_CRC_BYPASS     (0x04u)
 #define USBFS_ARB_EPX_CFG_DMA_REQ        (0x02u)
 #define USBFS_ARB_EPX_CFG_IN_DATA_RDY    (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT        (USBFS_ARB_EPX_CFG_RESET | \
+                                                     USBFS_ARB_EPX_CFG_CRC_BYPASS)
 
 #define USBFS_ARB_EPX_SR_IN_BUF_FULL     (0x01u)
 #define USBFS_ARB_EPX_SR_DMA_GNT         (0x02u)
@@ -1146,7 +1205,7 @@ extern volatile uint8 USBFS_deviceStatus;
     #define USBFS_ARB_EPX_INT_MASK           (0x1Du)
 #else
     #define USBFS_ARB_EPX_INT_MASK           (0x1Fu)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 #define USBFS_ARB_INT_MASK       (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
                                             (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
                                             (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
@@ -1183,7 +1242,7 @@ extern volatile uint8 USBFS_deviceStatus;
 #define USBFS_DYN_RECONFIG_RDY_STS       (0x10u)
 
 
-#endif /* End CY_USBFS_USBFS_H */
+#endif /*  CY_USBFS_USBFS_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
index e942a8f8..3840625b 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dm_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dm_DM_STRONG     Strong Drive 
+*  USBFS_Dm_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dm_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dm_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dm_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dm_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dm_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dm_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
index bbfcfee4..42e93ad7 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
index 21242d52..2f649353 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dm.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dm_0		USBFS_Dm__0__PC
+#define USBFS_Dm_0		(USBFS_Dm__0__PC)
 
 #endif /* End Pins USBFS_Dm_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
index 5904f4ae..6f4efeff 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.c  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file contains API to enable firmware control of a Pins component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -51,7 +51,16 @@ void USBFS_Dp_Write(uint8 value)
 *  Change the drive mode on the pins of the port.
 * 
 * Parameters:  
-*  mode:  Change the pins to this drive mode.
+*  mode:  Change the pins to one of the following drive modes.
+*
+*  USBFS_Dp_DM_STRONG     Strong Drive 
+*  USBFS_Dp_DM_OD_HI      Open Drain, Drives High 
+*  USBFS_Dp_DM_OD_LO      Open Drain, Drives Low 
+*  USBFS_Dp_DM_RES_UP     Resistive Pull Up 
+*  USBFS_Dp_DM_RES_DWN    Resistive Pull Down 
+*  USBFS_Dp_DM_RES_UPDWN  Resistive Pull Up/Down 
+*  USBFS_Dp_DM_DIG_HIZ    High Impedance Digital 
+*  USBFS_Dp_DM_ALG_HIZ    High Impedance Analog 
 *
 * Return: 
 *  None
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
index 217b6a3f..a3671299 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /* Check to see if required defines such as CY_PSOC5A are available */
 /* They are defined starting with cy_boot v3.0 */
 #if !defined (CY_PSOC5A)
-    #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+    #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
 #endif /* (CY_PSOC5A) */
 
 /* APIs are not generated for P15[7:6] */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
index 702fb7ed..fd693968 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_Dp.h  
-* Version 1.90
+* Version 2.10
 *
 * Description:
 *  This file containts Control Register function prototypes and register defines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions, 
 * disclaimers, and limitations in the end user license agreement accompanying 
 * the software package with which this file was provided.
@@ -25,7 +25,7 @@
 /***************************************
 *              Constants        
 ***************************************/
-#define USBFS_Dp_0		USBFS_Dp__0__PC
+#define USBFS_Dp_0		(USBFS_Dp__0__PC)
 
 #endif /* End Pins USBFS_Dp_ALIASES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c
index e837975c..9282b04f 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB AUDIO Class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,9 +21,9 @@
 
 #include "USBFS_audio.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -52,7 +53,7 @@
                                                                                   USBFS_VOL_MAX_MSB};
     volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,
                                                                                      USBFS_VOL_RES_MSB};
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+#endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
 
 /*******************************************************************************
@@ -93,17 +94,18 @@
 uint8 USBFS_DispatchAUDIOClassRqst(void) 
 {
     uint8 requestHandled = USBFS_FALSE;
+    uint8 bmRequestType  = CY_GET_REG8(USBFS_bmRequestType);
 
     #if defined(USBFS_ENABLE_AUDIO_STREAMING)
         uint8 epNumber;
         epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;
-    #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+    #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
-    if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
+
+    if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
     {
         /* Control Read */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
             /* Endpoint */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -112,12 +114,12 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlRead();
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_READ_REQUESTS` Place other request handler here */
 
@@ -127,8 +129,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -140,7 +141,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */
 
                         /* `#END` */
-                        
+
                          /* Entity ID Control Selector is MUTE */
                         USBFS_currentTD.wCount = 1u;
                         USBFS_currentTD.pData  = &USBFS_currentMute;
@@ -199,7 +200,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                         USBFS_currentTD.wCount = 0u;
                         requestHandled   = USBFS_InitControlWrite();
 
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
 
@@ -213,27 +214,25 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
         {   /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \
-                                                                                    USBFS_RQST_DIR_H2D)
+    else
     {
         /* Control Write */
-        if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_EP)
+        if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
         {
-            /* Endpoint */
+            /* point */
             switch (CY_GET_REG8(USBFS_bRequest))
             {
                 case USBFS_SET_CUR:
                 #if defined(USBFS_ENABLE_AUDIO_STREAMING)
                     if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
                     {
-                         /* Endpoint Control Selector is Sampling Frequency */
+                         /* point Control Selector is Sampling Frequency */
                         USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
                         USBFS_currentTD.pData  = USBFS_currentSampleFrequency[epNumber];
                         requestHandled   = USBFS_InitControlWrite();
                         USBFS_frequencyChanged = epNumber;
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
 
@@ -243,8 +242,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
                     break;
             }
         }
-        else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
-                                                                                    USBFS_RQST_RCPT_IFC)
+        else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
         {
             /* Interface or Entity ID */
             switch (CY_GET_REG8(USBFS_bRequest))
@@ -279,7 +277,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
                         /* `#END` */
                     }
-                #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+                #endif /*  USBFS_ENABLE_AUDIO_STREAMING */
 
                 /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
 
@@ -290,17 +288,14 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
             }
         }
         else
-        {   /* USBFS_RQST_RCPT_OTHER */
+        {
+            /* USBFS_RQST_RCPT_OTHER */
         }
     }
-    else
-    {   /* requestHandled is initialized as FALSE by default */
-    }
 
     return(requestHandled);
 }
 
-
 #endif /* USER_SUPPLIED_AUDIO_HANDLER */
 
 
@@ -312,7 +307,7 @@ uint8 USBFS_DispatchAUDIOClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_AUDIO_CLASS*/
+#endif  /*  USBFS_ENABLE_AUDIO_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h
index 0e0feb20..6aa9357c 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_audio.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -45,7 +48,7 @@
 #define USBFS_GET_MEM                    (0x85u)
 #define USBFS_GET_STAT                   (0xFFu)
 
-/* Endpoint Control Selectors (AUDIO Table A-19) */
+/* point Control Selectors (AUDIO Table A-19) */
 #define USBFS_EP_CONTROL_UNDEFINED       (0x00u)
 #define USBFS_SAMPLING_FREQ_CONTROL      (0x01u)
 #define USBFS_PITCH_CONTROL              (0x02u)
@@ -89,7 +92,7 @@ extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];
 extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];
 
-#endif /* End CY_USBFS_USBFS_audio_H */
+#endif /*  CY_USBFS_USBFS_audio_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c
index 3cbb2f9d..747b0b0e 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_boot.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Boot loader API for USBFS Component.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,23 +20,11 @@
                                           (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
 
 
-/***************************************
-*    Bootloader defines
-***************************************/
-
-#define USBFS_CyBtLdrStarttimer(X, T)         {USBFS_universalTime = T * 10; X = 0u;}
-#define USBFS_CyBtLdrChecktimer(X)            ((X++ < USBFS_universalTime) ? 1u : 0u)
-
-#define USBFS_BTLDR_OUT_EP      (0x01u)
-#define USBFS_BTLDR_IN_EP       (0x02u)
-
-
 /***************************************
 *    Bootloader Variables
 ***************************************/
 
-static uint16 USBFS_universalTime;
-static uint8 USBFS_started = 0u;
+static uint8  USBFS_started = 0u;
 
 
 /*******************************************************************************
@@ -68,7 +56,6 @@ void USBFS_CyBtldrCommStart(void)
 
     /* USB component started, the correct enumeration will be checked in first Read operation */
     USBFS_started = 1u;
-
 }
 
 
@@ -100,13 +87,13 @@ void USBFS_CyBtldrCommStop(void)
 *  Resets the receive and transmit communication Buffers.
 *
 * Parameters:
-*  None.
+*  None
 *
 * Return:
-*  None.
+*  None
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
 void USBFS_CyBtldrCommReset(void) 
@@ -135,39 +122,39 @@ void USBFS_CyBtldrCommReset(void)
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    uint16 time;
-    cystatus status;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
     /* Enable IN transfer */
     USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);
 
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
-
     /* Wait for the master to read it. */
-    while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+    while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&
+           (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)
     {
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
     else
     {
         *count = size;
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
 
-    return(status);
+    return(retCode);
 }
 
 
@@ -193,70 +180,77 @@ cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8
 *  Returns the value that best describes the problem.
 *
 * Reentrant:
-*  No.
+*  No
 *
 *******************************************************************************/
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
                                                             
 {
-    cystatus status;
-    uint16 time;
+    cystatus retCode;
+    uint16 timeoutMs;
+
+    timeoutMs = ((uint16) 10u * timeOut);  /* Convert from 10mS check to number 1mS checks */
 
-    if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
+    if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
     {
         size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;
     }
-    /* Start a timer to wait on. */
-    USBFS_CyBtLdrStarttimer(time, timeOut);
 
     /* Wait on enumeration in first time */
-    if(USBFS_started)
+    if (0u != USBFS_started)
     {
         /* Wait for Device to enumerate */
-        while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))
+        while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))
         {
-            CyDelay(1u); /* 1ms delay */
+            CyDelay(USBFS_BTLDR_WAIT_1_MS);
+            timeoutMs--;
         }
+
         /* Enable first OUT, if enumeration complete */
-        if(USBFS_GetConfiguration())
+        if (0u != USBFS_GetConfiguration())
         {
-            USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
+            (void) USBFS_IsConfigurationChanged();  /* Clear configuration changes state status */
             USBFS_CyBtldrCommReset();
             USBFS_started = 0u;
         }
     }
     else /* Check for configuration changes, has been done by Host */
     {
-        if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */
+        if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */
         {
-            if(USBFS_GetConfiguration() != 0u)   /* Init OUT endpoints when device reconfigured */
+            if (0u != USBFS_GetConfiguration())   /* Init OUT endpoints when device reconfigured */
             {
                 USBFS_CyBtldrCommReset();
             }
         }
     }
+
+    timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */
+
     /* Wait on next packet */
     while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \
-           USBFS_CyBtLdrChecktimer(time))
+          (0u != timeoutMs))
     {
-        CyDelay(1u); /* 1ms delay */
+        CyDelay(USBFS_BTLDR_WAIT_1_MS);
+        timeoutMs--;
     }
 
     /* OUT EP has completed */
     if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)
     {
         *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);
-        status = CYRET_SUCCESS;
+        retCode = CYRET_SUCCESS;
     }
     else
     {
         *count = 0u;
-        status = CYRET_TIMEOUT;
+        retCode = CYRET_TIMEOUT;
     }
-    return(status);
+
+    return(retCode);
 }
 
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+#endif /*  CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
index 7d65d6b7..1a68c5f6 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c
@@ -1,14 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  USB HID Class request handler.
+*  USB CDC class request handler.
 *
-* Note:
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
 *
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -26,7 +27,13 @@
 *    CDC Variables
 ***************************************/
 
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =
+{
+    0x00u, 0xC2u, 0x01u, 0x00u,     /* Data terminal rate 115200 */
+    0x00u,                          /* 1 Stop bit */
+    0x00u,                          /* None parity */
+    0x08u                           /* 8 data bits */
+};
 volatile uint8 USBFS_lineChanged;
 volatile uint16 USBFS_lineControlBitmap;
 volatile uint8 USBFS_cdc_data_in_ep;
@@ -36,7 +43,9 @@ volatile uint8 USBFS_cdc_data_out_ep;
 /***************************************
 *     Static Function Prototypes
 ***************************************/
-static uint16 USBFS_StrLen(const char8 string[]) ;
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
+    static uint16 USBFS_StrLen(const char8 string[]) ;
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */
 
 
 /***************************************
@@ -138,7 +147,6 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 ***************************************/
 #if (USBFS_ENABLE_CDC_CLASS_API != 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_CDC_Init
     ********************************************************************************
@@ -173,14 +181,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a specified number of bytes from the location specified by a
-    *  pointer to the PC.
+    *  This function sends a specified number of bytes from the location specified
+    *  by a pointer to the PC. The USBFS_CDCIsReady() function should be
+    *  called before sending new data, to be sure that the previous data has
+    *  finished sending.
+    *  If the last sent packet is less than maximum packet size the USB transfer
+    *  of this short packet will identify the end of the segment. If the last sent
+    *  packet is exactly maximum packet size, it shall be followed by a zero-length
+    *  packet (which is a short packet) to assure the end of segment is properly
+    *  identified. To send zero-length packet, use USBFS_PutData() API
+    *  with length parameter set to zero.
     *
     * Parameters:
     *  pData: pointer to the buffer containing data to be sent.
     *  length: Specifies the number of bytes to send from the pData
     *  buffer. Maximum length will be limited by the maximum packet
-    *  size for the endpoint.
+    *  size for the endpoint. Data will be lost if length is greater than Max
+    *  Packet Size.
     *
     * Return:
     *  None.
@@ -239,10 +256,15 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Sends a null terminated string to the PC.
+    *  This function sends a null terminated string to the PC. This function will
+    *  block if there is not enough memory to place the whole string. It will block
+    *  until the entire string has been written to the transmit buffer.
+    *  The USBUART_CDCIsReady() function should be called before sending data with
+    *  a new call to USBFS_PutString(), to be sure that the previous data
+    *  has finished sending.
     *
     * Parameters:
-    *  string: pointer to the string to be sent to the PC
+    *  string: pointer to the string to be sent to the PC.
     *
     * Return:
     *  None.
@@ -254,41 +276,44 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     * Reentrant:
     *  No.
     *
-    * Theory:
-    *  This function will block if there is not enough memory to place the whole
-    *  string, it will block until the entire string has been written to the
-    *  transmit buffer.
-    *
     *******************************************************************************/
     void USBFS_PutString(const char8 string[]) 
     {
-        uint16 str_length;
-        uint16 send_length;
-        uint16 buf_index = 0u;
+        uint16 strLength;
+        uint16 sendLength;
+        uint16 bufIndex = 0u;
 
         /* Get length of the null terminated string */
-        str_length = USBFS_StrLen(string);
+        strLength = USBFS_StrLen(string);
         do
         {
             /* Limits length to maximum packet size for the EP */
-            send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
-                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;
+            sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
+                          USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;
              /* Enable IN transfer */
-            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);
-            str_length -= send_length;
+            USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);
+            strLength -= sendLength;
 
-            /* If more data are present to send */
-            if(str_length > 0u)
+            /* If more data are present to send or full packet was sent */
+            if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))
             {
-                buf_index += send_length;
+                bufIndex += sendLength;
                 /* Wait for the Host to read it. */
                 while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==
                                           USBFS_IN_BUFFER_FULL)
                 {
                     ;
                 }
+                /* If the last sent packet is exactly maximum packet size,
+                *  it shall be followed by a zero-length packet to assure the
+                *  end of segment is properly identified by the terminal.
+                */
+                if(strLength == 0u)
+                {
+                    USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);
+                }
             }
-        }while(str_length > 0u);
+        }while(strLength > 0u);
     }
 
 
@@ -357,12 +382,17 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  This function returns the number of bytes that were received from the PC.
+    *  The returned length value should be passed to USBFS_GetData() as
+    *  a parameter to read all received data. If all of the received data is not
+    *  read at one time by the USBFS_GetData() API, the unread data will
+    *  be lost.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  Returns the number of received bytes.
+    *  Returns the number of received bytes. The maximum amount of received data at
+    *  a time is limited by the maximum packet size for the endpoint.
     *
     * Global variables:
     *   USBFS_cdc_data_out_ep: CDC OUT endpoint number used.
@@ -370,12 +400,16 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *******************************************************************************/
     uint16 USBFS_GetCount(void) 
     {
-        uint16 bytesCount = 0u;
+        uint16 bytesCount;
 
         if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)
         {
             bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);
         }
+        else
+        {
+            bytesCount = 0u;
+        }
 
         return(bytesCount);
     }
@@ -387,9 +421,9 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     *
     * Summary:
     *  Returns a nonzero value if the component received data or received
-    *  zero-length packet. The GetAll() or GetData() API should be called to read
-    *  data from the buffer and re-init OUT endpoint even when zero-length packet
-    *  received.
+    *  zero-length packet. The USBFS_GetAll() or
+    *  USBFS_GetData() API should be called to read data from the buffer
+    *  and re-init OUT endpoint even when zero-length packet received.
     *
     * Parameters:
     *  None.
@@ -413,17 +447,19 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Returns a nonzero value if the component is ready to send more data to the
-    *  PC. Otherwise returns zero. Should be called before sending new data to
-    *  ensure the previous data has finished sending.This function returns the
-    *  number of bytes that were received from the PC.
+    *  This function returns a nonzero value if the component is ready to send more
+    *  data to the PC; otherwise, it returns zero. The function should be called
+    *  before sending new data when using any of the following APIs:
+    *  USBFS_PutData(),USBFS_PutString(),
+    *  USBFS_PutChar or USBFS_PutCRLF(),
+    *  to be sure that the previous data has finished sending.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If the buffer can accept new data then this function returns a nonzero value.
-    *  Otherwise zero is returned.
+    *  If the buffer can accept new data, this function returns a nonzero value.
+    *  Otherwise, it returns zero.
     *
     * Global variables:
     *   USBFS_cdc_data_in_ep: CDC IN endpoint number used.
@@ -440,10 +476,12 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Gets a specified number of bytes from the input buffer and places it in a
-    *  data array specified by the passed pointer.
-    *  USBFS_DataIsReady() API should be called before, to be sure
-    *  that data is received from the Host.
+    *  This function gets a specified number of bytes from the input buffer and
+    *  places them in a data array specified by the passed pointer.
+    *  The USBFS_DataIsReady() API should be called first, to be sure
+    *  that data is received from the host. If all received data will not be read at
+    *  once, the unread data will be lost. The USBFS_GetData() API should
+    *  be called to get the number of bytes that were received.
     *
     * Parameters:
     *  pData: Pointer to the data array where data will be placed.
@@ -502,7 +540,8 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  Reads one byte of received data from the buffer.
+    *  This function reads one byte of received data from the buffer. If more than
+    *  one byte has been received from the host, the rest of the data will be lost.
     *
     * Parameters:
     *  None.
@@ -531,17 +570,23 @@ uint8 USBFS_DispatchCDCClassRqst(void)
     ********************************************************************************
     *
     * Summary:
-    *  This function returns clear on read status of the line.
+    *  This function returns clear on read status of the line. It returns not zero
+    *  value when the host sends updated coding or control information to the
+    *  device. The USBFS_GetDTERate(), USBFS_GetCharFormat()
+    *  or USBFS_GetParityType() or USBFS_GetDataBits() API
+    *  should be called to read data coding information.
+    *  The USBFS_GetLineControl() API should be called to read line
+    *  control information.
     *
     * Parameters:
     *  None.
     *
     * Return:
-    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not
-    *  zero value returned. Otherwise zero is returned.
+    *  If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it
+    *  returns a nonzero value. Otherwise, it returns zero.
     *
     * Global variables:
-    *  USBFS_transferState - it is checked to be sure then OUT data
+    *  USBFS_transferState: it is checked to be sure then OUT data
     *    phase has been complete, and data written to the lineCoding or Control
     *    Bitmap buffer.
     *  USBFS_lineChanged: used as a flag to be aware that Host has been
@@ -689,7 +734,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
         return(USBFS_lineControlBitmap);
     }
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API*/
 
 
 /*******************************************************************************
@@ -700,7 +745,7 @@ uint8 USBFS_DispatchCDCClassRqst(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_CDC_CLASS*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS*/
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
index ca79f63e..0b95f086 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h
@@ -1,13 +1,16 @@
 /*******************************************************************************
 * File Name: USBFS_cdc.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component.
+*  Header File for the USBFS component.
 *  Contains CDC class prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
 ********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -41,7 +44,7 @@
     uint8 USBFS_GetParityType(void) ;
     uint8 USBFS_GetDataBits(void) ;
     uint16 USBFS_GetLineControl(void) ;
-#endif  /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif  /*  USBFS_ENABLE_CDC_CLASS_API */
 
 
 /***************************************
@@ -86,7 +89,7 @@ extern volatile uint16 USBFS_lineControlBitmap;
 extern volatile uint8 USBFS_cdc_data_in_ep;
 extern volatile uint8 USBFS_cdc_data_out_ep;
 
-#endif /* End CY_USBFS_USBFS_cdc_H */
+#endif /*  CY_USBFS_USBFS_cdc_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
index 8a8f5bea..e1fa37f1 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf
@@ -1,12 +1,12 @@
 ;******************************************************************************
 ; File Name: USBFS_cdc.inf
-; Version 2.60
+; Version 2.80
 ;
 ; Description:
 ;  Windows USB CDC setup file for USBUART Device.
 ;
 ;******************************************************************************
-; Copyright 2007-2013, Cypress Semiconductor Corporation.  All rights reserved.
+; Copyright 2007-2014, Cypress Semiconductor Corporation.  All rights reserved.
 ; You may use this file only in accordance with the license, terms, conditions,
 ; disclaimers, and limitations in the end user license agreement accompanying
 ; the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c
index 7b5dc275..16f6191b 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_cls.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Class request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -57,8 +57,8 @@ uint8 USBFS_DispatchClassRqst(void)
             break;
         case USBFS_RQST_RCPT_EP:         /* Class-specific request directed to the endpoint */
             /* Find related interface to the endpoint, wIndexLo contain EP number */
-            interfaceNumber =
-                USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;
+            interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &
+                              USBFS_DIR_UNUSED].interface;
             break;
         default:    /* RequestHandled is initialized as FALSE by default */
             break;
@@ -74,7 +74,7 @@ uint8 USBFS_DispatchClassRqst(void)
         case USBFS_CLASS_AUDIO:
             #if defined(USBFS_ENABLE_AUDIO_CLASS)
                 requestHandled = USBFS_DispatchAUDIOClassRqst();
-            #endif /* USBFS_ENABLE_HID_CLASS */
+            #endif /* USBFS_CLASS_AUDIO */
             break;
         case USBFS_CLASS_CDC:
             #if defined(USBFS_ENABLE_CDC_CLASS)
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
index 094719e6..66a0c123 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_descr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB descriptors and storage.
@@ -8,7 +8,7 @@
 *  Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,7 @@
 
 /*****************************************************************************
 *  User supplied descriptors.  If you want to specify your own descriptors,
-*  remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and
-*  add your descriptors.
+*  define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.
 *****************************************************************************/
 /* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c
index f4308eab..a5fd19d6 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_drv.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Endpoint 0 Driver for the USBFS Component.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c
index d758bf4d..37691f22 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_episr.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Data endpoint Interrupt Service Routines
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -16,9 +16,13 @@
 
 #include "USBFS.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    #include "USBFS_EP8_DMA_Done_SR.h"
+    #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 
 /***************************************
@@ -48,7 +52,8 @@
     ******************************************************************************/
     CY_ISR(USBFS_EP_1_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT)  && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -56,7 +61,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -72,23 +78,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &
                                                                     (uint8)~USBFS_SIE_EP_INT_EP1_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP1)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP1_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP1_ISR_REMOVE */
+#endif   /*  USBFS_EP1_ISR_REMOVE */
 
 
 #if(USBFS_EP2_ISR_REMOVE == 0u)
@@ -109,7 +117,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_2_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -117,7 +126,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
@@ -133,23 +143,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP2_MASK);
 
-        #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP2)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP2_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
     }
 
-#endif   /* End USBFS_EP2_ISR_REMOVE */
+#endif   /*  USBFS_EP2_ISR_REMOVE */
 
 
 #if(USBFS_EP3_ISR_REMOVE == 0u)
@@ -170,7 +182,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_3_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
 
@@ -178,7 +191,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -194,23 +208,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP3_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP3)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP3_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP3_ISR_REMOVE */
+#endif   /*  USBFS_EP3_ISR_REMOVE */
 
 
 #if(USBFS_EP4_ISR_REMOVE == 0u)
@@ -231,7 +247,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_4_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -239,7 +256,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -255,23 +273,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP4_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP4)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP4_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP4_ISR_REMOVE */
+#endif   /*  USBFS_EP4_ISR_REMOVE */
 
 
 #if(USBFS_EP5_ISR_REMOVE == 0u)
@@ -292,7 +312,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_5_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -300,7 +321,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -316,22 +338,24 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP5_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP5)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP5_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
-#endif   /* End USBFS_EP5_ISR_REMOVE */
+#endif   /*  USBFS_EP5_ISR_REMOVE */
 
 
 #if(USBFS_EP6_ISR_REMOVE == 0u)
@@ -352,7 +376,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_6_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -360,7 +385,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -376,23 +402,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP6_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP6)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP6_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP6_ISR_REMOVE */
+#endif   /*  USBFS_EP6_ISR_REMOVE */
 
 
 #if(USBFS_EP7_ISR_REMOVE == 0u)
@@ -413,7 +441,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_7_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -421,7 +450,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -437,23 +467,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP7_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP7)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT  */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT  */
 
         /* `#START EP7_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP7_ISR_REMOVE */
+#endif   /*  USBFS_EP7_ISR_REMOVE */
 
 
 #if(USBFS_EP8_ISR_REMOVE == 0u)
@@ -474,7 +506,8 @@
     *******************************************************************************/
     CY_ISR(USBFS_EP_8_ISR)
     {
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             uint8 int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
 
@@ -482,7 +515,8 @@
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             int_en = EA;
             CyGlobalIntEnable;  /* Make sure nested interrupt is enabled */
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
@@ -498,23 +532,25 @@
         CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
                                                                         & (uint8)~USBFS_SIE_EP_INT_EP8_MASK);
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT)
             if(USBFS_midi_out_ep == USBFS_EP8)
             {
                 USBFS_MIDI_OUT_EP_Service();
             }
-        #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+        #endif /*  USBFS_ISR_SERVICE_MIDI_OUT */
 
         /* `#START EP8_END_USER_CODE` Place your code here */
 
         /* `#END` */
 
-        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+        #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+                     USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
             EA = int_en;
         #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT  */
     }
 
-#endif   /* End USBFS_EP8_ISR_REMOVE */
+#endif   /*  USBFS_EP8_ISR_REMOVE */
 
 
 /*******************************************************************************
@@ -611,6 +647,17 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                         /* Clear Data ready status */
                         *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=
                                                                     (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                        #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+                            /* Setup common area DMA with rest of the data */
+                            if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)
+                            {
+                                USBFS_LoadNextInEP(ep, 0u);
+                            }
+                            else
+                            {
+                                USBFS_inBufFull[ep] = 1u;
+                            }
+                        #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
                         /* Write the Mode register */
                         CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);
                         #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)
@@ -618,7 +665,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                             {   /* Clear MIDI input pointer */
                                 USBFS_midiInPointer = 0u;
                             }
-                        #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                 }
                 /* (re)arm Out EP only for mode2 */
@@ -634,7 +681,7 @@ CY_ISR(USBFS_BUS_RESET_ISR)
                                                                                     USBFS_EP[ep].epMode);
                         }
                     }
-                #endif /* End USBFS_EP_MM */
+                #endif /*  USBFS_EP_MM */
 
                 /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */
 
@@ -652,7 +699,82 @@ CY_ISR(USBFS_BUS_RESET_ISR)
         /* `#END` */
     }
 
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    /******************************************************************************
+    * Function Name: USBFS_EP_DMA_DONE_ISR
+    *******************************************************************************
+    *
+    * Summary:
+    *  Endpoint 1 DMA Done Interrupt Service Routine
+    *
+    * Parameters:
+    *  None.
+    *
+    * Return:
+    *  None.
+    *
+    ******************************************************************************/
+    CY_ISR(USBFS_EP_DMA_DONE_ISR)
+    {
+        uint8 int8Status;
+        uint8 int17Status;
+        uint8 ep_status;
+        uint8 ep = USBFS_EP1;
+        uint8 ptr = 0u;
+
+        /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
+
+        /* `#END` */
+
+        /* Read clear on read status register with the EP source of interrupt */
+        int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;
+        int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;
+
+        while(int8Status != 0u)
+        {
+            while(int17Status != 0u)
+            {
+                if((int17Status & 1u) != 0u)  /* If EpX interrupt present */
+                {
+                    /* Read Endpoint Status Register */
+                    ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));
+                    if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&
+                        (USBFS_inBufFull[ep] == 0u))
+                    {
+                        /* `#START EP_DMA_DONE_USER_CODE` Place your code here */
+
+                        /* `#END` */
+
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
+                        /* repeat 2 last bytes to prefetch endpoint area */
+                        CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
+                                    USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);
+                        USBFS_LoadNextInEP(ep, 1);
+                        /* Set Data ready status, This will generate DMA request */
+                        * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+                    }
+                }
+                ptr += USBFS_EPX_CNTX_ADDR_OFFSET;               /* prepare pointer for next EP */
+                ep++;
+                int17Status >>= 1u;
+            }
+            int8Status >>= 1u;
+            if(int8Status != 0u)
+            {
+                /* Prepare pointer for EP8 */
+                ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+                ep = USBFS_EP8;
+                int17Status = int8Status & 0x01u;
+            }
+        }
+
+        /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
+
+        /* `#END` */
+    }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c
index cc1ea1e2..5a9ac690 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c
@@ -1,14 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_hid.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB HID Class request handler.
 *
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
+*
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -416,7 +419,7 @@ void USBFS_FindReport(void)
 
 /* `#END` */
 
-#endif  /* End USBFS_ENABLE_HID_CLASS */
+#endif  /*  USBFS_ENABLE_HID_CLASS */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h
index a34e4e73..c8075d2a 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h
@@ -1,12 +1,15 @@
 /*******************************************************************************
 * File Name: USBFS_hid.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
-*  Header File for the USFS component. Contains prototypes and constant values.
+*  Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+*  Device Class Definition for Human Interface Devices (HID) Version 1.11
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -58,7 +61,7 @@ uint8 USBFS_GetProtocol(uint8 interface) ;
 #define USBFS_HID_GET_REPORT_OUTPUT      (0x02u)
 #define USBFS_HID_GET_REPORT_FEATURE     (0x03u)
 
-#endif /* End CY_USBFS_USBFS_hid_H */
+#endif /*  CY_USBFS_USBFS_hid_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c
index 0247caf2..7354b89d 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c
@@ -1,14 +1,18 @@
 /*******************************************************************************
 * File Name: USBFS_midi.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  MIDI Streaming request handler.
 *  This file contains routines for sending and receiving MIDI
 *  messages, and handles running status in both directions.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -60,15 +64,15 @@
         volatile uint16 USBFS_midiInPointer;                            /* Input endpoint buffer pointer */
     #else
         volatile uint8 USBFS_midiInPointer;                             /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */
     volatile uint8 USBFS_midi_in_ep;                                    /* Input endpoint number */
     uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];       /* Input endpoint buffer */
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
     volatile uint8 USBFS_midi_out_ep;                                   /* Output endpoint number */
     uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE];     /* Output endpoint buffer */
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event;            /* MIDI RX status structure */
@@ -79,8 +83,8 @@
         static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event;        /* MIDI RX status structure */
         static volatile uint8 USBFS_MIDI2_TxRunStat;                     /* MIDI Output running status */
         volatile uint8 USBFS_MIDI2_InqFlags;                             /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
 
 /***************************************
@@ -134,30 +138,30 @@ void USBFS_MIDI_EP_Init(void)
 {
     #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
        USBFS_midiInPointer = 0u;
-    #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
 
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
         #if (USBFS_MIDI_IN_BUFF_SIZE > 0)
             /* Init DMA configurations for IN EP*/
             USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,
                                                                                 USBFS_MIDI_IN_BUFF_SIZE);
-                                                                                
-        #endif  /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+        #endif  /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
         #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
             /* Init DMA configurations for OUT EP*/
             (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,
                                                                                 USBFS_MIDI_OUT_BUFF_SIZE);
-        #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-    #endif  /* End USBFS__EP_DMAAUTO */
+        #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
+    #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
 
     #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
         USBFS_EnableOutEP(USBFS_midi_out_ep);
-    #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+    #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
 
     /* Initialize the MIDI port(s) */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
         USBFS_MIDI_Init();
-    #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 }
 
 #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
@@ -199,37 +203,43 @@ void USBFS_MIDI_EP_Init(void)
         #else
             uint8 outLength;
             uint8 outPointer;
-        #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */
+        #endif /*  USBFS_MIDI_OUT_BUFF_SIZE >=256 */
 
         uint8 dmaState = 0u;
 
         /* Service the USB MIDI output endpoint */
         if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)
         {
-            #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+            #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                 outLength = USBFS_GetEPCount(USBFS_midi_out_ep);
             #else
                 outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);
-            #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+            #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
             #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
-                #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+                #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)
                     outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, outLength);
                 #else
                     outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,
                                                                     USBFS_midiOutBuffer, (uint16)outLength);
-                #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+                #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
                 #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                     do  /* wait for DMA transfer complete */
                     {
-                        (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
-                    }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
-            #endif  /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+                        (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
+                    }
+                    while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
+                #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */
+
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
+
             if(dmaState != 0u)
             {
                 /* Suppress compiler warning */
             }
+
             if (outLength >= USBFS_EVENT_LENGTH)
             {
                 outPointer = 0u;
@@ -252,7 +262,7 @@ void USBFS_MIDI_EP_Init(void)
                         {
                             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                                 USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);
-                            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+                            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
                         }
                         else
                         {
@@ -260,7 +270,7 @@ void USBFS_MIDI_EP_Init(void)
 
                             /* `#END` */
                         }
-                    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+                    #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
                     /* Process any local MIDI output functions */
                     USBFS_callbackLocalMidiEvent(
@@ -272,7 +282,7 @@ void USBFS_MIDI_EP_Init(void)
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /* Enable Out EP*/
                 USBFS_EnableOutEP(USBFS_midi_out_ep);
-            #endif  /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif  /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
         }
     }
 
@@ -322,12 +332,12 @@ void USBFS_MIDI_EP_Init(void)
             #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
                 /* rearm IN EP */
                 USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);
-            #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/
+            #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
 
             /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */
             #if(USBFS_EP_MM == USBFS__EP_MANUAL)
                 USBFS_midiInPointer = 0u;
-            #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
+            #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */
             }
         }
     }
@@ -370,7 +380,8 @@ void USBFS_MIDI_EP_Init(void)
             uint8 m2 = 0u;
             do
             {
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI1 input port for a complete event */
                     m1 = USBFS_MIDI1_GetEvent();
@@ -382,7 +393,8 @@ void USBFS_MIDI_EP_Init(void)
                 }
 
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
-                if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+                if (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
                 {
                     /* Check MIDI2 input port for a complete event */
                     m2 = USBFS_MIDI2_GetEvent();
@@ -392,11 +404,12 @@ void USBFS_MIDI_EP_Init(void)
                                                     USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);
                     }
                 }
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+            #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 
-            }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
-                   && ((m1 != 0u) || (m2 != 0u)) );
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            }while( (USBFS_midiInPointer <=
+                    (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&
+                    ((m1 != 0u) || (m2 != 0u)) );
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         /* Service the USB MIDI input endpoint */
         USBFS_MIDI_IN_EP_Service();
@@ -453,8 +466,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_DisableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_DisableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         if (USBFS_midiInPointer >
                     (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
@@ -481,15 +494,16 @@ void USBFS_MIDI_EP_Init(void)
                         (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                     {
                         USBFS_MIDI_IN_EP_Service();
-                        if (USBFS_midiInPointer >
-                            (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
+                        if(USBFS_midiInPointer >
+                          (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
                         {
                             /* Error condition. HOST is not ready to receive this packet. */
                             retError = USBFS_TRUE;
                             break;
                         }
                     }
-                }while(ic > USBFS_EVENT_BYTE3);
+                }
+                while(ic > USBFS_EVENT_BYTE3);
 
                 if(retError == USBFS_FALSE)
                 {
@@ -507,8 +521,8 @@ void USBFS_MIDI_EP_Init(void)
             MIDI1_UART_EnableRxInt();
             #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
                 MIDI2_UART_EnableRxInt();
-            #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+            #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+        #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
         return (retError);
     }
@@ -712,7 +726,7 @@ void USBFS_MIDI_EP_Init(void)
             /* Change the priority of the UART TX interrupt */
             CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);
             CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);
-        #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
+        #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
 
         /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */
 
@@ -915,12 +929,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI1_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;
@@ -930,12 +945,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI1_UART_rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI1_UART_rxBufferWrite;
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary buffer pointer
@@ -948,7 +963,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /*  ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI1_UART_rxBuffer[rxBufferRead];
                     /* Increment pointer with a wrap */
@@ -965,11 +980,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI1_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                         MIDI1_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-                        #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+                        #endif /*  MIDI1_UART_RXBUFFERSIZE >= 256 */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -984,11 +999,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI1_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI1_UART_RX_VECT_NUM);
-            #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1105,6 +1120,7 @@ void USBFS_MIDI_EP_Init(void)
         /* `#END` */
     }
 
+
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
 
 
@@ -1137,12 +1153,13 @@ void USBFS_MIDI_EP_Init(void)
         uint8 rxData;
         #if (MIDI2_UART_RXBUFFERSIZE >= 256u)
             uint16 rxBufferRead;
-            #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */
+            #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */
                 uint16 rxBufferWrite;
-            #endif /* end CY_PSOC3 */
+            #endif /* (CY_PSOC3) */
         #else
             uint8 rxBufferRead;
-        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+        #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */
+
         uint8 rxBufferLoopDetect;
         /* Read buffer loop condition to the local variable */
         rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;
@@ -1152,12 +1169,12 @@ void USBFS_MIDI_EP_Init(void)
             /* Protect variables that could change on interrupt by disabling Rx interrupt.*/
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             rxBufferRead = MIDI2_UART_rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 rxBufferWrite = MIDI2_UART_rxBufferWrite;
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
 
             /* Stay here until either the buffer is empty or we have a complete message
             *  in the message buffer. Note that we must use a temporary output pointer to
@@ -1170,7 +1187,7 @@ void USBFS_MIDI_EP_Init(void)
                 while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
             #else
                 while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                 {
                     rxData = MIDI2_UART_rxBuffer[rxBufferRead];
                     rxBufferRead++;
@@ -1186,11 +1203,11 @@ void USBFS_MIDI_EP_Init(void)
                         MIDI2_UART_rxBufferLoopDetect = 0u;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                         MIDI2_UART_rxBufferRead = rxBufferRead;
                         #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                             CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-                        #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+                        #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
                     }
 
                     msgRtn = USBFS_ProcessMidiIn(rxData,
@@ -1205,11 +1222,11 @@ void USBFS_MIDI_EP_Init(void)
             */
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntDisable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
             MIDI2_UART_rxBufferRead = rxBufferRead;
             #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
                 CyIntEnable(MIDI2_UART_RX_VECT_NUM);
-            #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+            #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
         }
 
         return (msgRtn);
@@ -1325,17 +1342,17 @@ void USBFS_MIDI_EP_Init(void)
 
         /* `#END` */
     }
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
 
-#endif  /* End (USBFS_ENABLE_MIDI_API != 0u) */
+#endif  /*  (USBFS_ENABLE_MIDI_API != 0u) */
 
 
 /* `#START MIDI_FUNCTIONS` Place any additional functions here */
 
 /* `#END` */
 
-#endif  /* End defined(USBFS_ENABLE_MIDI_STREAMING) */
+#endif  /*  defined(USBFS_ENABLE_MIDI_STREAMING) */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h
index 473cc26d..c4c236d9 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h
@@ -1,13 +1,17 @@
 /*******************************************************************************
 * File Name: USBFS_midi.h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  Header File for the USBFS MIDI module.
 *  Contains prototypes and constant values.
 *
+* Related Document:
+*  Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+*  MIDI 1.0 Detailed Specification Document Version 4.2
+*
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,7 +25,7 @@
 
 
 /***************************************
-*    Data Struct Definition
+*    Data Structure Definition
 ***************************************/
 
 /* The following structure is used to hold status information for
@@ -112,12 +116,13 @@ typedef struct
 #define USBFS_CUSTOM_UART_TX_PRIOR_NUM   (0x04u)
 #define USBFS_CUSTOM_UART_RX_PRIOR_NUM   (0x02u)
 
-#define USBFS_ISR_SERVICE_MIDI_OUT     \
+#define USBFS_ISR_SERVICE_MIDI_OUT         \
         ( (USBFS_ENABLE_MIDI_API != 0u) && \
-          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )
+          (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))
 #define USBFS_ISR_SERVICE_MIDI_IN     \
         ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )
 
+
 /***************************************
 * External function references
 ***************************************/
@@ -132,13 +137,13 @@ void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)
 
 #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
     #include "MIDI1_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
     #include "MIDI2_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     #include <CyDmac.h>
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 
 
 /***************************************
@@ -159,8 +164,8 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         uint8 USBFS_MIDI2_GetEvent(void) ;
         void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])
                                                     ;
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 
 /***************************************
@@ -174,7 +179,7 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
         extern volatile uint16 USBFS_midiInPointer;                       /* Input endpoint buffer pointer */
     #else
         extern volatile uint8 USBFS_midiInPointer;                        /* Input endpoint buffer pointer */
-    #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+    #endif /*  USBFS_MIDI_IN_BUFF_SIZE >=256 */
     extern volatile uint8 USBFS_midi_in_ep;                               /* Input endpoint number */
     extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE];  /* Input endpoint buffer */
 #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
@@ -188,13 +193,13 @@ void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint
     extern volatile uint8 USBFS_MIDI1_InqFlags;                              /* Device inquiry flag */
     #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
         extern volatile uint8 USBFS_MIDI2_InqFlags;                          /* Device inquiry flag */
-    #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+    #endif /*  USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /*  USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
 
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
 
 
-#endif /* End CY_USBFS_USBFS_midi_H */
+#endif /*  CY_USBFS_USBFS_midi_H */
 
 
 /* [] END OF FILE */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c
index 003d7f17..f0e9a277 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_pm.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This file provides Suspend/Resume APIs functionality.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -36,7 +36,6 @@ static USBFS_BACKUP_STRUCT  USBFS_backup;
 
 #if(USBFS_DP_ISR_REMOVE == 0u)
 
-
     /*******************************************************************************
     * Function Name: USBFS_DP_Interrupt
     ********************************************************************************
@@ -119,7 +118,7 @@ void USBFS_RestoreConfig(void)
 ********************************************************************************
 *
 * Summary:
-*  This function disables the USBFS block and prepares for power donwn mode.
+*  This function disables the USBFS block and prepares for power down mode.
 *
 * Parameters:
 *  None.
@@ -145,7 +144,7 @@ void USBFS_Suspend(void)
 
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             USBFS_Stop_DMA(USBFS_MAX_EP);     /* Stop all DMAs */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
         USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;
@@ -158,7 +157,7 @@ void USBFS_Suspend(void)
         /* Disable the SIE */
         USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;
 
-        CyDelayUs(0u);  /*~50ns delay */
+        CyDelayUs(0u);  /* ~50ns delay */
         /* Store mode and Disable VRegulator*/
         USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;
         USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;
@@ -181,16 +180,16 @@ void USBFS_Suspend(void)
     {
         USBFS_backup.enableState = 0u;
     }
+
     CyExitCriticalSection(enableInterrupts);
 
     /* Set the DP Interrupt for wake-up from sleep mode. */
     #if(USBFS_DP_ISR_REMOVE == 0u)
-        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM,   &USBFS_DP_ISR);
+        (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
         CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);
         CyIntClearPending(USBFS_DP_INTC_VECT_NUM);
         CyIntEnable(USBFS_DP_INTC_VECT_NUM);
     #endif /* (USBFS_DP_ISR_REMOVE == 0u) */
-
 }
 
 
@@ -223,7 +222,7 @@ void USBFS_Resume(void)
     {
         #if(USBFS_DP_ISR_REMOVE == 0u)
             CyIntDisable(USBFS_DP_INTC_VECT_NUM);
-        #endif /* End USBFS_DP_ISR_REMOVE */
+        #endif /*  USBFS_DP_ISR_REMOVE */
 
         /* Enable USB block */
         USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
@@ -245,18 +244,18 @@ void USBFS_Resume(void)
         /* Set the USBIO pull-up enable */
         USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
 
-        /* Reinit Arbiter configuration for DMA transfers */
+        /* Re-init Arbiter configuration for DMA transfers */
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
-            /* usb arb interrupt enable */
+            /* Usb arb interrupt enable */
             USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
             #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAMANUAL */
             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                 /*Set cfg cmplt this rises DMA request when the full configuration is done */
                 USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-            #endif   /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+            #endif   /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         /* STALL_IN_OUT */
         CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
@@ -268,8 +267,8 @@ void USBFS_Resume(void)
 
         /* Restore USB register settings */
         USBFS_RestoreConfig();
-
     }
+
     CyExitCriticalSection(enableInterrupts);
 }
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
index c98757f8..a2f18c8d 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: .h
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  This private file provides constants and parameter values for the
@@ -10,7 +10,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -66,7 +66,14 @@ extern volatile T_USBFS_TD USBFS_currentTD;
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     extern uint8 USBFS_DmaChan[USBFS_MAX_EP];
     extern uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+    extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];
+    extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+    extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+    extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /*  ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
 
 extern volatile uint8 USBFS_ep0Toggle;
 extern volatile uint8 USBFS_lastPacketSize;
@@ -106,7 +113,7 @@ void USBFS_Config(uint8 clearAltSetting) ;
 void USBFS_ConfigAltChanged(void) ;
 void USBFS_ConfigReg(void) ;
 
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                             ;
 const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)
                                                             ;
@@ -119,56 +126,62 @@ uint8 USBFS_ValidateAlternateSetting(void) ;
 void USBFS_SaveConfig(void) ;
 void USBFS_RestoreConfig(void) ;
 
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
 #if defined(USBFS_ENABLE_IDSN_STRING)
     void USBFS_ReadDieID(uint8 descr[]) ;
 #endif /* USBFS_ENABLE_IDSN_STRING */
 
 #if defined(USBFS_ENABLE_HID_CLASS)
     uint8 USBFS_DispatchHIDClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_AUDIO_CLASS)
     uint8 USBFS_DispatchAUDIOClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /*  USBFS_ENABLE_HID_CLASS */
 #if defined(USBFS_ENABLE_CDC_CLASS)
     uint8 USBFS_DispatchCDCClassRqst(void);
-#endif /* End USBFS_ENABLE_CDC_CLASS */
+#endif /*  USBFS_ENABLE_CDC_CLASS */
 
 CY_ISR_PROTO(USBFS_EP_0_ISR);
 #if(USBFS_EP1_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_1_ISR);
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /*  USBFS_EP1_ISR_REMOVE */
 #if(USBFS_EP2_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_2_ISR);
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /*  USBFS_EP2_ISR_REMOVE */
 #if(USBFS_EP3_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_3_ISR);
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /*  USBFS_EP3_ISR_REMOVE */
 #if(USBFS_EP4_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_4_ISR);
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /*  USBFS_EP4_ISR_REMOVE */
 #if(USBFS_EP5_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_5_ISR);
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /*  USBFS_EP5_ISR_REMOVE */
 #if(USBFS_EP6_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_6_ISR);
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /*  USBFS_EP6_ISR_REMOVE */
 #if(USBFS_EP7_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_7_ISR);
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /*  USBFS_EP7_ISR_REMOVE */
 #if(USBFS_EP8_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_EP_8_ISR);
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /*  USBFS_EP8_ISR_REMOVE */
 CY_ISR_PROTO(USBFS_BUS_RESET_ISR);
 #if(USBFS_SOF_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_SOF_ISR);
-#endif /* End USBFS_SOF_ISR_REMOVE */
+#endif /*  USBFS_SOF_ISR_REMOVE */
 #if(USBFS_EP_MM != USBFS__EP_MANUAL)
     CY_ISR_PROTO(USBFS_ARB_ISR);
-#endif /* End USBFS_EP_MM */
+#endif /*  USBFS_EP_MM */
 #if(USBFS_DP_ISR_REMOVE == 0u)
     CY_ISR_PROTO(USBFS_DP_ISR);
-#endif /* End USBFS_DP_ISR_REMOVE */
-
+#endif /*  USBFS_DP_ISR_REMOVE */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+    CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
 
 /***************************************
 * Request Handlers
@@ -182,6 +195,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    HID Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_HID_CLASS)
     void USBFS_FindReport(void) ;
     void USBFS_FindReportDescriptor(void) ;
@@ -192,6 +206,7 @@ uint8 USBFS_HandleVendorRqst(void) ;
 /***************************************
 *    MIDI Internal references
 ***************************************/
+
 #if defined(USBFS_ENABLE_MIDI_STREAMING)
     void USBFS_MIDI_IN_EP_Service(void) ;
 #endif /* USBFS_ENABLE_MIDI_STREAMING */
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c
index af2f201a..0a177d20 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_std.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB Standard request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -17,9 +17,9 @@
 #include "USBFS.h"
 #include "USBFS_cdc.h"
 #include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) 
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
     #include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /*  USBFS_ENABLE_MIDI_STREAMING*/
 
 
 /***************************************
@@ -33,7 +33,6 @@
 
 #if defined(USBFS_ENABLE_FWSN_STRING)
 
-
     /*******************************************************************************
     * Function Name: USBFS_SerialNumString
     ********************************************************************************
@@ -57,10 +56,10 @@
         USBFS_snStringConfirm = USBFS_FALSE;
         if(snString != NULL)
         {
-            USBFS_fwSerialNumberStringDescriptor = snString;
             /* Check descriptor validation */
             if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )
             {
+                USBFS_fwSerialNumberStringDescriptor = snString;
                 USBFS_snStringConfirm = USBFS_TRUE;
             }
         }
@@ -90,6 +89,7 @@ uint8 USBFS_HandleStandardRqst(void)
 {
     uint8 requestHandled = USBFS_FALSE;
     uint8 interfaceNumber;
+    uint8 configurationN;
     #if defined(USBFS_ENABLE_STRINGS)
         volatile uint8 *pStr = 0u;
         #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)
@@ -117,11 +117,14 @@ uint8 USBFS_HandleStandardRqst(void)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)
                 {
                     pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));
-                    USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
-                    USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
-                                      USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
-                                     (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
-                    requestHandled  = USBFS_InitControlRead();
+                    if( pTmp != NULL )  /* Verify that requested descriptor exists */
+                    {
+                        USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
+                        USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
+                                          USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
+                                         (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
+                        requestHandled  = USBFS_InitControlRead();
+                    }
                 }
                 #if defined(USBFS_ENABLE_STRINGS)
                 else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)
@@ -138,34 +141,39 @@ uint8 USBFS_HandleStandardRqst(void)
                             pStr = &pStr[descrLength];
                             nStr++;
                         }
-                    #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */
+                    #endif /*  USBFS_ENABLE_DESCRIPTOR_STRINGS */
                     /* Microsoft OS String*/
                     #if defined(USBFS_ENABLE_MSOS_STRING)
                         if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )
                         {
                             pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];
                         }
-                    #endif /* End USBFS_ENABLE_MSOS_STRING*/
+                    #endif /*  USBFS_ENABLE_MSOS_STRING*/
                     /* SN string */
                     #if defined(USBFS_ENABLE_SN_STRING)
                         if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&
                             (CY_GET_REG8(USBFS_wValueLo) ==
                             USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )
                         {
-                            pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
-                            #if defined(USBFS_ENABLE_FWSN_STRING)
-                                if(USBFS_snStringConfirm != USBFS_FALSE)
-                                {
-                                    pStr = USBFS_fwSerialNumberStringDescriptor;
-                                }
-                            #endif  /* USBFS_ENABLE_FWSN_STRING */
+
                             #if defined(USBFS_ENABLE_IDSN_STRING)
                                 /* Read DIE ID and generate string descriptor in RAM */
                                 USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);
                                 pStr = USBFS_idSerialNumberStringDescriptor;
-                            #endif    /* End USBFS_ENABLE_IDSN_STRING */
+                            #elif defined(USBFS_ENABLE_FWSN_STRING)
+                                if(USBFS_snStringConfirm != USBFS_FALSE)
+                                {
+                                    pStr = USBFS_fwSerialNumberStringDescriptor;
+                                }
+                                else
+                                {
+                                    pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                                }
+                            #else
+                                pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+                            #endif  /* defined(USBFS_ENABLE_IDSN_STRING) */
                         }
-                    #endif    /* End USBFS_ENABLE_SN_STRING */
+                    #endif    /*  USBFS_ENABLE_SN_STRING */
                     if (*pStr != 0u)
                     {
                         USBFS_currentTD.count = *pStr;
@@ -173,7 +181,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         requestHandled  = USBFS_InitControlRead();
                     }
                 }
-                #endif /* End USBFS_ENABLE_STRINGS */
+                #endif /*  USBFS_ENABLE_STRINGS */
                 else
                 {
                     requestHandled = USBFS_DispatchClassRqst();
@@ -225,10 +233,23 @@ uint8 USBFS_HandleStandardRqst(void)
                 requestHandled = USBFS_InitNoDataControlTransfer();
                 break;
             case USBFS_SET_CONFIGURATION:
-                USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);
-                USBFS_configurationChanged = USBFS_TRUE;
-                USBFS_Config(USBFS_TRUE);
-                requestHandled = USBFS_InitNoDataControlTransfer();
+                configurationN = CY_GET_REG8(USBFS_wValueLo);
+                if(configurationN > 0u)
+                {   /* Verify that configuration descriptor exists */
+                    pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);
+                }
+                /* Responds with a Request Error when configuration number is invalid */
+                if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))
+                {
+                    /* Set new configuration if it has been changed */
+                    if(configurationN != USBFS_configuration)
+                    {
+                        USBFS_configuration = configurationN;
+                        USBFS_configurationChanged = USBFS_TRUE;
+                        USBFS_Config(USBFS_TRUE);
+                    }
+                    requestHandled = USBFS_InitNoDataControlTransfer();
+                }
                 break;
             case USBFS_SET_INTERFACE:
                 if (USBFS_ValidateAlternateSetting() != 0u)
@@ -241,7 +262,7 @@ uint8 USBFS_HandleStandardRqst(void)
                         USBFS_Config(USBFS_FALSE);
                     #else
                         USBFS_ConfigAltChanged();
-                    #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+                    #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
                     /* Update handled Alt setting changes status */
                     USBFS_interfaceSetting_last[interfaceNumber] =
                          USBFS_interfaceSetting[interfaceNumber];
@@ -342,7 +363,6 @@ uint8 USBFS_HandleStandardRqst(void)
         uint8 value;
         const char8 CYCODE hex[16u] = "0123456789ABCDEF";
 
-
         /* Check descriptor validation */
         if( descr != NULL)
         {
@@ -360,7 +380,7 @@ uint8 USBFS_HandleStandardRqst(void)
         }
     }
 
-#endif /* End USBFS_ENABLE_IDSN_STRING */
+#endif /*  USBFS_ENABLE_IDSN_STRING */
 
 
 /*******************************************************************************
@@ -384,20 +404,18 @@ void USBFS_ConfigReg(void)
     uint8 ep;
     uint8 i;
     #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-        uint8 ep_type = 0u;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+        uint8 epType = 0u;
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     /* Set the endpoint buffer addresses */
     ep = USBFS_EP1;
     for (i = 0u; i < 0x80u; i+= 0x10u)
     {
-        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |
-                                                          USBFS_ARB_EPX_CFG_RESET);
-
+        CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);
         #if(USBFS_EP_MM != USBFS__EP_MANUAL)
             /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */
             CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);
-        #endif   /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+        #endif   /*  USBFS_EP_MM != USBFS__EP_MANUAL */
 
         if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)
         {
@@ -410,8 +428,8 @@ void USBFS_ConfigReg(void)
                 CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);
                 /* Prepare EP type mask for automatic memory allocation */
                 #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
-                    ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));
-                #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                    epType |= (uint8)(0x01u << (ep - USBFS_EP1));
+                #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
         }
         else
@@ -427,7 +445,7 @@ void USBFS_ConfigReg(void)
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i),     USBFS_EP[ep].buffOffset & 0xFFu);
             CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         ep++;
     }
@@ -438,13 +456,13 @@ void USBFS_ConfigReg(void)
         USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST;   /* DMA burst threshold */
         USBFS_DMA_THRES_MSB_REG = 0u;
         USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;
-        USBFS_EP_TYPE_REG = ep_type;
+        USBFS_EP_TYPE_REG = epType;
         /* Cfg_cmp bit set to 1 once configuration is complete. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |
                                        USBFS_ARB_CFG_CFG_CPM;
         /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */
         USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
-    #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
 
     CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);
 }
@@ -477,11 +495,11 @@ void USBFS_Config(uint8 clearAltSetting)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     const uint8 *pDescr;
     #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
         uint16 buffCount = 0u;
-    #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+    #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
     const T_USBFS_LUT CYCODE *pTmp;
     const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;
@@ -534,56 +552,56 @@ void USBFS_Config(uint8 clearAltSetting)
             pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;
             for (i = 0u; i < ep; i++)
             {
-                /* Compare current Alternate setting with EP Alt*/
+                /* Compare current Alternate setting with EP Alt */
                 if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                 {
                     cur_ep = pEP->addr & USBFS_DIR_UNUSED;
-                    ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                    epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                     if (pEP->addr & USBFS_DIR_IN)
                     {
                         /* IN Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_in_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     else
                     {
                         /* OUT Endpoint */
                         USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                        USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                        USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                         #if defined(USBFS_ENABLE_CDC_CLASS)
                             if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                 (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                (ep_type != USBFS_EP_TYPE_INT))
+                                (epType != USBFS_EP_TYPE_INT))
                             {
                                 USBFS_cdc_data_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                        #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                         #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                      (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                             if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                               (ep_type == USBFS_EP_TYPE_BULK))
+                               (epType == USBFS_EP_TYPE_BULK))
                             {
                                 USBFS_midi_out_ep = cur_ep;
                             }
-                        #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                        #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                     }
                     USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;
                     USBFS_EP[cur_ep].addr = pEP->addr;
@@ -591,7 +609,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 }
                 pEP = &pEP[1u];
             }
-        #else /* Config for static EP memory allocation  */
+        #else /* Configure for static EP memory allocation  */
             for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)
             {
                 /* p_list points the endpoint setting table. */
@@ -610,67 +628,67 @@ void USBFS_Config(uint8 clearAltSetting)
                         /* Compare current Alternate setting with EP Alt*/
                         if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
                         {
-                            ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                            epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                             if ((pEP->addr & USBFS_DIR_IN) != 0u)
                             {
                                 /* IN Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                         USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_IN_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_in_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             else
                             {
                                 /* OUT Endpoint */
                                 USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;
-                                USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                                USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                     USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
-                                /* Find and init CDC IN endpoint number */
+                                /* Find and initialize CDC IN endpoint number */
                                 #if defined(USBFS_ENABLE_CDC_CLASS)
                                     if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
                                         (pEP->bMisc == USBFS_CLASS_CDC)) &&
-                                        (ep_type != USBFS_EP_TYPE_INT))
+                                        (epType != USBFS_EP_TYPE_INT))
                                     {
                                         USBFS_cdc_data_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_CDC_CLASS*/
+                                #endif  /*  USBFS_ENABLE_CDC_CLASS*/
                                 #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
                                              (USBFS_MIDI_OUT_BUFF_SIZE > 0) )
                                     if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
-                                       (ep_type == USBFS_EP_TYPE_BULK))
+                                       (epType == USBFS_EP_TYPE_BULK))
                                     {
                                         USBFS_midi_out_ep = i;
                                     }
-                                #endif  /* End USBFS_ENABLE_MIDI_STREAMING*/
+                                #endif  /*  USBFS_ENABLE_MIDI_STREAMING*/
                             }
                             USBFS_EP[i].addr = pEP->addr;
                             USBFS_EP[i].attrib = pEP->attributes;
 
                             #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
                                 break;      /* use first EP setting in Auto memory managment */
-                            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+                            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
                         }
                     }
                     pEP = &pEP[1u];
                 }
             }
-        #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+        #endif /*  (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
 
         /* Init class array for each interface and interface number for each EP.
         *  It is used for handling Class specific requests directed to either an
@@ -694,7 +712,7 @@ void USBFS_Config(uint8 clearAltSetting)
                 USBFS_EP[ep].buffOffset = buffCount;
                  buffCount += USBFS_EP[ep].bufferSize;
             }
-        #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+        #endif /*  USBFS_EP_MM != USBFS__EP_DMAAUTO */
 
         /* Configure hardware registers */
         USBFS_ConfigReg();
@@ -725,7 +743,7 @@ void USBFS_ConfigAltChanged(void)
     uint8 ep;
     uint8 cur_ep;
     uint8 i;
-    uint8 ep_type;
+    uint8 epType;
     uint8 ri;
 
     const T_USBFS_LUT CYCODE *pTmp;
@@ -753,19 +771,19 @@ void USBFS_ConfigAltChanged(void)
             {
                 cur_ep = pEP->addr & USBFS_DIR_UNUSED;
                 ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
-                ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+                epType = pEP->attributes & USBFS_EP_TYPE_MASK;
                 if ((pEP->addr & USBFS_DIR_IN) != 0u)
                 {
                     /* IN Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
                 }
                 else
                 {
                     /* OUT Endpoint */
                     USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
-                    USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+                    USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
                                                 USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
                 }
                  /* Change the SIE mode for the selected EP to NAK ALL */
@@ -823,7 +841,7 @@ void USBFS_ConfigAltChanged(void)
                                                                 USBFS_EP[cur_ep].buffOffset & 0xFFu);
                 CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),
                                                                 USBFS_EP[cur_ep].buffOffset >> 8u);
-            #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+            #endif /*  USBFS_EP_MM == USBFS__EP_DMAAUTO */
             }
             /* Get next EP element */
             pEP = &pEP[1u];
@@ -840,13 +858,13 @@ void USBFS_ConfigAltChanged(void)
 *  This routine returns a pointer a configuration table entry
 *
 * Parameters:
-*  c:  Configuration Index
+*  confIndex:  Configuration Index
 *
 * Return:
-*  Device Descriptor pointer.
+*  Device Descriptor pointer or NULL when descriptor isn't exists.
 *
 *******************************************************************************/
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
                                                         
 {
     /* Device Table */
@@ -856,8 +874,20 @@ const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
 
     /* The first entry points to the Device Descriptor,
     *  the rest configuration entries.
-	*/
-    return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );
+    *  Set pointer to the first Configuration Descriptor
+    */
+    pTmp = &pTmp[1u];
+    /* For this table, c is the number of configuration descriptors  */
+    if(confIndex >= pTmp->c)   /* Verify that required configuration descriptor exists */
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) NULL;
+    }
+    else
+    {
+        pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;
+    }
+
+    return( pTmp );
 }
 
 
@@ -902,14 +932,24 @@ const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void)
                                                         
 {
     const T_USBFS_LUT CYCODE *pTmp;
+    const uint8 CYCODE *pInterfaceClass;
     uint8 currentInterfacesNum;
 
     pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
-    currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
-    /* Third entry in the LUT starts the Interface Table pointers */
-    /* The INTERFACE_CLASS table is located after all interfaces */
-    pTmp = &pTmp[currentInterfacesNum + 2u];
-    return( (const uint8 CYCODE *) pTmp->p_list );
+    if( pTmp != NULL )
+    {
+        currentInterfacesNum  = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
+        /* Third entry in the LUT starts the Interface Table pointers */
+        /* The INTERFACE_CLASS table is located after all interfaces */
+        pTmp = &pTmp[currentInterfacesNum + 2u];
+        pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;
+    }
+    else
+    {
+        pInterfaceClass = (const uint8 CYCODE *) NULL;
+    }
+
+    return( pInterfaceClass );
 }
 
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
index 6543a676..2565e8fb 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: USBFS_vnd.c
-* Version 2.60
+* Version 2.80
 *
 * Description:
 *  USB vendor request handler.
@@ -8,7 +8,7 @@
 * Note:
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -34,7 +34,7 @@
 ********************************************************************************
 *
 * Summary:
-*  This routine provide users with a method to implement vendor specifc
+*  This routine provide users with a method to implement vendor specific
 *  requests.
 *
 *  To implement vendor specific requests, add your code in this function to
@@ -66,7 +66,7 @@ uint8 USBFS_HandleVendorRqst(void)
                     USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];
                     requestHandled  = USBFS_InitControlRead();
-                #endif /* End USBFS_ENABLE_MSOS_STRING */
+                #endif /*  USBFS_ENABLE_MSOS_STRING */
                 break;
             default:
                 break;
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld
index 66ec5a45..6972232b 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld
@@ -45,10 +45,10 @@ CY_METADATA_SIZE    = 64;
  */
 EXTERN(Reset)
 
-/* Bring in the interrupt routines & vector */
+/* Bring in interrupt routines & vector */
 EXTERN(main)
 
-/* Bring in the meta data */
+/* Bring in meta data */
 EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
 EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
 
@@ -90,7 +90,7 @@ SECTIONS
     /* Make sure we pulled in some reset code.  */
     ASSERT (. != __cy_reset, "No reset code");
 
-	/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
+	/* Place DMA initialization before text to ensure it gets placed in first 64K of flash */
     *(.dma_init)
     ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
 		
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
index cb5d1655..011f0576 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: core_cm3_psoc5.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *   Provides important type information for the PSoC5.  This includes types
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c
index 9906255c..4780df06 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.c
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides an API for the power management.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -20,8 +20,8 @@
 
 
 /*******************************************************************
-* Place your includes, defines and code here. Do not use merge
-* region below unless any component datasheet suggest to do so.
+* Place your includes, defines, and code here. Do not use the merge
+* region below unless any component datasheet suggests doing so.
 *******************************************************************/
 /* `#START CY_PM_HEADER_INCLUDE` */
 
@@ -51,8 +51,8 @@ static void CyPmHviLviRestore(void) ;
 *
 * Summary:
 *  This function is called in preparation for entering sleep or hibernate low
-*  power modes. Saves all state of the clocking system that does not persist
-*  during sleep/hibernate or that needs to be altered in preparation for
+*  power modes. Saves all the states of the clocking system that do not persist
+*  during sleep/hibernate or that need to be altered in preparation for
 *  sleep/hibernate. Shutdowns all the digital and analog clock dividers for the
 *  active power mode configuration.
 *
@@ -105,6 +105,45 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imo2x = CY_PM_DISABLED;
     }
 
+    /* Master clock - save source */
+    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+
+    /* Switch Master clock's source from PLL's output to PLL's source */
+    if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)
+    {
+        switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)
+        {
+        case CY_PM_CLKDIST_PLL_SRC_IMO:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_XTAL:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);
+            break;
+
+        case CY_PM_CLKDIST_PLL_SRC_DSI:
+            CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);
+            break;
+
+        default:
+            CYASSERT(0u != 0u);
+            break;
+        }
+    }
+
+    /* PLL - check enable state, disable if needed */
+    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
+    {
+        /* PLL is enabled - save state and disable */
+        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
+        CyPLL_OUT_Stop();
+    }
+    else
+    {
+        /* PLL is disabled - save state */
+        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
+    }
+
     /* IMO - set appropriate frequency for LPM */
     CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);
 
@@ -119,8 +158,11 @@ void CyPmSaveClocks(void)
         /* IMO - save disabled state */
         cyPmClockBackup.imoEnable = CY_PM_DISABLED;
 
-        /* IMO - enable */
+        /* Enable the IMO. Use software delay instead of the FTW-based inside */
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
+
+        /* Settling time of the IMO is of the order of less than 6us */
+        CyDelayUs(6u);
     }
 
     /* IMO - save the current IMOCLK source and set to IMO if not yet */
@@ -130,7 +172,7 @@ void CyPmSaveClocks(void)
         cyPmClockBackup.imoClkSrc =
             (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;
 
-        /* IMO -  set IMOCLK source to MHz OSC */
+        /* IMO -  set IMOCLK source to IMO */
         CyIMO_SetSource(CY_IMO_SOURCE_IMO);
     }
     else
@@ -161,16 +203,13 @@ void CyPmSaveClocks(void)
     if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)
     {
         CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);
-    }    /* Need to change nothing if master clock divider is 1 */
-
-    /* Master clock - save current source */
-    cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+    }    /* No change if master clock divider is 1 */
 
     /* Master clock source - set it to IMO if not yet. */
     if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)
     {
         CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
-    }    /* Need to change nothing if master clock source is IMO */
+    }    /* No change if master clock source is IMO */
 
     /* Bus clock - save divider and set it, if needed, to divide-by-one */
     cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
@@ -180,22 +219,9 @@ void CyPmSaveClocks(void)
         CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);
     }    /* Do nothing if saved and actual values are equal */
 
-    /* Set number of wait cycles for the flash according CPU frequency in MHz */
+    /* Set number of wait cycles for flash according to CPU frequency in MHz */
     CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);
 
-    /* PLL - check enable state, disable if needed */
-    if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
-    {
-        /* PLL is enabled - save state and disable */
-        cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
-        CyPLL_OUT_Stop();
-    }
-    else
-    {
-        /* PLL is disabled - save state */
-        cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
-    }
-
     /* MHz ECO - check enable state and disable if needed */
     if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))
     {
@@ -211,8 +237,8 @@ void CyPmSaveClocks(void)
 
 
     /***************************************************************************
-    * Save enable state of delay between the system bus clock and each of the
-    * 4 individual analog clocks. This bit non-retention and it's value should
+    * Save the enable state of delay between the system bus clock and each of the
+    * 4 individual analog clocks. This bit non-retention and its value should
     * be restored on wakeup.
     ***************************************************************************/
     if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))
@@ -240,11 +266,11 @@ void CyPmSaveClocks(void)
 *
 *  PSoC 3 and PSoC 5LP:
 *  The merge region could be used to process state when the megahertz crystal is
-*  not ready after the hold-off timeout.
+*  not ready after a hold-off timeout.
 *
 *  PSoC 5:
-*  The 130 ms is given for the megahertz crystal to stabilize. It's readiness is
-*  not verified after the hold-off timeout.
+*  The 130 ms is given for the megahertz crystal to stabilize. Its readiness is
+*  not verified after a hold-off timeout.
 *
 * Parameters:
 *  None
@@ -265,10 +291,10 @@ void CyPmRestoreClocks(void)
         CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ,  CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,
         CY_IMO_FREQ_48MHZ, 5u, 6u};
 
-    /* Restore enable state of delay between the system bus clock and ACLKs. */
+    /* Restore enable state of delay between system bus clock and ACLKs. */
     if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)
     {
-        /* Delay for both the bandgap and the delay line to settle out */
+        /* Delay for both bandgap and delay line to settle out */
         CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *
                         CY_PM_GET_CPU_FREQ_MHZ);
 
@@ -279,7 +305,7 @@ void CyPmRestoreClocks(void)
     if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)
     {
         /***********************************************************************
-        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait
+        * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait
         * period uses FTW for period measurement. This could cause a problem
         * if CTW/FTW is used as a wake up time in the low power modes APIs.
         * So, the XTAL wait procedure is implemented with a software delay.
@@ -309,7 +335,7 @@ void CyPmRestoreClocks(void)
         {
             /*******************************************************************
             * Process the situation when megahertz crystal is not ready.
-            * Time to stabialize value is crystal specific.
+            * Time to stabilize the value is crystal specific.
             *******************************************************************/
            /* `#START_MHZ_ECO_TIMEOUT` */
 
@@ -318,10 +344,10 @@ void CyPmRestoreClocks(void)
     }   /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */
 
 
-    /* Temprorary set the maximum flash wait cycles */
+    /* Temprorary set maximum flash wait cycles */
     CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);
 
-    /* The XTAL and DSI clocks are ready to be source for Master clock. */
+    /* XTAL and DSI clocks are ready to be source for Master clock. */
     if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||
        (CY_PM_MASTER_CLK_SRC_DSI  == cyPmClockBackup.masterClkSrc))
     {
@@ -366,13 +392,6 @@ void CyPmRestoreClocks(void)
         CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
     }
 
-    /* IMO - restore disable state if needed */
-    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
-       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
-    {
-        CyIMO_Stop();
-    }
-
     /* IMO - restore IMOCLK source */
     CyIMO_SetSource(cyPmClockBackup.imoClkSrc);
 
@@ -389,6 +408,7 @@ void CyPmRestoreClocks(void)
                                 cyPmClockBackup.clkImoSrc;
     }
 
+
     /* PLL restore state */
     if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)
     {
@@ -398,12 +418,38 @@ void CyPmRestoreClocks(void)
         * as a wakeup time in the low power modes APIs. To omit this issue PLL
         * wait procedure is implemented with a software delay.
         ***********************************************************************/
+        status = CYRET_TIMEOUT;
 
         /* Enable PLL */
         (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);
 
-        /* Make a 250 us delay */
-        CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);
+        /* Read to clear lock status after delay */
+        CyDelayUs((uint32)80u);
+        (void) CY_PM_FASTCLK_PLL_SR_REG;
+
+        /* It should take 250 us lock: 251-80 = 171 */
+        for(i = 171u; i > 0u; i--)
+        {
+            CyDelayUs((uint32)1u);
+
+            /* Accept PLL is OK after two consecutive polls indicate PLL lock */
+            if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&
+               (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))
+            {
+                status = CYRET_SUCCESS;
+                break;
+            }
+        }
+
+        if(CYRET_TIMEOUT == status)
+        {
+            /*******************************************************************
+            * Process the situation when PLL is not ready.
+            *******************************************************************/
+           /* `#START_PLL_TIMEOUT` */
+
+           /* `#END` */
+        }
     }   /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */
 
 
@@ -421,6 +467,13 @@ void CyPmRestoreClocks(void)
         CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);
     }
 
+    /* IMO - disable if it was originally disabled */
+    if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
+       (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
+    {
+        CyIMO_Stop();
+    }
+
     /* Bus clock - restore divider, if needed */
     clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
     clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;
@@ -490,7 +543,7 @@ void CyPmRestoreClocks(void)
 *  Sleep Timer component and one second interval should be configured with the
 *  RTC component.
 *
-*  The wakeup behavior depends on wakeupSource parameter in the following
+*  The wakeup behavior depends on the wakeupSource parameter in the following
 *  manner: upon function execution the device will be switched from Active to
 *  Alternate Active mode and then the CPU will be halted. When an enabled wakeup
 *  event occurs the device will return to Active mode.  Similarly when an
@@ -534,7 +587,7 @@ void CyPmRestoreClocks(void)
             For PSoC 3 silicon the valid range of  values is 1 to 256.
 *
 *  wakeUpSource:    Specifies a bitwise mask of wakeup sources. In addition, if
-*                   a wakeupTime has been specified the associated timer will be
+*                   a wakeupTime has been specified, the associated timer will be
 *                   included as a wakeup source.
 *
 *           Define                      Source
@@ -556,13 +609,13 @@ void CyPmRestoreClocks(void)
 *  *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.
 *  **Note: CTW and One PPS wakeup signals are in the same mask bit.
 *
-*  When specifying a Comparator as the wakeupSource an instance specific define
-*  should be used that will track with the specific comparator that the instance
-*  is placed into. As an example, for a Comparator instance named MyComp the
+*  When specifying a Comparator as the wakeupSource, an instance specific define
+*  that will track with the specific comparator that the instance
+*  is placed into should be used. As an example, for a Comparator instance named MyComp the
 *  value to OR into the mask is: MyComp_ctComp__CMP_MASK.
 *
 *  When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()
-*  function must be called upon wakeup with corresponding parameter. Please
+*  function must be called upon wakeup with a corresponding parameter. Please
 *  refer to the CyPmReadStatus() API in the System Reference Guide for more
 *  information.
 *
@@ -576,7 +629,7 @@ void CyPmRestoreClocks(void)
 *  If a wakeupTime other than NONE is specified, then upon exit the state of the
 *  specified timer will be left as specified by wakeupTime with the timer
 *  enabled and the interrupt disabled.  Also, the ILO 1 KHz (if CTW timer is
-*  used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)
+*  used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)
 *  will be left started.
 *
 *******************************************************************************/
@@ -602,7 +655,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
         {
             CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_FTW;
         }
 
@@ -612,7 +665,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current CTW configuration and set new one */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_CTW;
         }
 
@@ -622,7 +675,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
             /* Save current 1PPS configuration and set new one */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;
         }
 
@@ -674,7 +727,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  Puts the part into the Sleep state.
 *
 *  Note Before calling this function, you must manually configure the power
-*  mode of the source clocks for the timer that is used as wakeup timer.
+*  mode of the source clocks for the timer that is used as the wakeup timer.
 *
 *  Note Before calling this function, you must prepare clock tree configuration
 *  for the low power mode by calling CyPmSaveClocks(). And restore clock
@@ -685,7 +738,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  PSoC 3:
 *  Before switching to Sleep, if a wakeupTime other than NONE is specified,
 *  then the appropriate timer state is configured as specified with the
-*  interrupt for that timer disabled.  The wakeup source will be the combination
+*  interrupt for that timer disabled.  The wakeup source will be a combination
 *  of the values specified in the wakeupSource and any timer specified in the
 *  wakeupTime argument.  Once the wakeup condition is satisfied, then all saved
 *  state is restored and the function returns in the Active state.
@@ -706,7 +759,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  The wakeupTime parameter is not used and the only NONE can be specified.
 *  The wakeup time must be configured with the component, SleepTimer for CTW
 *  intervals and RTC for 1PPS interval. The component must be configured to
-*  generate an interrrupt.
+*  generate interrupt.
 *
 * Parameters:
 *  wakeupTime:      Specifies a timer wakeup source and the frequency of that
@@ -780,7 +833,7 @@ void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource)
 *  detect (power supply supervising capabilities) are required in a design
 *  during sleep, use the Central Time Wheel (CTW) to periodically wake the
 *  device, perform software buzz, and refresh the supervisory services. If LVI,
-*  HVI, or Brown Out is not required, then use of the CTW is not required.
+*  HVI, or Brown Out is not required, then CTW is not required.
 *  Refer to the device errata for more information.
 *
 *******************************************************************************/
@@ -816,13 +869,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
     /***********************************************************************
     * PSoC3 < TO6:
-    * - Hardware buzz must be disabled before sleep mode entry.
+    * - Hardware buzz must be disabled before the sleep mode entry.
     * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must
-    *   be aslo disabled.
+    *   be also disabled.
     *
     * PSoC3 >= TO6:
-    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be
-    *   enabled before sleep mode entry and restored on wakeup.
+    * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware
+    *   buzz must be enabled before the sleep mode entry and restored on
+    *   the wakeup.
     ***********************************************************************/
     #if(CY_PSOC3)
 
@@ -860,9 +914,9 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************************
-    * For ARM-based devices, an interrupt is required for the CPU to wake up. The
+    * For ARM-based devices,interrupt is required for the CPU to wake up. The
     * Power Management implementation assumes that wakeup time is configured with a
-    * separate component (component-based wakeup time configuration) for an
+    * separate component (component-based wakeup time configuration) for
     * interrupt to be issued on terminal count. For more information, refer to the
     * Wakeup Time Configuration section of System Reference Guide.
     *******************************************************************************/
@@ -887,10 +941,10 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         /* CTW - save current and set new configuration */
         if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))
         {
-            /* Save current and set new configuration of the CTW */
+            /* Save current and set new configuration of CTW */
             CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_CTW;
         }
 
@@ -900,7 +954,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
             /* Save current and set new configuration of the 1PPS */
             CyPmOppsSet();
 
-            /* Include associated timer to the wakeupSource */
+            /* Include associated timer to wakeupSource */
             wakeupSource |= PM_SLEEP_SRC_ONE_PPS;
         }
 
@@ -923,8 +977,8 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 
 
     /*******************************************************************
-    * Do not use merge region below unless any component datasheet
-    * suggest to do so.
+    * Do not use the merge region below unless any component datasheet
+    * suggests doing so.
     *******************************************************************/
     /* `#START CY_PM_JUST_BEFORE_SLEEP` */
 
@@ -949,13 +1003,13 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
         CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));
     }
 
-    /* Switch to the Sleep mode */
+    /* Switch to Sleep mode */
     CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);
 
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1023,7 +1077,7 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  PSoC 3 and PSoC 5LP:
 *  Before switching to Hibernate, the current status of the PICU wakeup source
 *  bit is saved and then set. This configures the device to wake up from the
-*  PICU. Make sure you have at least one pin configured to generate a PICU
+*  PICU. Make sure you have at least one pin configured to generate PICU
 *  interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls
 *  the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."
 *  In the Pins component datasheet, this register is referred to as the IRQ
@@ -1046,14 +1100,14 @@ void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource)
 *  requirement begins when the device wakes up. There is no hardware check that
 *  this requirement is met. The specified delay should be done on ISR entry.
 *
-*  After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
+*  After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
 *  instance name of the Pins component) function must be called to clear the
-*  latched pin events to allow proper Hibernate mode entry andd to enable
+*  latched pin events to allow the proper Hibernate mode entry and to enable
 *  detection of future events.
 *
 *  The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to
 *  measure Hibernate/Sleep regulator settling time after a reset. The holdoff
-*  delay is measured using rising edges of the 1 kHz ILO.
+*  delay is measured using the rising edges of the 1 kHz ILO.
 *
 *******************************************************************************/
 void CyPmHibernate(void) 
@@ -1065,8 +1119,8 @@ void CyPmHibernate(void)
 
         /***********************************************************************
         * The Hibernate/Sleep regulator has a settling time after a reset.
-        * During this time, the system ignores requests to enter Sleep and
-        * Hibernate modes. The holdoff delay is measured using rising edges of
+        * During this time, the system ignores requests to enter the Sleep and
+        * Hibernate modes. The holdoff delay is measured using the rising edges of
         * the 1 kHz ILO.
         ***********************************************************************/
         if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))
@@ -1123,7 +1177,7 @@ void CyPmHibernate(void)
     /* Recommended readback. */
     (void) CY_PM_MODE_CSR_REG;
 
-    /* Two recommended NOPs to get into the mode. */
+    /* Two recommended NOPs to get into mode. */
     CY_NOP;
     CY_NOP;
 
@@ -1193,7 +1247,7 @@ uint8 CyPmReadStatus(uint8 mask)
     /* Enter critical section */
     interruptState = CyEnterCriticalSection();
 
-    /* Save value of the register, copy it and clear desired bit */
+    /* Save value of register, copy it and clear desired bit */
     interruptStatus |= CY_PM_INT_SR_REG;
     tmpStatus = interruptStatus;
     interruptStatus &= ((uint8)(~mask));
@@ -1234,11 +1288,11 @@ static void CyPmHibSaveSet(void)
     if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))
     {
         /***********************************************************************
-        * If I2C backup regulator is enabled, all the fixed-function registers
-        * store their values while device is in low power mode, otherwise their
+        * If the I2C backup regulator is enabled, all the fixed-function registers
+        * store their values while the device is in the low power mode, otherwise their
         * configuration is lost. The I2C API makes a decision to restore or not
         * to restore I2C registers based on this. If this regulator will be
-        * disabled and then enabled, I2C API will suppose that I2C block
+        * disabled and then enabled, I2C API will suppose that the I2C block
         * registers preserved their values, while this is not true. So, the
         * backup regulator is disabled. The I2C sleep APIs is responsible for
         * restoration.
@@ -1289,7 +1343,7 @@ static void CyPmHibSaveSet(void)
 
 
     /***************************************************************************
-    * Save and set power mode wakeup trim registers
+    * Save and set the power mode wakeup trim registers
     ***************************************************************************/
     cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;
     cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;
@@ -1304,12 +1358,12 @@ static void CyPmHibSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Restore device for proper Hibernate mode exit:
-*  - Restore LVI/HVI configuration - call CyPmHviLviRestore()
+*  Restores the device for the proper Hibernate mode exit:
+*  - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()
 *  - CyPmHibSlpSaveRestore() function is called
-*  - Restores ILO power down mode state and enable it
-*  - Restores state of 1 kHz and 100 kHz ILO and disable them
-*  - Restores sleep regulator settings
+*  - Restores ILO power down mode state and enables it
+*  - Restores the state of 1 kHz and 100 kHz ILO and disables them
+*  - Restores the sleep regulator settings
 *
 * Parameters:
 *  None
@@ -1352,7 +1406,7 @@ static void CyPmHibRestore(void)
 
 
     /***************************************************************************
-    * Restore power mode wakeup trim registers
+    * Restore the power mode wakeup trim registers
     ***************************************************************************/
     CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;
     CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;
@@ -1364,10 +1418,10 @@ static void CyPmHibRestore(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs CTW configuration:
-*  - Disables CTW interrupt
+*  Performs the CTW configuration:
+*  - Disables the CTW interrupt
 *  - Enables 1 kHz ILO
-*  - Sets new CTW interval
+*  - Sets a new CTW interval
 *
 * Parameters:
 *  ctwInterval: the CTW interval to be set.
@@ -1404,11 +1458,11 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
         /* Set CTW interval if needed */
         if(CY_PM_TW_CFG1_REG != ctwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG1_REG = ctwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the CTW */
+        /* Enable CTW */
         CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;
     }
 }
@@ -1421,7 +1475,7 @@ void CyPmCtwSetInterval(uint8 ctwInterval)
 * Summary:
 *  Performs 1PPS configuration:
 *  - Starts 32 KHz XTAL
-*  - Disables 1PPS interupts
+*  - Disables 1PPS interrupts
 *  - Enables 1PPS
 *
 * Parameters:
@@ -1453,10 +1507,10 @@ void CyPmOppsSet(void)
 ********************************************************************************
 *
 * Summary:
-*  Performs FTW configuration:
-*  - Disables FTW interrupt
+*  Performs the FTW configuration:
+*  - Disables the FTW interrupt
 *  - Enables 100 kHz ILO
-*  - Sets new FTW interval.
+*  - Sets a new FTW interval.
 *
 * Parameters:
 *  ftwInterval - FTW counter interval.
@@ -1465,7 +1519,7 @@ void CyPmOppsSet(void)
 *  None
 *
 * Side Effects:
-*  Enables ILO 100 KHz clock and leaves it enabled.
+*  Enables the ILO 100 KHz clock and leaves it enabled.
 *
 *******************************************************************************/
 void CyPmFtwSetInterval(uint8 ftwInterval) 
@@ -1476,13 +1530,13 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
     /* Enable 100kHz ILO */
     CyILO_Start100K();
 
-    /* Iterval could be set only while FTW is disabled */
+    /* Interval could be set only while FTW is disabled */
     if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))
     {
         /* Disable FTW, set new FTW interval if needed and enable it again */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Disable the CTW, set new CTW interval and enable it again */
+            /* Disable CTW, set new CTW interval and enable it again */
             CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));
             CY_PM_TW_CFG0_REG = ftwInterval;
             CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
@@ -1493,11 +1547,11 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
         /* Set new FTW counter interval if needed. FTW is disabled. */
         if(CY_PM_TW_CFG0_REG != ftwInterval)
         {
-            /* Set the new CTW interval. Could be changed if CTW is disabled */
+            /* Set new CTW interval. Could be changed if CTW is disabled */
             CY_PM_TW_CFG0_REG = ftwInterval;
         }   /* Required interval is already set */
 
-        /* Enable the FTW */
+        /* Enable FTW */
         CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
     }
 }
@@ -1508,12 +1562,12 @@ void CyPmFtwSetInterval(uint8 ftwInterval)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for preparing device for Sleep and Hibernate low power
+*  This API is used for preparing the device for the Sleep and Hibernate low power
 *  modes entry:
-*  - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)
-*  - Saves SC/CT routing connections (PSoC 3/5/5LP)
-*  - Disables Serial Wire Viewer (SWV) (PSoC 3)
-*  - Save boost reference selection and set it to internal
+*  - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)
+*  - Saves the SC/CT routing connections (PSoC 3/5/5LP)
+*  - Disables the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Saves the boost reference selection and sets it to internal
 *
 * Parameters:
 *  None
@@ -1643,11 +1697,11 @@ static void CyPmHibSlpSaveSet(void)
 ********************************************************************************
 *
 * Summary:
-*  This API is used for restoring device configurations after wakeup from Sleep
+*  This API is used for restoring the device configurations after wakeup from the Sleep
 *  and Hibernate low power modes:
-*  - Restores SC/CT routing connections
-*  - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)
-*  - Restore boost reference selection
+*  - Restores the SC/CT routing connections
+*  - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)
+*  - Restores the  boost reference selection
 *
 * Parameters:
 *  None
@@ -1740,7 +1794,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lvidEn = CY_PM_ENABLED;
         cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;
 
-        /* Save state of reset device at a specified Vddd threshold */
+        /* Save state of reset device at specified Vddd threshold */
         cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1756,7 +1810,7 @@ static void CyPmHviLviSaveDisable(void)
         cyPmBackup.lviaEn = CY_PM_ENABLED;
         cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;
 
-        /* Save state of reset device at a specified Vdda threshold */
+        /* Save state of reset device at specified Vdda threshold */
         cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \
                              CY_PM_DISABLED : CY_PM_ENABLED;
 
@@ -1784,7 +1838,7 @@ static void CyPmHviLviSaveDisable(void)
 ********************************************************************************
 *
 * Summary:
-*  Restores analog and digital LVI and HVI configuration.
+*  Restores the analog and digital LVI and HVI configuration.
 *
 * Parameters:
 *  None
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h
index 327908be..6ea9bd60 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * File Name: cyPm.h
-* Version 4.0
+* Version 4.20
 *
 * Description:
 *  Provides the function definitions for the power management API.
@@ -10,7 +10,7 @@
 *  System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -54,7 +54,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC3)
 
-    /* Wake up time for the Sleep mode */
+    /* Wake up time for Sleep mode */
     #define PM_SLEEP_TIME_ONE_PPS           (0x01u)
     #define PM_SLEEP_TIME_CTW_2MS           (0x02u)
     #define PM_SLEEP_TIME_CTW_4MS           (0x03u)
@@ -72,7 +72,7 @@ void CyPmOppsSet(void) ;
     /* Difference between parameter's value and register's one */
     #define CY_PM_FTW_INTERVAL_SHIFT        (0x000Eu)
 
-    /* Wake up time for the Alternate Active mode */
+    /* Wake up time for Alternate Active mode */
     #define PM_ALT_ACT_TIME_ONE_PPS         (0x0001u)
     #define PM_ALT_ACT_TIME_CTW_2MS         (0x0002u)
     #define PM_ALT_ACT_TIME_CTW_4MS         (0x0003u)
@@ -91,7 +91,7 @@ void CyPmOppsSet(void) ;
 #endif  /* (CY_PSOC3) */
 
 
-/* Wake up sources for the Sleep mode */
+/* Wake up sources for Sleep mode */
 #define PM_SLEEP_SRC_COMPARATOR0        (0x0001u)
 #define PM_SLEEP_SRC_COMPARATOR1        (0x0002u)
 #define PM_SLEEP_SRC_COMPARATOR2        (0x0004u)
@@ -104,7 +104,7 @@ void CyPmOppsSet(void) ;
 #define PM_SLEEP_SRC_ONE_PPS            (0x0800u)
 #define PM_SLEEP_SRC_LCD                (0x1000u)
 
-/* Wake up sources for the Alternate Active mode */
+/* Wake up sources for Alternate Active mode */
 #define PM_ALT_ACT_SRC_COMPARATOR0      (0x0001u)
 #define PM_ALT_ACT_SRC_COMPARATOR1      (0x0002u)
 #define PM_ALT_ACT_SRC_COMPARATOR2      (0x0004u)
@@ -145,7 +145,7 @@ void CyPmOppsSet(void) ;
 #define     CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US   (5u)
 
 
-/* Delay line bandgap current settling time starting from a wakeup event */
+/* Delay line bandgap current settling time starting from wakeup event */
 #define     CY_PM_CLK_DELAY_BANDGAP_SETTLE_US       (50u)
 
 /* Delay line internal bias settling */
@@ -177,7 +177,7 @@ void CyPmOppsSet(void) ;
 
 #if(CY_PSOC5)
 
-    /* The CPU clock is directly derived from bus clock */
+    /* CPU clock is directly derived from bus clock */
     #define     CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])
 
 #endif  /* (CY_PSOC5) */
@@ -186,7 +186,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low
 * power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI
 * instruction into the instruction stream generated by the compiler. The GCC
 * compiler has to execute assembly language instruction.
 *******************************************************************************/
@@ -219,7 +219,7 @@ void CyPmOppsSet(void) ;
 /*******************************************************************************
 * This macro defines the IMO frequency that will be set by CyPmSaveClocks()
 * function based on Enable Fast IMO during Startup option from the DWR file.
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the
 * low power mode and restore IMO back to the value set by CyPmSaveClocks()
 * immediately on wakeup.
 *******************************************************************************/
@@ -243,7 +243,7 @@ typedef struct cyPmClockBackupStruct
     /* CyPmSaveClocks()/CyPmRestoreClocks() */
     uint8  enClkA;              /* Analog clocks enable         */
     uint8  enClkD;              /* Digital clocks enable        */
-    uint8  masterClkSrc;        /* The Master clock source      */
+    uint8  masterClkSrc;        /* Master clock source          */
     uint8  imoFreq;             /* IMO frequency (reg's value)  */
     uint8  imoUsbClk;           /* IMO USB CLK (reg's value)    */
     uint8  flashWaitCycles;     /* Flash wait cycles            */
@@ -252,7 +252,7 @@ typedef struct cyPmClockBackupStruct
     uint8  clkImoSrc;
     uint8  imo2x;               /* IMO doubler enable state     */
     uint8  clkSyncDiv;          /* Master clk divider           */
-    uint16 clkBusDiv;           /* The clk_bus divider          */
+    uint16 clkBusDiv;           /* clk_bus divider              */
     uint8  pllEnableState;      /* PLL enable state             */
     uint8  xmhzEnableState;     /* XM HZ enable state           */
     uint8  clkDistDelay;        /* Delay for clk_bus and ACLKs  */
@@ -472,6 +472,14 @@ typedef struct cyPmBackupStruct
 #define CY_PM_BOOST_CR2_REG           (* (reg8 *) CYREG_BOOST_CR2 )
 #define CY_PM_BOOST_CR2_PTR           (  (reg8 *) CYREG_BOOST_CR2 )
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_REG           (* (reg8 *) CYREG_INTC_CSR_EN )
+    #define CY_PM_INTC_CSR_EN_PTR           (  (reg8 *) CYREG_INTC_CSR_EN )
+
+#endif  /* (CY_PSOC3) */
+
 
 /***************************************
 * Register Constants
@@ -521,7 +529,12 @@ typedef struct cyPmBackupStruct
 #define CY_PM_CLKDIST_IMO_OUT_IMO       (0x00u)
 #define CY_PM_CLKDIST_IMO2X_SRC         (0x40u)
 
-/* Waiting for the hibernate/sleep regulator to stabilize */
+#define CY_PM_CLKDIST_PLL_SRC_MASK      (0x03u)
+#define CY_PM_CLKDIST_PLL_SRC_IMO       (0x00u)
+#define CY_PM_CLKDIST_PLL_SRC_XTAL      (0x01u)
+#define CY_PM_CLKDIST_PLL_SRC_DSI       (0x02u)
+
+/* Waiting for hibernate/sleep regulator to stabilize */
 #define CY_PM_MODE_CSR_PWRUP_PULSE_Q    (0x08u)
 
 #define CY_PM_MODE_CSR_ACTIVE           (0x00u)     /* Active power mode      */
@@ -533,10 +546,10 @@ typedef struct cyPmBackupStruct
 /* I2C regulator backup enable */
 #define CY_PM_PWRSYS_CR1_I2CREG_BACKUP  (0x04u)
 
-/* When set, prepares the system to disable the LDO-A */
+/* When set, prepares system to disable LDO-A */
 #define CY_PM_PWRSYS_CR1_LDOA_ISO       (0x01u)
 
-/* When set, disables the analog LDO regulator */
+/* When set, disables analog LDO regulator */
 #define CY_PM_PWRSYS_CR1_LDOA_DIS       (0x02u)
 
 #define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET  (0x04u)
@@ -554,19 +567,19 @@ typedef struct cyPmBackupStruct
 /* Bus Clock divider to divide-by-one */
 #define CY_PM_BUS_CLK_DIV_BY_ONE        (0x00u)
 
-/* HVI/LVI feature on the external analog and digital supply mask */
+/* HVI/LVI feature on external analog and digital supply mask */
 #define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)
 
-/* The high-voltage-interrupt feature on the external analog supply */
+/* High-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_HVIA_EN         (0x04u)
 
-/* The low-voltage-interrupt feature on the external analog supply */
+/* Low-voltage-interrupt feature on external analog supply */
 #define CY_PM_RESET_CR1_LVIA_EN         (0x02u)
 
-/* The low-voltage-interrupt feature on the external digital supply */
+/* Low-voltage-interrupt feature on external digital supply */
 #define CY_PM_RESET_CR1_LVID_EN         (0x01u)
 
-/* Allows the system to program delays on clk_sync_d */
+/* Allows system to program delays on clk_sync_d */
 #define CY_PM_CLKDIST_DELAY_EN          (0x04u)
 
 
@@ -595,7 +608,7 @@ typedef struct cyPmBackupStruct
 #endif  /* (CY_PSOC3) */
 
 
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+/* Disables sleep regulator and shorts vccd to vpwrsleep */
 #define CY_PM_PWRSYS_SLP_TR_BYPASS          (0x10u)
 
 /* Boost Control 2: Select external precision reference */
@@ -615,9 +628,37 @@ typedef struct cyPmBackupStruct
 
 #endif  /* (CY_PSOC5) */
 
+#if(CY_PSOC3)
+
+    /* Interrrupt Controller Configuration and Status Register */
+    #define CY_PM_INTC_CSR_EN_CLK       (0x01u)
+
+#endif  /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of
+* whether lock is subsequently lost) until it is read. Upon reading it will
+* clear. If lock is still true then the bit will simply set again. If lock
+* happens to be false when the clear on read occurs then the bit will stay
+* cleared until the next lock event.
+*******************************************************************************/
+#define CY_PM_FASTCLK_PLL_LOCKED       (0x01u)
+
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #if(CY_PSOC3)
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h
index 2514d9aa..eb881789 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice.h
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h
index 27a4bffb..d36e44e6 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevice_trm.h
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
index dc11e6db..28f802c8 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu.inc
 * OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
index ede64b20..0de4ccb6 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cydevicegnu_trm.inc
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
index 8f6fcc72..75b02a6f 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
index 9ce82ff8..2fef27b2 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydeviceiar_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc
index b5f7a51f..244d4d53 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv.inc
 ; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
index 790c65b5..e3bfe5d0 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
@@ -1,7 +1,7 @@
 ;
 ; FILENAME: cydevicerv_trm.inc
 ; 
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator  3.1
 ;
 ; DESCRIPTION:
 ; This file provides all of the address values for the entire PSoC device.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h
index dac33841..7db03e67 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -3,15 +3,37 @@
 #include <cydevice.h>
 #include <cydevice_trm.h>
 
-/* USBFS_bus_reset */
-#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_bus_reset__INTC_MASK 0x800000u
-#define USBFS_bus_reset__INTC_NUMBER 23u
-#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
-#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
-#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* LED */
+#define LED__0__MASK 0x02u
+#define LED__0__PC CYREG_PRT0_PC1
+#define LED__0__PORT 0u
+#define LED__0__SHIFT 1
+#define LED__AG CYREG_PRT0_AG
+#define LED__AMUX CYREG_PRT0_AMUX
+#define LED__BIE CYREG_PRT0_BIE
+#define LED__BIT_MASK CYREG_PRT0_BIT_MASK
+#define LED__BYP CYREG_PRT0_BYP
+#define LED__CTL CYREG_PRT0_CTL
+#define LED__DM0 CYREG_PRT0_DM0
+#define LED__DM1 CYREG_PRT0_DM1
+#define LED__DM2 CYREG_PRT0_DM2
+#define LED__DR CYREG_PRT0_DR
+#define LED__INP_DIS CYREG_PRT0_INP_DIS
+#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define LED__LCD_EN CYREG_PRT0_LCD_EN
+#define LED__MASK 0x02u
+#define LED__PORT 0u
+#define LED__PRT CYREG_PRT0_PRT
+#define LED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define LED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define LED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define LED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define LED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define LED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define LED__PS CYREG_PRT0_PS
+#define LED__SHIFT 1
+#define LED__SLW CYREG_PRT0_SLW
 
 /* USBFS_arb_int */
 #define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -23,6 +45,122 @@
 #define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
+/* USBFS_bus_reset */
+#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_bus_reset__INTC_MASK 0x800000u
+#define USBFS_bus_reset__INTC_NUMBER 23u
+#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
+#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
+#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_Dm */
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x01u
+#define USBFS_ep_1__INTC_NUMBER 0u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x02u
+#define USBFS_ep_2__INTC_NUMBER 1u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
 /* USBFS_sof_int */
 #define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
 #define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
@@ -33,528 +171,6 @@
 #define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
 #define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x02u
-#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__0__PORT 5u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__0__SHIFT 1
-#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x01u
-#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__1__PORT 5u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__1__SHIFT 0
-#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__2__MASK 0x20u
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__2__PORT 6u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__2__SHIFT 5
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x10u
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__3__PORT 6u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__3__SHIFT 4
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x80u
-#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__4__PORT 2u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__4__SHIFT 7
-#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x40u
-#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__5__PORT 2u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__5__SHIFT 6
-#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x08u
-#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__6__PORT 2u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__6__SHIFT 3
-#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x04u
-#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__7__PORT 2u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__7__SHIFT 2
-#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x02u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__DB0__PORT 5u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB0__SHIFT 1
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x01u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__DB1__PORT 5u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB1__SHIFT 0
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB2__MASK 0x20u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__DB2__PORT 6u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB2__SHIFT 5
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x10u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__DB3__PORT 6u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB3__SHIFT 4
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x80u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__DB4__PORT 2u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB4__SHIFT 7
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x40u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__DB5__PORT 2u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB5__SHIFT 6
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x08u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__DB6__PORT 2u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB6__SHIFT 3
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x04u
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__DB7__PORT 2u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB7__SHIFT 2
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x01u
-#define USBFS_ep_1__INTC_NUMBER 0u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x02u
-#define USBFS_ep_2__INTC_NUMBER 1u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-#define SD_PULLUP__0__MASK 0x02u
-#define SD_PULLUP__0__PC CYREG_PRT3_PC1
-#define SD_PULLUP__0__PORT 3u
-#define SD_PULLUP__0__SHIFT 1
-#define SD_PULLUP__1__MASK 0x04u
-#define SD_PULLUP__1__PC CYREG_PRT3_PC2
-#define SD_PULLUP__1__PORT 3u
-#define SD_PULLUP__1__SHIFT 2
-#define SD_PULLUP__2__MASK 0x08u
-#define SD_PULLUP__2__PC CYREG_PRT3_PC3
-#define SD_PULLUP__2__PORT 3u
-#define SD_PULLUP__2__SHIFT 3
-#define SD_PULLUP__3__MASK 0x10u
-#define SD_PULLUP__3__PC CYREG_PRT3_PC4
-#define SD_PULLUP__3__PORT 3u
-#define SD_PULLUP__3__SHIFT 4
-#define SD_PULLUP__4__MASK 0x20u
-#define SD_PULLUP__4__PC CYREG_PRT3_PC5
-#define SD_PULLUP__4__PORT 3u
-#define SD_PULLUP__4__SHIFT 5
-#define SD_PULLUP__AG CYREG_PRT3_AG
-#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
-#define SD_PULLUP__BIE CYREG_PRT3_BIE
-#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_PULLUP__BYP CYREG_PRT3_BYP
-#define SD_PULLUP__CTL CYREG_PRT3_CTL
-#define SD_PULLUP__DM0 CYREG_PRT3_DM0
-#define SD_PULLUP__DM1 CYREG_PRT3_DM1
-#define SD_PULLUP__DM2 CYREG_PRT3_DM2
-#define SD_PULLUP__DR CYREG_PRT3_DR
-#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_PULLUP__MASK 0x3Eu
-#define SD_PULLUP__PORT 3u
-#define SD_PULLUP__PRT CYREG_PRT3_PRT
-#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_PULLUP__PS CYREG_PRT3_PS
-#define SD_PULLUP__SHIFT 1
-#define SD_PULLUP__SLW CYREG_PRT3_SLW
-
 /* USBFS_USB */
 #define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
 #define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
@@ -632,6 +248,8 @@
 #define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
 #define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
 #define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
 #define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
 #define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
 #define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
@@ -642,13 +260,13 @@
 #define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
 #define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
 #define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
 #define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
 #define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
 #define USBFS_USB__PM_ACT_MSK 0x01u
 #define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
 #define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
 #define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
 #define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
 #define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
@@ -673,13 +291,11 @@
 #define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
 #define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
 #define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
 #define USBFS_USB__SOF0 CYREG_USB_SOF0
 #define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
 #define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
 
 /* SCSI_Out */
 #define SCSI_Out__0__AG CYREG_PRT15_AG
@@ -1223,181 +839,571 @@
 #define SCSI_Out__SEL__SHIFT 7
 #define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+/* SCSI_Out_DBx */
+#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x02u
+#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__0__PORT 5u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__0__SHIFT 1
+#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x01u
+#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__1__PORT 5u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__1__SHIFT 0
+#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__2__MASK 0x20u
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__2__PORT 6u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__2__SHIFT 5
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x10u
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__3__PORT 6u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__3__SHIFT 4
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x80u
+#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__4__PORT 2u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__4__SHIFT 7
+#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x40u
+#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__5__PORT 2u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__5__SHIFT 6
+#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x08u
+#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__6__PORT 2u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__6__SHIFT 3
+#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x04u
+#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__7__PORT 2u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__7__SHIFT 2
+#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x02u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__DB0__PORT 5u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB0__SHIFT 1
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x01u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__DB1__PORT 5u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB1__SHIFT 0
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB2__MASK 0x20u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__DB2__PORT 6u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB2__SHIFT 5
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x10u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__DB3__PORT 6u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB3__SHIFT 4
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x80u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__DB4__PORT 2u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB4__SHIFT 7
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x40u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__DB5__PORT 2u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB5__SHIFT 6
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x08u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__DB6__PORT 2u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB6__SHIFT 3
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x04u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__DB7__PORT 2u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB7__SHIFT 2
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
 
-/* LED */
-#define LED__0__MASK 0x02u
-#define LED__0__PC CYREG_PRT0_PC1
-#define LED__0__PORT 0u
-#define LED__0__SHIFT 1
-#define LED__AG CYREG_PRT0_AG
-#define LED__AMUX CYREG_PRT0_AMUX
-#define LED__BIE CYREG_PRT0_BIE
-#define LED__BIT_MASK CYREG_PRT0_BIT_MASK
-#define LED__BYP CYREG_PRT0_BYP
-#define LED__CTL CYREG_PRT0_CTL
-#define LED__DM0 CYREG_PRT0_DM0
-#define LED__DM1 CYREG_PRT0_DM1
-#define LED__DM2 CYREG_PRT0_DM2
-#define LED__DR CYREG_PRT0_DR
-#define LED__INP_DIS CYREG_PRT0_INP_DIS
-#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define LED__LCD_EN CYREG_PRT0_LCD_EN
-#define LED__MASK 0x02u
-#define LED__PORT 0u
-#define LED__PRT CYREG_PRT0_PRT
-#define LED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define LED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define LED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define LED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define LED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define LED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define LED__PS CYREG_PRT0_PS
-#define LED__SHIFT 1
-#define LED__SLW CYREG_PRT0_SLW
+/* SD_PULLUP */
+#define SD_PULLUP__0__MASK 0x02u
+#define SD_PULLUP__0__PC CYREG_PRT3_PC1
+#define SD_PULLUP__0__PORT 3u
+#define SD_PULLUP__0__SHIFT 1
+#define SD_PULLUP__1__MASK 0x04u
+#define SD_PULLUP__1__PC CYREG_PRT3_PC2
+#define SD_PULLUP__1__PORT 3u
+#define SD_PULLUP__1__SHIFT 2
+#define SD_PULLUP__2__MASK 0x08u
+#define SD_PULLUP__2__PC CYREG_PRT3_PC3
+#define SD_PULLUP__2__PORT 3u
+#define SD_PULLUP__2__SHIFT 3
+#define SD_PULLUP__3__MASK 0x10u
+#define SD_PULLUP__3__PC CYREG_PRT3_PC4
+#define SD_PULLUP__3__PORT 3u
+#define SD_PULLUP__3__SHIFT 4
+#define SD_PULLUP__4__MASK 0x20u
+#define SD_PULLUP__4__PC CYREG_PRT3_PC5
+#define SD_PULLUP__4__PORT 3u
+#define SD_PULLUP__4__SHIFT 5
+#define SD_PULLUP__AG CYREG_PRT3_AG
+#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
+#define SD_PULLUP__BIE CYREG_PRT3_BIE
+#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_PULLUP__BYP CYREG_PRT3_BYP
+#define SD_PULLUP__CTL CYREG_PRT3_CTL
+#define SD_PULLUP__DM0 CYREG_PRT3_DM0
+#define SD_PULLUP__DM1 CYREG_PRT3_DM1
+#define SD_PULLUP__DM2 CYREG_PRT3_DM2
+#define SD_PULLUP__DR CYREG_PRT3_DR
+#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_PULLUP__MASK 0x3Eu
+#define SD_PULLUP__PORT 3u
+#define SD_PULLUP__PRT CYREG_PRT3_PRT
+#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_PULLUP__PS CYREG_PRT3_PS
+#define SD_PULLUP__SHIFT 1
+#define SD_PULLUP__SLW CYREG_PRT3_SLW
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
-#define CYDEV_CHIP_MEMBER_5B 4u
-#define CYDEV_CHIP_FAMILY_PSOC5 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 4u
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
-#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1
 #define BCLK__BUS_CLK__HZ 64000000U
 #define BCLK__BUS_CLK__KHZ 64000U
 #define BCLK__BUS_CLK__MHZ 64U
+#define CY_VERSION "PSoC Creator  3.1"
 #define CYDEV_BOOTLOADER_APPLICATIONS 1u
 #define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
 #define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
+#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
+#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1
+#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
 #define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
 #define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 3u
-#define CYDEV_CHIP_DIE_PSOC4A 2u
+#define CYDEV_CHIP_DIE_PANTHER 6u
+#define CYDEV_CHIP_DIE_PSOC4A 3u
+#define CYDEV_CHIP_DIE_PSOC5LP 5u
 #define CYDEV_CHIP_DIE_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_PSOC3 1u
 #define CYDEV_CHIP_FAMILY_PSOC4 2u
+#define CYDEV_CHIP_FAMILY_PSOC5 3u
 #define CYDEV_CHIP_FAMILY_UNKNOWN 0u
 #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
 #define CYDEV_CHIP_JTAG_ID 0x2E133069u
 #define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 2u
-#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_4A 3u
+#define CYDEV_CHIP_MEMBER_4D 2u
+#define CYDEV_CHIP_MEMBER_4F 4u
+#define CYDEV_CHIP_MEMBER_5A 6u
+#define CYDEV_CHIP_MEMBER_5B 5u
 #define CYDEV_CHIP_MEMBER_UNKNOWN 0u
 #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_3A_ES1 0u
 #define CYDEV_CHIP_REVISION_3A_ES2 1u
 #define CYDEV_CHIP_REVISION_3A_ES3 3u
 #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
 #define CYDEV_CHIP_REVISION_4A_ES0 17u
 #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_5A_ES0 0u
 #define CYDEV_CHIP_REVISION_5A_ES1 1u
 #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
 #define CYDEV_CHIP_REVISION_5B_ES0 0u
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
 #define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
 #define CYDEV_CONFIGURATION_COMPRESSED 1
 #define CYDEV_CONFIGURATION_DMA 0
 #define CYDEV_CONFIGURATION_ECC 0
 #define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
 #define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
 #define CYDEV_CONFIGURATION_MODE_DMA 2
 #define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DEBUGGING_DPS_Disable 3
 #define CYDEV_DEBUGGING_DPS_JTAG_4 1
 #define CYDEV_DEBUGGING_DPS_JTAG_5 0
 #define CYDEV_DEBUGGING_DPS_SWD 2
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
 #define CYDEV_DEBUGGING_ENABLE 1
 #define CYDEV_DEBUGGING_XRES 0
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
 #define CYDEV_DMA_CHANNELS_AVAILABLE 24u
 #define CYDEV_ECC_ENABLE 0
 #define CYDEV_HEAP_SIZE 0x0800
@@ -1425,16 +1431,34 @@
 #define CYDEV_VDDIO2_MV 5000
 #define CYDEV_VDDIO3 5.0
 #define CYDEV_VDDIO3_MV 5000
-#define CYDEV_VIO0 5
+#define CYDEV_VIO0 5.0
 #define CYDEV_VIO0_MV 5000
-#define CYDEV_VIO1 5
+#define CYDEV_VIO1 5.0
 #define CYDEV_VIO1_MV 5000
-#define CYDEV_VIO2 5
+#define CYDEV_VIO2 5.0
 #define CYDEV_VIO2_MV 5000
-#define CYDEV_VIO3 5
+#define CYDEV_VIO3 5.0
 #define CYDEV_VIO3_MV 5000
-#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
+#define CYIPBLOCK_ARM_CM3_VERSION 0
+#define CYIPBLOCK_P3_ANAIF_VERSION 0
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
+#define CYIPBLOCK_P3_COMP_VERSION 0
+#define CYIPBLOCK_P3_DMA_VERSION 0
+#define CYIPBLOCK_P3_DRQ_VERSION 0
+#define CYIPBLOCK_P3_EMIF_VERSION 0
+#define CYIPBLOCK_P3_I2C_VERSION 0
+#define CYIPBLOCK_P3_LCD_VERSION 0
+#define CYIPBLOCK_P3_LPF_VERSION 0
+#define CYIPBLOCK_P3_PM_VERSION 0
+#define CYIPBLOCK_P3_TIMER_VERSION 0
+#define CYIPBLOCK_P3_USB_VERSION 0
+#define CYIPBLOCK_P3_VIDAC_VERSION 0
+#define CYIPBLOCK_P3_VREF_VERSION 0
+#define CYIPBLOCK_S8_GPIO_VERSION 0
+#define CYIPBLOCK_S8_IRQ_VERSION 0
+#define CYIPBLOCK_S8_SAR_VERSION 0
+#define CYIPBLOCK_S8_SIO_VERSION 0
+#define CYIPBLOCK_S8_UDB_VERSION 0
 #define DMA_CHANNELS_USED__MASK0 0x00000000u
 #define CYDEV_BOOTLOADER_ENABLE 1
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 88469572..0fdd743a 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator with device 
@@ -410,7 +410,7 @@ void cyfitter_cfg(void)
 		for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
 		{
 			const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
-			CYMEMZERO(ms->address, (uint32)(ms->size));
+			CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
 		}
 
 		cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
index 191ee788..3e3d4993 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * Description:
 * This file is automatically generated by PSoC Creator.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 461a6778..2e4a3b02 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -3,15 +3,37 @@
 .include "cydevicegnu.inc"
 .include "cydevicegnu_trm.inc"
 
-/* USBFS_bus_reset */
-.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_bus_reset__INTC_MASK, 0x800000
-.set USBFS_bus_reset__INTC_NUMBER, 23
-.set USBFS_bus_reset__INTC_PRIOR_NUM, 7
-.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
-.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* LED */
+.set LED__0__MASK, 0x02
+.set LED__0__PC, CYREG_PRT0_PC1
+.set LED__0__PORT, 0
+.set LED__0__SHIFT, 1
+.set LED__AG, CYREG_PRT0_AG
+.set LED__AMUX, CYREG_PRT0_AMUX
+.set LED__BIE, CYREG_PRT0_BIE
+.set LED__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set LED__BYP, CYREG_PRT0_BYP
+.set LED__CTL, CYREG_PRT0_CTL
+.set LED__DM0, CYREG_PRT0_DM0
+.set LED__DM1, CYREG_PRT0_DM1
+.set LED__DM2, CYREG_PRT0_DM2
+.set LED__DR, CYREG_PRT0_DR
+.set LED__INP_DIS, CYREG_PRT0_INP_DIS
+.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set LED__LCD_EN, CYREG_PRT0_LCD_EN
+.set LED__MASK, 0x02
+.set LED__PORT, 0
+.set LED__PRT, CYREG_PRT0_PRT
+.set LED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set LED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set LED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set LED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set LED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set LED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set LED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set LED__PS, CYREG_PRT0_PS
+.set LED__SHIFT, 1
+.set LED__SLW, CYREG_PRT0_SLW
 
 /* USBFS_arb_int */
 .set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -23,6 +45,122 @@
 .set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
+/* USBFS_bus_reset */
+.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_bus_reset__INTC_MASK, 0x800000
+.set USBFS_bus_reset__INTC_NUMBER, 23
+.set USBFS_bus_reset__INTC_PRIOR_NUM, 7
+.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
+.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_Dm */
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x01
+.set USBFS_ep_1__INTC_NUMBER, 0
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x02
+.set USBFS_ep_2__INTC_NUMBER, 1
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
 /* USBFS_sof_int */
 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
 .set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
@@ -33,528 +171,6 @@
 .set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
 .set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x02
-.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__0__PORT, 5
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__0__SHIFT, 1
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x01
-.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__1__PORT, 5
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__1__SHIFT, 0
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__2__MASK, 0x20
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__2__PORT, 6
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__2__SHIFT, 5
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x10
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__3__PORT, 6
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__3__SHIFT, 4
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x80
-.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__4__PORT, 2
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__4__SHIFT, 7
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x40
-.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__5__PORT, 2
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__5__SHIFT, 6
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x08
-.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__6__PORT, 2
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__6__SHIFT, 3
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x04
-.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__7__PORT, 2
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__7__SHIFT, 2
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x02
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__DB0__PORT, 5
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 1
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x01
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__DB1__PORT, 5
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 0
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB2__MASK, 0x20
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__DB2__PORT, 6
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 5
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x10
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__DB3__PORT, 6
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 4
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x80
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__DB4__PORT, 2
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 7
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x40
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__DB5__PORT, 2
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 6
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x08
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__DB6__PORT, 2
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 3
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x04
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__DB7__PORT, 2
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 2
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x01
-.set USBFS_ep_1__INTC_NUMBER, 0
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x02
-.set USBFS_ep_2__INTC_NUMBER, 1
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-.set SD_PULLUP__0__MASK, 0x02
-.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
-.set SD_PULLUP__0__PORT, 3
-.set SD_PULLUP__0__SHIFT, 1
-.set SD_PULLUP__1__MASK, 0x04
-.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
-.set SD_PULLUP__1__PORT, 3
-.set SD_PULLUP__1__SHIFT, 2
-.set SD_PULLUP__2__MASK, 0x08
-.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
-.set SD_PULLUP__2__PORT, 3
-.set SD_PULLUP__2__SHIFT, 3
-.set SD_PULLUP__3__MASK, 0x10
-.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
-.set SD_PULLUP__3__PORT, 3
-.set SD_PULLUP__3__SHIFT, 4
-.set SD_PULLUP__4__MASK, 0x20
-.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
-.set SD_PULLUP__4__PORT, 3
-.set SD_PULLUP__4__SHIFT, 5
-.set SD_PULLUP__AG, CYREG_PRT3_AG
-.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX
-.set SD_PULLUP__BIE, CYREG_PRT3_BIE
-.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_PULLUP__BYP, CYREG_PRT3_BYP
-.set SD_PULLUP__CTL, CYREG_PRT3_CTL
-.set SD_PULLUP__DM0, CYREG_PRT3_DM0
-.set SD_PULLUP__DM1, CYREG_PRT3_DM1
-.set SD_PULLUP__DM2, CYREG_PRT3_DM2
-.set SD_PULLUP__DR, CYREG_PRT3_DR
-.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_PULLUP__MASK, 0x3E
-.set SD_PULLUP__PORT, 3
-.set SD_PULLUP__PRT, CYREG_PRT3_PRT
-.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_PULLUP__PS, CYREG_PRT3_PS
-.set SD_PULLUP__SHIFT, 1
-.set SD_PULLUP__SLW, CYREG_PRT3_SLW
-
 /* USBFS_USB */
 .set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
 .set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
@@ -632,6 +248,8 @@
 .set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
 .set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
 .set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
 .set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
 .set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
 .set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
@@ -642,13 +260,13 @@
 .set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
 .set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
 .set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
 .set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
 .set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
 .set USBFS_USB__PM_ACT_MSK, 0x01
 .set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
 .set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
 .set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
 .set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
 .set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
@@ -673,13 +291,11 @@
 .set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
 .set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
 .set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
 .set USBFS_USB__SOF0, CYREG_USB_SOF0
 .set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
 .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
 
 /* SCSI_Out */
 .set SCSI_Out__0__AG, CYREG_PRT15_AG
@@ -1223,181 +839,570 @@
 .set SCSI_Out__SEL__SHIFT, 7
 .set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+/* SCSI_Out_DBx */
+.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x02
+.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__0__PORT, 5
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__0__SHIFT, 1
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x01
+.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__1__PORT, 5
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__1__SHIFT, 0
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__2__MASK, 0x20
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__2__PORT, 6
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__2__SHIFT, 5
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x10
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__3__PORT, 6
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__3__SHIFT, 4
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x80
+.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__4__PORT, 2
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__4__SHIFT, 7
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x40
+.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__5__PORT, 2
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__5__SHIFT, 6
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x08
+.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__6__PORT, 2
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__6__SHIFT, 3
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x04
+.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__7__PORT, 2
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__7__SHIFT, 2
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x02
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__DB0__PORT, 5
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 1
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x01
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__DB1__PORT, 5
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 0
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB2__MASK, 0x20
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__DB2__PORT, 6
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 5
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x10
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__DB3__PORT, 6
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 4
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x80
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__DB4__PORT, 2
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 7
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x40
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__DB5__PORT, 2
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 6
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x08
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__DB6__PORT, 2
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 3
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x04
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__DB7__PORT, 2
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 2
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
 
-/* LED */
-.set LED__0__MASK, 0x02
-.set LED__0__PC, CYREG_PRT0_PC1
-.set LED__0__PORT, 0
-.set LED__0__SHIFT, 1
-.set LED__AG, CYREG_PRT0_AG
-.set LED__AMUX, CYREG_PRT0_AMUX
-.set LED__BIE, CYREG_PRT0_BIE
-.set LED__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set LED__BYP, CYREG_PRT0_BYP
-.set LED__CTL, CYREG_PRT0_CTL
-.set LED__DM0, CYREG_PRT0_DM0
-.set LED__DM1, CYREG_PRT0_DM1
-.set LED__DM2, CYREG_PRT0_DM2
-.set LED__DR, CYREG_PRT0_DR
-.set LED__INP_DIS, CYREG_PRT0_INP_DIS
-.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set LED__LCD_EN, CYREG_PRT0_LCD_EN
-.set LED__MASK, 0x02
-.set LED__PORT, 0
-.set LED__PRT, CYREG_PRT0_PRT
-.set LED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set LED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set LED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set LED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set LED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set LED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set LED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set LED__PS, CYREG_PRT0_PS
-.set LED__SHIFT, 1
-.set LED__SLW, CYREG_PRT0_SLW
+/* SD_PULLUP */
+.set SD_PULLUP__0__MASK, 0x02
+.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
+.set SD_PULLUP__0__PORT, 3
+.set SD_PULLUP__0__SHIFT, 1
+.set SD_PULLUP__1__MASK, 0x04
+.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
+.set SD_PULLUP__1__PORT, 3
+.set SD_PULLUP__1__SHIFT, 2
+.set SD_PULLUP__2__MASK, 0x08
+.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
+.set SD_PULLUP__2__PORT, 3
+.set SD_PULLUP__2__SHIFT, 3
+.set SD_PULLUP__3__MASK, 0x10
+.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
+.set SD_PULLUP__3__PORT, 3
+.set SD_PULLUP__3__SHIFT, 4
+.set SD_PULLUP__4__MASK, 0x20
+.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
+.set SD_PULLUP__4__PORT, 3
+.set SD_PULLUP__4__SHIFT, 5
+.set SD_PULLUP__AG, CYREG_PRT3_AG
+.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX
+.set SD_PULLUP__BIE, CYREG_PRT3_BIE
+.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_PULLUP__BYP, CYREG_PRT3_BYP
+.set SD_PULLUP__CTL, CYREG_PRT3_CTL
+.set SD_PULLUP__DM0, CYREG_PRT3_DM0
+.set SD_PULLUP__DM1, CYREG_PRT3_DM1
+.set SD_PULLUP__DM2, CYREG_PRT3_DM2
+.set SD_PULLUP__DR, CYREG_PRT3_DR
+.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_PULLUP__MASK, 0x3E
+.set SD_PULLUP__PORT, 3
+.set SD_PULLUP__PRT, CYREG_PRT3_PRT
+.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_PULLUP__PS, CYREG_PRT3_PS
+.set SD_PULLUP__SHIFT, 1
+.set SD_PULLUP__SLW, CYREG_PRT3_SLW
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
-.set CYDEV_CHIP_MEMBER_5B, 4
-.set CYDEV_CHIP_FAMILY_PSOC5, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 4
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
-.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1
 .set BCLK__BUS_CLK__HZ, 64000000
 .set BCLK__BUS_CLK__KHZ, 64000
 .set BCLK__BUS_CLK__MHZ, 64
 .set CYDEV_BOOTLOADER_APPLICATIONS, 1
 .set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0
 .set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1
+.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0
+.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1
+.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
 .set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
 .set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 3
-.set CYDEV_CHIP_DIE_PSOC4A, 2
+.set CYDEV_CHIP_DIE_PANTHER, 6
+.set CYDEV_CHIP_DIE_PSOC4A, 3
+.set CYDEV_CHIP_DIE_PSOC5LP, 5
 .set CYDEV_CHIP_DIE_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_PSOC3, 1
 .set CYDEV_CHIP_FAMILY_PSOC4, 2
+.set CYDEV_CHIP_FAMILY_PSOC5, 3
 .set CYDEV_CHIP_FAMILY_UNKNOWN, 0
 .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
 .set CYDEV_CHIP_JTAG_ID, 0x2E133069
 .set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 2
-.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_4A, 3
+.set CYDEV_CHIP_MEMBER_4D, 2
+.set CYDEV_CHIP_MEMBER_4F, 4
+.set CYDEV_CHIP_MEMBER_5A, 6
+.set CYDEV_CHIP_MEMBER_5B, 5
 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0
 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_3A_ES1, 0
 .set CYDEV_CHIP_REVISION_3A_ES2, 1
 .set CYDEV_CHIP_REVISION_3A_ES3, 3
 .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
 .set CYDEV_CHIP_REVISION_4A_ES0, 17
 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_5A_ES0, 0
 .set CYDEV_CHIP_REVISION_5A_ES1, 1
 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
 .set CYDEV_CHIP_REVISION_5B_ES0, 0
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
 .set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
 .set CYDEV_CONFIGURATION_COMPRESSED, 1
 .set CYDEV_CONFIGURATION_DMA, 0
 .set CYDEV_CONFIGURATION_ECC, 0
 .set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
 .set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
 .set CYDEV_CONFIGURATION_MODE_DMA, 2
 .set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DEBUGGING_DPS_Disable, 3
 .set CYDEV_DEBUGGING_DPS_JTAG_4, 1
 .set CYDEV_DEBUGGING_DPS_JTAG_5, 0
 .set CYDEV_DEBUGGING_DPS_SWD, 2
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
 .set CYDEV_DEBUGGING_ENABLE, 1
 .set CYDEV_DEBUGGING_XRES, 0
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
 .set CYDEV_DMA_CHANNELS_AVAILABLE, 24
 .set CYDEV_ECC_ENABLE, 0
 .set CYDEV_HEAP_SIZE, 0x0800
@@ -1419,16 +1424,30 @@
 .set CYDEV_VDDIO1_MV, 5000
 .set CYDEV_VDDIO2_MV, 5000
 .set CYDEV_VDDIO3_MV, 5000
-.set CYDEV_VIO0, 5
 .set CYDEV_VIO0_MV, 5000
-.set CYDEV_VIO1, 5
 .set CYDEV_VIO1_MV, 5000
-.set CYDEV_VIO2, 5
 .set CYDEV_VIO2_MV, 5000
-.set CYDEV_VIO3, 5
 .set CYDEV_VIO3_MV, 5000
-.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
+.set CYIPBLOCK_ARM_CM3_VERSION, 0
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
+.set CYIPBLOCK_P3_COMP_VERSION, 0
+.set CYIPBLOCK_P3_DMA_VERSION, 0
+.set CYIPBLOCK_P3_DRQ_VERSION, 0
+.set CYIPBLOCK_P3_EMIF_VERSION, 0
+.set CYIPBLOCK_P3_I2C_VERSION, 0
+.set CYIPBLOCK_P3_LCD_VERSION, 0
+.set CYIPBLOCK_P3_LPF_VERSION, 0
+.set CYIPBLOCK_P3_PM_VERSION, 0
+.set CYIPBLOCK_P3_TIMER_VERSION, 0
+.set CYIPBLOCK_P3_USB_VERSION, 0
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0
+.set CYIPBLOCK_P3_VREF_VERSION, 0
+.set CYIPBLOCK_S8_GPIO_VERSION, 0
+.set CYIPBLOCK_S8_IRQ_VERSION, 0
+.set CYIPBLOCK_S8_SAR_VERSION, 0
+.set CYIPBLOCK_S8_SIO_VERSION, 0
+.set CYIPBLOCK_S8_UDB_VERSION, 0
 .set DMA_CHANNELS_USED__MASK0, 0x00000000
 .set CYDEV_BOOTLOADER_ENABLE, 1
 .endif
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index a84954a5..570da230 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -3,15 +3,37 @@
     INCLUDE cydeviceiar.inc
     INCLUDE cydeviceiar_trm.inc
 
-/* USBFS_bus_reset */
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_bus_reset__INTC_MASK EQU 0x800000
-USBFS_bus_reset__INTC_NUMBER EQU 23
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* LED */
+LED__0__MASK EQU 0x02
+LED__0__PC EQU CYREG_PRT0_PC1
+LED__0__PORT EQU 0
+LED__0__SHIFT EQU 1
+LED__AG EQU CYREG_PRT0_AG
+LED__AMUX EQU CYREG_PRT0_AMUX
+LED__BIE EQU CYREG_PRT0_BIE
+LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED__BYP EQU CYREG_PRT0_BYP
+LED__CTL EQU CYREG_PRT0_CTL
+LED__DM0 EQU CYREG_PRT0_DM0
+LED__DM1 EQU CYREG_PRT0_DM1
+LED__DM2 EQU CYREG_PRT0_DM2
+LED__DR EQU CYREG_PRT0_DR
+LED__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED__MASK EQU 0x02
+LED__PORT EQU 0
+LED__PRT EQU CYREG_PRT0_PRT
+LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED__PS EQU CYREG_PRT0_PS
+LED__SHIFT EQU 1
+LED__SLW EQU CYREG_PRT0_SLW
 
 /* USBFS_arb_int */
 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -23,6 +45,122 @@ USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
 USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
+/* USBFS_bus_reset */
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_bus_reset__INTC_MASK EQU 0x800000
+USBFS_bus_reset__INTC_NUMBER EQU 23
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_Dm */
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x01
+USBFS_ep_1__INTC_NUMBER EQU 0
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x02
+USBFS_ep_2__INTC_NUMBER EQU 1
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
 /* USBFS_sof_int */
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@@ -33,528 +171,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x01
-USBFS_ep_1__INTC_NUMBER EQU 0
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x02
-USBFS_ep_2__INTC_NUMBER EQU 1
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-SD_PULLUP__0__MASK EQU 0x02
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
-SD_PULLUP__0__PORT EQU 3
-SD_PULLUP__0__SHIFT EQU 1
-SD_PULLUP__1__MASK EQU 0x04
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
-SD_PULLUP__1__PORT EQU 3
-SD_PULLUP__1__SHIFT EQU 2
-SD_PULLUP__2__MASK EQU 0x08
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
-SD_PULLUP__2__PORT EQU 3
-SD_PULLUP__2__SHIFT EQU 3
-SD_PULLUP__3__MASK EQU 0x10
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
-SD_PULLUP__3__PORT EQU 3
-SD_PULLUP__3__SHIFT EQU 4
-SD_PULLUP__4__MASK EQU 0x20
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
-SD_PULLUP__4__PORT EQU 3
-SD_PULLUP__4__SHIFT EQU 5
-SD_PULLUP__AG EQU CYREG_PRT3_AG
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
-SD_PULLUP__DR EQU CYREG_PRT3_DR
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_PULLUP__MASK EQU 0x3E
-SD_PULLUP__PORT EQU 3
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_PULLUP__PS EQU CYREG_PRT3_PS
-SD_PULLUP__SHIFT EQU 1
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW
-
 /* USBFS_USB */
 USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
 USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
@@ -632,6 +248,8 @@ USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
 USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
 USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
 USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
 USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
 USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
@@ -642,13 +260,13 @@ USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
 USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
 USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
 USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
 USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
 USBFS_USB__PM_ACT_MSK EQU 0x01
 USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
 USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
 USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
 USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
@@ -673,13 +291,11 @@ USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
 USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
 USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
 USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SOF0 EQU CYREG_USB_SOF0
 USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 
 /* SCSI_Out */
 SCSI_Out__0__AG EQU CYREG_PRT15_AG
@@ -1223,181 +839,570 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
 SCSI_Out__SEL__SHIFT EQU 7
 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
 
-/* USBFS_Dm */
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
 
-/* LED */
-LED__0__MASK EQU 0x02
-LED__0__PC EQU CYREG_PRT0_PC1
-LED__0__PORT EQU 0
-LED__0__SHIFT EQU 1
-LED__AG EQU CYREG_PRT0_AG
-LED__AMUX EQU CYREG_PRT0_AMUX
-LED__BIE EQU CYREG_PRT0_BIE
-LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED__BYP EQU CYREG_PRT0_BYP
-LED__CTL EQU CYREG_PRT0_CTL
-LED__DM0 EQU CYREG_PRT0_DM0
-LED__DM1 EQU CYREG_PRT0_DM1
-LED__DM2 EQU CYREG_PRT0_DM2
-LED__DR EQU CYREG_PRT0_DR
-LED__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED__MASK EQU 0x02
-LED__PORT EQU 0
-LED__PRT EQU CYREG_PRT0_PRT
-LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED__PS EQU CYREG_PRT0_PS
-LED__SHIFT EQU 1
-LED__SLW EQU CYREG_PRT0_SLW
+/* SD_PULLUP */
+SD_PULLUP__0__MASK EQU 0x02
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
+SD_PULLUP__0__PORT EQU 3
+SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__MASK EQU 0x04
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
+SD_PULLUP__1__PORT EQU 3
+SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__MASK EQU 0x08
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
+SD_PULLUP__2__PORT EQU 3
+SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__MASK EQU 0x10
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
+SD_PULLUP__3__PORT EQU 3
+SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__MASK EQU 0x20
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
+SD_PULLUP__4__PORT EQU 3
+SD_PULLUP__4__SHIFT EQU 5
+SD_PULLUP__AG EQU CYREG_PRT3_AG
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
+SD_PULLUP__DR EQU CYREG_PRT3_DR
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_PULLUP__MASK EQU 0x3E
+SD_PULLUP__PORT EQU 3
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_PULLUP__PS EQU CYREG_PRT3_PS
+SD_PULLUP__SHIFT EQU 1
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW
 
 /* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
 BCLK__BUS_CLK__HZ EQU 64000000
 BCLK__BUS_CLK__KHZ EQU 64000
 BCLK__BUS_CLK__MHZ EQU 64
 CYDEV_BOOTLOADER_APPLICATIONS EQU 1
 CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
 CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
 CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0800
@@ -1419,16 +1424,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 5000
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
-CYDEV_VIO3 EQU 5
 CYDEV_VIO3_MV EQU 5000
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x00000000
 CYDEV_BOOTLOADER_ENABLE EQU 1
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index e03927f0..49b39c06 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -3,15 +3,37 @@ INCLUDED_CYFITTERRV_INC EQU 1
     GET cydevicerv.inc
     GET cydevicerv_trm.inc
 
-; USBFS_bus_reset
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_bus_reset__INTC_MASK EQU 0x800000
-USBFS_bus_reset__INTC_NUMBER EQU 23
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; LED
+LED__0__MASK EQU 0x02
+LED__0__PC EQU CYREG_PRT0_PC1
+LED__0__PORT EQU 0
+LED__0__SHIFT EQU 1
+LED__AG EQU CYREG_PRT0_AG
+LED__AMUX EQU CYREG_PRT0_AMUX
+LED__BIE EQU CYREG_PRT0_BIE
+LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED__BYP EQU CYREG_PRT0_BYP
+LED__CTL EQU CYREG_PRT0_CTL
+LED__DM0 EQU CYREG_PRT0_DM0
+LED__DM1 EQU CYREG_PRT0_DM1
+LED__DM2 EQU CYREG_PRT0_DM2
+LED__DR EQU CYREG_PRT0_DR
+LED__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED__MASK EQU 0x02
+LED__PORT EQU 0
+LED__PRT EQU CYREG_PRT0_PRT
+LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED__PS EQU CYREG_PRT0_PS
+LED__SHIFT EQU 1
+LED__SLW EQU CYREG_PRT0_SLW
 
 ; USBFS_arb_int
 USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -23,6 +45,122 @@ USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
 USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
+; USBFS_bus_reset
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_bus_reset__INTC_MASK EQU 0x800000
+USBFS_bus_reset__INTC_NUMBER EQU 23
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_Dm
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+; USBFS_Dp
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+; USBFS_dp_int
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_1
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x01
+USBFS_ep_1__INTC_NUMBER EQU 0
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_2
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x02
+USBFS_ep_2__INTC_NUMBER EQU 1
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
 ; USBFS_sof_int
 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
 USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
@@ -33,528 +171,6 @@ USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
 USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
 USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
 
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x01
-USBFS_ep_1__INTC_NUMBER EQU 0
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x02
-USBFS_ep_2__INTC_NUMBER EQU 1
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_PULLUP
-SD_PULLUP__0__MASK EQU 0x02
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
-SD_PULLUP__0__PORT EQU 3
-SD_PULLUP__0__SHIFT EQU 1
-SD_PULLUP__1__MASK EQU 0x04
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
-SD_PULLUP__1__PORT EQU 3
-SD_PULLUP__1__SHIFT EQU 2
-SD_PULLUP__2__MASK EQU 0x08
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
-SD_PULLUP__2__PORT EQU 3
-SD_PULLUP__2__SHIFT EQU 3
-SD_PULLUP__3__MASK EQU 0x10
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
-SD_PULLUP__3__PORT EQU 3
-SD_PULLUP__3__SHIFT EQU 4
-SD_PULLUP__4__MASK EQU 0x20
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
-SD_PULLUP__4__PORT EQU 3
-SD_PULLUP__4__SHIFT EQU 5
-SD_PULLUP__AG EQU CYREG_PRT3_AG
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
-SD_PULLUP__DR EQU CYREG_PRT3_DR
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_PULLUP__MASK EQU 0x3E
-SD_PULLUP__PORT EQU 3
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_PULLUP__PS EQU CYREG_PRT3_PS
-SD_PULLUP__SHIFT EQU 1
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW
-
 ; USBFS_USB
 USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
 USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
@@ -632,6 +248,8 @@ USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
 USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
 USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
 USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
 USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
 USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
@@ -642,13 +260,13 @@ USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
 USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
 USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
 USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
 USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
 USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
 USBFS_USB__PM_ACT_MSK EQU 0x01
 USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
 USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
 USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
 USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
@@ -673,13 +291,11 @@ USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
 USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
 USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
 USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
 USBFS_USB__SOF0 EQU CYREG_USB_SOF0
 USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
 
 ; SCSI_Out
 SCSI_Out__0__AG EQU CYREG_PRT15_AG
@@ -1223,181 +839,570 @@ SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
 SCSI_Out__SEL__SHIFT EQU 7
 SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
 
-; USBFS_Dm
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-
-; USBFS_Dp
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+; SCSI_Out_DBx
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
 
-; LED
-LED__0__MASK EQU 0x02
-LED__0__PC EQU CYREG_PRT0_PC1
-LED__0__PORT EQU 0
-LED__0__SHIFT EQU 1
-LED__AG EQU CYREG_PRT0_AG
-LED__AMUX EQU CYREG_PRT0_AMUX
-LED__BIE EQU CYREG_PRT0_BIE
-LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED__BYP EQU CYREG_PRT0_BYP
-LED__CTL EQU CYREG_PRT0_CTL
-LED__DM0 EQU CYREG_PRT0_DM0
-LED__DM1 EQU CYREG_PRT0_DM1
-LED__DM2 EQU CYREG_PRT0_DM2
-LED__DR EQU CYREG_PRT0_DR
-LED__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED__MASK EQU 0x02
-LED__PORT EQU 0
-LED__PRT EQU CYREG_PRT0_PRT
-LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED__PS EQU CYREG_PRT0_PS
-LED__SHIFT EQU 1
-LED__SLW EQU CYREG_PRT0_SLW
+; SD_PULLUP
+SD_PULLUP__0__MASK EQU 0x02
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
+SD_PULLUP__0__PORT EQU 3
+SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__MASK EQU 0x04
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
+SD_PULLUP__1__PORT EQU 3
+SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__MASK EQU 0x08
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
+SD_PULLUP__2__PORT EQU 3
+SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__MASK EQU 0x10
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
+SD_PULLUP__3__PORT EQU 3
+SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__MASK EQU 0x20
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
+SD_PULLUP__4__PORT EQU 3
+SD_PULLUP__4__SHIFT EQU 5
+SD_PULLUP__AG EQU CYREG_PRT3_AG
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
+SD_PULLUP__DR EQU CYREG_PRT3_DR
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_PULLUP__MASK EQU 0x3E
+SD_PULLUP__PORT EQU 3
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_PULLUP__PS EQU CYREG_PRT3_PS
+SD_PULLUP__SHIFT EQU 1
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW
 
 ; Miscellaneous
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
 BCLK__BUS_CLK__HZ EQU 64000000
 BCLK__BUS_CLK__KHZ EQU 64000
 BCLK__BUS_CLK__MHZ EQU 64
 CYDEV_BOOTLOADER_APPLICATIONS EQU 1
 CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
 CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
 CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
 CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
 CYDEV_CHIP_DIE_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_PSOC3 EQU 1
 CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
 CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
 CYDEV_CHIP_JTAG_ID EQU 0x2E133069
 CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_3A_ES1 EQU 0
 CYDEV_CHIP_REVISION_3A_ES2 EQU 1
 CYDEV_CHIP_REVISION_3A_ES3 EQU 3
 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
 CYDEV_CHIP_REVISION_4A_ES0 EQU 17
 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_5A_ES0 EQU 0
 CYDEV_CHIP_REVISION_5A_ES1 EQU 1
 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
 CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
 CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
 CYDEV_CONFIGURATION_COMPRESSED EQU 1
 CYDEV_CONFIGURATION_DMA EQU 0
 CYDEV_CONFIGURATION_ECC EQU 0
 CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
 CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
 CYDEV_CONFIGURATION_MODE_DMA EQU 2
 CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DEBUGGING_DPS_Disable EQU 3
 CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
 CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
 CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
 CYDEV_DEBUGGING_ENABLE EQU 1
 CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
 CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
 CYDEV_ECC_ENABLE EQU 0
 CYDEV_HEAP_SIZE EQU 0x0800
@@ -1419,16 +1424,30 @@ CYDEV_VDDIO0_MV EQU 5000
 CYDEV_VDDIO1_MV EQU 5000
 CYDEV_VDDIO2_MV EQU 5000
 CYDEV_VDDIO3_MV EQU 5000
-CYDEV_VIO0 EQU 5
 CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
 CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
 CYDEV_VIO2_MV EQU 5000
-CYDEV_VIO3 EQU 5
 CYDEV_VIO3_MV EQU 5000
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
 DMA_CHANNELS_USED__MASK0 EQU 0x00000000
 CYDEV_BOOTLOADER_ENABLE EQU 1
     ENDIF
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c
index 38cbe3ae..94803895 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 * FILENAME: cymetadata.c
 * 
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator  3.1
 *
 * DESCRIPTION:
 * This file defines all extra memory spaces that need to be included.
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h
index 6caced2f..b7525d13 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h
@@ -1,9 +1,9 @@
 /*******************************************************************************
 * File Name: cypins.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   This file contains the function prototypes and constants used for port/pin
+*   This file contains the function prototypes and constants used for a port/pin
 *   in access and control.
 *
 *  Note:
@@ -11,7 +11,7 @@
 *   System Reference Guide provided with PSoC Creator.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -103,6 +103,13 @@
 *  Note that this only has an effect for pins configured as software pins that
 *  are not driven by hardware.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16).
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -123,7 +130,14 @@
 ********************************************************************************
 *
 * Summary:
-*  This macro sets the state of the specified pin to 0
+*  This macro sets the state of the specified pin to 0.
+*
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
 *
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
@@ -147,6 +161,13 @@
 * Summary:
 *  Sets the drive mode for the pin (DM).
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: Port pin configuration register (uint16)
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -193,7 +214,7 @@
 *
 *
 * Return:
-*   mode:  Current drive mode for the pin
+*   mode:  The current drive mode for the pin
 *
 *   Define                Source
 *   PIN_DM_ALG_HIZ        Analog HiZ
@@ -214,10 +235,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to fast edge rate.
+*  Set the slew rate for the pin to fast the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -239,10 +267,17 @@
 ********************************************************************************
 *
 * Summary:
-*  Set the slew rate for the pin to slow edge rate.
+*  Set the slew rate for the pin to slow the edge rate.
 *  Note that this only applies for pins in strong output drive modes,
 *  not to resistive drive modes.
 *
+*  The macro operation is not atomic. It is not guaranteed that shared register
+*  will remain uncorrupted during simultaneous read-modify-write operations
+*  performed by two threads (main and interrupt threads). To guarantee data
+*  integrity in such cases, the macro should be invoked while the specific
+*  interrupt is disabled or within critical section (all interrupts are
+*  disabled).
+*
 * Parameters:
 *   pinPC: address of a Pin Configuration register.
 *   #defines for each pin on a chip are provided in the cydevice_trm.h file
@@ -259,7 +294,18 @@
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
 #define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)
 #define PC_DRIVE_MODE_MASK  (CY_PINS_PC_DRIVE_MODE_MASK)
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h
index 24db0621..528f949f 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
 * FILENAME: cytypes.h
-* Version 4.0
+* Version 4.20
 *
 *  Description:
 *  CyTypes provides register access macros and approved types for use in
@@ -12,12 +12,12 @@
 *  data the correct way.
 *
 *  Register Access macros and functions perform their operations on an
-*  input of type pointer to void.  The arguments passed to it should be
+*  input of the type pointer to void.  The arguments passed to it should be
 *  pointers to the type associated with the register size.
 *  (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -40,7 +40,7 @@
 
 #if defined( __ICCARM__ )
     /* Suppress warning for multiple volatile variables in an expression. */
-    /* This is common in component code and the usage is not order dependent. */
+    /* This is common in component code and usage is not order dependent. */
     #pragma diag_suppress=Pa082
 #endif  /* defined( __ICCARM__ ) */
 
@@ -61,28 +61,98 @@
 /*******************************************************************************
 * MEMBER encodes both the family and the detailed architecture
 *******************************************************************************/
-#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
 #ifdef CYDEV_CHIP_MEMBER_4D
-    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
 #else
-    #define CY_PSOC4D   (0u != 0u)
-    #define CY_PSOC4SF  (CY_PSOC4D)
+    #define CY_PSOC4_4000   (0u != 0u)
 #endif  /* CYDEV_CHIP_MEMBER_4D */
 
-#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
-#ifdef CYDEV_CHIP_MEMBER_5B
-    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#define CY_PSOC4_4100       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#define CY_PSOC4_4200       (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+
+#ifdef CYDEV_CHIP_MEMBER_4F
+    #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
+    #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
 #else
-    #define CY_PSOC5LP  (0u != 0u)
-#endif  /* CYDEV_CHIP_MEMBER_5B */
+    #define CY_PSOC4_4100BL (0u != 0u)
+    #define CY_PSOC4_4200BL (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_4F */
 
 
 /*******************************************************************************
-* UDB revisions
+* IP blocks
 *******************************************************************************/
-#define CY_UDB_V0 (CY_PSOC5A)
-#define CY_UDB_V1 (!CY_UDB_V0)
+#if (CY_PSOC4)
+
+    /* Using SRSSv2 or SRS-Lite */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_SRSSV2            (0u == 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #else
+        #define CY_IP_SRSSV2            (0u != 0u)
+        #define CY_IP_SRSSLT            (!CY_IP_SRSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (0u == 0u)
+    #else
+        #define CY_IP_CPUSSV2           (0u != 0u)
+        #define CY_IP_CPUSS             (!CY_IP_CPUSSV2)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Product uses FLASH-Lite or regular FLASH */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FMLT              (0u != 0u)          /* FLASH-Lite */
+        #define CY_IP_FM                (!CY_IP_FMLT)       /* Regular FLASH */
+    #else
+        #define CY_IP_FMLT              (-1u != 0u)
+        #define CY_IP_FM                (!CY_IP_FMLT)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of interrupt request inputs to CM0 */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_INT_NR            (32u)
+    #else
+        #define CY_IP_INT_NR            (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_FLASH_MACROS      (1u)
+    #else
+        #define CY_IP_FLASH_MACROS      (-1u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+
+    /* Number of Flash macros used in the device (0, 1 or 2) */
+    #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_BLESS             (0u != 0u)
+    #else
+        #define CY_IP_BLESS             (0u != 0u)
+    #endif  /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+    /* Watch Crystal Oscillator (WCO) is present (32kHz) */
+    #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)
+        #define CY_IP_WCO               (0u != 0u)
+    #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)
+        #define CY_IP_WCO               (0u == 0u)
+    #elif (CY_IP_SRSSV2)
+        #define CY_IP_WCO               (-1u)
+    #else
+        #define CY_IP_WCO               (0u != 0u)
+    #endif  /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+#endif  /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* The components version defines. Available started from cy_boot 4.20
+* Use the following construction in order to identify cy_boot version:
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)
+*******************************************************************************/
+#define CY_BOOT_4_20            (420u)
+#define CY_BOOT_VERSION         (CY_BOOT_4_20)
 
 
 /*******************************************************************************
@@ -104,7 +174,7 @@ typedef          float  float32;
 
 #endif  /* (!CY_PSOC3) */
 
-/* Signed or unsigned depending on the compiler selection */
+/* Signed or unsigned depending on compiler selection */
 typedef          char   char8;
 
 
@@ -154,7 +224,7 @@ typedef          char   char8;
 
 #else
 
-    /* Prototype for function to set a 24-bit register. Located at cyutils.c */
+    /* Prototype for function to set 24-bit register. Located at cyutils.c */
     extern void     CySetReg24(uint32 volatile * addr, uint32 value);
 
     #if(CY_PSOC4)
@@ -204,18 +274,39 @@ typedef          char   char8;
     #define XDATA
 
     #if defined(__ARMCC_VERSION)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit"), zero_init))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
+
+        /* Specifies a minimum alignment (in bytes) for variables of the
+        *  specified type.
+        */
         #define CY_ALIGN(align)     __align(align)
+
+
+        /* Attached to an enum, struct, or union type definition, specified that
+        *  the minimum required memory be used to represent the type.
+        */
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           __inline
     #elif defined (__GNUC__)
+
         #define CY_NOINIT           __attribute__ ((section(".noinit")))
         #define CY_NORETURN         __attribute__ ((noreturn))
         #define CY_SECTION(name)    __attribute__ ((section(name)))
         #define CY_ALIGN(align)     __attribute__ ((aligned(align)))
+        #define CY_PACKED
+        #define CY_PACKED_ATTR      __attribute__ ((packed))
+        #define CY_INLINE           inline
     #elif defined (__ICCARM__)
+
         #define CY_NOINIT           __no_init
         #define CY_NORETURN         __noreturn
+        #define CY_PACKED           __packed
+        #define CY_PACKED_ATTR
+        #define CY_INLINE           inline
     #endif  /* (__ARMCC_VERSION) */
 
 #endif  /* (CY_PSOC3) */
@@ -223,12 +314,12 @@ typedef          char   char8;
 
 #if(CY_PSOC3)
 
-    /* 8051 naturally returns an 8 bit value. */
+    /* 8051 naturally returns 8 bit value. */
     typedef unsigned char cystatus;
 
 #else
 
-    /* ARM naturally returns a 32 bit value. */
+    /* ARM naturally returns 32 bit value. */
     typedef unsigned long cystatus;
 
 #endif  /* (CY_PSOC3) */
@@ -274,7 +365,7 @@ typedef volatile uint32 CYXDATA reg32;
     * KEIL for the 8051 is a big endian compiler This causes problems as the on chip
     * registers are little endian.  Byte swapping for two and four byte registers is
     * implemented in the functions below.  This will require conditional compilation
-    * of function prototypes in code.
+    * of function prototypes in the code.
     *******************************************************************************/
 
     /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
@@ -347,24 +438,24 @@ typedef volatile uint32 CYXDATA reg32;
 *  Data manipulation defines
 *******************************************************************************/
 
-/* Get 8 bits of a 16 bit value. */
+/* Get 8 bits of 16 bit value. */
 #define LO8(x)                  ((uint8) ((x) & 0xFFu))
 #define HI8(x)                  ((uint8) ((uint16)(x) >> 8))
 
-/* Get 16 bits of a 32 bit value. */
+/* Get 16 bits of 32 bit value. */
 #define LO16(x)                 ((uint16) ((x) & 0xFFFFu))
 #define HI16(x)                 ((uint16) ((uint32)(x) >> 16))
 
-/* Swap the byte ordering of a 32 bit value */
+/* Swap the byte ordering of 32 bit value */
 #define CYSWAP_ENDIAN32(x)  \
         ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))
 
-/* Swap the byte ordering of a 16 bit value */
+/* Swap the byte ordering of 16 bit value */
 #define CYSWAP_ENDIAN16(x)      ((uint16)(((x) << 8) | ((x) >> 8)))
 
 
 /*******************************************************************************
-* Defines the standard return values used PSoC content. A function is
+* Defines the standard return values used in PSoC content. A function is
 * not limited to these return values but can use them when returning standard
 * error values. Return values can be overloaded if documented in the function
 * header. On the 8051 a function can use a larger return type but still use the
@@ -413,24 +504,55 @@ typedef volatile uint32 CYXDATA reg32;
 
 
 /*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+*    #ifdef <OBSOLETED_DEFINE>
+*        #undef  <OBSOLETED_DEFINE>
+*        #define <OBSOLETED_DEFINE>      (<New Value>)
+*    #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+*       used in the application and their modification might lead to unexpected
+*       consequences.
 *******************************************************************************/
+#define CY_UDB_V0           (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#define CY_UDB_V1           (!CY_UDB_V0)
+#define CY_PSOC4A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+    #define CY_PSOC4D   (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#else
+    #define CY_PSOC4D   (0u != 0u)
+    #define CY_PSOC4SF  (CY_PSOC4D)
+#endif  /* CYDEV_CHIP_MEMBER_4D */
+#define CY_PSOC5A  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#ifdef CYDEV_CHIP_MEMBER_5B
+    #define CY_PSOC5LP  (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#else
+    #define CY_PSOC5LP  (0u != 0u)
+#endif  /* CYDEV_CHIP_MEMBER_5B */
+
+#if (!CY_PSOC4)
+
+    /* Device is PSoC 3 and the revision is ES2 or earlier */
+    #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
 
-/* Device is PSoC 3 and the revision is ES2 or earlier */
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
+    /* Device is PSoC 3 and the revision is ES3 or later */
+    #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+        (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
 
-/* Device is PSoC 3 and the revision is ES3 or later */
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
-    (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
+    /* Device is PSoC 5 and the revision is ES1 or earlier */
+    #define CY_PSOC5_ES1 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES1 or earlier */
-#define CY_PSOC5_ES1 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
+    /* Device is PSoC 5 and the revision is ES2 or later */
+    #define CY_PSOC5_ES2 (CY_PSOC5A && \
+        (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
 
-/* Device is PSoC 5 and the revision is ES2 or later */
-#define CY_PSOC5_ES2 (CY_PSOC5A && \
-    (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
+#endif  /* (!CY_PSOC4) */
 
 #endif  /* CY_BOOT_CYTYPES_H */
 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c
index 6d42579a..dcfe346e 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c
@@ -1,12 +1,12 @@
 /*******************************************************************************
 * FILENAME: cyutils.c
-* Version 4.0
+* Version 4.20
 *
 *  Description:
-*   CyUtils provides function to handle 24-bit value writes.
+*   CyUtils provides a function to handle 24-bit value writes.
 *
 ********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation.  All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation.  All rights reserved.
 * You may use this file only in accordance with the license, terms, conditions,
 * disclaimers, and limitations in the end user license agreement accompanying
 * the software package with which this file was provided.
@@ -21,11 +21,11 @@
     ****************************************************************************
     *
     * Summary:
-    *  Writes the 24-bit value to the specified register.
+    *  Writes a 24-bit value to the specified register.
     *
     * Parameters:
-    *  addr : adress where data must be written
-    *  value: data that must be written
+    *  addr : the address where data must be written.
+    *  value: the data that must be written.
     *
     * Return:
     *  None
@@ -56,7 +56,7 @@
         *  Reads the 24-bit value from the specified register.
         *
         * Parameters:
-        *  addr : adress where data must be read
+        *  addr : the address where data must be read.
         *
         * Return:
         *  None
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h
index d3473436..c1a83bba 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h
@@ -1,6 +1,6 @@
 /*******************************************************************************
  * File Name: project.h
- * PSoC Creator 3.0 Component Pack 7
+ * PSoC Creator  3.1
  *
  *  Description:
  *  This file is automatically generated by PSoC Creator and should not 
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch
index 6abdb6b1..8d101927 100755
Binary files a/software/SCSI2SD/v4/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cycdx b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cycdx
index b11ceaf4..368476d2 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cycdx
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cycdx
@@ -4,17 +4,33 @@
   <block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="LED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
   <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
-    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
-    <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+    <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
     <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
       <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
       <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
@@ -47,7 +63,7 @@
     <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
     <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
     <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
-      <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />
+      <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
       <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
     </register>
     <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cydwr b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cydwr
index c4aab391..f30b9274 100755
Binary files a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cydwr and b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cydwr differ
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit
index 470a7b52..8d65665b 100644
Binary files a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyprj b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyprj
index be991fac..d91b719c 100755
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyprj
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyprj
@@ -947,14 +947,14 @@
 <GlobalPages />
 <GlobalTools name="Code Generation">
 <GlobalPages>
+<name_val_pair name="General@Application Type" v="Bootloader" />
+<name_val_pair name="General@Custom Code Gen Options" v="" />
+<name_val_pair name="General@Skip Code Generation" v="False" />
+<name_val_pair name="General@Custom Synthesis Options" v="" />
+<name_val_pair name="General@Quiet Output" v="True" />
 <name_val_pair name="General@Synthesis Goal" v="Speed" />
 <name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />
-<name_val_pair name="General@Quiet Output" v="True" />
-<name_val_pair name="General@Custom Synthesis Options" v="" />
-<name_val_pair name="General@Skip Code Generation" v="False" />
-<name_val_pair name="General@Custom Code Gen Options" v="" />
 <name_val_pair name="General@Virtual Node Substitution" v="3" />
-<name_val_pair name="General@Application Type" v="Bootloader" />
 <name_val_pair name="General@Custom Fitter Options" v="" />
 </GlobalPages>
 </GlobalTools>
@@ -965,9 +965,9 @@
 </GlobalTools>
 <GlobalTools name="Customizer">
 <GlobalPages>
-<name_val_pair name="General@Customizer Build Mode" v="Release" />
-<name_val_pair name="General@Command Line Options" v="" />
 <name_val_pair name="General@Assembly References" v="" />
+<name_val_pair name="General@Command Line Options" v="" />
+<name_val_pair name="General@Customizer Build Mode" v="Release" />
 </GlobalPages>
 </GlobalTools>
 </name>
@@ -975,133 +975,323 @@
 <platform>
 <name v="c9323d49-d323-40b8-9b59-cc008d68a989">
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Preprocessor Definitions" v="DEBUG" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Struct Return Method" v="System Default" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Verbose Asm" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
 <name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
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+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
+</name>
+</platform>
+<platform>
+<name v="fdb8e1ae-f83a-46cf-9446-1d703716f38a">
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
 </name>
 </platform>
 </platforms>
@@ -1110,18 +1300,9 @@
 <component_generation v="PSoC Creator  3.0" />
 <last_selected_tab v="Cypress" />
 <component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1)" />
-<WriteAppVersionLastSavedWith v="3.0.0.1539" />
-<WriteAppMarketingVersionLastSavedWith v=" 3.0 Component Pack 7" />
-<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" />
-<custom_data>
-<CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">
-<CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2">
-<userData />
-</CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997>
-<properties />
-</CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111>
-</custom_data>
-</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
+<WriteAppVersionLastSavedWith v="3.1.0.1570" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
 </CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
 <top_block v="TopDesign" />
 <selected_device v="CY8C5267AXI-LP051" />
@@ -1132,8 +1313,8 @@
 <CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
 <ignored_deps />
 </CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
-<boot_component v="cy_boot_v4_0" />
+<boot_component v="cy_boot_v4_20" />
 <BootloaderTag hexFile="" elfFile="" />
 <current_generation v="0" />
 </CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
-</CyXmlSerializer>
+</CyXmlSerializer>
\ No newline at end of file
diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.svd b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.svd
index 97ec4d4a..72130dcc 100644
--- a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.svd
+++ b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.svd
@@ -9,17 +9,17 @@
     <peripheral>
       <name>USBFS</name>
       <description>USBFS</description>
-      <baseAddress>0x40004394</baseAddress>
+      <baseAddress>0x0</baseAddress>
       <addressBlock>
         <offset>0</offset>
-        <size>0x1D0A</size>
+        <size>0x0</size>
         <usage>registers</usage>
       </addressBlock>
       <registers>
         <register>
           <name>USBFS_PM_USB_CR0</name>
           <description>USB Power Mode Control Register 0</description>
-          <addressOffset>0x0</addressOffset>
+          <addressOffset>0x40004394</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -51,7 +51,7 @@
         <register>
           <name>USBFS_PM_ACT_CFG</name>
           <description>Active Power Mode Configuration Register</description>
-          <addressOffset>0x11</addressOffset>
+          <addressOffset>0x400043A5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -60,7 +60,7 @@
         <register>
           <name>USBFS_PM_STBY_CFG</name>
           <description>Standby Power Mode Configuration Register</description>
-          <addressOffset>0x21</addressOffset>
+          <addressOffset>0x400043B5</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -69,7 +69,7 @@
         <register>
           <name>USBFS_PRT_PS</name>
           <description>Port Pin State Register</description>
-          <addressOffset>0xE5D</addressOffset>
+          <addressOffset>0x400051F1</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -94,7 +94,7 @@
         <register>
           <name>USBFS_PRT_DM0</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5E</addressOffset>
+          <addressOffset>0x400051F2</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -119,7 +119,7 @@
         <register>
           <name>USBFS_PRT_DM1</name>
           <description>Port Drive Mode Register</description>
-          <addressOffset>0xE5F</addressOffset>
+          <addressOffset>0x400051F3</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -144,7 +144,7 @@
         <register>
           <name>USBFS_PRT_INP_DIS</name>
           <description>Input buffer disable override</description>
-          <addressOffset>0xE64</addressOffset>
+          <addressOffset>0x400051F8</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -169,7 +169,7 @@
         <register>
           <name>USBFS_EP0_DR0</name>
           <description>bmRequestType</description>
-          <addressOffset>0x1C6C</addressOffset>
+          <addressOffset>0x40006000</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -178,7 +178,7 @@
         <register>
           <name>USBFS_EP0_DR1</name>
           <description>bRequest</description>
-          <addressOffset>0x1C6D</addressOffset>
+          <addressOffset>0x40006001</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -187,7 +187,7 @@
         <register>
           <name>USBFS_EP0_DR2</name>
           <description>wValueLo</description>
-          <addressOffset>0x1C6E</addressOffset>
+          <addressOffset>0x40006002</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -196,7 +196,7 @@
         <register>
           <name>USBFS_EP0_DR3</name>
           <description>wValueHi</description>
-          <addressOffset>0x1C6F</addressOffset>
+          <addressOffset>0x40006003</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -205,7 +205,7 @@
         <register>
           <name>USBFS_EP0_DR4</name>
           <description>wIndexLo</description>
-          <addressOffset>0x1C70</addressOffset>
+          <addressOffset>0x40006004</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -214,7 +214,7 @@
         <register>
           <name>USBFS_EP0_DR5</name>
           <description>wIndexHi</description>
-          <addressOffset>0x1C71</addressOffset>
+          <addressOffset>0x40006005</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -223,7 +223,7 @@
         <register>
           <name>USBFS_EP0_DR6</name>
           <description>lengthLo</description>
-          <addressOffset>0x1C72</addressOffset>
+          <addressOffset>0x40006006</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -232,7 +232,7 @@
         <register>
           <name>USBFS_EP0_DR7</name>
           <description>lengthHi</description>
-          <addressOffset>0x1C73</addressOffset>
+          <addressOffset>0x40006007</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -241,7 +241,7 @@
         <register>
           <name>USBFS_CR0</name>
           <description>USB Control Register 0</description>
-          <addressOffset>0x1C74</addressOffset>
+          <addressOffset>0x40006008</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -250,8 +250,8 @@
             <field>
               <name>device_address</name>
               <description>No description available</description>
-              <lsb>6</lsb>
-              <msb>0</msb>
+              <lsb>0</lsb>
+              <msb>6</msb>
               <access>read-only</access>
             </field>
             <field>
@@ -266,7 +266,7 @@
         <register>
           <name>USBFS_CR1</name>
           <description>USB Control Register 1</description>
-          <addressOffset>0x1C75</addressOffset>
+          <addressOffset>0x40006009</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -305,7 +305,7 @@
         <register>
           <name>USBFS_SIE_EP1_CR0</name>
           <description>The Endpoint1 Control Register</description>
-          <addressOffset>0x1C7A</addressOffset>
+          <addressOffset>0x4000600E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -314,7 +314,7 @@
         <register>
           <name>USBFS_USBIO_CR0</name>
           <description>USBIO Control Register 0</description>
-          <addressOffset>0x1C7C</addressOffset>
+          <addressOffset>0x40006010</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -353,7 +353,7 @@
         <register>
           <name>USBFS_USBIO_CR1</name>
           <description>USBIO Control Register 1</description>
-          <addressOffset>0x1C7E</addressOffset>
+          <addressOffset>0x40006012</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -392,7 +392,7 @@
         <register>
           <name>USBFS_SIE_EP2_CR0</name>
           <description>The Endpoint2 Control Register</description>
-          <addressOffset>0x1C8A</addressOffset>
+          <addressOffset>0x4000601E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -401,7 +401,7 @@
         <register>
           <name>USBFS_SIE_EP3_CR0</name>
           <description>The Endpoint3 Control Register</description>
-          <addressOffset>0x1C9A</addressOffset>
+          <addressOffset>0x4000602E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -410,7 +410,7 @@
         <register>
           <name>USBFS_SIE_EP4_CR0</name>
           <description>The Endpoint4 Control Register</description>
-          <addressOffset>0x1CAA</addressOffset>
+          <addressOffset>0x4000603E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -419,7 +419,7 @@
         <register>
           <name>USBFS_SIE_EP5_CR0</name>
           <description>The Endpoint5 Control Register</description>
-          <addressOffset>0x1CBA</addressOffset>
+          <addressOffset>0x4000604E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -428,7 +428,7 @@
         <register>
           <name>USBFS_SIE_EP6_CR0</name>
           <description>The Endpoint6 Control Register</description>
-          <addressOffset>0x1CCA</addressOffset>
+          <addressOffset>0x4000605E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -437,7 +437,7 @@
         <register>
           <name>USBFS_SIE_EP7_CR0</name>
           <description>The Endpoint7 Control Register</description>
-          <addressOffset>0x1CDA</addressOffset>
+          <addressOffset>0x4000606E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -446,7 +446,7 @@
         <register>
           <name>USBFS_SIE_EP8_CR0</name>
           <description>The Endpoint8 Control Register</description>
-          <addressOffset>0x1CEA</addressOffset>
+          <addressOffset>0x4000607E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -455,7 +455,7 @@
         <register>
           <name>USBFS_BUF_SIZE</name>
           <description>Dedicated Endpoint Buffer Size Register</description>
-          <addressOffset>0x1CF8</addressOffset>
+          <addressOffset>0x4000608C</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -464,7 +464,7 @@
         <register>
           <name>USBFS_EP_ACTIVE</name>
           <description>Endpoint Active Indication Register</description>
-          <addressOffset>0x1CFA</addressOffset>
+          <addressOffset>0x4000608E</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -473,7 +473,7 @@
         <register>
           <name>USBFS_EP_TYPE</name>
           <description>Endpoint Type (IN/OUT) Indication</description>
-          <addressOffset>0x1CFB</addressOffset>
+          <addressOffset>0x4000608F</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
@@ -482,7 +482,7 @@
         <register>
           <name>USBFS_USB_CLK_EN</name>
           <description>USB Block Clock Enable Register</description>
-          <addressOffset>0x1D09</addressOffset>
+          <addressOffset>0x4000609D</addressOffset>
           <size>8</size>
           <access>read-write</access>
           <resetValue>0</resetValue>
diff --git a/software/include/scsi2sd.h b/software/include/scsi2sd.h
index 2ca053ad..504fe799 100755
--- a/software/include/scsi2sd.h
+++ b/software/include/scsi2sd.h
@@ -166,7 +166,14 @@ typedef enum
 	// Command content:
 	// uint8_t CONFIG_REBOOT
 	// Response: None.
-	CONFIG_REBOOT
+	CONFIG_REBOOT,
+
+	// Command content:
+	// uint8_t CONFIG_INFO
+	// Response:
+	// uint8_t[16] CSD
+	// uint8_t[16] CID
+	CONFIG_SDINFO
 } CONFIG_COMMAND;
 
 typedef enum