From: Michael McMaster Date: Wed, 20 Jan 2021 09:46:16 +0000 (+1000) Subject: Invert logic of the nor flash HOLD pin X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=846bde57ddb7bb4da789943afabe30f5fd18ea6a;p=SCSI2SD.git Invert logic of the nor flash HOLD pin --- diff --git a/software/SCSI2SD/src/flash.c b/software/SCSI2SD/src/flash.c index 39affaa..fe493dc 100644 --- a/software/SCSI2SD/src/flash.c +++ b/software/SCSI2SD/src/flash.c @@ -102,6 +102,7 @@ static void spiFlash_init(S2S_Device* dev) CyDelayUs(1); nNOR_CS_Write(0); // Select + CyDelayCycles(4); // Tiny delay // JEDEC standard "Read Identification" command // returns CFI information diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 601f1b7..5f6e1cf 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -450,8 +450,8 @@ #define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL #define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL #define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -459,9 +459,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -485,8 +485,8 @@ #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -494,9 +494,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1 @@ -567,34 +567,34 @@ #define NOR_SCK__SLW CYREG_PRT3_SLW /* NOR_SPI */ -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_RxStsReg__4__POS 4 #define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u @@ -602,34 +602,34 @@ #define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u #define NOR_SPI_BSPIM_RxStsReg__6__POS 6 #define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u -#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0 -#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1 -#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK +#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL #define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u #define NOR_SPI_BSPIM_TxStsReg__0__POS 0 #define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u #define NOR_SPI_BSPIM_TxStsReg__1__POS 1 -#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u #define NOR_SPI_BSPIM_TxStsReg__2__POS 2 #define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u @@ -637,9 +637,9 @@ #define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_TxStsReg__4__POS 4 #define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu -#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB03_MSK +#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB03_ST /* SCSI_In */ #define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1 @@ -1760,15 +1760,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1781,35 +1781,35 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE @@ -2673,8 +2673,6 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2682,13 +2680,13 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST /* Debug_Timer */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2803,6 +2801,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2810,67 +2810,58 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index da9035b..0d852e5 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -149,7 +149,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 42u +#define CY_CFG_BASE_ADDR_COUNT 43u CYPACKED typedef struct { uint8 offset; @@ -410,44 +410,45 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x4001003Eu, /* Base address: 0x40010000 Count: 62 */ - 0x40010147u, /* Base address: 0x40010100 Count: 71 */ - 0x40010245u, /* Base address: 0x40010200 Count: 69 */ - 0x40010350u, /* Base address: 0x40010300 Count: 80 */ - 0x40010455u, /* Base address: 0x40010400 Count: 85 */ - 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */ - 0x4001066Bu, /* Base address: 0x40010600 Count: 107 */ - 0x40010757u, /* Base address: 0x40010700 Count: 87 */ - 0x4001084Au, /* Base address: 0x40010800 Count: 74 */ - 0x40010952u, /* Base address: 0x40010900 Count: 82 */ - 0x40010A52u, /* Base address: 0x40010A00 Count: 82 */ + 0x40010041u, /* Base address: 0x40010000 Count: 65 */ + 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */ + 0x4001024Du, /* Base address: 0x40010200 Count: 77 */ + 0x40010348u, /* Base address: 0x40010300 Count: 72 */ + 0x40010418u, /* Base address: 0x40010400 Count: 24 */ + 0x40010556u, /* Base address: 0x40010500 Count: 86 */ + 0x4001064Fu, /* Base address: 0x40010600 Count: 79 */ + 0x40010751u, /* Base address: 0x40010700 Count: 81 */ + 0x40010848u, /* Base address: 0x40010800 Count: 72 */ + 0x40010955u, /* Base address: 0x40010900 Count: 85 */ + 0x40010A5Fu, /* Base address: 0x40010A00 Count: 95 */ 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */ - 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ - 0x40010D57u, /* Base address: 0x40010D00 Count: 87 */ - 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */ - 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ - 0x4001141Cu, /* Base address: 0x40011400 Count: 28 */ - 0x4001155Cu, /* Base address: 0x40011500 Count: 92 */ - 0x40011653u, /* Base address: 0x40011600 Count: 83 */ - 0x40011755u, /* Base address: 0x40011700 Count: 85 */ - 0x40011857u, /* Base address: 0x40011800 Count: 87 */ - 0x4001194Cu, /* Base address: 0x40011900 Count: 76 */ - 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */ - 0x4001401Du, /* Base address: 0x40014000 Count: 29 */ - 0x40014121u, /* Base address: 0x40014100 Count: 33 */ - 0x40014215u, /* Base address: 0x40014200 Count: 21 */ - 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ - 0x40014410u, /* Base address: 0x40014400 Count: 16 */ - 0x40014519u, /* Base address: 0x40014500 Count: 25 */ - 0x40014614u, /* Base address: 0x40014600 Count: 20 */ - 0x40014715u, /* Base address: 0x40014700 Count: 21 */ - 0x4001480Du, /* Base address: 0x40014800 Count: 13 */ - 0x40014913u, /* Base address: 0x40014900 Count: 19 */ - 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */ - 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */ + 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */ + 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */ + 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */ + 0x40010F37u, /* Base address: 0x40010F00 Count: 55 */ + 0x4001141Au, /* Base address: 0x40011400 Count: 26 */ + 0x40011553u, /* Base address: 0x40011500 Count: 83 */ + 0x40011656u, /* Base address: 0x40011600 Count: 86 */ + 0x40011753u, /* Base address: 0x40011700 Count: 83 */ + 0x4001184Bu, /* Base address: 0x40011800 Count: 75 */ + 0x40011954u, /* Base address: 0x40011900 Count: 84 */ + 0x40011A47u, /* Base address: 0x40011A00 Count: 71 */ + 0x40011B52u, /* Base address: 0x40011B00 Count: 82 */ + 0x4001401Au, /* Base address: 0x40014000 Count: 26 */ + 0x40014125u, /* Base address: 0x40014100 Count: 37 */ + 0x40014212u, /* Base address: 0x40014200 Count: 18 */ + 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */ + 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */ + 0x4001451Du, /* Base address: 0x40014500 Count: 29 */ + 0x40014611u, /* Base address: 0x40014600 Count: 17 */ + 0x40014716u, /* Base address: 0x40014700 Count: 22 */ + 0x4001480Fu, /* Base address: 0x40014800 Count: 15 */ + 0x4001491Au, /* Base address: 0x40014900 Count: 26 */ + 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */ + 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */ 0x40015005u, /* Base address: 0x40015000 Count: 5 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -455,55 +456,63 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x30u}, - {0x0Au, 0x27u}, + {0x0Au, 0x36u}, {0x01u, 0x22u}, - {0x10u, 0x0Au}, - {0x11u, 0x88u}, - {0x18u, 0x8Au}, + {0x10u, 0xA8u}, + {0x11u, 0x2Au}, + {0x18u, 0x84u}, {0x19u, 0x82u}, {0x1Cu, 0x08u}, - {0x20u, 0x01u}, + {0x20u, 0x02u}, {0x21u, 0x03u}, - {0x31u, 0x80u}, + {0x30u, 0x84u}, + {0x60u, 0x02u}, {0x78u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x86u, 0x0Fu}, {0x84u, 0x0Fu}, - {0x01u, 0x08u}, - {0x03u, 0x10u}, - {0x06u, 0x24u}, - {0x07u, 0x03u}, - {0x0Bu, 0x84u}, - {0x0Cu, 0x24u}, - {0x0Eu, 0x12u}, - {0x0Fu, 0x80u}, - {0x12u, 0x18u}, + {0x84u, 0x0Fu}, + {0x01u, 0x6Du}, + {0x02u, 0x20u}, + {0x05u, 0x12u}, + {0x06u, 0x03u}, + {0x07u, 0xE8u}, + {0x09u, 0x0Du}, + {0x0Bu, 0x60u}, + {0x0Du, 0x6Du}, + {0x11u, 0x71u}, + {0x12u, 0x24u}, + {0x13u, 0x82u}, {0x14u, 0x24u}, + {0x15u, 0x02u}, {0x16u, 0x09u}, - {0x19u, 0x08u}, - {0x1Au, 0x03u}, - {0x1Bu, 0x60u}, - {0x1Fu, 0x04u}, - {0x21u, 0x10u}, - {0x22u, 0x20u}, - {0x29u, 0x84u}, - {0x2Au, 0x04u}, - {0x2Bu, 0x21u}, - {0x2Du, 0x84u}, - {0x2Fu, 0x42u}, - {0x30u, 0x38u}, - {0x33u, 0x07u}, + {0x17u, 0x0Du}, + {0x19u, 0x92u}, + {0x1Bu, 0x64u}, + {0x1Du, 0x20u}, + {0x1Eu, 0x18u}, + {0x21u, 0x40u}, + {0x22u, 0x04u}, + {0x24u, 0x24u}, + {0x26u, 0x12u}, + {0x28u, 0x40u}, + {0x29u, 0x2Du}, + {0x2Bu, 0x40u}, + {0x2Du, 0x6Du}, + {0x30u, 0x40u}, + {0x33u, 0x0Fu}, {0x34u, 0x07u}, - {0x35u, 0xE0u}, - {0x37u, 0x18u}, - {0x3Fu, 0x40u}, - {0x40u, 0x63u}, + {0x35u, 0xF0u}, + {0x36u, 0x38u}, + {0x39u, 0x20u}, + {0x3Bu, 0x08u}, + {0x3Eu, 0x01u}, + {0x40u, 0x13u}, {0x41u, 0x02u}, - {0x42u, 0x10u}, - {0x45u, 0xECu}, - {0x46u, 0x2Du}, - {0x47u, 0x0Fu}, + {0x42u, 0x60u}, + {0x45u, 0x2Cu}, + {0x46u, 0xFDu}, + {0x47u, 0x0Eu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -514,7 +523,7 @@ void cyfitter_cfg(void) {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x22u}, + {0x5Cu, 0x02u}, {0x5Du, 0x02u}, {0x5Fu, 0x01u}, {0x60u, 0x08u}, @@ -523,659 +532,558 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x88u, 0x02u}, - {0xA4u, 0x01u}, - {0xB0u, 0x01u}, - {0xB4u, 0x02u}, - {0xBEu, 0x01u}, - {0xD8u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x09u}, + {0xADu, 0x01u}, + {0xB3u, 0x01u}, + {0xBFu, 0x04u}, + {0xD9u, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x80u}, - {0x05u, 0x10u}, - {0x07u, 0x04u}, - {0x08u, 0x08u}, - {0x0Au, 0x44u}, + {0x00u, 0x06u}, + {0x08u, 0x0Au}, + {0x0Au, 0x01u}, {0x10u, 0x80u}, - {0x11u, 0x10u}, - {0x16u, 0x10u}, - {0x1Au, 0xC4u}, - {0x1Cu, 0x04u}, - {0x1Fu, 0x01u}, - {0x21u, 0x44u}, - {0x22u, 0x10u}, - {0x28u, 0x08u}, - {0x29u, 0x80u}, - {0x2Au, 0x01u}, - {0x32u, 0x10u}, - {0x33u, 0x40u}, - {0x35u, 0x40u}, - {0x36u, 0x40u}, - {0x38u, 0x02u}, - {0x39u, 0x48u}, - {0x3Bu, 0x10u}, - {0x40u, 0x08u}, - {0x41u, 0x10u}, - {0x42u, 0x21u}, - {0x48u, 0x14u}, - {0x49u, 0x04u}, - {0x4Au, 0x40u}, - {0x4Bu, 0x10u}, - {0x50u, 0x20u}, - {0x51u, 0xA0u}, - {0x52u, 0x80u}, - {0x53u, 0x04u}, - {0x58u, 0x42u}, - {0x5Bu, 0x28u}, - {0x60u, 0x20u}, - {0x62u, 0x20u}, - {0x63u, 0x81u}, - {0x65u, 0x20u}, - {0x67u, 0x08u}, - {0x69u, 0x50u}, - {0x6Au, 0x08u}, - {0x6Bu, 0x40u}, - {0x6Cu, 0x01u}, - {0x6Fu, 0x02u}, + {0x11u, 0x28u}, + {0x18u, 0x04u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x81u}, + {0x20u, 0x08u}, + {0x21u, 0x20u}, + {0x22u, 0x14u}, + {0x23u, 0x04u}, + {0x24u, 0x20u}, + {0x29u, 0x42u}, + {0x2Au, 0x10u}, + {0x2Fu, 0x02u}, + {0x31u, 0x22u}, + {0x32u, 0x44u}, + {0x39u, 0x61u}, + {0x3Au, 0x04u}, + {0x40u, 0x0Au}, + {0x41u, 0x04u}, + {0x49u, 0x20u}, + {0x4Au, 0x90u}, + {0x4Bu, 0x02u}, + {0x51u, 0x80u}, + {0x52u, 0x48u}, + {0x53u, 0x20u}, + {0x58u, 0x04u}, + {0x59u, 0x01u}, + {0x5Au, 0x40u}, + {0x5Bu, 0x10u}, + {0x61u, 0x18u}, + {0x62u, 0x02u}, + {0x63u, 0x01u}, + {0x68u, 0x01u}, + {0x69u, 0x14u}, + {0x6Bu, 0x80u}, {0x70u, 0x80u}, - {0x71u, 0x08u}, - {0x72u, 0x08u}, - {0x73u, 0x40u}, - {0x80u, 0x04u}, - {0x81u, 0x18u}, - {0x84u, 0x60u}, - {0x87u, 0x40u}, - {0x88u, 0x20u}, - {0x8Au, 0x08u}, - {0x8Bu, 0x20u}, - {0xC0u, 0x45u}, - {0xC2u, 0x0Eu}, - {0xC4u, 0x2Au}, - {0xCAu, 0x0Du}, - {0xCCu, 0x0Cu}, + {0x72u, 0x04u}, + {0x73u, 0x50u}, + {0x81u, 0x90u}, + {0x82u, 0x08u}, + {0x83u, 0x80u}, + {0x86u, 0x02u}, + {0x87u, 0x22u}, + {0x8Au, 0x10u}, + {0x8Du, 0x14u}, + {0x8Eu, 0x01u}, + {0xC0u, 0x0Cu}, + {0xC2u, 0x0Du}, + {0xC4u, 0x0Eu}, + {0xCAu, 0x1Du}, + {0xCCu, 0x0Fu}, {0xCEu, 0x0Fu}, {0xD0u, 0x0Eu}, {0xD2u, 0x04u}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE0u, 0x03u}, - {0xE4u, 0x06u}, - {0xE6u, 0x08u}, - {0x08u, 0x02u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x01u}, - {0x10u, 0x01u}, - {0x11u, 0x02u}, - {0x13u, 0x11u}, - {0x15u, 0x01u}, + {0xE0u, 0x05u}, + {0xE2u, 0x0Au}, + {0xE4u, 0x09u}, + {0xE6u, 0x04u}, + {0x05u, 0x02u}, + {0x0Fu, 0x02u}, + {0x14u, 0x02u}, + {0x16u, 0x05u}, {0x17u, 0x02u}, - {0x19u, 0x02u}, - {0x1Bu, 0x05u}, + {0x18u, 0x02u}, + {0x1Au, 0x09u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x01u}, {0x20u, 0x02u}, - {0x2Du, 0x02u}, - {0x2Fu, 0x09u}, - {0x31u, 0x10u}, - {0x33u, 0x08u}, - {0x34u, 0x01u}, - {0x35u, 0x03u}, - {0x36u, 0x02u}, - {0x37u, 0x04u}, - {0x38u, 0x80u}, - {0x3Bu, 0x20u}, - {0x3Eu, 0x10u}, + {0x22u, 0x11u}, + {0x2Cu, 0x01u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x02u}, + {0x30u, 0x03u}, + {0x31u, 0x02u}, + {0x32u, 0x10u}, + {0x34u, 0x04u}, + {0x36u, 0x08u}, + {0x37u, 0x01u}, + {0x3Au, 0x02u}, + {0x3Fu, 0x01u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x20u}, + {0x5Cu, 0x92u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x04u}, {0x81u, 0x28u}, - {0x82u, 0x10u}, - {0x83u, 0x04u}, - {0x84u, 0x2Bu}, - {0x85u, 0x12u}, - {0x86u, 0x14u}, - {0x87u, 0x01u}, - {0x88u, 0x43u}, - {0x8Au, 0x0Cu}, - {0x8Cu, 0x28u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x17u}, - {0x8Fu, 0x08u}, - {0x91u, 0x13u}, - {0x93u, 0x2Cu}, - {0x94u, 0x0Du}, - {0x96u, 0x12u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x20u}, - {0x9Fu, 0x02u}, - {0xA0u, 0x02u}, - {0xAAu, 0x17u}, - {0xB0u, 0x40u}, - {0xB1u, 0x0Fu}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x30u}, - {0xB5u, 0x40u}, - {0xB6u, 0x30u}, - {0xBAu, 0x88u}, - {0xBEu, 0x01u}, + {0x85u, 0x28u}, + {0x86u, 0xFFu}, + {0x88u, 0xC0u}, + {0x89u, 0x28u}, + {0x8Au, 0x08u}, + {0x8Cu, 0x1Fu}, + {0x8Eu, 0x20u}, + {0x8Fu, 0x28u}, + {0x90u, 0x80u}, + {0x93u, 0x20u}, + {0x95u, 0x05u}, + {0x96u, 0x9Fu}, + {0x97u, 0x02u}, + {0x99u, 0x03u}, + {0x9Au, 0x60u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0xC0u}, + {0x9Du, 0x04u}, + {0x9Eu, 0x01u}, + {0x9Fu, 0x03u}, + {0xA0u, 0xC0u}, + {0xA1u, 0x28u}, + {0xA2u, 0x02u}, + {0xA4u, 0xC0u}, + {0xA5u, 0x10u}, + {0xA6u, 0x04u}, + {0xA8u, 0x7Fu}, + {0xA9u, 0x10u}, + {0xAAu, 0x80u}, + {0xACu, 0x90u}, + {0xADu, 0x01u}, + {0xAEu, 0x40u}, + {0xAFu, 0x06u}, + {0xB1u, 0x08u}, + {0xB2u, 0xFFu}, + {0xB3u, 0x20u}, + {0xB5u, 0x10u}, + {0xB7u, 0x07u}, + {0xB9u, 0x20u}, + {0xBBu, 0x80u}, + {0xBEu, 0x04u}, {0xBFu, 0x05u}, + {0xD4u, 0x09u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x22u}, {0xDFu, 0x01u}, - {0x00u, 0x89u}, - {0x03u, 0x08u}, - {0x04u, 0x20u}, - {0x09u, 0x24u}, - {0x0Au, 0x01u}, - {0x0Fu, 0x40u}, - {0x12u, 0x88u}, - {0x15u, 0x40u}, - {0x16u, 0x01u}, - {0x17u, 0x02u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x09u}, - {0x1Cu, 0x02u}, - {0x1Fu, 0x20u}, - {0x20u, 0x14u}, - {0x21u, 0x01u}, - {0x24u, 0x40u}, - {0x27u, 0x15u}, - {0x2Fu, 0x01u}, - {0x30u, 0x80u}, - {0x32u, 0x50u}, - {0x33u, 0x02u}, - {0x37u, 0x15u}, - {0x38u, 0x80u}, - {0x39u, 0x09u}, - {0x3Cu, 0x40u}, - {0x59u, 0x64u}, + {0x00u, 0x88u}, + {0x03u, 0x04u}, + {0x09u, 0x20u}, + {0x0Au, 0x81u}, + {0x0Bu, 0x20u}, + {0x0Eu, 0x2Au}, + {0x10u, 0x20u}, + {0x11u, 0x41u}, + {0x12u, 0x18u}, + {0x14u, 0x01u}, + {0x16u, 0x80u}, + {0x1Bu, 0x04u}, + {0x1Eu, 0x2Au}, + {0x1Fu, 0x02u}, + {0x20u, 0x20u}, + {0x21u, 0x20u}, + {0x22u, 0x83u}, + {0x27u, 0x41u}, + {0x29u, 0x80u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x14u}, + {0x2Cu, 0x01u}, + {0x2Fu, 0x02u}, + {0x30u, 0x02u}, + {0x32u, 0x98u}, + {0x36u, 0x08u}, + {0x39u, 0x69u}, + {0x3Cu, 0x80u}, + {0x3Fu, 0x04u}, + {0x59u, 0x14u}, {0x5Au, 0x02u}, - {0x5Du, 0x80u}, - {0x5Fu, 0x10u}, - {0x62u, 0x40u}, - {0x64u, 0x04u}, - {0x67u, 0x02u}, - {0x68u, 0x10u}, - {0x69u, 0x51u}, - {0x70u, 0x40u}, - {0x71u, 0x10u}, - {0x72u, 0x62u}, - {0x82u, 0x20u}, - {0x84u, 0x10u}, - {0x86u, 0x04u}, - {0x8Au, 0x40u}, - {0x8Du, 0x10u}, - {0x8Eu, 0x40u}, - {0x90u, 0x02u}, - {0x91u, 0x88u}, - {0x92u, 0x86u}, - {0x95u, 0x20u}, - {0x96u, 0x01u}, + {0x5Bu, 0x40u}, + {0x5Cu, 0x80u}, + {0x61u, 0x80u}, + {0x66u, 0x80u}, + {0x83u, 0x01u}, + {0x87u, 0x01u}, + {0x8Bu, 0x01u}, + {0x8Cu, 0x04u}, + {0x90u, 0x04u}, + {0x91u, 0x14u}, + {0x92u, 0x24u}, + {0x93u, 0x06u}, + {0x95u, 0x61u}, + {0x96u, 0xC0u}, {0x97u, 0x01u}, - {0x99u, 0x64u}, + {0x9Au, 0x41u}, + {0x9Cu, 0x0Eu}, + {0x9Du, 0x63u}, + {0x9Eu, 0x14u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x04u}, + {0xA1u, 0x04u}, + {0xA3u, 0x81u}, + {0xA5u, 0x0Au}, + {0xA8u, 0x10u}, + {0xADu, 0x04u}, + {0xB2u, 0x80u}, + {0xB3u, 0x50u}, + {0xB5u, 0x20u}, + {0xB7u, 0x20u}, + {0xC0u, 0x07u}, + {0xC2u, 0xEFu}, + {0xC4u, 0x9Fu}, + {0xCAu, 0x1Fu}, + {0xCCu, 0x4Fu}, + {0xCEu, 0x5Fu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x18u}, + {0xE2u, 0x85u}, + {0xE6u, 0x20u}, + {0xEAu, 0x48u}, + {0x80u, 0x04u}, + {0x82u, 0x02u}, + {0x94u, 0x04u}, + {0x96u, 0x0Au}, + {0x98u, 0x04u}, + {0x99u, 0x01u}, + {0x9Au, 0x12u}, {0x9Cu, 0x02u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0x0Cu}, + {0x9Eu, 0x04u}, + {0xA0u, 0x04u}, + {0xA2u, 0x03u}, + {0xB0u, 0x10u}, + {0xB2u, 0x01u}, + {0xB4u, 0x08u}, + {0xB6u, 0x06u}, + {0xB7u, 0x01u}, + {0xBAu, 0x80u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x92u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x98u}, + {0x01u, 0x80u}, + {0x05u, 0x01u}, + {0x09u, 0x20u}, + {0x0Au, 0x81u}, + {0x0Bu, 0x20u}, + {0x0Eu, 0x2Au}, + {0x10u, 0x20u}, + {0x11u, 0x41u}, + {0x12u, 0x0Cu}, + {0x16u, 0x80u}, + {0x18u, 0x10u}, + {0x1Bu, 0x10u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x2Au}, + {0x22u, 0x14u}, + {0x27u, 0x02u}, + {0x28u, 0x08u}, + {0x32u, 0x14u}, + {0x37u, 0x20u}, + {0x39u, 0x14u}, + {0x3Au, 0x01u}, + {0x3Bu, 0x40u}, + {0x40u, 0x04u}, + {0x41u, 0x02u}, + {0x43u, 0x08u}, + {0x48u, 0x04u}, + {0x49u, 0x06u}, + {0x4Au, 0x02u}, + {0x50u, 0x02u}, + {0x53u, 0x52u}, + {0x5Cu, 0x80u}, + {0x62u, 0x80u}, + {0x66u, 0x80u}, + {0x68u, 0x20u}, + {0x69u, 0x69u}, + {0x6Bu, 0x04u}, + {0x71u, 0x40u}, + {0x72u, 0x03u}, + {0x80u, 0x10u}, + {0x83u, 0x10u}, + {0x84u, 0x04u}, + {0x88u, 0x80u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x02u}, + {0x91u, 0x14u}, + {0x93u, 0x46u}, + {0x95u, 0x69u}, + {0x96u, 0xC1u}, + {0x97u, 0x20u}, + {0x98u, 0x01u}, + {0x9Au, 0x41u}, + {0x9Cu, 0x0Cu}, + {0x9Du, 0xE6u}, + {0x9Eu, 0x06u}, + {0x9Fu, 0x14u}, + {0xA0u, 0x04u}, {0xA1u, 0x24u}, - {0xA2u, 0x80u}, - {0xA3u, 0x02u}, - {0xA4u, 0x04u}, - {0xA6u, 0x20u}, - {0xA7u, 0x40u}, - {0xA9u, 0xA4u}, + {0xA2u, 0x82u}, + {0xA4u, 0x62u}, + {0xA5u, 0x0Au}, + {0xA6u, 0x28u}, + {0xA7u, 0x10u}, + {0xA9u, 0x93u}, {0xAAu, 0x20u}, - {0xACu, 0x10u}, - {0xAEu, 0x40u}, - {0xB1u, 0x80u}, - {0xB2u, 0x15u}, - {0xB5u, 0x40u}, - {0xB7u, 0x01u}, - {0xC0u, 0x4Fu}, - {0xC2u, 0x17u}, - {0xC4u, 0x1Au}, - {0xCAu, 0x10u}, - {0xCCu, 0xEDu}, - {0xCEu, 0x1Bu}, - {0xD6u, 0x3Fu}, - {0xD8u, 0x38u}, - {0xE0u, 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0x50u}, + {0xB0u, 0x48u}, + {0xB1u, 0x08u}, + {0xB3u, 0x02u}, + {0xC0u, 0xE9u}, + {0xC2u, 0xDFu}, + {0xC4u, 0xDFu}, + {0xCAu, 0x0Cu}, + {0xCCu, 0xE7u}, + {0xCEu, 0x3Au}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x19u}, + {0xE2u, 0x04u}, + {0xE4u, 0x40u}, + {0xE8u, 0x0Cu}, + {0xEAu, 0x01u}, + {0xECu, 0x02u}, + {0xEEu, 0x01u}, + {0x00u, 0x11u}, + {0x02u, 0x22u}, + {0x03u, 0x0Cu}, + {0x06u, 0xFFu}, + {0x07u, 0x10u}, + {0x08u, 0x0Fu}, + {0x09u, 0x01u}, + {0x0Au, 0xF0u}, + {0x0Cu, 0x21u}, + {0x0Eu, 0x12u}, + {0x0Fu, 0x10u}, + {0x12u, 0xFFu}, + {0x13u, 0x02u}, + {0x14u, 0x84u}, + {0x15u, 0x10u}, + {0x16u, 0x48u}, + {0x17u, 0x08u}, + {0x18u, 0xFFu}, + {0x19u, 0x01u}, + {0x20u, 0x33u}, + {0x22u, 0xCCu}, + {0x24u, 0x44u}, + {0x25u, 0x01u}, + {0x26u, 0x88u}, {0x29u, 0x10u}, - {0x2Au, 0x44u}, - {0x30u, 0x22u}, - {0x33u, 0x48u}, - {0x39u, 0x52u}, - {0x3Cu, 0x20u}, + {0x2Bu, 0x04u}, + {0x2Du, 0x01u}, + {0x31u, 0x1Cu}, + {0x32u, 0xFFu}, + {0x33u, 0x02u}, + {0x35u, 0x01u}, + {0x3Eu, 0x04u}, {0x3Fu, 0x10u}, - {0x45u, 0x2Au}, - {0x48u, 0x03u}, - {0x4Du, 0x02u}, - {0x4Eu, 0x02u}, - {0x4Fu, 0x14u}, - {0x55u, 0x04u}, - {0x56u, 0xA8u}, - {0x67u, 0x20u}, - {0x6Du, 0xA1u}, - {0x6Eu, 0x01u}, - {0x6Fu, 0x15u}, - {0x75u, 0x80u}, - {0x76u, 0x01u}, - {0x77u, 0x02u}, - {0x8Du, 0x40u}, - {0x90u, 0x02u}, - {0x91u, 0x80u}, - {0x94u, 0x10u}, - {0x95u, 0x01u}, - {0x96u, 0x41u}, - {0x97u, 0x0Cu}, - {0x98u, 0x08u}, - {0x9Au, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x81u}, - {0x9Eu, 0x99u}, - {0x9Fu, 0x15u}, - {0xA0u, 0x80u}, - {0xA1u, 0x28u}, - {0xA2u, 0x04u}, - {0xA4u, 0x10u}, - {0xA5u, 0x54u}, - {0xA6u, 0x81u}, - {0xA7u, 0x10u}, - {0xAAu, 0x80u}, - {0xABu, 0x20u}, - {0xACu, 0x44u}, - {0xADu, 0x10u}, - {0xAFu, 0x08u}, - {0xB2u, 0x08u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xFBu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0x0Fu}, - {0xCCu, 0x0Fu}, - {0xCEu, 0x0Du}, - {0xD0u, 0xE0u}, - {0xD2u, 0x30u}, - {0xD8u, 0x40u}, - {0xE0u, 0x02u}, - {0xE2u, 0x08u}, - {0xE8u, 0x80u}, - {0xEAu, 0x0Au}, - {0xEEu, 0x02u}, - {0x00u, 0x02u}, - {0x02u, 0x01u}, - {0x05u, 0xFFu}, - {0x09u, 0x55u}, - {0x0Bu, 0xAAu}, - {0x0Cu, 0x02u}, - {0x0Eu, 0x11u}, - {0x0Fu, 0xFFu}, - {0x11u, 0x69u}, - {0x13u, 0x96u}, - {0x14u, 0x02u}, - {0x16u, 0x09u}, - {0x18u, 0x02u}, - {0x1Au, 0x05u}, - {0x1Cu, 0x01u}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0x02u}, - {0x1Fu, 0xF0u}, - {0x23u, 0xFFu}, - {0x25u, 0xFFu}, - {0x2Bu, 0xFFu}, - {0x2Du, 0x33u}, - {0x2Fu, 0xCCu}, - {0x30u, 0x04u}, - {0x31u, 0xFFu}, - {0x32u, 0x10u}, - {0x34u, 0x08u}, - {0x36u, 0x03u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x02u}, - {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x22u}, - {0x5Du, 0x90u}, + {0x5Cu, 0x20u}, {0x5Fu, 0x01u}, - {0x80u, 0x0Fu}, - {0x81u, 0x96u}, - {0x82u, 0xF0u}, - {0x83u, 0x69u}, - {0x84u, 0xFFu}, - {0x85u, 0xFFu}, - {0x89u, 0xFFu}, - {0x8Au, 0xFFu}, - {0x8Fu, 0xFFu}, - {0x92u, 0xFFu}, - {0x93u, 0xFFu}, - {0x94u, 0x55u}, - {0x96u, 0xAAu}, - {0x97u, 0xFFu}, - {0x98u, 0x33u}, - {0x99u, 0x55u}, - {0x9Au, 0xCCu}, - {0x9Bu, 0xAAu}, - {0x9Du, 0x0Fu}, - {0x9Eu, 0xFFu}, - {0x9Fu, 0xF0u}, - {0xA4u, 0xFFu}, - {0xACu, 0x69u}, - {0xADu, 0x33u}, - {0xAEu, 0x96u}, - {0xAFu, 0xCCu}, - {0xB6u, 0xFFu}, - {0xB7u, 0xFFu}, - {0xBAu, 0x80u}, - {0xBBu, 0x80u}, + {0x80u, 0x01u}, + {0x82u, 0x02u}, + {0x84u, 0x04u}, + {0x86u, 0x09u}, + {0x89u, 0x01u}, + {0x8Cu, 0x08u}, + {0x8Du, 0x01u}, + {0x8Eu, 0x04u}, + {0x8Fu, 0x02u}, + {0x91u, 0x02u}, + {0x98u, 0x08u}, + {0x9Au, 0x04u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x08u}, + {0xA2u, 0x16u}, + {0xA3u, 0x04u}, + {0xAFu, 0x08u}, + {0xB0u, 0x10u}, + {0xB1u, 0x08u}, + {0xB3u, 0x04u}, + {0xB4u, 0x0Cu}, + {0xB6u, 0x03u}, + {0xB7u, 0x03u}, + {0xBAu, 0x20u}, + {0xBEu, 0x40u}, + {0xBFu, 0x40u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -1183,1038 +1091,1172 @@ void cyfitter_cfg(void) {0xDCu, 0x22u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x08u}, - {0x03u, 0x88u}, - {0x05u, 0x81u}, - {0x09u, 0x60u}, - {0x0Bu, 0x90u}, - {0x0Eu, 0x29u}, - {0x11u, 0x08u}, - {0x12u, 0x02u}, - {0x18u, 0x02u}, - {0x1Bu, 0x80u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x29u}, - {0x21u, 0x40u}, - {0x22u, 0x40u}, - {0x26u, 0x01u}, - {0x27u, 0x40u}, + {0x00u, 0x02u}, + {0x03u, 0x22u}, + {0x04u, 0x02u}, + {0x05u, 0x28u}, + {0x06u, 0x02u}, + {0x08u, 0x40u}, + {0x0Au, 0x0Au}, + {0x0Eu, 0x80u}, + {0x0Fu, 0x28u}, + {0x13u, 0x01u}, + {0x15u, 0x04u}, + {0x17u, 0x01u}, + {0x1Au, 0x01u}, + {0x1Bu, 0xA3u}, + {0x1Cu, 0x20u}, + {0x22u, 0x85u}, + {0x25u, 0x01u}, + {0x27u, 0x14u}, + {0x28u, 0x40u}, {0x2Bu, 0x01u}, - {0x2Du, 0x08u}, - {0x2Eu, 0x80u}, - {0x2Fu, 0x48u}, - {0x30u, 0x01u}, - {0x32u, 0x60u}, - {0x33u, 0x08u}, - {0x34u, 0x02u}, - {0x37u, 0x40u}, - {0x38u, 0x24u}, - {0x3Bu, 0x81u}, - {0x3Du, 0x88u}, - {0x3Eu, 0x20u}, - {0x58u, 0x50u}, - {0x5Bu, 0x09u}, - {0x5Fu, 0x80u}, - {0x62u, 0x2Au}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x14u}, + {0x30u, 0x02u}, + {0x36u, 0x09u}, + {0x37u, 0x20u}, + {0x39u, 0x50u}, + {0x3Cu, 0x28u}, + {0x3Du, 0x82u}, + {0x58u, 0x24u}, + {0x5Au, 0x80u}, + {0x5Bu, 0x02u}, + {0x5Du, 0x08u}, + {0x5Eu, 0x08u}, + {0x60u, 0x84u}, + {0x61u, 0x04u}, + {0x62u, 0x01u}, {0x63u, 0x11u}, - {0x65u, 0x80u}, - {0x84u, 0x10u}, - {0x87u, 0x80u}, - {0x8Bu, 0x01u}, - {0x8Du, 0x02u}, - {0x90u, 0x64u}, - {0x91u, 0x41u}, - {0x92u, 0x02u}, - {0x93u, 0xC8u}, - {0x94u, 0x02u}, - {0x95u, 0x80u}, + {0x68u, 0x01u}, + {0x6Du, 0x40u}, + {0x6Fu, 0x01u}, + {0x80u, 0x04u}, + {0x83u, 0x04u}, + {0x84u, 0x04u}, + {0x86u, 0x80u}, + {0x8Au, 0x02u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x20u}, + {0x91u, 0x10u}, + {0x93u, 0x28u}, + {0x94u, 0x20u}, + {0x95u, 0x4Eu}, {0x96u, 0x01u}, - {0x97u, 0x02u}, - {0x98u, 0x01u}, - {0x99u, 0x30u}, - {0x9Au, 0xB0u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x21u}, - {0xA1u, 0x64u}, - {0xA3u, 0x09u}, - {0xA4u, 0x40u}, - {0xA5u, 0x08u}, - {0xA6u, 0xA3u}, - {0xA7u, 0x20u}, - {0xA8u, 0x04u}, + {0x98u, 0x12u}, + {0x99u, 0x20u}, + {0x9Au, 0x40u}, + {0x9Cu, 0x80u}, + {0x9Du, 0x55u}, + {0x9Eu, 0x0Eu}, + {0xA0u, 0x0Cu}, + {0xA1u, 0x40u}, + {0xA2u, 0x2Cu}, + {0xA3u, 0x44u}, + {0xA4u, 0x80u}, + {0xA5u, 0x2Bu}, + {0xA7u, 0x90u}, {0xAAu, 0x40u}, - {0xACu, 0x81u}, - {0xADu, 0x40u}, - {0xAFu, 0x0Au}, - {0xB1u, 0x40u}, - {0xB3u, 0x48u}, - {0xB5u, 0x80u}, - {0xB7u, 0x10u}, - {0xC0u, 0x9Eu}, - {0xC2u, 0xEFu}, - {0xC4u, 0x05u}, - {0xCAu, 0xF8u}, - {0xCCu, 0x9Fu}, - {0xCEu, 0x7Fu}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x1Fu}, + {0xABu, 0x42u}, + {0xACu, 0x14u}, + {0xB1u, 0x80u}, + {0xB2u, 0x04u}, + {0xB3u, 0x05u}, + {0xC0u, 0xFDu}, + {0xC2u, 0x73u}, + {0xC4u, 0x38u}, + {0xCAu, 0x79u}, + {0xCCu, 0xE1u}, + {0xCEu, 0xFCu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x81u}, {0xE2u, 0x08u}, - {0xE4u, 0x10u}, - {0xE6u, 0x02u}, - {0xE8u, 0x80u}, + {0xE4u, 0x08u}, + {0xEAu, 0x81u}, {0xECu, 0x80u}, - {0x04u, 0x02u}, - {0x08u, 0x02u}, - {0x0Cu, 0x02u}, - {0x12u, 0x04u}, - {0x15u, 0x01u}, - {0x17u, 0x02u}, + {0xEEu, 0x20u}, + {0x03u, 0x4Cu}, + {0x05u, 0x01u}, + {0x07u, 0x30u}, + {0x08u, 0x05u}, + {0x09u, 0x40u}, + {0x0Au, 0x0Au}, + {0x0Bu, 0x1Cu}, + {0x0Du, 0x04u}, + {0x0Fu, 0x08u}, + {0x10u, 0x30u}, + {0x12u, 0xC0u}, + {0x13u, 0x0Cu}, + {0x14u, 0x50u}, + {0x15u, 0x4Cu}, + {0x16u, 0xA0u}, + {0x17u, 0x20u}, + {0x18u, 0x60u}, {0x19u, 0x02u}, - {0x1Bu, 0x01u}, - {0x1Cu, 0x02u}, - {0x1Du, 0x02u}, - {0x1Fu, 0x01u}, - {0x25u, 0x02u}, - {0x27u, 0x05u}, - {0x2Cu, 0x01u}, - {0x2Du, 0x02u}, - {0x2Fu, 0x09u}, - {0x32u, 0x04u}, - {0x33u, 0x03u}, - {0x34u, 0x02u}, - {0x35u, 0x04u}, - {0x36u, 0x01u}, - {0x37u, 0x08u}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x50u}, - {0x56u, 0x08u}, + {0x1Au, 0x90u}, + {0x1Du, 0x0Cu}, + {0x20u, 0x03u}, + {0x21u, 0x01u}, + {0x22u, 0x0Cu}, + {0x23u, 0x02u}, + {0x24u, 0x06u}, + {0x26u, 0x09u}, + {0x2Bu, 0x40u}, + {0x2Cu, 0x0Fu}, + {0x2Du, 0x04u}, + {0x2Eu, 0xF0u}, + {0x2Fu, 0x08u}, + {0x31u, 0x0Cu}, + {0x34u, 0xFFu}, + {0x35u, 0x70u}, + {0x37u, 0x03u}, + {0x3Bu, 0x02u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x22u}, - {0x5Du, 0x90u}, + {0x5Cu, 0x20u}, {0x5Fu, 0x01u}, - {0x82u, 0x20u}, - {0x84u, 0xD8u}, - {0x85u, 0x0Fu}, - {0x86u, 0x03u}, - {0x87u, 0x80u}, - {0x88u, 0xC4u}, + {0x80u, 0x01u}, + {0x81u, 0x01u}, + {0x82u, 0xF8u}, + {0x83u, 0x02u}, + {0x84u, 0x40u}, + {0x85u, 0x01u}, + {0x86u, 0x80u}, + {0x87u, 0x02u}, + {0x88u, 0x10u}, {0x89u, 0x04u}, + {0x8Au, 0x20u}, {0x8Bu, 0x08u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x50u}, - {0x8Eu, 0xCEu}, - {0x8Fu, 0x8Fu}, + {0x8Cu, 0x10u}, + {0x8Du, 0x20u}, + {0x8Eu, 0x20u}, + {0x8Fu, 0x1Fu}, {0x90u, 0x02u}, - {0x91u, 0x04u}, - {0x93u, 0x08u}, - {0x94u, 0x03u}, - {0x95u, 0x01u}, - {0x96u, 0xD4u}, - {0x97u, 0x02u}, - {0x99u, 0x01u}, + {0x92u, 0xF0u}, + {0x94u, 0x05u}, + {0x95u, 0x04u}, + {0x96u, 0xF8u}, + {0x97u, 0x08u}, + {0x99u, 0x0Fu}, {0x9Au, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x80u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0xF0u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x20u}, {0xA0u, 0x40u}, - {0xA1u, 0x20u}, + {0xA1u, 0x0Fu}, {0xA2u, 0x80u}, - {0xA3u, 0x0Fu}, - {0xA6u, 0xDFu}, - {0xA7u, 0x10u}, - {0xA9u, 0x10u}, + {0xA3u, 0x10u}, + {0xA8u, 0xF4u}, + {0xA9u, 0x20u}, {0xAAu, 0x08u}, - {0xABu, 0x8Fu}, - {0xADu, 0x4Fu}, - {0xAFu, 0x80u}, - {0xB0u, 0xC0u}, - {0xB2u, 0x1Fu}, + {0xABu, 0x1Fu}, + {0xAFu, 0x1Fu}, + {0xB1u, 0x30u}, + {0xB2u, 0x0Fu}, {0xB3u, 0x03u}, + {0xB4u, 0x30u}, {0xB5u, 0x0Cu}, - {0xB6u, 0x20u}, - {0xB7u, 0xF0u}, - {0xB9u, 0x80u}, - {0xBAu, 0x02u}, - {0xBBu, 0x28u}, - {0xD6u, 0x08u}, + {0xB6u, 0xC0u}, + {0xB8u, 0x08u}, + {0xBAu, 0xA0u}, + {0xBBu, 0x2Au}, + {0xD4u, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x22u}, - {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x90u}, - {0x03u, 0x20u}, - {0x04u, 0x24u}, - {0x07u, 0x41u}, - {0x0Au, 0x80u}, - {0x0Bu, 0x02u}, - {0x0Cu, 0xA0u}, - {0x0Du, 0x01u}, - {0x0Eu, 0x14u}, - {0x10u, 0x02u}, + {0x03u, 0x04u}, + {0x04u, 0x02u}, + {0x05u, 0x10u}, + {0x06u, 0x20u}, + {0x07u, 0x01u}, + {0x08u, 0x01u}, + {0x09u, 0x2Au}, + {0x0Eu, 0x69u}, + {0x11u, 0x43u}, + {0x12u, 0x01u}, + {0x13u, 0x04u}, + {0x14u, 0x80u}, {0x15u, 0x20u}, - {0x16u, 0x40u}, - {0x17u, 0x08u}, - {0x19u, 0x08u}, - {0x1Bu, 0x50u}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x10u}, - {0x1Fu, 0x0Au}, - {0x22u, 0x54u}, - {0x23u, 0x10u}, - {0x24u, 0x08u}, - {0x25u, 0x50u}, - {0x26u, 0x08u}, - {0x27u, 0x01u}, - {0x28u, 0x02u}, - {0x29u, 0x08u}, - {0x2Eu, 0x44u}, - {0x2Fu, 0x48u}, - {0x32u, 0x54u}, - {0x36u, 0x2Au}, - {0x3Du, 0xA8u}, - {0x58u, 0x10u}, - {0x59u, 0x40u}, - {0x5Du, 0x80u}, - {0x60u, 0x02u}, - {0x61u, 0x30u}, - {0x66u, 0x80u}, - {0x7Bu, 0x0Cu}, - {0x80u, 0x04u}, - {0x83u, 0x40u}, - {0x87u, 0x04u}, - {0x8Au, 0x01u}, - {0x8Du, 0x08u}, - {0x8Eu, 0x08u}, - {0x90u, 0x74u}, - {0x91u, 0x63u}, - {0x92u, 0x04u}, - {0x93u, 0x40u}, - {0x94u, 0x02u}, - {0x95u, 0x80u}, - {0x96u, 0x13u}, - {0x97u, 0x18u}, - {0x98u, 0x10u}, - {0x99u, 0x20u}, - {0x9Au, 0x30u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x01u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x05u}, - {0xA0u, 0x02u}, - {0xA1u, 0x04u}, - {0xA3u, 0x01u}, - {0xA4u, 0x01u}, - {0xA6u, 0x81u}, - {0xA7u, 0x04u}, - {0xABu, 0x68u}, - {0xACu, 0x04u}, - {0xADu, 0x82u}, - {0xAEu, 0x11u}, - {0xB0u, 0x50u}, - {0xB1u, 0x20u}, - {0xB7u, 0x20u}, - {0xC0u, 0xF7u}, - {0xC2u, 0xF9u}, - {0xC4u, 0x71u}, - {0xCAu, 0xFAu}, - {0xCCu, 0xEEu}, - {0xCEu, 0x70u}, - {0xD6u, 0x1Cu}, - {0xD8u, 0x1Cu}, - {0xE0u, 0x20u}, - {0xE2u, 0x02u}, - {0xE6u, 0x50u}, - {0xE8u, 0x42u}, - {0xECu, 0x01u}, - {0xEEu, 0x08u}, - {0x00u, 0x05u}, - {0x01u, 0x02u}, - {0x02u, 0x0Au}, - {0x03u, 0x01u}, - {0x08u, 0xA0u}, - {0x0Au, 0x4Fu}, - {0x0Du, 0x04u}, + {0x18u, 0x08u}, + {0x19u, 0x20u}, + {0x1Cu, 0x30u}, + {0x1Eu, 0x24u}, + {0x1Fu, 0x44u}, + {0x20u, 0x82u}, + {0x23u, 0x44u}, + {0x25u, 0x14u}, + {0x27u, 0x48u}, + {0x29u, 0x40u}, + {0x2Au, 0x11u}, + {0x2Fu, 0x86u}, + {0x31u, 0x20u}, + {0x32u, 0x08u}, + {0x33u, 0x82u}, + {0x34u, 0x20u}, + {0x35u, 0x04u}, + {0x37u, 0x40u}, + {0x38u, 0x12u}, + {0x3Bu, 0x44u}, + {0x3Du, 0xA8u}, + {0x3Fu, 0x01u}, + {0x64u, 0x04u}, + {0x65u, 0x80u}, + {0x67u, 0x10u}, + {0x78u, 0x20u}, + {0x79u, 0x20u}, + {0x7Au, 0x08u}, + {0x81u, 0x04u}, + {0x84u, 0x01u}, + {0x86u, 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{0x49u, 0x08u}, - {0x4Au, 0x88u}, - {0x50u, 0x40u}, - {0x52u, 0x54u}, - {0x53u, 0x80u}, - {0x5Cu, 0x03u}, - {0x63u, 0x02u}, - {0x68u, 0x64u}, - {0x69u, 0x50u}, - {0x6Bu, 0x41u}, + {0x49u, 0x15u}, + {0x4Au, 0x80u}, + {0x51u, 0x28u}, + {0x52u, 0x01u}, + {0x61u, 0x02u}, + {0x68u, 0x80u}, + {0x69u, 0x0Bu}, + {0x6Au, 0x4Cu}, + {0x6Bu, 0x09u}, {0x72u, 0x02u}, {0x73u, 0x01u}, - {0x81u, 0x10u}, + {0x80u, 0x40u}, {0x84u, 0x01u}, - {0x88u, 0x40u}, - {0x8Au, 0x20u}, - {0x8Cu, 0x10u}, - {0x90u, 0x01u}, - {0x91u, 0x09u}, - {0x92u, 0x08u}, - {0x94u, 0x44u}, - {0x95u, 0x50u}, - {0x96u, 0x04u}, + {0x8Au, 0x80u}, + {0x8Bu, 0x10u}, + {0x8Eu, 0x10u}, + {0x90u, 0x04u}, + {0x93u, 0x10u}, + {0x94u, 0xC8u}, + {0x95u, 0x0Au}, + {0x96u, 0x4Au}, {0x97u, 0x01u}, {0x98u, 0x08u}, - {0x9Au, 0x08u}, - {0x9Du, 0x19u}, - {0x9Eu, 0x54u}, - {0x9Fu, 0x40u}, - {0xA1u, 0x10u}, - {0xA2u, 0x1Cu}, + {0x99u, 0x10u}, + {0x9Du, 0x05u}, + {0x9Eu, 0x03u}, + {0x9Fu, 0x19u}, + {0xA2u, 0x10u}, {0xA3u, 0x01u}, - {0xA4u, 0x64u}, - {0xA6u, 0x80u}, - {0xA7u, 0x88u}, - {0xA8u, 0x01u}, - {0xABu, 0x04u}, - {0xACu, 0x08u}, - {0xB2u, 0x20u}, - {0xB3u, 0x20u}, - {0xC0u, 0x4Fu}, - {0xC2u, 0xEBu}, - {0xC4u, 0x47u}, - {0xCAu, 0x27u}, - {0xCCu, 0xEFu}, - {0xCEu, 0xEFu}, - {0xD0u, 0x07u}, + {0xA4u, 0x80u}, + {0xA5u, 0x28u}, + {0xA9u, 0x05u}, + {0xACu, 0x80u}, + {0xB0u, 0x08u}, + {0xB1u, 0x10u}, + {0xB2u, 0x08u}, + {0xB3u, 0x41u}, + {0xB6u, 0x01u}, + {0xC0u, 0xFDu}, + {0xC2u, 0xBFu}, + {0xC4u, 0xF7u}, + {0xCAu, 0x48u}, + {0xCCu, 0x21u}, + {0xCEu, 0x0Au}, + {0xD0u, 0x0Bu}, {0xD2u, 0x0Cu}, - {0xD8u, 0x08u}, - {0xE2u, 0xB0u}, - {0xEAu, 0x02u}, - {0xECu, 0x04u}, - {0x02u, 0x10u}, - {0x04u, 0x02u}, - {0x06u, 0x0Du}, - {0x08u, 0x3Du}, - {0x0Cu, 0x0Du}, - {0x0Du, 0xE0u}, - {0x0Eu, 0x30u}, - {0x13u, 0x01u}, - {0x14u, 0x01u}, - {0x15u, 0x31u}, - {0x16u, 0x02u}, - {0x17u, 0x02u}, - {0x18u, 0x02u}, - {0x19u, 0x98u}, - {0x1Au, 0x04u}, - {0x1Bu, 0x03u}, - {0x1Cu, 0x3Du}, - {0x1Fu, 0xECu}, - {0x20u, 0x3Du}, - {0x23u, 0x02u}, - {0x24u, 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{0x1Bu, 0x10u}, - {0x1Du, 0x06u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x10u}, - {0x21u, 0x44u}, - {0x22u, 0x22u}, - {0x23u, 0x10u}, - {0x25u, 0x90u}, - {0x27u, 0x80u}, - {0x2Au, 0x42u}, - {0x2Bu, 0x14u}, - {0x2Fu, 0x88u}, - {0x30u, 0x88u}, - {0x33u, 0x20u}, - {0x35u, 0x10u}, - {0x36u, 0x0Au}, + {0x0Du, 0x01u}, + {0x0Fu, 0x22u}, + {0x10u, 0x80u}, + {0x12u, 0x03u}, + {0x13u, 0x28u}, + {0x15u, 0x08u}, + {0x16u, 0x22u}, + {0x17u, 0x11u}, + {0x18u, 0x14u}, + {0x19u, 0x10u}, + {0x1Bu, 0x11u}, + {0x1Eu, 0x20u}, + {0x20u, 0x80u}, + {0x21u, 0x02u}, + {0x22u, 0x48u}, + {0x23u, 0x40u}, + {0x25u, 0x05u}, + {0x26u, 0x40u}, + {0x27u, 0x04u}, + {0x29u, 0x42u}, + {0x30u, 0x20u}, + {0x31u, 0x02u}, + {0x32u, 0x48u}, {0x37u, 0x80u}, - {0x38u, 0x40u}, - {0x3Fu, 0x40u}, - {0x58u, 0x20u}, - {0x59u, 0x89u}, - {0x60u, 0x20u}, - {0x61u, 0x80u}, - {0x62u, 0x05u}, - {0x66u, 0xA0u}, - {0x67u, 0x20u}, - {0x80u, 0x02u}, - {0x81u, 0x40u}, - {0x82u, 0x40u}, - {0x85u, 0x01u}, - {0x86u, 0x08u}, - {0x8Eu, 0x01u}, - {0x90u, 0x03u}, - {0x92u, 0x09u}, - {0x93u, 0x40u}, - {0x95u, 0x50u}, - {0x96u, 0x04u}, - {0x97u, 0x01u}, - {0x98u, 0x08u}, - {0x99u, 0x02u}, - {0x9Au, 0x2Au}, - {0x9Bu, 0x1Fu}, - {0x9Cu, 0x42u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x14u}, - {0x9Fu, 0x40u}, - {0xA0u, 0x80u}, - {0xA1u, 0x08u}, - {0xA2u, 0x1Cu}, - {0xA3u, 0x01u}, - {0xA4u, 0x64u}, + {0x39u, 0x61u}, + {0x3Bu, 0x04u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x04u}, + {0x60u, 0x90u}, + {0x61u, 0x20u}, + {0x62u, 0x40u}, + {0x83u, 0x80u}, + {0x84u, 0x05u}, + {0x86u, 0x40u}, + {0x8Au, 0x40u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x10u}, + {0x90u, 0x20u}, + {0x91u, 0x61u}, + {0x92u, 0x24u}, + {0x93u, 0x14u}, + {0x94u, 0x80u}, + {0x95u, 0x02u}, + {0x96u, 0x82u}, + {0x98u, 0x01u}, + {0x99u, 0x42u}, + {0x9Du, 0x14u}, + {0x9Eu, 0x2Au}, + {0x9Fu, 0x05u}, + {0xA0u, 0x20u}, + {0xA1u, 0x10u}, + {0xA2u, 0x01u}, + {0xA4u, 0x40u}, {0xA5u, 0x02u}, - {0xA6u, 0x81u}, - {0xA7u, 0x08u}, - {0xAAu, 0x02u}, - {0xAEu, 0x48u}, - {0xAFu, 0x80u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xEBu}, - {0xC4u, 0x7Fu}, - {0xCAu, 0xAFu}, - {0xCCu, 0xFEu}, - {0xCEu, 0x18u}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x79u}, - {0xE0u, 0x01u}, - {0xE6u, 0x41u}, - {0xEEu, 0x08u}, - {0x00u, 0x33u}, - {0x02u, 0xCCu}, - {0x03u, 0x80u}, - {0x04u, 0x12u}, - {0x05u, 0x0Fu}, - {0x06u, 0x21u}, + {0xA6u, 0x0Au}, + {0xA7u, 0x01u}, + {0xA8u, 0x08u}, + {0xAAu, 0x12u}, + {0xAEu, 0x10u}, + {0xAFu, 0x04u}, + {0xB6u, 0x01u}, + {0xC0u, 0xF7u}, + {0xC2u, 0xBFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x09u}, + {0xCCu, 0x1Fu}, + {0xCEu, 0x6Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x02u}, + {0xE2u, 0x21u}, + {0xECu, 0x01u}, + {0xEEu, 0x4Cu}, + {0x00u, 0x11u}, + {0x02u, 0x22u}, + {0x07u, 0xFFu}, {0x08u, 0x0Fu}, - {0x09u, 0x01u}, + {0x09u, 0x48u}, {0x0Au, 0xF0u}, - {0x0Bu, 0x02u}, - {0x0Cu, 0x48u}, - {0x0Eu, 0x84u}, - {0x0Fu, 0x40u}, + {0x0Bu, 0x84u}, + {0x0Cu, 0x12u}, + {0x0Du, 0x11u}, + {0x0Eu, 0x21u}, + {0x0Fu, 0x22u}, {0x10u, 0xFFu}, - {0x11u, 0x04u}, - {0x13u, 0x08u}, - {0x15u, 0x01u}, - {0x17u, 0x02u}, - {0x19u, 0x04u}, - {0x1Au, 0xFFu}, - {0x1Bu, 0x08u}, - {0x1Cu, 0xFFu}, - {0x1Fu, 0x30u}, - {0x20u, 0x44u}, - {0x22u, 0x88u}, - {0x23u, 0x0Fu}, - {0x25u, 0x4Fu}, - {0x27u, 0x20u}, - {0x2Bu, 0x4Fu}, - {0x2Cu, 0x11u}, - {0x2Du, 0x40u}, - {0x2Eu, 0x22u}, - {0x2Fu, 0x1Fu}, + {0x11u, 0x33u}, + {0x13u, 0xCCu}, + {0x14u, 0x48u}, + {0x16u, 0x84u}, + {0x17u, 0xFFu}, + {0x18u, 0xFFu}, + {0x1Fu, 0xFFu}, + {0x20u, 0x33u}, + {0x21u, 0x12u}, + {0x22u, 0xCCu}, + {0x23u, 0x21u}, + {0x24u, 0x44u}, + {0x25u, 0x44u}, + {0x26u, 0x88u}, + {0x27u, 0x88u}, + {0x29u, 0x0Fu}, + {0x2Au, 0xFFu}, + {0x2Bu, 0xF0u}, {0x30u, 0xFFu}, - {0x31u, 0x0Cu}, - {0x33u, 0x03u}, - {0x35u, 0x80u}, - {0x37u, 0x70u}, - {0x3Bu, 0x0Au}, + {0x33u, 0xFFu}, {0x3Eu, 0x01u}, - {0x54u, 0x01u}, + {0x3Fu, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Fu, 0x01u}, + {0x80u, 0x55u}, + {0x81u, 0x0Fu}, + {0x82u, 0xAAu}, + {0x83u, 0xF0u}, + {0x84u, 0x33u}, + {0x86u, 0xCCu}, + {0x87u, 0xFFu}, + {0x89u, 0x33u}, + {0x8Bu, 0xCCu}, + {0x8Eu, 0xFFu}, + {0x90u, 0x0Fu}, + {0x92u, 0xF0u}, + {0x93u, 0xFFu}, + {0x95u, 0xFFu}, + {0x99u, 0x69u}, + {0x9Au, 0xFFu}, + {0x9Bu, 0x96u}, + {0x9Cu, 0xFFu}, + {0x9Du, 0xFFu}, + {0xA6u, 0xFFu}, + {0xA8u, 0xFFu}, + {0xABu, 0xFFu}, + {0xACu, 0x69u}, + {0xADu, 0x55u}, + {0xAEu, 0x96u}, + {0xAFu, 0xAAu}, + {0xB0u, 0xFFu}, + {0xB1u, 0xFFu}, + {0xBAu, 0x02u}, + {0xBBu, 0x02u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x22u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x02u, 0x40u}, + {0x03u, 0x02u}, + {0x04u, 0x02u}, + {0x05u, 0x22u}, + {0x06u, 0x02u}, + {0x0Au, 0x81u}, + {0x0Bu, 0x08u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0x28u}, + {0x12u, 0x19u}, + {0x14u, 0x04u}, + {0x15u, 0x04u}, + {0x17u, 0x01u}, + {0x19u, 0x01u}, + {0x1Au, 0x80u}, + {0x1Eu, 0x40u}, + {0x21u, 0x01u}, + {0x27u, 0x20u}, + {0x28u, 0x02u}, + {0x2Au, 0x10u}, + {0x2Du, 0x24u}, + {0x2Eu, 0x02u}, + {0x32u, 0x28u}, + {0x33u, 0x82u}, + {0x34u, 0x04u}, + {0x36u, 0xC4u}, + {0x37u, 0x01u}, + {0x39u, 0x02u}, + {0x3Bu, 0x18u}, + {0x3Cu, 0x40u}, + {0x3Du, 0x10u}, + {0x3Fu, 0x28u}, + {0x49u, 0x40u}, + {0x4Bu, 0x80u}, + {0x58u, 0x20u}, + {0x5Bu, 0x40u}, + {0x5Cu, 0x80u}, + {0x5Du, 0x01u}, + {0x5Eu, 0x24u}, + {0x60u, 0x08u}, + {0x61u, 0x50u}, + {0x67u, 0x02u}, + {0x80u, 0x08u}, + {0x86u, 0x04u}, + {0x8Cu, 0x40u}, + {0x8Du, 0x06u}, + {0x8Fu, 0x02u}, + {0x90u, 0x04u}, + {0x92u, 0x01u}, + {0x93u, 0x1Au}, + {0x94u, 0x22u}, + {0x95u, 0x0Eu}, + {0x96u, 0x40u}, + {0x98u, 0x12u}, + {0x99u, 0x20u}, + {0x9Au, 0x53u}, + {0x9Bu, 0x11u}, + {0x9Du, 0x51u}, + {0x9Eu, 0x0Cu}, + {0x9Fu, 0x20u}, + {0xA0u, 0x08u}, + {0xA2u, 0xACu}, + {0xA3u, 0xC4u}, + {0xA4u, 0x82u}, + {0xA5u, 0x2Au}, + {0xA6u, 0x41u}, + {0xA7u, 0x10u}, + {0xAAu, 0x40u}, + {0xABu, 0x80u}, + {0xB1u, 0x40u}, + {0xB2u, 0x10u}, + {0xB7u, 0x21u}, + {0xC0u, 0xDDu}, + {0xC2u, 0x7Bu}, + {0xC4u, 0x77u}, + {0xCAu, 0xECu}, + {0xCCu, 0xDFu}, + {0xCEu, 0x77u}, + {0xD6u, 0xFCu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x50u}, + {0xE4u, 0x40u}, + {0xEEu, 0x08u}, + {0x00u, 0x96u}, + {0x02u, 0x69u}, + {0x05u, 0x88u}, + {0x07u, 0x03u}, + {0x08u, 0x0Fu}, + {0x09u, 0x21u}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x02u}, + {0x0Eu, 0xFFu}, + {0x10u, 0x55u}, + {0x12u, 0xAAu}, + {0x13u, 0x01u}, + {0x14u, 0x33u}, + {0x15u, 0xE0u}, + {0x16u, 0xCCu}, + {0x1Au, 0xFFu}, + {0x1Bu, 0xECu}, + {0x1Cu, 0xFFu}, + {0x21u, 0x04u}, + {0x23u, 0x43u}, + {0x26u, 0xFFu}, + {0x27u, 0x12u}, + {0x28u, 0xFFu}, + {0x31u, 0x10u}, + {0x32u, 0xFFu}, + {0x35u, 0x0Fu}, + {0x37u, 0xE0u}, + {0x3Au, 0x08u}, + {0x3Fu, 0x40u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x20u}, - {0x5Du, 0x20u}, + {0x5Cu, 0x02u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x44u}, - {0x82u, 0x88u}, - {0x84u, 0x12u}, - {0x86u, 0x21u}, - {0x88u, 0x0Fu}, - {0x89u, 0x0Fu}, - {0x8Au, 0xF0u}, - {0x8Bu, 0xF0u}, - {0x8Cu, 0x11u}, - {0x8Du, 0x11u}, - {0x8Eu, 0x22u}, - {0x8Fu, 0x22u}, - {0x91u, 0x33u}, - {0x92u, 0xFFu}, - {0x93u, 0xCCu}, - {0x94u, 0x33u}, - {0x96u, 0xCCu}, - {0x98u, 0x48u}, - {0x9Au, 0x84u}, - {0x9Bu, 0xFFu}, - {0x9Du, 0xFFu}, - {0x9Eu, 0xFFu}, - {0xA1u, 0x44u}, - {0xA3u, 0x88u}, - {0xA5u, 0x84u}, - {0xA6u, 0xFFu}, - {0xA7u, 0x48u}, + {0x84u, 0x02u}, + {0x86u, 0x09u}, + {0x87u, 0x01u}, + {0x89u, 0xE0u}, + {0x8Cu, 0x02u}, + {0x8Eu, 0x05u}, + {0x93u, 0xECu}, + {0x94u, 0x01u}, + {0x95u, 0x88u}, + {0x96u, 0x02u}, + {0x97u, 0x03u}, + {0x98u, 0x02u}, + {0x9Au, 0x01u}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x01u}, + {0xA3u, 0x12u}, + {0xA5u, 0x04u}, + {0xA7u, 0x43u}, {0xA9u, 0x21u}, - {0xABu, 0x12u}, - {0xAFu, 0xFFu}, - {0xB1u, 0xFFu}, - {0xB4u, 0xFFu}, - {0xBEu, 0x10u}, - {0xBFu, 0x01u}, + {0xABu, 0x02u}, + {0xB2u, 0x03u}, + {0xB3u, 0xE0u}, + {0xB4u, 0x08u}, + {0xB5u, 0x10u}, + {0xB6u, 0x04u}, + {0xB7u, 0x0Fu}, + {0xBAu, 0x08u}, + {0xBFu, 0x04u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x12u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x71u}, - {0x02u, 0x10u}, - {0x05u, 0x23u}, - {0x06u, 0x12u}, - {0x08u, 0x18u}, - {0x09u, 0x02u}, - {0x0Au, 0x83u}, - {0x0Bu, 0x08u}, - {0x0Cu, 0x20u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x02u}, - {0x10u, 0x20u}, - {0x14u, 0x40u}, - {0x15u, 0x41u}, - {0x1Bu, 0x20u}, - {0x1Fu, 0x01u}, - {0x20u, 0x80u}, - {0x25u, 0x09u}, - {0x26u, 0x82u}, - {0x27u, 0x04u}, - {0x28u, 0x50u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x01u}, - {0x2Cu, 0x01u}, + {0x00u, 0x01u}, + {0x03u, 0x0Au}, + {0x05u, 0x80u}, + {0x07u, 0x10u}, + {0x08u, 0x08u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x88u}, + {0x0Eu, 0x2Au}, + {0x12u, 0x18u}, + {0x18u, 0x20u}, + {0x1Bu, 0x08u}, + {0x1Eu, 0x2Au}, + {0x22u, 0x11u}, + {0x23u, 0x02u}, + {0x24u, 0x04u}, + {0x25u, 0x04u}, + {0x27u, 0x01u}, + {0x28u, 0x10u}, + {0x2Bu, 0x40u}, {0x2Du, 0x08u}, - {0x2Fu, 0x48u}, - {0x30u, 0x20u}, - {0x31u, 0x01u}, - {0x32u, 0x40u}, - {0x35u, 0x10u}, - {0x36u, 0x8Au}, - {0x39u, 0x50u}, - {0x3Cu, 0x02u}, - {0x3Du, 0x08u}, - {0x3Eu, 0x20u}, - {0x3Fu, 0x40u}, - {0x41u, 0x08u}, - {0x42u, 0x20u}, - {0x5Bu, 0x40u}, - {0x5Cu, 0x40u}, - {0x60u, 0x02u}, - {0x62u, 0x40u}, - {0x81u, 0x01u}, - {0x90u, 0x40u}, - {0x91u, 0x41u}, - {0x92u, 0x02u}, - {0x93u, 0xC8u}, - {0x97u, 0x02u}, - {0x98u, 0x01u}, - {0x99u, 0x38u}, + {0x2Eu, 0x10u}, + {0x2Fu, 0x80u}, + {0x30u, 0x08u}, + {0x32u, 0x11u}, + {0x35u, 0x04u}, + {0x37u, 0x01u}, + {0x39u, 0x08u}, + {0x3Bu, 0x20u}, + {0x3Cu, 0x24u}, + {0x58u, 0x40u}, + {0x5Eu, 0x40u}, + {0x60u, 0x01u}, + {0x65u, 0x80u}, + {0x68u, 0x82u}, + {0x69u, 0x14u}, + {0x71u, 0x2Au}, + {0x73u, 0x01u}, + {0x82u, 0x50u}, + {0x84u, 0x40u}, + {0x88u, 0x10u}, + {0x8Bu, 0x80u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x04u}, + {0x8Fu, 0x03u}, + {0x91u, 0x08u}, + {0x92u, 0x01u}, + {0x93u, 0xA8u}, + {0x94u, 0x20u}, + {0x95u, 0x14u}, + {0x98u, 0x18u}, + {0x99u, 0x0Cu}, {0x9Au, 0x10u}, - {0x9Cu, 0x02u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x21u}, - {0xA1u, 0x06u}, + {0x9Bu, 0x10u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x08u}, {0xA2u, 0x08u}, - {0xA3u, 0x08u}, - {0xA4u, 0x40u}, - {0xA5u, 0x08u}, - {0xA6u, 0x80u}, - {0xA7u, 0x20u}, - {0xAFu, 0x08u}, - {0xB0u, 0x40u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xDFu}, - {0xC4u, 0x94u}, - {0xCAu, 0xFFu}, - {0xCCu, 0xFDu}, - {0xCEu, 0xFCu}, - {0xD6u, 0x18u}, - {0xD8u, 0x08u}, - {0xE0u, 0x01u}, - {0xEAu, 0x08u}, - {0xEEu, 0x08u}, - {0xA8u, 0x08u}, - {0xA9u, 0x02u}, + {0xA3u, 0x42u}, + {0xA4u, 0x82u}, + {0xA5u, 0x2Au}, + {0xA6u, 0x11u}, {0xABu, 0x40u}, - {0xAEu, 0x10u}, - {0xB2u, 0x02u}, - {0xB3u, 0x04u}, - {0xE8u, 0x20u}, - {0xEAu, 0x80u}, + {0xADu, 0x01u}, + {0xAFu, 0x02u}, + {0xB1u, 0x0Cu}, + {0xB2u, 0x08u}, + {0xB3u, 0x10u}, + {0xB4u, 0xA0u}, + {0xC0u, 0xABu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x06u}, + {0xCAu, 0xE3u}, + {0xCCu, 0xC7u}, + {0xCEu, 0x66u}, + {0xD6u, 0x18u}, + {0xD8u, 0x18u}, + {0xE0u, 0x80u}, + {0xE2u, 0x10u}, + {0xE4u, 0x80u}, + {0xE6u, 0x48u}, + {0xE8u, 0xB0u}, + {0xECu, 0x80u}, {0xEEu, 0x01u}, - {0x05u, 0x20u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x04u}, - {0x12u, 0x08u}, - {0x13u, 0x02u}, + {0x06u, 0x08u}, + {0x0Cu, 0x10u}, + {0x0Eu, 0x40u}, + {0x11u, 0x10u}, + {0x13u, 0x08u}, {0x16u, 0x80u}, - {0x17u, 0x80u}, - {0x30u, 0x10u}, + {0x17u, 0x40u}, + {0x30u, 0x40u}, {0x33u, 0x01u}, - {0x36u, 0x20u}, - {0x37u, 0x08u}, - {0x39u, 0x04u}, - {0x3Au, 0x80u}, - {0x3Cu, 0x10u}, - {0x3Eu, 0x04u}, + {0x36u, 0x22u}, + {0x3Au, 0x81u}, + {0x3Du, 0x44u}, {0x40u, 0x04u}, - {0x56u, 0x02u}, - {0x59u, 0x40u}, - {0x6Bu, 0x03u}, - {0x83u, 0x08u}, + {0x53u, 0x02u}, + {0x5Fu, 0x40u}, + {0x6Bu, 0x09u}, + {0x82u, 0x01u}, {0xC0u, 0x80u}, {0xC2u, 0xA0u}, {0xC4u, 0xF0u}, @@ -2224,200 +2266,209 @@ void cyfitter_cfg(void) {0xD4u, 0x80u}, {0xD6u, 0x20u}, {0xE2u, 0x20u}, - {0x03u, 0x02u}, - {0x0Au, 0x01u}, - {0x30u, 0x04u}, - {0x33u, 0x10u}, - {0x34u, 0x02u}, - {0x37u, 0x80u}, - {0x3Au, 0x80u}, - {0x5Au, 0x20u}, - {0x63u, 0x80u}, - {0x84u, 0x02u}, - {0x89u, 0x20u}, - {0x93u, 0x04u}, + {0x00u, 0x10u}, + {0x0Au, 0x02u}, + {0x30u, 0x08u}, + {0x33u, 0x20u}, + {0x36u, 0x08u}, + {0x37u, 0x40u}, + {0x39u, 0x80u}, + {0x59u, 0x40u}, + {0x61u, 0x20u}, + {0x82u, 0x08u}, + {0x85u, 0x10u}, + {0x86u, 0x02u}, + {0x87u, 0x20u}, + {0x88u, 0x08u}, + {0x89u, 0x40u}, + {0x91u, 0x10u}, + {0x92u, 0x40u}, {0x94u, 0x04u}, - {0x96u, 0x04u}, - {0x99u, 0x20u}, - {0x9Bu, 0x90u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x40u}, - {0xA2u, 0x10u}, - {0xA6u, 0x20u}, - {0xA8u, 0x10u}, - {0xAAu, 0x08u}, - {0xABu, 0x10u}, - {0xADu, 0x04u}, - {0xB6u, 0x02u}, + {0x95u, 0x04u}, + {0x97u, 0x40u}, + {0x98u, 0x10u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x40u}, + {0x9Cu, 0x40u}, + {0xA1u, 0x20u}, + {0xA6u, 0x22u}, + {0xA7u, 0x02u}, + {0xA9u, 0x20u}, + {0xB5u, 0x40u}, {0xC0u, 0x40u}, {0xC2u, 0x40u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0x80u}, {0xD8u, 0x40u}, - {0xE6u, 0x40u}, - {0xEEu, 0xC0u}, - {0x10u, 0x10u}, + {0xE2u, 0x60u}, + {0xEAu, 0x20u}, + {0x10u, 0x40u}, {0x33u, 0x80u}, - {0x83u, 0x40u}, - {0x86u, 0x80u}, - {0x93u, 0x04u}, + {0x81u, 0x20u}, + {0x88u, 0x10u}, + {0x8Eu, 0x20u}, + {0x92u, 0x42u}, {0x94u, 0x04u}, - {0x9Cu, 0x14u}, - {0x9Eu, 0x80u}, - {0xA2u, 0x10u}, - {0xA7u, 0x40u}, - {0xAAu, 0x10u}, - {0xADu, 0x40u}, - {0xAEu, 0x05u}, - {0xB3u, 0x02u}, - {0xB6u, 0x20u}, + {0x95u, 0x84u}, + {0x97u, 0x40u}, + {0x98u, 0x10u}, + {0x9Au, 0x08u}, + {0x9Cu, 0x40u}, + {0xA6u, 0x20u}, + {0xB4u, 0x10u}, + {0xB7u, 0x02u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0xE2u, 0x60u}, - {0xE8u, 0x10u}, - {0xEAu, 0x40u}, - {0xEEu, 0x30u}, - {0x68u, 0x40u}, - {0x84u, 0x04u}, - {0x87u, 0x04u}, - {0x93u, 0x04u}, + {0xE6u, 0x80u}, + {0x86u, 0x01u}, + {0x8Du, 0x80u}, + {0x92u, 0x42u}, {0x94u, 0x04u}, - {0x9Cu, 0x04u}, + {0x95u, 0x04u}, + {0x97u, 0x40u}, + {0x99u, 0x20u}, + {0x9Au, 0x08u}, {0xA7u, 0x80u}, - {0xB2u, 0x10u}, - {0xDCu, 0x20u}, - {0xE0u, 0x40u}, - {0xE2u, 0x10u}, + {0xA9u, 0x40u}, + {0xE4u, 0x40u}, + {0xEAu, 0x80u}, {0x05u, 0x08u}, {0x06u, 0x08u}, - {0x08u, 0x08u}, - {0x09u, 0x20u}, - {0x13u, 0x02u}, - {0x52u, 0x20u}, - {0x58u, 0x02u}, - {0x62u, 0x02u}, - {0x71u, 0x04u}, + {0x09u, 0x01u}, + {0x0Bu, 0x02u}, + {0x11u, 0x04u}, + {0x56u, 0x04u}, + {0x5Bu, 0x02u}, + {0x65u, 0x40u}, + {0x78u, 0x80u}, {0xC0u, 0x05u}, {0xC2u, 0x0Au}, {0xC4u, 0x08u}, - {0xD4u, 0x04u}, - {0xD6u, 0x02u}, - {0xD8u, 0x02u}, + {0xD4u, 0x02u}, + {0xD6u, 0x03u}, {0xDCu, 0x01u}, - {0x00u, 0x02u}, - {0x02u, 0x02u}, - {0x08u, 0x84u}, - {0x56u, 0x22u}, - {0x5Bu, 0x04u}, - {0x60u, 0x10u}, - {0x85u, 0x01u}, - {0x86u, 0x02u}, - {0x8Du, 0x04u}, - {0x98u, 0x08u}, + {0x01u, 0x42u}, + {0x09u, 0x04u}, + {0x0Au, 0x01u}, + {0x52u, 0x02u}, + {0x57u, 0x01u}, + {0x66u, 0x82u}, + {0x80u, 0x02u}, + {0x86u, 0x82u}, + {0x87u, 0x02u}, + {0x89u, 0x08u}, + {0x8Eu, 0x02u}, + {0x91u, 0x04u}, + {0x93u, 0x02u}, {0x99u, 0x08u}, {0x9Au, 0x08u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x04u}, - {0xA1u, 0x20u}, - {0xA6u, 0x20u}, - {0xB6u, 0x02u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x02u}, + {0xA5u, 0x04u}, + {0xA9u, 0x05u}, + {0xACu, 0x80u}, + {0xADu, 0x40u}, {0xC0u, 0x0Au}, {0xC2u, 0x0Au}, - {0xD4u, 0x02u}, - {0xD6u, 0x06u}, - {0xD8u, 0x02u}, - {0xE0u, 0x08u}, - {0xECu, 0x08u}, + {0xD4u, 0x01u}, + {0xD6u, 0x05u}, + {0xD8u, 0x01u}, + {0xE4u, 0x08u}, + {0xE6u, 0x04u}, {0x54u, 0x20u}, - {0x87u, 0x04u}, - {0x95u, 0x02u}, - {0x98u, 0x04u}, - {0x99u, 0x08u}, + {0x87u, 0x01u}, + {0x91u, 0x04u}, + {0x92u, 0x01u}, + {0x93u, 0x02u}, + {0x99u, 0x0Au}, {0x9Au, 0x08u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Fu, 0x04u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x04u}, {0xA0u, 0x20u}, - {0xA1u, 0x20u}, - {0xA2u, 0x02u}, - {0xA6u, 0x20u}, - {0xA8u, 0x10u}, - {0xACu, 0x28u}, - {0xB0u, 0x81u}, - {0xB2u, 0x20u}, + {0xA4u, 0x02u}, + {0xA5u, 0x08u}, + {0xA7u, 0x01u}, + {0xACu, 0x20u}, + {0xB5u, 0x40u}, {0xD4u, 0x02u}, - {0xEAu, 0x05u}, - {0xECu, 0x01u}, - {0x0Bu, 0x84u}, - {0x0Du, 0x01u}, + {0xEAu, 0x02u}, + {0x09u, 0x08u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x02u}, {0x0Fu, 0x02u}, - {0x86u, 0x08u}, - {0x87u, 0x40u}, - {0x8Au, 0x02u}, - {0x95u, 0x02u}, - {0x97u, 0x04u}, - {0x98u, 0x04u}, - {0x99u, 0x08u}, + {0x82u, 0x04u}, + {0x85u, 0x40u}, + {0x86u, 0x01u}, + {0x89u, 0x04u}, + {0x8Fu, 0x01u}, + {0x91u, 0x04u}, + {0x92u, 0x01u}, + {0x93u, 0x02u}, + {0x97u, 0x01u}, + {0x99u, 0x0Au}, {0x9Au, 0x08u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Fu, 0x04u}, - {0xA2u, 0x02u}, - {0xB5u, 0x20u}, - {0xB6u, 0x20u}, - {0xC2u, 0x0Fu}, - {0xE6u, 0x04u}, - {0xE8u, 0x08u}, - {0xEEu, 0x02u}, - {0x02u, 0x04u}, - {0x80u, 0x02u}, - {0x8Cu, 0x04u}, - {0x94u, 0x04u}, + {0x9Du, 0x40u}, {0x9Eu, 0x04u}, - {0xAAu, 0x04u}, - {0xACu, 0x40u}, + {0xA4u, 0x02u}, + {0xA5u, 0x08u}, + {0xABu, 0x01u}, + {0xC2u, 0x0Fu}, + {0xE2u, 0x06u}, + {0x01u, 0x80u}, + {0x65u, 0x04u}, + {0x8Bu, 0x40u}, + {0x92u, 0x40u}, + {0x95u, 0x04u}, + {0x97u, 0x40u}, + {0x99u, 0x20u}, + {0x9Du, 0x80u}, + {0xAAu, 0x08u}, {0xAFu, 0x80u}, + {0xB4u, 0x04u}, {0xC0u, 0x40u}, - {0xE2u, 0x20u}, - {0xE8u, 0x80u}, - {0xEAu, 0x40u}, + {0xD8u, 0x80u}, + {0xECu, 0x80u}, {0xEEu, 0x10u}, - {0x01u, 0x02u}, - {0x50u, 0x20u}, - {0x54u, 0x02u}, + {0x03u, 0x20u}, + {0x51u, 0x02u}, + {0x56u, 0x20u}, {0x5Bu, 0x02u}, - {0x66u, 0x02u}, - {0x70u, 0x04u}, - {0x80u, 0x20u}, - {0x85u, 0x02u}, - {0x8Au, 0x02u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x04u}, - {0xA0u, 0x02u}, + {0x65u, 0x20u}, + {0x77u, 0x10u}, + {0x82u, 0x40u}, + {0x87u, 0x20u}, + {0x8Du, 0x02u}, + {0x8Eu, 0x20u}, + {0x8Fu, 0x02u}, + {0x92u, 0x40u}, + {0x99u, 0x20u}, + {0x9Bu, 0x10u}, + {0xA9u, 0x04u}, + {0xABu, 0x10u}, + {0xADu, 0x04u}, {0xC0u, 0x10u}, - {0xD4u, 0x20u}, - {0xD6u, 0x60u}, + {0xD4u, 0xC0u}, + {0xD6u, 0x40u}, {0xD8u, 0x80u}, - {0xDCu, 0x80u}, - {0xE2u, 0x80u}, + {0xDEu, 0x20u}, + {0xE0u, 0x20u}, {0xE4u, 0x10u}, - {0x83u, 0x04u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Fu, 0x04u}, - {0xACu, 0x04u}, + {0xEAu, 0x20u}, + {0xEEu, 0xC0u}, + {0x99u, 0x0Au}, + {0x9Au, 0x08u}, {0xAFu, 0x01u}, - {0xB1u, 0x08u}, - {0xEAu, 0x01u}, - {0xABu, 0x02u}, - {0xB0u, 0x02u}, - {0xE8u, 0x04u}, + {0x85u, 0x08u}, + {0x99u, 0x08u}, + {0xAAu, 0x08u}, + {0xB5u, 0x02u}, + {0xEAu, 0x02u}, {0x10u, 0x07u}, {0x11u, 0x01u}, - {0x1Au, 0x03u}, - {0x1Cu, 0x04u}, + {0x1Au, 0x07u}, + {0x1Cu, 0x07u}, {0x1Du, 0x01u}, {0x00u, 0xFFu}, {0x01u, 0xBFu}, @@ -2443,30 +2494,43 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT5_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; + /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { + 0x00u, 0x24u, 0x00u, 0x12u, 0x08u, 0x00u, 0x61u, 0x20u, 0x00u, 0x00u, 0x40u, 0x04u, 0x07u, 0x00u, 0xD8u, 0x24u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x03u, 0x04u, 0x00u, 0x00u, 0x18u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0xA2u, 0x24u, 0x08u, 0x09u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0xE0u, 0x07u, 0x3Fu, 0x38u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, + 0x63u, 0x04u, 0x50u, 0x00u, 0x02u, 0xCEu, 0xBFu, 0xD0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x20u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x77u, 0x80u, 0x08u, 0x00u, 0x39u, 0x00u, 0x06u, 0x60u, 0x04u, 0xC0u, 0x20u, 0x08u, 0xC6u, 0x00u, 0x00u, 0x9Fu, - 0x42u, 0x90u, 0x00u, 0x40u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x5Eu, 0x04u, 0xC6u, 0xC0u, 0x00u, 0x02u, - 0x00u, 0xC0u, 0x00u, 0x01u, 0xC2u, 0x00u, 0x04u, 0xFFu, 0x80u, 0x7Fu, 0x46u, 0x80u, 0x46u, 0x00u, 0x80u, 0x00u, - 0x80u, 0xFFu, 0x0Fu, 0x00u, 0x70u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x01u, 0x01u, - 0x32u, 0x06u, 0x40u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x11u, 0x00u, 0x01u, + 0x5Cu, 0x00u, 0x00u, 0x00u, 0x30u, 0x05u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x01u, 0x50u, 0x06u, + 0x11u, 0x04u, 0x22u, 0x03u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0x54u, 0x00u, 0x08u, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u, 0x0Cu, 0x00u, 0x24u, 0x00u, 0x10u, 0x00u, 0x08u, 0x03u, 0x00u, 0x04u, + 0x0Fu, 0x07u, 0x40u, 0x00u, 0x30u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x20u, 0x02u, 0x00u, 0x00u, 0x44u, 0x00u, + 0x16u, 0x04u, 0x30u, 0x00u, 0x05u, 0xBEu, 0xF0u, 0xCDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x11u, 0x11u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u}; + 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index e1a9a82..789c24b 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -450,8 +450,8 @@ .set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL .set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL .set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -459,9 +459,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -485,8 +485,8 @@ .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -494,9 +494,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1 @@ -567,34 +567,34 @@ .set NOR_SCK__SLW, CYREG_PRT3_SLW /* NOR_SPI */ -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_RxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20 @@ -602,34 +602,34 @@ .set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40 .set NOR_SPI_BSPIM_RxStsReg__6__POS, 6 .set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70 -.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0 -.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1 -.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK +.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL .set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01 .set NOR_SPI_BSPIM_TxStsReg__0__POS, 0 .set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02 .set NOR_SPI_BSPIM_TxStsReg__1__POS, 1 -.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04 .set NOR_SPI_BSPIM_TxStsReg__2__POS, 2 .set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08 @@ -637,9 +637,9 @@ .set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_TxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F -.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB03_MSK +.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB03_ST /* SCSI_In */ .set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1 @@ -1760,15 +1760,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1781,35 +1781,35 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE @@ -2673,8 +2673,6 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2682,13 +2680,13 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST /* Debug_Timer */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2803,6 +2801,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2810,67 +2810,58 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 6f16a1b..b2ef245 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -449,8 +449,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -458,9 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -484,8 +484,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -493,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -566,34 +566,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW /* NOR_SPI */ -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -601,34 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -636,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F -NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST /* SCSI_In */ SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -1759,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1780,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2672,8 +2672,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2681,13 +2679,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST /* Debug_Timer */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2802,6 +2800,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2809,67 +2809,58 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index a8e4fa9..3837ba0 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -449,8 +449,8 @@ SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -458,9 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -484,8 +484,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -493,9 +493,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -566,34 +566,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW ; NOR_SPI -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -601,34 +601,34 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 -NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 -NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 -NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 -NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 -NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -636,9 +636,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F -NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST ; SCSI_In SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -1759,15 +1759,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1780,35 +1780,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2672,8 +2672,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2681,13 +2679,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST ; Debug_Timer Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2802,6 +2800,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2809,67 +2809,58 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx index f3c0f70..678f845 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -5,16 +5,16 @@