From: Michael McMaster Date: Thu, 11 Jun 2015 23:44:34 +0000 (+1000) Subject: Adding configurable geometry support to firmware. X-Git-Tag: v4.03.00~1 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=94cc9e77bc5048862614c87c7fe191ee77add25c;p=SCSI2SD-V6.git Adding configurable geometry support to firmware. Fix for scsi2sd-util crashes on exit. --- diff --git a/readme.txt b/readme.txt index 67c16f33..4664ced3 100644 --- a/readme.txt +++ b/readme.txt @@ -35,10 +35,11 @@ Micro SD Card Interface USB Interface (firmware updates and config) USB 2.0 micro-B Power - 5V via standard molex drive connector. + 5V via standard molex drive connector + USB or self-powered using the SCSI host termination power. (v5 only) Dimensions - 10cm x 10cm x 1.5cm - Mounting holes to suit standard 2.5" - 3.5" drive bracket. + 10cm x 5cm x 1.5cm (v5) + 10cm x 10cm x 1.5cm (v3, v4) Performance @@ -95,6 +96,17 @@ Compatibility Device-type modifier: 0x4c Applix 1616 IMS MM/1 + NeXTcube + NeXTSTEP 3.3 + NeXTStation + Modified geometry settings are required to avoid "cylinder group too large" errors while formatting. + (To simulate Quantum Fireball 1050S) + 512 bytesPerSector + 139 sectorsPerTrack + 4 tracksPerCylinder + 4135 cylinder per volume + 1 spare sector per cylinder + 2051459 usable sectors on volume + Samplers diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index bb31e0d2..c4f9f4b4 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -32,7 +32,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0424; +static const uint16_t FIRMWARE_VERSION = 0x0430; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = diff --git a/software/SCSI2SD/src/diagnostic.c b/software/SCSI2SD/src/diagnostic.c index 709836ce..c35e6e24 100755 --- a/software/SCSI2SD/src/diagnostic.c +++ b/software/SCSI2SD/src/diagnostic.c @@ -99,11 +99,15 @@ void scsiReceiveDiagnostic() uint64 fromByteAddr = scsiByteAddress( scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->cfg->headsPerCylinder, + scsiDev.target->cfg->sectorsPerTrack, suppliedFmt, &scsiDev.data[6]); scsiSaveByteAddress( scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->cfg->headsPerCylinder, + scsiDev.target->cfg->sectorsPerTrack, translateFmt, fromByteAddr, &scsiDev.data[6]); diff --git a/software/SCSI2SD/src/geometry.c b/software/SCSI2SD/src/geometry.c index cbf71ce3..0666b5a2 100755 --- a/software/SCSI2SD/src/geometry.c +++ b/software/SCSI2SD/src/geometry.c @@ -46,36 +46,49 @@ uint32_t SCSISector2SD( // Standard mapping according to ECMA-107 and ISO/IEC 9293:1994 // Sector always starts at 1. There is no 0 sector. -uint64 CHS2LBA(uint32 c, uint8 h, uint32 s) +uint64_t CHS2LBA( + uint32_t c, + uint8_t h, + uint32_t s, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack) { return ( - (((uint64)c) * SCSI_HEADS_PER_CYLINDER + h) * - (uint64) SCSI_SECTORS_PER_TRACK + (((uint64_t)c) * headsPerCylinder + h) * + (uint64_t) sectorsPerTrack ) + (s - 1); } -void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s) +void LBA2CHS( + uint32_t lba, + uint32_t* c, + uint8_t* h, + uint32_t* s, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack) { - *c = lba / (SCSI_SECTORS_PER_TRACK * SCSI_HEADS_PER_CYLINDER); - *h = (lba / SCSI_SECTORS_PER_TRACK) % SCSI_HEADS_PER_CYLINDER; - *s = (lba % SCSI_SECTORS_PER_TRACK) + 1; + *c = lba / (((uint32_t) sectorsPerTrack) * headsPerCylinder); + *h = (lba / sectorsPerTrack) % headsPerCylinder; + *s = (lba % sectorsPerTrack) + 1; } -uint64 scsiByteAddress( +uint64_t scsiByteAddress( uint16_t bytesPerSector, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack, int format, - const uint8* addr) + const uint8_t* addr) { - uint64 result; + uint64_t result; switch (format) { case ADDRESS_BLOCK: { - uint32 lba = - (((uint32) addr[0]) << 24) + - (((uint32) addr[1]) << 16) + - (((uint32) addr[2]) << 8) + + uint32_t lba = + (((uint32_t) addr[0]) << 24) + + (((uint32_t) addr[1]) << 16) + + (((uint32_t) addr[2]) << 8) + addr[3]; result = (uint64_t) bytesPerSector * lba; @@ -83,38 +96,39 @@ uint64 scsiByteAddress( case ADDRESS_PHYSICAL_BYTE: { - uint32 cyl = - (((uint32) addr[0]) << 16) + - (((uint32) addr[1]) << 8) + + uint32_t cyl = + (((uint32_t) addr[0]) << 16) + + (((uint32_t) addr[1]) << 8) + addr[2]; - uint8 head = addr[3]; + uint8_t head = addr[3]; - uint32 bytes = - (((uint32) addr[4]) << 24) + - (((uint32) addr[5]) << 16) + - (((uint32) addr[6]) << 8) + + uint32_t bytes = + (((uint32_t) addr[4]) << 24) + + (((uint32_t) addr[5]) << 16) + + (((uint32_t) addr[6]) << 8) + addr[7]; - result = CHS2LBA(cyl, head, 1) * (uint64_t) bytesPerSector + bytes; + result = CHS2LBA(cyl, head, 1, headsPerCylinder, sectorsPerTrack) * + (uint64_t) bytesPerSector + bytes; } break; case ADDRESS_PHYSICAL_SECTOR: { uint32 cyl = - (((uint32) addr[0]) << 16) + - (((uint32) addr[1]) << 8) + + (((uint32_t) addr[0]) << 16) + + (((uint32_t) addr[1]) << 8) + addr[2]; uint8 head = scsiDev.data[3]; uint32 sector = - (((uint32) addr[4]) << 24) + - (((uint32) addr[5]) << 16) + - (((uint32) addr[6]) << 8) + + (((uint32_t) addr[4]) << 24) + + (((uint32_t) addr[5]) << 16) + + (((uint32_t) addr[6]) << 8) + addr[7]; - result = CHS2LBA(cyl, head, sector) * (uint64_t) bytesPerSector; + result = CHS2LBA(cyl, head, sector, headsPerCylinder, sectorsPerTrack) * (uint64_t) bytesPerSector; } break; default: @@ -127,12 +141,14 @@ uint64 scsiByteAddress( void scsiSaveByteAddress( uint16_t bytesPerSector, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack, int format, - uint64 byteAddr, - uint8* buf) + uint64_t byteAddr, + uint8_t* buf) { - uint32 lba = byteAddr / bytesPerSector; - uint32 byteOffset = byteAddr % bytesPerSector; + uint32_t lba = byteAddr / bytesPerSector; + uint32_t byteOffset = byteAddr % bytesPerSector; switch (format) { @@ -151,12 +167,12 @@ void scsiSaveByteAddress( case ADDRESS_PHYSICAL_BYTE: { - uint32 cyl; - uint8 head; - uint32 sector; - uint32 bytes; + uint32_t cyl; + uint8_t head; + uint32_t sector; + uint32_t bytes; - LBA2CHS(lba, &cyl, &head, §or); + LBA2CHS(lba, &cyl, &head, §or, headsPerCylinder, sectorsPerTrack); bytes = sector * bytesPerSector + byteOffset; @@ -174,11 +190,11 @@ void scsiSaveByteAddress( case ADDRESS_PHYSICAL_SECTOR: { - uint32 cyl; - uint8 head; - uint32 sector; + uint32_t cyl; + uint8_t head; + uint32_t sector; - LBA2CHS(lba, &cyl, &head, §or); + LBA2CHS(lba, &cyl, &head, §or, headsPerCylinder, sectorsPerTrack); buf[0] = cyl >> 16; buf[1] = cyl >> 8; diff --git a/software/SCSI2SD/src/geometry.h b/software/SCSI2SD/src/geometry.h index 6d1e7af2..8df3d4c9 100755 --- a/software/SCSI2SD/src/geometry.h +++ b/software/SCSI2SD/src/geometry.h @@ -22,12 +22,6 @@ #include "config.h" #include "sd.h" -// Max allowed by legacy IBM-PC Bios (6 bits) -#define SCSI_SECTORS_PER_TRACK 63 - -// MS-DOS up to 7.10 will crash on 256 heads. -#define SCSI_HEADS_PER_CYLINDER 255 - typedef enum { ADDRESS_BLOCK = 0, @@ -50,16 +44,36 @@ uint32_t SCSISector2SD( uint16_t bytesPerSector, uint32_t scsiSector); -uint64 CHS2LBA(uint32 c, uint8 h, uint32 s); -void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s); +uint64_t CHS2LBA( + uint32_t c, + uint8_t h, + uint32_t s, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack); +void LBA2CHS( + uint32_t lba, + uint32_t* c, + uint8_t* h, + uint32_t* s, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack); // Convert an address in the given SCSI_ADDRESS_FORMAT to // a linear byte address. // addr must be >= 8 bytes. -uint64 scsiByteAddress( - uint16_t bytesPerSector, int format, const uint8* addr); +uint64_t scsiByteAddress( + uint16_t bytesPerSector, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack, + int format, + const uint8_t* addr); void scsiSaveByteAddress( - uint16_t bytesPerSector, int format, uint64 byteAddr, uint8* buf); + uint16_t bytesPerSector, + uint16_t headsPerCylinder, + uint16_t sectorsPerTrack, + int format, + uint64_t byteAddr, + uint8_t* buf); #endif diff --git a/software/SCSI2SD/src/mode.c b/software/SCSI2SD/src/mode.c index b234549e..17ead1c6 100755 --- a/software/SCSI2SD/src/mode.c +++ b/software/SCSI2SD/src/mode.c @@ -97,7 +97,7 @@ static const uint8 FormatDevicePage[] = 0x00, 0x00, // No alternate sectors 0x00, 0x00, // No alternate tracks 0x00, 0x00, // No alternate tracks per lun -0x00, SCSI_SECTORS_PER_TRACK, // Sectors per track +0x00, 0x00, // Sectors per track, configurable 0xFF, 0xFF, // Data bytes per physical sector. Configurable. 0x00, 0x01, // Interleave 0x00, 0x00, // Track skew factor @@ -111,7 +111,7 @@ static const uint8 RigidDiskDriveGeometry[] = 0x04, // Page code 0x16, // Page length 0xFF, 0xFF, 0xFF, // Number of cylinders -SCSI_HEADS_PER_CYLINDER, // Number of heads +0x00, // Number of heads (replaced by configured value) 0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation 0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current 0x00, 0x1, // Drive step rate (units of 100ns) @@ -128,7 +128,7 @@ static const uint8 RigidDiskDriveGeometry_SCSI1[] = 0x04, // Page code 0x12, // Page length 0xFF, 0xFF, 0xFF, // Number of cylinders -SCSI_HEADS_PER_CYLINDER, // Number of heads +0x00, // Number of heads (replaced by configured value) 0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation 0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current 0x00, 0x1, // Drive step rate (units of 100ns) @@ -311,6 +311,10 @@ static void doModeSense( pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage)); if (pc != 0x01) { + uint16_t sectorsPerTrack = scsiDev.target->cfg->sectorsPerTrack; + scsiDev.data[idx+10] = sectorsPerTrack >> 8; + scsiDev.data[idx+11] = sectorsPerTrack & 0xFF; + // Fill out the configured bytes-per-sector uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; scsiDev.data[idx+12] = bytesPerSector >> 8; @@ -351,7 +355,9 @@ static void doModeSense( scsiDev.target->cfg->scsiSectors), &cyl, &head, - §or); + §or, + scsiDev.target->cfg->headsPerCylinder, + scsiDev.target->cfg->sectorsPerTrack); scsiDev.data[idx+2] = cyl >> 16; scsiDev.data[idx+3] = cyl >> 8; @@ -359,6 +365,8 @@ static void doModeSense( memcpy(&scsiDev.data[idx+6], &scsiDev.data[idx+2], 3); memcpy(&scsiDev.data[idx+9], &scsiDev.data[idx+2], 3); + + scsiDev.data[idx+5] = scsiDev.target->cfg->headsPerCylinder; } if ((scsiDev.compatMode >= COMPAT_SCSI2)) diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 6df123ee..bda3f9f6 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -207,40 +207,40 @@ /* USBFS_ep_1 */ #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x40u -#define USBFS_ep_1__INTC_NUMBER 6u +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x80u -#define USBFS_ep_2__INTC_NUMBER 7u +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x100u -#define USBFS_ep_3__INTC_NUMBER 8u +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u #define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ #define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x200u -#define USBFS_ep_4__INTC_NUMBER 9u +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u #define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 #define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -381,34 +381,34 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -416,9 +416,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -436,12 +436,14 @@ #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -449,9 +451,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST /* SD_SCK */ #define SD_SCK__0__MASK 0x04u @@ -1875,15 +1877,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1896,37 +1898,37 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -2377,10 +2379,10 @@ /* SD_RX_DMA_COMPLETE */ #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u -#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u #define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2399,10 +2401,10 @@ /* SD_TX_DMA_COMPLETE */ #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u -#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u #define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2804,10 +2806,10 @@ /* SCSI_TX_DMA_COMPLETE */ #define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u #define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 #define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2843,13 +2845,23 @@ #define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + /* SCSI_Filtered */ #define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2857,9 +2869,13 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK +#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u @@ -2890,12 +2906,12 @@ /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U @@ -2976,7 +2992,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000003Eu +#define CYDEV_INTR_RISING 0x0000007Eu #define CYDEV_PROJ_TYPE 2 #define CYDEV_PROJ_TYPE_BOOTLOADER 1 #define CYDEV_PROJ_TYPE_LOADABLE 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 7b14d7cf..8829a4f0 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 41u +#define CY_CFG_BASE_ADDR_COUNT 40u CYPACKED typedef struct { uint8 offset; @@ -383,40 +383,39 @@ void cyfitter_cfg(void) 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x4001003Eu, /* Base address: 0x40010000 Count: 62 */ - 0x40010137u, /* Base address: 0x40010100 Count: 55 */ - 0x40010246u, /* Base address: 0x40010200 Count: 70 */ - 0x40010350u, /* Base address: 0x40010300 Count: 80 */ - 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */ - 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */ - 0x40010654u, /* Base address: 0x40010600 Count: 84 */ - 0x40010750u, /* Base address: 0x40010700 Count: 80 */ - 0x40010851u, /* Base address: 0x40010800 Count: 81 */ - 0x40010958u, /* Base address: 0x40010900 Count: 88 */ - 0x40010A46u, /* Base address: 0x40010A00 Count: 70 */ - 0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */ - 0x40010C46u, /* Base address: 0x40010C00 Count: 70 */ - 0x40010D4Au, /* Base address: 0x40010D00 Count: 74 */ - 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */ - 0x4001145Fu, /* Base address: 0x40011400 Count: 95 */ - 0x40011558u, /* Base address: 0x40011500 Count: 88 */ - 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */ - 0x40011750u, /* Base address: 0x40011700 Count: 80 */ - 0x40011804u, /* Base address: 0x40011800 Count: 4 */ - 0x40011913u, /* Base address: 0x40011900 Count: 19 */ - 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */ + 0x40010036u, /* Base address: 0x40010000 Count: 54 */ + 0x4001013Du, /* Base address: 0x40010100 Count: 61 */ + 0x40010243u, /* Base address: 0x40010200 Count: 67 */ + 0x40010358u, /* Base address: 0x40010300 Count: 88 */ + 0x40010448u, /* Base address: 0x40010400 Count: 72 */ + 0x40010555u, /* Base address: 0x40010500 Count: 85 */ + 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */ + 0x40010746u, /* Base address: 0x40010700 Count: 70 */ + 0x4001083Fu, /* Base address: 0x40010800 Count: 63 */ + 0x40010948u, /* Base address: 0x40010900 Count: 72 */ + 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */ + 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */ + 0x40010C42u, /* Base address: 0x40010C00 Count: 66 */ + 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */ + 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */ + 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */ + 0x4001142Cu, /* Base address: 0x40011400 Count: 44 */ + 0x40011550u, /* Base address: 0x40011500 Count: 80 */ + 0x4001163Eu, /* Base address: 0x40011600 Count: 62 */ + 0x4001173Fu, /* Base address: 0x40011700 Count: 63 */ + 0x40011904u, /* Base address: 0x40011900 Count: 4 */ + 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ - 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */ - 0x4001420Bu, /* Base address: 0x40014200 Count: 11 */ - 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */ - 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ - 0x40014518u, /* Base address: 0x40014500 Count: 24 */ - 0x40014611u, /* Base address: 0x40014600 Count: 17 */ - 0x40014711u, /* Base address: 0x40014700 Count: 17 */ - 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */ - 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */ - 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ - 0x40014D06u, /* Base address: 0x40014D00 Count: 6 */ + 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */ + 0x40014211u, /* Base address: 0x40014200 Count: 17 */ + 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ + 0x40014411u, /* Base address: 0x40014400 Count: 17 */ + 0x40014517u, /* Base address: 0x40014500 Count: 23 */ + 0x40014608u, /* Base address: 0x40014600 Count: 8 */ + 0x4001470Du, /* Base address: 0x40014700 Count: 13 */ + 0x40014806u, /* Base address: 0x40014800 Count: 6 */ + 0x40014908u, /* Base address: 0x40014900 Count: 8 */ + 0x40014D04u, /* Base address: 0x40014D00 Count: 4 */ 0x40015002u, /* Base address: 0x40015000 Count: 2 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -424,45 +423,49 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x36u}, - {0x00u, 0x04u}, - {0x01u, 0x11u}, - {0x18u, 0x0Cu}, + {0x0Au, 0x4Bu}, + {0x00u, 0x11u}, + {0x01u, 0x02u}, + {0x18u, 0x08u}, {0x19u, 0x04u}, {0x1Cu, 0x71u}, - {0x20u, 0x60u}, - {0x21u, 0xC0u}, + {0x20u, 0xA0u}, + {0x21u, 0x68u}, {0x2Cu, 0x0Eu}, - {0x30u, 0x05u}, + {0x30u, 0x0Au}, {0x31u, 0x0Cu}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, {0x20u, 0x02u}, - {0x86u, 0x0Fu}, - {0x02u, 0x07u}, - {0x06u, 0x70u}, - {0x08u, 0xAAu}, - {0x0Au, 0x55u}, - {0x0Eu, 0x08u}, - {0x11u, 0x01u}, - {0x15u, 0x08u}, - {0x20u, 0x44u}, - {0x22u, 0x88u}, - {0x26u, 0x80u}, - {0x28u, 0x99u}, - {0x29u, 0x02u}, - {0x2Au, 0x22u}, - {0x2Du, 0x04u}, - {0x30u, 0x0Fu}, - {0x31u, 0x04u}, - {0x33u, 0x02u}, - {0x34u, 0xF0u}, - {0x35u, 0x08u}, - {0x37u, 0x01u}, + {0x84u, 0x0Fu}, + {0x00u, 0x80u}, + {0x04u, 0x10u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x28u}, + {0x10u, 0x01u}, + {0x14u, 0x32u}, + {0x15u, 0x04u}, + {0x16u, 0x44u}, + {0x1Au, 0x04u}, + {0x1Du, 0x08u}, + {0x24u, 0x4Cu}, + {0x26u, 0x32u}, + {0x29u, 0x01u}, + {0x2Eu, 0x7Eu}, + {0x30u, 0x0Eu}, + {0x31u, 0x08u}, + {0x32u, 0x70u}, + {0x33u, 0x04u}, + {0x34u, 0x01u}, + {0x35u, 0x01u}, + {0x36u, 0x80u}, + {0x37u, 0x02u}, + {0x3Eu, 0x50u}, {0x3Fu, 0x55u}, - {0x40u, 0x56u}, - {0x41u, 0x02u}, - {0x42u, 0x30u}, + {0x40u, 0x42u}, + {0x41u, 0x03u}, + {0x42u, 0x50u}, {0x45u, 0xF2u}, {0x46u, 0xCDu}, {0x47u, 0x0Eu}, @@ -484,261 +487,253 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x85u, 0x08u}, - {0x8Bu, 0x3Fu}, - {0x8Du, 0x40u}, - {0x91u, 0x01u}, - {0x93u, 0x14u}, - {0x95u, 0x19u}, - {0x97u, 0x22u}, - {0x99u, 0x26u}, - {0x9Bu, 0x19u}, - {0xABu, 0x02u}, - {0xB1u, 0x07u}, - {0xB3u, 0x40u}, - {0xB5u, 0x38u}, - {0xBFu, 0x04u}, - {0xD9u, 0x04u}, - {0xDCu, 0x10u}, + {0x88u, 0x01u}, + {0xB6u, 0x01u}, + {0xBEu, 0x40u}, + {0xD8u, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x80u}, - {0x01u, 0x22u}, - {0x03u, 0x20u}, - {0x11u, 0x22u}, - {0x13u, 0x04u}, - {0x19u, 0x02u}, - {0x1Bu, 0x20u}, + {0x00u, 0x41u}, + {0x03u, 0x10u}, + {0x05u, 0x10u}, + {0x0Au, 0x10u}, + {0x0Bu, 0x44u}, + {0x11u, 0x40u}, + {0x12u, 0x20u}, + {0x18u, 0x40u}, + {0x19u, 0x48u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x12u}, + {0x1Du, 0x80u}, {0x20u, 0x04u}, - {0x21u, 0x80u}, - {0x22u, 0x05u}, - {0x25u, 0x31u}, - {0x26u, 0x01u}, - {0x27u, 0x58u}, - {0x28u, 0x02u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x24u}, - {0x2Fu, 0x04u}, - {0x31u, 0x06u}, - {0x35u, 0x20u}, - {0x36u, 0x01u}, - {0x37u, 0x08u}, - {0x3Du, 0x04u}, - {0x3Eu, 0x90u}, - {0x41u, 0x30u}, - {0x43u, 0x08u}, - {0x49u, 0x10u}, - {0x4Au, 0x01u}, - {0x4Bu, 0x0Au}, - {0x50u, 0x08u}, - {0x52u, 0x90u}, - {0x5Au, 0x8Au}, - {0x5Bu, 0x10u}, - {0x60u, 0x54u}, - {0x61u, 0x80u}, - {0x68u, 0x40u}, - {0x69u, 0x50u}, - {0x6Au, 0x04u}, - {0x70u, 0x02u}, - {0x72u, 0x20u}, - {0x73u, 0x06u}, - {0x83u, 0x01u}, - {0x85u, 0x10u}, - {0x8Cu, 0x08u}, - {0xC0u, 0x0Fu}, - {0xC4u, 0x0Eu}, - {0xCAu, 0x2Cu}, - {0xCCu, 0xE3u}, - {0xCEu, 0x70u}, - {0xD0u, 0x06u}, - {0xD2u, 0x0Cu}, + {0x21u, 0x02u}, + {0x23u, 0x22u}, + {0x2Bu, 0x04u}, + {0x31u, 0x04u}, + {0x32u, 0x80u}, + {0x3Au, 0x40u}, + {0x41u, 0x10u}, + {0x42u, 0x10u}, + {0x43u, 0x02u}, + {0x48u, 0x01u}, + {0x49u, 0x02u}, + {0x4Bu, 0x04u}, + {0x50u, 0x10u}, + {0x52u, 0x04u}, + {0x53u, 0x80u}, + {0x59u, 0x40u}, + {0x5Au, 0x08u}, + {0x5Bu, 0x22u}, + {0x60u, 0x04u}, + {0x61u, 0x82u}, + {0x63u, 0x20u}, + {0x68u, 0x90u}, + {0x69u, 0x10u}, + {0x6Au, 0x80u}, + {0x70u, 0x60u}, + {0x72u, 0x40u}, + {0x73u, 0x10u}, + {0x81u, 0x02u}, + {0x83u, 0x10u}, + {0x85u, 0x40u}, + {0x88u, 0x40u}, + {0x89u, 0x08u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x10u}, + {0xC0u, 0x4Du}, + {0xC2u, 0x0Eu}, + {0xC4u, 0x05u}, + {0xCAu, 0x04u}, + {0xCCu, 0x0Au}, + {0xCEu, 0x08u}, + {0xD0u, 0x07u}, + {0xD2u, 0x08u}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE2u, 0x01u}, - {0xE4u, 0x0Cu}, - {0xE6u, 0x10u}, - {0x00u, 0x08u}, - {0x01u, 0x47u}, - {0x02u, 0x04u}, - {0x03u, 0x88u}, - {0x07u, 0x80u}, - {0x09u, 0x95u}, - {0x0Bu, 0x2Au}, - {0x11u, 0x03u}, - {0x13u, 0x0Cu}, - {0x14u, 0x04u}, - {0x16u, 0x08u}, - {0x17u, 0x70u}, - {0x18u, 0x08u}, - {0x19u, 0xA6u}, - {0x1Au, 0x14u}, - {0x1Bu, 0x59u}, - {0x1Cu, 0x08u}, - {0x1Eu, 0x05u}, - {0x23u, 0x03u}, - {0x25u, 0x01u}, - {0x2Bu, 0x02u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x06u}, - {0x30u, 0x01u}, - {0x31u, 0x0Fu}, - {0x32u, 0x0Cu}, - {0x34u, 0x02u}, - {0x35u, 0xF0u}, - {0x36u, 0x10u}, - {0x3Au, 0x08u}, - {0x3Bu, 0x02u}, + {0xE0u, 0x06u}, + {0xE2u, 0x10u}, + {0xE4u, 0x04u}, + {0xE6u, 0x20u}, + {0x09u, 0x05u}, + {0x0Bu, 0x0Au}, + {0x0Du, 0x0Fu}, + {0x0Eu, 0x01u}, + {0x0Fu, 0xF0u}, + {0x10u, 0x01u}, + {0x12u, 0x02u}, + {0x15u, 0x60u}, + {0x17u, 0x90u}, + {0x19u, 0x30u}, + {0x1Bu, 0xC0u}, + {0x1Du, 0x06u}, + {0x1Fu, 0x09u}, + {0x21u, 0x03u}, + {0x23u, 0x0Cu}, + {0x25u, 0x50u}, + {0x26u, 0x02u}, + {0x27u, 0xA0u}, + {0x30u, 0x03u}, + {0x37u, 0xFFu}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x19u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, - {0x84u, 0x03u}, - {0x88u, 0x10u}, - {0x8Au, 0x60u}, - {0x8Cu, 0x18u}, - {0x8Eu, 0x03u}, - {0x90u, 0x20u}, - {0x92u, 0x5Cu}, - {0x96u, 0x1Fu}, - {0x98u, 0x3Fu}, - {0x9Au, 0x40u}, - {0xA0u, 0x80u}, - {0xA5u, 0x01u}, - {0xA6u, 0x01u}, - {0xA8u, 0x27u}, - {0xA9u, 0x02u}, - {0xAAu, 0x50u}, - {0xB0u, 0x80u}, - {0xB1u, 0x02u}, - {0xB2u, 0x70u}, - {0xB3u, 0x01u}, - {0xB4u, 0x0Fu}, - {0xBAu, 0x08u}, - {0xBEu, 0x01u}, - {0xBFu, 0x05u}, + {0x83u, 0x1Fu}, + {0x85u, 0x3Fu}, + {0x86u, 0x70u}, + {0x87u, 0x40u}, + {0x89u, 0x03u}, + {0x8Cu, 0x44u}, + {0x8Du, 0x20u}, + {0x8Eu, 0x88u}, + {0x8Fu, 0x5Cu}, + {0x94u, 0x99u}, + {0x95u, 0x18u}, + {0x96u, 0x22u}, + {0x97u, 0x03u}, + {0x98u, 0xAAu}, + {0x9Au, 0x55u}, + {0x9Bu, 0x01u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x07u}, + {0x9Fu, 0x60u}, + {0xA1u, 0x02u}, + {0xA5u, 0x27u}, + {0xA6u, 0x08u}, + {0xA7u, 0x50u}, + {0xA9u, 0x80u}, + {0xAAu, 0x80u}, + {0xB3u, 0x80u}, + {0xB4u, 0xF0u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x0Fu}, + {0xB7u, 0x70u}, + {0xBBu, 0x80u}, + {0xBFu, 0x04u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x81u}, - {0x02u, 0x90u}, - {0x03u, 0x18u}, - {0x05u, 0x01u}, - {0x09u, 0x01u}, - {0x0Au, 0x18u}, - {0x0Eu, 0x2Au}, - {0x11u, 0x24u}, - {0x12u, 0x40u}, - {0x16u, 0x02u}, - {0x19u, 0x30u}, - {0x1Au, 0x88u}, - {0x1Bu, 0x08u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x3Au}, - {0x20u, 0x50u}, - {0x26u, 0x02u}, - {0x27u, 0x04u}, - {0x28u, 0x28u}, - {0x2Du, 0x04u}, - {0x2Fu, 0x84u}, - {0x35u, 0x20u}, - {0x36u, 0x02u}, + {0x00u, 0x40u}, + {0x03u, 0x20u}, + {0x05u, 0x40u}, + {0x09u, 0x20u}, + {0x0Au, 0x12u}, + {0x0Cu, 0x02u}, + {0x0Fu, 0x80u}, + {0x10u, 0x20u}, + {0x13u, 0x10u}, + {0x17u, 0x04u}, + {0x19u, 0x40u}, + {0x1Au, 0x02u}, + {0x1Bu, 0x30u}, + {0x1Cu, 0x80u}, + {0x20u, 0x06u}, + {0x21u, 0xB0u}, + {0x22u, 0x24u}, + {0x23u, 0x08u}, + {0x25u, 0x40u}, + {0x28u, 0x08u}, + {0x29u, 0x08u}, + {0x2Bu, 0x80u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x04u}, + {0x31u, 0x80u}, + {0x32u, 0x08u}, + {0x33u, 0x10u}, + {0x34u, 0x10u}, + {0x35u, 0x40u}, {0x37u, 0x04u}, - {0x3Du, 0x22u}, - {0x3Eu, 0x04u}, - {0x45u, 0x04u}, - {0x47u, 0x04u}, - {0x58u, 0x90u}, - {0x5Au, 0x02u}, - {0x5Bu, 0x08u}, - {0x5Fu, 0x80u}, - {0x60u, 0x02u}, - {0x61u, 0x06u}, - {0x62u, 0x05u}, - {0x63u, 0x08u}, - {0x66u, 0x80u}, - {0x6Du, 0x14u}, - {0x6Fu, 0x22u}, - {0x83u, 0x08u}, - {0x84u, 0x90u}, - {0x86u, 0x10u}, - {0x87u, 0x80u}, - {0x88u, 0x10u}, - {0x89u, 0x10u}, - {0x8Au, 0x02u}, - {0x8Du, 0x40u}, - {0x8Fu, 0x02u}, - {0x91u, 0x60u}, - {0x92u, 0x04u}, - {0x93u, 0x08u}, - {0x94u, 0x50u}, - {0x95u, 0x04u}, - {0x96u, 0x90u}, - {0x99u, 0x02u}, - {0x9Au, 0x38u}, - {0x9Bu, 0x42u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x34u}, - {0x9Eu, 0x80u}, - {0xA0u, 0x02u}, - {0xA1u, 0x11u}, - {0xA2u, 0x80u}, - {0xA5u, 0x02u}, - {0xA7u, 0x0Cu}, - {0xA9u, 0x10u}, - {0xB6u, 0x01u}, - {0xC0u, 0x1Fu}, - {0xC2u, 0xEEu}, - {0xC4u, 0x8Eu}, - {0xCAu, 0xE6u}, - {0xCCu, 0xE0u}, - {0xCEu, 0xE0u}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x1Fu}, - {0xE2u, 0xC4u}, + {0x38u, 0x64u}, + {0x3Au, 0x02u}, + {0x3Fu, 0xA0u}, + {0x58u, 0x66u}, + {0x5Du, 0x80u}, + {0x5Fu, 0x20u}, + {0x61u, 0x04u}, + {0x62u, 0x80u}, + {0x63u, 0x48u}, + {0x65u, 0x30u}, + {0x66u, 0x40u}, + {0x67u, 0x02u}, + {0x6Du, 0x28u}, + {0x6Eu, 0x80u}, + {0x6Fu, 0x10u}, + {0x80u, 0x30u}, + {0x85u, 0x80u}, + {0x86u, 0x40u}, + {0x87u, 0xA0u}, + {0x88u, 0x42u}, + {0x8Au, 0x0Au}, + {0x8Du, 0x04u}, + {0x90u, 0x60u}, + {0x91u, 0x10u}, + {0x92u, 0xF0u}, + {0x93u, 0x14u}, + {0x94u, 0x01u}, + {0x95u, 0x60u}, + {0x96u, 0x08u}, + {0x97u, 0x40u}, + {0x99u, 0x08u}, + {0x9Du, 0x14u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x10u}, + {0xA0u, 0xA0u}, + {0xA3u, 0x82u}, + {0xA4u, 0x45u}, + {0xA5u, 0x40u}, + {0xA6u, 0xA0u}, + {0xA7u, 0x04u}, + {0xAAu, 0x04u}, + {0xACu, 0x14u}, + {0xADu, 0x10u}, + {0xB7u, 0x02u}, + {0xC0u, 0x85u}, + {0xC2u, 0x17u}, + {0xC4u, 0x26u}, + {0xCAu, 0xC7u}, + {0xCCu, 0x7Eu}, + {0xCEu, 0x3Fu}, + {0xD6u, 0x3Fu}, + {0xD8u, 0x3Fu}, + {0xE0u, 0x04u}, + {0xE2u, 0x0Au}, {0xE4u, 0x08u}, - {0xE6u, 0xE2u}, - {0xE8u, 0x01u}, - {0xEEu, 0x02u}, - {0x02u, 0xFFu}, - {0x04u, 0x0Fu}, - {0x05u, 0x0Fu}, - {0x06u, 0xF0u}, - {0x08u, 0x69u}, - {0x09u, 0x90u}, - {0x0Au, 0x96u}, - {0x0Bu, 0x2Fu}, - {0x0Cu, 0xFFu}, - {0x10u, 0x33u}, - {0x12u, 0xCCu}, - {0x13u, 0x70u}, - {0x15u, 0x03u}, - {0x16u, 0xFFu}, - {0x17u, 0x0Cu}, - {0x18u, 0xFFu}, - {0x1Bu, 0x80u}, - {0x1Du, 0xC0u}, - {0x1Fu, 0x1Fu}, - {0x21u, 0x06u}, - {0x23u, 0x09u}, - {0x25u, 0x05u}, - {0x27u, 0x0Au}, - {0x29u, 0xA0u}, - {0x2Au, 0xFFu}, - {0x2Bu, 0x4Fu}, - {0x2Cu, 0x55u}, - {0x2Eu, 0xAAu}, - {0x2Fu, 0x80u}, - {0x31u, 0x7Fu}, - {0x32u, 0xFFu}, - {0x35u, 0x80u}, - {0x3Au, 0x08u}, + {0xE6u, 0x24u}, + {0xE8u, 0x0Bu}, + {0xEEu, 0x01u}, + {0x02u, 0x07u}, + {0x07u, 0x10u}, + {0x09u, 0x0Au}, + {0x0Bu, 0x05u}, + {0x0Cu, 0x44u}, + {0x0Du, 0x04u}, + {0x0Eu, 0x88u}, + {0x0Fu, 0x08u}, + {0x11u, 0x10u}, + {0x13u, 0x20u}, + {0x14u, 0x99u}, + {0x16u, 0x22u}, + {0x17u, 0x07u}, + {0x1Eu, 0x70u}, + {0x1Fu, 0x08u}, + {0x22u, 0x80u}, + {0x23u, 0x20u}, + {0x24u, 0xAAu}, + {0x25u, 0x09u}, + {0x26u, 0x55u}, + {0x27u, 0x02u}, + {0x2Au, 0x08u}, + {0x30u, 0x0Fu}, + {0x33u, 0x0Fu}, + {0x35u, 0x30u}, + {0x36u, 0xF0u}, {0x3Fu, 0x10u}, {0x56u, 0x08u}, {0x58u, 0x04u}, @@ -747,479 +742,441 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x83u, 0x7Cu}, - {0x84u, 0x40u}, - {0x85u, 0x48u}, - {0x86u, 0x80u}, - {0x87u, 0x03u}, - {0x88u, 0x20u}, - {0x8Au, 0x18u}, - {0x92u, 0x01u}, - {0x93u, 0x01u}, - {0x94u, 0x18u}, - {0x95u, 0x70u}, - {0x96u, 0x25u}, - {0x98u, 0x2Eu}, - {0x99u, 0x04u}, - {0x9Au, 0x10u}, - {0x9Bu, 0x23u}, - {0x9Du, 0x11u}, - {0x9Fu, 0x02u}, - {0xA0u, 0x08u}, - {0xA2u, 0x33u}, - {0xA6u, 0x80u}, - {0xAAu, 0x40u}, - {0xAFu, 0x02u}, - {0xB0u, 0x07u}, - {0xB1u, 0x0Fu}, - {0xB2u, 0xC0u}, - {0xB3u, 0x70u}, - {0xB4u, 0x38u}, - {0xBAu, 0x20u}, - {0xBEu, 0x04u}, - {0xBFu, 0x04u}, - {0xD4u, 0x01u}, + {0x84u, 0x10u}, + {0x85u, 0x69u}, + {0x86u, 0x20u}, + {0x87u, 0x96u}, + {0x88u, 0x06u}, + {0x8Au, 0x09u}, + {0x8Bu, 0xFFu}, + {0x8Cu, 0x07u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0xFFu}, + {0x90u, 0x03u}, + {0x91u, 0x0Fu}, + {0x92u, 0x0Cu}, + {0x93u, 0xF0u}, + {0x94u, 0x05u}, + {0x95u, 0xFFu}, + {0x96u, 0x0Au}, + {0x99u, 0xFFu}, + {0x9Au, 0x02u}, + {0xA2u, 0x10u}, + {0xA3u, 0xFFu}, + {0xA6u, 0x20u}, + {0xA8u, 0x01u}, + {0xA9u, 0x55u}, + {0xABu, 0xAAu}, + {0xADu, 0x33u}, + {0xAEu, 0x03u}, + {0xAFu, 0xCCu}, + {0xB0u, 0x0Fu}, + {0xB4u, 0x30u}, + {0xB7u, 0xFFu}, + {0xBAu, 0x02u}, + {0xBBu, 0x80u}, + {0xBEu, 0x10u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDDu, 0x10u}, + {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0x88u}, - {0x02u, 0x04u}, - {0x03u, 0x40u}, - {0x04u, 0x08u}, - {0x05u, 0x10u}, - {0x08u, 0x02u}, - {0x0Au, 0x18u}, - {0x0Eu, 0x64u}, - {0x11u, 0x20u}, - {0x12u, 0x01u}, - {0x14u, 0x50u}, - {0x15u, 0x02u}, - {0x16u, 0x08u}, - {0x19u, 0x08u}, - {0x1Cu, 0x20u}, - {0x1Du, 0x10u}, - {0x1Eu, 0x40u}, - {0x1Fu, 0x10u}, + {0x00u, 0x40u}, + {0x01u, 0x02u}, + {0x04u, 0x40u}, + {0x06u, 0x20u}, + {0x07u, 0x08u}, + {0x0Au, 0x12u}, + {0x0Eu, 0x90u}, + {0x0Fu, 0x04u}, + {0x10u, 0x80u}, + {0x11u, 0x10u}, + {0x13u, 0x08u}, + {0x14u, 0x10u}, + {0x15u, 0x01u}, + {0x16u, 0x12u}, + {0x17u, 0x10u}, + {0x19u, 0x02u}, + {0x1Au, 0x02u}, + {0x1Du, 0x20u}, + {0x1Eu, 0x80u}, {0x20u, 0x08u}, - {0x21u, 0x02u}, - {0x23u, 0x80u}, - {0x25u, 0x09u}, - {0x29u, 0xA8u}, + {0x21u, 0x08u}, + {0x27u, 0x01u}, + {0x29u, 0x08u}, {0x2Bu, 0x40u}, + {0x2Du, 0x20u}, + {0x2Eu, 0x02u}, {0x2Fu, 0x01u}, - {0x31u, 0x02u}, - {0x32u, 0x08u}, - {0x33u, 0x50u}, - {0x34u, 0x40u}, - {0x35u, 0x01u}, - {0x36u, 0x10u}, - {0x37u, 0x04u}, - {0x39u, 0x24u}, - {0x3Du, 0x02u}, - {0x3Eu, 0x04u}, - {0x4Cu, 0x0Cu}, - {0x58u, 0x80u}, - {0x59u, 0x04u}, - {0x5Bu, 0x20u}, - {0x5Fu, 0x80u}, - {0x60u, 0x38u}, - {0x62u, 0x40u}, - {0x63u, 0x02u}, - {0x80u, 0x10u}, - {0x88u, 0x04u}, - {0x8Eu, 0x0Au}, - {0x8Fu, 0x40u}, - {0x91u, 0xE4u}, - {0x92u, 0x18u}, - {0x98u, 0x02u}, - {0x99u, 0x22u}, - {0x9Au, 0xADu}, - {0x9Bu, 0x52u}, - {0x9Cu, 0x28u}, - {0x9Du, 0x80u}, - {0x9Eu, 0x42u}, - {0xA0u, 0x02u}, - {0xA1u, 0x14u}, - {0xA3u, 0x24u}, - {0xA4u, 0x10u}, - {0xABu, 0x80u}, - {0xADu, 0x01u}, - {0xAEu, 0x11u}, - {0xAFu, 0x20u}, - {0xB1u, 0x20u}, - {0xC0u, 0x6Fu}, - {0xC2u, 0x7Eu}, - {0xC4u, 0x73u}, - {0xCAu, 0x1Fu}, - {0xCCu, 0xFFu}, - {0xCEu, 0xC6u}, - {0xD6u, 0x1Eu}, - {0xD8u, 0x0Eu}, - {0xE4u, 0x01u}, - {0xE6u, 0x10u}, - {0xE8u, 0x0Au}, - {0xEAu, 0x01u}, - {0xEEu, 0x02u}, - {0x00u, 0x04u}, - {0x01u, 0x33u}, - {0x02u, 0x20u}, - {0x03u, 0xCCu}, - {0x04u, 0x42u}, - {0x05u, 0x69u}, - {0x07u, 0x96u}, - {0x08u, 0x01u}, - {0x0Au, 0x5Eu}, - {0x0Bu, 0xFFu}, - {0x10u, 0x77u}, - {0x12u, 0x08u}, - {0x14u, 0x39u}, - {0x15u, 0xFFu}, - {0x16u, 0x06u}, - {0x19u, 0x0Fu}, - {0x1Bu, 0xF0u}, - {0x1Cu, 0x46u}, - {0x1Fu, 0xFFu}, - {0x20u, 0x46u}, - {0x25u, 0xFFu}, - {0x26u, 0x46u}, - {0x28u, 0x42u}, - {0x2Au, 0x04u}, - {0x2Bu, 0xFFu}, - {0x2Cu, 0x46u}, - {0x2Du, 0x55u}, - {0x2Fu, 0xAAu}, - {0x30u, 0x08u}, - {0x32u, 0x0Fu}, - {0x33u, 0xFFu}, + {0x30u, 0x02u}, + {0x31u, 0x08u}, + {0x32u, 0x40u}, + {0x36u, 0x28u}, + {0x37u, 0x01u}, + {0x38u, 0x48u}, + {0x39u, 0x20u}, + {0x3Cu, 0x40u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x08u}, + {0x5Bu, 0xA0u}, + {0x60u, 0x09u}, + {0x68u, 0x02u}, + {0x80u, 0x01u}, + {0x83u, 0x10u}, + {0x85u, 0x02u}, + {0x89u, 0x10u}, + {0x8Au, 0x40u}, + {0x8Cu, 0x24u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x02u}, + {0x90u, 0x40u}, + {0x91u, 0x30u}, + {0x92u, 0xF0u}, + {0x93u, 0x46u}, + {0x94u, 0x01u}, + {0x95u, 0x01u}, + {0x99u, 0x28u}, + {0x9Bu, 0x98u}, + {0x9Cu, 0x18u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x80u}, + {0xA1u, 0x04u}, + {0xA2u, 0xA8u}, + {0xA3u, 0x06u}, + {0xA4u, 0x06u}, + {0xA6u, 0x02u}, + {0xABu, 0xB0u}, + {0xACu, 0x04u}, + {0xB2u, 0x04u}, + {0xB3u, 0x08u}, + {0xB5u, 0x50u}, + {0xB6u, 0x02u}, + {0xC0u, 0xE9u}, + {0xC2u, 0x75u}, + {0xC4u, 0xFEu}, + {0xCAu, 0xB3u}, + {0xCCu, 0xEBu}, + {0xCEu, 0x7Eu}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x0Cu}, + {0xE0u, 0x05u}, + {0xE2u, 0x20u}, + {0xE4u, 0x08u}, + {0xE6u, 0x80u}, + {0xEAu, 0x09u}, + {0xECu, 0x04u}, + {0xEEu, 0x10u}, + {0x00u, 0x0Du}, + {0x04u, 0x01u}, + {0x05u, 0x0Fu}, + {0x06u, 0x32u}, + {0x08u, 0x62u}, + {0x09u, 0x03u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x0Cu}, + {0x10u, 0x02u}, + {0x11u, 0x05u}, + {0x12u, 0x0Du}, + {0x13u, 0x0Au}, + {0x14u, 0x0Du}, + {0x15u, 0x20u}, + {0x17u, 0x4Fu}, + {0x1Au, 0x10u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x54u}, + {0x1Fu, 0x70u}, + {0x20u, 0x0Du}, + {0x24u, 0x0Du}, + {0x25u, 0x06u}, + {0x27u, 0x09u}, + {0x29u, 0x10u}, + {0x2Bu, 0x2Fu}, + {0x2Cu, 0x0Du}, + {0x2Du, 0x40u}, + {0x2Fu, 0x1Fu}, + {0x30u, 0x0Fu}, + {0x31u, 0x7Fu}, {0x34u, 0x70u}, - {0x38u, 0x08u}, - {0x3Au, 0x30u}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x01u}, + {0x3Au, 0x02u}, + {0x54u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Bu, 0x04u}, {0x5Cu, 0x10u}, + {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0xFFu}, - {0x86u, 0xFFu}, - {0x87u, 0xFFu}, - {0x88u, 0x50u}, - {0x8Au, 0xA0u}, - {0x8Bu, 0xFFu}, - {0x8Cu, 0x09u}, - {0x8Du, 0x05u}, - {0x8Eu, 0x06u}, - {0x8Fu, 0x0Au}, - {0x90u, 0x05u}, - {0x92u, 0x0Au}, - {0x94u, 0x90u}, - {0x95u, 0x0Fu}, - {0x96u, 0x60u}, - {0x97u, 0xF0u}, - {0x9Bu, 0xFFu}, - {0x9Cu, 0x03u}, - {0x9Du, 0x30u}, - {0x9Eu, 0x0Cu}, - {0x9Fu, 0xC0u}, - {0xA0u, 0x30u}, - {0xA1u, 0x03u}, - {0xA2u, 0xC0u}, - {0xA3u, 0x0Cu}, + {0x80u, 0x96u}, + {0x82u, 0x69u}, + {0x85u, 0x02u}, + {0x87u, 0x11u}, + {0x88u, 0x0Fu}, + {0x8Au, 0xF0u}, + {0x8Du, 0x01u}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0x02u}, + {0x90u, 0x55u}, + {0x92u, 0xAAu}, + {0x95u, 0x02u}, + {0x96u, 0xFFu}, + {0x97u, 0x05u}, + {0x99u, 0x02u}, + {0x9Au, 0xFFu}, + {0x9Bu, 0x09u}, + {0x9Cu, 0x33u}, + {0x9Du, 0x02u}, + {0x9Eu, 0xCCu}, + {0x9Fu, 0x01u}, {0xA4u, 0xFFu}, - {0xA5u, 0x50u}, - {0xA7u, 0xA0u}, - {0xA8u, 0x0Fu}, - {0xA9u, 0x90u}, - {0xAAu, 0xF0u}, - {0xABu, 0x60u}, - {0xADu, 0x09u}, - {0xAFu, 0x06u}, - {0xB0u, 0xFFu}, - {0xB1u, 0xFFu}, - {0xBEu, 0x01u}, - {0xBFu, 0x01u}, - {0xD4u, 0x40u}, - {0xD6u, 0x04u}, + {0xA8u, 0xFFu}, + {0xB1u, 0x03u}, + {0xB3u, 0x08u}, + {0xB4u, 0xFFu}, + {0xB5u, 0x10u}, + {0xB7u, 0x04u}, + {0xBAu, 0x20u}, + {0xBBu, 0x02u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x91u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x01u}, - {0x03u, 0x2Au}, - {0x04u, 0x04u}, + {0x01u, 0x20u}, + {0x02u, 0x80u}, + {0x03u, 0x02u}, + {0x04u, 0x08u}, {0x05u, 0x10u}, - {0x06u, 0x40u}, - {0x08u, 0x44u}, - {0x0Bu, 0x80u}, - {0x0Du, 0x03u}, - {0x0Eu, 0x21u}, - {0x10u, 0x88u}, - {0x11u, 0x04u}, + {0x07u, 0x40u}, + {0x08u, 0x20u}, + {0x0Au, 0x10u}, + {0x0Bu, 0x41u}, + {0x0Cu, 0x08u}, + {0x0Eu, 0x8Au}, + {0x12u, 0x08u}, + {0x13u, 0x08u}, + {0x15u, 0x06u}, {0x16u, 0x02u}, - {0x17u, 0x15u}, - {0x18u, 0x80u}, - {0x1Du, 0x10u}, - {0x1Eu, 0x64u}, - {0x1Fu, 0x04u}, - {0x23u, 0x80u}, - {0x26u, 0x08u}, - {0x27u, 0x20u}, - {0x28u, 0x44u}, - {0x29u, 0x04u}, - {0x2Bu, 0x42u}, - {0x2Du, 0x08u}, - {0x2Eu, 0x90u}, - {0x30u, 0x88u}, - {0x33u, 0x20u}, - {0x37u, 0x68u}, - {0x39u, 0x84u}, - {0x3Bu, 0x90u}, - {0x3Du, 0x20u}, - {0x3Fu, 0x0Au}, - {0x59u, 0x08u}, - {0x5Au, 0x08u}, - {0x60u, 0x02u}, - {0x61u, 0x28u}, - {0x62u, 0x01u}, - {0x80u, 0x40u}, - {0x81u, 0x04u}, + {0x19u, 0x20u}, + {0x1Bu, 0x20u}, + {0x1Eu, 0x88u}, + {0x20u, 0x40u}, + {0x21u, 0x28u}, + {0x22u, 0x40u}, + {0x27u, 0x80u}, + {0x2Eu, 0x10u}, + {0x2Fu, 0x22u}, + {0x31u, 0x28u}, + {0x32u, 0x40u}, + {0x37u, 0x89u}, + {0x38u, 0x44u}, + {0x39u, 0x80u}, + {0x3Du, 0x28u}, + {0x58u, 0x80u}, + {0x5Au, 0x20u}, + {0x5Fu, 0x80u}, + {0x60u, 0x04u}, + {0x63u, 0x01u}, {0x83u, 0x40u}, - {0x89u, 0x04u}, - {0x8Bu, 0x80u}, - {0x8Cu, 0x80u}, - {0x8Du, 0x10u}, - {0x91u, 0xE0u}, - {0x92u, 0x18u}, - {0x93u, 0x20u}, - {0x95u, 0x02u}, - {0x96u, 0x04u}, - {0x97u, 0x02u}, - {0x98u, 0x04u}, - {0x99u, 0x02u}, - {0x9Au, 0xA0u}, - {0x9Bu, 0x4Au}, - {0x9Du, 0x01u}, - {0xA0u, 0x02u}, + {0x8Au, 0x11u}, + {0x8Fu, 0x04u}, + {0x92u, 0x72u}, + {0x93u, 0x40u}, + {0x95u, 0x01u}, + {0x98u, 0xA0u}, + {0x99u, 0x08u}, + {0x9Bu, 0x09u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x04u}, {0xA1u, 0x14u}, - {0xA3u, 0x25u}, - {0xA4u, 0x08u}, - {0xA6u, 0x18u}, - {0xA9u, 0x80u}, - {0xABu, 0x28u}, + {0xA2u, 0x88u}, + {0xA3u, 0x02u}, + {0xA6u, 0x02u}, + {0xA7u, 0x40u}, + {0xA8u, 0x02u}, + {0xAAu, 0x20u}, + {0xABu, 0x20u}, {0xACu, 0x80u}, - {0xB0u, 0x14u}, - {0xB1u, 0x08u}, + {0xB1u, 0x28u}, {0xB4u, 0x08u}, - {0xB5u, 0x04u}, - {0xB6u, 0x40u}, - {0xB7u, 0x04u}, - {0xC0u, 0x7Fu}, - {0xC2u, 0xBDu}, - {0xC4u, 0xFEu}, - {0xCAu, 0x7Fu}, - {0xCCu, 0x7Eu}, - {0xCEu, 0xEEu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x05u}, - {0xE2u, 0x0Au}, - {0xEAu, 0x05u}, - {0xEEu, 0x62u}, - {0x00u, 0x0Fu}, - {0x02u, 0xF0u}, - {0x03u, 0xFFu}, - {0x04u, 0x50u}, - {0x05u, 0x30u}, - {0x06u, 0xA0u}, - {0x07u, 0xC0u}, - {0x0Du, 0x06u}, - {0x0Eu, 0xFFu}, - {0x0Fu, 0x09u}, - {0x10u, 0x06u}, - {0x12u, 0x09u}, - {0x14u, 0x05u}, - {0x15u, 0x03u}, - {0x16u, 0x0Au}, - {0x17u, 0x0Cu}, - {0x18u, 0x30u}, - {0x19u, 0x05u}, - {0x1Au, 0xC0u}, - {0x1Bu, 0x0Au}, - {0x1Cu, 0x60u}, - {0x1Eu, 0x90u}, - {0x1Fu, 0xFFu}, - {0x20u, 0xFFu}, - {0x21u, 0x60u}, - {0x23u, 0x90u}, - {0x24u, 0x03u}, - {0x25u, 0x50u}, - {0x26u, 0x0Cu}, - {0x27u, 0xA0u}, - {0x29u, 0xFFu}, - {0x2Au, 0xFFu}, - {0x2Du, 0x0Fu}, - {0x2Fu, 0xF0u}, - {0x32u, 0xFFu}, - {0x33u, 0xFFu}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x04u}, + {0xC0u, 0x7Bu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xB6u}, + {0xCAu, 0x70u}, + {0xCCu, 0xDEu}, + {0xCEu, 0x6Au}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x0Cu}, + {0xE2u, 0x44u}, + {0xE6u, 0xCAu}, + {0xE8u, 0x04u}, + {0xEAu, 0x01u}, + {0xEEu, 0x86u}, + {0x00u, 0x01u}, + {0x01u, 0x02u}, + {0x02u, 0x02u}, + {0x03u, 0x01u}, + {0x08u, 0x02u}, + {0x0Au, 0x01u}, + {0x0Cu, 0x04u}, + {0x0Eu, 0x08u}, + {0x15u, 0x02u}, + {0x16u, 0x20u}, + {0x17u, 0x01u}, + {0x19u, 0x02u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x01u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x02u}, + {0x20u, 0x08u}, + {0x22u, 0x04u}, + {0x28u, 0x03u}, + {0x2Au, 0x0Cu}, + {0x2Du, 0x02u}, + {0x2Fu, 0x01u}, + {0x30u, 0x10u}, + {0x32u, 0x40u}, + {0x34u, 0x20u}, + {0x36u, 0x0Fu}, + {0x37u, 0x03u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x40u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x99u}, {0x5Fu, 0x01u}, - {0x82u, 0x20u}, - {0x83u, 0x02u}, - {0x84u, 0x08u}, - {0x86u, 0x04u}, - {0x88u, 0x04u}, - {0x89u, 0x04u}, - {0x8Au, 0x08u}, - {0x8Cu, 0x08u}, - {0x8Eu, 0x04u}, - {0x91u, 0x04u}, - {0x94u, 0x08u}, - {0x95u, 0x01u}, - {0x96u, 0x14u}, - {0x99u, 0x04u}, - {0x9Cu, 0x08u}, - {0x9Eu, 0x04u}, - {0xA5u, 0x04u}, - {0xA6u, 0x01u}, - {0xAAu, 0x02u}, - {0xACu, 0x01u}, - {0xAEu, 0x02u}, - {0xB0u, 0x10u}, - {0xB1u, 0x01u}, - {0xB2u, 0x0Cu}, - {0xB3u, 0x02u}, - {0xB4u, 0x20u}, + {0x87u, 0x10u}, + {0x89u, 0x02u}, + {0x8Bu, 0x01u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x01u}, + {0x91u, 0x01u}, + {0x93u, 0x02u}, + {0x95u, 0x10u}, + {0x97u, 0x20u}, + {0x9Du, 0x04u}, + {0xA3u, 0x20u}, + {0xA5u, 0x08u}, + {0xA9u, 0x02u}, + {0xABu, 0x01u}, + {0xADu, 0x02u}, + {0xAFu, 0x01u}, + {0xB1u, 0x03u}, + {0xB3u, 0x08u}, {0xB5u, 0x04u}, - {0xB6u, 0x03u}, - {0xB9u, 0x20u}, - {0xBAu, 0x08u}, - {0xBEu, 0x40u}, - {0xBFu, 0x10u}, + {0xB7u, 0x30u}, + {0xBBu, 0x02u}, + {0xBFu, 0x40u}, {0xD6u, 0x08u}, - {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x99u}, + {0xDCu, 0x90u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x41u}, - {0x03u, 0x28u}, - {0x04u, 0x0Au}, - {0x06u, 0x02u}, - {0x07u, 0x20u}, - {0x09u, 0x08u}, - {0x0Bu, 0x01u}, - {0x0Eu, 0x21u}, - {0x0Fu, 0x88u}, - {0x10u, 0x10u}, - {0x11u, 0x80u}, - {0x13u, 0x20u}, - {0x14u, 0x40u}, - {0x15u, 0x10u}, - {0x17u, 0x08u}, - {0x18u, 0x40u}, - {0x19u, 0x40u}, - {0x1Au, 0x84u}, - {0x1Bu, 0x08u}, - {0x1Du, 0x04u}, - {0x21u, 0x28u}, - {0x22u, 0x01u}, - {0x27u, 0x10u}, - {0x29u, 0x04u}, - {0x2Du, 0x30u}, - {0x2Eu, 0x09u}, - {0x2Fu, 0x42u}, - {0x32u, 0x06u}, - {0x33u, 0x10u}, - {0x34u, 0x50u}, - {0x35u, 0x80u}, - {0x36u, 0x18u}, - {0x37u, 0x08u}, - {0x39u, 0x20u}, - {0x3Bu, 0x01u}, - {0x3Du, 0x08u}, - {0x3Eu, 0x02u}, - {0x3Fu, 0x88u}, - {0x58u, 0x20u}, - {0x5Bu, 0x40u}, - {0x62u, 0x10u}, - {0x63u, 0x01u}, - {0x6Cu, 0x01u}, - {0x6Du, 0x80u}, - {0x6Fu, 0x02u}, - {0x81u, 0x01u}, - {0x82u, 0x0Au}, - {0x83u, 0x40u}, - {0x85u, 0x20u}, - {0x88u, 0x04u}, - {0x89u, 0x30u}, - {0x8Cu, 0x10u}, - {0x8Du, 0x0Cu}, - {0x90u, 0x29u}, - {0x92u, 0x08u}, - {0x93u, 0x80u}, - {0x94u, 0x02u}, - {0x96u, 0x86u}, - {0x9Cu, 0x0Cu}, - {0x9Du, 0x49u}, - {0x9Eu, 0x10u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x45u}, - {0xA2u, 0x10u}, - {0xA3u, 0xA0u}, - {0xA6u, 0x04u}, - {0xA7u, 0x4Au}, - {0xAAu, 0x40u}, - {0xB0u, 0x22u}, - {0xB2u, 0x08u}, - {0xB3u, 0x40u}, - {0xB5u, 0x02u}, - {0xB6u, 0x02u}, - {0xC0u, 0xBFu}, - {0xC2u, 0xF5u}, - {0xC4u, 0x77u}, - {0xCAu, 0xF2u}, - {0xCCu, 0x77u}, - {0xCEu, 0xD5u}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x0Cu}, - {0xE0u, 0x40u}, - {0xE2u, 0x22u}, - {0xE4u, 0x20u}, - {0xE6u, 0x41u}, - {0xE8u, 0x40u}, - {0xEAu, 0x31u}, - {0xEEu, 0x92u}, - {0x00u, 0x02u}, - {0x02u, 0x01u}, - {0x0Cu, 0x01u}, - {0x0Eu, 0x02u}, - {0x11u, 0x06u}, - {0x12u, 0x10u}, - {0x14u, 0x02u}, + {0x05u, 0x01u}, + {0x06u, 0x09u}, + {0x0Eu, 0x28u}, + {0x0Fu, 0x02u}, + {0x14u, 0x04u}, {0x15u, 0x01u}, - {0x16u, 0x05u}, - {0x17u, 0x02u}, - {0x18u, 0x02u}, - {0x1Au, 0x01u}, - {0x25u, 0x02u}, - {0x27u, 0x01u}, + {0x1Du, 0x40u}, + {0x1Eu, 0x28u}, + {0x1Fu, 0x01u}, + {0x21u, 0x42u}, + {0x22u, 0x04u}, + {0x23u, 0x48u}, + {0x25u, 0x80u}, + {0x26u, 0x80u}, {0x28u, 0x02u}, - {0x29u, 0x01u}, - {0x2Au, 0x09u}, - {0x2Bu, 0x04u}, - {0x30u, 0x03u}, - {0x31u, 0x07u}, + {0x29u, 0x10u}, + {0x2Bu, 0xA0u}, + {0x2Fu, 0x01u}, + {0x30u, 0x04u}, + {0x31u, 0x82u}, {0x32u, 0x08u}, - {0x34u, 0x10u}, - {0x36u, 0x04u}, - {0x39u, 0x02u}, - {0x3Au, 0x02u}, + {0x36u, 0x94u}, + {0x38u, 0x90u}, + {0x3Au, 0x08u}, + {0x3Fu, 0x02u}, + {0x58u, 0x80u}, + {0x5Du, 0x06u}, + {0x5Fu, 0x60u}, + {0x63u, 0x02u}, + {0x65u, 0x80u}, + {0x6Cu, 0x16u}, + {0x6Du, 0x41u}, + {0x6Fu, 0x80u}, + {0x74u, 0x80u}, + {0x76u, 0x95u}, + {0x80u, 0x80u}, + {0x86u, 0x04u}, + {0x8Au, 0x88u}, + {0x8Bu, 0x08u}, + {0x8Eu, 0x04u}, + {0x90u, 0x90u}, + {0x94u, 0x28u}, + {0x95u, 0xC0u}, + {0x98u, 0x02u}, + {0x99u, 0x91u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x10u}, + {0xA2u, 0x08u}, + {0xA3u, 0x20u}, + {0xA4u, 0x02u}, + {0xA8u, 0x80u}, + {0xAAu, 0x08u}, + {0xABu, 0x01u}, + {0xB0u, 0x40u}, + {0xB1u, 0x10u}, + {0xB2u, 0x80u}, + {0xB7u, 0x80u}, + {0xC0u, 0xD0u}, + {0xC2u, 0xE0u}, + {0xC4u, 0x50u}, + {0xCAu, 0x1Fu}, + {0xCCu, 0x7Bu}, + {0xCEu, 0x8Eu}, + {0xD6u, 0xF8u}, + {0xD8u, 0x18u}, + {0xE0u, 0x20u}, + {0xE2u, 0x40u}, + {0xE6u, 0xF2u}, + {0xE8u, 0x40u}, + {0xEAu, 0x01u}, + {0xECu, 0x20u}, + {0xEEu, 0x02u}, + {0x03u, 0xFFu}, + {0x05u, 0x50u}, + {0x07u, 0xA0u}, + {0x09u, 0x30u}, + {0x0Bu, 0xC0u}, + {0x0Du, 0x06u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x09u}, + {0x11u, 0x60u}, + {0x12u, 0x04u}, + {0x13u, 0x90u}, + {0x17u, 0xFFu}, + {0x19u, 0x03u}, + {0x1Au, 0x08u}, + {0x1Bu, 0x0Cu}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x10u}, + {0x1Fu, 0xF0u}, + {0x20u, 0x01u}, + {0x21u, 0x05u}, + {0x22u, 0x02u}, + {0x23u, 0x0Au}, + {0x2Du, 0xFFu}, + {0x2Eu, 0x02u}, + {0x30u, 0x10u}, + {0x32u, 0x08u}, + {0x34u, 0x04u}, + {0x35u, 0xFFu}, + {0x36u, 0x03u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x10u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -1227,145 +1184,138 @@ void cyfitter_cfg(void) {0x5Cu, 0x09u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x0Fu}, - {0x82u, 0xF0u}, - {0x84u, 0x06u}, + {0x84u, 0x50u}, {0x85u, 0xFFu}, - {0x86u, 0x09u}, - {0x88u, 0x60u}, - {0x89u, 0x55u}, - {0x8Au, 0x90u}, - {0x8Bu, 0xAAu}, + {0x86u, 0xA0u}, + {0x88u, 0x30u}, + {0x89u, 0x33u}, + {0x8Au, 0xC0u}, + {0x8Bu, 0xCCu}, + {0x8Cu, 0xFFu}, + {0x8Fu, 0xFFu}, + {0x90u, 0x90u}, + {0x91u, 0x0Fu}, + {0x92u, 0x60u}, + {0x93u, 0xF0u}, {0x94u, 0x05u}, - {0x95u, 0x0Fu}, {0x96u, 0x0Au}, - {0x97u, 0xF0u}, - {0x98u, 0x03u}, - {0x9Au, 0x0Cu}, - {0x9Bu, 0xFFu}, - {0x9Du, 0x33u}, - {0x9Fu, 0xCCu}, - {0xA1u, 0x96u}, - {0xA3u, 0x69u}, + {0x97u, 0xFFu}, + {0x99u, 0x55u}, + {0x9Bu, 0xAAu}, + {0x9Cu, 0x0Fu}, + {0x9Du, 0xFFu}, + {0x9Eu, 0xF0u}, + {0xA0u, 0x09u}, + {0xA1u, 0x69u}, + {0xA2u, 0x06u}, + {0xA3u, 0x96u}, + {0xA4u, 0x03u}, + {0xA6u, 0x0Cu}, {0xA7u, 0xFFu}, - {0xA8u, 0x50u}, - {0xAAu, 0xA0u}, - {0xABu, 0xFFu}, - {0xACu, 0x30u}, - {0xADu, 0xFFu}, - {0xAEu, 0xC0u}, - {0xB3u, 0xFFu}, - {0xB4u, 0xFFu}, - {0xBBu, 0x08u}, - {0xBEu, 0x10u}, - {0xD6u, 0x08u}, + {0xA8u, 0xFFu}, + {0xAEu, 0xFFu}, + {0xB1u, 0xFFu}, + {0xB6u, 0xFFu}, + {0xB8u, 0x02u}, + {0xBBu, 0x02u}, + {0xBEu, 0x41u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, {0xDCu, 0x10u}, - {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x41u}, - {0x04u, 0x02u}, - {0x05u, 0x04u}, + {0x00u, 0x80u}, + {0x04u, 0x28u}, + {0x05u, 0x41u}, + {0x07u, 0x40u}, + {0x09u, 0x80u}, + {0x0Au, 0x44u}, + {0x0Cu, 0x82u}, + {0x0Eu, 0x20u}, + {0x10u, 0x80u}, + {0x11u, 0x40u}, + {0x14u, 0x14u}, + {0x16u, 0x81u}, + {0x18u, 0x92u}, + {0x19u, 0x10u}, + {0x1Au, 0x44u}, + {0x1Fu, 0x41u}, + {0x22u, 0x20u}, + {0x26u, 0x02u}, + {0x29u, 0x40u}, + {0x2Au, 0x02u}, + {0x2Fu, 0xA0u}, + {0x30u, 0x9Eu}, + {0x31u, 0x20u}, + {0x34u, 0x08u}, + {0x35u, 0xA0u}, + {0x36u, 0x02u}, + {0x38u, 0x28u}, + {0x3Au, 0x81u}, + {0x3Du, 0x20u}, + {0x3Fu, 0x84u}, + {0x58u, 0x80u}, + {0x60u, 0x02u}, + {0x61u, 0x80u}, + {0x81u, 0x10u}, + {0x82u, 0x01u}, + {0x84u, 0x80u}, + {0x86u, 0x12u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x60u}, + {0x90u, 0x40u}, + {0x94u, 0x2Au}, + {0x95u, 0xE0u}, + {0x97u, 0x80u}, + {0x98u, 0x08u}, + {0x99u, 0xA0u}, + {0x9Bu, 0x40u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x08u}, + {0xA1u, 0x20u}, + {0xA3u, 0x40u}, + {0xA4u, 0x80u}, + {0xA6u, 0x30u}, + {0xABu, 0x04u}, + {0xB2u, 0x10u}, + {0xB3u, 0x02u}, + {0xB4u, 0x40u}, + {0xB6u, 0x80u}, + {0xC0u, 0xE1u}, + {0xC2u, 0xBBu}, + {0xC4u, 0xF9u}, + {0xCAu, 0xC9u}, + {0xCCu, 0xFFu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE2u, 0x50u}, + {0xE4u, 0x20u}, + {0xE6u, 0x92u}, + {0xEAu, 0x49u}, + {0xECu, 0x80u}, + {0xEEu, 0x20u}, + {0x02u, 0x02u}, {0x06u, 0x08u}, - {0x0Au, 0xA4u}, - {0x0Cu, 0x04u}, - {0x0Eu, 0x08u}, - {0x12u, 0x04u}, - {0x17u, 0x50u}, - {0x18u, 0x41u}, - {0x1Au, 0x60u}, - {0x1Bu, 0x20u}, - {0x1Cu, 0x08u}, - {0x21u, 0x02u}, - {0x26u, 0x08u}, - {0x28u, 0x08u}, - {0x29u, 0x08u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x42u}, - {0x31u, 0x02u}, - {0x33u, 0x04u}, - {0x35u, 0x20u}, - {0x36u, 0x88u}, - {0x38u, 0x40u}, - {0x3Au, 0x40u}, - {0x3Du, 0x04u}, - {0x3Fu, 0x20u}, - {0x58u, 0x60u}, - {0x5Bu, 0x08u}, - {0x5Eu, 0x80u}, - {0x62u, 0x84u}, - {0x63u, 0x08u}, - {0x67u, 0x02u}, - {0x6Cu, 0x16u}, - {0x6Fu, 0x80u}, - {0x74u, 0x41u}, - {0x76u, 0x08u}, - {0x77u, 0x50u}, - {0x83u, 0x10u}, - {0x85u, 0x40u}, - {0x87u, 0x08u}, - {0x88u, 0x02u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x08u}, - {0x8Fu, 0x01u}, - {0x91u, 0x14u}, - {0x92u, 0x08u}, - {0x94u, 0x20u}, - {0x96u, 0x02u}, - {0x98u, 0x40u}, - {0x99u, 0x20u}, - {0x9Cu, 0x06u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x50u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x20u}, - {0xA2u, 0x50u}, - {0xA4u, 0x02u}, - {0xA7u, 0x4Eu}, - {0xAEu, 0x05u}, - {0xB0u, 0x40u}, - {0xB1u, 0x04u}, - {0xC0u, 0x79u}, - {0xC2u, 0x6Eu}, - {0xC4u, 0xC2u}, - {0xCAu, 0xF6u}, - {0xCCu, 0x73u}, - {0xCEu, 0x60u}, - {0xD6u, 0x1Eu}, - {0xD8u, 0x1Eu}, - {0xE0u, 0x30u}, - {0xE2u, 0x48u}, - {0xE4u, 0x08u}, - {0xE6u, 0x50u}, - {0xE8u, 0x20u}, - {0xEAu, 0x01u}, - {0xEEu, 0x02u}, - {0x02u, 0x01u}, - {0x05u, 0x0Au}, - {0x07u, 0x05u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x07u}, - {0x17u, 0x10u}, - {0x1Bu, 0x20u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x23u, 0x08u}, - {0x25u, 0x09u}, - {0x27u, 0x02u}, - {0x29u, 0x04u}, - {0x2Bu, 0x08u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x04u}, - {0x2Fu, 0x20u}, - {0x31u, 0x30u}, - {0x32u, 0x03u}, - {0x35u, 0x0Fu}, - {0x36u, 0x04u}, + {0x0Bu, 0x08u}, + {0x0Du, 0x04u}, + {0x0Fu, 0x08u}, + {0x15u, 0x09u}, + {0x17u, 0x02u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x01u}, + {0x1Fu, 0x07u}, + {0x20u, 0x04u}, + {0x22u, 0x08u}, + {0x2Du, 0x0Au}, + {0x2Fu, 0x05u}, + {0x30u, 0x01u}, + {0x31u, 0x0Fu}, + {0x32u, 0x0Cu}, + {0x34u, 0x02u}, {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, @@ -1373,692 +1323,680 @@ void cyfitter_cfg(void) {0x5Fu, 0x01u}, {0x80u, 0x01u}, {0x82u, 0x02u}, - {0x83u, 0x10u}, - {0x85u, 0x01u}, - {0x87u, 0x02u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x02u}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x01u}, - {0x92u, 0x08u}, - {0x93u, 0x08u}, + {0x84u, 0x08u}, + {0x86u, 0x04u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x08u}, + {0x8Eu, 0x04u}, + {0x90u, 0x02u}, + {0x92u, 0x01u}, {0x94u, 0x02u}, {0x96u, 0x01u}, - {0x99u, 0x02u}, + {0x97u, 0x08u}, {0x9Bu, 0x01u}, - {0x9Du, 0x02u}, - {0x9Fu, 0x01u}, - {0xA3u, 0x04u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x08u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x08u}, + {0xA2u, 0x04u}, {0xA4u, 0x02u}, - {0xA6u, 0x11u}, + {0xA6u, 0x01u}, + {0xA7u, 0x10u}, {0xA8u, 0x02u}, - {0xA9u, 0x02u}, - {0xAAu, 0x05u}, - {0xABu, 0x21u}, - {0xADu, 0x04u}, - {0xAFu, 0x08u}, + {0xAAu, 0x01u}, + {0xABu, 0x04u}, + {0xACu, 0x08u}, + {0xAEu, 0x04u}, {0xB0u, 0x03u}, - {0xB1u, 0x0Cu}, - {0xB2u, 0x04u}, + {0xB1u, 0x04u}, {0xB3u, 0x10u}, - {0xB4u, 0x08u}, - {0xB5u, 0x03u}, - {0xB6u, 0x10u}, - {0xB7u, 0x20u}, - {0xBAu, 0x02u}, - {0xBBu, 0x20u}, - {0xBFu, 0x01u}, + {0xB5u, 0x08u}, + {0xB6u, 0x0Cu}, + {0xB7u, 0x03u}, + {0xBAu, 0x82u}, + {0xBFu, 0x40u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x99u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x82u}, - {0x04u, 0x20u}, + {0x00u, 0x88u}, + {0x02u, 0x80u}, {0x05u, 0x01u}, - {0x0Au, 0x10u}, - {0x0Bu, 0x80u}, - {0x0Fu, 0x02u}, - {0x12u, 0x18u}, - {0x15u, 0x80u}, - {0x18u, 0x02u}, - {0x19u, 0x92u}, - {0x1Au, 0x10u}, - {0x1Du, 0x04u}, - {0x1Fu, 0x40u}, - {0x20u, 0x80u}, - {0x21u, 0x40u}, - {0x22u, 0x58u}, - {0x23u, 0x04u}, - {0x24u, 0x80u}, - {0x25u, 0x10u}, - {0x26u, 0x10u}, - {0x2Bu, 0x47u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x20u}, - {0x2Fu, 0x82u}, - {0x30u, 0x02u}, - {0x31u, 0x10u}, - {0x32u, 0x40u}, - {0x34u, 0x04u}, - {0x37u, 0x10u}, - {0x38u, 0x02u}, - {0x3Bu, 0x84u}, - {0x3Du, 0x24u}, - {0x58u, 0x09u}, - {0x5Au, 0x20u}, - {0x5Bu, 0x40u}, - {0x5Cu, 0x20u}, - {0x5Eu, 0x05u}, + {0x06u, 0x10u}, + {0x08u, 0x02u}, + {0x0Au, 0x22u}, + {0x0Fu, 0x0Au}, + {0x12u, 0x4Au}, + {0x13u, 0x04u}, + {0x14u, 0x40u}, + {0x18u, 0x40u}, + {0x19u, 0x80u}, + {0x1Au, 0x03u}, + {0x1Cu, 0x88u}, + {0x1Du, 0x15u}, + {0x22u, 0x0Au}, + {0x23u, 0x06u}, + {0x27u, 0x40u}, + {0x28u, 0x10u}, + {0x29u, 0x10u}, + {0x2Fu, 0x02u}, + {0x30u, 0xC0u}, + {0x31u, 0x20u}, + {0x32u, 0x08u}, + {0x34u, 0x08u}, + {0x37u, 0x40u}, + {0x38u, 0x20u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x80u}, + {0x58u, 0x10u}, + {0x5Au, 0x60u}, + {0x5Cu, 0x24u}, + {0x5Du, 0x02u}, {0x5Fu, 0x80u}, {0x62u, 0x40u}, - {0x64u, 0x02u}, - {0x78u, 0x01u}, - {0x7Au, 0x80u}, - {0x80u, 0x08u}, - {0x81u, 0x02u}, - {0x83u, 0x48u}, - {0x85u, 0x10u}, - {0x86u, 0x84u}, - {0x88u, 0x40u}, - {0x8Du, 0x10u}, - {0x94u, 0x80u}, - {0x96u, 0x02u}, - {0x98u, 0x20u}, - {0x99u, 0x20u}, + {0x63u, 0x02u}, + {0x64u, 0x01u}, + {0x80u, 0x04u}, + {0x81u, 0x40u}, + {0x85u, 0x02u}, + {0x8Au, 0x01u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x20u}, + {0x92u, 0x70u}, + {0x94u, 0x2Cu}, + {0x95u, 0x60u}, + {0x97u, 0x80u}, + {0x98u, 0x2Bu}, {0x9Bu, 0x80u}, - {0x9Du, 0x04u}, - {0xA0u, 0x20u}, - {0xA2u, 0x40u}, - {0xA3u, 0x80u}, - {0xA8u, 0x20u}, - {0xA9u, 0x04u}, - {0xAEu, 0x01u}, - {0xB5u, 0x20u}, - {0xC0u, 0x59u}, - {0xC2u, 0x8Cu}, - {0xC4u, 0x86u}, - {0xCAu, 0xFDu}, - {0xCCu, 0x6Du}, - {0xCEu, 0x6Bu}, - {0xD6u, 0xFFu}, + {0x9Du, 0xC4u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x08u}, + {0xA1u, 0x20u}, + {0xA3u, 0x40u}, + {0xA4u, 0x80u}, + {0xA6u, 0x30u}, + {0xA8u, 0x10u}, + {0xAAu, 0x40u}, + {0xABu, 0x80u}, + {0xACu, 0x20u}, + {0xADu, 0x01u}, + {0xB6u, 0x60u}, + {0xB7u, 0x40u}, + {0xC0u, 0x3Du}, + {0xC2u, 0xCDu}, + {0xC4u, 0x1Fu}, + {0xCAu, 0x16u}, + {0xCCu, 0x5Eu}, + {0xCEu, 0x34u}, + {0xD6u, 0xF8u}, {0xD8u, 0x18u}, - {0xE2u, 0x64u}, - {0xE6u, 0x92u}, - {0xE8u, 0x10u}, - {0xECu, 0x01u}, - {0x80u, 0x60u}, - {0x86u, 0x40u}, - {0x87u, 0x80u}, - {0x8Fu, 0x80u}, - {0xE4u, 0x10u}, - {0xE6u, 0x02u}, - {0x09u, 0x04u}, - {0x0Bu, 0x88u}, - {0x15u, 0x53u}, - {0x16u, 0x01u}, - {0x17u, 0xACu}, - {0x1Eu, 0x02u}, - {0x21u, 0x02u}, - {0x23u, 0x11u}, - {0x25u, 0x01u}, - {0x27u, 0x42u}, - {0x28u, 0x01u}, - {0x29u, 0x08u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x24u}, - {0x30u, 0x03u}, - {0x31u, 0xC0u}, - {0x33u, 0x0Fu}, - {0x35u, 0x30u}, + {0xE0u, 0x11u}, + {0xE2u, 0xAAu}, + {0xE6u, 0x84u}, + {0xEAu, 0x04u}, + {0xECu, 0x40u}, + {0x07u, 0x02u}, + {0x08u, 0x30u}, + {0x0Au, 0xC0u}, + {0x0Cu, 0x60u}, + {0x0Eu, 0x90u}, + {0x10u, 0xFFu}, + {0x14u, 0x05u}, + {0x16u, 0x0Au}, + {0x17u, 0x01u}, + {0x18u, 0x03u}, + {0x1Au, 0x0Cu}, + {0x1Du, 0x01u}, + {0x1Eu, 0xFFu}, + {0x1Fu, 0x02u}, + {0x20u, 0x0Fu}, + {0x22u, 0xF0u}, + {0x24u, 0x50u}, + {0x26u, 0xA0u}, + {0x28u, 0x06u}, + {0x2Au, 0x09u}, + {0x2Eu, 0xFFu}, + {0x2Fu, 0x04u}, + {0x30u, 0xFFu}, + {0x33u, 0x03u}, + {0x35u, 0x04u}, {0x3Eu, 0x01u}, - {0x3Fu, 0x15u}, - {0x40u, 0x36u}, - {0x41u, 0x04u}, - {0x42u, 0x50u}, - {0x44u, 0x01u}, - {0x45u, 0xBEu}, - {0x46u, 0xFCu}, - {0x47u, 0x0Du}, - {0x48u, 0x1Fu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x22u}, - {0x4Eu, 0xF0u}, - {0x4Fu, 0x08u}, - {0x50u, 0x04u}, + {0x3Fu, 0x04u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x64u, 0x40u}, - {0x65u, 0x01u}, - {0x66u, 0x10u}, - {0x67u, 0x11u}, - {0x68u, 0xC0u}, - {0x69u, 0x01u}, - {0x6Bu, 0x11u}, - {0x6Cu, 0x40u}, - {0x6Du, 0x01u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x80u, 0x40u}, - {0x81u, 0x0Du}, - {0x84u, 0x01u}, - {0x88u, 0x22u}, - {0x89u, 0x0Du}, - {0x8Au, 0x08u}, - {0x8Cu, 0x01u}, - {0x90u, 0x07u}, - {0x91u, 0x0Du}, - {0x92u, 0x18u}, - {0x94u, 0x08u}, - {0x95u, 0x0Du}, - {0x96u, 0x21u}, - {0x98u, 0x04u}, - {0x99u, 0x12u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x0Du}, - {0xA0u, 0x01u}, - {0xA1u, 0x0Du}, - {0xA4u, 0x40u}, - {0xA8u, 0x01u}, - {0xA9u, 0x12u}, - {0xABu, 0x04u}, - {0xACu, 0x01u}, - {0xADu, 0x11u}, - {0xAFu, 0x02u}, - {0xB0u, 0x80u}, - {0xB1u, 0x0Fu}, - {0xB4u, 0x40u}, - {0xB6u, 0x3Fu}, - {0xB7u, 0x10u}, - {0xB8u, 0xA0u}, - {0xBBu, 0x02u}, - {0xBEu, 0x40u}, + {0x83u, 0x10u}, + {0x84u, 0x50u}, + {0x86u, 0xA0u}, + {0x87u, 0x20u}, + {0x88u, 0x30u}, + {0x8Au, 0xC0u}, + {0x8Bu, 0x0Eu}, + {0x8Du, 0x01u}, + {0x8Eu, 0xFFu}, + {0x94u, 0x05u}, + {0x95u, 0x32u}, + {0x96u, 0x0Au}, + {0x97u, 0x04u}, + {0x98u, 0x03u}, + {0x99u, 0x01u}, + {0x9Au, 0x0Cu}, + {0x9Cu, 0x0Fu}, + {0x9Du, 0x01u}, + {0x9Eu, 0xF0u}, + {0xA1u, 0x01u}, + {0xA2u, 0xFFu}, + {0xA5u, 0x34u}, + {0xA6u, 0xFFu}, + {0xA7u, 0x0Au}, + {0xA8u, 0x09u}, + {0xA9u, 0x28u}, + {0xAAu, 0x06u}, + {0xABu, 0x10u}, + {0xACu, 0x90u}, + {0xAEu, 0x60u}, + {0xAFu, 0x20u}, + {0xB0u, 0xFFu}, + {0xB3u, 0x01u}, + {0xB5u, 0x1Eu}, + {0xB7u, 0x20u}, + {0xB9u, 0x08u}, + {0xBEu, 0x01u}, + {0xBFu, 0x44u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x10u}, + {0xDFu, 0x01u}, + {0x01u, 0x40u}, + {0x02u, 0x04u}, + {0x04u, 0x28u}, + {0x05u, 0x40u}, + {0x06u, 0x14u}, + {0x09u, 0x1Au}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x80u}, + {0x0Du, 0x28u}, + {0x0Eu, 0x20u}, + {0x10u, 0x86u}, + {0x12u, 0x10u}, + {0x14u, 0x04u}, + {0x15u, 0x60u}, + {0x17u, 0x09u}, + {0x18u, 0x40u}, + {0x1Eu, 0x80u}, + {0x22u, 0x10u}, + {0x23u, 0x20u}, + {0x24u, 0x10u}, + {0x25u, 0x30u}, + {0x26u, 0x80u}, + {0x28u, 0x02u}, + {0x2Cu, 0x20u}, + {0x2Du, 0x80u}, + {0x2Eu, 0x20u}, + {0x2Fu, 0x40u}, + {0x30u, 0x80u}, + {0x31u, 0x08u}, + {0x34u, 0x08u}, + {0x36u, 0x60u}, + {0x38u, 0x08u}, + {0x3Cu, 0x44u}, + {0x3Du, 0x21u}, + {0x5Au, 0x80u}, + {0x60u, 0x02u}, + {0x65u, 0x40u}, + {0x67u, 0x02u}, + {0x78u, 0x01u}, + {0x7Au, 0x80u}, + {0x80u, 0x22u}, + {0x83u, 0x2Au}, + {0x84u, 0x08u}, + {0x85u, 0x02u}, + {0x87u, 0x01u}, + {0x88u, 0x08u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x10u}, + {0xC0u, 0xE3u}, + {0xC2u, 0xEFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0xF8u}, + {0xCCu, 0x7Au}, + {0xCEu, 0xF2u}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE0u, 0x81u}, + {0xE2u, 0x50u}, + {0xE4u, 0x11u}, + {0x81u, 0x5Cu}, + {0x84u, 0x14u}, + {0x85u, 0x24u}, + {0x87u, 0x10u}, + {0x88u, 0x3Fu}, + {0x89u, 0x50u}, + {0x8Au, 0x40u}, + {0x8Bu, 0x0Cu}, + {0x8Cu, 0x34u}, + {0x90u, 0x34u}, + {0x91u, 0x21u}, + {0x93u, 0x1Eu}, + {0x94u, 0x20u}, + {0x95u, 0x11u}, + {0x96u, 0x02u}, + {0x97u, 0x22u}, + {0x98u, 0x08u}, + {0x99u, 0x30u}, + {0x9Au, 0x75u}, + {0x9Bu, 0x0Fu}, + {0x9Cu, 0x4Bu}, + {0x9Eu, 0x30u}, + {0xA0u, 0x34u}, + {0xA1u, 0x5Cu}, + {0xA5u, 0x54u}, + {0xA6u, 0x34u}, + {0xA7u, 0x08u}, + {0xA8u, 0x14u}, + {0xA9u, 0x08u}, + {0xAAu, 0x20u}, + {0xADu, 0x0Cu}, + {0xAFu, 0x50u}, + {0xB3u, 0x30u}, + {0xB4u, 0x07u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x78u}, + {0xB7u, 0x40u}, + {0xB8u, 0x80u}, + {0xBAu, 0x30u}, + {0xBBu, 0x08u}, {0xBFu, 0x40u}, - {0xD4u, 0x09u}, - {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x04u, 0x05u}, - {0x05u, 0x10u}, - {0x07u, 0x01u}, - {0x08u, 0x40u}, - {0x0Au, 0x20u}, - {0x0Du, 0x06u}, - {0x0Eu, 0x24u}, - {0x0Fu, 0x01u}, - {0x10u, 0x08u}, + {0x00u, 0x04u}, + {0x01u, 0x01u}, + {0x03u, 0x06u}, + {0x06u, 0x02u}, + {0x07u, 0x14u}, + {0x09u, 0x20u}, + {0x0Bu, 0xA2u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x06u}, + {0x10u, 0x82u}, + {0x11u, 0x04u}, + {0x12u, 0x08u}, {0x15u, 0x01u}, - {0x16u, 0x02u}, - {0x17u, 0x18u}, - {0x1Bu, 0x01u}, - {0x1Cu, 0x01u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x04u}, - {0x1Fu, 0x20u}, - {0x20u, 0x08u}, - {0x22u, 0x02u}, - {0x23u, 0x10u}, - {0x27u, 0x42u}, - {0x28u, 0x08u}, - {0x29u, 0x0Au}, - {0x2Du, 0x01u}, - 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{0x32u, 0x04u}, + {0x36u, 0x80u}, {0x37u, 0x08u}, {0x38u, 0x01u}, - {0x3Bu, 0x40u}, + {0x3Au, 0x80u}, {0x3Cu, 0x04u}, {0x3Du, 0x40u}, - {0x43u, 0x10u}, - {0x52u, 0x40u}, - {0x59u, 0x08u}, - {0x5Fu, 0x01u}, - {0x61u, 0x02u}, - {0x67u, 0x10u}, + {0x41u, 0x10u}, + {0x5Au, 0x01u}, + {0x5Bu, 0x40u}, + {0x5Cu, 0x02u}, + {0x62u, 0x02u}, + {0x65u, 0x04u}, {0x81u, 0x40u}, - {0x83u, 0x01u}, - {0x8Cu, 0x01u}, + {0x8Au, 0x02u}, + {0x8Du, 0x04u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x20u}, + {0xD4u, 0x80u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x80u}, {0xE6u, 0x20u}, - {0x31u, 0x08u}, - {0x33u, 0x40u}, - {0x35u, 0x80u}, - {0x37u, 0x04u}, - {0x39u, 0x40u}, - {0x50u, 0x08u}, - {0x57u, 0x80u}, - {0x58u, 0x20u}, - {0x62u, 0x01u}, - {0x87u, 0x10u}, - {0x88u, 0x08u}, - {0x89u, 0x80u}, - {0x8Bu, 0x80u}, - {0x8Du, 0x40u}, - {0x8Eu, 0x01u}, + {0x33u, 0x18u}, + {0x36u, 0x08u}, + {0x37u, 0x20u}, + {0x38u, 0x20u}, + {0x51u, 0x08u}, + {0x56u, 0x20u}, + {0x58u, 0x10u}, + {0x5Cu, 0x02u}, + {0x84u, 0x02u}, + {0x89u, 0x10u}, {0x94u, 0x04u}, - {0x97u, 0x10u}, - {0x9Bu, 0x40u}, - {0x9Du, 0x08u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x10u}, - {0xA5u, 0x02u}, - {0xA6u, 0x20u}, - {0xAFu, 0x08u}, + {0x95u, 0x20u}, + {0x96u, 0x09u}, + {0x9Bu, 0x30u}, + {0x9Fu, 0x08u}, + {0xA6u, 0x80u}, + {0xA8u, 0x01u}, + {0xAAu, 0x08u}, + {0xABu, 0x50u}, + {0xACu, 0x02u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0xE0u}, - {0xD8u, 0x40u}, - {0xE2u, 0x10u}, - {0xEEu, 0x40u}, - {0x12u, 0x20u}, - {0x8Fu, 0x04u}, - {0x94u, 0x04u}, - {0x9Du, 0x08u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x14u}, - {0xA5u, 0x0Au}, - {0xA6u, 0x20u}, - {0xACu, 0x20u}, + {0xD6u, 0x80u}, + {0xE6u, 0x40u}, + {0xEAu, 0x80u}, + {0xEEu, 0xC0u}, + {0x12u, 0x80u}, + {0x32u, 0x10u}, + {0x58u, 0x08u}, + {0x88u, 0x10u}, + {0x8Au, 0x08u}, + {0x94u, 0x24u}, + {0x96u, 0x09u}, + {0x9Cu, 0x10u}, + {0x9Fu, 0x08u}, + {0xA6u, 0x88u}, + {0xA7u, 0x08u}, + {0xAAu, 0x20u}, + {0xB5u, 0x08u}, {0xC4u, 0x10u}, - {0xEEu, 0x10u}, - {0x85u, 0x08u}, - {0x86u, 0x40u}, - {0x94u, 0x04u}, - {0x9Au, 0x80u}, - {0x9Du, 0x08u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x02u}, - {0xA5u, 0x0Au}, - {0xB2u, 0x80u}, - {0xB4u, 0x02u}, - {0xE2u, 0x50u}, - {0x08u, 0x18u}, - {0x0Fu, 0x10u}, - {0x13u, 0x02u}, - {0x14u, 0x80u}, - {0x50u, 0x04u}, + {0xCCu, 0x10u}, + {0xD6u, 0x40u}, + {0xEAu, 0x20u}, + {0x86u, 0x04u}, + {0x87u, 0x08u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x10u}, + {0x94u, 0x24u}, + {0x96u, 0x28u}, + {0x9Fu, 0x08u}, + {0xA7u, 0x08u}, + {0xA8u, 0x08u}, + {0xB2u, 0x01u}, + {0xE6u, 0x50u}, + {0xEEu, 0x20u}, + {0x09u, 0x80u}, + {0x0Au, 0x20u}, + {0x0Cu, 0x02u}, + {0x10u, 0x20u}, + {0x15u, 0x04u}, + {0x50u, 0x08u}, {0x52u, 0x02u}, - {0x56u, 0x08u}, - {0x5Du, 0x10u}, - {0x84u, 0x10u}, + {0x57u, 0x08u}, + {0x5Cu, 0x40u}, + {0x82u, 0x02u}, + {0x83u, 0x08u}, + {0x8Eu, 0x10u}, {0xC2u, 0x0Eu}, {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x00u, 0x10u}, - {0x03u, 0x80u}, - {0x04u, 0x20u}, - {0x06u, 0x80u}, - {0x08u, 0x12u}, - {0x0Cu, 0x20u}, - {0x0Du, 0x01u}, - {0x80u, 0x10u}, - {0x85u, 0x01u}, - {0x88u, 0x14u}, - {0x8Au, 0x02u}, - {0x8Eu, 0x04u}, - {0x93u, 0x10u}, - {0x95u, 0x10u}, - {0x98u, 0x88u}, - {0x9Bu, 0x02u}, - {0x9Eu, 0x08u}, - {0xA6u, 0x02u}, - {0xA8u, 0x04u}, + {0xE2u, 0x02u}, + {0x00u, 0x08u}, + {0x03u, 0x08u}, + {0x05u, 0x02u}, + {0x06u, 0x02u}, + {0x09u, 0x12u}, + {0x0Du, 0x24u}, + {0x80u, 0x08u}, + {0x82u, 0x02u}, + {0x85u, 0x06u}, + {0x89u, 0x02u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x40u}, + {0x91u, 0x04u}, + {0x94u, 0x40u}, + {0xA0u, 0x20u}, + {0xA4u, 0x08u}, + {0xA8u, 0x02u}, + {0xB5u, 0x80u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE2u, 0x06u}, - {0xE4u, 0x04u}, - {0xE6u, 0x01u}, - {0x85u, 0x10u}, - {0x87u, 0x10u}, - {0x8Fu, 0x01u}, - {0x90u, 0x10u}, - {0x93u, 0x10u}, - {0x95u, 0x10u}, - {0x98u, 0x88u}, - {0x9Au, 0x80u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x04u}, - {0x9Eu, 0x08u}, - {0xA6u, 0x04u}, + {0xE0u, 0x02u}, + {0xE2u, 0x05u}, + {0xEAu, 0x08u}, + {0x85u, 0x04u}, + {0x88u, 0x02u}, + {0x91u, 0x04u}, + {0xA0u, 0x04u}, + {0xA1u, 0x10u}, {0xA8u, 0x20u}, - {0xACu, 0x02u}, - {0xB3u, 0x80u}, - {0xE6u, 0x08u}, - {0xEAu, 0x01u}, - {0x08u, 0x04u}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x08u}, + {0xADu, 0x20u}, + {0xE6u, 0x01u}, + {0x09u, 0x20u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x02u}, {0x0Eu, 0x08u}, - {0x80u, 0x80u}, - {0x84u, 0x08u}, - {0x97u, 0x01u}, - {0x98u, 0x80u}, - {0x9Cu, 0x04u}, - {0x9Eu, 0x08u}, - {0xA6u, 0x04u}, - {0xAAu, 0x80u}, - {0xAFu, 0x02u}, - {0xB0u, 0x08u}, - {0xB4u, 0x10u}, + {0x87u, 0x10u}, + {0x8Du, 0x20u}, + {0x8Eu, 0x04u}, + {0xA4u, 0x02u}, + {0xA9u, 0x10u}, + {0xACu, 0x04u}, {0xC2u, 0x0Fu}, - {0xEAu, 0x09u}, - {0x67u, 0x80u}, - {0x85u, 0x08u}, - {0x87u, 0x40u}, - {0x9Au, 0x80u}, - {0x9Du, 0x08u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x02u}, - {0xA5u, 0x02u}, + {0xE2u, 0x02u}, + {0xE6u, 0x02u}, + {0x83u, 0x40u}, + {0x98u, 0x20u}, + {0xA8u, 0x20u}, {0xB4u, 0x04u}, - {0xD8u, 0x80u}, - {0xE2u, 0x10u}, - {0xE6u, 0x10u}, - {0x06u, 0x40u}, - {0x54u, 0x02u}, - {0x56u, 0x80u}, - {0x83u, 0x10u}, - {0x86u, 0x40u}, - {0x8Du, 0x02u}, - {0x9Au, 0x80u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x02u}, - {0xA5u, 0x02u}, - {0xC0u, 0x20u}, - {0xD4u, 0x40u}, - {0xD6u, 0x20u}, - {0xE0u, 0x10u}, {0xE2u, 0x20u}, - {0x9Eu, 0x08u}, - {0x01u, 0x02u}, - {0x86u, 0x08u}, - {0x8Du, 0x02u}, - {0x9Eu, 0x08u}, + {0xEEu, 0x20u}, + {0x04u, 0x02u}, + {0x57u, 0x40u}, + {0x58u, 0x20u}, + {0x8Cu, 0x01u}, + {0x98u, 0x20u}, + {0xA3u, 0x40u}, + {0xC0u, 0x20u}, + {0xD4u, 0xC0u}, + {0x01u, 0x04u}, + {0x89u, 0x04u}, {0xC0u, 0x08u}, - {0xE2u, 0x02u}, + {0xE2u, 0x04u}, {0x10u, 0x03u}, {0x1Au, 0x03u}, {0x00u, 0xFDu}, - {0x01u, 0xAFu}, - {0x02u, 0x0Au}, + {0x01u, 0xBFu}, + {0x02u, 0x2Au}, {0x10u, 0x55u}, }; @@ -2081,18 +2019,30 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0x01u, 0xC0u, 0x00u, 0x02u, 0x40u, 0xC0u, 0x00u, 0x04u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0x00u, 0x00u, 0xFFu, + 0x08u, 0x90u, 0x21u, 0x40u, 0x22u, 0x1Fu, 0x08u, 0x20u, 0x40u, 0xC0u, 0x00u, 0x08u, 0x10u, 0xC0u, 0x00u, 0x01u, + 0x01u, 0x00u, 0x00u, 0x9Fu, 0x01u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x60u, + 0x40u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xFFu, 0x08u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x10u, + 0x52u, 0x03u, 0x10u, 0x00u, 0x06u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index a7a64017..62eb76fe 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -207,40 +207,40 @@ /* USBFS_ep_1 */ .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x40 -.set USBFS_ep_1__INTC_NUMBER, 6 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x80 -.set USBFS_ep_2__INTC_NUMBER, 7 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x100 -.set USBFS_ep_3__INTC_NUMBER, 8 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 .set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x200 -.set USBFS_ep_4__INTC_NUMBER, 9 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 .set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -381,34 +381,34 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -416,9 +416,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -436,12 +436,14 @@ .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -449,9 +451,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST /* SD_SCK */ .set SD_SCK__0__MASK, 0x04 @@ -1875,15 +1877,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1896,37 +1898,37 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -2377,10 +2379,10 @@ /* SD_RX_DMA_COMPLETE */ .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5 .set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2399,10 +2401,10 @@ /* SD_TX_DMA_COMPLETE */ .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20 -.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6 .set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2804,10 +2806,10 @@ /* SCSI_TX_DMA_COMPLETE */ .set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 .set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 .set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2843,13 +2845,23 @@ .set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + /* SCSI_Filtered */ .set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2857,9 +2869,13 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK +.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 @@ -2890,12 +2906,12 @@ /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 @@ -2975,7 +2991,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000003E +.set CYDEV_INTR_RISING, 0x0000007E .set CYDEV_PROJ_TYPE, 2 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 .set CYDEV_PROJ_TYPE_LOADABLE, 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index dc757612..0c155fc0 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -207,40 +207,40 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_1 */ USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x40 -USBFS_ep_1__INTC_NUMBER EQU 6 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x80 -USBFS_ep_2__INTC_NUMBER EQU 7 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_3 */ USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x100 -USBFS_ep_3__INTC_NUMBER EQU 8 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_4 */ USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x200 -USBFS_ep_4__INTC_NUMBER EQU 9 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -436,12 +436,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -449,9 +451,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST /* SD_SCK */ SD_SCK__0__MASK EQU 0x04 @@ -1875,15 +1877,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1896,37 +1898,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2377,10 +2379,10 @@ SD_RX_DMA__TERMOUT1_SEL EQU 0 /* SD_RX_DMA_COMPLETE */ SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2399,10 +2401,10 @@ SD_TX_DMA__TERMOUT1_SEL EQU 0 /* SD_TX_DMA_COMPLETE */ SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2804,10 +2806,10 @@ SCSI_TX_DMA__TERMOUT1_SEL EQU 0 /* SCSI_TX_DMA_COMPLETE */ SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2843,13 +2845,23 @@ SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + /* SCSI_Filtered */ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2857,9 +2869,13 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 @@ -2890,12 +2906,12 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 @@ -2975,7 +2991,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000003E +CYDEV_INTR_RISING EQU 0x0000007E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index aba1877f..ac8e851d 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -207,40 +207,40 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_1 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x40 -USBFS_ep_1__INTC_NUMBER EQU 6 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_2 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x80 -USBFS_ep_2__INTC_NUMBER EQU 7 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_3 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x100 -USBFS_ep_3__INTC_NUMBER EQU 8 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_4 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x200 -USBFS_ep_4__INTC_NUMBER EQU 9 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -381,34 +381,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -416,9 +416,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -436,12 +436,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -449,9 +451,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST ; SD_SCK SD_SCK__0__MASK EQU 0x04 @@ -1875,15 +1877,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1896,37 +1898,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2377,10 +2379,10 @@ SD_RX_DMA__TERMOUT1_SEL EQU 0 ; SD_RX_DMA_COMPLETE SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2399,10 +2401,10 @@ SD_TX_DMA__TERMOUT1_SEL EQU 0 ; SD_TX_DMA_COMPLETE SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2804,10 +2806,10 @@ SCSI_TX_DMA__TERMOUT1_SEL EQU 0 ; SCSI_TX_DMA_COMPLETE SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2843,13 +2845,23 @@ SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + ; SCSI_Filtered SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2857,9 +2869,13 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 @@ -2890,12 +2906,12 @@ SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 @@ -2975,7 +2991,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000003E +CYDEV_INTR_RISING EQU 0x0000007E CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index b48e729d..20a6a858 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -69,6 +69,7 @@ #include #include #include +#include #include #include #include diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index f461b84a..eec56737 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,18 +1,11 @@ - - - - - - - - - - - + + + + @@ -71,20 +64,24 @@ - - - - + + + + + + + + + + + - - - - - - + + + @@ -112,9 +109,9 @@ - - - + + + @@ -141,23 +138,28 @@ - + + + + + + + - + - + - + - - - + + @@ -165,6 +167,9 @@ + + + @@ -261,11 +266,10 @@ - - - - + + + + - \ No newline at end of file diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit index 4eb3570c..74fb4b30 100644 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj index 3d72eb5e..e3b9bc0b 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -3124,6 +3124,36 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -3718,6 +3748,15 @@ + + + + + + + + + diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd index 0462adfa..3069cd02 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd @@ -6,48 +6,6 @@ 8 32 - - SCSI_Out_Bits - No description available - 0x4000647B - - 0 - 0x0 - registers - - - - SCSI_Out_Bits_CONTROL_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - - - SCSI_Out_Ctl - No description available - 0x40006478 - - 0 - 0x0 - registers - - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - Debug_Timer No description available @@ -340,10 +298,31 @@ + + SCSI_Out_Ctl + No description available + 0x40006474 + + 0 + 0x0 + registers + + + + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_Filtered No description available - 0x4000646D + 0x40006468 0 0x0 @@ -498,7 +477,7 @@ SCSI_Parity_Error No description available - 0x40006465 + 0x40006466 0 0x0 @@ -650,6 +629,27 @@ + + SCSI_Out_Bits + No description available + 0x40006478 + + 0 + 0x0 + registers + + + + SCSI_Out_Bits_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_CTL_PHASE No description available diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 1a73ac58..977098ef 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 78af9754..c2608714 100644 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used)) const uint8 cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x24u, 0x04u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit index 3e1777a5..2a6bd100 100644 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 84c3865c..1f62920b 100755 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/scsi2sd-util/scsi2sd-util.cc b/software/scsi2sd-util/scsi2sd-util.cc index 6db8f8d5..a46a534d 100644 --- a/software/scsi2sd-util/scsi2sd-util.cc +++ b/software/scsi2sd-util/scsi2sd-util.cc @@ -781,8 +781,10 @@ private: if (!myInitialConfig) { +/* This doesn't work properly, and causes crashes. wxCommandEvent loadEvent(wxEVT_NULL, ID_BtnLoad); GetEventHandler()->AddPendingEvent(loadEvent); +*/ } }