From: Michael McMaster Date: Fri, 20 Feb 2015 06:56:27 +0000 (+1000) Subject: Implement WRITE BUFFER and WRITE WITH VERIFY commands X-Git-Tag: v4.01.01^0 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=95b519789b3f328963842e3de8f70dda373a0f37;p=SCSI2SD.git Implement WRITE BUFFER and WRITE WITH VERIFY commands Also fixes a problem with SD card initialisation not setting the clock back to normal on an error condition. The next initialisation attempt ends up running the card at a very slow rate. --- diff --git a/CHANGELOG b/CHANGELOG index 41398d9..cf022b5 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,9 @@ +201501?? 4.1.1 + - Fix MODE SENSE bug when the allocation length is less than the + page size. + - Add WRITE BUFFER and WRITE AND VERIFY support. + - Fix rare case of very slow performance + 20150201 4.1 - Rewrite of the SD card interface to fix compatibility problems. This fixes write issues with Samsung SD cards. diff --git a/readme.txt b/readme.txt index 50b5f86..1c22fde 100644 --- a/readme.txt +++ b/readme.txt @@ -82,6 +82,11 @@ Compatibility Alpha 21264 CPU, 667MHz, with a QLogic SCSI controller in a PCI slot SCSI-based Macintosh Powerbooks (2.5" SCSI2SD) Also reported to work on Thinkpad 860 running Win NT 4.0 PowerPC. + Data General MV/2500DC running AOS/VS + Vendor: MICROoP + Product: 1578-15 UP + Revision: DG02 + Device-type modifier: 0x4c Samplers @@ -105,3 +110,6 @@ Other HP 16601A, 16700A logic analyzers Fluke 9100 series + Reftek RT-72A Seismic datalogger. + http://www.iris.iris.edu/passcal/Reftek/72A-R-005-00.1.pdf + http://www.iris.iris.edu/passcal/Manual/rtfm.s3a.13.html diff --git a/software/SCSI2SD/src/bits.c b/software/SCSI2SD/src/bits.c index ab83ba0..ec8eea7 100755 --- a/software/SCSI2SD/src/bits.c +++ b/software/SCSI2SD/src/bits.c @@ -14,6 +14,9 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") + #include "bits.h" const uint8 Lookup_OddParity[] = @@ -45,3 +48,5 @@ uint8 countBits(uint8 value) } return i; } + +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/cdrom.c b/software/SCSI2SD/src/cdrom.c index 44d03a3..18ed321 100755 --- a/software/SCSI2SD/src/cdrom.c +++ b/software/SCSI2SD/src/cdrom.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -327,3 +329,5 @@ int scsiCDRomCommand() return commandHandled; } + +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index 74c554e..6178b9f 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "config.h" @@ -30,7 +32,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0410; +static const uint16_t FIRMWARE_VERSION = 0x0411; enum USB_ENDPOINTS { @@ -274,7 +276,7 @@ void debugPoll() hidBuffer[26] = blockDev.state; hidBuffer[27] = scsiDev.lastSenseASC >> 8; hidBuffer[28] = scsiDev.lastSenseASC; - + hidBuffer[29] = scsiReadDBxPins(); hidBuffer[58] = sdDev.capacity >> 24; hidBuffer[59] = sdDev.capacity >> 16; @@ -323,6 +325,11 @@ void debugResume() Debug_Timer_Start(); } +int isDebugEnabled() +{ + return usbReady; +} + // Public method for storing MODE SELECT results. void configSave(int scsiId, uint16_t bytesPerSector) { @@ -377,4 +384,4 @@ const TargetConfig* getConfigById(int scsiId) } - +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/debug.h b/software/SCSI2SD/src/debug.h index cece6bc..683c75b 100755 --- a/software/SCSI2SD/src/debug.h +++ b/software/SCSI2SD/src/debug.h @@ -20,6 +20,7 @@ void debugInit(void); void debugPause(void); void debugResume(void); +int isDebugEnabled(void); #endif diff --git a/software/SCSI2SD/src/diagnostic.c b/software/SCSI2SD/src/diagnostic.c index c518d75..709836c 100755 --- a/software/SCSI2SD/src/diagnostic.c +++ b/software/SCSI2SD/src/diagnostic.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -162,4 +164,54 @@ void scsiReadBuffer() (allocLength > MAX_SECTOR_SIZE) ? MAX_SECTOR_SIZE : allocLength; scsiDev.phase = DATA_IN; } + else + { + // error. + scsiDev.status = CHECK_CONDITION; + scsiDev.target->sense.code = ILLEGAL_REQUEST; + scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } +} + +// Callback after the DATA OUT phase is complete. +static void doWriteBuffer(void) +{ + if (scsiDev.status == GOOD) // skip if we've already encountered an error + { + // scsiDev.dataLen bytes are in scsiDev.data + // Don't shift it down 4 bytes ... this space is taken by + // the read buffer header anyway + scsiDev.phase = STATUS; + } } + +void scsiWriteBuffer() +{ + // WRITE BUFFER + // Used for testing the speed of the SCSI interface. + uint8 mode = scsiDev.data[1] & 7; + + int allocLength = + (((uint32) scsiDev.cdb[6]) << 16) + + (((uint32) scsiDev.cdb[7]) << 8) + + scsiDev.cdb[8]; + + if (mode == 0 && allocLength <= sizeof(scsiDev.data)) + { + scsiDev.dataLen = allocLength; + scsiDev.phase = DATA_OUT; + scsiDev.postDataOutHook = doWriteBuffer; + } + else + { + // error. + scsiDev.status = CHECK_CONDITION; + scsiDev.target->sense.code = ILLEGAL_REQUEST; + scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.phase = STATUS; + } +} + + +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/diagnostic.h b/software/SCSI2SD/src/diagnostic.h index 4cba50c..98e90d2 100755 --- a/software/SCSI2SD/src/diagnostic.h +++ b/software/SCSI2SD/src/diagnostic.h @@ -19,6 +19,7 @@ void scsiSendDiagnostic(void); void scsiReceiveDiagnostic(void); +void scsiWriteBuffer(void); void scsiReadBuffer(void); #endif diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 003f5f3..af1c50a 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -15,6 +15,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -38,7 +40,7 @@ static int doSdInit() if (blockDev.state & DISK_PRESENT) { result = sdInit(); - + if (result) { blockDev.state = blockDev.state | DISK_INITIALISED; @@ -167,8 +169,8 @@ static void doReadCapacity() static void doWrite(uint32 lba, uint32 blocks) { - if ((blockDev.state & DISK_WP) || - (scsiDev.target->cfg->deviceType == CONFIG_OPTICAL)) + if (unlikely(blockDev.state & DISK_WP) || + unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL)) { scsiDev.status = CHECK_CONDITION; @@ -176,12 +178,13 @@ static void doWrite(uint32 lba, uint32 blocks) scsiDev.target->sense.asc = WRITE_PROTECTED; scsiDev.phase = STATUS; } - else if (((uint64) lba) + blocks > + else if (unlikely(((uint64) lba) + blocks > getScsiCapacity( scsiDev.target->cfg->sdSectorStart, scsiDev.target->liveCfg.bytesPerSector, scsiDev.target->cfg->scsiSectors - )) + ) + )) { scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = ILLEGAL_REQUEST; @@ -201,7 +204,7 @@ static void doWrite(uint32 lba, uint32 blocks) // No need for single-block writes atm. Overhead of the // multi-block write is minimal. transfer.multiBlock = 1; - + sdWriteMultiSectorPrep(); } } @@ -213,7 +216,7 @@ static void doRead(uint32 lba, uint32 blocks) scsiDev.target->cfg->sdSectorStart, scsiDev.target->liveCfg.bytesPerSector, scsiDev.target->cfg->scsiSectors); - if (((uint64) lba) + blocks > capacity) + if (unlikely(((uint64) lba) + blocks > capacity)) { scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = ILLEGAL_REQUEST; @@ -230,7 +233,7 @@ static void doRead(uint32 lba, uint32 blocks) scsiDev.dataLen = 0; // No data yet if ((blocks == 1) || - (((uint64) lba) + blocks == capacity) + unlikely(((uint64) lba) + blocks == capacity) ) { // We get errors on reading the last sector using a multi-sector @@ -264,7 +267,11 @@ static void doSeek(uint32 lba) static int doTestUnitReady() { int ready = 1; - if (!(blockDev.state & DISK_STARTED)) + if (likely(blockDev.state == (DISK_STARTED | DISK_PRESENT | DISK_INITIALISED))) + { + // nothing to do. + } + else if (unlikely(!(blockDev.state & DISK_STARTED))) { ready = 0; scsiDev.status = CHECK_CONDITION; @@ -272,7 +279,7 @@ static int doTestUnitReady() scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED; scsiDev.phase = STATUS; } - else if (!(blockDev.state & DISK_PRESENT)) + else if (unlikely(!(blockDev.state & DISK_PRESENT))) { ready = 0; scsiDev.status = CHECK_CONDITION; @@ -280,7 +287,7 @@ static int doTestUnitReady() scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT; scsiDev.phase = STATUS; } - else if (!(blockDev.state & DISK_INITIALISED)) + else if (unlikely(!(blockDev.state & DISK_INITIALISED))) { ready = 0; scsiDev.status = CHECK_CONDITION; @@ -297,7 +304,7 @@ int scsiDiskCommand() int commandHandled = 1; uint8 command = scsiDev.cdb[0]; - if (command == 0x1B) + if (unlikely(command == 0x1B)) { // START STOP UNIT // Enable or disable media access operations. @@ -318,36 +325,16 @@ int scsiDiskCommand() blockDev.state &= ~DISK_STARTED; } } - else if (command == 0x00) + else if (unlikely(command == 0x00)) { // TEST UNIT READY doTestUnitReady(); } - else if (!doTestUnitReady()) + else if (unlikely(!doTestUnitReady())) { // Status and sense codes already set by doTestUnitReady } - else if (command == 0x04) - { - // FORMAT UNIT - // We don't really do any formatting, but we need to read the correct - // number of bytes in the DATA_OUT phase to make the SCSI host happy. - - int fmtData = (scsiDev.cdb[1] & 0x10) ? 1 : 0; - if (fmtData) - { - // We need to read the parameter list, but we don't know how - // big it is yet. Start with the header. - scsiDev.dataLen = 4; - scsiDev.phase = DATA_OUT; - scsiDev.postDataOutHook = doFormatUnitHeader; - } - else - { - // No data to read, we're already finished! - } - } - else if (command == 0x08) + else if (likely(command == 0x08)) { // READ(6) uint32 lba = @@ -355,11 +342,10 @@ int scsiDiskCommand() (((uint32) scsiDev.cdb[2]) << 8) + scsiDev.cdb[3]; uint32 blocks = scsiDev.cdb[4]; - if (blocks == 0) blocks = 256; + if (unlikely(blocks == 0)) blocks = 256; doRead(lba, blocks); } - - else if (command == 0x28) + else if (likely(command == 0x28)) { // READ(10) // Ignore all cache control bits - we don't support a memory cache. @@ -375,90 +361,110 @@ int scsiDiskCommand() doRead(lba, blocks); } - - else if (command == 0x25) + else if (likely(command == 0x0A)) { - // READ CAPACITY - doReadCapacity(); - } - - else if (command == 0x0B) - { - // SEEK(6) + // WRITE(6) uint32 lba = (((uint32) scsiDev.cdb[1] & 0x1F) << 16) + (((uint32) scsiDev.cdb[2]) << 8) + scsiDev.cdb[3]; - - doSeek(lba); + uint32 blocks = scsiDev.cdb[4]; + if (unlikely(blocks == 0)) blocks = 256; + doWrite(lba, blocks); } - - else if (command == 0x2B) + else if (likely(command == 0x2A) || // WRITE(10) + unlikely(command == 0x2E)) // WRITE AND VERIFY { - // SEEK(10) + // Ignore all cache control bits - we don't support a memory cache. + // Don't bother verifying either. The SD card likely stores ECC + // along with each flash row. + uint32 lba = (((uint32) scsiDev.cdb[2]) << 24) + (((uint32) scsiDev.cdb[3]) << 16) + (((uint32) scsiDev.cdb[4]) << 8) + scsiDev.cdb[5]; + uint32 blocks = + (((uint32) scsiDev.cdb[7]) << 8) + + scsiDev.cdb[8]; - doSeek(lba); + doWrite(lba, blocks); } - else if (command == 0x0A) + + else if (unlikely(command == 0x04)) { - // WRITE(6) + // FORMAT UNIT + // We don't really do any formatting, but we need to read the correct + // number of bytes in the DATA_OUT phase to make the SCSI host happy. + + int fmtData = (scsiDev.cdb[1] & 0x10) ? 1 : 0; + if (fmtData) + { + // We need to read the parameter list, but we don't know how + // big it is yet. Start with the header. + scsiDev.dataLen = 4; + scsiDev.phase = DATA_OUT; + scsiDev.postDataOutHook = doFormatUnitHeader; + } + else + { + // No data to read, we're already finished! + } + } + else if (unlikely(command == 0x25)) + { + // READ CAPACITY + doReadCapacity(); + } + else if (unlikely(command == 0x0B)) + { + // SEEK(6) uint32 lba = (((uint32) scsiDev.cdb[1] & 0x1F) << 16) + (((uint32) scsiDev.cdb[2]) << 8) + scsiDev.cdb[3]; - uint32 blocks = scsiDev.cdb[4]; - if (blocks == 0) blocks = 256; - doWrite(lba, blocks); + + doSeek(lba); } - else if (command == 0x2A) + else if (unlikely(command == 0x2B)) { - // WRITE(10) - // Ignore all cache control bits - we don't support a memory cache. - + // SEEK(10) uint32 lba = (((uint32) scsiDev.cdb[2]) << 24) + (((uint32) scsiDev.cdb[3]) << 16) + (((uint32) scsiDev.cdb[4]) << 8) + scsiDev.cdb[5]; - uint32 blocks = - (((uint32) scsiDev.cdb[7]) << 8) + - scsiDev.cdb[8]; - doWrite(lba, blocks); + doSeek(lba); } - else if (command == 0x36) + else if (unlikely(command == 0x36)) { // LOCK UNLOCK CACHE // We don't have a cache to lock data into. do nothing. } - else if (command == 0x34) + else if (unlikely(command == 0x34)) { // PRE-FETCH. // We don't have a cache to pre-fetch into. do nothing. } - else if (command == 0x1E) + else if (unlikely(command == 0x1E)) { // PREVENT ALLOW MEDIUM REMOVAL // Not much we can do to prevent the user removing the SD card. // do nothing. } - else if (command == 0x01) + else if (unlikely(command == 0x01)) { // REZERO UNIT // Set the lun to a vendor-specific state. Ignore. } - else if (command == 0x35) + else if (unlikely(command == 0x35)) { // SYNCHRONIZE CACHE // We don't have a cache. do nothing. } - else if (command == 0x2F) + else if (unlikely(command == 0x2F)) { // VERIFY // TODO: When they supply data to verify, we should read the data and @@ -512,15 +518,27 @@ void scsiDiskPoll() int scsiActive = 0; int sdActive = 0; while ((i < totalSDSectors) && - (scsiDev.phase == DATA_IN) && - !scsiDev.resetFlag) + likely(scsiDev.phase == DATA_IN) && + likely(!scsiDev.resetFlag)) { - if ((sdActive == 1) && sdReadSectorDMAPoll()) + // Wait for the next DMA interrupt. It's beneficial to halt the + // processor to give the DMA controller more memory bandwidth to + // work with. + // We're optimistically assuming a race condition won't occur + // between these checks and the interrupt handers. The 1ms + // systick timer interrupt saves us on the event of a race. + int scsiBusy = scsiDMABusy(); + int sdBusy = sdDMABusy(); + if (scsiBusy && sdBusy) __WFI(); + + if (sdActive && !sdBusy && sdReadSectorDMAPoll()) { sdActive = 0; prep++; } - else if ((sdActive == 0) && (prep - i < buffers) && (prep < totalSDSectors)) + else if (!sdActive && + (prep - i < buffers) && + (prep < totalSDSectors)) { // Start an SD transfer if we have space. if (transfer.multiBlock) @@ -534,12 +552,12 @@ void scsiDiskPoll() sdActive = 1; } - if ((scsiActive == 1) && scsiWriteDMAPoll()) + if (scsiActive && !scsiBusy && scsiWriteDMAPoll()) { scsiActive = 0; ++i; } - else if ((scsiActive == 0) && ((prep - i) > 0)) + else if (!scsiActive && ((prep - i) > 0)) { int dmaBytes = SD_SECTOR_SIZE; if ((i % sdPerScsi) == (sdPerScsi - 1)) @@ -575,16 +593,26 @@ void scsiDiskPoll() int sdActive = 0; while ((i < totalSDSectors) && - ((scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase. + (likely(scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase. scsiComplete) && - !scsiDev.resetFlag) + likely(!scsiDev.resetFlag)) { - if ((sdActive == 1) && sdWriteSectorDMAPoll(i == (totalSDSectors - 1))) + // Wait for the next DMA interrupt. It's beneficial to halt the + // processor to give the DMA controller more memory bandwidth to + // work with. + // We're optimistically assuming a race condition won't occur + // between these checks and the interrupt handers. The 1ms + // systick timer interrupt saves us on the event of a race. + int scsiBusy = scsiDMABusy(); + int sdBusy = sdDMABusy(); + if (scsiBusy && sdBusy) __WFI(); + + if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1))) { sdActive = 0; i++; } - else if ((sdActive == 0) && ((prep - i) > 0)) + else if (!sdActive && ((prep - i) > 0)) { // Start an SD transfer if we have space. sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]); @@ -593,16 +621,16 @@ void scsiDiskPoll() uint32_t now = getTime_ms(); - if ((scsiActive == 1) && scsiReadDMAPoll()) + if (scsiActive && !scsiBusy && scsiReadDMAPoll()) { scsiActive = 0; ++prep; lastActivityTime = now; } - else if ((scsiActive == 0) && + else if (!scsiActive && ((prep - i) < buffers) && (prep < totalSDSectors) && - !scsiDisconnected) + likely(!scsiDisconnected)) { int dmaBytes = SD_SECTOR_SIZE; if ((prep % sdPerScsi) == (sdPerScsi - 1)) @@ -615,10 +643,10 @@ void scsiDiskPoll() } else if ( (scsiActive == 0) && - !scsiDisconnected && - scsiDev.discPriv && - (diffTime_ms(lastActivityTime, now) >= 20) && - (scsiDev.phase == DATA_OUT)) + likely(!scsiDisconnected) && + unlikely(scsiDev.discPriv) && + unlikely(diffTime_ms(lastActivityTime, now) >= 20) && + likely(scsiDev.phase == DATA_OUT)) { // We're transferring over the SCSI bus faster than the SD card // can write. There is no more buffer space once we've finished @@ -631,12 +659,12 @@ void scsiDiskPoll() scsiDisconnected = 1; lastActivityTime = getTime_ms(); } - else if (scsiDisconnected && + else if (unlikely(scsiDisconnected) && ( (prep == i) || // Buffers empty. // Send some messages every 100ms so we don't timeout. // At a minimum, a reselection involves an IDENTIFY message. - (diffTime_ms(lastActivityTime, now) >= 100) + unlikely(diffTime_ms(lastActivityTime, now) >= 100) )) { int reconnected = scsiReconnect(); @@ -652,13 +680,13 @@ void scsiDiskPoll() } } else if ( - !scsiComplete && + likely(!scsiComplete) && (sdActive == 1) && (prep == totalSDSectors) && // All scsi data read and buffered - !scsiDev.discPriv && // Prefer disconnect where possible. - (diffTime_ms(lastActivityTime, now) >= 150) && + likely(!scsiDev.discPriv) && // Prefer disconnect where possible. + unlikely(diffTime_ms(lastActivityTime, now) >= 150) && - (scsiDev.phase == DATA_OUT) && + likely(scsiDev.phase == DATA_OUT) && !(scsiDev.cdb[scsiDev.cdbLen - 1] & 0x01) // Not linked command ) { @@ -685,8 +713,8 @@ void scsiDiskPoll() } while ( !scsiDev.resetFlag && - scsiDisconnected && - (diffTime_ms(lastActivityTime, getTime_ms()) <= 10000)) + unlikely(scsiDisconnected) && + (elapsedTime_ms(lastActivityTime) <= 10000)) { scsiDisconnected = !scsiReconnect(); } @@ -723,7 +751,7 @@ void scsiDiskReset() transfer.currentBlock = 0; // Cancel long running commands! - if (transfer.inProgress == 1) + if (unlikely(transfer.inProgress == 1)) { if (transfer.dir == TRANSFER_WRITE) { @@ -736,8 +764,6 @@ void scsiDiskReset() } transfer.inProgress = 0; transfer.multiBlock = 0; - // SD_CS_Write(1); - } void scsiDiskInit() @@ -757,3 +783,4 @@ void scsiDiskInit() #endif } +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/inquiry.c b/software/SCSI2SD/src/inquiry.c index 5420beb..51dd319 100755 --- a/software/SCSI2SD/src/inquiry.c +++ b/software/SCSI2SD/src/inquiry.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -25,7 +27,7 @@ static uint8 StandardResponse[] = { 0x00, // "Direct-access device". AKA standard hard disk -0x00, // device type qualifier +0x00, // device type modifier 0x02, // Complies with ANSI SCSI-2. 0x01, // Response format is compatible with the old CCS format. 0x1f, // standard length. @@ -112,6 +114,7 @@ void scsiInquiry() { const TargetConfig* config = scsiDev.target->cfg; memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse)); + scsiDev.data[1] = scsiDev.target->cfg->deviceTypeModifier; memcpy(&scsiDev.data[8], config->vendor, sizeof(config->vendor)); memcpy(&scsiDev.data[16], config->prodId, sizeof(config->prodId)); memcpy(&scsiDev.data[32], config->revision, sizeof(config->revision)); @@ -203,3 +206,4 @@ void scsiInquiry() } } +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/led.c b/software/SCSI2SD/src/led.c index 8ad6dad..47cc093 100755 --- a/software/SCSI2SD/src/led.c +++ b/software/SCSI2SD/src/led.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "led.h" @@ -75,3 +77,4 @@ void ledOff() #endif } +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c index 00f9f83..58e4ca8 100755 --- a/software/SCSI2SD/src/main.c +++ b/software/SCSI2SD/src/main.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -59,13 +61,21 @@ int main() scsiDiskPoll(); configPoll(); - uint32_t now = getTime_ms(); - if (diffTime_ms(lastSDPoll, now) > 200) + if (unlikely(scsiDev.phase == BUS_FREE)) { - lastSDPoll = now; - sdPoll(); + if (unlikely(elapsedTime_ms(lastSDPoll) > 200)) + { + lastSDPoll = getTime_ms(); + sdPoll(); + } + else + { + // Wait for our 1ms timer to save some power. + __WFI(); + } } } return 0; } +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/mode.c b/software/SCSI2SD/src/mode.c index e748b1b..c66608a 100755 --- a/software/SCSI2SD/src/mode.c +++ b/software/SCSI2SD/src/mode.c @@ -15,6 +15,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -152,8 +154,6 @@ static void doModeSense( } else { - int pageFound = 1; - ////////////// Mode Parameter Header //////////////////////////////////// @@ -243,22 +243,25 @@ static void doModeSense( scsiDev.data[idx++] = bytesPerSector & 0xFF; } - switch (pageCode) - { - case 0x3F: - // EVERYTHING + int pageFound = 0; - case 0x01: + if (pageCode == 0x01 || pageCode == 0x3F) + { + pageFound = 1; pageIn(pc, idx, ReadWriteErrorRecoveryPage, sizeof(ReadWriteErrorRecoveryPage)); idx += sizeof(ReadWriteErrorRecoveryPage); - if (pageCode != 0x3f) break; + } - case 0x02: + if (pageCode == 0x02 || pageCode == 0x3F) + { + pageFound = 1; pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage)); idx += sizeof(DisconnectReconnectPage); - if (pageCode != 0x3f) break; + } - case 0x03: + if (pageCode == 0x03 || pageCode == 0x3F) + { + pageFound = 1; pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage)); if (pc != 0x01) { @@ -275,10 +278,11 @@ static void doModeSense( } idx += sizeof(FormatDevicePage); - if (pageCode != 0x3f) break; + } - case 0x04: + if (pageCode == 0x04 || pageCode == 0x3F) { + pageFound = 1; pageIn(pc, idx, RigidDiskDriveGeometry, sizeof(RigidDiskDriveGeometry)); if (pc != 0x01) @@ -305,25 +309,40 @@ static void doModeSense( } idx += sizeof(RigidDiskDriveGeometry); - if (pageCode != 0x3f) break; } - case 0x08: + // DON'T output the following pages for SCSI1 hosts. They get upset when + // we have more data to send than the allocation length provided. + // (ie. Try not to output any more pages below this comment) + + + if (!scsiDev.compatMode && (pageCode == 0x08 || pageCode == 0x3F)) + { + pageFound = 1; pageIn(pc, idx, CachingPage, sizeof(CachingPage)); idx += sizeof(CachingPage); - if (pageCode != 0x3f) break; + } - case 0x0A: + if (!scsiDev.compatMode && (pageCode == 0x0A || pageCode == 0x3F)) + { + pageFound = 1; pageIn(pc, idx, ControlModePage, sizeof(ControlModePage)); idx += sizeof(ControlModePage); - if (pageCode != 0x3f) break; + } - case 0x30: + if (( + (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_APPLE) || + (idx + sizeof(AppleVendorPage) <= allocLength) + ) && + (pageCode == 0x30 || pageCode == 0x3F)) + { + pageFound = 1; pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage)); idx += sizeof(AppleVendorPage); - break; + } - default: + if (!pageFound) + { // Unknown Page Code pageFound = 0; scsiDev.status = CHECK_CONDITION; @@ -331,15 +350,7 @@ static void doModeSense( scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } - - - if (idx > allocLength) - { - // Chop the reply off early if shorter length is requested - idx = allocLength; - } - - if (pageFound) + else { // Go back and fill out the mode data length if (sixByteCmd) @@ -353,17 +364,9 @@ static void doModeSense( scsiDev.data[1] = (idx - 2); } - scsiDev.dataLen = idx; + scsiDev.dataLen = idx > allocLength ? allocLength : idx; scsiDev.phase = DATA_IN; } - else - { - // Page not found - scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; - scsiDev.phase = STATUS; - } } } @@ -538,4 +541,4 @@ int scsiModeCommand() return commandHandled; } - +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index 63739e0..15622d5 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -28,6 +30,7 @@ #include "disk.h" #include "time.h" #include "cdrom.h" +#include "debug.h" #include @@ -50,7 +53,16 @@ static void enter_BusFree() { // This delay probably isn't needed for most SCSI hosts, but it won't // hurt either. It's possible some of the samplers needed this delay. - CyDelayUs(2); + if (scsiDev.compatMode) + { + CyDelayUs(2); + } + + if (scsiDev.status != GOOD && isDebugEnabled()) + { + // We want to capture debug information for failure cases. + CyDelay(64); + } SCSI_ClearPin(SCSI_Out_BSY); // We now have a Bus Clear Delay of 800ns to release remaining signals. @@ -75,7 +87,7 @@ void process_MessageIn() scsiEnterPhase(MESSAGE_IN); scsiWriteByte(scsiDev.msgIn); - if (scsiDev.atnFlag) + if (unlikely(scsiDev.atnFlag)) { // If there was a parity error, we go // back to MESSAGE_OUT first, get out parity error message, then come @@ -253,7 +265,7 @@ static void process_Command() scsiDev.cmdCount++; - if (scsiDev.resetFlag) + if (unlikely(scsiDev.resetFlag)) { // Don't log bogus commands scsiDev.cmdCount--; @@ -340,6 +352,12 @@ static void process_Command() { enter_Status(CONFLICT); } + else if (scsiDiskCommand()) + { + // Already handled. + // check for the performance-critical read/write + // commands ASAP. + } else if (command == 0x1C) { scsiReceiveDiagnostic(); @@ -348,14 +366,17 @@ static void process_Command() { scsiSendDiagnostic(); } + else if (command == 0x3B) + { + scsiWriteBuffer(); + } else if (command == 0x3C) { scsiReadBuffer(); } else if ( - !scsiModeCommand() && - !scsiDiskCommand() && - !scsiCDRomCommand()) + !scsiCDRomCommand() && + !scsiModeCommand()) { scsiDev.target->sense.code = ILLEGAL_REQUEST; scsiDev.target->sense.asc = INVALID_COMMAND_OPERATION_CODE; @@ -515,7 +536,7 @@ static void process_SelectionPhase() if (!bsy && sel && target && (goodParity || !(target->cfg->flags & CONFIG_ENABLE_PARITY) || !atnFlag) && - (maskBitCount <= 2)) + likely(maskBitCount <= 2)) { scsiDev.target = target; @@ -546,7 +567,7 @@ static void process_SelectionPhase() scsiDev.selCount++; // Wait until the end of the selection phase. - while (!scsiDev.resetFlag) + while (likely(!scsiDev.resetFlag)) { if (!SCSI_ReadFilt(SCSI_Filt_SEL)) { @@ -686,20 +707,32 @@ static void process_MessageOut() // Extended message. int msgLen = scsiReadByte(); if (msgLen == 0) msgLen = 256; + uint8_t extmsg[256]; for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i) { // Discard bytes. - scsiReadByte(); + extmsg[i] = scsiReadByte(); + } + + if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request + { + // Negotiate down to 8bit + scsiEnterPhase(MESSAGE_IN); + static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00}; + scsiWrite(WDTR, sizeof(WDTR)); + } + else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request + { + // Negotiate back to async + scsiEnterPhase(MESSAGE_IN); + static const uint8_t SDTR[] = {0x01, 0x03, 0x01, 0x00, 0x00}; + scsiWrite(SDTR, sizeof(SDTR)); + } + else + { + // Not supported + messageReject(); } - - // We don't support ANY extended messages. - // Modify Data Pointer: We don't support reselection. - // Wide Data Transfer Request: No. 8bit only. - // Synchronous data transfer request. No, we can't do that. - // We don't support any 2-byte messages either. - // And we don't support any optional 1-byte messages. - // In each case, the correct response is MESSAGE REJECT. - messageReject(); } else { @@ -712,7 +745,7 @@ static void process_MessageOut() void scsiPoll(void) { - if (scsiDev.resetFlag) + if (unlikely(scsiDev.resetFlag)) { scsiReset(); if ((scsiDev.resetFlag = SCSI_ReadFilt(SCSI_Filt_RST))) @@ -932,7 +965,7 @@ int scsiReconnect() while ( !bsy && !scsiDev.resetFlag && - (diffTime_ms(waitStart_ms, getTime_ms()) < 250)) + (elapsedTime_ms(waitStart_ms) < 250)) { bsy = SCSI_ReadFilt(SCSI_Filt_BSY); } @@ -967,3 +1000,4 @@ int scsiReconnect() return reconnected; } +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h index d7e2404..2a48af3 100755 --- a/software/SCSI2SD/src/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -147,4 +147,10 @@ void scsiPoll(void); void scsiDisconnect(void); int scsiReconnect(void); + +// Utility macros, consistent with the Linux Kernel code. +#define likely(x) __builtin_expect(!!(x), 1) +#define unlikely(x) __builtin_expect(!!(x), 0) +//#define likely(x) (x) +//#define unlikely(x) (x) #endif diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index b6c4e64..5952b85 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -42,19 +44,19 @@ static uint8 scsiDmaTxTd[1] = { CY_DMA_INVALID_TD }; // Source of dummy bytes for DMA reads static uint8 dummyBuffer = 0xFF; -volatile static uint8 rxDMAComplete; -volatile static uint8 txDMAComplete; +volatile uint8_t scsiRxDMAComplete; +volatile uint8_t scsiTxDMAComplete; CY_ISR_PROTO(scsiRxCompleteISR); CY_ISR(scsiRxCompleteISR) { - rxDMAComplete = 1; + scsiRxDMAComplete = 1; } CY_ISR_PROTO(scsiTxCompleteISR); CY_ISR(scsiTxCompleteISR) { - txDMAComplete = 1; + scsiTxDMAComplete = 1; } CY_ISR_PROTO(scsiResetISR); @@ -80,14 +82,14 @@ scsiReadDBxPins() uint8_t scsiReadByte(void) { - while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {} + while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {} scsiPhyTx(0); - while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {} + while (scsiPhyRxFifoEmpty() && likely(!scsiDev.resetFlag)) {} uint8_t val = scsiPhyRx(); scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read(); - while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {} return val; } @@ -98,7 +100,7 @@ scsiReadPIO(uint8* data, uint32 count) int prep = 0; int i = 0; - while (i < count && !scsiDev.resetFlag) + while (i < count && likely(!scsiDev.resetFlag)) { uint8_t status = scsiPhyStatus(); @@ -114,7 +116,7 @@ scsiReadPIO(uint8* data, uint32 count) } } scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read(); - while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {} } static void @@ -136,7 +138,7 @@ doRxSingleDMA(uint8* data, uint32 count) TD_INC_DST_ADR | SCSI_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete ); - + CyDmaTdSetAddress( scsiDmaTxTd[0], LO16((uint32)&dummyBuffer), @@ -146,18 +148,18 @@ doRxSingleDMA(uint8* data, uint32 count) LO16((uint32)scsiTarget_datapath__F1_REG), LO16((uint32)data) ); - + CyDmaChSetInitialTd(scsiDmaTxChan, scsiDmaTxTd[0]); CyDmaChSetInitialTd(scsiDmaRxChan, scsiDmaRxTd[0]); - + // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was // disabled. CyDmaClearPendingDrq(scsiDmaTxChan); CyDmaClearPendingDrq(scsiDmaRxChan); - txDMAComplete = 0; - rxDMAComplete = 0; + scsiTxDMAComplete = 0; + scsiRxDMAComplete = 0; CyDmaChEnable(scsiDmaRxChan, 1); CyDmaChEnable(scsiDmaTxChan, 1); @@ -178,9 +180,13 @@ scsiReadDMA(uint8* data, uint32 count) int scsiReadDMAPoll() { - if (txDMAComplete && rxDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) + if (scsiTxDMAComplete && scsiRxDMAComplete) { - if (dmaSentCount == dmaTotalCount) + // Wait until our scsi signals are consistent. This should only be + // a few cycles. + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {} + + if (likely(dmaSentCount == dmaTotalCount)) { dmaInProgress = 0; scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read(); @@ -191,7 +197,7 @@ scsiReadDMAPoll() // Transfer was too large for a single DMA transfer. Continue // to send remaining bytes. uint32_t count = dmaTotalCount - dmaSentCount; - if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES; + if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES; doRxSingleDMA(dmaBuffer + dmaSentCount, count); dmaSentCount += count; return 0; @@ -213,26 +219,32 @@ scsiRead(uint8_t* data, uint32_t count) else { scsiReadDMA(data, count); - while (!scsiReadDMAPoll() && !scsiDev.resetFlag) {}; + + // Wait for the next DMA interrupt (or the 1ms systick) + // It's beneficial to halt the processor to + // give the DMA controller more memory bandwidth to work with. + __WFI(); + + while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {}; } } void scsiWriteByte(uint8 value) { - while (scsiPhyTxFifoFull() && !scsiDev.resetFlag) {} + while (unlikely(scsiPhyTxFifoFull()) && likely(!scsiDev.resetFlag)) {} scsiPhyTx(value); - while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {} scsiPhyRxFifoClear(); } static void -scsiWritePIO(uint8_t* data, uint32_t count) +scsiWritePIO(const uint8_t* data, uint32_t count) { int i = 0; - while (i < count && !scsiDev.resetFlag) + while (i < count && likely(!scsiDev.resetFlag)) { if (!scsiPhyTxFifoFull()) { @@ -241,12 +253,12 @@ scsiWritePIO(uint8_t* data, uint32_t count) } } - while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {} + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && likely(!scsiDev.resetFlag)) {} scsiPhyRxFifoClear(); } static void -doTxSingleDMA(uint8* data, uint32 count) +doTxSingleDMA(const uint8* data, uint32 count) { // Prepare DMA transfer dmaInProgress = 1; @@ -269,14 +281,14 @@ doTxSingleDMA(uint8* data, uint32 count) // disabled. CyDmaClearPendingDrq(scsiDmaTxChan); - txDMAComplete = 0; - rxDMAComplete = 1; + scsiTxDMAComplete = 0; + scsiRxDMAComplete = 1; CyDmaChEnable(scsiDmaTxChan, 1); } void -scsiWriteDMA(uint8* data, uint32 count) +scsiWriteDMA(const uint8* data, uint32 count) { dmaSentCount = 0; dmaTotalCount = count; @@ -290,9 +302,13 @@ scsiWriteDMA(uint8* data, uint32 count) int scsiWriteDMAPoll() { - if (txDMAComplete && (scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) + if (scsiTxDMAComplete) { - if (dmaSentCount == dmaTotalCount) + // Wait until our scsi signals are consistent. This should only be + // a few cycles. + while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE)) {} + + if (likely(dmaSentCount == dmaTotalCount)) { scsiPhyRxFifoClear(); dmaInProgress = 0; @@ -303,7 +319,7 @@ scsiWriteDMAPoll() // Transfer was too large for a single DMA transfer. Continue // to send remaining bytes. uint32_t count = dmaTotalCount - dmaSentCount; - if (count > MAX_DMA_BYTES) count = MAX_DMA_BYTES; + if (unlikely(count > MAX_DMA_BYTES)) count = MAX_DMA_BYTES; doTxSingleDMA(dmaBuffer + dmaSentCount, count); dmaSentCount += count; return 0; @@ -316,7 +332,7 @@ scsiWriteDMAPoll() } void -scsiWrite(uint8_t* data, uint32_t count) +scsiWrite(const uint8_t* data, uint32_t count) { if (count < 8) { @@ -325,11 +341,17 @@ scsiWrite(uint8_t* data, uint32_t count) else { scsiWriteDMA(data, count); - while (!scsiWriteDMAPoll() && !scsiDev.resetFlag) {}; + + // Wait for the next DMA interrupt (or the 1ms systick) + // It's beneficial to halt the processor to + // give the DMA controller more memory bandwidth to work with. + __WFI(); + + while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {}; } } -static void busSettleDelay(void) +static inline void busSettleDelay(void) { // Data Release time (switching IO) = 400ns // + Bus Settle time (switching phase) = 400ns. @@ -356,7 +378,7 @@ void scsiPhyReset() dmaTotalCount = 0; CyDmaChSetRequest(scsiDmaTxChan, CY_DMA_CPU_TERM_CHAIN); CyDmaChSetRequest(scsiDmaRxChan, CY_DMA_CPU_TERM_CHAIN); - while (!(txDMAComplete && rxDMAComplete)) {} + while (!(scsiTxDMAComplete && scsiRxDMAComplete)) {} CyDmaChDisable(scsiDmaTxChan); CyDmaChDisable(scsiDmaRxChan); @@ -406,7 +428,7 @@ static void scsiPhyInitDMA() HI16(CYDEV_SRAM_BASE), HI16(CYDEV_PERIPH_BASE) ); - + CyDmaChDisable(scsiDmaRxChan); CyDmaChDisable(scsiDmaTxChan); @@ -425,3 +447,4 @@ void scsiPhyInit() SCSI_RST_ISR_StartEx(scsiResetISR); } +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/scsiPhy.h b/software/SCSI2SD/src/scsiPhy.h index bee2987..b4c0f79 100755 --- a/software/SCSI2SD/src/scsiPhy.h +++ b/software/SCSI2SD/src/scsiPhy.h @@ -67,6 +67,10 @@ enum FilteredInputs // Contains the odd-parity flag for a given 8-bit value. extern const uint8_t Lookup_OddParity[256]; +extern volatile uint8_t scsiRxDMAComplete; +extern volatile uint8_t scsiTxDMAComplete; +#define scsiDMABusy() (!(scsiRxDMAComplete && scsiTxDMAComplete)) + void scsiPhyReset(void); void scsiPhyInit(void); @@ -76,8 +80,8 @@ void scsiReadDMA(uint8_t* data, uint32_t count); int scsiReadDMAPoll(); void scsiWriteByte(uint8_t value); -void scsiWrite(uint8_t* data, uint32_t count); -void scsiWriteDMA(uint8_t* data, uint32_t count); +void scsiWrite(const uint8_t* data, uint32_t count); +void scsiWriteDMA(const uint8_t* data, uint32_t count); int scsiWriteDMAPoll(); uint8_t scsiReadDBxPins(void); diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index e0649bd..00163f3 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "device.h" #include "scsi.h" @@ -37,10 +39,6 @@ static int sdIOState = SD_IDLE; static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL; static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL; -// DMA descriptors -static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD }; -static uint8 sdDMATxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD }; - // Dummy location for DMA to send unchecked CRC bytes to static uint8 discardBuffer; @@ -53,18 +51,18 @@ static uint8_t writeStartToken = 0xFC; // Source of dummy SPI bytes for DMA static uint8 dummyBuffer = 0xFF; -volatile static uint8 rxDMAComplete; -volatile static uint8 txDMAComplete; +volatile uint8_t sdRxDMAComplete; +volatile uint8_t sdTxDMAComplete; CY_ISR_PROTO(sdRxISR); CY_ISR(sdRxISR) { - rxDMAComplete = 1; + sdRxDMAComplete = 1; } CY_ISR_PROTO(sdTxISR); CY_ISR(sdTxISR) { - txDMAComplete = 1; + sdTxDMAComplete = 1; } static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc) @@ -98,14 +96,23 @@ static uint16_t sdDoCommand( int useCRC, int use2byteResponse) { - uint8_t send[7]; + int waitWhileBusy = (cmd != SD_GO_IDLE_STATE) && (cmd != SD_STOP_TRANSMISSION); + + // "busy" probe. We'll examine the results later. + if (waitWhileBusy) + { + SDCard_WriteTxData(0xFF); + } + // send is static as the address must remain consistent for the static + // DMA descriptors to work. + static uint8_t send[7]; send[0] = cmd | 0x40; send[1] = param >> 24; send[2] = param >> 16; send[3] = param >> 8; send[4] = param; - if (useCRC) + if (unlikely(useCRC)) { send[5] = (sdCrc7(send, 5, 0) << 1) | 1; } @@ -115,31 +122,52 @@ static uint16_t sdDoCommand( } send[6] = 0xFF; // Result code or stuff byte. - CyDmaTdSetConfiguration(sdDMATxTd[0], sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN); - CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR)); - CyDmaTdSetConfiguration(sdDMARxTd[0], sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN); - CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); + static uint8_t dmaRxTd = CY_DMA_INVALID_TD; + static uint8_t dmaTxTd = CY_DMA_INVALID_TD; + if (unlikely(dmaRxTd == CY_DMA_INVALID_TD)) + { + dmaRxTd = CyDmaTdAllocate(); + dmaTxTd = CyDmaTdAllocate(); + CyDmaTdSetConfiguration(dmaTxTd, sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR)); + CyDmaTdSetConfiguration(dmaRxTd, sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(dmaRxTd, LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); + } + + sdTxDMAComplete = 0; + sdRxDMAComplete = 0; + + CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd); + CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd); + + // Some Samsung cards enter a busy-state after single-sector reads. + // But we also need to wait for R1B to complete from the multi-sector + // reads. + if (waitWhileBusy) + { + while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {} + int busy = SDCard_ReadRxData() != 0xFF; + if (unlikely(busy)) + { + while (sdSpiByte(0xFF) != 0xFF) {} + } + } + // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was // disabled. CyDmaClearPendingDrq(sdDMATxChan); CyDmaClearPendingDrq(sdDMARxChan); - txDMAComplete = 0; - rxDMAComplete = 0; - - CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]); - CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]); - // There is no flow control, so we must ensure we can read the bytes // before we start transmitting CyDmaChEnable(sdDMARxChan, 1); CyDmaChEnable(sdDMATxChan, 1); - while (!(txDMAComplete && rxDMAComplete)) {} + while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); } uint16_t response = discardBuffer; - if (cmd == SD_STOP_TRANSMISSION) + if (unlikely(cmd == SD_STOP_TRANSMISSION)) { // Stuff byte is required for this command only. // Part 1 Simplified standard 3.01 @@ -149,11 +177,11 @@ static uint16_t sdDoCommand( } uint32_t start = getTime_ms(); - while ((response & 0x80) && (diffTime_ms(start, getTime_ms()) <= 200)) + while ((response & 0x80) && likely(elapsedTime_ms(start) <= 200)) { response = sdSpiByte(0xFF); } - if (use2byteResponse) + if (unlikely(use2byteResponse)) { response = (response << 8) | sdSpiByte(0xFF); } @@ -161,21 +189,13 @@ static uint16_t sdDoCommand( } -static uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param) +static inline uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param) { - // Some Samsung cards enter a busy-state after single-sector reads. - // But we also need to wait for R1B to complete from the multi-sector - // reads. - while (sdSpiByte(0xFF) == 0x00) {} return sdDoCommand(cmd, param, 0, 0); } -static uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param) +static inline uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param) { - // Some Samsung cards enter a busy-state after single-sector reads. - // But we also need to wait for R1B to complete from the multi-sector - // reads. - while (sdSpiByte(0xFF) == 0x00) {} return sdDoCommand(cmd, param, 1, 0); } @@ -203,14 +223,14 @@ sdReadMultiSectorPrep() sdLBA = sdLBA * SD_SECTOR_SIZE; } v = sdCommandAndResponse(SD_READ_MULTIPLE_BLOCK, sdLBA); - if (v) + if (unlikely(v)) { scsiDiskReset(); sdClearStatus(); scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE; + scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -226,16 +246,16 @@ dmaReadSector(uint8_t* outputBuffer) // Don't wait more than 200ms. The standard recommends 100ms. uint32_t start = getTime_ms(); uint8_t token = sdSpiByte(0xFF); - while (token != 0xFE && (diffTime_ms(start, getTime_ms()) <= 200)) + while (token != 0xFE && likely(elapsedTime_ms(start) <= 200)) { - if (token && ((token & 0xE0) == 0)) + if (unlikely(token && ((token & 0xE0) == 0))) { // Error token! break; } token = sdSpiByte(0xFF); } - if (token != 0xFE) + if (unlikely(token != 0xFE)) { if (transfer.multiBlock) { @@ -245,31 +265,41 @@ dmaReadSector(uint8_t* outputBuffer) { scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = 0x4400 | token; + scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR; scsiDev.phase = STATUS; } sdClearStatus(); return; } - // Receive 512 bytes of data and then 2 bytes CRC. - CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE, sdDMARxTd[1], TD_INC_DST_ADR); - CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer)); - CyDmaTdSetConfiguration(sdDMARxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN); - CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); + static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD}; + static uint8_t dmaTxTd = CY_DMA_INVALID_TD; + if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD)) + { + dmaRxTd[0] = CyDmaTdAllocate(); + dmaRxTd[1] = CyDmaTdAllocate(); + dmaTxTd = CyDmaTdAllocate(); + + // Receive 512 bytes of data and then 2 bytes CRC. + CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE, dmaRxTd[1], TD_INC_DST_ADR); + CyDmaTdSetConfiguration(dmaRxTd[1], 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); + + CyDmaTdSetConfiguration(dmaTxTd, SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(dmaTxTd, LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR)); - CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN); - CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR)); + } + CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)outputBuffer)); sdIOState = SD_DMA; - txDMAComplete = 0; - rxDMAComplete = 0; + sdTxDMAComplete = 0; + sdRxDMAComplete = 0; // Re-loading the initial TD's here is very important, or else // we'll be re-using the last-used TD, which would be the last // in the chain (ie. CRC TD) - CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]); - CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]); + CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]); + CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd); // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was @@ -286,7 +316,7 @@ dmaReadSector(uint8_t* outputBuffer) int sdReadSectorDMAPoll() { - if (rxDMAComplete && txDMAComplete) + if (sdRxDMAComplete && sdTxDMAComplete) { // DMA transfer is complete sdIOState = SD_IDLE; @@ -306,14 +336,14 @@ void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer) lba = lba * SD_SECTOR_SIZE; } v = sdCommandAndResponse(SD_READ_SINGLE_BLOCK, lba); - if (v) + if (unlikely(v)) { scsiDiskReset(); sdClearStatus(); scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION; + scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -332,29 +362,26 @@ sdReadMultiSectorDMA(uint8_t* outputBuffer) void sdCompleteRead() { - if (sdIOState != SD_IDLE) + if (unlikely(sdIOState != SD_IDLE)) { // Not much choice but to wait until we've completed the transfer. // Cancelling the transfer can't be done as we have no way to reset // the SD card. while (!sdReadSectorDMAPoll()) { /* spin */ } } - transfer.inProgress = 0; - - // We cannot send even a single "padding" byte, as we normally would when - // sending a command. If we've just finished reading the very last block - // on the card, then reading an additional dummy byte will just trigger - // an error condition as we're trying to read past-the-end of the storage - // device. - // ie. do not use sdCommandAndResponse here. - uint8 r1b = sdDoCommand(SD_STOP_TRANSMISSION, 0, 0, 0); - - if (r1b) + + if (transfer.inProgress) { - scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR | r1b; - scsiDev.phase = STATUS; + transfer.inProgress = 0; + uint8 r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0); + + if (unlikely(r1b)) + { + scsiDev.status = CHECK_CONDITION; + scsiDev.target->sense.code = HARDWARE_ERROR; + scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR; + scsiDev.phase = STATUS; + } } // R1b has an optional trailing "busy" signal, but we defer waiting on this. @@ -374,22 +401,34 @@ static void sdWaitWriteBusy() void sdWriteMultiSectorDMA(uint8_t* outputBuffer) { - // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte - // We need to do this without stopping the clock - CyDmaTdSetConfiguration(sdDMATxTd[0], 1, sdDMATxTd[1], TD_INC_SRC_ADR); - CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR)); + static uint8_t dmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD}; + static uint8_t dmaTxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD}; + if (unlikely(dmaRxTd[0] == CY_DMA_INVALID_TD)) + { + dmaRxTd[0] = CyDmaTdAllocate(); + dmaRxTd[1] = CyDmaTdAllocate(); + dmaTxTd[0] = CyDmaTdAllocate(); + dmaTxTd[1] = CyDmaTdAllocate(); + dmaTxTd[2] = CyDmaTdAllocate(); + + // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte + // We need to do this without stopping the clock + CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR); + CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR)); - CyDmaTdSetConfiguration(sdDMATxTd[1], SD_SECTOR_SIZE, sdDMATxTd[2], TD_INC_SRC_ADR); - CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR)); + CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR); + + CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN); + CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR)); + + CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0); + CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); + CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR); + CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer)); + } + CyDmaTdSetAddress(dmaTxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR)); - CyDmaTdSetConfiguration(sdDMATxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN); - CyDmaTdSetAddress(sdDMATxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR)); - CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 3, sdDMARxTd[1], 0); - CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer)); - CyDmaTdSetConfiguration(sdDMARxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR); - CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer)); - sdIOState = SD_DMA; // The DMA controller is a bit trigger-happy. It will retain // a drq request that was triggered while the channel was @@ -397,14 +436,14 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer) CyDmaClearPendingDrq(sdDMATxChan); CyDmaClearPendingDrq(sdDMARxChan); - txDMAComplete = 0; - rxDMAComplete = 0; + sdTxDMAComplete = 0; + sdRxDMAComplete = 0; // Re-loading the initial TD's here is very important, or else // we'll be re-using the last-used TD, which would be the last // in the chain (ie. CRC TD) - CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]); - CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]); + CyDmaChSetInitialTd(sdDMARxChan, dmaRxTd[0]); + CyDmaChSetInitialTd(sdDMATxChan, dmaTxTd[0]); // There is no flow control, so we must ensure we can read the bytes // before we start transmitting @@ -415,7 +454,7 @@ sdWriteMultiSectorDMA(uint8_t* outputBuffer) int sdWriteSectorDMAPoll(int sendStopToken) { - if (rxDMAComplete && txDMAComplete) + if (sdRxDMAComplete && sdTxDMAComplete) { if (sdIOState == SD_DMA) { @@ -431,7 +470,7 @@ sdWriteSectorDMAPoll(int sendStopToken) // At this point we should either have an accepted token, or we'll // timeout and proceed into the error case below. - if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted. + if (unlikely(((dataToken & 0x1F) >> 1) != 0x2)) // Accepted. { sdIOState = SD_IDLE; @@ -445,7 +484,7 @@ sdWriteSectorDMAPoll(int sendStopToken) scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = 0x6900 | dataToken; + scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -492,7 +531,7 @@ sdWriteSectorDMAPoll(int sendStopToken) void sdCompleteWrite() { - if (sdIOState != SD_IDLE) + if (unlikely(sdIOState != SD_IDLE)) { // Not much choice but to wait until we've completed the transfer. // Cancelling the transfer can't be done as we have no way to reset @@ -500,13 +539,10 @@ void sdCompleteWrite() while (!sdWriteSectorDMAPoll(1)) { /* spin */ } } - transfer.inProgress = 0; - - if (scsiDev.phase == DATA_OUT) + if (transfer.inProgress && likely(scsiDev.phase == DATA_OUT)) { - sdSpiByte(0xFF); uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1); - if (r2) + if (unlikely(r2)) { sdClearStatus(); scsiDev.status = CHECK_CONDITION; @@ -515,6 +551,7 @@ void sdCompleteWrite() scsiDev.phase = STATUS; } } + transfer.inProgress = 0; } @@ -569,7 +606,7 @@ static int sdOpCond() sdClearStatus(); // Spec says to poll for 1 second. - } while ((status != 0) && (diffTime_ms(start, getTime_ms()) < 1000)); + } while ((status != 0) && (elapsedTime_ms(start) < 1000)); return status == 0; } @@ -598,7 +635,7 @@ static int sdReadOCR() } while (!status && !complete && - (diffTime_ms(start, getTime_ms()) < 1000)); + (elapsedTime_ms(start) < 1000)); return (status == 0) && complete; } @@ -702,12 +739,6 @@ static void sdInitDMA() CyDmaChDisable(sdDMATxChan); CyDmaChDisable(sdDMARxChan); - sdDMARxTd[0] = CyDmaTdAllocate(); - sdDMARxTd[1] = CyDmaTdAllocate(); - sdDMATxTd[0] = CyDmaTdAllocate(); - sdDMATxTd[1] = CyDmaTdAllocate(); - sdDMATxTd[2] = CyDmaTdAllocate(); - SD_RX_DMA_COMPLETE_StartEx(sdRxISR); SD_TX_DMA_COMPLETE_StartEx(sdTxISR); } @@ -791,6 +822,7 @@ int sdInit() goto out; bad: + SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry sdDev.capacity = 0; out: @@ -826,13 +858,13 @@ void sdWriteMultiSectorPrep() sdLBA = sdLBA * SD_SECTOR_SIZE; } v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA); - if (v) + if (unlikely(v)) { scsiDiskReset(); sdClearStatus(); scsiDev.status = CHECK_CONDITION; scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = 0x8800 | v; + scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -854,7 +886,7 @@ void sdPoll() // overpower the SD pullup resistor. SD_CS_Write(0); SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ); - + CyDelayCycles(64); uint8_t cs = SD_CS_Read(); SD_CS_SetDriveMode(SD_CS_DM_STRONG) ; @@ -862,14 +894,14 @@ void sdPoll() if (cs && !(blockDev.state & DISK_PRESENT)) { static int firstInit = 1; - + // Debounce CyDelay(250); - + if (sdInit()) { blockDev.state |= DISK_PRESENT | DISK_INITIALISED; - + if (!firstInit) { int i; @@ -894,3 +926,5 @@ void sdPoll() } } } + +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/sd.h b/software/SCSI2SD/src/sd.h index abb4507..3b4a11d 100755 --- a/software/SCSI2SD/src/sd.h +++ b/software/SCSI2SD/src/sd.h @@ -61,9 +61,13 @@ typedef struct } SdDevice; extern SdDevice sdDev; +extern volatile uint8_t sdRxDMAComplete; +extern volatile uint8_t sdTxDMAComplete; int sdInit(void); +#define sdDMABusy() (!(sdRxDMAComplete && sdTxDMAComplete)) + void sdWriteMultiSectorPrep(void); void sdWriteMultiSectorDMA(uint8_t* outputBuffer); int sdWriteSectorDMAPoll(int sendStopToken); diff --git a/software/SCSI2SD/src/time.c b/software/SCSI2SD/src/time.c index 3880a9d..3d6b3fe 100755 --- a/software/SCSI2SD/src/time.c +++ b/software/SCSI2SD/src/time.c @@ -14,6 +14,8 @@ // // You should have received a copy of the GNU General Public License // along with SCSI2SD. If not, see . +#pragma GCC push_options +#pragma GCC optimize("-flto") #include "time.h" #include "limits.h" @@ -54,3 +56,18 @@ uint32_t diffTime_ms(uint32_t start, uint32_t end) return (UINT_MAX - start) + end; } } + +uint32_t elapsedTime_ms(uint32_t since) +{ + uint32_t now = counter; + if (now >= since) + { + return now - since; + } + else + { + return (UINT_MAX - since) + now; + } +} + +#pragma GCC pop_options diff --git a/software/SCSI2SD/src/time.h b/software/SCSI2SD/src/time.h index 69b88eb..ca1ebe0 100755 --- a/software/SCSI2SD/src/time.h +++ b/software/SCSI2SD/src/time.h @@ -22,5 +22,6 @@ void timeInit(void); uint32_t getTime_ms(void); // Returns milliseconds since init uint32_t diffTime_ms(uint32_t start, uint32_t end); +uint32_t elapsedTime_ms(uint32_t since); #endif diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index a110bfa..0db6988 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -381,32 +381,32 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u @@ -419,29 +419,29 @@ #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -449,9 +449,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST /* SD_SCK */ #define SD_SCK__0__MASK 0x04u @@ -1909,24 +1909,24 @@ /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -2366,7 +2366,7 @@ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u #define SD_RX_DMA__NUMBEROF_TDS 0u -#define SD_RX_DMA__PRIORITY 2u +#define SD_RX_DMA__PRIORITY 0u #define SD_RX_DMA__TERMIN_EN 0u #define SD_RX_DMA__TERMIN_SEL 0u #define SD_RX_DMA__TERMOUT0_EN 1u @@ -2388,7 +2388,7 @@ #define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_TX_DMA__DRQ_NUMBER 3u #define SD_TX_DMA__NUMBEROF_TDS 0u -#define SD_TX_DMA__PRIORITY 2u +#define SD_TX_DMA__PRIORITY 1u #define SD_TX_DMA__TERMIN_EN 0u #define SD_TX_DMA__TERMIN_SEL 0u #define SD_TX_DMA__TERMOUT0_EN 1u @@ -2677,57 +2677,57 @@ #define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW /* scsiTarget */ -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB05_06_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB05_06_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB05_06_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB05_06_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB05_06_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB05_06_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB05_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB05_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB05_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB05_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB05_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB05_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB05_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB05_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB05_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB05_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB05_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB05_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB05_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB05_MSK +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2735,13 +2735,9 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST /* Debug_Timer_Interrupt */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2852,8 +2848,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2861,49 +2857,45 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK -#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index f8cc0b1..7b14d7c 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -380,43 +380,43 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x4001004Eu, /* Base address: 0x40010000 Count: 78 */ + 0x4001003Eu, /* Base address: 0x40010000 Count: 62 */ 0x40010137u, /* Base address: 0x40010100 Count: 55 */ - 0x4001024Du, /* Base address: 0x40010200 Count: 77 */ - 0x40010353u, /* Base address: 0x40010300 Count: 83 */ - 0x40010439u, /* Base address: 0x40010400 Count: 57 */ - 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */ - 0x40010621u, /* Base address: 0x40010600 Count: 33 */ - 0x40010754u, /* Base address: 0x40010700 Count: 84 */ - 0x40010918u, /* Base address: 0x40010900 Count: 24 */ - 0x40010A42u, /* Base address: 0x40010A00 Count: 66 */ + 0x40010246u, /* Base address: 0x40010200 Count: 70 */ + 0x40010350u, /* Base address: 0x40010300 Count: 80 */ + 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */ + 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */ + 0x40010654u, /* Base address: 0x40010600 Count: 84 */ + 0x40010750u, /* Base address: 0x40010700 Count: 80 */ + 0x40010851u, /* Base address: 0x40010800 Count: 81 */ + 0x40010958u, /* Base address: 0x40010900 Count: 88 */ + 0x40010A46u, /* Base address: 0x40010A00 Count: 70 */ 0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */ - 0x40010C43u, /* Base address: 0x40010C00 Count: 67 */ - 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */ - 0x40010E55u, /* Base address: 0x40010E00 Count: 85 */ - 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */ - 0x40011451u, /* Base address: 0x40011400 Count: 81 */ - 0x4001154Bu, /* Base address: 0x40011500 Count: 75 */ - 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */ + 0x40010C46u, /* Base address: 0x40010C00 Count: 70 */ + 0x40010D4Au, /* Base address: 0x40010D00 Count: 74 */ + 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */ + 0x4001145Fu, /* Base address: 0x40011400 Count: 95 */ + 0x40011558u, /* Base address: 0x40011500 Count: 88 */ + 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */ 0x40011750u, /* Base address: 0x40011700 Count: 80 */ 0x40011804u, /* Base address: 0x40011800 Count: 4 */ - 0x40011910u, /* Base address: 0x40011900 Count: 16 */ - 0x40011B07u, /* Base address: 0x40011B00 Count: 7 */ - 0x40014016u, /* Base address: 0x40014000 Count: 22 */ - 0x4001411Cu, /* Base address: 0x40014100 Count: 28 */ - 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */ - 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ - 0x40014411u, /* Base address: 0x40014400 Count: 17 */ - 0x4001451Au, /* Base address: 0x40014500 Count: 26 */ - 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */ - 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */ - 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */ - 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */ - 0x40014C05u, /* Base address: 0x40014C00 Count: 5 */ - 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */ + 0x40011913u, /* Base address: 0x40011900 Count: 19 */ + 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */ + 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ + 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */ + 0x4001420Bu, /* Base address: 0x40014200 Count: 11 */ + 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */ + 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ + 0x40014518u, /* Base address: 0x40014500 Count: 24 */ + 0x40014611u, /* Base address: 0x40014600 Count: 17 */ + 0x40014711u, /* Base address: 0x40014700 Count: 17 */ + 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */ + 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */ + 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ + 0x40014D06u, /* Base address: 0x40014D00 Count: 6 */ 0x40015002u, /* Base address: 0x40015000 Count: 2 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -425,790 +425,681 @@ void cyfitter_cfg(void) {0x7Eu, 0x02u}, {0x01u, 0x20u}, {0x0Au, 0x36u}, - {0x00u, 0x12u}, - {0x01u, 0x04u}, + {0x00u, 0x04u}, + {0x01u, 0x11u}, + {0x18u, 0x0Cu}, {0x19u, 0x04u}, {0x1Cu, 0x71u}, - {0x20u, 0x58u}, - {0x21u, 0x98u}, + {0x20u, 0x60u}, + {0x21u, 0xC0u}, {0x2Cu, 0x0Eu}, - {0x30u, 0x0Au}, + {0x30u, 0x05u}, {0x31u, 0x0Cu}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, - {0x25u, 0x02u}, - {0x87u, 0x0Fu}, - {0x01u, 0x30u}, - {0x02u, 0x08u}, - {0x03u, 0xC0u}, - {0x05u, 0x06u}, - {0x07u, 0x09u}, - {0x09u, 0x0Fu}, - {0x0Bu, 0xF0u}, - {0x11u, 0x05u}, - {0x12u, 0x80u}, - {0x13u, 0x0Au}, - {0x16u, 0x17u}, - {0x19u, 0x03u}, - {0x1Au, 0x40u}, - {0x1Bu, 0x0Cu}, - {0x1Eu, 0x20u}, - {0x20u, 0x0Au}, - {0x22u, 0x05u}, - {0x24u, 0x50u}, - {0x25u, 0x50u}, - {0x26u, 0xA0u}, - {0x27u, 0xA0u}, - {0x28u, 0x09u}, - {0x2Au, 0x02u}, - {0x2Cu, 0x04u}, - {0x2Du, 0x60u}, - {0x2Eu, 0x08u}, - {0x2Fu, 0x90u}, - {0x32u, 0x0Fu}, - {0x34u, 0xC0u}, - {0x36u, 0x30u}, - {0x37u, 0xFFu}, - {0x3Eu, 0x50u}, - {0x3Fu, 0x40u}, - {0x56u, 0x08u}, + {0x20u, 0x02u}, + {0x86u, 0x0Fu}, + {0x02u, 0x07u}, + {0x06u, 0x70u}, + {0x08u, 0xAAu}, + {0x0Au, 0x55u}, + {0x0Eu, 0x08u}, + {0x11u, 0x01u}, + {0x15u, 0x08u}, + {0x20u, 0x44u}, + {0x22u, 0x88u}, + {0x26u, 0x80u}, + {0x28u, 0x99u}, + {0x29u, 0x02u}, + {0x2Au, 0x22u}, + {0x2Du, 0x04u}, + {0x30u, 0x0Fu}, + {0x31u, 0x04u}, + {0x33u, 0x02u}, + {0x34u, 0xF0u}, + {0x35u, 0x08u}, + {0x37u, 0x01u}, + {0x3Fu, 0x55u}, + {0x40u, 0x56u}, + {0x41u, 0x02u}, + {0x42u, 0x30u}, + {0x45u, 0xF2u}, + {0x46u, 0xCDu}, + {0x47u, 0x0Eu}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Au, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x01u}, - {0x5Du, 0x90u}, + {0x5Du, 0x01u}, {0x5Fu, 0x01u}, - {0x81u, 0x0Fu}, - {0x82u, 0x70u}, - {0x83u, 0xF0u}, - {0x84u, 0x90u}, - {0x86u, 0x2Fu}, - {0x87u, 0xFFu}, - {0x8Bu, 0xFFu}, - {0x8Cu, 0xC0u}, - {0x8Du, 0x55u}, - {0x8Eu, 0x1Fu}, - {0x8Fu, 0xAAu}, - {0x91u, 0xFFu}, - {0x92u, 0x80u}, - {0x94u, 0x06u}, - {0x95u, 0xFFu}, - {0x96u, 0x09u}, - {0x9Cu, 0x05u}, - {0x9Eu, 0x0Au}, - {0x9Fu, 0xFFu}, - {0xA0u, 0xA0u}, - {0xA2u, 0x4Fu}, - {0xA6u, 0x80u}, - {0xA8u, 0x0Fu}, - {0xA9u, 0x69u}, - {0xABu, 0x96u}, - {0xACu, 0x03u}, - {0xADu, 0x33u}, - {0xAEu, 0x0Cu}, - {0xAFu, 0xCCu}, - {0xB0u, 0x7Fu}, - {0xB1u, 0xFFu}, - {0xB2u, 0x80u}, - {0xBBu, 0x02u}, - {0xBEu, 0x04u}, - {0xD8u, 0x04u}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0x85u, 0x08u}, + {0x8Bu, 0x3Fu}, + {0x8Du, 0x40u}, + {0x91u, 0x01u}, + {0x93u, 0x14u}, + {0x95u, 0x19u}, + {0x97u, 0x22u}, + {0x99u, 0x26u}, + {0x9Bu, 0x19u}, + {0xABu, 0x02u}, + {0xB1u, 0x07u}, + {0xB3u, 0x40u}, + {0xB5u, 0x38u}, + {0xBFu, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x11u}, + {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x05u, 0x41u}, - {0x07u, 0x20u}, - {0x08u, 0x02u}, - {0x09u, 0x40u}, - {0x0Au, 0x24u}, - {0x0Bu, 0x05u}, - {0x0Du, 0x04u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x80u}, - {0x10u, 0x01u}, - {0x11u, 0x28u}, - {0x13u, 0x02u}, + {0x00u, 0x80u}, + {0x01u, 0x22u}, + {0x03u, 0x20u}, + {0x11u, 0x22u}, + {0x13u, 0x04u}, + {0x19u, 0x02u}, + {0x1Bu, 0x20u}, + {0x20u, 0x04u}, + {0x21u, 0x80u}, + {0x22u, 0x05u}, + {0x25u, 0x31u}, + {0x26u, 0x01u}, + {0x27u, 0x58u}, + {0x28u, 0x02u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x24u}, + {0x2Fu, 0x04u}, + {0x31u, 0x06u}, + {0x35u, 0x20u}, + {0x36u, 0x01u}, + {0x37u, 0x08u}, + {0x3Du, 0x04u}, + {0x3Eu, 0x90u}, + {0x41u, 0x30u}, + {0x43u, 0x08u}, + {0x49u, 0x10u}, + {0x4Au, 0x01u}, + {0x4Bu, 0x0Au}, + {0x50u, 0x08u}, + {0x52u, 0x90u}, + {0x5Au, 0x8Au}, + {0x5Bu, 0x10u}, + {0x60u, 0x54u}, + {0x61u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x50u}, + {0x6Au, 0x04u}, + {0x70u, 0x02u}, + {0x72u, 0x20u}, + {0x73u, 0x06u}, + {0x83u, 0x01u}, + {0x85u, 0x10u}, + {0x8Cu, 0x08u}, + {0xC0u, 0x0Fu}, + {0xC4u, 0x0Eu}, + {0xCAu, 0x2Cu}, + {0xCCu, 0xE3u}, + {0xCEu, 0x70u}, + {0xD0u, 0x06u}, + {0xD2u, 0x0Cu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE2u, 0x01u}, + {0xE4u, 0x0Cu}, + {0xE6u, 0x10u}, + {0x00u, 0x08u}, + {0x01u, 0x47u}, + {0x02u, 0x04u}, + {0x03u, 0x88u}, + {0x07u, 0x80u}, + {0x09u, 0x95u}, + {0x0Bu, 0x2Au}, + {0x11u, 0x03u}, + {0x13u, 0x0Cu}, + {0x14u, 0x04u}, {0x16u, 0x08u}, - {0x17u, 0x4Au}, + {0x17u, 0x70u}, {0x18u, 0x08u}, - {0x1Au, 0x22u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x50u}, - {0x21u, 0x80u}, + {0x19u, 0xA6u}, + {0x1Au, 0x14u}, + {0x1Bu, 0x59u}, + {0x1Cu, 0x08u}, + {0x1Eu, 0x05u}, + {0x23u, 0x03u}, {0x25u, 0x01u}, - {0x27u, 0x40u}, - {0x28u, 0x02u}, - {0x2Bu, 0x10u}, - {0x2Du, 0x20u}, - {0x2Eu, 0x80u}, - {0x32u, 0x12u}, - {0x35u, 0x40u}, - {0x37u, 0x0Au}, - {0x38u, 0x20u}, - {0x3Bu, 0x05u}, - {0x3Du, 0x22u}, - {0x3Fu, 0x48u}, - {0x58u, 0x04u}, - {0x59u, 0x10u}, - {0x5Au, 0x80u}, - {0x61u, 0x08u}, - {0x62u, 0x50u}, - {0x81u, 0x90u}, - {0x85u, 0x40u}, - {0x86u, 0x40u}, - {0x88u, 0x10u}, - {0x8Eu, 0x40u}, - {0xC0u, 0xB8u}, - {0xC2u, 0xBFu}, - {0xC4u, 0xFFu}, - {0xCAu, 0x3Au}, - {0xCCu, 0xD5u}, - {0xCEu, 0xF7u}, - {0xD6u, 0x0Eu}, - {0xD8u, 0x0Eu}, - {0xE0u, 0x08u}, - {0xE2u, 0x02u}, - {0xE4u, 0x01u}, - {0xE6u, 0xC4u}, - {0x01u, 0x02u}, - {0x02u, 0x07u}, - {0x07u, 0x20u}, - {0x09u, 0x57u}, - {0x0Bu, 0xA0u}, - {0x0Cu, 0x06u}, - {0x0Du, 0x03u}, - {0x0Eu, 0x01u}, - {0x11u, 0x6Fu}, - {0x13u, 0x90u}, - {0x15u, 0x08u}, - {0x17u, 0x03u}, - {0x19u, 0x30u}, - {0x1Au, 0x02u}, - {0x1Bu, 0xC0u}, - {0x1Cu, 0x01u}, - {0x1Du, 0x70u}, - {0x1Eu, 0x04u}, - {0x1Fu, 0x8Cu}, - {0x20u, 0x10u}, - {0x23u, 0x3Fu}, - {0x24u, 0x08u}, - {0x25u, 0x10u}, - {0x27u, 0x01u}, - {0x28u, 0x01u}, - {0x2Au, 0x02u}, - {0x30u, 0x10u}, - {0x32u, 0x08u}, - {0x33u, 0xF0u}, - {0x36u, 0x07u}, - {0x37u, 0x0Fu}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x05u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x06u}, + {0x30u, 0x01u}, + {0x31u, 0x0Fu}, + {0x32u, 0x0Cu}, + {0x34u, 0x02u}, + {0x35u, 0xF0u}, + {0x36u, 0x10u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x02u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x19u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x81u, 0x02u}, - {0x82u, 0x02u}, - {0x83u, 0x01u}, - {0x85u, 0x02u}, - {0x87u, 0x01u}, - {0x89u, 0x02u}, - {0x8Bu, 0x05u}, - {0x90u, 0x02u}, - {0x92u, 0x01u}, - {0x94u, 0x02u}, - {0x96u, 0x09u}, - {0x97u, 0x08u}, - {0x98u, 0x02u}, - {0x99u, 0x01u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Eu, 0x05u}, - {0xA1u, 0x02u}, - {0xA3u, 0x11u}, - {0xB0u, 0x03u}, - {0xB1u, 0x04u}, - {0xB3u, 0x10u}, - {0xB4u, 0x04u}, - {0xB5u, 0x03u}, - {0xB6u, 0x08u}, - {0xB7u, 0x08u}, - {0xBAu, 0x02u}, - {0xBBu, 0x20u}, + {0x80u, 0x02u}, + {0x84u, 0x03u}, + {0x88u, 0x10u}, + {0x8Au, 0x60u}, + {0x8Cu, 0x18u}, + {0x8Eu, 0x03u}, + {0x90u, 0x20u}, + {0x92u, 0x5Cu}, + {0x96u, 0x1Fu}, + {0x98u, 0x3Fu}, + {0x9Au, 0x40u}, + {0xA0u, 0x80u}, + {0xA5u, 0x01u}, + {0xA6u, 0x01u}, + {0xA8u, 0x27u}, + {0xA9u, 0x02u}, + {0xAAu, 0x50u}, + {0xB0u, 0x80u}, + {0xB1u, 0x02u}, + {0xB2u, 0x70u}, + {0xB3u, 0x01u}, + {0xB4u, 0x0Fu}, + {0xBAu, 0x08u}, + {0xBEu, 0x01u}, + {0xBFu, 0x05u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x99u}, + {0xDCu, 0x01u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x04u, 0x02u}, - {0x07u, 0x02u}, - {0x09u, 0x08u}, - {0x0Au, 0x8Au}, - {0x0Du, 0x80u}, - {0x0Fu, 0x08u}, - {0x16u, 0x50u}, - {0x17u, 0x20u}, - {0x19u, 0x02u}, - {0x1Au, 0x0Au}, - {0x1Du, 0xC4u}, - {0x1Fu, 0x01u}, - {0x21u, 0x01u}, - {0x22u, 0x70u}, - {0x23u, 0x18u}, - {0x27u, 0x12u}, - {0x28u, 0x40u}, - {0x2Eu, 0x08u}, - {0x2Fu, 0x80u}, - {0x32u, 0x14u}, - {0x35u, 0x40u}, - {0x37u, 0x1Au}, - {0x38u, 0x08u}, - {0x39u, 0x02u}, - {0x3Bu, 0x10u}, - {0x3Du, 0x21u}, - {0x3Fu, 0x88u}, - {0x44u, 0x01u}, - {0x45u, 0x80u}, - {0x58u, 0x24u}, - {0x5Au, 0x01u}, - {0x5Bu, 0x80u}, - {0x5Du, 0x80u}, - {0x5Eu, 0x20u}, - {0x60u, 0x08u}, - {0x62u, 0x89u}, - {0x63u, 0x40u}, - {0x65u, 0x20u}, + {0x01u, 0x81u}, + {0x02u, 0x90u}, + {0x03u, 0x18u}, + {0x05u, 0x01u}, + {0x09u, 0x01u}, + {0x0Au, 0x18u}, + {0x0Eu, 0x2Au}, + {0x11u, 0x24u}, + {0x12u, 0x40u}, + {0x16u, 0x02u}, + {0x19u, 0x30u}, + {0x1Au, 0x88u}, + {0x1Bu, 0x08u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x3Au}, + {0x20u, 0x50u}, + {0x26u, 0x02u}, + {0x27u, 0x04u}, + {0x28u, 0x28u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x84u}, + {0x35u, 0x20u}, + {0x36u, 0x02u}, + {0x37u, 0x04u}, + {0x3Du, 0x22u}, + {0x3Eu, 0x04u}, + {0x45u, 0x04u}, + {0x47u, 0x04u}, + {0x58u, 0x90u}, + {0x5Au, 0x02u}, + {0x5Bu, 0x08u}, + {0x5Fu, 0x80u}, + {0x60u, 0x02u}, + {0x61u, 0x06u}, + {0x62u, 0x05u}, + {0x63u, 0x08u}, {0x66u, 0x80u}, - {0x80u, 0x04u}, - {0x82u, 0x10u}, - {0x84u, 0x04u}, - {0x86u, 0x19u}, - {0x89u, 0x02u}, - {0x8Au, 0x08u}, - {0x8Cu, 0x08u}, - {0x8Fu, 0x98u}, - {0x90u, 0x02u}, - {0x92u, 0x50u}, - {0x95u, 0x08u}, - {0x96u, 0x04u}, - {0x97u, 0x40u}, - {0x9Au, 0x50u}, - {0x9Cu, 0x03u}, - {0x9Du, 0x60u}, - {0x9Eu, 0x88u}, - {0x9Fu, 0x2Au}, - {0xA1u, 0x08u}, - {0xA3u, 0x80u}, - {0xA4u, 0x11u}, - {0xA5u, 0x10u}, - {0xA6u, 0x02u}, - {0xA7u, 0x50u}, - {0xA8u, 0x15u}, - {0xA9u, 0x04u}, - {0xABu, 0x84u}, - {0xAEu, 0x01u}, - {0xB0u, 0x04u}, - {0xB2u, 0x11u}, - {0xC0u, 0x98u}, - {0xC2u, 0xCFu}, - {0xC4u, 0x70u}, - {0xCAu, 0xC1u}, - {0xCCu, 0xF6u}, - {0xCEu, 0xF7u}, - {0xD6u, 0x3Fu}, - {0xD8u, 0x3Fu}, - {0xE2u, 0x38u}, - {0xE4u, 0x04u}, - {0xE6u, 0x4Bu}, - {0xEAu, 0x2Cu}, - {0xEEu, 0x04u}, - {0x00u, 0x02u}, - {0x01u, 0x02u}, - {0x03u, 0x0Du}, - {0x05u, 0x0Du}, - {0x0Bu, 0x10u}, - {0x0Du, 0x0Du}, - {0x11u, 0x02u}, - {0x13u, 0x54u}, - {0x15u, 0x0Du}, - {0x19u, 0x01u}, - {0x1Bu, 0x32u}, - {0x1Du, 0x0Du}, - {0x21u, 0x0Du}, - {0x25u, 0x62u}, - {0x27u, 0x08u}, - {0x28u, 0x01u}, - {0x29u, 0x80u}, - {0x30u, 0x01u}, - {0x33u, 0x70u}, + {0x6Du, 0x14u}, + {0x6Fu, 0x22u}, + {0x83u, 0x08u}, + {0x84u, 0x90u}, + {0x86u, 0x10u}, + {0x87u, 0x80u}, + {0x88u, 0x10u}, + {0x89u, 0x10u}, + {0x8Au, 0x02u}, + {0x8Du, 0x40u}, + {0x8Fu, 0x02u}, + {0x91u, 0x60u}, + {0x92u, 0x04u}, + {0x93u, 0x08u}, + {0x94u, 0x50u}, + {0x95u, 0x04u}, + {0x96u, 0x90u}, + {0x99u, 0x02u}, + {0x9Au, 0x38u}, + {0x9Bu, 0x42u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x34u}, + {0x9Eu, 0x80u}, + {0xA0u, 0x02u}, + {0xA1u, 0x11u}, + {0xA2u, 0x80u}, + {0xA5u, 0x02u}, + {0xA7u, 0x0Cu}, + {0xA9u, 0x10u}, + {0xB6u, 0x01u}, + {0xC0u, 0x1Fu}, + {0xC2u, 0xEEu}, + {0xC4u, 0x8Eu}, + {0xCAu, 0xE6u}, + {0xCCu, 0xE0u}, + {0xCEu, 0xE0u}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE2u, 0xC4u}, + {0xE4u, 0x08u}, + {0xE6u, 0xE2u}, + {0xE8u, 0x01u}, + {0xEEu, 0x02u}, + {0x02u, 0xFFu}, + {0x04u, 0x0Fu}, + {0x05u, 0x0Fu}, + {0x06u, 0xF0u}, + {0x08u, 0x69u}, + {0x09u, 0x90u}, + {0x0Au, 0x96u}, + {0x0Bu, 0x2Fu}, + {0x0Cu, 0xFFu}, + {0x10u, 0x33u}, + {0x12u, 0xCCu}, + {0x13u, 0x70u}, + {0x15u, 0x03u}, + {0x16u, 0xFFu}, + {0x17u, 0x0Cu}, + {0x18u, 0xFFu}, + {0x1Bu, 0x80u}, + {0x1Du, 0xC0u}, + {0x1Fu, 0x1Fu}, + {0x21u, 0x06u}, + {0x23u, 0x09u}, + {0x25u, 0x05u}, + {0x27u, 0x0Au}, + {0x29u, 0xA0u}, + {0x2Au, 0xFFu}, + {0x2Bu, 0x4Fu}, + {0x2Cu, 0x55u}, + {0x2Eu, 0xAAu}, + {0x2Fu, 0x80u}, + {0x31u, 0x7Fu}, + {0x32u, 0xFFu}, {0x35u, 0x80u}, - {0x36u, 0x02u}, - {0x37u, 0x0Fu}, - {0x3Bu, 0x80u}, - {0x3Eu, 0x41u}, + {0x3Au, 0x08u}, {0x3Fu, 0x10u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, - {0x88u, 0x04u}, - {0xACu, 0x01u}, - {0xB0u, 0x02u}, - {0xB2u, 0x01u}, - {0xB4u, 0x04u}, - {0xBEu, 0x15u}, - {0xC0u, 0x14u}, - {0xC1u, 0x02u}, - {0xC2u, 0x30u}, - {0xC5u, 0xD2u}, - {0xC6u, 0xECu}, - {0xC7u, 0x0Fu}, - {0xC8u, 0x1Fu}, - {0xC9u, 0xFFu}, - {0xCAu, 0xFFu}, - {0xCBu, 0xFFu}, - {0xCFu, 0x2Cu}, - {0xD6u, 0x01u}, + {0x83u, 0x7Cu}, + {0x84u, 0x40u}, + {0x85u, 0x48u}, + {0x86u, 0x80u}, + {0x87u, 0x03u}, + {0x88u, 0x20u}, + {0x8Au, 0x18u}, + {0x92u, 0x01u}, + {0x93u, 0x01u}, + {0x94u, 0x18u}, + {0x95u, 0x70u}, + {0x96u, 0x25u}, + {0x98u, 0x2Eu}, + {0x99u, 0x04u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x23u}, + {0x9Du, 0x11u}, + {0x9Fu, 0x02u}, + {0xA0u, 0x08u}, + {0xA2u, 0x33u}, + {0xA6u, 0x80u}, + {0xAAu, 0x40u}, + {0xAFu, 0x02u}, + {0xB0u, 0x07u}, + {0xB1u, 0x0Fu}, + {0xB2u, 0xC0u}, + {0xB3u, 0x70u}, + {0xB4u, 0x38u}, + {0xBAu, 0x20u}, + {0xBEu, 0x04u}, + {0xBFu, 0x04u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, - {0xDAu, 0x04u}, + {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDDu, 0x01u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0xE2u, 0xC0u}, - {0xE6u, 0x80u}, - {0xE8u, 0x40u}, - {0xE9u, 0x40u}, - {0xEEu, 0x08u}, - {0x02u, 0x80u}, - {0x05u, 0x20u}, - {0x06u, 0x80u}, + {0x01u, 0x88u}, + {0x02u, 0x04u}, + {0x03u, 0x40u}, + {0x04u, 0x08u}, + {0x05u, 0x10u}, + {0x08u, 0x02u}, + {0x0Au, 0x18u}, + {0x0Eu, 0x64u}, + {0x11u, 0x20u}, + {0x12u, 0x01u}, + {0x14u, 0x50u}, + {0x15u, 0x02u}, + {0x16u, 0x08u}, + {0x19u, 0x08u}, + {0x1Cu, 0x20u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x40u}, + {0x1Fu, 0x10u}, + {0x20u, 0x08u}, + {0x21u, 0x02u}, + {0x23u, 0x80u}, + {0x25u, 0x09u}, + {0x29u, 0xA8u}, + {0x2Bu, 0x40u}, + {0x2Fu, 0x01u}, + {0x31u, 0x02u}, + {0x32u, 0x08u}, + {0x33u, 0x50u}, + {0x34u, 0x40u}, + {0x35u, 0x01u}, + {0x36u, 0x10u}, + {0x37u, 0x04u}, + {0x39u, 0x24u}, + {0x3Du, 0x02u}, + {0x3Eu, 0x04u}, + {0x4Cu, 0x0Cu}, + {0x58u, 0x80u}, + {0x59u, 0x04u}, + {0x5Bu, 0x20u}, + {0x5Fu, 0x80u}, + {0x60u, 0x38u}, + {0x62u, 0x40u}, + {0x63u, 0x02u}, + {0x80u, 0x10u}, + {0x88u, 0x04u}, + {0x8Eu, 0x0Au}, + {0x8Fu, 0x40u}, + {0x91u, 0xE4u}, + {0x92u, 0x18u}, + {0x98u, 0x02u}, + {0x99u, 0x22u}, + {0x9Au, 0xADu}, + {0x9Bu, 0x52u}, + {0x9Cu, 0x28u}, + {0x9Du, 0x80u}, + {0x9Eu, 0x42u}, + {0xA0u, 0x02u}, + {0xA1u, 0x14u}, + {0xA3u, 0x24u}, + {0xA4u, 0x10u}, + {0xABu, 0x80u}, + {0xADu, 0x01u}, + {0xAEu, 0x11u}, + {0xAFu, 0x20u}, + {0xB1u, 0x20u}, + {0xC0u, 0x6Fu}, + {0xC2u, 0x7Eu}, + {0xC4u, 0x73u}, + {0xCAu, 0x1Fu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xC6u}, + {0xD6u, 0x1Eu}, + {0xD8u, 0x0Eu}, + {0xE4u, 0x01u}, + {0xE6u, 0x10u}, + {0xE8u, 0x0Au}, + {0xEAu, 0x01u}, + {0xEEu, 0x02u}, + {0x00u, 0x04u}, + {0x01u, 0x33u}, + {0x02u, 0x20u}, + {0x03u, 0xCCu}, + {0x04u, 0x42u}, + {0x05u, 0x69u}, + {0x07u, 0x96u}, + {0x08u, 0x01u}, + {0x0Au, 0x5Eu}, + {0x0Bu, 0xFFu}, + {0x10u, 0x77u}, {0x12u, 0x08u}, - {0x16u, 0x01u}, - {0x19u, 0x01u}, - {0x1Au, 0x01u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x28u}, - {0x20u, 0x11u}, - {0x23u, 0x04u}, - {0x28u, 0x28u}, - {0x2Au, 0x02u}, + {0x14u, 0x39u}, + {0x15u, 0xFFu}, + {0x16u, 0x06u}, + {0x19u, 0x0Fu}, + {0x1Bu, 0xF0u}, + {0x1Cu, 0x46u}, + {0x1Fu, 0xFFu}, + {0x20u, 0x46u}, + {0x25u, 0xFFu}, + {0x26u, 0x46u}, + {0x28u, 0x42u}, + {0x2Au, 0x04u}, + {0x2Bu, 0xFFu}, + {0x2Cu, 0x46u}, + {0x2Du, 0x55u}, + {0x2Fu, 0xAAu}, {0x30u, 0x08u}, - {0x31u, 0x10u}, - {0x32u, 0x01u}, - {0x33u, 0x40u}, - {0x38u, 0x11u}, - {0x39u, 0x44u}, - {0x44u, 0x41u}, - {0x45u, 0x90u}, - {0x47u, 0x26u}, - {0x4Du, 0x01u}, - {0x4Fu, 0x08u}, - {0x54u, 0x10u}, - {0x57u, 0x68u}, - {0x5Cu, 0x40u}, - {0x5Eu, 0x29u}, - {0x65u, 0x05u}, - {0x67u, 0x06u}, - {0x6Cu, 0x24u}, - {0x6Eu, 0x02u}, - {0x6Fu, 0x01u}, - {0x74u, 0x01u}, - {0x75u, 0x80u}, - {0x76u, 0x08u}, - {0x77u, 0x10u}, - {0x84u, 0x02u}, - {0x89u, 0x04u}, - {0x8Fu, 0x10u}, - {0x92u, 0x50u}, - {0x93u, 0x02u}, - {0x95u, 0x09u}, - {0x96u, 0x04u}, - {0x98u, 0x08u}, - {0x99u, 0x24u}, - {0x9Au, 0x81u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0x9Fu, 0x20u}, - {0xA0u, 0x04u}, - {0xA1u, 0x80u}, - {0xA2u, 0xA8u}, - {0xA3u, 0x80u}, - {0xA4u, 0x11u}, - {0xA5u, 0x10u}, - {0xA6u, 0x02u}, - {0xA7u, 0x5Cu}, - {0xA9u, 0x80u}, - {0xAAu, 0x80u}, - {0xACu, 0x44u}, - {0xB0u, 0x20u}, - {0xB3u, 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0x02u}, - {0x0Bu, 0x09u}, - {0x0Cu, 0x01u}, - {0x0Eu, 0x12u}, - {0x13u, 0x08u}, - {0x17u, 0x21u}, - {0x1Au, 0x08u}, - {0x1Bu, 0x28u}, - {0x1Du, 0x01u}, - {0x1Eu, 0x10u}, - {0x20u, 0x04u}, - {0x24u, 0x30u}, - {0x26u, 0x08u}, - {0x27u, 0x24u}, - {0x29u, 0x20u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x01u}, - {0x2Cu, 0x01u}, - {0x2Fu, 0x80u}, - {0x30u, 0x08u}, - {0x32u, 0x01u}, - {0x33u, 0x60u}, - {0x36u, 0x20u}, - {0x37u, 0x06u}, - {0x39u, 0x46u}, - {0x3Bu, 0x10u}, - {0x3Cu, 0x18u}, - {0x40u, 0x28u}, - {0x41u, 0x08u}, - {0x43u, 0x02u}, - {0x49u, 0x38u}, - {0x4Au, 0x80u}, - {0x4Bu, 0x40u}, - {0x50u, 0x02u}, - {0x51u, 0x21u}, - {0x52u, 0x44u}, - {0x5Eu, 0x40u}, - {0x60u, 0x80u}, - {0x61u, 0x20u}, - {0x62u, 0x40u}, - {0x63u, 0x20u}, - {0x83u, 0x01u}, - {0x8Du, 0x01u}, - {0x8Eu, 0x10u}, - {0x90u, 0x08u}, - {0x92u, 0x40u}, - {0x95u, 0x44u}, - {0x96u, 0x06u}, - {0x98u, 0x41u}, - {0x99u, 0x80u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x13u}, - {0x9Cu, 0x20u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x64u}, - {0xA0u, 0x24u}, - {0xA2u, 0x21u}, - {0xA3u, 0x80u}, - {0xA4u, 0x08u}, - {0xA6u, 0x02u}, - {0xABu, 0x40u}, - {0xB1u, 0x01u}, - {0xB3u, 0x08u}, - {0xB4u, 0x10u}, - {0xB6u, 0x10u}, - {0xB7u, 0x20u}, - {0xC0u, 0x9Cu}, - {0xC2u, 0xB3u}, - {0xC4u, 0x54u}, - {0xCAu, 0x9Du}, - {0xCCu, 0xEFu}, - {0xCEu, 0x6Fu}, - {0xD0u, 0x07u}, - {0xD2u, 0x0Cu}, - {0xD6u, 0x10u}, - {0xD8u, 0x0Fu}, - {0xE2u, 0x01u}, - {0xE6u, 0x02u}, - {0xE8u, 0x04u}, - {0xEAu, 0x19u}, - {0xEEu, 0x08u}, - {0x82u, 0x10u}, - {0x8Du, 0x10u}, - {0x8Fu, 0x40u}, - {0x92u, 0x50u}, - {0x95u, 0x10u}, - {0x96u, 0x08u}, - {0x99u, 0x04u}, - {0x9Au, 0x02u}, - {0x9Fu, 0x14u}, - {0xA1u, 0x04u}, - {0xA5u, 0x10u}, - {0xA6u, 0x0Au}, - {0xA7u, 0x40u}, - {0xA8u, 0x05u}, - {0xB1u, 0x20u}, - {0xB2u, 0x01u}, - {0xB5u, 0x40u}, - {0xB7u, 0x01u}, - {0xE4u, 0x50u}, - {0xE6u, 0x02u}, - {0xE8u, 0x60u}, - {0xEAu, 0x08u}, - {0xECu, 0x90u}, - {0xEEu, 0x08u}, - {0x01u, 0xFFu}, - {0x05u, 0x06u}, - {0x06u, 0xFFu}, - {0x07u, 0x09u}, - {0x08u, 0x03u}, - {0x0Au, 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{0x88u, 0x50u}, + {0x8Au, 0xA0u}, + {0x8Bu, 0xFFu}, + {0x8Cu, 0x09u}, + {0x8Du, 0x05u}, + {0x8Eu, 0x06u}, + {0x8Fu, 0x0Au}, + {0x90u, 0x05u}, + {0x92u, 0x0Au}, + {0x94u, 0x90u}, + {0x95u, 0x0Fu}, + {0x96u, 0x60u}, + {0x97u, 0xF0u}, + {0x9Bu, 0xFFu}, + {0x9Cu, 0x03u}, + {0x9Du, 0x30u}, + {0x9Eu, 0x0Cu}, + {0x9Fu, 0xC0u}, + {0xA0u, 0x30u}, + {0xA1u, 0x03u}, + {0xA2u, 0xC0u}, + {0xA3u, 0x0Cu}, + {0xA4u, 0xFFu}, + {0xA5u, 0x50u}, + {0xA7u, 0xA0u}, + {0xA8u, 0x0Fu}, + {0xA9u, 0x90u}, + {0xAAu, 0xF0u}, + {0xABu, 0x60u}, + {0xADu, 0x09u}, + {0xAFu, 0x06u}, {0xB0u, 0xFFu}, - {0xB7u, 0x01u}, - {0xBAu, 0x02u}, + {0xB1u, 0xFFu}, + {0xBEu, 0x01u}, + {0xBFu, 0x01u}, + {0xD4u, 0x40u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x91u}, {0xDFu, 0x01u}, - {0x01u, 0x04u}, - {0x02u, 0x18u}, - {0x04u, 0x40u}, - {0x05u, 0x02u}, - {0x07u, 0x24u}, - {0x09u, 0x80u}, - {0x0Au, 0xF8u}, - {0x0Bu, 0x02u}, - {0x0Fu, 0x60u}, - {0x10u, 0x11u}, - {0x11u, 0xAAu}, - {0x12u, 0x44u}, - {0x14u, 0x0Au}, - {0x15u, 0x08u}, - {0x1Bu, 0x08u}, - {0x1Cu, 0x40u}, - {0x1Fu, 0x02u}, - {0x22u, 0x01u}, - {0x24u, 0x01u}, - {0x28u, 0x10u}, - {0x29u, 0x01u}, - {0x2Au, 0x40u}, - {0x30u, 0x01u}, - {0x32u, 0x54u}, - {0x35u, 0x02u}, - {0x3Au, 0x14u}, - {0x3Bu, 0x02u}, - {0x58u, 0x40u}, - {0x5Cu, 0x04u}, - {0x5Du, 0x60u}, - {0x5Eu, 0x01u}, + {0x01u, 0x01u}, + {0x03u, 0x2Au}, + {0x04u, 0x04u}, + {0x05u, 0x10u}, + {0x06u, 0x40u}, + {0x08u, 0x44u}, + {0x0Bu, 0x80u}, + {0x0Du, 0x03u}, + {0x0Eu, 0x21u}, + {0x10u, 0x88u}, + {0x11u, 0x04u}, + {0x16u, 0x02u}, + {0x17u, 0x15u}, + {0x18u, 0x80u}, + {0x1Du, 0x10u}, + {0x1Eu, 0x64u}, + {0x1Fu, 0x04u}, + {0x23u, 0x80u}, + {0x26u, 0x08u}, + {0x27u, 0x20u}, + {0x28u, 0x44u}, + {0x29u, 0x04u}, + {0x2Bu, 0x42u}, + {0x2Du, 0x08u}, + {0x2Eu, 0x90u}, + {0x30u, 0x88u}, + {0x33u, 0x20u}, + {0x37u, 0x68u}, + {0x39u, 0x84u}, + {0x3Bu, 0x90u}, + {0x3Du, 0x20u}, + {0x3Fu, 0x0Au}, + {0x59u, 0x08u}, + {0x5Au, 0x08u}, {0x60u, 0x02u}, - {0x67u, 0x01u}, - {0x6Du, 0x89u}, - {0x6Eu, 0x10u}, - {0x75u, 0x04u}, - {0x76u, 0x8Au}, - {0x86u, 0x08u}, - {0x88u, 0x40u}, - {0x8Bu, 0x02u}, - {0x8Du, 0x05u}, - {0x8Eu, 0x08u}, - {0x91u, 0x0Cu}, - {0x92u, 0x40u}, - {0x93u, 0x40u}, - {0x95u, 0x11u}, - {0x96u, 0x12u}, - {0x98u, 0x08u}, + {0x61u, 0x28u}, + {0x62u, 0x01u}, + {0x80u, 0x40u}, + {0x81u, 0x04u}, + {0x83u, 0x40u}, + {0x89u, 0x04u}, + {0x8Bu, 0x80u}, + {0x8Cu, 0x80u}, + {0x8Du, 0x10u}, + {0x91u, 0xE0u}, + {0x92u, 0x18u}, + {0x93u, 0x20u}, + {0x95u, 0x02u}, + {0x96u, 0x04u}, + {0x97u, 0x02u}, + {0x98u, 0x04u}, {0x99u, 0x02u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x11u}, + {0x9Au, 0xA0u}, + {0x9Bu, 0x4Au}, {0x9Du, 0x01u}, - {0x9Eu, 0x86u}, - {0x9Fu, 0x10u}, - {0xA1u, 0x81u}, - {0xA3u, 0x10u}, - {0xA5u, 0x40u}, - {0xA6u, 0x02u}, - {0xA7u, 0x48u}, - {0xA8u, 0x28u}, - {0xAAu, 0x08u}, - {0xABu, 0x10u}, - {0xADu, 0x20u}, - {0xAFu, 0x04u}, - {0xB3u, 0x40u}, - {0xC0u, 0xF6u}, - {0xC2u, 0x3Fu}, - {0xC4u, 0xEFu}, - {0xCAu, 0x0Bu}, - {0xCCu, 0x8Fu}, - {0xCEu, 0x07u}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE2u, 0x10u}, - {0xE6u, 0x80u}, - {0xE8u, 0x20u}, - {0xEAu, 0x98u}, - {0xEEu, 0x42u}, - {0x07u, 0xFFu}, - {0x09u, 0x0Fu}, - {0x0Bu, 0xF0u}, - {0x0Du, 0xFFu}, - {0x10u, 0x08u}, - {0x12u, 0x05u}, - {0x13u, 0xFFu}, - {0x15u, 0xFFu}, - {0x19u, 0x33u}, - {0x1Bu, 0xCCu}, - {0x1Cu, 0x0Du}, - {0x1Eu, 0x32u}, - {0x20u, 0x20u}, - {0x22u, 0x12u}, - {0x23u, 0xFFu}, - {0x25u, 0x69u}, - {0x26u, 0x40u}, - {0x27u, 0x96u}, - {0x28u, 0x04u}, - {0x2Au, 0x08u}, - {0x2Cu, 0x10u}, - {0x2Du, 0x55u}, - {0x2Eu, 0x20u}, - {0x2Fu, 0xAAu}, - {0x32u, 0x40u}, - {0x34u, 0x03u}, - {0x35u, 0xFFu}, - {0x36u, 0x3Cu}, - {0x3Bu, 0x20u}, - {0x3Eu, 0x50u}, + {0xA0u, 0x02u}, + {0xA1u, 0x14u}, + {0xA3u, 0x25u}, + {0xA4u, 0x08u}, + {0xA6u, 0x18u}, + {0xA9u, 0x80u}, + {0xABu, 0x28u}, + {0xACu, 0x80u}, + {0xB0u, 0x14u}, + {0xB1u, 0x08u}, + {0xB4u, 0x08u}, + {0xB5u, 0x04u}, + {0xB6u, 0x40u}, + {0xB7u, 0x04u}, + {0xC0u, 0x7Fu}, + {0xC2u, 0xBDu}, + {0xC4u, 0xFEu}, + {0xCAu, 0x7Fu}, + {0xCCu, 0x7Eu}, + {0xCEu, 0xEEu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x05u}, + {0xE2u, 0x0Au}, + {0xEAu, 0x05u}, + {0xEEu, 0x62u}, + {0x00u, 0x0Fu}, + {0x02u, 0xF0u}, + {0x03u, 0xFFu}, + {0x04u, 0x50u}, + {0x05u, 0x30u}, + {0x06u, 0xA0u}, + {0x07u, 0xC0u}, + {0x0Du, 0x06u}, + {0x0Eu, 0xFFu}, + {0x0Fu, 0x09u}, + {0x10u, 0x06u}, + {0x12u, 0x09u}, + {0x14u, 0x05u}, + {0x15u, 0x03u}, + {0x16u, 0x0Au}, + {0x17u, 0x0Cu}, + {0x18u, 0x30u}, + {0x19u, 0x05u}, + {0x1Au, 0xC0u}, + {0x1Bu, 0x0Au}, + {0x1Cu, 0x60u}, + {0x1Eu, 0x90u}, + {0x1Fu, 0xFFu}, + {0x20u, 0xFFu}, + {0x21u, 0x60u}, + {0x23u, 0x90u}, + {0x24u, 0x03u}, + {0x25u, 0x50u}, + {0x26u, 0x0Cu}, + {0x27u, 0xA0u}, + {0x29u, 0xFFu}, + {0x2Au, 0xFFu}, + {0x2Du, 0x0Fu}, + {0x2Fu, 0xF0u}, + {0x32u, 0xFFu}, + {0x33u, 0xFFu}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x19u}, {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x82u, 0x02u}, + {0x82u, 0x20u}, + {0x83u, 0x02u}, + {0x84u, 0x08u}, + {0x86u, 0x04u}, + {0x88u, 0x04u}, {0x89u, 0x04u}, - {0x8Bu, 0x08u}, - {0x92u, 0x04u}, - {0x95u, 0x08u}, - {0x97u, 0x04u}, - {0x99u, 0x08u}, - {0x9Bu, 0x05u}, - {0x9Du, 0x08u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x04u}, - {0xA2u, 0x08u}, - {0xAAu, 0x01u}, - {0xABu, 0x02u}, - {0xADu, 0x08u}, - {0xAFu, 0x04u}, - {0xB0u, 0x03u}, - {0xB2u, 0x08u}, + {0x8Au, 0x08u}, + {0x8Cu, 0x08u}, + {0x8Eu, 0x04u}, + {0x91u, 0x04u}, + {0x94u, 0x08u}, + {0x95u, 0x01u}, + {0x96u, 0x14u}, + {0x99u, 0x04u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0x04u}, + {0xA5u, 0x04u}, + {0xA6u, 0x01u}, + {0xAAu, 0x02u}, + {0xACu, 0x01u}, + {0xAEu, 0x02u}, + {0xB0u, 0x10u}, + {0xB1u, 0x01u}, + {0xB2u, 0x0Cu}, {0xB3u, 0x02u}, - {0xB4u, 0x04u}, - {0xB5u, 0x0Cu}, - {0xB7u, 0x01u}, - {0xBBu, 0x20u}, - {0xBEu, 0x01u}, + {0xB4u, 0x20u}, + {0xB5u, 0x04u}, + {0xB6u, 0x03u}, + {0xB9u, 0x20u}, + {0xBAu, 0x08u}, + {0xBEu, 0x40u}, + {0xBFu, 0x10u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, @@ -1216,740 +1107,953 @@ void cyfitter_cfg(void) {0xDCu, 0x99u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x08u, 0x02u}, - {0x09u, 0x40u}, - {0x0Du, 0x40u}, - {0x0Fu, 0x80u}, - {0x12u, 0x84u}, - {0x15u, 0x01u}, - {0x16u, 0x12u}, - {0x17u, 0x10u}, - {0x18u, 0x80u}, - {0x19u, 0x14u}, - {0x1Du, 0x80u}, - {0x1Eu, 0x05u}, - {0x1Fu, 0x04u}, - {0x21u, 0x18u}, - {0x22u, 0x80u}, - {0x23u, 0x08u}, - {0x25u, 0x30u}, - {0x28u, 0x02u}, - {0x2Bu, 0x04u}, - {0x2Du, 0x8Au}, - {0x31u, 0x14u}, - {0x32u, 0x80u}, - {0x34u, 0x28u}, - {0x36u, 0x02u}, + {0x00u, 0x41u}, + {0x03u, 0x28u}, + {0x04u, 0x0Au}, + {0x06u, 0x02u}, + {0x07u, 0x20u}, + {0x09u, 0x08u}, + {0x0Bu, 0x01u}, + {0x0Eu, 0x21u}, + {0x0Fu, 0x88u}, + {0x10u, 0x10u}, + {0x11u, 0x80u}, + {0x13u, 0x20u}, + {0x14u, 0x40u}, + {0x15u, 0x10u}, + {0x17u, 0x08u}, + {0x18u, 0x40u}, + {0x19u, 0x40u}, + {0x1Au, 0x84u}, + {0x1Bu, 0x08u}, + {0x1Du, 0x04u}, + {0x21u, 0x28u}, + {0x22u, 0x01u}, + {0x27u, 0x10u}, + {0x29u, 0x04u}, + {0x2Du, 0x30u}, + {0x2Eu, 0x09u}, + {0x2Fu, 0x42u}, + {0x32u, 0x06u}, + {0x33u, 0x10u}, + {0x34u, 0x50u}, + {0x35u, 0x80u}, + {0x36u, 0x18u}, + {0x37u, 0x08u}, {0x39u, 0x20u}, - {0x3Du, 0x20u}, - {0x3Eu, 0x08u}, - {0x3Fu, 0x40u}, - {0x59u, 0x20u}, - {0x5Au, 0x80u}, - {0x5Du, 0x42u}, - {0x5Eu, 0x20u}, - {0x5Fu, 0x08u}, - {0x60u, 0x02u}, - {0x62u, 0x30u}, - {0x67u, 0x02u}, - {0x68u, 0x01u}, - {0x69u, 0x80u}, - {0x6Au, 0x40u}, - {0x6Cu, 0x08u}, - {0x6Du, 0x04u}, - {0x6Eu, 0x80u}, - {0x80u, 0x08u}, - {0x82u, 0x20u}, - {0x83u, 0x01u}, - {0x85u, 0x04u}, - {0x89u, 0x04u}, - {0x8Au, 0x54u}, - {0x8Du, 0x08u}, - {0x8Eu, 0x40u}, - {0x91u, 0x40u}, - {0x94u, 0x80u}, - {0x95u, 0x14u}, - {0x96u, 0x53u}, - {0x99u, 0x82u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0x11u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x84u}, - {0xA1u, 0x01u}, - {0xA3u, 0x04u}, - {0xA5u, 0x28u}, - {0xA7u, 0x08u}, - {0xA9u, 0x02u}, + {0x3Bu, 0x01u}, + {0x3Du, 0x08u}, + {0x3Eu, 0x02u}, + {0x3Fu, 0x88u}, + {0x58u, 0x20u}, + {0x5Bu, 0x40u}, + {0x62u, 0x10u}, + {0x63u, 0x01u}, + {0x6Cu, 0x01u}, + {0x6Du, 0x80u}, + {0x6Fu, 0x02u}, + {0x81u, 0x01u}, + {0x82u, 0x0Au}, + {0x83u, 0x40u}, + {0x85u, 0x20u}, + {0x88u, 0x04u}, + {0x89u, 0x30u}, + {0x8Cu, 0x10u}, + {0x8Du, 0x0Cu}, + {0x90u, 0x29u}, + {0x92u, 0x08u}, + {0x93u, 0x80u}, + {0x94u, 0x02u}, + {0x96u, 0x86u}, + {0x9Cu, 0x0Cu}, + {0x9Du, 0x49u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x45u}, + {0xA2u, 0x10u}, + {0xA3u, 0xA0u}, + {0xA6u, 0x04u}, + {0xA7u, 0x4Au}, {0xAAu, 0x40u}, - {0xADu, 0x20u}, - {0xB0u, 0x20u}, - {0xB3u, 0x20u}, - {0xC0u, 0x08u}, - {0xC2u, 0x99u}, - {0xC4u, 0xFAu}, - {0xCAu, 0xDCu}, - {0xCCu, 0xEEu}, - {0xCEu, 0x74u}, - {0xD6u, 0xFCu}, - {0xD8u, 0x1Cu}, - {0xE0u, 0xC0u}, - {0xE2u, 0x28u}, - {0xE4u, 0x80u}, - {0xE6u, 0x18u}, - {0xECu, 0x20u}, - {0xEEu, 0x80u}, - {0x00u, 0x01u}, - {0x02u, 0x02u}, - {0x04u, 0x02u}, - {0x05u, 0x02u}, - {0x06u, 0x01u}, - {0x09u, 0x02u}, - {0x0Du, 0x08u}, - {0x0Fu, 0x05u}, - {0x11u, 0x02u}, - {0x12u, 0x08u}, + {0xB0u, 0x22u}, + {0xB2u, 0x08u}, + {0xB3u, 0x40u}, + {0xB5u, 0x02u}, + {0xB6u, 0x02u}, + {0xC0u, 0xBFu}, + {0xC2u, 0xF5u}, + {0xC4u, 0x77u}, + {0xCAu, 0xF2u}, + {0xCCu, 0x77u}, + {0xCEu, 0xD5u}, + {0xD6u, 0x0Cu}, + {0xD8u, 0x0Cu}, + {0xE0u, 0x40u}, + {0xE2u, 0x22u}, + {0xE4u, 0x20u}, + {0xE6u, 0x41u}, + {0xE8u, 0x40u}, + {0xEAu, 0x31u}, + {0xEEu, 0x92u}, + {0x00u, 0x02u}, + {0x02u, 0x01u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x02u}, + {0x11u, 0x06u}, + {0x12u, 0x10u}, {0x14u, 0x02u}, - {0x15u, 0x02u}, - {0x16u, 0x01u}, + {0x15u, 0x01u}, + {0x16u, 0x05u}, + {0x17u, 0x02u}, {0x18u, 0x02u}, - {0x19u, 0x08u}, - {0x1Au, 0x05u}, - {0x1Bu, 0x04u}, - {0x1Du, 0x04u}, - {0x1Fu, 0x08u}, - {0x21u, 0x08u}, - {0x23u, 0x14u}, - {0x24u, 0x02u}, - {0x26u, 0x11u}, - {0x2Du, 0x08u}, - {0x2Fu, 0x04u}, + {0x1Au, 0x01u}, + {0x25u, 0x02u}, + {0x27u, 0x01u}, + {0x28u, 0x02u}, + {0x29u, 0x01u}, + {0x2Au, 0x09u}, + {0x2Bu, 0x04u}, {0x30u, 0x03u}, - {0x31u, 0x10u}, - {0x32u, 0x04u}, - {0x33u, 0x02u}, + {0x31u, 0x07u}, + {0x32u, 0x08u}, {0x34u, 0x10u}, - {0x35u, 0x01u}, - {0x36u, 0x08u}, - {0x37u, 0x0Cu}, - {0x39u, 0x08u}, + {0x36u, 0x04u}, + {0x39u, 0x02u}, {0x3Au, 0x02u}, - {0x3Bu, 0x80u}, - {0x3Fu, 0x04u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x99u}, + {0x5Cu, 0x09u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x03u}, - {0x81u, 0xFFu}, - {0x82u, 0x0Cu}, - {0x84u, 0xFFu}, - {0x87u, 0xFFu}, - {0x88u, 0x06u}, - {0x89u, 0x05u}, - {0x8Au, 0x09u}, - {0x8Bu, 0x0Au}, - {0x8Du, 0x0Fu}, - {0x8Fu, 0xF0u}, - {0x90u, 0x0Fu}, - {0x91u, 0x90u}, - {0x92u, 0xF0u}, - {0x93u, 0x60u}, - {0x94u, 0x50u}, - {0x96u, 0xA0u}, - {0x98u, 0x30u}, - {0x99u, 0x30u}, - {0x9Au, 0xC0u}, - {0x9Bu, 0xC0u}, - {0x9Du, 0x03u}, - {0x9Eu, 0xFFu}, - {0x9Fu, 0x0Cu}, - {0xA1u, 0xFFu}, - {0xA5u, 0x09u}, - {0xA6u, 0xFFu}, - {0xA7u, 0x06u}, - {0xA8u, 0x05u}, - {0xA9u, 0x50u}, - {0xAAu, 0x0Au}, - {0xABu, 0xA0u}, - {0xACu, 0x60u}, - {0xAEu, 0x90u}, - {0xB2u, 0xFFu}, + {0x80u, 0x0Fu}, + {0x82u, 0xF0u}, + {0x84u, 0x06u}, + {0x85u, 0xFFu}, + {0x86u, 0x09u}, + {0x88u, 0x60u}, + {0x89u, 0x55u}, + {0x8Au, 0x90u}, + {0x8Bu, 0xAAu}, + {0x94u, 0x05u}, + {0x95u, 0x0Fu}, + {0x96u, 0x0Au}, + {0x97u, 0xF0u}, + {0x98u, 0x03u}, + {0x9Au, 0x0Cu}, + {0x9Bu, 0xFFu}, + {0x9Du, 0x33u}, + {0x9Fu, 0xCCu}, + {0xA1u, 0x96u}, + {0xA3u, 0x69u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x50u}, + {0xAAu, 0xA0u}, + {0xABu, 0xFFu}, + {0xACu, 0x30u}, + {0xADu, 0xFFu}, + {0xAEu, 0xC0u}, {0xB3u, 0xFFu}, - {0xBEu, 0x04u}, - {0xBFu, 0x04u}, + {0xB4u, 0xFFu}, + {0xBBu, 0x08u}, + {0xBEu, 0x10u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x10u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x0Au}, - {0x04u, 0x08u}, - {0x05u, 0x01u}, - {0x06u, 0x0Cu}, - {0x07u, 0x40u}, - {0x08u, 0x02u}, - {0x09u, 0x08u}, - {0x0Au, 0x04u}, - {0x0Cu, 0x10u}, - {0x0Eu, 0x51u}, - {0x12u, 0x10u}, - {0x14u, 0x01u}, - {0x15u, 0x14u}, - {0x19u, 0x0Au}, - {0x1Au, 0x04u}, - {0x1Bu, 0x84u}, - {0x1Fu, 0x04u}, - {0x21u, 0x40u}, - {0x22u, 0x58u}, - {0x23u, 0x40u}, - {0x24u, 0x20u}, - {0x28u, 0x02u}, - {0x2Bu, 0x80u}, - {0x2Eu, 0x19u}, - {0x32u, 0x51u}, - {0x33u, 0x08u}, - {0x34u, 0x11u}, - {0x37u, 0x40u}, - {0x38u, 0x20u}, - {0x3Bu, 0x48u}, - {0x3Du, 0x16u}, - {0x3Eu, 0x40u}, - {0x58u, 0xA0u}, - {0x60u, 0x02u}, - {0x62u, 0x10u}, - {0x79u, 0xC0u}, - {0x80u, 0x44u}, - {0x81u, 0x01u}, - {0x84u, 0x80u}, - {0x85u, 0x80u}, - {0x86u, 0x80u}, - {0x8Eu, 0x08u}, - {0xC0u, 0x7Cu}, - {0xC2u, 0xFEu}, - {0xC4u, 0xE4u}, - {0xCAu, 0xE9u}, - {0xCCu, 0xBFu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x0Cu}, - {0xD8u, 0x0Cu}, - {0xE0u, 0x01u}, - {0xE2u, 0x10u}, - {0xE6u, 0x46u}, - {0x00u, 0x0Cu}, - {0x02u, 0x10u}, - {0x04u, 0x11u}, - {0x06u, 0x62u}, - {0x08u, 0xC0u}, - {0x0Cu, 0x1Cu}, - {0x0Du, 0x04u}, - {0x0Fu, 0x03u}, - {0x10u, 0x24u}, - {0x11u, 0x23u}, - {0x12u, 0x10u}, - {0x13u, 0x04u}, - {0x14u, 0x70u}, - {0x15u, 0x25u}, - {0x16u, 0x0Fu}, - {0x17u, 0x02u}, - {0x1Bu, 0x08u}, - {0x1Cu, 0x1Cu}, - {0x20u, 0x08u}, - {0x21u, 0x08u}, - {0x23u, 0x10u}, - {0x24u, 0x14u}, + {0x00u, 0x41u}, + {0x04u, 0x02u}, + {0x05u, 0x04u}, + {0x06u, 0x08u}, + {0x0Au, 0xA4u}, + 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{0xBFu, 0x01u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x99u}, + {0xDFu, 0x01u}, + {0x01u, 0x82u}, + {0x04u, 0x20u}, + {0x05u, 0x01u}, + {0x0Au, 0x10u}, + {0x0Bu, 0x80u}, + {0x0Fu, 0x02u}, + {0x12u, 0x18u}, + {0x15u, 0x80u}, + {0x18u, 0x02u}, + {0x19u, 0x92u}, + {0x1Au, 0x10u}, + {0x1Du, 0x04u}, + {0x1Fu, 0x40u}, + {0x20u, 0x80u}, + {0x21u, 0x40u}, + {0x22u, 0x58u}, + {0x23u, 0x04u}, + {0x24u, 0x80u}, + {0x25u, 0x10u}, + {0x26u, 0x10u}, + {0x2Bu, 0x47u}, + {0x2Cu, 0x20u}, + {0x2Du, 0x20u}, + {0x2Fu, 0x82u}, + {0x30u, 0x02u}, + {0x31u, 0x10u}, + {0x32u, 0x40u}, + {0x34u, 0x04u}, + {0x37u, 0x10u}, + {0x38u, 0x02u}, + {0x3Bu, 0x84u}, + {0x3Du, 0x24u}, + {0x58u, 0x09u}, + {0x5Au, 0x20u}, + {0x5Bu, 0x40u}, + {0x5Cu, 0x20u}, + {0x5Eu, 0x05u}, + {0x5Fu, 0x80u}, + {0x62u, 0x40u}, + {0x64u, 0x02u}, + {0x78u, 0x01u}, + {0x7Au, 0x80u}, + {0x80u, 0x08u}, + {0x81u, 0x02u}, + {0x83u, 0x48u}, + {0x85u, 0x10u}, + {0x86u, 0x84u}, + {0x88u, 0x40u}, + {0x8Du, 0x10u}, + {0x94u, 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{0x28u, 0x08u}, + {0x29u, 0x0Au}, + {0x2Du, 0x01u}, + {0x2Fu, 0x06u}, + {0x30u, 0x08u}, + {0x35u, 0x10u}, + {0x36u, 0x04u}, + {0x37u, 0x41u}, + {0x3Au, 0x10u}, + {0x3Eu, 0x12u}, + {0x41u, 0x06u}, + {0x42u, 0x01u}, + {0x43u, 0x02u}, + {0x48u, 0x01u}, + {0x49u, 0x10u}, + {0x4Bu, 0x07u}, + {0x50u, 0x44u}, + {0x51u, 0x20u}, + {0x52u, 0x40u}, + {0x58u, 0x02u}, + {0x5Bu, 0x02u}, + {0x5Eu, 0x42u}, + {0x5Fu, 0x24u}, + {0x64u, 0x02u}, + {0x66u, 0x01u}, + {0x80u, 0x40u}, + {0x82u, 0x01u}, + {0x83u, 0x20u}, + {0x84u, 0x04u}, + {0x86u, 0x01u}, + {0x88u, 0x08u}, + {0x8Au, 0x10u}, + {0x8Eu, 0x02u}, + {0x90u, 0x04u}, + {0x91u, 0x01u}, + {0x92u, 0x70u}, + {0x93u, 0x08u}, + {0x94u, 0x08u}, + {0x97u, 0x12u}, + {0x98u, 0x40u}, + {0x99u, 0x1Au}, + {0x9Au, 0x02u}, + {0x9Bu, 0x19u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x40u}, + {0xA0u, 0x09u}, + {0xA1u, 0x02u}, + {0xA2u, 0x15u}, + {0xA5u, 0x20u}, {0xA7u, 0x21u}, - {0xA9u, 0x04u}, - {0xAFu, 0x08u}, - {0xB4u, 0x08u}, - {0xC0u, 0x4Fu}, - {0xC2u, 0x7Du}, - {0xC4u, 0xBFu}, - {0xCAu, 0xDDu}, - {0xCCu, 0xF7u}, - {0xCEu, 0xC8u}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x09u}, - {0xE2u, 0x10u}, - {0xE6u, 0x01u}, - {0xE8u, 0x4Cu}, - {0x06u, 0x08u}, - {0x07u, 0x07u}, - {0x08u, 0x99u}, - {0x0Au, 0x22u}, - {0x11u, 0x44u}, - {0x13u, 0x88u}, - {0x16u, 0x07u}, - {0x17u, 0x70u}, - {0x19u, 0x99u}, - {0x1Au, 0x70u}, - {0x1Bu, 0x22u}, - {0x1Du, 0xAAu}, - {0x1Fu, 0x55u}, - {0x20u, 0xAAu}, - {0x22u, 0x55u}, - {0x27u, 0x80u}, - {0x2Au, 0x80u}, - {0x2Cu, 0x44u}, - {0x2Eu, 0x88u}, - {0x2Fu, 0x08u}, - {0x32u, 0x0Fu}, - {0x33u, 0x0Fu}, - {0x34u, 0xF0u}, - {0x35u, 0xF0u}, + {0xAAu, 0x10u}, + {0xB0u, 0x40u}, + {0xB4u, 0x02u}, + {0xB5u, 0x04u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xF5u}, + {0xC4u, 0xF2u}, + {0xCAu, 0xB7u}, + {0xCCu, 0xF2u}, + {0xCEu, 0xA4u}, + {0xD0u, 0x0Bu}, + {0xD2u, 0x0Cu}, + {0xD6u, 0xF0u}, + {0xD8u, 0x90u}, + {0xE4u, 0x02u}, + {0xE6u, 0x10u}, + {0xECu, 0x04u}, + {0x00u, 0x10u}, + {0x01u, 0xC0u}, + {0x03u, 0x02u}, + {0x05u, 0x80u}, + {0x06u, 0x01u}, + {0x08u, 0xC0u}, + {0x09u, 0xC0u}, + {0x0Au, 0x1Eu}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x18u}, + {0x0Du, 0x1Fu}, + {0x0Eu, 0x61u}, + {0x0Fu, 0x20u}, + {0x10u, 0x42u}, + {0x11u, 0x90u}, + {0x12u, 0x84u}, + {0x13u, 0x40u}, + {0x14u, 0x82u}, + {0x15u, 0xC0u}, + {0x16u, 0x5Cu}, + {0x17u, 0x04u}, + {0x18u, 0x88u}, + {0x19u, 0x7Fu}, + {0x1Au, 0x40u}, + {0x1Bu, 0x80u}, + {0x1Du, 0xC0u}, + {0x1Fu, 0x01u}, + {0x20u, 0x79u}, + {0x24u, 0x61u}, + {0x26u, 0x18u}, + {0x27u, 0x60u}, + {0x28u, 0x69u}, + {0x2Au, 0x10u}, + {0x2Bu, 0xFFu}, + {0x2Cu, 0x79u}, + {0x2Fu, 0x9Fu}, + {0x30u, 0x1Eu}, + {0x32u, 0x01u}, + {0x34u, 0xC0u}, + {0x35u, 0xFFu}, + {0x36u, 0x20u}, + {0x3Au, 0x20u}, + {0x3Eu, 0x44u}, + {0x3Fu, 0x10u}, + {0x56u, 0x02u}, + {0x57u, 0x28u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x80u, 0xC1u}, - {0x81u, 0x34u}, - {0x84u, 0x07u}, - {0x85u, 0x14u}, - {0x86u, 0x18u}, - {0x87u, 0x20u}, - {0x8Au, 0x80u}, - {0x8Bu, 0x34u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x34u}, - {0x8Eu, 0xC0u}, - {0x90u, 0x01u}, - {0x91u, 0x4Bu}, - {0x93u, 0x30u}, - {0x94u, 0x22u}, - {0x95u, 0x08u}, - {0x96u, 0x08u}, - {0x97u, 0x75u}, - {0x98u, 0x04u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x20u}, - {0x9Eu, 0x21u}, - {0x9Fu, 0x02u}, - {0xA0u, 0xC1u}, - {0xA1u, 0x34u}, - {0xA4u, 0xC1u}, - {0xA8u, 0xC0u}, - {0xA9u, 0x3Fu}, - {0xABu, 0x40u}, - {0xACu, 0x10u}, - {0xADu, 0x14u}, - {0xB0u, 0x40u}, - {0xB1u, 0x78u}, - {0xB3u, 0x07u}, - {0xB4u, 0x80u}, - {0xB6u, 0x3Fu}, - {0xB7u, 0x40u}, - {0xB8u, 0x80u}, - {0xB9u, 0x02u}, - {0xBBu, 0x0Cu}, - {0xBEu, 0x51u}, - {0xBFu, 0x40u}, - {0xD6u, 0x02u}, - {0xD7u, 0x2Cu}, + {0x80u, 0x44u}, + {0x82u, 0x88u}, + {0x86u, 0x70u}, + {0x87u, 0x07u}, + {0x89u, 0x99u}, + {0x8Bu, 0x22u}, + {0x92u, 0x07u}, + {0x93u, 0x80u}, + {0x95u, 0xAAu}, + {0x97u, 0x55u}, + {0x98u, 0xAAu}, + {0x9Au, 0x55u}, + {0x9Bu, 0x70u}, + {0x9Du, 0x44u}, + {0x9Fu, 0x88u}, + {0xA2u, 0x80u}, + {0xA8u, 0x99u}, + {0xAAu, 0x22u}, + {0xABu, 0x08u}, + {0xAEu, 0x08u}, + {0xB0u, 0x0Fu}, + {0xB2u, 0xF0u}, + {0xB3u, 0x0Fu}, + {0xB5u, 0xF0u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, + {0xDCu, 0x11u}, {0xDFu, 0x01u}, - {0x01u, 0x40u}, - {0x02u, 0x04u}, - {0x03u, 0x60u}, - {0x04u, 0x28u}, - {0x0Au, 0x4Au}, - {0x0Bu, 0x10u}, - {0x0Eu, 0x28u}, - {0x10u, 0x8Au}, - {0x11u, 0x04u}, - {0x14u, 0x41u}, - {0x16u, 0x08u}, - {0x18u, 0x01u}, - {0x19u, 0x02u}, - {0x1Bu, 0x12u}, - {0x1Eu, 0x2Cu}, - {0x21u, 0x08u}, - {0x22u, 0x41u}, - {0x23u, 0xD0u}, - {0x25u, 0x04u}, - {0x26u, 0x20u}, + {0x01u, 0x08u}, + {0x03u, 0x40u}, + {0x04u, 0x08u}, + {0x05u, 0x14u}, + {0x06u, 0x40u}, + {0x07u, 0x01u}, + {0x0Au, 0x88u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x24u}, + {0x11u, 0x60u}, + {0x13u, 0x02u}, + {0x15u, 0x01u}, + {0x16u, 0x02u}, + {0x17u, 0x14u}, + {0x19u, 0x08u}, + {0x1Au, 0x80u}, + {0x1Bu, 0x02u}, + {0x1Cu, 0x86u}, + {0x1Du, 0x0Au}, + {0x1Eu, 0x06u}, + {0x21u, 0x04u}, + {0x22u, 0x10u}, {0x27u, 0x08u}, - {0x29u, 0x20u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x01u}, - {0x2Cu, 0x20u}, - {0x2Du, 0x80u}, - {0x31u, 0x08u}, - {0x32u, 0x81u}, - {0x34u, 0x41u}, - {0x37u, 0x28u}, - {0x39u, 0x55u}, - {0x3Du, 0x08u}, - {0x60u, 0x40u}, - {0x68u, 0x49u}, - {0x69u, 0x55u}, - {0x6Bu, 0x40u}, - {0x70u, 0x80u}, - {0x72u, 0x03u}, - {0x83u, 0x01u}, - {0x88u, 0x04u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x10u}, - {0x90u, 0x28u}, - {0x91u, 0x02u}, - {0x92u, 0x08u}, - {0x94u, 0x01u}, - {0x95u, 0x44u}, - {0x96u, 0x06u}, - {0x97u, 0x50u}, - {0x98u, 0x41u}, - {0x99u, 0x88u}, - {0x9Au, 0x0Du}, - {0x9Bu, 0x30u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x20u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x40u}, - {0xA0u, 0x22u}, - {0xA2u, 0x88u}, - {0xA4u, 0x08u}, - {0xA5u, 0x08u}, - {0xA6u, 0x12u}, - {0xA7u, 0x13u}, - {0xABu, 0x08u}, - {0xB0u, 0x80u}, + {0x2Au, 0x20u}, + {0x2Fu, 0x25u}, + {0x30u, 0x02u}, + {0x32u, 0x14u}, + {0x33u, 0x40u}, + {0x35u, 0x90u}, + {0x36u, 0x04u}, + {0x37u, 0x01u}, + {0x39u, 0x28u}, + {0x3Cu, 0x84u}, + {0x3Du, 0x01u}, + {0x3Eu, 0x10u}, + {0x67u, 0x20u}, + {0x6Du, 0x01u}, + {0x6Eu, 0x19u}, + {0x6Fu, 0x15u}, + {0x75u, 0x80u}, + {0x76u, 0x02u}, + {0x87u, 0x01u}, + {0x89u, 0x04u}, + {0x8Du, 0x02u}, + {0x91u, 0x60u}, + {0x92u, 0x48u}, + {0x93u, 0x28u}, + {0x94u, 0x04u}, + {0x96u, 0x01u}, + {0x97u, 0x12u}, + {0x99u, 0x12u}, + {0x9Au, 0x20u}, + {0x9Bu, 0x42u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x42u}, + {0x9Fu, 0x15u}, + {0xA0u, 0x0Au}, + {0xA1u, 0x10u}, + {0xA2u, 0x10u}, + {0xA5u, 0x2Au}, + {0xA7u, 0x02u}, + {0xA9u, 0x04u}, + {0xABu, 0x0Au}, + {0xADu, 0x01u}, + {0xAFu, 0x30u}, + {0xB0u, 0x08u}, {0xB2u, 0x10u}, - {0xB3u, 0x04u}, {0xB6u, 0x01u}, - {0xB7u, 0x28u}, - {0xC0u, 0x6Fu}, - {0xC2u, 0x6Fu}, - {0xC4u, 0xDFu}, - {0xCAu, 0x5Du}, - {0xCCu, 0xFBu}, - {0xCEu, 0x4Fu}, - {0xD8u, 0x01u}, - {0xE2u, 0x48u}, - {0xE6u, 0x14u}, - {0xEAu, 0x20u}, - {0xECu, 0x01u}, - {0x39u, 0x20u}, - {0x3Fu, 0x10u}, - {0x59u, 0x04u}, + {0xC0u, 0xFCu}, + {0xC2u, 0x7Au}, + {0xC4u, 0xFBu}, + {0xCAu, 0x74u}, + {0xCCu, 0xFFu}, + {0xCEu, 0xF6u}, + {0xD8u, 0x40u}, + {0xE2u, 0x08u}, + {0xE8u, 0x0Cu}, + {0xECu, 0x08u}, + {0xEEu, 0x41u}, + {0x38u, 0x80u}, + {0x3Eu, 0x40u}, + {0x58u, 0x04u}, {0x5Fu, 0x01u}, - {0x27u, 0x08u}, - {0x82u, 0x02u}, - {0x87u, 0x08u}, - {0x99u, 0x04u}, - {0x9Au, 0x02u}, - {0x9Fu, 0x10u}, - {0xA1u, 0x04u}, - {0xA6u, 0x08u}, - {0xB1u, 0x10u}, - {0xB2u, 0x04u}, - {0xB6u, 0x42u}, - {0xB7u, 0x04u}, - {0xE0u, 0x20u}, + {0x1Fu, 0x40u}, + {0x87u, 0x40u}, + {0x88u, 0x04u}, + {0x8Fu, 0x04u}, + {0x9Cu, 0x24u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x41u}, + {0xA3u, 0x80u}, + {0xA6u, 0x04u}, + {0xA8u, 0x04u}, + {0xAAu, 0x08u}, + {0xABu, 0x40u}, + {0xADu, 0x80u}, + {0xAEu, 0x02u}, + {0xB0u, 0x08u}, + {0xB1u, 0x40u}, + {0xE4u, 0x90u}, {0xE8u, 0x80u}, - {0xECu, 0x11u}, - {0xEEu, 0x40u}, - {0x81u, 0x04u}, - {0x8Du, 0x04u}, - {0x99u, 0x04u}, - {0xA1u, 0x04u}, - {0xABu, 0x10u}, - {0xAEu, 0x08u}, - {0xE6u, 0x40u}, + {0xEEu, 0x20u}, + {0x88u, 0x40u}, + {0x8Bu, 0x80u}, + {0x8Cu, 0x20u}, + {0x9Cu, 0x20u}, + {0xA0u, 0x40u}, + {0xA3u, 0x80u}, + {0xAAu, 0x04u}, + {0xB0u, 0x01u}, + {0xE2u, 0x80u}, + {0xE4u, 0x02u}, + {0xE6u, 0x20u}, + {0xEAu, 0x80u}, {0x13u, 0x40u}, {0x17u, 0x48u}, - {0x32u, 0x02u}, - {0x36u, 0x80u}, + {0x33u, 0x08u}, + {0x36u, 0x20u}, {0x37u, 0x08u}, - {0x39u, 0x01u}, + {0x38u, 0x01u}, {0x3Bu, 0x40u}, - {0x3Du, 0x04u}, - {0x3Fu, 0x20u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x40u}, {0x43u, 0x10u}, - {0x58u, 0x08u}, - {0x5Eu, 0x42u}, - {0x61u, 0x08u}, - {0x66u, 0x08u}, - {0x89u, 0x01u}, - {0x8Eu, 0x40u}, + {0x52u, 0x40u}, + {0x59u, 0x08u}, + {0x5Fu, 0x01u}, + {0x61u, 0x02u}, + {0x67u, 0x10u}, + {0x81u, 0x40u}, + {0x83u, 0x01u}, + {0x8Cu, 0x01u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD6u, 0xE0u}, + {0xD4u, 0x20u}, + {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0x32u, 0x04u}, + {0xE2u, 0x80u}, + {0xE6u, 0x20u}, + {0x31u, 0x08u}, {0x33u, 0x40u}, - {0x34u, 0x10u}, - {0x36u, 0x01u}, - {0x3Bu, 0x10u}, - {0x52u, 0x20u}, - {0x56u, 0x20u}, - {0x5Bu, 0x20u}, - {0x5Fu, 0x02u}, - {0x86u, 0x20u}, - {0x8Bu, 0x02u}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x10u}, - {0x95u, 0x04u}, + {0x35u, 0x80u}, + {0x37u, 0x04u}, + {0x39u, 0x40u}, + {0x50u, 0x08u}, + {0x57u, 0x80u}, + {0x58u, 0x20u}, + {0x62u, 0x01u}, + {0x87u, 0x10u}, + {0x88u, 0x08u}, + {0x89u, 0x80u}, + {0x8Bu, 0x80u}, + {0x8Du, 0x40u}, + {0x8Eu, 0x01u}, + {0x94u, 0x04u}, + {0x97u, 0x10u}, {0x9Bu, 0x40u}, - {0x9Cu, 0x08u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x40u}, {0x9Fu, 0x10u}, - {0xA5u, 0x08u}, - {0xA6u, 0x82u}, - {0xA7u, 0x10u}, - {0xAAu, 0x01u}, - {0xB2u, 0x08u}, + {0xA5u, 0x02u}, + {0xA6u, 0x20u}, + {0xAFu, 0x08u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, {0xD4u, 0xE0u}, - {0xD6u, 0x80u}, - {0xE6u, 0x40u}, - {0xEEu, 0x80u}, - {0x12u, 0x80u}, - {0x95u, 0x04u}, - {0x96u, 0x08u}, - {0x97u, 0x10u}, - {0x9Cu, 0x18u}, - {0x9Fu, 0x10u}, - {0xA5u, 0x08u}, - {0xA6u, 0x82u}, - {0xABu, 0x20u}, - {0xB6u, 0x01u}, + {0xD8u, 0x40u}, + {0xE2u, 0x10u}, + {0xEEu, 0x40u}, + {0x12u, 0x20u}, + {0x8Fu, 0x04u}, + {0x94u, 0x04u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x14u}, + {0xA5u, 0x0Au}, + {0xA6u, 0x20u}, + {0xACu, 0x20u}, {0xC4u, 0x10u}, - {0xEAu, 0x80u}, - {0x84u, 0x10u}, - {0x95u, 0x04u}, - {0x99u, 0x20u}, - {0x9Cu, 0x18u}, - {0x9Fu, 0x10u}, - {0xA5u, 0x08u}, - {0xAAu, 0x02u}, - {0xAEu, 0x04u}, - {0xAFu, 0x10u}, - {0xB5u, 0x20u}, - {0xE6u, 0x40u}, - {0xEAu, 0x90u}, {0xEEu, 0x10u}, - {0x08u, 0x44u}, - {0x0Fu, 0x40u}, - {0x11u, 0x08u}, - {0x14u, 0x10u}, - {0x51u, 0x08u}, + {0x85u, 0x08u}, + {0x86u, 0x40u}, + {0x94u, 0x04u}, + {0x9Au, 0x80u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x10u}, + {0xA0u, 0x02u}, + {0xA5u, 0x0Au}, + {0xB2u, 0x80u}, + {0xB4u, 0x02u}, + {0xE2u, 0x50u}, + {0x08u, 0x18u}, + {0x0Fu, 0x10u}, + {0x13u, 0x02u}, + {0x14u, 0x80u}, + {0x50u, 0x04u}, + {0x52u, 0x02u}, {0x56u, 0x08u}, - {0x5Bu, 0x40u}, - {0x5Fu, 0x80u}, - {0x80u, 0x40u}, - {0x83u, 0x80u}, + {0x5Du, 0x10u}, {0x84u, 0x10u}, - {0x8Eu, 0x40u}, {0xC2u, 0x0Eu}, {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0xE2u, 0x08u}, - {0x00u, 0x40u}, + {0x00u, 0x10u}, {0x03u, 0x80u}, - {0x05u, 0x40u}, - {0x06u, 0x40u}, - {0x08u, 0x20u}, - {0x0Au, 0x80u}, - {0x0Eu, 0x11u}, - {0x84u, 0x20u}, - {0x86u, 0x01u}, - {0x89u, 0x08u}, - {0x8Eu, 0x30u}, - {0x93u, 0x40u}, - {0x94u, 0x40u}, - {0x96u, 0x80u}, + {0x04u, 0x20u}, + {0x06u, 0x80u}, + {0x08u, 0x12u}, + {0x0Cu, 0x20u}, + {0x0Du, 0x01u}, + {0x80u, 0x10u}, + {0x85u, 0x01u}, + {0x88u, 0x14u}, + {0x8Au, 0x02u}, + {0x8Eu, 0x04u}, + {0x93u, 0x10u}, + {0x95u, 0x10u}, + {0x98u, 0x88u}, + {0x9Bu, 0x02u}, {0x9Eu, 0x08u}, - {0x9Fu, 0x40u}, - {0xA1u, 0x04u}, - {0xA5u, 0x08u}, - {0xB0u, 0x44u}, + {0xA6u, 0x02u}, + {0xA8u, 0x04u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE2u, 0x08u}, + {0xE2u, 0x06u}, {0xE4u, 0x04u}, + {0xE6u, 0x01u}, + {0x85u, 0x10u}, + {0x87u, 0x10u}, + {0x8Fu, 0x01u}, + {0x90u, 0x10u}, + {0x93u, 0x10u}, + {0x95u, 0x10u}, + {0x98u, 0x88u}, + {0x9Au, 0x80u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x04u}, + {0x9Eu, 0x08u}, + {0xA6u, 0x04u}, + {0xA8u, 0x20u}, + {0xACu, 0x02u}, + {0xB3u, 0x80u}, {0xE6u, 0x08u}, {0xEAu, 0x01u}, - {0xEEu, 0x01u}, - {0x8Bu, 0x80u}, - {0x9Cu, 0x80u}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x40u}, - {0xA3u, 0x80u}, - {0xA6u, 0x20u}, - {0xAEu, 0x40u}, - {0xAFu, 0x40u}, - {0xB1u, 0x40u}, - {0xB4u, 0x80u}, - {0xB5u, 0x04u}, - {0xE2u, 0x01u}, - {0xEAu, 0x09u}, - {0xEEu, 0x02u}, - {0x08u, 0x80u}, - {0x0Bu, 0x20u}, - {0x0Eu, 0x21u}, - {0x87u, 0x10u}, - {0x96u, 0x01u}, - {0x9Cu, 0x80u}, + {0x08u, 0x04u}, + {0x0Bu, 0x01u}, + {0x0Cu, 0x08u}, + {0x0Eu, 0x08u}, + {0x80u, 0x80u}, + {0x84u, 0x08u}, + {0x97u, 0x01u}, + {0x98u, 0x80u}, + {0x9Cu, 0x04u}, {0x9Eu, 0x08u}, - {0x9Fu, 0x40u}, - {0xA6u, 0x30u}, - {0xAEu, 0x11u}, + {0xA6u, 0x04u}, + {0xAAu, 0x80u}, + {0xAFu, 0x02u}, + {0xB0u, 0x08u}, + {0xB4u, 0x10u}, {0xC2u, 0x0Fu}, + {0xEAu, 0x09u}, {0x67u, 0x80u}, + {0x85u, 0x08u}, {0x87u, 0x40u}, - {0x8Cu, 0x08u}, - {0x8Du, 0x08u}, - {0x99u, 0x20u}, - {0x9Cu, 0x08u}, + {0x9Au, 0x80u}, + {0x9Du, 0x08u}, {0x9Fu, 0x10u}, - {0xA5u, 0x08u}, - {0xB1u, 0x04u}, + {0xA0u, 0x02u}, + {0xA5u, 0x02u}, + {0xB4u, 0x04u}, {0xD8u, 0x80u}, {0xE2u, 0x10u}, - {0x04u, 0x02u}, - {0x50u, 0x04u}, - {0x59u, 0x20u}, + {0xE6u, 0x10u}, + {0x06u, 0x40u}, + {0x54u, 0x02u}, + {0x56u, 0x80u}, {0x83u, 0x10u}, - {0x8Cu, 0x04u}, - {0x94u, 0x02u}, - {0x99u, 0x20u}, + {0x86u, 0x40u}, + {0x8Du, 0x02u}, + {0x9Au, 0x80u}, {0x9Fu, 0x10u}, - {0xB4u, 0x01u}, + {0xA0u, 0x02u}, + {0xA5u, 0x02u}, {0xC0u, 0x20u}, - {0xD4u, 0xA0u}, + {0xD4u, 0x40u}, + {0xD6u, 0x20u}, + {0xE0u, 0x10u}, {0xE2u, 0x20u}, - {0x8Au, 0x08u}, {0x9Eu, 0x08u}, - {0xA6u, 0x20u}, - {0xABu, 0x40u}, - {0xE0u, 0x04u}, - {0x02u, 0x20u}, - {0xA6u, 0x20u}, + {0x01u, 0x02u}, + {0x86u, 0x08u}, + {0x8Du, 0x02u}, + {0x9Eu, 0x08u}, {0xC0u, 0x08u}, + {0xE2u, 0x02u}, {0x10u, 0x03u}, {0x1Au, 0x03u}, {0x00u, 0xFDu}, @@ -1976,32 +2080,19 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = { - 0x04u, 0x00u, 0x00u, 0x9Fu, 0x04u, 0xC0u, 0x00u, 0x04u, 0x00u, 0x7Fu, 0x00u, 0x80u, 0x00u, 0x90u, 0x00u, 0x40u, - 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0xC0u, 0x00u, 0x08u, 0x00u, 0x00u, 0x01u, 0x60u, 0x00u, 0xC0u, 0x02u, 0x02u, - 0x00u, 0xC0u, 0x00u, 0x01u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x03u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, - 0x53u, 0x06u, 0x40u, 0x00u, 0x02u, 0xCEu, 0xFDu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 814905c..6c74b5f 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -381,32 +381,32 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 @@ -419,29 +419,29 @@ .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -449,9 +449,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST /* SD_SCK */ .set SD_SCK__0__MASK, 0x04 @@ -1909,24 +1909,24 @@ /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -2366,7 +2366,7 @@ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 .set SD_RX_DMA__NUMBEROF_TDS, 0 -.set SD_RX_DMA__PRIORITY, 2 +.set SD_RX_DMA__PRIORITY, 0 .set SD_RX_DMA__TERMIN_EN, 0 .set SD_RX_DMA__TERMIN_SEL, 0 .set SD_RX_DMA__TERMOUT0_EN, 1 @@ -2388,7 +2388,7 @@ .set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_TX_DMA__DRQ_NUMBER, 3 .set SD_TX_DMA__NUMBEROF_TDS, 0 -.set SD_TX_DMA__PRIORITY, 2 +.set SD_TX_DMA__PRIORITY, 1 .set SD_TX_DMA__TERMIN_EN, 0 .set SD_TX_DMA__TERMIN_SEL, 0 .set SD_TX_DMA__TERMOUT0_EN, 1 @@ -2677,57 +2677,57 @@ .set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW /* scsiTarget */ -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB05_06_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB05_06_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB05_06_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB05_06_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB05_06_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB05_06_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB05_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB05_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB05_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB05_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB05_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB05_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB05_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB05_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB05_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB05_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB05_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB05_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB05_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB05_MSK +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB00_01_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB00_01_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB00_01_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB00_01_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB00_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB00_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB00_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB00_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB00_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB00_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB00_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB00_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB00_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB00_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB00_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB00_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB00_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB00_MSK .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2735,13 +2735,9 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST /* Debug_Timer_Interrupt */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2852,8 +2848,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2861,49 +2857,45 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK -.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 2f12302..ec34581 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -381,32 +381,32 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -419,29 +419,29 @@ SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -449,9 +449,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST /* SD_SCK */ SD_SCK__0__MASK EQU 0x04 @@ -1909,24 +1909,24 @@ SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2366,7 +2366,7 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 SD_RX_DMA__NUMBEROF_TDS EQU 0 -SD_RX_DMA__PRIORITY EQU 2 +SD_RX_DMA__PRIORITY EQU 0 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 @@ -2388,7 +2388,7 @@ SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 SD_TX_DMA__NUMBEROF_TDS EQU 0 -SD_TX_DMA__PRIORITY EQU 2 +SD_TX_DMA__PRIORITY EQU 1 SD_TX_DMA__TERMIN_EN EQU 0 SD_TX_DMA__TERMIN_SEL EQU 0 SD_TX_DMA__TERMOUT0_EN EQU 1 @@ -2677,57 +2677,57 @@ SCSI_Noise__SEL__SHIFT EQU 0 SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW /* scsiTarget */ -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2735,13 +2735,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST /* Debug_Timer_Interrupt */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2852,8 +2848,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2861,49 +2857,45 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index c42672d..be5a1f5 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -381,32 +381,32 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -419,29 +419,29 @@ SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -449,9 +449,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST ; SD_SCK SD_SCK__0__MASK EQU 0x04 @@ -1909,24 +1909,24 @@ SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2366,7 +2366,7 @@ SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 SD_RX_DMA__NUMBEROF_TDS EQU 0 -SD_RX_DMA__PRIORITY EQU 2 +SD_RX_DMA__PRIORITY EQU 0 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 @@ -2388,7 +2388,7 @@ SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_TX_DMA__DRQ_NUMBER EQU 3 SD_TX_DMA__NUMBEROF_TDS EQU 0 -SD_TX_DMA__PRIORITY EQU 2 +SD_TX_DMA__PRIORITY EQU 1 SD_TX_DMA__TERMIN_EN EQU 0 SD_TX_DMA__TERMIN_SEL EQU 0 SD_TX_DMA__TERMOUT0_EN EQU 1 @@ -2677,57 +2677,57 @@ SCSI_Noise__SEL__SHIFT EQU 0 SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW ; scsiTarget -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2735,13 +2735,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST ; Debug_Timer_Interrupt Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2852,8 +2848,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2861,49 +2857,45 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK -SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index acda16c..c07d021 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used)) const uint8 cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x10u, 0x04u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x20u, 0x04u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index cb10da0..f461b84 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -11,7 +11,7 @@ - + @@ -82,9 +82,9 @@ - - - + + + @@ -112,9 +112,9 @@ - - - + + + @@ -144,7 +144,7 @@ - + diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr index ad662c8..c332a41 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cydwr differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit index cf48a6b..afd7982 100644 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj index 43b5b68..2f7d469 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -3355,7 +3355,7 @@ - + diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd index 6c4fda2..0462adf 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd @@ -30,7 +30,7 @@ SCSI_Out_Ctl No description available - 0x4000647D + 0x40006478 0 0x0 @@ -343,7 +343,7 @@ SCSI_Filtered No description available - 0x4000646C + 0x4000646D 0 0x0 @@ -498,7 +498,7 @@ SCSI_Parity_Error No description available - 0x40006466 + 0x40006465 0 0x0 @@ -653,7 +653,7 @@ SCSI_CTL_PHASE No description available - 0x4000647C + 0x40006472 0 0x0 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 6a33d2e..e5f05a0 100755 Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr index 805706b..f77b3fc 100755 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cydwr differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit index 67548f7..7cb75d6 100644 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj index 15c22fe..0f6ea55 100755 --- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2483,7 +2483,7 @@ - + @@ -2497,7 +2497,7 @@ - + diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index a69b553..99cb769 100755 Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/include/scsi2sd.h b/software/include/scsi2sd.h index 504fe79..cec7485 100755 --- a/software/include/scsi2sd.h +++ b/software/include/scsi2sd.h @@ -95,6 +95,12 @@ typedef enum CONFIG_FLOPPY_14MB } CONFIG_TYPE; +typedef enum +{ + CONFIG_QUIRKS_NONE, + CONFIG_QUIRKS_APPLE +} CONFIG_QUIRKS; + typedef struct __attribute__((packed)) { uint8_t deviceType; @@ -112,7 +118,7 @@ typedef struct __attribute__((packed)) uint8_t deviceType; // CONFIG_TYPE uint8_t flags; // CONFIG_FLAGS - uint8_t pad0; + uint8_t deviceTypeModifier; // Used in INQUIRY response. uint32_t sdSectorStart; uint32_t scsiSectors; @@ -131,7 +137,9 @@ typedef struct __attribute__((packed)) char revision[4]; char serial[16]; - uint8_t reserved[962]; // Pad out to 1024 bytes for main section. + uint16_t quirks; // CONFIG_QUIRKS + + uint8_t reserved[960]; // Pad out to 1024 bytes for main section. uint8_t vpd[3072]; // Total size is 4k. } TargetConfig; diff --git a/software/scsi2sd-util/ConfigUtil.cc b/software/scsi2sd-util/ConfigUtil.cc index 9055460..e717cf8 100644 --- a/software/scsi2sd-util/ConfigUtil.cc +++ b/software/scsi2sd-util/ConfigUtil.cc @@ -24,6 +24,7 @@ using namespace SCSI2SD; +ADD QUIRKS MODES namespace { // Endian conversion routines. @@ -93,7 +94,7 @@ ConfigUtil::Default(size_t targetIdx) // Default to maximum fail-safe options. config.flags = 0;// CONFIG_ENABLE_PARITY | CONFIG_ENABLE_UNIT_ATTENTION; - config.pad0 = 0; + config.deviceTypeModifier = 0; config.sdSectorStart = 0; // Default to 2GB. Many systems have trouble with > 2GB disks, and @@ -145,3 +146,60 @@ ConfigUtil::toBytes(const TargetConfig& _config) return std::vector(begin, begin + sizeof(config)); } +wxXmlNode* +ConfigUtil::toXML(const TargetConfig& config) +{ + wxXmlNode* target = new wxXmlNode(wxXML_ELEMENT_NODE, "SCSITarget"); + + { + std::stringstream s; s << scsiId & CONFIG_TARGET_ID_BITS; + target.AddAttribute("id", s.str()); + } + { + std::stringstream s; s << config.deviceType; + new wxXmlNode( + new wxXmlNode(target, wxXML_ELEMENT_NODE, "deviceType"), + wxXML_TEXT_NODE, "", s.str()); + } + + { + std::stringstream s; s << "0x" << std::hex << config.deviceTypeModifier; + new wxXmlNode( + new wxXmlNode(target, wxXML_ELEMENT_NODE, "deviceTypeModifier"), + wxXML_TEXT_NODE, "", s.str()); + } + + wxXmlNode* flags(new wxXmlNode(target, wxXML_ELEMENT_NODE, "flags")); + + new wxXmlNode( + new wxXmlNode(flags, wxXML_ELEMENT_NODE, "enabled"), + wxXML_TEXT_NODE, + "", + config.scsiId & CONFIG_TARGET_ENABLED ? "true" : "false"); + + "" << + (config.flags & CONFIG_ENABLE_UNIT_ATTENTION ? "true" : "false") << + "\n" << + "" << + (config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") << + "\n" << + + "" << config.sdSectorStart << "\n" << + "" << config.scsiSectors << "\n" << + "" << config.bytesPerSector << "\n" << + "" << config.sectorsPerTrack<< "\n" << + "" << config.headsPerCylinder << "\n" << + + "" << std::string(config.vendor, 8) << "" << + "" << std::string(config.prodId, 16) << "" << + "" << std::string(config.revision, 4) << "" << + "" << std::string(config.serial, 16) << "" << + + ""; +} + +void +ConfigUtil::deserialise(const std::string& in) +{ + +} diff --git a/software/scsi2sd-util/SCSI2SD_HID.cc b/software/scsi2sd-util/SCSI2SD_HID.cc index 6944b83..b2aa4d0 100644 --- a/software/scsi2sd-util/SCSI2SD_HID.cc +++ b/software/scsi2sd-util/SCSI2SD_HID.cc @@ -404,7 +404,7 @@ HID::sendHIDPacket( size_t respLen; resp = hidPacket_getPacket(&respLen); - for (int retry = 0; retry < responseLength * 2 && !resp; ++retry) + for (unsigned int retry = 0; retry < responseLength * 2 && !resp; ++retry) { readHID(hidBuf, sizeof(hidBuf)); // Will block hidPacket_recv(hidBuf, HID_PACKET_SIZE); diff --git a/software/scsi2sd-util/scsi2sd-util.cc b/software/scsi2sd-util/scsi2sd-util.cc index a5ec3ee..cc26e8b 100644 --- a/software/scsi2sd-util/scsi2sd-util.cc +++ b/software/scsi2sd-util/scsi2sd-util.cc @@ -849,10 +849,12 @@ private: return; } - void OnExit(wxCommandEvent& event) + // Note: Don't confuse this with the wxApp::OnExit virtual method + void OnExitEvt(wxCommandEvent& event) { Close(true); } + void OnAbout(wxCommandEvent& event) { wxMessageBox( @@ -882,7 +884,7 @@ wxBEGIN_EVENT_TABLE(AppFrame, wxFrame) EVT_MENU(AppFrame::ID_ConfigDefaults, AppFrame::OnID_ConfigDefaults) EVT_MENU(AppFrame::ID_Firmware, AppFrame::OnID_Firmware) EVT_MENU(AppFrame::ID_LogWindow, AppFrame::OnID_LogWindow) - EVT_MENU(wxID_EXIT, AppFrame::OnExit) + EVT_MENU(wxID_EXIT, AppFrame::OnExitEvt) EVT_MENU(wxID_ABOUT, AppFrame::OnAbout) EVT_TIMER(AppFrame::ID_Timer, AppFrame::OnID_Timer)