From: Michael McMaster Date: Mon, 3 Mar 2014 12:08:40 +0000 (+1000) Subject: Adding minimum command timer. X-Git-Tag: 3.3~6 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=9dab0bcac4c99781bd40997a1c2298c273342e9f;p=SCSI2SD.git Adding minimum command timer. --- diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c new file mode 100755 index 0000000..34c3e24 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.c @@ -0,0 +1,754 @@ +/******************************************************************************* +* File Name: SCSI_CMD_TIMER.c +* Version 2.50 +* +* Description: +* The Timer component consists of a 8, 16, 24 or 32-bit timer with +* a selectable period between 2 and 2^Width - 1. The timer may free run +* or be used as a capture timer as well. The capture can be initiated +* by a positive or negative edge signal as well as via software. +* A trigger input can be programmed to enable the timer on rising edge +* falling edge, either edge or continous run. +* Interrupts may be generated due to a terminal count condition +* or a capture event. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "SCSI_CMD_TIMER.h" + +uint8 SCSI_CMD_TIMER_initVar = 0u; + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_Init +******************************************************************************** +* +* Summary: +* Initialize to the schematic state +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_Init(void) +{ + #if(!SCSI_CMD_TIMER_UsingFixedFunction) + /* Interrupt State Backup for Critical Region*/ + uint8 SCSI_CMD_TIMER_interruptState; + #endif /* Interrupt state back up for Fixed Function only */ + + #if (SCSI_CMD_TIMER_UsingFixedFunction) + /* Clear all bits but the enable bit (if it's already set) for Timer operation */ + SCSI_CMD_TIMER_CONTROL &= SCSI_CMD_TIMER_CTRL_ENABLE; + + /* Clear the mode bits for continuous run mode */ + #if (CY_PSOC5A) + SCSI_CMD_TIMER_CONTROL2 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK)); + #endif /* Clear bits in CONTROL2 only in PSOC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK)); + #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */ + + /* Check if One Shot mode is enabled i.e. RunMode !=0*/ + #if (SCSI_CMD_TIMER_RunModeUsed != 0x0u) + /* Set 3rd bit of Control register to enable one shot mode */ + SCSI_CMD_TIMER_CONTROL |= 0x04u; + #endif /* One Shot enabled only when RunModeUsed is not Continuous*/ + + #if (SCSI_CMD_TIMER_RunModeUsed == 2) + #if (CY_PSOC5A) + /* Set last 2 bits of control2 register if one shot(halt on + interrupt) is enabled*/ + SCSI_CMD_TIMER_CONTROL2 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Set last 2 bits of control3 register if one shot(halt on + interrupt) is enabled*/ + SCSI_CMD_TIMER_CONTROL3 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */ + + #endif /* Remove section if One Shot Halt on Interrupt is not enabled */ + + #if (SCSI_CMD_TIMER_UsingHWEnable != 0) + #if (CY_PSOC5A) + /* Set the default Run Mode of the Timer to Continuous */ + SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH; + #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Clear and Set ROD and COD bits of CFG2 register */ + SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_RCOD_MASK)); + SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_RCOD; + + /* Clear and Enable the HW enable bit in CFG2 register */ + SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENBL_MASK)); + SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_ENBL; + + /* Set the default Run Mode of the Timer to Continuous */ + SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS; + #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */ + + #endif /* Configure Run Mode with hardware enable */ + + /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */ + SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_RT1_MASK)); + SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNC; + + /*Enable DSI Sync all all inputs of the Timer*/ + SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_SYNCDSI_MASK)); + SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNCDSI_EN; + + /* Set the IRQ to use the status register interrupts */ + SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL2_IRQ_SEL; + #endif /* Configuring registers of fixed function implementation */ + + /* Set Initial values from Configuration */ + SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_INIT_PERIOD); + SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_INIT_PERIOD); + + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)/* Capture counter is enabled */ + SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL |= SCSI_CMD_TIMER_CNTR_ENABLE; + SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_INIT_CAPTURE_COUNT); + #endif /* Configure capture counter value */ + + #if (!SCSI_CMD_TIMER_UsingFixedFunction) + #if (SCSI_CMD_TIMER_SoftwareCaptureMode) + SCSI_CMD_TIMER_SetCaptureMode(SCSI_CMD_TIMER_INIT_CAPTURE_MODE); + #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */ + + #if (SCSI_CMD_TIMER_SoftwareTriggerMode) + if (0u == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE)) + { + SCSI_CMD_TIMER_SetTriggerMode(SCSI_CMD_TIMER_INIT_TRIGGER_MODE); + } + #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */ + + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection(); + + /* Use the interrupt output of the status register for IRQ output */ + SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK; + + /* Exit Critical Region*/ + CyExitCriticalSection(SCSI_CMD_TIMER_interruptState); + + #if (SCSI_CMD_TIMER_EnableTriggerMode) + SCSI_CMD_TIMER_EnableTrigger(); + #endif /* Set Trigger enable bit for UDB implementation in the control register*/ + + #if (SCSI_CMD_TIMER_InterruptOnCaptureCount) + #if (!SCSI_CMD_TIMER_ControlRegRemoved) + SCSI_CMD_TIMER_SetInterruptCount(SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT); + #endif /* Set interrupt count in control register if control register is not removed */ + #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/ + + SCSI_CMD_TIMER_ClearFIFO(); + #endif /* Configure additional features of UDB implementation */ + + SCSI_CMD_TIMER_SetInterruptMode(SCSI_CMD_TIMER_INIT_INTERRUPT_MODE); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_Enable +******************************************************************************** +* +* Summary: +* Enable the Timer +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_Enable(void) +{ + /* Globally Enable the Fixed Function Block chosen */ + #if (SCSI_CMD_TIMER_UsingFixedFunction) + SCSI_CMD_TIMER_GLOBAL_ENABLE |= SCSI_CMD_TIMER_BLOCK_EN_MASK; + SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE |= SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK; + #endif /* Set Enable bit for enabling Fixed function timer*/ + + /* Remove assignment if control register is removed */ + #if (!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction) + SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_ENABLE; + #endif /* Remove assignment if control register is removed */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_Start +******************************************************************************** +* +* Summary: +* The start function initializes the timer with the default values, the +* enables the timerto begin counting. It does not enable interrupts, +* the EnableInt command should be called if interrupt generation is required. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* SCSI_CMD_TIMER_initVar: Is modified when this function is called for the +* first time. Is used to ensure that initialization happens only once. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_Start(void) +{ + if(SCSI_CMD_TIMER_initVar == 0u) + { + SCSI_CMD_TIMER_Init(); + + SCSI_CMD_TIMER_initVar = 1u; /* Clear this bit for Initialization */ + } + + /* Enable the Timer */ + SCSI_CMD_TIMER_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_Stop +******************************************************************************** +* +* Summary: +* The stop function halts the timer, but does not change any modes or disable +* interrupts. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: If the Enable mode is set to Hardware only then this function +* has no effect on the operation of the timer. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_Stop(void) +{ + /* Disable Timer */ + #if(!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction) + SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENABLE)); + #endif /* Remove assignment if control register is removed */ + + /* Globally disable the Fixed Function Block chosen */ + #if (SCSI_CMD_TIMER_UsingFixedFunction) + SCSI_CMD_TIMER_GLOBAL_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_EN_MASK)); + SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK)); + #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SetInterruptMode +******************************************************************************** +* +* Summary: +* This function selects which of the interrupt inputs may cause an interrupt. +* The twosources are caputure and terminal. One, both or neither may +* be selected. +* +* Parameters: +* interruptMode: This parameter is used to enable interrups on either/or +* terminal count or capture. +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) +{ + SCSI_CMD_TIMER_STATUS_MASK = interruptMode; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SoftwareCapture +******************************************************************************** +* +* Summary: +* This function forces a capture independent of the capture signal. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: +* An existing hardware capture could be overwritten. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SoftwareCapture(void) +{ + /* Generate a software capture by reading the counter register */ + (void)SCSI_CMD_TIMER_COUNTER_LSB; + /* Capture Data is now in the FIFO */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ReadStatusRegister +******************************************************************************** +* +* Summary: +* Reads the status register and returns it's state. This function should use +* defined types for the bit-field information as the bits in this register may +* be permuteable. +* +* Parameters: +* void +* +* Return: +* The contents of the status register +* +* Side Effects: +* Status register bits may be clear on read. +* +*******************************************************************************/ +uint8 SCSI_CMD_TIMER_ReadStatusRegister(void) +{ + return (SCSI_CMD_TIMER_STATUS); +} + + +#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ReadControlRegister +******************************************************************************** +* +* Summary: +* Reads the control register and returns it's value. +* +* Parameters: +* void +* +* Return: +* The contents of the control register +* +*******************************************************************************/ +uint8 SCSI_CMD_TIMER_ReadControlRegister(void) +{ + return ((uint8)SCSI_CMD_TIMER_CONTROL); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_WriteControlRegister +******************************************************************************** +* +* Summary: +* Sets the bit-field of the control register. +* +* Parameters: +* control: The contents of the control register +* +* Return: +* +*******************************************************************************/ +void SCSI_CMD_TIMER_WriteControlRegister(uint8 control) +{ + SCSI_CMD_TIMER_CONTROL = control; +} +#endif /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ReadPeriod +******************************************************************************** +* +* Summary: +* This function returns the current value of the Period. +* +* Parameters: +* void +* +* Return: +* The present value of the counter. +* +*******************************************************************************/ +uint16 SCSI_CMD_TIMER_ReadPeriod(void) +{ + #if(SCSI_CMD_TIMER_UsingFixedFunction) + return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR)); + #else + return (CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR)); + #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_WritePeriod +******************************************************************************** +* +* Summary: +* This function is used to change the period of the counter. The new period +* will be loaded the next time terminal count is detected. +* +* Parameters: +* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will +* result in the counter remaining at zero. +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_WritePeriod(uint16 period) +{ + #if(SCSI_CMD_TIMER_UsingFixedFunction) + uint16 period_temp = (uint16)period; + CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period_temp); + #else + CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period); + #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ReadCapture +******************************************************************************** +* +* Summary: +* This function returns the last value captured. +* +* Parameters: +* void +* +* Return: +* Present Capture value. +* +*******************************************************************************/ +uint16 SCSI_CMD_TIMER_ReadCapture(void) +{ + #if(SCSI_CMD_TIMER_UsingFixedFunction) + return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR)); + #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_WriteCounter +******************************************************************************** +* +* Summary: +* This funtion is used to set the counter to a specific value +* +* Parameters: +* counter: New counter value. +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \ + +{ + #if(SCSI_CMD_TIMER_UsingFixedFunction) + /* This functionality is removed until a FixedFunction HW update to + * allow this register to be written + */ + CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, (uint16)counter); + + #else + CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, counter); + #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ReadCounter +******************************************************************************** +* +* Summary: +* This function returns the current counter value. +* +* Parameters: +* void +* +* Return: +* Present compare value. +* +*******************************************************************************/ +uint16 SCSI_CMD_TIMER_ReadCounter(void) +{ + + /* Force capture by reading Accumulator */ + /* Must first do a software capture to be able to read the counter */ + /* It is up to the user code to make sure there isn't already captured data in the FIFO */ + (void)SCSI_CMD_TIMER_COUNTER_LSB; + + /* Read the data from the FIFO (or capture register for Fixed Function)*/ + #if(SCSI_CMD_TIMER_UsingFixedFunction) + return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR)); + #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */ +} + + +#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Specific Functions */ + +/******************************************************************************* + * The functions below this point are only available using the UDB + * implementation. If a feature is selected, then the API is enabled. + ******************************************************************************/ + + +#if (SCSI_CMD_TIMER_SoftwareCaptureMode) + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SetCaptureMode +******************************************************************************** +* +* Summary: +* This function sets the capture mode to either rising or falling edge. +* +* Parameters: +* captureMode: This parameter sets the capture mode of the UDB capture feature +* The parameter values are defined using the +* #define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0 +#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1 +#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2 +#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3 +#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4 + identifiers +* The following are the possible values of the parameter +* SCSI_CMD_TIMER__B_TIMER__CM_NONE - Set Capture mode to None +* SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input +* SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input +* SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE - Either edge of Capture input +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) +{ + /* This must only set to two bits of the control register associated */ + captureMode = ((uint8)((uint8)captureMode << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT)); + captureMode &= (SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK); + + /* Clear the Current Setting */ + SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK)); + + /* Write The New Setting */ + SCSI_CMD_TIMER_CONTROL |= captureMode; +} +#endif /* Remove API if Capture Mode is not Software Controlled */ + + +#if (SCSI_CMD_TIMER_SoftwareTriggerMode) + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SetTriggerMode +******************************************************************************** +* +* Summary: +* This function sets the trigger input mode +* +* Parameters: +* triggerMode: Pass one of the pre-defined Trigger Modes (except Software) + #define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u + #define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u + #define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u + #define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu + #define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) +{ + /* This must only set to two bits of the control register associated */ + triggerMode &= SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK; + + /* Clear the Current Setting */ + SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK)); + + /* Write The New Setting */ + SCSI_CMD_TIMER_CONTROL |= (triggerMode | SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE); + +} +#endif /* Remove API if Trigger Mode is not Software Controlled */ + +#if (SCSI_CMD_TIMER_EnableTriggerMode) + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_EnableTrigger +******************************************************************************** +* +* Summary: +* Sets the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_EnableTrigger(void) +{ + #if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */ + SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_TRIG_EN; + #endif /* Remove code section if control register is not used */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_DisableTrigger +******************************************************************************** +* +* Summary: +* Clears the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_DisableTrigger(void) +{ + #if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */ + SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_EN)); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API is Trigger Mode is set to None */ + + +#if(SCSI_CMD_TIMER_InterruptOnCaptureCount) +#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */ + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SetInterruptCount +******************************************************************************** +* +* Summary: +* This function sets the capture count before an interrupt is triggered. +* +* Parameters: +* interruptCount: A value between 0 and 3 is valid. If the value is 0, then +* an interrupt will occur each time a capture occurs. +* A value of 1 to 3 will cause the interrupt +* to delay by the same number of captures. +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) +{ + /* This must only set to two bits of the control register associated */ + interruptCount &= SCSI_CMD_TIMER_CTRL_INTCNT_MASK; + + /* Clear the Current Setting */ + SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_INTCNT_MASK)); + /* Write The New Setting */ + SCSI_CMD_TIMER_CONTROL |= interruptCount; +} +#endif /* Remove API if control register is removed */ +#endif /* SCSI_CMD_TIMER_InterruptOnCaptureCount */ + + +#if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SetCaptureCount +******************************************************************************** +* +* Summary: +* This function sets the capture count +* +* Parameters: +* captureCount: A value between 2 and 127 inclusive is valid. A value of 1 +* to 127 will cause the interrupt to delay by the same number of +* captures. +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) +{ + SCSI_CMD_TIMER_CAP_COUNT = captureCount; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ReadCaptureCount +******************************************************************************** +* +* Summary: +* This function reads the capture count setting +* +* Parameters: +* void +* +* Return: +* Returns the Capture Count Setting +* +*******************************************************************************/ +uint8 SCSI_CMD_TIMER_ReadCaptureCount(void) +{ + return ((uint8)SCSI_CMD_TIMER_CAP_COUNT); +} +#endif /* SCSI_CMD_TIMER_UsingHWCaptureCounter */ + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ClearFIFO +******************************************************************************** +* +* Summary: +* This function clears all capture data from the capture FIFO +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ClearFIFO(void) +{ + while(0u != (SCSI_CMD_TIMER_ReadStatusRegister() & SCSI_CMD_TIMER_STATUS_FIFONEMP)) + { + (void)SCSI_CMD_TIMER_ReadCapture(); + } +} + +#endif /* UDB Specific Functions */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h new file mode 100755 index 0000000..fc4e09b --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER.h @@ -0,0 +1,439 @@ +/******************************************************************************* +* File Name: SCSI_CMD_TIMER.h +* Version 2.50 +* +* Description: +* Contains the function prototypes and constants available to the timer +* user module. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CY_Timer_v2_30_SCSI_CMD_TIMER_H) +#define CY_Timer_v2_30_SCSI_CMD_TIMER_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + +extern uint8 SCSI_CMD_TIMER_initVar; + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Timer_v2_50 requires cy_boot v3.0 or later +#endif /* (CY_ PSOC5LP) */ + + +/************************************** +* Parameter Defaults +**************************************/ + +#define SCSI_CMD_TIMER_Resolution 16u +#define SCSI_CMD_TIMER_UsingFixedFunction 1u +#define SCSI_CMD_TIMER_UsingHWCaptureCounter 0u +#define SCSI_CMD_TIMER_SoftwareCaptureMode 0u +#define SCSI_CMD_TIMER_SoftwareTriggerMode 0u +#define SCSI_CMD_TIMER_UsingHWEnable 0u +#define SCSI_CMD_TIMER_EnableTriggerMode 0u +#define SCSI_CMD_TIMER_InterruptOnCaptureCount 0u +#define SCSI_CMD_TIMER_RunModeUsed 1u +#define SCSI_CMD_TIMER_ControlRegRemoved 0u + + +/*************************************** +* Type defines +***************************************/ + + +/************************************************************************** + * Sleep Wakeup Backup structure for Timer Component + *************************************************************************/ +typedef struct +{ + uint8 TimerEnableState; + #if(!SCSI_CMD_TIMER_UsingFixedFunction) + #if (CY_UDB_V0) + uint16 TimerUdb; /* Timer internal counter value */ + uint16 TimerPeriod; /* Timer Period value */ + uint8 InterruptMaskValue; /* Timer Compare Value */ + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; /* Timer Capture Counter Value */ + #endif /* variable declaration for backing up Capture Counter value*/ + #endif /* variables for non retention registers in CY_UDB_V0 */ + + #if (CY_UDB_V1) + uint16 TimerUdb; + uint8 InterruptMaskValue; + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; + #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */ + #endif /* (CY_UDB_V1) */ + + #if (!SCSI_CMD_TIMER_ControlRegRemoved) + uint8 TimerControlRegister; + #endif /* variable declaration for backing up enable state of the Timer */ + #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */ +}SCSI_CMD_TIMER_backupStruct; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_CMD_TIMER_Start(void) ; +void SCSI_CMD_TIMER_Stop(void) ; + +void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) ; +uint8 SCSI_CMD_TIMER_ReadStatusRegister(void) ; +/* Deprecated function. Do not use this in future. Retained for backward compatibility */ +#define SCSI_CMD_TIMER_GetInterruptSource() SCSI_CMD_TIMER_ReadStatusRegister() + +#if(!SCSI_CMD_TIMER_ControlRegRemoved) + uint8 SCSI_CMD_TIMER_ReadControlRegister(void) ; + void SCSI_CMD_TIMER_WriteControlRegister(uint8 control) \ + ; +#endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */ + +uint16 SCSI_CMD_TIMER_ReadPeriod(void) ; +void SCSI_CMD_TIMER_WritePeriod(uint16 period) \ + ; +uint16 SCSI_CMD_TIMER_ReadCounter(void) ; +void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \ + ; +uint16 SCSI_CMD_TIMER_ReadCapture(void) ; +void SCSI_CMD_TIMER_SoftwareCapture(void) ; + + +#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Prototypes */ + #if (SCSI_CMD_TIMER_SoftwareCaptureMode) + void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) ; + #endif /* (!SCSI_CMD_TIMER_UsingFixedFunction) */ + + #if (SCSI_CMD_TIMER_SoftwareTriggerMode) + void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) ; + #endif /* (SCSI_CMD_TIMER_SoftwareTriggerMode) */ + #if (SCSI_CMD_TIMER_EnableTriggerMode) + void SCSI_CMD_TIMER_EnableTrigger(void) ; + void SCSI_CMD_TIMER_DisableTrigger(void) ; + #endif /* (SCSI_CMD_TIMER_EnableTriggerMode) */ + + #if(SCSI_CMD_TIMER_InterruptOnCaptureCount) + #if(!SCSI_CMD_TIMER_ControlRegRemoved) + void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) \ + ; + #endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */ + #endif /* (SCSI_CMD_TIMER_InterruptOnCaptureCount) */ + + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) \ + ; + uint8 SCSI_CMD_TIMER_ReadCaptureCount(void) ; + #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */ + + void SCSI_CMD_TIMER_ClearFIFO(void) ; +#endif /* UDB Prototypes */ + +/* Sleep Retention APIs */ +void SCSI_CMD_TIMER_Init(void) ; +void SCSI_CMD_TIMER_Enable(void) ; +void SCSI_CMD_TIMER_SaveConfig(void) ; +void SCSI_CMD_TIMER_RestoreConfig(void) ; +void SCSI_CMD_TIMER_Sleep(void) ; +void SCSI_CMD_TIMER_Wakeup(void) ; + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */ +#define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0 +#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1 +#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2 +#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3 +#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4 + + + +/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */ +#define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u +#define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u +#define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u +#define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu +#define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u + + +/*************************************** +* Initialial Parameter Constants +***************************************/ + +#define SCSI_CMD_TIMER_INIT_PERIOD 1199u +#define SCSI_CMD_TIMER_INIT_CAPTURE_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT)) +#define SCSI_CMD_TIMER_INIT_TRIGGER_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT)) +#if (SCSI_CMD_TIMER_UsingFixedFunction) + #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT))) +#else + #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT))) +#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */ +#define SCSI_CMD_TIMER_INIT_CAPTURE_COUNT (2u) +#define SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT)) + + +/*************************************** +* Registers +***************************************/ + +#if (SCSI_CMD_TIMER_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */ + + + /*************************************** + * Fixed Function Registers + ***************************************/ + + #define SCSI_CMD_TIMER_STATUS (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 ) + /* In Fixed Function Block Status and Mask are the same register */ + #define SCSI_CMD_TIMER_STATUS_MASK (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 ) + #define SCSI_CMD_TIMER_CONTROL (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG0) + #define SCSI_CMD_TIMER_CONTROL2 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1) + #define SCSI_CMD_TIMER_CONTROL2_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1) + #define SCSI_CMD_TIMER_RT1 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__RT1) + #define SCSI_CMD_TIMER_RT1_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__RT1) + + #if (CY_PSOC3 || CY_PSOC5LP) + #define SCSI_CMD_TIMER_CONTROL3 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2) + #define SCSI_CMD_TIMER_CONTROL3_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #define SCSI_CMD_TIMER_GLOBAL_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG) + #define SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG) + + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 ) + + + /*************************************** + * Register Constants + ***************************************/ + + /* Fixed Function Block Chosen */ + #define SCSI_CMD_TIMER_BLOCK_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK + #define SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK + + /* Control Register Bit Locations */ + /* Interrupt Count - Not valid for Fixed Function Block */ + #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u + /* Trigger Polarity - Not valid for Fixed Function Block */ + #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x00u + /* Trigger Enable - Not valid for Fixed Function Block */ + #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x00u + /* Capture Polarity - Not valid for Fixed Function Block */ + #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x00u + /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */ + #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x00u + + /* Control Register Bit Masks */ + #define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT)) + + /* Control2 Register Bit Masks */ + /* As defined in Register Map, Part of the TMRX_CFG1 register */ + #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT 0x00u + #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT)) + + #if (CY_PSOC5A) + /* Use CFG1 Mode bits to set run mode */ + /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x01u + #define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x07u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) + #endif /* (CY_PSOC5A) */ + #if (CY_PSOC3 || CY_PSOC5LP) + /* Control3 Register Bit Locations */ + #define SCSI_CMD_TIMER_CTRL_RCOD_SHIFT 0x02u + #define SCSI_CMD_TIMER_CTRL_ENBL_SHIFT 0x00u + #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x00u + + /* Control3 Register Bit Masks */ + #define SCSI_CMD_TIMER_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */ + #define SCSI_CMD_TIMER_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */ + #define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) /* Run mode bit mask */ + + #define SCSI_CMD_TIMER_CTRL_RCOD ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_ENBL ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */ + #define SCSI_CMD_TIMER_RT1_SHIFT 0x04u + /* Sync TC and CMP bit masks */ + #define SCSI_CMD_TIMER_RT1_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT)) + #define SCSI_CMD_TIMER_SYNC ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT)) + #define SCSI_CMD_TIMER_SYNCDSI_SHIFT 0x00u + /* Sync all DSI inputs with Mask */ + #define SCSI_CMD_TIMER_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT)) + /* Sync all DSI inputs */ + #define SCSI_CMD_TIMER_SYNCDSI_EN ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT)) + + #define SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) + + /* Status Register Bit Locations */ + /* As defined in Register Map, part of TMRX_SR0 register */ + #define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x07u + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x06u + /* As defined in Register Map, part of TMRX_SR0 register */ + #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_TC_SHIFT - 0x04u) + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT - 0x04u) + + /* Status Register Bit Masks */ + #define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT)) + #define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on TC */ + #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on Capture */ + #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) + +#else /* UDB Registers and Register Constants */ + + + /*************************************** + * UDB Registers + ***************************************/ + + #define SCSI_CMD_TIMER_STATUS (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_REG ) + #define SCSI_CMD_TIMER_STATUS_MASK (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__MASK_REG) + #define SCSI_CMD_TIMER_STATUS_AUX_CTRL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG) + #define SCSI_CMD_TIMER_CONTROL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG ) + + #if(SCSI_CMD_TIMER_Resolution <= 8u) /* 8-bit Timer */ + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #elif(SCSI_CMD_TIMER_Resolution <= 16u) /* 8-bit Timer */ + #if(CY_PSOC3) /* 8-bit addres space */ + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 16-bit address space */ + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #endif /* CY_PSOC3 */ + #elif(SCSI_CMD_TIMER_Resolution <= 24u)/* 24-bit Timer */ + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit Timer */ + #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */ + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit address space */ + #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #endif /* CY_PSOC3 || CY_PSOC5 */ + #endif + + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + #define SCSI_CMD_TIMER_CAP_COUNT (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define SCSI_CMD_TIMER_CAP_COUNT_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */ + + + /*************************************** + * Register Constants + ***************************************/ + + /* Control Register Bit Locations */ + #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */ + + /* Control Register Bit Masks */ + #define SCSI_CMD_TIMER_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_TRIG_EN ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT)) + #define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT)) + + /* Bit Counter (7-bit) Control Register Bit Definitions */ + /* As defined by the Register map for the AUX Control Register */ + #define SCSI_CMD_TIMER_CNTR_ENABLE 0x20u + + /* Status Register Bit Locations */ + #define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_TC_SHIFT + #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT + #define SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */ + #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT + + /* Status Register Bit Masks */ + /* Sticky TC Event Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT)) + /* Sticky Capture Event Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT)) + /* NOT-Sticky FIFO Full Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_FIFOFULL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT)) + /* NOT-Sticky FIFO Not Empty Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_FIFONEMP ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT)) + + #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */ + + /* Datapath Auxillary Control Register definitions */ + #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */ + #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */ + #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */ + #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */ + #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */ + +#endif /* Implementation Specific Registers and Register Constants */ + +#endif /* CY_Timer_v2_30_SCSI_CMD_TIMER_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c new file mode 100755 index 0000000..1093726 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.c @@ -0,0 +1,356 @@ +/******************************************************************************* +* File Name: SCSI_CMD_TIMER_ISR.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + +#if !defined(SCSI_CMD_TIMER_ISR__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_CMD_TIMER_ISR_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_CMD_TIMER_ISR_Disable(); + + /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */ + SCSI_CMD_TIMER_ISR_SetVector(&SCSI_CMD_TIMER_ISR_Interrupt); + + /* Set the priority. */ + SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_CMD_TIMER_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_StartEx +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_CMD_TIMER_ISR_Disable(); + + /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */ + SCSI_CMD_TIMER_ISR_SetVector(address); + + /* Set the priority. */ + SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_CMD_TIMER_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_CMD_TIMER_ISR_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_CMD_TIMER_ISR_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_CMD_TIMER_ISR. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_CMD_TIMER_ISR_Interrupt) +{ + /* Place your Interrupt code here. */ + /* `#START SCSI_CMD_TIMER_ISR_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_CMD_TIMER_ISR_StartEx instead. +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start +* or SCSI_CMD_TIMER_ISR_StartEx will override any effect this method +* would have had. This method should only be called after +* SCSI_CMD_TIMER_ISR_Start or SCSI_CMD_TIMER_ISR_StartEx has been called. To set +* the initial priority for the component use the cydwr file in the tool. +* +* Parameters: +* priority: Priority of the interrupt. 0 - 7, 0 being the highest. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority) +{ + *SCSI_CMD_TIMER_ISR_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt. 0 - 7, 0 being the highest. +* +*******************************************************************************/ +uint8 SCSI_CMD_TIMER_ISR_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_CMD_TIMER_ISR_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_CMD_TIMER_ISR_INTC_SET_EN = SCSI_CMD_TIMER_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_CMD_TIMER_ISR_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_CMD_TIMER_ISR_INTC_SET_EN & (uint32)SCSI_CMD_TIMER_ISR__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_CMD_TIMER_ISR_INTC_CLR_EN = SCSI_CMD_TIMER_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_SetPending(void) +{ + *SCSI_CMD_TIMER_ISR_INTC_SET_PD = SCSI_CMD_TIMER_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_ISR_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CMD_TIMER_ISR_ClearPending(void) +{ + *SCSI_CMD_TIMER_ISR_INTC_CLR_PD = SCSI_CMD_TIMER_ISR__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h new file mode 100755 index 0000000..0454ab4 --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_ISR.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_CMD_TIMER_ISR.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_CMD_TIMER_ISR_H) +#define CY_ISR_SCSI_CMD_TIMER_ISR_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_CMD_TIMER_ISR_Start(void); +void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address); +void SCSI_CMD_TIMER_ISR_Stop(void); + +CY_ISR_PROTO(SCSI_CMD_TIMER_ISR_Interrupt); + +void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address); +cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void); + +void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority); +uint8 SCSI_CMD_TIMER_ISR_GetPriority(void); + +void SCSI_CMD_TIMER_ISR_Enable(void); +uint8 SCSI_CMD_TIMER_ISR_GetState(void); +void SCSI_CMD_TIMER_ISR_Disable(void); + +void SCSI_CMD_TIMER_ISR_SetPending(void); +void SCSI_CMD_TIMER_ISR_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_CMD_TIMER_ISR ISR. */ +#define SCSI_CMD_TIMER_ISR_INTC_VECTOR ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_VECT) + +/* Address of the SCSI_CMD_TIMER_ISR ISR priority. */ +#define SCSI_CMD_TIMER_ISR_INTC_PRIOR ((reg8 *) SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG) + +/* Priority of the SCSI_CMD_TIMER_ISR interrupt. */ +#define SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_CMD_TIMER_ISR interrupt. */ +#define SCSI_CMD_TIMER_ISR_INTC_SET_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_CMD_TIMER_ISR interrupt. */ +#define SCSI_CMD_TIMER_ISR_INTC_CLR_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_CMD_TIMER_ISR interrupt state to pending. */ +#define SCSI_CMD_TIMER_ISR_INTC_SET_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_CMD_TIMER_ISR interrupt. */ +#define SCSI_CMD_TIMER_ISR_INTC_CLR_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_CMD_TIMER_ISR_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c new file mode 100755 index 0000000..f9556fa --- /dev/null +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CMD_TIMER_PM.c @@ -0,0 +1,194 @@ +/******************************************************************************* +* File Name: SCSI_CMD_TIMER_PM.c +* Version 2.50 +* +* Description: +* This file provides the power management source code to API for the +* Timer. +* +* Note: +* None +* +******************************************************************************* +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "SCSI_CMD_TIMER.h" +static SCSI_CMD_TIMER_backupStruct SCSI_CMD_TIMER_backup; + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_SaveConfig +******************************************************************************** +* +* Summary: +* Save the current user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* SCSI_CMD_TIMER_backup: Variables of this global structure are modified to +* store the values of non retention configuration registers when Sleep() API is +* called. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_SaveConfig(void) +{ + #if (!SCSI_CMD_TIMER_UsingFixedFunction) + /* Backup the UDB non-rentention registers for CY_UDB_V0 */ + #if (CY_UDB_V0) + SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter(); + SCSI_CMD_TIMER_backup.TimerPeriod = SCSI_CMD_TIMER_ReadPeriod(); + SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK; + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount(); + #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */ + #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */ + + #if (CY_UDB_V1) + SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter(); + SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK; + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount(); + #endif /* Back Up capture counter register */ + #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */ + + #if(!SCSI_CMD_TIMER_ControlRegRemoved) + SCSI_CMD_TIMER_backup.TimerControlRegister = SCSI_CMD_TIMER_ReadControlRegister(); + #endif /* Backup the enable state of the Timer component */ + #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* SCSI_CMD_TIMER_backup: Variables of this global structure are used to +* restore the values of non retention registers on wakeup from sleep mode. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_RestoreConfig(void) +{ + #if (!SCSI_CMD_TIMER_UsingFixedFunction) + /* Restore the UDB non-rentention registers for CY_UDB_V0 */ + #if (CY_UDB_V0) + /* Interrupt State Backup for Critical Region*/ + uint8 SCSI_CMD_TIMER_interruptState; + + SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb); + SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_backup.TimerPeriod); + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection(); + /* Use the interrupt output of the status register for IRQ output */ + SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK; + /* Exit Critical Region*/ + CyExitCriticalSection(SCSI_CMD_TIMER_interruptState); + SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue; + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter); + #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */ + #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */ + + #if (CY_UDB_V1) + SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb); + SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue; + #if (SCSI_CMD_TIMER_UsingHWCaptureCounter) + SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter); + #endif /* Restore Capture counter register*/ + #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */ + + #if(!SCSI_CMD_TIMER_ControlRegRemoved) + SCSI_CMD_TIMER_WriteControlRegister(SCSI_CMD_TIMER_backup.TimerControlRegister); + #endif /* Restore the enable state of the Timer component */ + #endif /* Restore non retention registers in the UDB implementation only */ +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_Sleep +******************************************************************************** +* +* Summary: +* Stop and Save the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* SCSI_CMD_TIMER_backup.TimerEnableState: Is modified depending on the +* enable state of the block before entering sleep mode. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_Sleep(void) +{ + #if(!SCSI_CMD_TIMER_ControlRegRemoved) + /* Save Counter's enable state */ + if(SCSI_CMD_TIMER_CTRL_ENABLE == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER_CTRL_ENABLE)) + { + /* Timer is enabled */ + SCSI_CMD_TIMER_backup.TimerEnableState = 1u; + } + else + { + /* Timer is disabled */ + SCSI_CMD_TIMER_backup.TimerEnableState = 0u; + } + #endif /* Back up enable state from the Timer control register */ + SCSI_CMD_TIMER_Stop(); + SCSI_CMD_TIMER_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_CMD_TIMER_Wakeup +******************************************************************************** +* +* Summary: +* Restores and enables the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* SCSI_CMD_TIMER_backup.enableState: Is used to restore the enable state of +* block on wakeup from sleep mode. +* +*******************************************************************************/ +void SCSI_CMD_TIMER_Wakeup(void) +{ + SCSI_CMD_TIMER_RestoreConfig(); + #if(!SCSI_CMD_TIMER_ControlRegRemoved) + if(SCSI_CMD_TIMER_backup.TimerEnableState == 1u) + { /* Enable Timer's operation */ + SCSI_CMD_TIMER_Enable(); + } /* Do nothing if Timer was disabled before */ + #endif /* Remove this code section if Control register is removed */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 7d179bd..9a5677e 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -3,6 +3,34 @@ #include #include +/* SCSI_CMD_TIMER_TimerHW */ +#define SCSI_CMD_TIMER_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define SCSI_CMD_TIMER_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define SCSI_CMD_TIMER_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define SCSI_CMD_TIMER_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define SCSI_CMD_TIMER_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define SCSI_CMD_TIMER_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define SCSI_CMD_TIMER_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define SCSI_CMD_TIMER_TimerHW__PER0 CYREG_TMR0_PER0 +#define SCSI_CMD_TIMER_TimerHW__PER1 CYREG_TMR0_PER1 +#define SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK 0x01u +#define SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK 0x01u +#define SCSI_CMD_TIMER_TimerHW__RT0 CYREG_TMR0_RT0 +#define SCSI_CMD_TIMER_TimerHW__RT1 CYREG_TMR0_RT1 +#define SCSI_CMD_TIMER_TimerHW__SR0 CYREG_TMR0_SR0 + +/* SCSI_CMD_TIMER_ISR */ +#define SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_CMD_TIMER_ISR__INTC_MASK 0x01u +#define SCSI_CMD_TIMER_ISR__INTC_NUMBER 0u +#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM 7u +#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + /* USBFS_bus_reset */ #define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 @@ -504,8 +532,8 @@ #define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL #define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK #define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -513,13 +541,13 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -529,9 +557,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0 @@ -565,24 +593,24 @@ /* SCSI_CTL_IO */ #define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL #define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u -#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL /* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT12_AG @@ -1041,8 +1069,8 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1050,76 +1078,80 @@ #define scsiTarget_StatusReg__3__MASK 0x08u #define scsiTarget_StatusReg__3__POS 3 #define scsiTarget_StatusReg__MASK 0x0Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1134,20 +1166,20 @@ /* USBFS_ep_1 */ #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x01u -#define USBFS_ep_1__INTC_NUMBER 0u +#define USBFS_ep_1__INTC_MASK 0x02u +#define USBFS_ep_1__INTC_NUMBER 1u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x02u -#define USBFS_ep_2__INTC_NUMBER 1u +#define USBFS_ep_2__INTC_MASK 0x04u +#define USBFS_ep_2__INTC_NUMBER 2u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2722,7 +2754,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x1000 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x00000000u +#define CYDEV_INTR_RISING 0x00000001u #define CYDEV_PROJ_TYPE 2 #define CYDEV_PROJ_TYPE_BOOTLOADER 1 #define CYDEV_PROJ_TYPE_LOADABLE 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index d3600d7..13e06dc 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 33u +#define CY_CFG_BASE_ADDR_COUNT 35u CYPACKED typedef struct { uint8 offset; @@ -363,36 +363,38 @@ void cyfitter_cfg(void) { static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004502u, /* Base address: 0x40004500 Count: 2 */ + 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40010101u, /* Base address: 0x40010100 Count: 1 */ - 0x40010308u, /* Base address: 0x40010300 Count: 8 */ - 0x40010442u, /* Base address: 0x40010400 Count: 66 */ - 0x4001053Cu, /* Base address: 0x40010500 Count: 60 */ - 0x40010604u, /* Base address: 0x40010600 Count: 4 */ - 0x40010747u, /* Base address: 0x40010700 Count: 71 */ - 0x40010908u, /* Base address: 0x40010900 Count: 8 */ - 0x40010A44u, /* Base address: 0x40010A00 Count: 68 */ - 0x40010B40u, /* Base address: 0x40010B00 Count: 64 */ - 0x40010C35u, /* Base address: 0x40010C00 Count: 53 */ - 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */ - 0x40010E43u, /* Base address: 0x40010E00 Count: 67 */ - 0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */ + 0x40010046u, /* Base address: 0x40010000 Count: 70 */ + 0x40010136u, /* Base address: 0x40010100 Count: 54 */ + 0x4001023Eu, /* Base address: 0x40010200 Count: 62 */ + 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */ + 0x40010447u, /* Base address: 0x40010400 Count: 71 */ + 0x40010546u, /* Base address: 0x40010500 Count: 70 */ + 0x4001060Bu, /* Base address: 0x40010600 Count: 11 */ + 0x4001074Au, /* Base address: 0x40010700 Count: 74 */ + 0x40010906u, /* Base address: 0x40010900 Count: 6 */ + 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */ + 0x40010B10u, /* Base address: 0x40010B00 Count: 16 */ + 0x40010C36u, /* Base address: 0x40010C00 Count: 54 */ + 0x40010D36u, /* Base address: 0x40010D00 Count: 54 */ + 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */ 0x40011504u, /* Base address: 0x40011500 Count: 4 */ - 0x40011648u, /* Base address: 0x40011600 Count: 72 */ - 0x40011740u, /* Base address: 0x40011700 Count: 64 */ - 0x40011904u, /* Base address: 0x40011900 Count: 4 */ - 0x4001400Bu, /* Base address: 0x40014000 Count: 11 */ - 0x4001410Fu, /* Base address: 0x40014100 Count: 15 */ - 0x40014207u, /* Base address: 0x40014200 Count: 7 */ - 0x40014303u, /* Base address: 0x40014300 Count: 3 */ - 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */ - 0x40014516u, /* Base address: 0x40014500 Count: 22 */ - 0x40014608u, /* Base address: 0x40014600 Count: 8 */ - 0x40014708u, /* Base address: 0x40014700 Count: 8 */ - 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ - 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ - 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ + 0x4001164Bu, /* Base address: 0x40011600 Count: 75 */ + 0x40011749u, /* Base address: 0x40011700 Count: 73 */ + 0x40011902u, /* Base address: 0x40011900 Count: 2 */ + 0x4001400Du, /* Base address: 0x40014000 Count: 13 */ + 0x4001410Eu, /* Base address: 0x40014100 Count: 14 */ + 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */ + 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ + 0x40014410u, /* Base address: 0x40014400 Count: 16 */ + 0x40014515u, /* Base address: 0x40014500 Count: 21 */ + 0x40014603u, /* Base address: 0x40014600 Count: 3 */ + 0x40014703u, /* Base address: 0x40014700 Count: 3 */ + 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */ + 0x4001490Au, /* Base address: 0x40014900 Count: 10 */ + 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015101u, /* Base address: 0x40015100 Count: 1 */ }; @@ -400,403 +402,188 @@ void cyfitter_cfg(void) static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x36u, 0x02u}, {0x7Eu, 0x02u}, - {0x00u, 0x01u}, + {0x01u, 0x80u}, + {0x0Au, 0x4Bu}, + {0x00u, 0x02u}, {0x01u, 0x03u}, - {0x18u, 0x04u}, + {0x18u, 0x08u}, {0x19u, 0x0Cu}, {0x1Cu, 0x61u}, - {0x20u, 0x98u}, - {0x21u, 0x38u}, - {0x30u, 0x03u}, - {0x31u, 0x05u}, + {0x20u, 0xC0u}, + {0x21u, 0x90u}, + {0x30u, 0x0Au}, + {0x31u, 0x09u}, {0x7Cu, 0x40u}, - {0x3Du, 0x03u}, + {0x33u, 0x03u}, {0x86u, 0x0Fu}, - {0xE2u, 0x80u}, - {0x81u, 0x40u}, - {0x85u, 0x04u}, - {0xA0u, 0x04u}, - {0xACu, 0x04u}, - {0xE2u, 0x08u}, - {0xE6u, 0x25u}, - {0xEAu, 0x01u}, - {0xEEu, 0x02u}, - {0x07u, 0x04u}, - {0x0Bu, 0x04u}, - {0x0Du, 0x04u}, - {0x0Fu, 0x02u}, + {0x03u, 0x04u}, + {0x06u, 0x10u}, + {0x07u, 0x44u}, + {0x0Bu, 0x40u}, + {0x0Du, 0x44u}, + {0x0Eu, 0x0Cu}, + {0x0Fu, 0x22u}, + {0x12u, 0x01u}, {0x13u, 0x03u}, - {0x19u, 0x04u}, - {0x1Bu, 0x01u}, + {0x16u, 0x10u}, + {0x18u, 0x10u}, + {0x1Au, 0x04u}, + {0x1Cu, 0x01u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x30u}, + {0x21u, 0x08u}, + {0x22u, 0x02u}, + {0x24u, 0x20u}, + {0x29u, 0x44u}, + {0x2Bu, 0x11u}, + {0x2Cu, 0x10u}, + {0x2Eu, 0x08u}, + {0x30u, 0x1Cu}, {0x31u, 0x07u}, - {0x56u, 0x08u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x90u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x80u, 0xD6u}, - {0x81u, 0x2Cu}, - {0x84u, 0x17u}, - {0x86u, 0x28u}, - {0x88u, 0xD2u}, - {0x89u, 0x31u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x42u}, - {0x8Cu, 0xD6u}, - {0x8Du, 0x2Cu}, - {0x91u, 0xC0u}, - {0x94u, 0x29u}, - {0x96u, 0x46u}, - {0x97u, 0x2Cu}, - {0x98u, 0x20u}, - {0x99u, 0x40u}, - {0x9Au, 0xD0u}, - {0x9Bu, 0x2Fu}, - {0x9Cu, 0x04u}, - {0x9Du, 0x24u}, - {0xA0u, 0xD6u}, - {0xA1u, 0x08u}, - {0xA3u, 0x10u}, - {0xA4u, 0xD0u}, - {0xA5u, 0x24u}, - {0xA6u, 0x06u}, - {0xA7u, 0x08u}, - {0xA8u, 0x21u}, - {0xA9u, 0x11u}, - {0xAAu, 0x8Eu}, - {0xABu, 0x8Eu}, - {0xACu, 0x02u}, - {0xADu, 0x2Cu}, - {0xB0u, 0x01u}, - {0xB1u, 0xC1u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x31u}, - {0xB4u, 0xF0u}, - {0xB5u, 0x0Fu}, - {0xB6u, 0x08u}, - {0xB8u, 0x08u}, - {0xB9u, 0x02u}, - {0xBAu, 0x20u}, - {0xBBu, 0x0Cu}, - {0xBEu, 0x41u}, - {0xD4u, 0x09u}, - {0xD8u, 0x0Bu}, - {0xD9u, 0x0Bu}, - {0xDBu, 0x0Bu}, - {0xDCu, 0x99u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x04u, 0x29u}, - {0x06u, 0x02u}, - {0x0Eu, 0x28u}, - {0x0Fu, 0x02u}, - {0x17u, 0x65u}, - {0x1Cu, 0x10u}, - {0x1Du, 0x48u}, - {0x1Eu, 0x28u}, - {0x1Fu, 0x09u}, - {0x21u, 0x02u}, - {0x23u, 0x40u}, - {0x24u, 0x08u}, - {0x25u, 0x10u}, - {0x26u, 0x02u}, - {0x27u, 0x38u}, - {0x29u, 0xC0u}, - {0x2Du, 0x02u}, - {0x2Fu, 0x2Au}, - {0x31u, 0x02u}, - {0x32u, 0x10u}, - {0x34u, 0x01u}, - {0x36u, 0x02u}, - {0x37u, 0x54u}, - {0x39u, 0x48u}, - {0x3Au, 0x10u}, - {0x3Cu, 0x81u}, - {0x3Du, 0x20u}, - {0x3Eu, 0x01u}, - {0x58u, 0x80u}, - {0x5Du, 0x98u}, - {0x5Eu, 0x02u}, - {0x60u, 0x02u}, - {0x62u, 0x80u}, - {0x65u, 0x08u}, - {0x66u, 0x04u}, - {0x67u, 0x02u}, - {0x7Eu, 0x80u}, - {0x89u, 0x02u}, - {0x8Cu, 0x20u}, - {0x91u, 0x48u}, - {0x92u, 0x20u}, - {0x9Au, 0x10u}, - {0xA0u, 0x04u}, - {0xA4u, 0x10u}, - {0xAEu, 0x10u}, - {0xB0u, 0x10u}, - {0xB6u, 0x10u}, - {0xC0u, 0xF0u}, - {0xC2u, 0xE0u}, - {0xC4u, 0xF0u}, - {0xCAu, 0xF0u}, - {0xCCu, 0xF5u}, - {0xCEu, 0xBEu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xDEu, 0x80u}, - {0xE2u, 0x40u}, - {0xE6u, 0x20u}, - {0xEAu, 0x02u}, - {0xEEu, 0x08u}, - {0xD4u, 0x40u}, - {0xDBu, 0x0Bu}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x04u, 0x20u}, - {0x06u, 0x02u}, - {0x07u, 0x60u}, - {0x0Eu, 0xA1u}, - {0x0Fu, 0x04u}, - {0x15u, 0x14u}, - {0x17u, 0x09u}, - {0x1Fu, 0x08u}, - {0x25u, 0x40u}, - {0x26u, 0x40u}, - {0x27u, 0x80u}, - {0x2Cu, 0x80u}, - {0x2Fu, 0x2Au}, - {0x36u, 0x02u}, - {0x37u, 0xA8u}, - {0x3Cu, 0x10u}, - {0x3Du, 0x80u}, - {0x3Eu, 0x01u}, + {0x32u, 0x03u}, + {0x33u, 0x08u}, + {0x36u, 0x20u}, + {0x37u, 0x70u}, + {0x3Eu, 0x44u}, {0x3Fu, 0x04u}, - {0x45u, 0x88u}, - {0x46u, 0x40u}, - {0x47u, 0x20u}, - {0x4Cu, 0x04u}, - {0x4Du, 0x0Au}, - {0x4Fu, 0x06u}, - {0x55u, 0x20u}, - {0x56u, 0x84u}, - {0x61u, 0x20u}, - {0x62u, 0x08u}, - {0x63u, 0x01u}, - {0x65u, 0x80u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x11u}, - {0x6Eu, 0x09u}, - {0x6Fu, 0x27u}, - {0x74u, 0xC0u}, - {0x76u, 0x02u}, - {0x78u, 0x02u}, - {0x7Eu, 0x80u}, - {0x81u, 0x48u}, - {0x90u, 0x18u}, - {0x92u, 0x80u}, - {0x93u, 0x40u}, - {0x94u, 0x20u}, - {0x96u, 0x01u}, - {0x98u, 0x23u}, - {0x9Bu, 0x38u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x06u}, - {0x9Fu, 0x45u}, - {0xA0u, 0x04u}, - {0xA1u, 0x08u}, - {0xA2u, 0x90u}, - {0xA4u, 0x50u}, - {0xA6u, 0x01u}, - {0xA7u, 0x23u}, - {0xAAu, 0x40u}, - {0xACu, 0x80u}, - {0xB1u, 0x12u}, - {0xC0u, 0xF0u}, - {0xC2u, 0xF0u}, - {0xC4u, 0x70u}, - {0xCAu, 0xF0u}, - {0xCCu, 0xF0u}, - {0xCEu, 0xF0u}, - {0xD0u, 0xF0u}, - {0xD2u, 0x20u}, - {0xD8u, 0x1Eu}, - {0xDEu, 0x81u}, - {0xE8u, 0x40u}, - {0xEEu, 0x03u}, - {0x9Cu, 0x04u}, - {0xA7u, 0x40u}, - {0xAEu, 0x11u}, - {0xB0u, 0x80u}, - {0xB6u, 0x10u}, - {0xE8u, 0x40u}, - {0xEAu, 0x02u}, - {0xEEu, 0x01u}, - {0x04u, 0x24u}, - {0x06u, 0x12u}, - {0x07u, 0x03u}, - {0x0Au, 0x24u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x03u}, - {0x10u, 0x40u}, - {0x12u, 0x80u}, - {0x13u, 0x20u}, - {0x16u, 0x80u}, - {0x1Au, 0x18u}, - {0x1Bu, 0x24u}, - {0x1Fu, 0x18u}, - {0x21u, 0x40u}, - {0x22u, 0x20u}, - {0x25u, 0x24u}, - {0x26u, 0x04u}, - {0x27u, 0x12u}, - {0x29u, 0x80u}, - {0x2Au, 0x40u}, - {0x2Cu, 0x24u}, - {0x2Du, 0x24u}, - {0x2Eu, 0x09u}, - {0x2Fu, 0x09u}, - {0x30u, 0x07u}, - {0x31u, 0x80u}, - {0x33u, 0x40u}, - {0x34u, 0x38u}, - {0x35u, 0x07u}, - {0x36u, 0xC0u}, - {0x37u, 0x38u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x05u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x99u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x85u, 0x33u}, - {0x86u, 0xFFu}, - {0x87u, 0xCCu}, - {0x89u, 0xFFu}, - {0x8Du, 0x0Fu}, - {0x8Eu, 0xFFu}, - {0x8Fu, 0xF0u}, - {0x90u, 0x96u}, - {0x92u, 0x69u}, + {0x81u, 0x33u}, + {0x82u, 0x02u}, + {0x83u, 0xCCu}, + {0x85u, 0x55u}, + {0x86u, 0x20u}, + {0x87u, 0xAAu}, + {0x88u, 0x20u}, + {0x89u, 0x96u}, + {0x8Au, 0x08u}, + {0x8Bu, 0x69u}, + {0x8Fu, 0xFFu}, + {0x90u, 0x20u}, + {0x92u, 0x10u}, {0x93u, 0xFFu}, - {0x94u, 0xFFu}, - {0x98u, 0x33u}, - {0x9Au, 0xCCu}, - {0x9Du, 0x96u}, - {0x9Fu, 0x69u}, - {0xA0u, 0x55u}, - {0xA1u, 0x55u}, - {0xA2u, 0xAAu}, - {0xA3u, 0xAAu}, - {0xA7u, 0xFFu}, - {0xACu, 0x0Fu}, - {0xAEu, 0xF0u}, - {0xB2u, 0xFFu}, - {0xB3u, 0xFFu}, + {0x95u, 0xFFu}, + {0x96u, 0x20u}, + {0x9Au, 0x18u}, + {0x9Eu, 0x07u}, + {0xA0u, 0x07u}, + {0xA4u, 0x01u}, + {0xA5u, 0x0Fu}, + {0xA7u, 0xF0u}, + {0xA8u, 0x04u}, + {0xB2u, 0x07u}, + {0xB4u, 0x38u}, + {0xB7u, 0xFFu}, {0xBEu, 0x04u}, - {0xBFu, 0x04u}, + {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x09u}, {0xDFu, 0x01u}, - {0x00u, 0x50u}, - {0x03u, 0x20u}, - {0x05u, 0x04u}, - {0x06u, 0x20u}, - {0x07u, 0x01u}, - {0x0Au, 0x64u}, - {0x0Eu, 0x80u}, - {0x0Fu, 0xA4u}, - {0x10u, 0xA5u}, - {0x13u, 0x40u}, - {0x14u, 0x40u}, - {0x15u, 0x40u}, + {0x00u, 0x40u}, + {0x03u, 0x10u}, + {0x05u, 0x10u}, + {0x06u, 0x80u}, + {0x07u, 0x20u}, + {0x09u, 0x08u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x82u}, + {0x0Du, 0x24u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x40u}, + {0x10u, 0x40u}, + {0x13u, 0x48u}, + {0x14u, 0x90u}, + {0x16u, 0x04u}, {0x18u, 0x40u}, - {0x1Au, 0x06u}, - {0x1Bu, 0x10u}, - {0x1Fu, 0x04u}, - {0x22u, 0x46u}, - {0x23u, 0x04u}, - {0x25u, 0x08u}, - {0x28u, 0x81u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x20u}, - {0x2Cu, 0x40u}, - {0x2Eu, 0x04u}, - {0x30u, 0x42u}, - {0x31u, 0x20u}, - {0x32u, 0x40u}, - {0x36u, 0x40u}, - {0x37u, 0x01u}, - {0x39u, 0x10u}, - {0x3Bu, 0x04u}, - {0x3Du, 0x40u}, - {0x3Eu, 0x20u}, - {0x3Fu, 0x04u}, - {0x6Au, 0x40u}, - {0x6Fu, 0x01u}, - {0x8Cu, 0x40u}, - {0x90u, 0x10u}, - {0x91u, 0x50u}, - {0x93u, 0x40u}, - {0x96u, 0x08u}, - {0x97u, 0x0Cu}, - {0x99u, 0x04u}, - {0x9Cu, 0x40u}, - {0x9Fu, 0x01u}, - {0xA0u, 0xA2u}, - {0xA1u, 0x20u}, - {0xA3u, 0x20u}, - {0xA5u, 0x08u}, - {0xA6u, 0x02u}, - {0xA7u, 0x50u}, - {0xADu, 0x50u}, - {0xB2u, 0xC0u}, - {0xB3u, 0x08u}, - {0xB4u, 0x42u}, - {0xC0u, 0xA7u}, - {0xC2u, 0x7Eu}, - {0xC4u, 0x9Fu}, - {0xCAu, 0xCFu}, - {0xCCu, 0x9Du}, - {0xCEu, 0x76u}, - {0xE2u, 0x40u}, - {0xEAu, 0x40u}, - {0xECu, 0x80u}, - {0x80u, 0x10u}, - {0x84u, 0x0Eu}, + {0x19u, 0x84u}, + {0x1Du, 0x20u}, + {0x1Fu, 0x14u}, + {0x20u, 0x02u}, + {0x21u, 0xC0u}, + {0x22u, 0x03u}, + {0x23u, 0x10u}, + {0x25u, 0x40u}, + {0x29u, 0x10u}, + {0x2Au, 0x01u}, + {0x2Fu, 0x20u}, + {0x31u, 0x80u}, + {0x32u, 0x01u}, + {0x36u, 0x06u}, + {0x39u, 0x18u}, + {0x3Au, 0x02u}, + {0x3Bu, 0x40u}, + {0x3Cu, 0x02u}, + {0x3Du, 0x60u}, + {0x3Fu, 0x0Cu}, + {0x5Bu, 0x40u}, + {0x60u, 0x02u}, + {0x6Du, 0x40u}, + {0x80u, 0x40u}, + {0x81u, 0x80u}, + {0x83u, 0x20u}, + {0x86u, 0x01u}, + {0x8Bu, 0x08u}, + {0x8Eu, 0x01u}, + {0xC0u, 0x75u}, + {0xC2u, 0xFFu}, + {0xC4u, 0x7Du}, + {0xCAu, 0x45u}, + {0xCCu, 0xC9u}, + {0xCEu, 0xFFu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE4u, 0x05u}, + {0x01u, 0x03u}, + {0x03u, 0x0Cu}, + {0x25u, 0x05u}, + {0x27u, 0x0Au}, + {0x29u, 0x06u}, + {0x2Bu, 0x09u}, + {0x35u, 0x0Fu}, + {0x3Fu, 0x10u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x85u, 0x10u}, + {0x87u, 0x2Du}, {0x89u, 0x01u}, - {0x8Au, 0x0Eu}, - {0x8Bu, 0x92u}, - {0x8Cu, 0x04u}, - {0x8Du, 0x19u}, - {0x8Fu, 0xA4u}, - {0x90u, 0x0Cu}, - {0x91u, 0x08u}, - {0x92u, 0x01u}, - {0x94u, 0x02u}, - {0x96u, 0x04u}, - {0x97u, 0x3Fu}, - {0x9Au, 0x0Bu}, - {0xA4u, 0x04u}, - {0xA7u, 0x04u}, - {0xA9u, 0x26u}, - {0xABu, 0x99u}, - {0xADu, 0x40u}, - {0xB0u, 0x10u}, - {0xB1u, 0x38u}, - {0xB3u, 0x40u}, - {0xB4u, 0x0Eu}, - {0xB5u, 0x07u}, - {0xB6u, 0x01u}, - {0xB7u, 0x80u}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x67u}, + {0x8Fu, 0x18u}, + {0x90u, 0x04u}, + {0x92u, 0x03u}, + {0x96u, 0x12u}, + {0x98u, 0x03u}, + {0x9Au, 0x14u}, + {0x9Fu, 0x40u}, + {0xA1u, 0x02u}, + {0xA4u, 0x08u}, + {0xA5u, 0x02u}, + {0xA9u, 0x16u}, + {0xAAu, 0x07u}, + {0xABu, 0x48u}, + {0xAFu, 0x77u}, + {0xB0u, 0x08u}, + {0xB1u, 0x07u}, + {0xB3u, 0x70u}, + {0xB4u, 0x07u}, + {0xB5u, 0x08u}, + {0xB6u, 0x10u}, {0xBEu, 0x41u}, - {0xBFu, 0x44u}, - {0xC0u, 0x26u}, - {0xC1u, 0x04u}, - {0xC2u, 0x50u}, - {0xC5u, 0xD2u}, - {0xC6u, 0xCEu}, - {0xC7u, 0x0Fu}, + {0xBFu, 0x10u}, + {0xC0u, 0x34u}, + {0xC1u, 0x02u}, + {0xC2u, 0x60u}, + {0xC5u, 0xCDu}, + {0xC6u, 0xF2u}, + {0xC7u, 0x0Eu}, {0xC8u, 0x1Fu}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, @@ -815,452 +602,743 @@ void cyfitter_cfg(void) {0xE8u, 0x40u}, {0xE9u, 0x40u}, {0xEEu, 0x08u}, - {0x00u, 0x80u}, - {0x02u, 0x80u}, - {0x03u, 0x28u}, - {0x04u, 0x08u}, - {0x07u, 0x10u}, - {0x09u, 0x20u}, - {0x0Bu, 0x60u}, - {0x12u, 0x10u}, + {0x01u, 0x40u}, + {0x03u, 0x01u}, + {0x09u, 0x08u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x40u}, + {0x12u, 0x08u}, {0x13u, 0x08u}, - {0x19u, 0x52u}, - {0x1Bu, 0x20u}, - {0x20u, 0x42u}, - {0x21u, 0x31u}, - {0x22u, 0x08u}, + {0x18u, 0x40u}, + {0x19u, 0x10u}, + {0x1Au, 0x0Cu}, + {0x1Bu, 0x40u}, + {0x20u, 0x28u}, + {0x21u, 0x0Du}, {0x23u, 0x40u}, - {0x28u, 0x02u}, - {0x29u, 0x18u}, - {0x33u, 0x09u}, - {0x38u, 0x50u}, - {0x39u, 0x20u}, - {0x40u, 0x40u}, - {0x41u, 0x10u}, - {0x48u, 0x41u}, - {0x49u, 0x19u}, - {0x50u, 0x04u}, - {0x52u, 0x10u}, + {0x24u, 0x08u}, + {0x25u, 0x10u}, + {0x27u, 0x04u}, + {0x29u, 0x1Au}, + {0x2Bu, 0x02u}, + {0x2Du, 0x20u}, + {0x2Fu, 0x10u}, + {0x33u, 0x80u}, + {0x38u, 0x20u}, + {0x39u, 0x08u}, + {0x3Bu, 0x40u}, + {0x3Fu, 0x01u}, + {0x41u, 0x05u}, + {0x42u, 0x04u}, + {0x48u, 0x84u}, + {0x49u, 0x0Au}, + {0x50u, 0x08u}, + {0x52u, 0x20u}, {0x53u, 0x80u}, - {0x59u, 0x02u}, - {0x5Au, 0xA8u}, - {0x60u, 0x04u}, - {0x62u, 0x4Au}, - {0x68u, 0x82u}, - {0x69u, 0x14u}, - {0x70u, 0x20u}, - {0x72u, 0x80u}, - {0x73u, 0x12u}, - {0x81u, 0x10u}, - {0x84u, 0x01u}, - {0x87u, 0x10u}, - {0x8Bu, 0x11u}, - {0x90u, 0x04u}, - {0x91u, 0x40u}, - {0x92u, 0xA0u}, - {0x95u, 0x26u}, - {0x97u, 0x4Cu}, - {0x99u, 0x04u}, - {0x9Cu, 0x41u}, - {0x9Du, 0x11u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x1Bu}, - {0xA5u, 0x28u}, - {0xA7u, 0xF0u}, - {0xA8u, 0x40u}, - {0xAAu, 0x10u}, - {0xACu, 0x40u}, - {0xAEu, 0x01u}, - {0xAFu, 0x04u}, - {0xB2u, 0x02u}, - {0xB7u, 0x10u}, - {0xC0u, 0x0Fu}, + {0x58u, 0x24u}, + {0x59u, 0x80u}, + {0x5Bu, 0x02u}, + {0x60u, 0x48u}, + {0x61u, 0x80u}, + {0x63u, 0x10u}, + {0x68u, 0x02u}, + {0x69u, 0x10u}, + {0x6Bu, 0x50u}, + {0x71u, 0x01u}, + {0x72u, 0x02u}, + {0x73u, 0x24u}, + {0x80u, 0x06u}, + {0x81u, 0x40u}, + {0x83u, 0x01u}, + {0x85u, 0x09u}, + {0x86u, 0x04u}, + {0x87u, 0x08u}, + {0x89u, 0x04u}, + {0x8Au, 0x01u}, + {0x8Eu, 0x28u}, + {0x8Fu, 0x02u}, + {0x90u, 0x20u}, + {0x91u, 0xC0u}, + {0x92u, 0x02u}, + {0x93u, 0x38u}, + {0x95u, 0x18u}, + {0x96u, 0x05u}, + {0x97u, 0xC0u}, + {0x98u, 0x02u}, + {0x99u, 0x80u}, + {0x9Cu, 0xD0u}, + {0x9Du, 0x10u}, + {0x9Eu, 0x86u}, + {0x9Fu, 0x30u}, + {0xA1u, 0x40u}, + {0xA3u, 0x24u}, + {0xA5u, 0x18u}, + {0xA6u, 0x04u}, + {0xA8u, 0x10u}, + {0xB3u, 0x04u}, + {0xB5u, 0x24u}, + {0xB7u, 0x41u}, + {0xC0u, 0x01u}, {0xC2u, 0x0Eu}, - {0xC4u, 0x04u}, - {0xCAu, 0x0Eu}, - {0xCCu, 0x03u}, - {0xCEu, 0x0Cu}, - {0xD0u, 0x05u}, - {0xD2u, 0x0Cu}, + {0xC4u, 0x06u}, + {0xCAu, 0x6Fu}, + {0xCCu, 0x08u}, + {0xCEu, 0x8Eu}, + {0xD0u, 0x07u}, + {0xD2u, 0x04u}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE2u, 0x02u}, - {0xE6u, 0x21u}, - {0xE8u, 0x02u}, - {0xECu, 0x0Cu}, - {0x01u, 0x04u}, - {0x03u, 0x01u}, - {0x04u, 0x24u}, - {0x05u, 0x10u}, - {0x06u, 0x12u}, - {0x0Bu, 0x04u}, - {0x0Eu, 0x18u}, - {0x0Fu, 0x04u}, - {0x10u, 0x40u}, + {0xE0u, 0x06u}, + {0xE2u, 0x08u}, + {0xE4u, 0x0Fu}, + {0xEAu, 0x04u}, + {0xEEu, 0x40u}, + {0x00u, 0x08u}, + {0x05u, 0xFFu}, + {0x06u, 0x03u}, + {0x0Au, 0x04u}, + {0x0Du, 0x33u}, + {0x0Fu, 0xCCu}, + {0x10u, 0x04u}, + {0x12u, 0x02u}, + {0x13u, 0xFFu}, + {0x15u, 0x96u}, + {0x17u, 0x69u}, + {0x18u, 0x04u}, + {0x1Au, 0x01u}, + {0x20u, 0x08u}, + {0x25u, 0x0Fu}, + {0x26u, 0x04u}, + {0x27u, 0xF0u}, + {0x28u, 0x08u}, + {0x29u, 0x55u}, + {0x2Bu, 0xAAu}, + {0x2Cu, 0x08u}, + {0x2Fu, 0xFFu}, + {0x30u, 0x08u}, + {0x33u, 0xFFu}, + {0x34u, 0x07u}, + {0x38u, 0x02u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x09u}, + {0x5Fu, 0x01u}, + {0x81u, 0x02u}, + {0x83u, 0x0Du}, + {0x84u, 0x04u}, + {0x86u, 0x03u}, + {0x87u, 0x10u}, + {0x88u, 0x08u}, + {0x89u, 0x02u}, + {0x8Au, 0x03u}, + {0x8Bu, 0x54u}, + {0x8Du, 0x8Du}, + {0x91u, 0x8Du}, + {0x94u, 0x01u}, + {0x95u, 0x62u}, + {0x96u, 0x02u}, + {0x97u, 0x08u}, + {0x99u, 0x01u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x32u}, + {0x9Eu, 0x0Cu}, + {0xA3u, 0x80u}, + {0xA5u, 0x8Du}, + {0xA9u, 0x8Du}, + {0xADu, 0x0Du}, + {0xAEu, 0x12u}, + {0xAFu, 0x80u}, + {0xB1u, 0x0Fu}, + {0xB3u, 0x70u}, + {0xB4u, 0x10u}, + {0xB5u, 0x80u}, + {0xB6u, 0x0Fu}, + {0xBBu, 0x02u}, + {0xBFu, 0x10u}, + {0xD4u, 0x40u}, + {0xD8u, 0x0Bu}, + {0xD9u, 0x0Bu}, + {0xDBu, 0x0Bu}, + {0xDCu, 0x99u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x24u}, + {0x02u, 0x40u}, + {0x04u, 0x28u}, + {0x06u, 0x04u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x40u}, + {0x0Eu, 0x25u}, + {0x10u, 0x80u}, + {0x11u, 0x80u}, + {0x13u, 0x24u}, + {0x16u, 0x02u}, + {0x18u, 0x04u}, + {0x19u, 0x20u}, + {0x1Au, 0x80u}, + {0x1Eu, 0x05u}, + {0x23u, 0x20u}, + {0x25u, 0x25u}, + {0x2Bu, 0x25u}, + {0x2Cu, 0x20u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x10u}, + {0x2Fu, 0x02u}, + {0x33u, 0x05u}, + {0x34u, 0x10u}, + {0x36u, 0x19u}, + {0x39u, 0x84u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x2Au}, + {0x45u, 0x20u}, + {0x46u, 0x08u}, + {0x66u, 0x28u}, + {0x67u, 0x01u}, + {0x7Cu, 0x02u}, + {0x80u, 0x80u}, + {0x8Du, 0x04u}, + {0x91u, 0x8Cu}, + {0x92u, 0x08u}, + {0x93u, 0x4Cu}, + {0x96u, 0x01u}, + {0x97u, 0x80u}, + {0x98u, 0x02u}, + {0x99u, 0x11u}, + {0x9Bu, 0x45u}, + {0x9Cu, 0xD0u}, + {0x9Du, 0x20u}, + {0x9Eu, 0x84u}, + {0xA0u, 0x10u}, + {0xA1u, 0x40u}, + {0xA3u, 0x24u}, + {0xA6u, 0x04u}, + {0xA8u, 0x80u}, + {0xACu, 0x0Cu}, + {0xADu, 0x80u}, + {0xB1u, 0x04u}, + {0xB3u, 0x02u}, + {0xB4u, 0x28u}, + {0xB7u, 0x40u}, + {0xC0u, 0x6Eu}, + {0xC2u, 0xEAu}, + {0xC4u, 0x8Fu}, + {0xCAu, 0xFEu}, + {0xCCu, 0xE3u}, + {0xCEu, 0xFAu}, + {0xD8u, 0x70u}, + {0xDEu, 0x80u}, + {0xE2u, 0x04u}, + {0xE6u, 0x40u}, + {0xE8u, 0x04u}, + {0xEAu, 0x08u}, + {0xEEu, 0x4Au}, + {0x82u, 0x04u}, + {0x8Au, 0x04u}, + {0x8Eu, 0x03u}, + {0x98u, 0x04u}, + {0x9Au, 0x01u}, + {0xACu, 0x04u}, + {0xAEu, 0x02u}, + {0xB0u, 0x07u}, + {0xD8u, 0x04u}, + {0xDCu, 0x09u}, + {0xDFu, 0x01u}, + {0x00u, 0x60u}, + {0x03u, 0x40u}, + {0x04u, 0x29u}, + {0x06u, 0x02u}, + {0x0Au, 0x08u}, + {0x0Du, 0x20u}, + {0x0Eu, 0x62u}, + {0x13u, 0x40u}, + {0x17u, 0x15u}, + {0x18u, 0x40u}, + {0x1Bu, 0x01u}, + {0x1Eu, 0x01u}, + {0x24u, 0x2Eu}, + {0x25u, 0x10u}, + {0x26u, 0x08u}, + {0x27u, 0x02u}, + {0x2Cu, 0x20u}, + {0x2Eu, 0x10u}, + {0x36u, 0x59u}, + {0x39u, 0x04u}, + {0x3Au, 0x08u}, + {0x3Cu, 0x81u}, + {0x3Du, 0x20u}, + {0x3Fu, 0x08u}, + {0x45u, 0x1Au}, + {0x4Cu, 0x01u}, + {0x4Du, 0x02u}, + {0x4Eu, 0x08u}, + {0x4Fu, 0x09u}, + {0x56u, 0x2Au}, + {0x65u, 0x20u}, + {0x6Cu, 0x20u}, + {0x6Du, 0x03u}, + {0x6Eu, 0xD2u}, + {0x6Fu, 0x16u}, + {0x74u, 0x40u}, + {0x77u, 0x01u}, + {0x7Cu, 0x02u}, + {0x81u, 0x02u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x04u}, + {0x91u, 0x08u}, + {0x92u, 0x08u}, + {0x93u, 0x48u}, + {0x94u, 0x28u}, + {0x96u, 0x10u}, + {0x97u, 0x01u}, + {0x98u, 0x02u}, + {0x99u, 0x11u}, + {0x9Bu, 0x40u}, + {0x9Cu, 0xC0u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x22u}, + {0xA0u, 0x10u}, + {0xA4u, 0x60u}, + {0xA5u, 0x10u}, + {0xA6u, 0x1Du}, + {0xA7u, 0x03u}, + {0xA9u, 0x10u}, + {0xAAu, 0xC0u}, + {0xAFu, 0x40u}, + {0xB2u, 0x40u}, + {0xB4u, 0x04u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xF2u}, + {0xC4u, 0x71u}, + {0xCAu, 0x60u}, + {0xCCu, 0xF0u}, + {0xCEu, 0xF0u}, + {0xD0u, 0xE0u}, + {0xD2u, 0x30u}, + {0xD8u, 0x20u}, + {0xDEu, 0x80u}, + {0xEEu, 0x42u}, + {0x8Du, 0x40u}, + {0x95u, 0x40u}, + {0xAFu, 0x08u}, + {0xB3u, 0x40u}, + {0xE0u, 0x40u}, + {0xEEu, 0x80u}, + {0x38u, 0x08u}, + {0x3Eu, 0x04u}, + {0x58u, 0x04u}, + {0x5Fu, 0x01u}, + {0x1Bu, 0x08u}, + {0x80u, 0x10u}, + {0x90u, 0x20u}, + {0x93u, 0x80u}, + {0x95u, 0x40u}, + {0xA8u, 0x20u}, + {0xABu, 0x08u}, + {0xACu, 0x05u}, + {0xADu, 0x04u}, + {0xB0u, 0x04u}, + {0xB2u, 0x20u}, + {0xB4u, 0x40u}, + {0xB7u, 0x90u}, + {0xEAu, 0x60u}, + {0xECu, 0x90u}, + {0xEEu, 0x04u}, + {0x04u, 0x0Fu}, + {0x05u, 0x04u}, + {0x06u, 0xF0u}, + {0x07u, 0x02u}, + {0x0Cu, 0x55u}, + {0x0Du, 0x04u}, + {0x0Eu, 0xAAu}, + {0x0Fu, 0x01u}, + {0x10u, 0x33u}, + {0x12u, 0xCCu}, {0x13u, 0x03u}, - {0x15u, 0x10u}, - {0x16u, 0x03u}, - {0x19u, 0x04u}, - {0x1Au, 0x24u}, - {0x1Bu, 0x02u}, - {0x1Du, 0x10u}, - {0x21u, 0x20u}, - {0x22u, 0x04u}, - {0x26u, 0x20u}, - {0x29u, 0x08u}, - {0x2Cu, 0x24u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x09u}, - {0x30u, 0x38u}, - {0x31u, 0x07u}, - {0x32u, 0x07u}, - {0x33u, 0x10u}, - {0x34u, 0x40u}, + {0x17u, 0x04u}, + {0x19u, 0x08u}, + {0x1Au, 0xFFu}, + {0x1Cu, 0x69u}, + {0x1Eu, 0x96u}, + {0x20u, 0xFFu}, + {0x2Bu, 0x04u}, + {0x2Cu, 0xFFu}, {0x35u, 0x08u}, - {0x37u, 0x20u}, - {0x39u, 0x08u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x54u}, + {0x36u, 0xFFu}, + {0x37u, 0x07u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x99u}, + {0x5Cu, 0x90u}, {0x5Fu, 0x01u}, - {0x85u, 0x33u}, - {0x86u, 0xFFu}, - {0x87u, 0xCCu}, - {0x89u, 0xFFu}, - {0x8Du, 0x0Fu}, - {0x8Eu, 0xFFu}, - {0x8Fu, 0xF0u}, - {0x90u, 0x69u}, - {0x92u, 0x96u}, - {0x93u, 0xFFu}, - {0x96u, 0xFFu}, - {0x98u, 0x33u}, - {0x9Au, 0xCCu}, - {0x9Du, 0x69u}, - {0x9Fu, 0x96u}, - {0xA0u, 0x55u}, - {0xA1u, 0x55u}, - {0xA2u, 0xAAu}, - {0xA3u, 0xAAu}, - {0xA9u, 0xFFu}, - {0xACu, 0x0Fu}, - {0xAEu, 0xF0u}, - {0xB0u, 0xFFu}, - {0xB7u, 0xFFu}, - {0xBEu, 0x01u}, - {0xBFu, 0x40u}, + {0x84u, 0x0Fu}, + {0x86u, 0xF0u}, + {0x88u, 0x69u}, + {0x89u, 0x02u}, + {0x8Au, 0x96u}, + {0x8Cu, 0x55u}, + {0x8Eu, 0xAAu}, + {0x90u, 0x33u}, + {0x92u, 0xCCu}, + {0x95u, 0x01u}, + {0x9Eu, 0xFFu}, + {0xA1u, 0x04u}, + {0xA2u, 0xFFu}, + {0xA5u, 0x08u}, + {0xAEu, 0xFFu}, + {0xB1u, 0x04u}, + {0xB2u, 0xFFu}, + {0xB3u, 0x01u}, + {0xB5u, 0x02u}, + {0xB7u, 0x08u}, + {0xBEu, 0x04u}, + {0xBFu, 0x55u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x01u, 0x40u}, - {0x03u, 0x20u}, - {0x05u, 0x04u}, + {0x01u, 0x08u}, + {0x03u, 0x09u}, + {0x05u, 0x08u}, {0x07u, 0x01u}, - {0x08u, 0x01u}, - {0x09u, 0x20u}, - {0x0Au, 0x10u}, - {0x0Cu, 0x08u}, - {0x0Eu, 0x80u}, - {0x0Fu, 0xA4u}, - {0x11u, 0x04u}, - {0x13u, 0x42u}, - {0x14u, 0x40u}, + {0x08u, 0x81u}, + {0x0Au, 0x80u}, + {0x0Cu, 0x01u}, + {0x0Eu, 0x0Au}, + {0x11u, 0x40u}, + {0x12u, 0x80u}, + {0x14u, 0x80u}, {0x15u, 0x40u}, - {0x18u, 0x44u}, - {0x19u, 0x04u}, - {0x1Au, 0x10u}, - {0x1Fu, 0x02u}, - {0x22u, 0x55u}, - {0x26u, 0x80u}, - {0x2Au, 0x22u}, - {0x2Bu, 0x02u}, - {0x2Cu, 0x48u}, - {0x31u, 0x18u}, - {0x32u, 0x81u}, - {0x36u, 0x40u}, - {0x37u, 0x01u}, - {0x39u, 0x22u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x08u}, - {0x3Cu, 0x40u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x04u}, - {0x43u, 0xC0u}, - {0x59u, 0x01u}, - {0x5Bu, 0x58u}, - {0x86u, 0x20u}, - {0x8Au, 0x04u}, - {0xC0u, 0xA5u}, - {0xC2u, 0x7Eu}, - {0xC4u, 0x9Du}, - {0xCAu, 0xADu}, - {0xCCu, 0x9Fu}, - {0xCEu, 0x7Fu}, - {0xD6u, 0x0Fu}, - {0xE2u, 0x88u}, - {0x80u, 0x01u}, - {0x90u, 0x02u}, - {0xB2u, 0x01u}, - {0xEAu, 0x20u}, - {0x01u, 0x05u}, - {0x02u, 0x01u}, - {0x05u, 0x09u}, - {0x06u, 0x0Cu}, - {0x07u, 0x02u}, - {0x08u, 0x01u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x38u}, - {0x0Eu, 0x10u}, - {0x0Fu, 0x04u}, - {0x13u, 0x05u}, - {0x14u, 0x04u}, - {0x15u, 0x05u}, - {0x16u, 0x03u}, - {0x18u, 0x10u}, - {0x19u, 0x23u}, + {0x18u, 0x20u}, + {0x1Fu, 0x40u}, + {0x20u, 0x4Au}, + {0x21u, 0x04u}, + {0x26u, 0x20u}, + {0x27u, 0x03u}, + {0x28u, 0x20u}, + {0x2Bu, 0x80u}, + {0x2Cu, 0x04u}, + {0x33u, 0x04u}, + {0x36u, 0x08u}, + {0x37u, 0x12u}, + {0x3Au, 0x20u}, + {0x3Du, 0x84u}, + {0x5Du, 0x22u}, + {0x5Fu, 0x88u}, + {0x6Cu, 0x01u}, + {0x82u, 0x8Du}, + {0x83u, 0x0Cu}, + {0x85u, 0x46u}, + {0x88u, 0x80u}, + {0x8Au, 0x20u}, + {0x8Bu, 0x80u}, + {0x8Du, 0x60u}, + {0x92u, 0x80u}, + {0x94u, 0x02u}, + {0x99u, 0x08u}, + {0x9Fu, 0x01u}, + {0xB3u, 0x01u}, + {0xB4u, 0x01u}, + {0xC0u, 0xA7u}, + {0xC2u, 0xD9u}, + {0xC4u, 0x99u}, + {0xCAu, 0x23u}, + {0xCCu, 0xE2u}, + {0xCEu, 0x54u}, + {0xD6u, 0xF0u}, + {0xE0u, 0x30u}, + {0xE2u, 0x09u}, + {0xE6u, 0x40u}, + {0xEAu, 0x44u}, + {0xEEu, 0x20u}, + {0x81u, 0x08u}, + {0x82u, 0x40u}, + {0xE4u, 0x05u}, + {0xE6u, 0xC0u}, + {0x87u, 0x04u}, + {0x93u, 0x08u}, + {0xA8u, 0x20u}, + {0xABu, 0x04u}, + {0x00u, 0x2Cu}, + {0x01u, 0x01u}, + {0x04u, 0xC1u}, + {0x06u, 0x2Eu}, + {0x08u, 0x60u}, + {0x09u, 0x48u}, + {0x0Au, 0x8Fu}, + {0x0Bu, 0x21u}, + {0x0Cu, 0x44u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x20u}, + {0x10u, 0x0Cu}, + {0x12u, 0x20u}, + {0x14u, 0x21u}, + {0x15u, 0x62u}, + {0x16u, 0xC2u}, + {0x17u, 0x08u}, + {0x18u, 0x08u}, + {0x19u, 0x01u}, {0x1Cu, 0x10u}, - {0x1Du, 0x02u}, - {0x1Fu, 0x01u}, - {0x20u, 0x10u}, - {0x21u, 0x05u}, - {0x24u, 0x10u}, - {0x25u, 0x05u}, - {0x28u, 0x08u}, - {0x29u, 0x02u}, - {0x2Au, 0x03u}, - {0x2Bu, 0x11u}, - {0x2Du, 0x38u}, - {0x2Eu, 0x22u}, - {0x30u, 0x20u}, - {0x31u, 0x03u}, + {0x1Du, 0x01u}, + {0x20u, 0x2Cu}, + {0x21u, 0x10u}, + {0x24u, 0x20u}, + {0x25u, 0x04u}, + {0x26u, 0x0Cu}, + {0x28u, 0x24u}, + {0x29u, 0x47u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x18u}, + {0x2Cu, 0x10u}, + {0x2Du, 0x01u}, + {0x30u, 0x80u}, + {0x31u, 0x3Fu}, {0x32u, 0x0Fu}, - {0x33u, 0x04u}, - {0x36u, 0x10u}, - {0x37u, 0x38u}, - {0x3Bu, 0x02u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x44u}, + {0x34u, 0x10u}, + {0x36u, 0x60u}, + {0x37u, 0x40u}, + {0x38u, 0x20u}, + {0x39u, 0x02u}, + {0x3Au, 0x80u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x41u}, + {0x54u, 0x09u}, {0x58u, 0x0Bu}, - {0x59u, 0x0Bu}, - {0x5Cu, 0x99u}, + {0x59u, 0x04u}, + {0x5Bu, 0x0Bu}, + {0x5Cu, 0x09u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x18u}, - {0x86u, 0x60u}, - {0x87u, 0x06u}, - {0x8Cu, 0x04u}, - {0x8Eu, 0x03u}, - {0x93u, 0x02u}, - {0x94u, 0x03u}, - {0x96u, 0x04u}, - {0x97u, 0x0Au}, - {0x98u, 0x30u}, - {0x99u, 0x0Cu}, - {0x9Au, 0x48u}, - {0x9Du, 0x01u}, - {0xA4u, 0x01u}, - {0xA6u, 0x06u}, - {0xA8u, 0x05u}, - {0xAAu, 0x02u}, - {0xACu, 0x28u}, - {0xAEu, 0x50u}, - {0xB1u, 0x0Eu}, - {0xB3u, 0x01u}, - {0xB4u, 0x78u}, + {0x84u, 0x19u}, + {0x86u, 0x24u}, + {0x87u, 0x04u}, + {0x8Du, 0x04u}, + {0x8Fu, 0x02u}, + {0x93u, 0x03u}, + {0x94u, 0x09u}, + {0x96u, 0x32u}, + {0x98u, 0x20u}, + {0x9Au, 0x18u}, + {0x9Cu, 0x06u}, + {0xA3u, 0x04u}, + {0xA8u, 0x2Au}, + {0xA9u, 0x04u}, + {0xAAu, 0x11u}, + {0xABu, 0x01u}, + {0xB1u, 0x07u}, + {0xB4u, 0x38u}, {0xB6u, 0x07u}, - {0xBAu, 0x80u}, - {0xBEu, 0x10u}, - {0xBFu, 0x04u}, + {0xB8u, 0x80u}, + {0xBAu, 0x20u}, {0xD8u, 0x0Bu}, - {0xD9u, 0x0Bu}, + {0xD9u, 0x04u}, {0xDCu, 0x99u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x80u}, - {0x05u, 0x05u}, - {0x06u, 0x20u}, - {0x07u, 0x09u}, - {0x08u, 0x20u}, + {0x00u, 0x04u}, + {0x04u, 0x28u}, + {0x05u, 0x40u}, + {0x06u, 0x80u}, + {0x08u, 0x80u}, {0x09u, 0x08u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x28u}, - {0x11u, 0x04u}, - {0x13u, 0x60u}, - {0x15u, 0x41u}, - {0x17u, 0x14u}, - {0x18u, 0x04u}, - {0x19u, 0x80u}, - {0x1Du, 0x85u}, - {0x1Eu, 0x02u}, - {0x20u, 0x20u}, - {0x22u, 0x01u}, + {0x0Au, 0x06u}, + {0x0Eu, 0xA1u}, + {0x0Fu, 0x08u}, + {0x12u, 0x08u}, + {0x15u, 0x01u}, + {0x17u, 0x94u}, + {0x19u, 0x20u}, + {0x1Au, 0x06u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x68u}, + {0x1Eu, 0x60u}, + {0x1Fu, 0x28u}, + {0x21u, 0x02u}, {0x24u, 0x02u}, - {0x26u, 0x0Au}, - {0x27u, 0x40u}, - {0x2Cu, 0x81u}, - {0x2Fu, 0x28u}, - {0x31u, 0x08u}, - {0x32u, 0x41u}, - {0x33u, 0x18u}, - {0x37u, 0x65u}, - {0x38u, 0x08u}, - {0x3Du, 0x05u}, - {0x3Eu, 0xA0u}, + {0x27u, 0x80u}, + {0x29u, 0x11u}, + {0x2Eu, 0x02u}, + {0x2Fu, 0x2Au}, + {0x31u, 0x02u}, + {0x35u, 0x40u}, + {0x36u, 0x08u}, + {0x37u, 0x10u}, + {0x39u, 0x08u}, + {0x3Bu, 0x40u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x22u}, + {0x3Eu, 0x80u}, + {0x4Cu, 0x01u}, + {0x4Du, 0x80u}, + {0x5Cu, 0x20u}, + {0x5Du, 0x04u}, + {0x5Eu, 0x40u}, + {0x5Fu, 0x02u}, + {0x65u, 0x80u}, {0x78u, 0x02u}, - {0x7Eu, 0x80u}, - {0x90u, 0x08u}, - {0x91u, 0x45u}, - {0x92u, 0x80u}, - {0x93u, 0x40u}, - {0x94u, 0x04u}, - {0x98u, 0x23u}, - {0x9Au, 0x80u}, - {0x9Bu, 0x3Du}, - {0x9Du, 0x80u}, - {0x9Fu, 0x40u}, - {0xA0u, 0x84u}, - {0xA1u, 0x08u}, - {0xA2u, 0x94u}, - {0xA3u, 0x20u}, - {0xA4u, 0x10u}, - {0xA5u, 0x80u}, - {0xA6u, 0x0Bu}, - {0xA8u, 0x04u}, - {0xAEu, 0x40u}, - {0xB6u, 0x80u}, - {0xB7u, 0x01u}, - {0xC0u, 0xF5u}, - {0xC2u, 0xE6u}, - {0xC4u, 0xF7u}, - {0xCAu, 0xF0u}, - {0xCCu, 0xFFu}, - {0xCEu, 0xF2u}, + {0x7Cu, 0x02u}, + {0x89u, 0x02u}, + {0x90u, 0x2Cu}, + {0x91u, 0x0Du}, + {0x92u, 0x01u}, + {0x93u, 0x48u}, + {0x94u, 0x01u}, + {0x98u, 0x02u}, + {0x99u, 0x11u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x16u}, + {0x9Cu, 0x80u}, + {0x9Du, 0x20u}, + {0xA0u, 0x40u}, + {0xA1u, 0x11u}, + {0xA2u, 0x48u}, + {0xA3u, 0x06u}, + {0xA5u, 0x28u}, + {0xA6u, 0x10u}, + {0xACu, 0x40u}, + {0xC0u, 0xF4u}, + {0xC2u, 0xF7u}, + {0xC4u, 0xF2u}, + {0xCAu, 0xF5u}, + {0xCCu, 0x71u}, + {0xCEu, 0xBAu}, + {0xD6u, 0xF0u}, + {0xD8u, 0x10u}, {0xDEu, 0x81u}, - {0xE8u, 0x04u}, - {0xECu, 0x80u}, + {0xE6u, 0x20u}, + {0xEAu, 0x02u}, {0xEEu, 0x02u}, - {0xABu, 0x40u}, - {0xB0u, 0x04u}, - {0xECu, 0x80u}, + {0xEAu, 0x02u}, {0xEEu, 0x02u}, - {0x33u, 0x40u}, + {0x30u, 0x20u}, + {0x33u, 0x01u}, {0x36u, 0x40u}, - {0x58u, 0x08u}, - {0x5Cu, 0x01u}, - {0x5Du, 0x10u}, + {0x53u, 0x08u}, + {0x5Bu, 0x08u}, {0x61u, 0x08u}, - {0x64u, 0x10u}, - {0x89u, 0x10u}, - {0xCCu, 0x30u}, - {0xD6u, 0xE0u}, + {0x65u, 0xA0u}, + {0x85u, 0x20u}, + {0xCCu, 0x70u}, + {0xD4u, 0x20u}, + {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0x59u, 0x40u}, - {0x5Fu, 0x20u}, - {0x83u, 0x40u}, - {0x8Bu, 0x20u}, - {0x9Cu, 0x08u}, - {0x9Fu, 0x40u}, + {0xE6u, 0x40u}, + {0x59u, 0x10u}, + {0x5Eu, 0x40u}, + {0x81u, 0x18u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x01u}, + {0xA4u, 0x20u}, {0xA5u, 0x08u}, {0xA6u, 0x40u}, - {0xA8u, 0x01u}, - {0xACu, 0x10u}, + {0xA7u, 0x08u}, + {0xB7u, 0x08u}, {0xD4u, 0x80u}, {0xD6u, 0x20u}, - {0xE6u, 0x80u}, - {0xEAu, 0x80u}, - {0xEEu, 0x40u}, - {0x89u, 0x08u}, - {0x8Cu, 0x08u}, - {0x9Cu, 0x08u}, + {0xE0u, 0x80u}, + {0xE6u, 0x20u}, + {0x10u, 0x20u}, + {0x58u, 0x02u}, + {0x8Fu, 0x02u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x01u}, + {0xA4u, 0x20u}, {0xA5u, 0x08u}, {0xA6u, 0x40u}, - {0xADu, 0x40u}, - {0xEEu, 0x10u}, - {0x94u, 0x02u}, + {0xA7u, 0x08u}, + {0xB6u, 0x40u}, + {0xC4u, 0x10u}, + {0xD6u, 0x40u}, + {0x80u, 0x01u}, + {0x97u, 0x10u}, + {0x9Fu, 0x01u}, + {0xA3u, 0x02u}, + {0xA5u, 0x08u}, {0xA6u, 0x40u}, - {0xB4u, 0x01u}, - {0x08u, 0x80u}, - {0x0Fu, 0x40u}, - {0x12u, 0x80u}, - {0x53u, 0x04u}, - {0x57u, 0x80u}, - {0x5Bu, 0x20u}, - {0x5Cu, 0x10u}, - {0x84u, 0x80u}, + {0xABu, 0x08u}, + {0xACu, 0x02u}, + {0xAFu, 0x10u}, + {0xB5u, 0x80u}, + {0xE0u, 0x80u}, + {0xE8u, 0x10u}, + {0xEEu, 0xC0u}, + {0x09u, 0x20u}, + {0x0Fu, 0x80u}, + {0x13u, 0x08u}, + {0x52u, 0x20u}, + {0x53u, 0x01u}, + {0x57u, 0x20u}, + {0x5Fu, 0x80u}, + {0x82u, 0x20u}, + {0x83u, 0x20u}, + {0x8Bu, 0x08u}, + {0x8Eu, 0x01u}, {0xC2u, 0x06u}, {0xC4u, 0x08u}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x01u, 0x20u}, - {0x06u, 0x80u}, - {0x07u, 0x01u}, - {0x09u, 0x01u}, - {0x0Au, 0x02u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x20u}, - {0x82u, 0x40u}, - {0x87u, 0x01u}, - {0x8Bu, 0x40u}, - {0x93u, 0x40u}, - {0x98u, 0x80u}, - {0xA4u, 0x80u}, - {0xABu, 0x80u}, - {0xAFu, 0x24u}, - {0xB2u, 0x80u}, - {0xB4u, 0x10u}, + {0xE6u, 0x03u}, + {0x02u, 0x01u}, + {0x04u, 0x40u}, + {0x06u, 0x20u}, + {0x0Bu, 0x11u}, + {0x0Fu, 0x82u}, + {0x83u, 0x01u}, + {0x86u, 0x20u}, + {0x8Bu, 0x11u}, + {0x8Du, 0x20u}, + {0x8Fu, 0x01u}, + {0x97u, 0x02u}, + {0x9Eu, 0x01u}, + {0xA1u, 0x20u}, + {0xABu, 0x40u}, + {0xB3u, 0x80u}, {0xC0u, 0x07u}, {0xC2u, 0x0Fu}, - {0xE2u, 0x04u}, - {0xE8u, 0x08u}, - {0xEAu, 0x01u}, - {0x92u, 0x02u}, - {0x96u, 0x80u}, - {0x9Au, 0x80u}, - {0xA1u, 0x01u}, - {0xB0u, 0x80u}, - {0xB2u, 0x10u}, - {0xB5u, 0x20u}, - {0xEAu, 0x0Du}, - {0x0Au, 0x80u}, - {0x0Fu, 0x40u}, - {0x96u, 0x80u}, - {0xA9u, 0x01u}, - {0xAEu, 0x80u}, - {0xB2u, 0x01u}, + {0xE0u, 0x02u}, + {0xE2u, 0x01u}, + {0xE6u, 0x03u}, + {0xECu, 0x04u}, + {0xA8u, 0x40u}, + {0xB7u, 0x40u}, + {0xEEu, 0x02u}, + {0x0Bu, 0x40u}, + {0x0Du, 0x08u}, {0xC2u, 0x0Cu}, - {0xEAu, 0x04u}, - {0x22u, 0x08u}, - {0x24u, 0x02u}, - {0x94u, 0x02u}, - {0x9Eu, 0x20u}, - {0xA6u, 0x08u}, - {0xAEu, 0x60u}, - {0xB2u, 0x08u}, + {0x23u, 0x10u}, + {0x26u, 0x10u}, + {0x89u, 0x08u}, + {0x94u, 0x01u}, + {0x97u, 0x10u}, + {0xA3u, 0x02u}, + {0xA5u, 0x08u}, + {0xA6u, 0x10u}, + {0xAEu, 0x50u}, + {0xAFu, 0x01u}, {0xC8u, 0x60u}, - {0xE8u, 0x10u}, + {0xEAu, 0x40u}, + {0xECu, 0x10u}, {0xEEu, 0x40u}, - {0x06u, 0x20u}, - {0x53u, 0x01u}, - {0x5Du, 0x20u}, - {0x83u, 0x01u}, - {0x99u, 0x20u}, - {0x9Eu, 0x20u}, - {0xB1u, 0x20u}, + {0x04u, 0x01u}, + {0x53u, 0x02u}, + {0x57u, 0x01u}, + {0x87u, 0x01u}, + {0x94u, 0x01u}, + {0xA3u, 0x02u}, {0xC0u, 0x20u}, {0xD4u, 0x80u}, {0xD6u, 0x20u}, - {0xE6u, 0x20u}, + {0xE6u, 0x10u}, + {0xADu, 0x08u}, {0xAFu, 0x40u}, {0x01u, 0x01u}, + {0x09u, 0x01u}, {0x0Bu, 0x01u}, - {0x0Du, 0x01u}, {0x0Fu, 0x01u}, {0x11u, 0x01u}, {0x1Bu, 0x01u}, - {0x00u, 0x0Au}, + {0x00u, 0x2Bu}, }; @@ -1279,6 +1357,7 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ + {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u}, {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u}, @@ -1290,12 +1369,12 @@ void cyfitter_cfg(void) /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = { - 0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, - 0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, - 0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, - 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, - 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, + 0x80u, 0x42u, 0x00u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x20u, 0x7Fu, 0x39u, 0x80u, 0x06u, 0x00u, 0xC6u, 0x9Fu, 0x00u, + 0x90u, 0xC6u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x5Eu, 0x00u, 0x77u, 0x60u, 0x08u, 0xC0u, 0x46u, 0x02u, 0x80u, + 0xC0u, 0x00u, 0x01u, 0x00u, 0xC0u, 0xC2u, 0x08u, 0x04u, 0xC0u, 0x80u, 0x04u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0xFFu, 0x80u, 0x00u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x40u, 0x40u, + 0x26u, 0x03u, 0x50u, 0x00u, 0x04u, 0xDCu, 0xF0u, 0xBEu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 25148f4..0765235 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -3,6 +3,34 @@ .include "cydevicegnu.inc" .include "cydevicegnu_trm.inc" +/* SCSI_CMD_TIMER_TimerHW */ +.set SCSI_CMD_TIMER_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set SCSI_CMD_TIMER_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set SCSI_CMD_TIMER_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set SCSI_CMD_TIMER_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set SCSI_CMD_TIMER_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set SCSI_CMD_TIMER_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set SCSI_CMD_TIMER_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set SCSI_CMD_TIMER_TimerHW__PER0, CYREG_TMR0_PER0 +.set SCSI_CMD_TIMER_TimerHW__PER1, CYREG_TMR0_PER1 +.set SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK, 0x01 +.set SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK, 0x01 +.set SCSI_CMD_TIMER_TimerHW__RT0, CYREG_TMR0_RT0 +.set SCSI_CMD_TIMER_TimerHW__RT1, CYREG_TMR0_RT1 +.set SCSI_CMD_TIMER_TimerHW__SR0, CYREG_TMR0_SR0 + +/* SCSI_CMD_TIMER_ISR */ +.set SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_CMD_TIMER_ISR__INTC_MASK, 0x01 +.set SCSI_CMD_TIMER_ISR__INTC_NUMBER, 0 +.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + /* USBFS_bus_reset */ .set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 @@ -504,8 +532,8 @@ .set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL .set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK .set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -513,13 +541,13 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -529,9 +557,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0 @@ -565,24 +593,24 @@ /* SCSI_CTL_IO */ .set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL .set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL /* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG @@ -1041,8 +1069,8 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1050,76 +1078,80 @@ .set scsiTarget_StatusReg__3__MASK, 0x08 .set scsiTarget_StatusReg__3__POS, 3 .set scsiTarget_StatusReg__MASK, 0x0F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1134,20 +1166,20 @@ /* USBFS_ep_1 */ .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x01 -.set USBFS_ep_1__INTC_NUMBER, 0 +.set USBFS_ep_1__INTC_MASK, 0x02 +.set USBFS_ep_1__INTC_NUMBER, 1 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x02 -.set USBFS_ep_2__INTC_NUMBER, 1 +.set USBFS_ep_2__INTC_MASK, 0x04 +.set USBFS_ep_2__INTC_NUMBER, 2 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2722,7 +2754,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x1000 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x00000000 +.set CYDEV_INTR_RISING, 0x00000001 .set CYDEV_PROJ_TYPE, 2 .set CYDEV_PROJ_TYPE_BOOTLOADER, 1 .set CYDEV_PROJ_TYPE_LOADABLE, 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 9483441..7e0fb10 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -3,6 +3,34 @@ INCLUDE cydeviceiar.inc INCLUDE cydeviceiar_trm.inc +/* SCSI_CMD_TIMER_TimerHW */ +SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0 +SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1 +SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01 +SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01 +SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0 +SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1 +SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +/* SCSI_CMD_TIMER_ISR */ +SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01 +SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0 +SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + /* USBFS_bus_reset */ USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -504,8 +532,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -513,13 +541,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -529,9 +557,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 @@ -565,24 +593,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_IO */ SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL /* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1041,8 +1069,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1050,76 +1078,80 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL /* SD_Clk_Ctl */ SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1134,20 +1166,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_1 */ USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x01 -USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_MASK EQU 0x02 +USBFS_ep_1__INTC_NUMBER EQU 1 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* USBFS_ep_2 */ USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x02 -USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_MASK EQU 0x04 +USBFS_ep_2__INTC_NUMBER EQU 2 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2722,7 +2754,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x1000 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_INTR_RISING EQU 0x00000001 CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index d206801..257ff86 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -3,6 +3,34 @@ INCLUDED_CYFITTERRV_INC EQU 1 GET cydevicerv.inc GET cydevicerv_trm.inc +; SCSI_CMD_TIMER_TimerHW +SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0 +SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1 +SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01 +SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01 +SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0 +SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1 +SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +; SCSI_CMD_TIMER_ISR +SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01 +SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0 +SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + ; USBFS_bus_reset USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 @@ -504,8 +532,8 @@ SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -513,13 +541,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -529,9 +557,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 @@ -565,24 +593,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_IO SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL ; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1041,8 +1069,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1050,76 +1078,80 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL ; SD_Clk_Ctl SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1134,20 +1166,20 @@ USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_1 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x01 -USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_MASK EQU 0x02 +USBFS_ep_1__INTC_NUMBER EQU 1 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; USBFS_ep_2 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x02 -USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_MASK EQU 0x04 +USBFS_ep_2__INTC_NUMBER EQU 2 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2722,7 +2754,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x1000 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_INTR_RISING EQU 0x00000001 CYDEV_PROJ_TYPE EQU 2 CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 CYDEV_PROJ_TYPE_LOADABLE EQU 2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index 92a14ac..1252396 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -58,6 +58,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx index ad440cf..4575072 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,12 +1,79 @@ - - + + + - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -87,31 +154,24 @@ - - - - - - - - - - - + + + - + - - - - + + + + - + + \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index 99bdf8a..f94969f 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj index 63786d6..2ee5808 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2318,6 +2318,75 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd index 6c18cab..ac6018c 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd @@ -6,6 +6,298 @@ 8 32 + + SCSI_CMD_TIMER + No description available + 0x400043A3 + + 0 + 0xB64 + registers + + + + SCSI_CMD_TIMER_GLOBAL_ENABLE + PM.ACT.CFG + 0x0 + 8 + read-write + 0 + 0 + + + en_timer + Enable timer/counters. + 0 + 3 + read-write + + + + + SCSI_CMD_TIMER_CONTROL + TMRx.CFG0 + 0xB5D + 8 + read-write + 0 + 0 + + + EN + Enables timer/comparator. + 0 + 0 + read-write + + + MODE + Mode. (0 = Timer; 1 = Comparator) + 1 + 1 + read-write + + + Timer + Timer mode. CNT/CMP register holds timer count value. + 0 + + + Comparator + Comparator mode. CNT/CMP register holds comparator threshold value. + 1 + + + + + ONESHOT + Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. + 2 + 2 + read-write + + + CMP_BUFF + Buffer compare register. Compare register updates only on timer terminal count. + 3 + 3 + read-write + + + INV + Invert sense of TIMEREN signal + 4 + 4 + read-write + + + DB + Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. + 5 + 5 + read-write + + + Timer + CMP and TC are output. + 0 + + + Deadband + PHI1 (instead of CMP) and PHI2 (instead of TC) are output. + 1 + + + + + DEADBAND_PERIOD + Deadband Period + 6 + 7 + read-write + + + + + SCSI_CMD_TIMER_CONTROL2 + TMRx.CFG1 + 0xB5E + 8 + read-write + 0 + 0 + + + IRQ_SEL + Irq selection. (0 = raw interrupts; 1 = status register interrupts) + 0 + 0 + read-write + + + FTC + First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + 1 + 1 + read-write + + + Disable_FTC + Disable the single cycle pulse, which signifies the timer is starting. + 0 + + + Enable_FTC + Enable the single cycle pulse, which signifies the timer is starting. + 1 + + + + + DCOR + Disable Clear on Read (DCOR) of Status Register SR0. + 2 + 2 + read-write + + + DBMODE + Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + 3 + 3 + read-write + + + CLK_BUS_EN_SEL + Digital Global Clock selection. + 4 + 6 + read-write + + + BUS_CLK_SEL + Bus Clock selection. + 7 + 7 + read-write + + + + + SCSI_CMD_TIMER_CONTROL3_ + TMRx.CFG2 + 0xB5F + 8 + read-write + 0 + 0 + + + TMR_CFG + Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ + 0 + 1 + read-write + + + Continuous + Timer runs while EN bit of CFG0 register is set to '1'. + 0 + + + Pulsewidth + Timer runs from positive to negative edge of TIMEREN. + 1 + + + Period + Timer runs from positive to positive edge of TIMEREN. + 2 + + + Irq + Timer runs until IRQ. + 3 + + + + + COD + Clear On Disable (COD). Clears or gates outputs to zero. + 2 + 2 + read-write + + + ROD + Reset On Disable (ROD). Resets internal state of output logic + 3 + 3 + read-write + + + CMP_CFG + Comparator configurations + 4 + 6 + read-write + + + Equal + Compare Equal + 0 + + + Less_than + Compare Less Than + 1 + + + Less_than_or_equal + Compare Less Than or Equal . + 2 + + + Greater + Compare Greater Than . + 3 + + + Greater_than_or_equal + Compare Greater Than or Equal + 4 + + + + + HW_EN + When set Timer Enable controls counting. + 7 + 7 + read-write + + + + + SCSI_CMD_TIMER_PERIOD + TMRx.PER0 - Assigned Period + 0xB61 + 16 + read-write + 0 + 0 + + + SCSI_CMD_TIMER_COUNTER + TMRx.CNT_CMP0 - Current Down Counter Value + 0xB63 + 16 + read-write + 0 + 0 + + + USBFS USBFS @@ -493,7 +785,7 @@ SD_Clk_Ctl No description available - 0x4000647A + 0x4000647C 0 0x1 @@ -514,7 +806,7 @@ SCSI_CTL_IO No description available - 0x4000647B + 0x40006471 0 0x1 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index e342d20..e5117e8 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c index bc8d848..2dbcd36 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c @@ -46,18 +46,23 @@ static void process_Command(void); static void doReserveRelease(void); +static uint8_t CmdTimerComplete = 0; +CY_ISR(CommandTimerISR) +{ + CmdTimerComplete = 1; +} + static void enter_BusFree() { - // TODO MPC3000 testing. + // Spin until the 10us timer has stopped. + // Required for Akai MPC3000, and possibly other broken controllers. // 1,2us: Cannot see SCSI device. // 5us: Can see SCSI device, format fails // 10us: Format succeeds. // 25us: Format fails. - CyDelayUs(10); - - - - + while (!CmdTimerComplete) {} + SCSI_CMD_TIMER_Stop(); + SCSI_ClearPin(SCSI_Out_BSY); // We now have a Bus Clear Delay of 800ns to release remaining signals. SCSI_ClearPin(SCSI_Out_MSG); @@ -406,6 +411,8 @@ static void scsiReset() scsiDev.sense.code = NO_SENSE; scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; scsiDiskReset(); + + SCSI_CMD_TIMER_Stop(); // Sleep to allow the bus to settle down a bit. // We must be ready again within the "Reset to selection time" of @@ -461,6 +468,11 @@ static void process_SelectionPhase() // for our BSY response, which is actually a very generous 250ms) SCSI_SetPin(SCSI_Out_BSY); ledOn(); + + // Used in enter_BusFree() to ensure each command takes at least 10us. + // as required by some old SCSI controllers (MPC3000). + CmdTimerComplete = 0; + SCSI_CMD_TIMER_Enable(); #ifdef MM_DEBUG scsiDev.selCount++; @@ -759,6 +771,9 @@ void scsiPoll(void) void scsiInit() { + SCSI_CMD_TIMER_Init(); // config but don't start the timeout counter + SCSI_CMD_TIMER_ISR_StartEx(CommandTimerISR); // setup timer interrupt sub-routine + scsiDev.scsiIdMask = 1 << (config->scsiId); scsiDev.atnFlag = 0; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h index 9677a58..3e72396 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h @@ -28,7 +28,7 @@ // Set this to true to log SCSI commands and status information via // USB HID packets. The can be captured and viewed in wireshark. // For windows users, capture using USBPcap http://desowin.org/usbpcap/ -#define MM_DEBUG 0 +#define MM_DEBUG 1 #include "geometry.h" #include "sense.h"