From: Michael McMaster <michael@codesrc.com>
Date: Sat, 20 May 2017 03:39:22 +0000 (+1000)
Subject: Save a cycle in fpga memory interface
X-Git-Tag: v6.1.1
X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=a10bf7d77c415169daa94fdd028a4533dc2bc31f;p=SCSI2SD-V6.git

Save a cycle in fpga memory interface
---

diff --git a/CHANGELOG b/CHANGELOG
index 92cf01db..6af0a610 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,4 +1,5 @@
-201705XX		6.1.1
+20170520		6.1.1
+	- Performance improvements to improve throughput at all scsi speeds
 	- Add new "turbo" speed option to boost speeds.
 		- May not be reliable, and use is not supported.
 		- Async timings trimmed
diff --git a/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c b/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
index 8a7bf907..1e200f7c 100755
--- a/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
+++ b/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
@@ -71,8 +71,15 @@ void MX_FSMC_Init(void)
   Timing.AddressSetupTime = 2;
   Timing.AddressHoldTime = 1;
 
-  // 1 for synchroniser skew, 1 to skip hold time, 1 to process read, 1 to output
-  Timing.DataSetupTime = 5;//4 doesn't work ? ?? ?
+  // Writes to device:
+  //   1 for synchroniser skew (dbx also delayed)
+  //   1 to skip hold time
+  //   1 to write data.
+
+  // Reads from device:
+  //   3 for syncroniser
+  //   1 to write back to fsmc bus.
+  Timing.DataSetupTime = 4;
 
   // Allow a clock for us to release signals, plus 3 for the synchroniser to
   // realise the cycle has ended. Need to avoid both devices acting as outputs
diff --git a/rtl/fpga_bitmap.o b/rtl/fpga_bitmap.o
index c535bdbd..aa8447bf 100644
Binary files a/rtl/fpga_bitmap.o and b/rtl/fpga_bitmap.o differ
diff --git a/src/firmware/scsiPhy.c b/src/firmware/scsiPhy.c
index 58d56f66..d0e70028 100755
--- a/src/firmware/scsiPhy.c
+++ b/src/firmware/scsiPhy.c
@@ -594,7 +594,7 @@ void scsiPhyReset()
 	scsiSetDefaultTiming();
 
 	// DMA Benchmark code
-	// Currently 11MB/s.
+	// Currently 14.9MB/s.
 	#ifdef DMA_BENCHMARK
 	while(1)
 	{
@@ -770,8 +770,11 @@ int scsiSelfTest()
 		return 32;
 	}
 	*SCSI_CTRL_BSY = 1;
+	s2s_delay_ms(1);
 	if (! scsiStatusBSY())
 	{
+		*SCSI_CTRL_BSY = 0;
+
 		// Error, BSY doesn't work.
 		return 32;
 	}
@@ -851,7 +854,6 @@ int scsiSelfTest()
 	}
 	*/
 
-
 	// FPGA comms test code
 	for(i = 0; i < 10000; ++i)
 	{