From: Michael McMaster Date: Fri, 23 Apr 2021 11:39:48 +0000 (+1000) Subject: Fix up SCSI timing and data corruption on 2021 boards X-Git-Tag: v6.4.1~1 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=a456251eb67af8f0e842bea7b45c105509170845;p=SCSI2SD-V6.git Fix up SCSI timing and data corruption on 2021 boards --- diff --git a/src/firmware/config.c b/src/firmware/config.c index 564d5694..e75be816 100755 --- a/src/firmware/config.c +++ b/src/firmware/config.c @@ -36,7 +36,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0640; +static const uint16_t FIRMWARE_VERSION = 0x0641; // Optional static config extern uint8_t* __fixed_config; diff --git a/src/firmware/disk.c b/src/firmware/disk.c index cdd7c45e..72cfeda9 100755 --- a/src/firmware/disk.c +++ b/src/firmware/disk.c @@ -739,6 +739,12 @@ void scsiDiskPoll() int enableParity = scsiDev.boardCfg.flags & S2S_CFG_ENABLE_PARITY; uint32_t maxSectors = sizeof(scsiDev.data) / SD_SECTOR_SIZE; + #ifdef STM32F4xx + // TODO fix this hack + // corruption occurs with 65536 byte transfers but not 32768 + // works fine on STM32F2 (or at least it did with older firmware ? + if (maxSectors > 64) maxSectors = 64; + #endif static_assert(SCSI_XFER_MAX >= sizeof(scsiDev.data), "Assumes SCSI_XFER_MAX >= sizeof(scsiDev.data)"); diff --git a/src/firmware/scsiPhy.c b/src/firmware/scsiPhy.c index 2f925fff..b90fd6c6 100755 --- a/src/firmware/scsiPhy.c +++ b/src/firmware/scsiPhy.c @@ -37,75 +37,19 @@ #include -static uint8_t asyncTimings[][4] = -{ -/* Speed, Assert, Deskew, Hold, Glitch */ -{/*1.5MB/s*/ 28, 18, 7, 15}, -//{/*1.5MB/s*/ 63, 31, 7, 15}, -{/*3.3MB/s*/ 13, 6, 6, 13}, -{/*5MB/s*/ 9, 6, 6, 6}, // 80ns -{/*safe*/ 3, 6, 6, 6}, // Probably safe -{/*turbo*/ 3, 3, 3, 2} -}; - #define SCSI_ASYNC_15 0 #define SCSI_ASYNC_33 1 #define SCSI_ASYNC_50 2 #define SCSI_ASYNC_SAFE 3 #define SCSI_ASYNC_TURBO 4 -// 5MB/s synchronous timing -#define SCSI_FAST5_DESKEW 6 // 55ns -#define SCSI_FAST5_HOLD 6 // 53ns - -// 10MB/s synchronous timing -// 2:0 Deskew count, 25ns -// 6:4 Hold count, 33ns -// 3:0 Assertion count, 30ns -// We want deskew + hold + assert + 3 to add up to 11 clocks -// the fpga code has 1 clock of overhead when transitioning from deskew to -// assert to hold - -#define SCSI_FAST10_DESKEW 2 // 25ns -#define SCSI_FAST10_HOLD 3 // 33ns -#define SCSI_FAST10_WRITE_ASSERT 3 // 30ns. Overall clocks only works if fpga overhead is 3. - -// Slow down the cycle to be valid. 2x assert period is TOO FAST when -// reading data. It's ok when writing due to the deskew. -// 50ns. ie. 100ns / 2. Rounded down because there's likely a few extra cycles -// here and there. -#define SCSI_FAST10_READ_ASSERT 5 - -// Fastest possible timing, probably not 20MB/s -#define SCSI_FAST20_DESKEW 1 -#define SCSI_FAST20_HOLD 2 -#define SCSI_FAST20_ASSERT 2 - - -#define syncDeskew(period) ((period) < 35 ? \ - SCSI_FAST10_DESKEW : SCSI_FAST5_DESKEW) - -#define syncHold(period) ((period) < 35 ? \ - ((period) == 25 ? SCSI_FAST10_HOLD : 4) /* 25ns/33ns */\ - : SCSI_FAST5_HOLD) - - -// Number of overhead cycles per period. -#define FPGA_OVERHEAD 2 -#define FPGA_CYCLES_PER_NS 9 -#define SCSI_PERIOD_CLKS(period) ((((int)period * 4) + (FPGA_CYCLES_PER_NS/2)) / FPGA_CYCLES_PER_NS) - -// 3.125MB/s (80 period) to < 10MB/s sync -// Assumes a 108MHz fpga clock. (9 ns) -// 3:0 Assertion count, variable -#define syncAssertionWrite(period,deskew) ((SCSI_PERIOD_CLKS(period) - deskew - FPGA_OVERHEAD + 1) / 2) -#define syncAssertionRead(period) syncAssertionWrite(period,0) - +#ifdef STM32F2xx +#include "scsiPhyTiming108MHz.h" +#endif -// Time until we consider ourselves selected -// 400ns at 108MHz -#define SCSI_DEFAULT_SELECTION 43 -#define SCSI_FAST_SELECTION 5 +#ifdef STM32F4xx +#include "scsiPhyTiming90MHz.h" +#endif // Private DMA variables. static int dmaInProgress = 0; diff --git a/src/firmware/scsiPhyTiming108MHz.h b/src/firmware/scsiPhyTiming108MHz.h new file mode 100755 index 00000000..9fa90192 --- /dev/null +++ b/src/firmware/scsiPhyTiming108MHz.h @@ -0,0 +1,87 @@ +// Copyright (C) 2021 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#ifndef S2S_SCSIPHYTIMING + +// Timing at a 108MHz clock. + +static uint8_t asyncTimings[][4] = +{ +/* Speed, Assert, Deskew, Hold, Glitch */ +{/*1.5MB/s*/ 28, 18, 7, 15}, +//{/*1.5MB/s*/ 63, 31, 7, 15}, +{/*3.3MB/s*/ 13, 6, 6, 13}, +{/*5MB/s*/ 9, 6, 6, 6}, // 80ns +{/*safe*/ 3, 6, 6, 6}, // Probably safe +{/*turbo*/ 3, 3, 3, 2} +}; + +// 5MB/s synchronous timing +#define SCSI_FAST5_DESKEW 6 // 55ns +#define SCSI_FAST5_HOLD 6 // 53ns + +// 10MB/s synchronous timing +// 2:0 Deskew count, 25ns +// 6:4 Hold count, 33ns +// 3:0 Assertion count, 30ns +// We want deskew + hold + assert + 3 to add up to 11 clocks +// the fpga code has 1 clock of overhead when transitioning from deskew to +// assert to hold + +#define SCSI_FAST10_DESKEW 2 // 25ns +#define SCSI_FAST10_HOLD 3 // 33ns +#define SCSI_FAST10_WRITE_ASSERT 3 // 30ns. Overall clocks only works if fpga overhead is 3. + +// Slow down the cycle to be valid. 2x assert period is TOO FAST when +// reading data. It's ok when writing due to the deskew. +// 50ns. ie. 100ns / 2. Rounded down because there's likely a few extra cycles +// here and there. +#define SCSI_FAST10_READ_ASSERT 5 + +// Fastest possible timing, probably not 20MB/s +#define SCSI_FAST20_DESKEW 1 +#define SCSI_FAST20_HOLD 2 +#define SCSI_FAST20_ASSERT 2 + + +#define syncDeskew(period) ((period) < 35 ? \ + SCSI_FAST10_DESKEW : SCSI_FAST5_DESKEW) + +#define syncHold(period) ((period) < 35 ? \ + ((period) == 25 ? SCSI_FAST10_HOLD : 4) /* 25ns/33ns */\ + : SCSI_FAST5_HOLD) + + +// Number of overhead cycles per period. +#define FPGA_OVERHEAD 2 +#define FPGA_CYCLES_PER_NS 9 +#define SCSI_PERIOD_CLKS(period) ((((int)period * 4) + (FPGA_CYCLES_PER_NS/2)) / FPGA_CYCLES_PER_NS) + +// 3.125MB/s (80 period) to < 10MB/s sync +// Assumes a 108MHz fpga clock. (9 ns) +// 3:0 Assertion count, variable +#define syncAssertionWrite(period,deskew) ((SCSI_PERIOD_CLKS(period) - deskew - FPGA_OVERHEAD + 1) / 2) +#define syncAssertionRead(period) syncAssertionWrite(period,0) + + +// Time until we consider ourselves selected +// 400ns at 108MHz +#define SCSI_DEFAULT_SELECTION 43 +#define SCSI_FAST_SELECTION 5 + + +#endif // S2S_SCSIPHYTIMING diff --git a/src/firmware/scsiPhyTiming90MHz.h b/src/firmware/scsiPhyTiming90MHz.h new file mode 100755 index 00000000..d1ee2be0 --- /dev/null +++ b/src/firmware/scsiPhyTiming90MHz.h @@ -0,0 +1,85 @@ +// Copyright (C) 2021 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#ifndef S2S_SCSIPHYTIMING + +// Timing at a 90Hz clock. + +static uint8_t asyncTimings[][4] = +{ +/* Speed, Assert, Deskew, Hold, Glitch */ +{/*1.5MB/s*/ 23, 15, 6, 12}, +{/*3.3MB/s*/ 11, 5, 5, 11}, +{/*5MB/s*/ 8, 5, 5, 5}, // 80ns +{/*safe*/ 2, 5, 5, 5}, // Probably safe +{/*turbo*/ 2, 2, 2, 2} +}; + +// 5MB/s synchronous timing +#define SCSI_FAST5_DESKEW 5 // 55ns +#define SCSI_FAST5_HOLD 5 // 53ns + +// 10MB/s synchronous timing +// 2:0 Deskew count, 25ns +// 6:4 Hold count, 33ns +// 3:0 Assertion count, 30ns +// We want deskew + hold + assert + 3 to add up to 100ns +// the fpga code has 1 clock of overhead when transitioning from deskew to +// assert to hold + +#define SCSI_FAST10_DESKEW 2 // 25ns +#define SCSI_FAST10_HOLD 2 // 33ns +#define SCSI_FAST10_WRITE_ASSERT 2 // 30ns. Overall clocks only works if fpga overhead is 3. + +// Slow down the cycle to be valid. 2x assert period is TOO FAST when +// reading data. It's ok when writing due to the deskew. +// 50ns. ie. 100ns / 2. Rounded down because there's likely a few extra cycles +// here and there. +#define SCSI_FAST10_READ_ASSERT 4 + +// Fastest possible timing, probably not 20MB/s +#define SCSI_FAST20_DESKEW 1 +#define SCSI_FAST20_HOLD 2 +#define SCSI_FAST20_ASSERT 2 + + +#define syncDeskew(period) ((period) < 35 ? \ + SCSI_FAST10_DESKEW : SCSI_FAST5_DESKEW) + +#define syncHold(period) ((period) < 35 ? \ + ((period) == 25 ? SCSI_FAST10_HOLD : 3) /* 25ns/33ns */\ + : SCSI_FAST5_HOLD) + + +// Number of overhead cycles per period. +#define FPGA_OVERHEAD 2 +#define FPGA_CYCLES_PER_NS 8 +#define SCSI_PERIOD_CLKS(period) ((((int)period * 4) + (FPGA_CYCLES_PER_NS/2)) / FPGA_CYCLES_PER_NS) + +// 3.125MB/s (80 period) to < 10MB/s sync +// 3:0 Assertion count, variable +#define syncAssertionWrite(period,deskew) ((SCSI_PERIOD_CLKS(period) - deskew - FPGA_OVERHEAD + 1) / 2) +#define syncAssertionRead(period) syncAssertionWrite(period,0) + + +// Time until we consider ourselves selected +// 400ns +#define SCSI_DEFAULT_SELECTION 36 +#define SCSI_FAST_SELECTION 4 + + +#endif // S2S_SCSIPHYTIMING