From: Michael McMaster Date: Sun, 31 Jan 2021 02:13:38 +0000 (+1000) Subject: SPI Flash DMA support X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=c6d35e2a72fbe68ed6e6ba49dbd4d6bc90ef613b;p=SCSI2SD.git SPI Flash DMA support --- diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 8f3a367..540d098 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -566,6 +566,9 @@ void scsiDiskPoll() int i = 0; int scsiActive = 0; int sdActive = 0; + + int isSDDevice = scsiDev.target->cfg->storageDevice == CONFIG_STOREDEVICE_SD; + while ((i < totalSDSectors) && likely(scsiDev.phase == DATA_IN) && likely(!scsiDev.resetFlag)) @@ -587,11 +590,23 @@ void scsiDiskPoll() CyExitCriticalSection(intr); } - if (sdActive && !sdBusy && sdReadSectorDMAPoll()) - { - sdActive = 0; - prep++; - } + if (isSDDevice) + { + if (sdActive && !sdBusy && sdReadSectorDMAPoll()) + { + sdActive = 0; + prep++; + } + } + else + { + S2S_Device* device = scsiDev.target->device; + if (sdActive && device->readAsyncPoll(device)) + { + sdActive = 0; + prep++; + } + } // Usually SD is slower than the SCSI interface. // Prioritise starting the read of the next sector over starting a @@ -601,7 +616,7 @@ void scsiDiskPoll() (prep - i < buffers) && (prep < totalSDSectors)) { - if (scsiDev.target->cfg->storageDevice == CONFIG_STOREDEVICE_SD) + if (isSDDevice) { // Start an SD transfer if we have space. if (transfer.multiBlock) @@ -618,8 +633,8 @@ void scsiDiskPoll() { // Sync Read onboard flash S2S_Device* device = scsiDev.target->device; - device->read(device, sdLBA + prep, 1, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); - prep++; + device->readAsync(device, sdLBA + prep, 1, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); + sdActive = 1; } } @@ -645,6 +660,15 @@ void scsiDiskPoll() scsiDev.phase = STATUS; } scsiDiskReset(); + + // Wait for current DMA transfer done then deselect (if reset encountered) + if (!isSDDevice) + { + S2S_Device* device = scsiDev.target->device; + while (!device->readAsyncPoll(device)) + { + } + } } else if (scsiDev.phase == DATA_OUT && transfer.currentBlock != transfer.blocks) diff --git a/software/SCSI2SD/src/flash.c b/software/SCSI2SD/src/flash.c index fea5bf7..0e8783c 100644 --- a/software/SCSI2SD/src/flash.c +++ b/software/SCSI2SD/src/flash.c @@ -45,6 +45,8 @@ static int spiFlash_pollMediaChange(S2S_Device* dev); static void spiFlash_pollMediaBusy(S2S_Device* dev); static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count); static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static int spiFlash_readAsyncPoll(S2S_Device* dev); static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); SpiFlash spiFlash = { @@ -57,6 +59,8 @@ SpiFlash spiFlash = { spiFlash_pollMediaBusy, spiFlash_erase, spiFlash_read, + spiFlash_readAsync, + spiFlash_readAsyncPoll, spiFlash_write, 0, // initial mediaState CONFIG_STOREDEVICE_FLASH @@ -65,6 +69,32 @@ SpiFlash spiFlash = { S2S_Device* spiFlashDevice = &(spiFlash.dev); +// Private DMA variables. +static uint8 spiFlashDMARxChan = CY_DMA_INVALID_CHANNEL; +static uint8 spiFlashDMATxChan = CY_DMA_INVALID_CHANNEL; +static uint8_t spiFlashDmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD }; +static uint8_t spiFlashDmaTxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD }; + +// Source of dummy SPI bytes for DMA +static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF}; +// Dummy location for DMA to sink usless data to +static uint8 discardBuffer[2] __attribute__((aligned(4))); + + +volatile uint8_t spiFlashRxDMAComplete = 1; +volatile uint8_t spiFlashTxDMAComplete = 1; + +CY_ISR_PROTO(spiFlashRxISR); +CY_ISR(spiFlashRxISR) +{ + spiFlashRxDMAComplete = 1; +} +CY_ISR_PROTO(spiFlashTxISR); +CY_ISR(spiFlashTxISR) +{ + spiFlashTxDMAComplete = 1; +} + // Read and write 1 byte. static uint8_t spiFlashByte(uint8_t value) { @@ -94,6 +124,35 @@ static void spiFlash_earlyInit(S2S_Device* dev) // Don't require the host to send us a START STOP UNIT command spiFlash->dev.mediaState = MEDIA_STARTED; + + // DMA stuff + spiFlashDMATxChan = + NOR_TX_DMA_DmaInitialize( + 2, // Bytes per burst + 1, // request per burst + HI16(CYDEV_SRAM_BASE), + HI16(CYDEV_PERIPH_BASE) + ); + + spiFlashDMARxChan = + NOR_RX_DMA_DmaInitialize( + 1, // Bytes per burst + 1, // request per burst + HI16(CYDEV_PERIPH_BASE), + HI16(CYDEV_SRAM_BASE) + ); + + CyDmaChDisable(spiFlashDMATxChan); + CyDmaChDisable(spiFlashDMARxChan); + + NOR_RX_DMA_COMPLETE_StartEx(spiFlashRxISR); + NOR_TX_DMA_COMPLETE_StartEx(spiFlashTxISR); + + spiFlashDmaRxTd[0] = CyDmaTdAllocate(); + spiFlashDmaRxTd[1] = CyDmaTdAllocate(); + + spiFlashDmaTxTd[0] = CyDmaTdAllocate(); + spiFlashDmaTxTd[1] = CyDmaTdAllocate(); } static void spiFlash_init(S2S_Device* dev) @@ -283,7 +342,7 @@ static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count spiFlashByte(linearAddress >> 16); spiFlashByte(linearAddress >> 8); spiFlashByte(linearAddress); - + // There's no harm in reading -extra- data, so keep the FIFO // one step ahead. NOR_SPI_WriteTxData(0xFF); @@ -305,7 +364,90 @@ static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {} NOR_SPI_ReadRxData(); } - + nNOR_CS_Write(1); // Deselect } +static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + nNOR_CS_Write(0); // Select + spiFlashByte(0x13); + + uint32_t linearAddress = sectorNumber * 512; + + // DMA implementation + // send is static as the address must remain consistent for the static + // DMA descriptors to work. + // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel. + static uint8_t send[4] __attribute__((aligned(4))); + send[0] = linearAddress >> 24; + send[1] = linearAddress >> 16; + send[2] = linearAddress >> 8; + send[3] = linearAddress; + + // Prepare DMA transfer + CyDmaTdSetConfiguration(spiFlashDmaTxTd[0], sizeof(send), spiFlashDmaTxTd[1], TD_INC_SRC_ADR); + CyDmaTdSetAddress(spiFlashDmaTxTd[0], LO16((uint32)&send), LO16((uint32)NOR_SPI_TXDATA_PTR)); + + CyDmaTdSetConfiguration( + spiFlashDmaTxTd[1], + count * 512, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + NOR_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + CyDmaTdSetAddress( + spiFlashDmaTxTd[1], + LO16((uint32)&dummyBuffer), + LO16((uint32)NOR_SPI_TXDATA_PTR)); + + CyDmaTdSetConfiguration(spiFlashDmaRxTd[0], sizeof(send), spiFlashDmaRxTd[1], 0); + CyDmaTdSetAddress(spiFlashDmaRxTd[0], LO16((uint32)NOR_SPI_RXDATA_PTR), LO16((uint32)&discardBuffer)); + + CyDmaTdSetConfiguration( + spiFlashDmaRxTd[1], + count * 512, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + TD_INC_DST_ADR | + NOR_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + + CyDmaTdSetAddress( + spiFlashDmaRxTd[1], + LO16((uint32)NOR_SPI_RXDATA_PTR), + LO16((uint32)buffer) + ); + + CyDmaChSetInitialTd(spiFlashDMATxChan, spiFlashDmaTxTd[0]); + CyDmaChSetInitialTd(spiFlashDMARxChan, spiFlashDmaRxTd[0]); + + // The DMA controller is a bit trigger-happy. It will retain + // a drq request that was triggered while the channel was + // disabled. + CyDmaChSetRequest(spiFlashDMATxChan, CY_DMA_CPU_REQ); + CyDmaClearPendingDrq(spiFlashDMARxChan); + + spiFlashTxDMAComplete = 0; + spiFlashRxDMAComplete = 0; + + CyDmaChEnable(spiFlashDMARxChan, 1); + CyDmaChEnable(spiFlashDMATxChan, 1); +} + +static int spiFlash_readAsyncPoll(S2S_Device* dev) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + int allComplete = 0; + uint8_t intr = CyEnterCriticalSection(); + allComplete = spiFlashTxDMAComplete && spiFlashRxDMAComplete; + CyExitCriticalSection(intr); + + if (allComplete) + { + nNOR_CS_Write(1); // Deselect + } + + return allComplete; +} \ No newline at end of file diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index 1eb563e..536318a 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -36,6 +36,8 @@ static int sd_pollMediaChange(S2S_Device* dev); static void sd_pollMediaBusy(S2S_Device* dev); static void sd_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count); static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static int sd_readAsyncPoll(S2S_Device* dev); static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); @@ -50,6 +52,8 @@ SdCard sdCard = { sd_pollMediaBusy, sd_erase, sd_read, + sd_readAsync, + sd_readAsyncPoll, sd_write, 0, // initial mediaState CONFIG_STOREDEVICE_SD @@ -1115,6 +1119,18 @@ static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint // TODO } +static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // TODO +} + + +static int sd_readAsyncPoll(S2S_Device* dev) +{ + return 1; +} + + static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) { // TODO diff --git a/software/SCSI2SD/src/storedevice.h b/software/SCSI2SD/src/storedevice.h index 4cd7735..e66c640 100644 --- a/software/SCSI2SD/src/storedevice.h +++ b/software/SCSI2SD/src/storedevice.h @@ -78,6 +78,8 @@ struct S2S_DeviceStruct void (*erase)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count); void (*read)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + void (*readAsync)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + int (*readAsyncPoll)(S2S_Device* dev); void (*write)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); MEDIA_STATE mediaState; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h index c0f90bd..53893b9 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h @@ -135,7 +135,7 @@ extern uint8 NOR_SPI_initVar; ***************************************/ #define NOR_SPI_INT_ON_SPI_DONE ((uint8) (0u << NOR_SPI_STS_SPI_DONE_SHIFT)) -#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (0u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT)) +#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (1u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT)) #define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \ NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT)) #define NOR_SPI_INT_ON_BYTE_COMP ((uint8) (0u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT)) @@ -154,7 +154,7 @@ extern uint8 NOR_SPI_initVar; #define NOR_SPI_INT_ON_RX_FULL ((uint8) (0u << \ NOR_SPI_STS_RX_FIFO_FULL_SHIFT)) -#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ +#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \ NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT)) #define NOR_SPI_INT_ON_RX_OVER ((uint8) (0u << \ NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT)) diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 2c4979a..c5ff31e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -192,34 +192,34 @@ #define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_MASK 0x200u +#define USBFS_ep_1__INTC_NUMBER 9u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_9 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_MASK 0x400u +#define USBFS_ep_2__INTC_NUMBER 10u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_10 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_MASK 0x800u +#define USBFS_ep_3__INTC_NUMBER 11u #define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_11 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_MASK 0x2000u +#define USBFS_ep_4__INTC_NUMBER 13u #define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_13 #define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -424,34 +424,34 @@ #define NOR_SO__SLW CYREG_PRT15_SLW /* SDCard */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -459,9 +459,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -485,8 +485,6 @@ #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -494,9 +492,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1 @@ -567,34 +565,34 @@ #define NOR_SCK__SLW CYREG_PRT3_SLW /* NOR_SPI */ -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_RxStsReg__4__POS 4 #define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u @@ -602,9 +600,9 @@ #define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u #define NOR_SPI_BSPIM_RxStsReg__6__POS 6 #define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u -#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK -#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST +#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST #define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 #define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 #define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 @@ -628,8 +626,8 @@ #define NOR_SPI_BSPIM_TxStsReg__0__POS 0 #define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u #define NOR_SPI_BSPIM_TxStsReg__1__POS 1 -#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u #define NOR_SPI_BSPIM_TxStsReg__2__POS 2 #define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u @@ -637,9 +635,9 @@ #define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_TxStsReg__4__POS 4 #define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu -#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB03_MSK -#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB03_ST +#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST /* SCSI_In */ #define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1 @@ -1760,15 +1758,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1781,15 +1779,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL @@ -2269,42 +2267,42 @@ #define NOR_Clock__PM_STBY_MSK 0x01u /* SD_RX_DMA */ -#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SD_RX_DMA__DRQ_NUMBER 2u +#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1 +#define SD_RX_DMA__DRQ_NUMBER 4u #define SD_RX_DMA__NUMBEROF_TDS 0u #define SD_RX_DMA__PRIORITY 0u #define SD_RX_DMA__TERMIN_EN 0u #define SD_RX_DMA__TERMIN_SEL 0u #define SD_RX_DMA__TERMOUT0_EN 1u -#define SD_RX_DMA__TERMOUT0_SEL 2u +#define SD_RX_DMA__TERMOUT0_SEL 4u #define SD_RX_DMA__TERMOUT1_EN 0u #define SD_RX_DMA__TERMOUT1_SEL 0u #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u -#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x80u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 7u #define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_7 #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SD_TX_DMA */ -#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SD_TX_DMA__DRQ_NUMBER 3u +#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1 +#define SD_TX_DMA__DRQ_NUMBER 5u #define SD_TX_DMA__NUMBEROF_TDS 0u #define SD_TX_DMA__PRIORITY 1u #define SD_TX_DMA__TERMIN_EN 0u #define SD_TX_DMA__TERMIN_SEL 0u #define SD_TX_DMA__TERMOUT0_EN 1u -#define SD_TX_DMA__TERMOUT0_SEL 3u +#define SD_TX_DMA__TERMOUT0_SEL 5u #define SD_TX_DMA__TERMOUT1_EN 0u #define SD_TX_DMA__TERMOUT1_SEL 0u #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u -#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x100u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 8u #define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_8 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2341,6 +2339,46 @@ #define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ #define nNOR_HOLD__SLW CYREG_PRT12_SLW +/* NOR_RX_DMA */ +#define NOR_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define NOR_RX_DMA__DRQ_NUMBER 0u +#define NOR_RX_DMA__NUMBEROF_TDS 0u +#define NOR_RX_DMA__PRIORITY 2u +#define NOR_RX_DMA__TERMIN_EN 0u +#define NOR_RX_DMA__TERMIN_SEL 0u +#define NOR_RX_DMA__TERMOUT0_EN 1u +#define NOR_RX_DMA__TERMOUT0_SEL 0u +#define NOR_RX_DMA__TERMOUT1_EN 0u +#define NOR_RX_DMA__TERMOUT1_SEL 0u +#define NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define NOR_RX_DMA_COMPLETE__INTC_MASK 0x02u +#define NOR_RX_DMA_COMPLETE__INTC_NUMBER 1u +#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* NOR_TX_DMA */ +#define NOR_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define NOR_TX_DMA__DRQ_NUMBER 1u +#define NOR_TX_DMA__NUMBEROF_TDS 0u +#define NOR_TX_DMA__PRIORITY 2u +#define NOR_TX_DMA__TERMIN_EN 0u +#define NOR_TX_DMA__TERMIN_SEL 0u +#define NOR_TX_DMA__TERMOUT0_EN 1u +#define NOR_TX_DMA__TERMOUT0_SEL 1u +#define NOR_TX_DMA__TERMOUT1_EN 0u +#define NOR_TX_DMA__TERMOUT1_SEL 0u +#define NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define NOR_TX_DMA_COMPLETE__INTC_MASK 0x04u +#define NOR_TX_DMA_COMPLETE__INTC_NUMBER 2u +#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + /* SCSI_Noise */ #define SCSI_Noise__0__AG CYREG_PRT4_AG #define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX @@ -2673,6 +2711,8 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2680,13 +2720,13 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST /* Debug_Timer */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2716,41 +2756,41 @@ /* SCSI_RX_DMA */ #define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__DRQ_NUMBER 2u #define SCSI_RX_DMA__NUMBEROF_TDS 0u #define SCSI_RX_DMA__PRIORITY 2u #define SCSI_RX_DMA__TERMIN_EN 0u #define SCSI_RX_DMA__TERMIN_SEL 0u #define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_SEL 2u #define SCSI_RX_DMA__TERMOUT1_EN 0u #define SCSI_RX_DMA__TERMOUT1_SEL 0u #define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 4u #define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 #define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA */ #define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__DRQ_NUMBER 3u #define SCSI_TX_DMA__NUMBEROF_TDS 0u #define SCSI_TX_DMA__PRIORITY 2u #define SCSI_TX_DMA__TERMIN_EN 0u #define SCSI_TX_DMA__TERMIN_SEL 0u #define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 3u #define SCSI_TX_DMA__TERMOUT1_EN 0u #define SCSI_TX_DMA__TERMOUT1_SEL 0u #define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x40u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 6u #define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6 #define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2779,20 +2819,20 @@ /* SCSI_RST_ISR */ #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x02u -#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_MASK 0x08u +#define SCSI_RST_ISR__INTC_NUMBER 3u #define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 #define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SCSI_SEL_ISR */ #define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_MASK 0x20u +#define SCSI_SEL_ISR__INTC_NUMBER 5u #define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_5 #define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2801,8 +2841,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2810,58 +2850,71 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK +#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U @@ -3019,7 +3072,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000007Fu +#define CYDEV_INTR_RISING 0x000001FFu #define CYDEV_IS_EXPORTING_CODE 0 #define CYDEV_IS_IMPORTING_CODE 0 #define CYDEV_PROJ_TYPE 2 @@ -3074,7 +3127,7 @@ #define CYIPBLOCK_S8_SAR_VERSION 0 #define CYIPBLOCK_S8_SIO_VERSION 0 #define CYIPBLOCK_S8_UDB_VERSION 0 -#define DMA_CHANNELS_USED__MASK0 0x0000000Fu +#define DMA_CHANNELS_USED__MASK0 0x0000003Fu #define CYDEV_BOOTLOADER_ENABLE 0 #endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 7ad20ba..17daa0e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -391,6 +391,14 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = { 0x00u, 0x03u, 0x00u, 0x00u}; + /* PHUB_CFGMEM4 Address: CYREG_PHUB_CFGMEM4_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM4_VAL[] = { + 0x00u, 0x04u, 0x00u, 0x00u}; + + /* PHUB_CFGMEM5 Address: CYREG_PHUB_CFGMEM5_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM5_VAL[] = { + 0x00u, 0x05u, 0x00u, 0x00u}; + #ifdef CYGlobalIntDisable /* Disable interrupts by default. Let user enable if/when they want. */ CYGlobalIntDisable @@ -413,105 +421,96 @@ void cyfitter_cfg(void) 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010041u, /* Base address: 0x40010000 Count: 65 */ + 0x4001003Du, /* Base address: 0x40010000 Count: 61 */ 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */ - 0x4001024Du, /* Base address: 0x40010200 Count: 77 */ - 0x40010348u, /* Base address: 0x40010300 Count: 72 */ - 0x40010418u, /* Base address: 0x40010400 Count: 24 */ + 0x4001025Au, /* Base address: 0x40010200 Count: 90 */ + 0x40010354u, /* Base address: 0x40010300 Count: 84 */ + 0x40010419u, /* Base address: 0x40010400 Count: 25 */ 0x40010556u, /* Base address: 0x40010500 Count: 86 */ - 0x4001064Fu, /* Base address: 0x40010600 Count: 79 */ - 0x40010751u, /* Base address: 0x40010700 Count: 81 */ - 0x40010848u, /* Base address: 0x40010800 Count: 72 */ - 0x40010955u, /* Base address: 0x40010900 Count: 85 */ - 0x40010A5Fu, /* Base address: 0x40010A00 Count: 95 */ - 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */ - 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */ - 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */ - 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */ - 0x40010F37u, /* Base address: 0x40010F00 Count: 55 */ - 0x4001141Au, /* Base address: 0x40011400 Count: 26 */ - 0x40011553u, /* Base address: 0x40011500 Count: 83 */ - 0x40011656u, /* Base address: 0x40011600 Count: 86 */ - 0x40011753u, /* Base address: 0x40011700 Count: 83 */ - 0x4001184Bu, /* Base address: 0x40011800 Count: 75 */ + 0x40010653u, /* Base address: 0x40010600 Count: 83 */ + 0x40010759u, /* Base address: 0x40010700 Count: 89 */ + 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */ + 0x4001095Eu, /* Base address: 0x40010900 Count: 94 */ + 0x40010A41u, /* Base address: 0x40010A00 Count: 65 */ + 0x40010B5Cu, /* Base address: 0x40010B00 Count: 92 */ + 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ + 0x40010D61u, /* Base address: 0x40010D00 Count: 97 */ + 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */ + 0x40010F41u, /* Base address: 0x40010F00 Count: 65 */ + 0x40011411u, /* Base address: 0x40011400 Count: 17 */ + 0x40011550u, /* Base address: 0x40011500 Count: 80 */ + 0x40011650u, /* Base address: 0x40011600 Count: 80 */ + 0x40011754u, /* Base address: 0x40011700 Count: 84 */ + 0x40011848u, /* Base address: 0x40011800 Count: 72 */ 0x40011954u, /* Base address: 0x40011900 Count: 84 */ - 0x40011A47u, /* Base address: 0x40011A00 Count: 71 */ - 0x40011B52u, /* Base address: 0x40011B00 Count: 82 */ - 0x4001401Au, /* Base address: 0x40014000 Count: 26 */ - 0x40014125u, /* Base address: 0x40014100 Count: 37 */ - 0x40014212u, /* Base address: 0x40014200 Count: 18 */ - 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */ - 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */ - 0x4001451Du, /* Base address: 0x40014500 Count: 29 */ - 0x40014611u, /* Base address: 0x40014600 Count: 17 */ - 0x40014716u, /* Base address: 0x40014700 Count: 22 */ - 0x4001480Fu, /* Base address: 0x40014800 Count: 15 */ - 0x4001491Au, /* Base address: 0x40014900 Count: 26 */ - 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */ - 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */ - 0x40015005u, /* Base address: 0x40015000 Count: 5 */ - 0x40015104u, /* Base address: 0x40015100 Count: 4 */ + 0x40011A4Eu, /* Base address: 0x40011A00 Count: 78 */ + 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */ + 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */ + 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */ + 0x40014218u, /* Base address: 0x40014200 Count: 24 */ + 0x40014312u, /* Base address: 0x40014300 Count: 18 */ + 0x40014412u, /* Base address: 0x40014400 Count: 18 */ + 0x40014515u, /* Base address: 0x40014500 Count: 21 */ + 0x4001460Du, /* Base address: 0x40014600 Count: 13 */ + 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */ + 0x40014817u, /* Base address: 0x40014800 Count: 23 */ + 0x40014914u, /* Base address: 0x40014900 Count: 20 */ + 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */ + 0x40014D07u, /* Base address: 0x40014D00 Count: 7 */ + 0x40015006u, /* Base address: 0x40015000 Count: 6 */ + 0x40015102u, /* Base address: 0x40015100 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x30u}, {0x0Au, 0x36u}, - {0x01u, 0x22u}, - {0x10u, 0xA8u}, - {0x11u, 0x2Au}, - {0x18u, 0x84u}, - {0x19u, 0x82u}, + {0x00u, 0x22u}, + {0x10u, 0x0Au}, + {0x11u, 0x88u}, + {0x18u, 0xC2u}, + {0x19u, 0x44u}, {0x1Cu, 0x08u}, - {0x20u, 0x02u}, - {0x21u, 0x03u}, - {0x30u, 0x84u}, - {0x60u, 0x02u}, + {0x20u, 0x01u}, + {0x31u, 0x84u}, + {0x60u, 0x20u}, + {0x61u, 0x22u}, {0x78u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, {0x84u, 0x0Fu}, {0x84u, 0x0Fu}, - {0x01u, 0x6Du}, - {0x02u, 0x20u}, - {0x05u, 0x12u}, - {0x06u, 0x03u}, - {0x07u, 0xE8u}, - {0x09u, 0x0Du}, - {0x0Bu, 0x60u}, - {0x0Du, 0x6Du}, - {0x11u, 0x71u}, - {0x12u, 0x24u}, - {0x13u, 0x82u}, - {0x14u, 0x24u}, - {0x15u, 0x02u}, - {0x16u, 0x09u}, - {0x17u, 0x0Du}, - {0x19u, 0x92u}, - {0x1Bu, 0x64u}, - {0x1Du, 0x20u}, - {0x1Eu, 0x18u}, - {0x21u, 0x40u}, - {0x22u, 0x04u}, - {0x24u, 0x24u}, - {0x26u, 0x12u}, - {0x28u, 0x40u}, - {0x29u, 0x2Du}, - {0x2Bu, 0x40u}, - {0x2Du, 0x6Du}, - {0x30u, 0x40u}, - {0x33u, 0x0Fu}, - {0x34u, 0x07u}, - {0x35u, 0xF0u}, - {0x36u, 0x38u}, - {0x39u, 0x20u}, - {0x3Bu, 0x08u}, - {0x3Eu, 0x01u}, - {0x40u, 0x13u}, + {0x01u, 0x06u}, + {0x02u, 0x03u}, + {0x05u, 0x02u}, + {0x06u, 0x04u}, + {0x07u, 0x01u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x24u}, + {0x0Fu, 0x04u}, + {0x10u, 0x24u}, + {0x11u, 0x08u}, + {0x12u, 0x09u}, + {0x19u, 0x08u}, + {0x1Au, 0x18u}, + {0x28u, 0x24u}, + {0x29u, 0x10u}, + {0x2Au, 0x12u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x20u}, + {0x2Fu, 0x02u}, + {0x30u, 0x07u}, + {0x31u, 0x07u}, + {0x33u, 0x10u}, + {0x34u, 0x38u}, + {0x35u, 0x08u}, + {0x39u, 0x22u}, + {0x3Fu, 0x04u}, + {0x40u, 0x46u}, {0x41u, 0x02u}, - {0x42u, 0x60u}, - {0x45u, 0x2Cu}, - {0x46u, 0xFDu}, + {0x42u, 0x50u}, + {0x45u, 0xDCu}, + {0x46u, 0x2Fu}, {0x47u, 0x0Eu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, @@ -532,1948 +531,1981 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0xADu, 0x01u}, + {0x96u, 0x01u}, + {0x97u, 0x01u}, + {0xAAu, 0x02u}, + {0xB2u, 0x01u}, {0xB3u, 0x01u}, - {0xBFu, 0x04u}, + {0xB4u, 0x02u}, + {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDCu, 0x22u}, {0xDFu, 0x01u}, - {0x00u, 0x06u}, - {0x08u, 0x0Au}, - {0x0Au, 0x01u}, - {0x10u, 0x80u}, - {0x11u, 0x28u}, - {0x18u, 0x04u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x81u}, - {0x20u, 0x08u}, - {0x21u, 0x20u}, - {0x22u, 0x14u}, - {0x23u, 0x04u}, - {0x24u, 0x20u}, - {0x29u, 0x42u}, - {0x2Au, 0x10u}, - {0x2Fu, 0x02u}, + {0x01u, 0x06u}, + {0x03u, 0x02u}, + {0x08u, 0x20u}, + {0x0Au, 0x44u}, + {0x0Eu, 0x20u}, + {0x11u, 0x40u}, + {0x12u, 0x08u}, + {0x17u, 0x10u}, + {0x19u, 0x02u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x10u}, + {0x1Fu, 0x10u}, + {0x21u, 0x11u}, + {0x22u, 0x02u}, + {0x23u, 0x20u}, + {0x25u, 0x04u}, + {0x27u, 0x10u}, + {0x29u, 0x20u}, + {0x2Bu, 0x01u}, {0x31u, 0x22u}, - {0x32u, 0x44u}, - {0x39u, 0x61u}, - {0x3Au, 0x04u}, - {0x40u, 0x0Au}, - {0x41u, 0x04u}, - {0x49u, 0x20u}, - {0x4Au, 0x90u}, - {0x4Bu, 0x02u}, - {0x51u, 0x80u}, - {0x52u, 0x48u}, - {0x53u, 0x20u}, - {0x58u, 0x04u}, - {0x59u, 0x01u}, - {0x5Au, 0x40u}, - {0x5Bu, 0x10u}, - {0x61u, 0x18u}, - {0x62u, 0x02u}, - {0x63u, 0x01u}, - {0x68u, 0x01u}, - {0x69u, 0x14u}, - {0x6Bu, 0x80u}, - {0x70u, 0x80u}, - {0x72u, 0x04u}, - {0x73u, 0x50u}, - {0x81u, 0x90u}, - {0x82u, 0x08u}, - {0x83u, 0x80u}, - {0x86u, 0x02u}, - {0x87u, 0x22u}, - {0x8Au, 0x10u}, - {0x8Du, 0x14u}, - {0x8Eu, 0x01u}, - {0xC0u, 0x0Cu}, - {0xC2u, 0x0Du}, - {0xC4u, 0x0Eu}, - {0xCAu, 0x1Du}, - {0xCCu, 0x0Fu}, - {0xCEu, 0x0Fu}, - {0xD0u, 0x0Eu}, - {0xD2u, 0x04u}, + {0x36u, 0x04u}, + {0x39u, 0x02u}, + {0x3Bu, 0x44u}, + {0x40u, 0x04u}, + {0x43u, 0x02u}, + {0x48u, 0x04u}, + {0x49u, 0x84u}, + {0x4Au, 0x88u}, + {0x52u, 0x10u}, + {0x53u, 0x68u}, + {0x58u, 0x12u}, + {0x59u, 0x08u}, + {0x5Au, 0x80u}, + {0x60u, 0x80u}, + {0x62u, 0x20u}, + {0x63u, 0x21u}, + {0x68u, 0x80u}, + {0x69u, 0x44u}, + {0x6Bu, 0x08u}, + {0x70u, 0x08u}, + {0x72u, 0x0Au}, + {0x73u, 0x80u}, + {0x81u, 0x04u}, + {0x84u, 0x02u}, + {0x86u, 0x88u}, + {0x87u, 0x80u}, + {0x8Au, 0x02u}, + {0x8Bu, 0x40u}, + {0x8Fu, 0x01u}, + {0xC0u, 0x0Du}, + {0xC2u, 0x2Au}, + {0xC4u, 0x43u}, + {0xCAu, 0x0Cu}, + {0xCCu, 0x45u}, + {0xCEu, 0x0Bu}, + {0xD0u, 0x05u}, + {0xD2u, 0x0Cu}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE0u, 0x05u}, - {0xE2u, 0x0Au}, + {0xE0u, 0x02u}, + {0xE2u, 0x08u}, {0xE4u, 0x09u}, - {0xE6u, 0x04u}, - {0x05u, 0x02u}, - {0x0Fu, 0x02u}, + {0xE6u, 0x82u}, + {0x01u, 0x1Cu}, + {0x04u, 0x01u}, + {0x05u, 0x14u}, + {0x06u, 0x02u}, + {0x07u, 0x08u}, + {0x08u, 0x02u}, + {0x09u, 0x24u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x10u}, + {0x0Du, 0x30u}, + {0x0Fu, 0x0Fu}, + {0x11u, 0x0Cu}, + {0x13u, 0x10u}, {0x14u, 0x02u}, - {0x16u, 0x05u}, - {0x17u, 0x02u}, - {0x18u, 0x02u}, - {0x1Au, 0x09u}, + {0x15u, 0x21u}, + {0x16u, 0x01u}, + {0x17u, 0x1Eu}, + {0x19u, 0x11u}, + {0x1Bu, 0x22u}, {0x1Cu, 0x02u}, - {0x1Eu, 0x01u}, + {0x1Eu, 0x05u}, {0x20u, 0x02u}, - {0x22u, 0x11u}, - {0x2Cu, 0x01u}, - {0x2Du, 0x01u}, - {0x2Eu, 0x02u}, - {0x30u, 0x03u}, - {0x31u, 0x02u}, - {0x32u, 0x10u}, - {0x34u, 0x04u}, + {0x21u, 0x1Cu}, + {0x22u, 0x09u}, + {0x29u, 0x10u}, + {0x2Bu, 0x0Cu}, + {0x2Du, 0x08u}, + {0x32u, 0x04u}, + {0x33u, 0x0Fu}, + {0x34u, 0x03u}, + {0x35u, 0x30u}, {0x36u, 0x08u}, - {0x37u, 0x01u}, - {0x3Au, 0x02u}, - {0x3Fu, 0x01u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x20u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x92u}, + {0x5Cu, 0x12u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x28u}, - {0x85u, 0x28u}, - {0x86u, 0xFFu}, - {0x88u, 0xC0u}, - {0x89u, 0x28u}, - {0x8Au, 0x08u}, - {0x8Cu, 0x1Fu}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x28u}, - {0x90u, 0x80u}, - {0x93u, 0x20u}, - {0x95u, 0x05u}, - {0x96u, 0x9Fu}, - {0x97u, 0x02u}, - {0x99u, 0x03u}, - {0x9Au, 0x60u}, + {0x81u, 0xC0u}, + {0x83u, 0x02u}, + {0x85u, 0x7Fu}, + {0x87u, 0x80u}, + {0x88u, 0x50u}, + {0x8Au, 0x0Cu}, + {0x8Bu, 0x60u}, + {0x8Cu, 0x5Cu}, + {0x8Fu, 0xFFu}, + {0x90u, 0x21u}, + {0x91u, 0x90u}, + {0x92u, 0x1Eu}, + {0x93u, 0x40u}, + {0x94u, 0x24u}, + {0x95u, 0xC0u}, + {0x96u, 0x10u}, + {0x97u, 0x08u}, + {0x98u, 0x30u}, + {0x99u, 0xC0u}, + {0x9Au, 0x0Fu}, {0x9Bu, 0x04u}, - {0x9Cu, 0xC0u}, - {0x9Du, 0x04u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0x03u}, - {0xA0u, 0xC0u}, - {0xA1u, 0x28u}, - {0xA2u, 0x02u}, - {0xA4u, 0xC0u}, - {0xA5u, 0x10u}, - {0xA6u, 0x04u}, - {0xA8u, 0x7Fu}, - {0xA9u, 0x10u}, - {0xAAu, 0x80u}, - {0xACu, 0x90u}, - {0xADu, 0x01u}, - {0xAEu, 0x40u}, - {0xAFu, 0x06u}, - {0xB1u, 0x08u}, - {0xB2u, 0xFFu}, - {0xB3u, 0x20u}, - {0xB5u, 0x10u}, - {0xB7u, 0x07u}, - {0xB9u, 0x20u}, - {0xBBu, 0x80u}, - {0xBEu, 0x04u}, - {0xBFu, 0x05u}, - {0xD4u, 0x09u}, + {0x9Cu, 0x5Cu}, + {0x9Du, 0xC0u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x11u}, + {0xA2u, 0x22u}, + {0xA3u, 0x9Fu}, + {0xA4u, 0x54u}, + {0xA5u, 0x80u}, + {0xA6u, 0x08u}, + {0xA8u, 0x08u}, + {0xACu, 0x0Cu}, + {0xADu, 0x1Fu}, + {0xAEu, 0x50u}, + {0xAFu, 0x20u}, + {0xB0u, 0x0Fu}, + {0xB2u, 0x30u}, + {0xB4u, 0x40u}, + {0xB5u, 0xFFu}, + {0xB6u, 0x40u}, + {0xBAu, 0x08u}, + {0xBEu, 0x50u}, + {0xBFu, 0x10u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x88u}, + {0x00u, 0x80u}, {0x03u, 0x04u}, - {0x09u, 0x20u}, - {0x0Au, 0x81u}, - {0x0Bu, 0x20u}, - {0x0Eu, 0x2Au}, - {0x10u, 0x20u}, - {0x11u, 0x41u}, - {0x12u, 0x18u}, - {0x14u, 0x01u}, + {0x04u, 0x14u}, + {0x06u, 0x20u}, + {0x09u, 0x80u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x44u}, + {0x0Eu, 0x12u}, + {0x10u, 0x22u}, + {0x12u, 0x44u}, {0x16u, 0x80u}, - {0x1Bu, 0x04u}, - {0x1Eu, 0x2Au}, - {0x1Fu, 0x02u}, - {0x20u, 0x20u}, + {0x18u, 0x40u}, + {0x19u, 0x14u}, + {0x1Au, 0x22u}, + {0x1Bu, 0x05u}, + {0x1Cu, 0x14u}, + {0x1Eu, 0x22u}, {0x21u, 0x20u}, - {0x22u, 0x83u}, - {0x27u, 0x41u}, - {0x29u, 0x80u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x14u}, - {0x2Cu, 0x01u}, - {0x2Fu, 0x02u}, - {0x30u, 0x02u}, - {0x32u, 0x98u}, - {0x36u, 0x08u}, - {0x39u, 0x69u}, - {0x3Cu, 0x80u}, - {0x3Fu, 0x04u}, - {0x59u, 0x14u}, - {0x5Au, 0x02u}, - {0x5Bu, 0x40u}, - {0x5Cu, 0x80u}, - {0x61u, 0x80u}, + {0x24u, 0x08u}, + {0x25u, 0x18u}, + {0x27u, 0x20u}, + {0x29u, 0x05u}, + {0x2Au, 0x40u}, + {0x2Bu, 0x01u}, + {0x2Du, 0x11u}, + {0x2Fu, 0x01u}, + {0x30u, 0x22u}, + {0x31u, 0x80u}, + {0x33u, 0x04u}, + {0x34u, 0x04u}, + {0x37u, 0x21u}, + {0x39u, 0x22u}, + {0x3Bu, 0x44u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x46u}, + {0x58u, 0x40u}, + {0x5Du, 0x40u}, + {0x60u, 0x02u}, {0x66u, 0x80u}, - {0x83u, 0x01u}, - {0x87u, 0x01u}, - {0x8Bu, 0x01u}, - {0x8Cu, 0x04u}, - {0x90u, 0x04u}, - {0x91u, 0x14u}, - {0x92u, 0x24u}, - {0x93u, 0x06u}, - {0x95u, 0x61u}, - {0x96u, 0xC0u}, - {0x97u, 0x01u}, - {0x9Au, 0x41u}, - {0x9Cu, 0x0Eu}, - {0x9Du, 0x63u}, - {0x9Eu, 0x14u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x04u}, + {0x82u, 0x20u}, + {0x89u, 0x02u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x02u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x02u}, + {0x91u, 0x20u}, + {0x92u, 0x10u}, + {0x93u, 0xA0u}, + {0x96u, 0x80u}, + {0x97u, 0x44u}, + {0x98u, 0x61u}, + {0x99u, 0x02u}, + {0x9Au, 0x18u}, + {0x9Du, 0xA0u}, + {0xA0u, 0x84u}, {0xA1u, 0x04u}, - {0xA3u, 0x81u}, - {0xA5u, 0x0Au}, - {0xA8u, 0x10u}, - {0xADu, 0x04u}, - {0xB2u, 0x80u}, - {0xB3u, 0x50u}, - {0xB5u, 0x20u}, - {0xB7u, 0x20u}, - {0xC0u, 0x07u}, - {0xC2u, 0xEFu}, - {0xC4u, 0x9Fu}, - {0xCAu, 0x1Fu}, - {0xCCu, 0x4Fu}, - {0xCEu, 0x5Fu}, - {0xD6u, 0x1Fu}, + {0xA2u, 0x80u}, + {0xA3u, 0x08u}, + {0xA5u, 0x22u}, + {0xA6u, 0x34u}, + {0xA7u, 0x13u}, + {0xA8u, 0x80u}, + {0xA9u, 0x08u}, + {0xABu, 0x20u}, + {0xACu, 0x08u}, + {0xAFu, 0x08u}, + {0xB0u, 0x51u}, + {0xB2u, 0x02u}, + {0xB4u, 0x04u}, + {0xB6u, 0x40u}, + {0xB7u, 0x28u}, + {0xC0u, 0x63u}, + {0xC2u, 0xAFu}, + {0xC4u, 0x1Fu}, + {0xCAu, 0xBBu}, + {0xCCu, 0xEFu}, + {0xCEu, 0xFFu}, + {0xD6u, 0x18u}, {0xD8u, 0x18u}, - {0xE2u, 0x85u}, - {0xE6u, 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{0x10u, 0x0Du}, + {0x0Fu, 0x01u}, {0x11u, 0x02u}, {0x13u, 0x09u}, + {0x14u, 0x02u}, {0x15u, 0x02u}, + {0x16u, 0x04u}, {0x17u, 0x01u}, - {0x18u, 0x02u}, + {0x18u, 0x04u}, {0x19u, 0x01u}, - {0x1Au, 0x0Du}, + {0x1Au, 0x0Au}, {0x1Bu, 0x02u}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x04u}, - {0x20u, 0x0Du}, - {0x28u, 0x0Du}, - {0x2Cu, 0x0Du}, - {0x33u, 0x03u}, - {0x34u, 0x0Fu}, - {0x35u, 0x04u}, + {0x1Cu, 0x04u}, + {0x1Eu, 0x03u}, + {0x24u, 0x04u}, + {0x26u, 0x12u}, + {0x29u, 0x02u}, + {0x2Bu, 0x05u}, + {0x30u, 0x01u}, + {0x32u, 0x06u}, + {0x33u, 0x04u}, + {0x34u, 0x10u}, + {0x35u, 0x03u}, + {0x36u, 0x08u}, {0x37u, 0x08u}, - {0x3Au, 0x20u}, - {0x3Bu, 0x08u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x20u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x21u}, + {0x5Cu, 0x22u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x02u}, - {0x85u, 0x18u}, - {0x8Cu, 0x10u}, - {0x8Du, 0x05u}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x28u}, - {0x90u, 0x10u}, - {0x91u, 0x02u}, - {0x92u, 0x20u}, - {0x94u, 0x34u}, - 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{0x9Au, 0x40u}, - {0x9Fu, 0x20u}, - {0xA0u, 0x20u}, - {0xA1u, 0x04u}, - {0xA2u, 0x01u}, - {0xA4u, 0x40u}, - {0xA5u, 0x02u}, - {0xA6u, 0x28u}, - {0xA7u, 0x08u}, - {0xA8u, 0x10u}, - {0xA9u, 0x20u}, - {0xAFu, 0x50u}, - {0xB0u, 0x48u}, - {0xB1u, 0x08u}, - {0xB3u, 0x02u}, - {0xC0u, 0xE9u}, - {0xC2u, 0xDFu}, - {0xC4u, 0xDFu}, - {0xCAu, 0x0Cu}, - {0xCCu, 0xE7u}, - {0xCEu, 0x3Au}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x19u}, + {0x66u, 0x20u}, + {0x84u, 0x80u}, + {0x85u, 0x40u}, + {0x90u, 0x0Au}, + {0x91u, 0x70u}, + {0x92u, 0x07u}, + {0x93u, 0x11u}, + {0x94u, 0x84u}, + {0x95u, 0x02u}, + {0x96u, 0x40u}, + {0x97u, 0x4Eu}, + {0x98u, 0x20u}, + {0x99u, 0x06u}, + {0x9Au, 0x06u}, + {0x9Bu, 0x71u}, + {0x9Cu, 0x04u}, + {0x9Fu, 0x06u}, + {0xA0u, 0x10u}, + {0xA1u, 0x28u}, + {0xA3u, 0x8Du}, + {0xA4u, 0x62u}, + {0xA5u, 0x82u}, + {0xAAu, 0x01u}, + {0xABu, 0x10u}, + {0xACu, 0x81u}, + {0xAFu, 0x40u}, + {0xB1u, 0x40u}, + {0xB3u, 0x01u}, + {0xB4u, 0x80u}, + {0xC0u, 0x1Fu}, + {0xC2u, 0xE7u}, + {0xC4u, 0x2Bu}, + {0xCAu, 0x2Du}, + {0xCCu, 0xEDu}, + {0xCEu, 0x1Fu}, + {0xD6u, 0x3Fu}, + {0xD8u, 0x39u}, {0xE2u, 0x04u}, - {0xE4u, 0x40u}, - {0xE8u, 0x0Cu}, - {0xEAu, 0x01u}, - {0xECu, 0x02u}, - {0xEEu, 0x01u}, - {0x00u, 0x11u}, - {0x02u, 0x22u}, - {0x03u, 0x0Cu}, - {0x06u, 0xFFu}, - {0x07u, 0x10u}, - {0x08u, 0x0Fu}, - {0x09u, 0x01u}, - {0x0Au, 0xF0u}, - {0x0Cu, 0x21u}, - {0x0Eu, 0x12u}, - {0x0Fu, 0x10u}, - {0x12u, 0xFFu}, + {0xE4u, 0x08u}, + {0xE6u, 0x04u}, + {0xE8u, 0x08u}, + {0xEAu, 0x05u}, + {0xEEu, 0x09u}, + {0x00u, 0x04u}, + {0x01u, 0x01u}, + {0x03u, 0x02u}, + {0x05u, 0x04u}, + {0x06u, 0x20u}, + {0x07u, 0x08u}, + {0x09u, 0x10u}, + {0x0Au, 0x07u}, + {0x0Bu, 0x8Fu}, + {0x0Cu, 0x01u}, + {0x0Du, 0x0Fu}, + {0x0Fu, 0x80u}, + {0x11u, 0x01u}, {0x13u, 0x02u}, - {0x14u, 0x84u}, - {0x15u, 0x10u}, - {0x16u, 0x48u}, - {0x17u, 0x08u}, - {0x18u, 0xFFu}, - {0x19u, 0x01u}, - {0x20u, 0x33u}, - {0x22u, 0xCCu}, - {0x24u, 0x44u}, - {0x25u, 0x01u}, - {0x26u, 0x88u}, - {0x29u, 0x10u}, - {0x2Bu, 0x04u}, - {0x2Du, 0x01u}, - {0x31u, 0x1Cu}, - {0x32u, 0xFFu}, - {0x33u, 0x02u}, - {0x35u, 0x01u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x10u}, + {0x15u, 0x20u}, + {0x16u, 0x18u}, + {0x17u, 0x0Fu}, + {0x18u, 0x07u}, + {0x19u, 0x04u}, + {0x1Bu, 0x08u}, + {0x1Eu, 0x20u}, + {0x20u, 0x20u}, + {0x21u, 0x4Fu}, + {0x22u, 0x10u}, + {0x23u, 0x80u}, + {0x26u, 0x02u}, + {0x27u, 0x10u}, + {0x28u, 0x20u}, + {0x29u, 0x50u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x8Fu}, + {0x31u, 0x03u}, + {0x32u, 0x38u}, + {0x33u, 0xF0u}, + {0x34u, 0x07u}, + {0x35u, 0x0Cu}, + {0x39u, 0x08u}, + {0x3Bu, 0x22u}, + {0x3Eu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x20u}, + {0x5Cu, 0x22u}, {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x82u, 0x02u}, - {0x84u, 0x04u}, - {0x86u, 0x09u}, - {0x89u, 0x01u}, - {0x8Cu, 0x08u}, - {0x8Du, 0x01u}, - {0x8Eu, 0x04u}, - {0x8Fu, 0x02u}, - {0x91u, 0x02u}, - {0x98u, 0x08u}, - {0x9Au, 0x04u}, - {0x9Cu, 0x08u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x08u}, - {0xA2u, 0x16u}, - {0xA3u, 0x04u}, - {0xAFu, 0x08u}, - {0xB0u, 0x10u}, - {0xB1u, 0x08u}, - {0xB3u, 0x04u}, - {0xB4u, 0x0Cu}, - {0xB6u, 0x03u}, - {0xB7u, 0x03u}, - {0xBAu, 0x20u}, - {0xBEu, 0x40u}, - {0xBFu, 0x40u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x03u, 0x22u}, - {0x04u, 0x02u}, - {0x05u, 0x28u}, - {0x06u, 0x02u}, - {0x08u, 0x40u}, - {0x0Au, 0x0Au}, - {0x0Eu, 0x80u}, - {0x0Fu, 0x28u}, - {0x13u, 0x01u}, - {0x15u, 0x04u}, - {0x17u, 0x01u}, - {0x1Au, 0x01u}, - {0x1Bu, 0xA3u}, - {0x1Cu, 0x20u}, - {0x22u, 0x85u}, - {0x25u, 0x01u}, - {0x27u, 0x14u}, - {0x28u, 0x40u}, - {0x2Bu, 0x01u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x14u}, - {0x30u, 0x02u}, - {0x36u, 0x09u}, - {0x37u, 0x20u}, - {0x39u, 0x50u}, - {0x3Cu, 0x28u}, - {0x3Du, 0x82u}, - {0x58u, 0x24u}, - {0x5Au, 0x80u}, - {0x5Bu, 0x02u}, - {0x5Du, 0x08u}, - {0x5Eu, 0x08u}, - {0x60u, 0x84u}, - {0x61u, 0x04u}, - {0x62u, 0x01u}, - {0x63u, 0x11u}, - {0x68u, 0x01u}, - {0x6Du, 0x40u}, - {0x6Fu, 0x01u}, - {0x80u, 0x04u}, - {0x83u, 0x04u}, - {0x84u, 0x04u}, - {0x86u, 0x80u}, - {0x8Au, 0x02u}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x20u}, + {0x80u, 0x05u}, + {0x82u, 0x0Au}, + {0x85u, 0x08u}, + {0x88u, 0x06u}, + {0x89u, 0x20u}, + {0x8Au, 0x09u}, + {0x8Cu, 0x0Fu}, + {0x8Eu, 0xF0u}, + {0x90u, 0x30u}, {0x91u, 0x10u}, - {0x93u, 0x28u}, - {0x94u, 0x20u}, - {0x95u, 0x4Eu}, - {0x96u, 0x01u}, - {0x98u, 0x12u}, - {0x99u, 0x20u}, - {0x9Au, 0x40u}, - {0x9Cu, 0x80u}, - {0x9Du, 0x55u}, - {0x9Eu, 0x0Eu}, - {0xA0u, 0x0Cu}, - {0xA1u, 0x40u}, - {0xA2u, 0x2Cu}, - {0xA3u, 0x44u}, - {0xA4u, 0x80u}, - {0xA5u, 0x2Bu}, - {0xA7u, 0x90u}, - {0xAAu, 0x40u}, - {0xABu, 0x42u}, - {0xACu, 0x14u}, - {0xB1u, 0x80u}, - {0xB2u, 0x04u}, - {0xB3u, 0x05u}, - {0xC0u, 0xFDu}, - {0xC2u, 0x73u}, - {0xC4u, 0x38u}, - {0xCAu, 0x79u}, - {0xCCu, 0xE1u}, - {0xCEu, 0xFCu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x81u}, - {0xE2u, 0x08u}, - {0xE4u, 0x08u}, - {0xEAu, 0x81u}, - {0xECu, 0x80u}, - {0xEEu, 0x20u}, - {0x03u, 0x4Cu}, - {0x05u, 0x01u}, - {0x07u, 0x30u}, - {0x08u, 0x05u}, - {0x09u, 0x40u}, - {0x0Au, 0x0Au}, - {0x0Bu, 0x1Cu}, - {0x0Du, 0x04u}, - {0x0Fu, 0x08u}, - {0x10u, 0x30u}, - {0x12u, 0xC0u}, - {0x13u, 0x0Cu}, - {0x14u, 0x50u}, - {0x15u, 0x4Cu}, - {0x16u, 0xA0u}, - {0x17u, 0x20u}, - {0x18u, 0x60u}, - {0x19u, 0x02u}, - {0x1Au, 0x90u}, - {0x1Du, 0x0Cu}, - {0x20u, 0x03u}, - {0x21u, 0x01u}, - {0x22u, 0x0Cu}, - {0x23u, 0x02u}, - {0x24u, 0x06u}, - {0x26u, 0x09u}, - {0x2Bu, 0x40u}, - {0x2Cu, 0x0Fu}, - {0x2Du, 0x04u}, - {0x2Eu, 0xF0u}, - {0x2Fu, 0x08u}, - {0x31u, 0x0Cu}, - {0x34u, 0xFFu}, - {0x35u, 0x70u}, - {0x37u, 0x03u}, - {0x3Bu, 0x02u}, - {0x3Eu, 0x10u}, - {0x3Fu, 0x40u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x20u}, - {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x81u, 0x01u}, - {0x82u, 0xF8u}, - {0x83u, 0x02u}, - {0x84u, 0x40u}, - {0x85u, 0x01u}, - {0x86u, 0x80u}, - {0x87u, 0x02u}, - {0x88u, 0x10u}, - {0x89u, 0x04u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x10u}, - {0x8Du, 0x20u}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x1Fu}, - {0x90u, 0x02u}, - {0x92u, 0xF0u}, - {0x94u, 0x05u}, + {0x92u, 0xC0u}, + {0x94u, 0x03u}, {0x95u, 0x04u}, - {0x96u, 0xF8u}, - {0x97u, 0x08u}, - {0x99u, 0x0Fu}, - {0x9Au, 0x01u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0xF0u}, - {0x9Du, 0x10u}, - {0x9Eu, 0x08u}, - {0x9Fu, 0x20u}, - {0xA0u, 0x40u}, - {0xA1u, 0x0Fu}, - {0xA2u, 0x80u}, - {0xA3u, 0x10u}, - {0xA8u, 0xF4u}, - {0xA9u, 0x20u}, - {0xAAu, 0x08u}, - {0xABu, 0x1Fu}, - {0xAFu, 0x1Fu}, + {0x96u, 0x0Cu}, + {0x9Du, 0x01u}, + {0xA4u, 0x60u}, + {0xA6u, 0x90u}, + {0xA8u, 0x50u}, + {0xA9u, 0x02u}, + {0xAAu, 0xA0u}, + {0xADu, 0x15u}, + {0xAFu, 0x2Au}, {0xB1u, 0x30u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x03u}, - {0xB4u, 0x30u}, - {0xB5u, 0x0Cu}, - {0xB6u, 0xC0u}, - {0xB8u, 0x08u}, - {0xBAu, 0xA0u}, - {0xBBu, 0x2Au}, - {0xD4u, 0x40u}, + {0xB3u, 0x0Cu}, + {0xB5u, 0x03u}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, + {0xBFu, 0x15u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x22u}, + {0xDDu, 0x20u}, {0xDFu, 0x01u}, - {0x03u, 0x04u}, - {0x04u, 0x02u}, + {0x00u, 0x02u}, + {0x02u, 0x80u}, + {0x03u, 0x0Au}, {0x05u, 0x10u}, - {0x06u, 0x20u}, - {0x07u, 0x01u}, - {0x08u, 0x01u}, - {0x09u, 0x2Au}, - {0x0Eu, 0x69u}, - {0x11u, 0x43u}, - {0x12u, 0x01u}, - {0x13u, 0x04u}, - {0x14u, 0x80u}, - {0x15u, 0x20u}, - {0x18u, 0x08u}, - {0x19u, 0x20u}, - {0x1Cu, 0x30u}, - {0x1Eu, 0x24u}, - {0x1Fu, 0x44u}, - {0x20u, 0x82u}, - {0x23u, 0x44u}, - {0x25u, 0x14u}, - {0x27u, 0x48u}, - {0x29u, 0x40u}, - {0x2Au, 0x11u}, - {0x2Fu, 0x86u}, - {0x31u, 0x20u}, - {0x32u, 0x08u}, - {0x33u, 0x82u}, - {0x34u, 0x20u}, - {0x35u, 0x04u}, - {0x37u, 0x40u}, - {0x38u, 0x12u}, - {0x3Bu, 0x44u}, - {0x3Du, 0xA8u}, - {0x3Fu, 0x01u}, - {0x64u, 0x04u}, - {0x65u, 0x80u}, - {0x67u, 0x10u}, - {0x78u, 0x20u}, - {0x79u, 0x20u}, - {0x7Au, 0x08u}, - {0x81u, 0x04u}, - {0x84u, 0x01u}, - {0x86u, 0x20u}, - {0x87u, 0x40u}, + {0x06u, 0xA2u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x40u}, + {0x0Du, 0x10u}, + {0x0Eu, 0x22u}, + {0x10u, 0x04u}, + {0x13u, 0x14u}, + {0x14u, 0x20u}, + {0x15u, 0x01u}, + {0x17u, 0x10u}, + {0x1Bu, 0x80u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x18u}, + {0x20u, 0x08u}, + {0x21u, 0x06u}, + {0x24u, 0x20u}, + {0x26u, 0x2Au}, + {0x27u, 0x10u}, + {0x28u, 0x04u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x28u}, + {0x2Du, 0x01u}, + {0x2Fu, 0x20u}, + {0x32u, 0x81u}, + {0x33u, 0x08u}, + {0x34u, 0x08u}, + {0x36u, 0x22u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x0Au}, + {0x44u, 0x08u}, + {0x46u, 0x04u}, + {0x48u, 0x08u}, + {0x4Au, 0x08u}, + {0x58u, 0x60u}, + {0x59u, 0x20u}, + {0x5Cu, 0x04u}, + {0x5Eu, 0x40u}, + {0x5Fu, 0x21u}, + {0x64u, 0x40u}, + {0x65u, 0x81u}, + {0x6Fu, 0x02u}, + {0x85u, 0x02u}, + {0x89u, 0x02u}, + {0x8Eu, 0x04u}, {0x8Fu, 0x01u}, - {0x90u, 0x02u}, - {0x91u, 0x10u}, - {0x93u, 0x31u}, - {0x94u, 0x28u}, - {0x95u, 0x4Fu}, - {0x97u, 0x02u}, - {0x98u, 0x02u}, - {0x9Au, 0x50u}, - {0x9Bu, 0x04u}, - {0x9Cu, 0x21u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x0Eu}, - {0x9Fu, 0x08u}, - {0xA0u, 0x0Cu}, + {0x91u, 0xA1u}, + {0x92u, 0x62u}, + {0x93u, 0x08u}, + {0x94u, 0xA8u}, + {0x95u, 0x1Cu}, + {0x97u, 0x40u}, + {0x98u, 0x80u}, + {0x99u, 0x01u}, + {0x9Au, 0x32u}, + {0x9Bu, 0x28u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x23u}, {0xA1u, 0x40u}, - {0xA2u, 0x2Cu}, - {0xA3u, 0x44u}, - {0xA4u, 0xD0u}, - {0xA5u, 0x08u}, - {0xA6u, 0x10u}, - {0xA7u, 0x92u}, - {0xABu, 0x08u}, - {0xAEu, 0x40u}, - {0xAFu, 0x20u}, - {0xB1u, 0x10u}, - {0xB2u, 0x10u}, - {0xB3u, 0x10u}, - {0xB5u, 0x30u}, - {0xC0u, 0xF2u}, - {0xC2u, 0xFEu}, - {0xC4u, 0x5Du}, - {0xCAu, 0xBDu}, - {0xCCu, 0x7Fu}, - {0xCEu, 0xFFu}, - {0xD8u, 0x70u}, - {0xE0u, 0x40u}, - {0xE4u, 0x08u}, + {0xA2u, 0x05u}, + {0xA3u, 0x45u}, + {0xA4u, 0x54u}, + {0xA5u, 0x01u}, + {0xA6u, 0x2Au}, + {0xA7u, 0x82u}, + {0xAAu, 0x28u}, + {0xACu, 0x10u}, + {0xADu, 0x08u}, + {0xAEu, 0x80u}, + {0xAFu, 0x10u}, + {0xB2u, 0x02u}, + {0xB3u, 0x20u}, + {0xB7u, 0x40u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xECu}, + {0xC4u, 0x76u}, + {0xCAu, 0xECu}, + {0xCCu, 0xEBu}, + {0xCEu, 0xF6u}, + {0xD6u, 0xF8u}, + {0xD8u, 0x10u}, + {0xE2u, 0x04u}, + {0xE6u, 0x04u}, {0xE8u, 0x82u}, - {0xECu, 0xA0u}, - {0xEEu, 0x40u}, - {0x00u, 0x03u}, - {0x01u, 0x20u}, - {0x02u, 0x0Cu}, - {0x03u, 0x40u}, - {0x06u, 0x80u}, - {0x08u, 0x06u}, - {0x09u, 0x01u}, - {0x0Au, 0x09u}, - {0x0Bu, 0x6Eu}, - {0x0Du, 0x03u}, - {0x0Eu, 0x70u}, - {0x0Fu, 0x74u}, - {0x10u, 0xC0u}, - {0x11u, 0x20u}, - {0x12u, 0x1Fu}, - {0x13u, 0x40u}, - {0x14u, 0x90u}, - {0x15u, 0x78u}, - {0x16u, 0x2Fu}, - {0x17u, 0x03u}, - {0x18u, 0x0Fu}, - {0x19u, 0x02u}, - {0x20u, 0x05u}, - {0x21u, 0x64u}, - {0x22u, 0x0Au}, - {0x24u, 0xA0u}, - {0x25u, 0x80u}, - {0x26u, 0x4Fu}, - {0x27u, 0x01u}, - {0x2Bu, 0x08u}, - {0x2Fu, 0x7Fu}, - {0x30u, 0x7Fu}, - {0x31u, 0x60u}, - {0x35u, 0x80u}, - {0x36u, 0x80u}, - {0x37u, 0x1Fu}, - {0x3Bu, 0x02u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x10u}, - {0x54u, 0x01u}, + {0xEAu, 0x01u}, + {0xECu, 0x60u}, + {0xEEu, 0x02u}, + {0x01u, 0x04u}, + {0x02u, 0x40u}, + {0x03u, 0x02u}, + {0x06u, 0x30u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x10u}, + {0x10u, 0x48u}, + {0x11u, 0x08u}, + {0x12u, 0x24u}, + {0x13u, 0x10u}, + {0x16u, 0x48u}, + {0x17u, 0x04u}, + {0x19u, 0x08u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x03u}, + {0x1Eu, 0x06u}, + {0x22u, 0x08u}, + {0x28u, 0x48u}, + {0x29u, 0x04u}, + {0x2Au, 0x12u}, + {0x2Bu, 0x01u}, + {0x30u, 0x01u}, + {0x33u, 0x18u}, + {0x34u, 0x70u}, + {0x35u, 0x07u}, + {0x36u, 0x0Eu}, + {0x3Fu, 0x04u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x22u}, - {0x5Du, 0x20u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x10u}, - {0x88u, 0x40u}, - {0x8Cu, 0x53u}, - {0x8Du, 0x01u}, - {0x8Eu, 0xACu}, - {0x90u, 0x02u}, - {0x91u, 0x15u}, - {0x92u, 0x01u}, - {0x93u, 0x2Au}, - {0x94u, 0x80u}, - {0x9Du, 0x02u}, - {0xA0u, 0x08u}, - {0xA1u, 0x04u}, - {0xA2u, 0x04u}, - {0xA5u, 0x08u}, - {0xA8u, 0x24u}, - {0xAAu, 0x08u}, - {0xACu, 0x11u}, - {0xADu, 0x20u}, - {0xAEu, 0x02u}, - {0xB0u, 0xC0u}, - {0xB1u, 0x0Cu}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x30u}, - {0xB4u, 0x30u}, - {0xB5u, 0x03u}, - {0xBEu, 0x15u}, - {0xBFu, 0x15u}, - {0xD6u, 0x08u}, + {0x82u, 0x70u}, + {0x84u, 0xC0u}, + {0x86u, 0x1Fu}, + {0x88u, 0x90u}, + {0x8Au, 0x2Fu}, + {0x8Cu, 0x06u}, + {0x8Eu, 0x09u}, + {0x8Fu, 0x04u}, + {0x94u, 0x03u}, + {0x96u, 0x0Cu}, + {0x97u, 0x02u}, + {0x98u, 0x0Fu}, + {0x9Cu, 0xA0u}, + {0x9Eu, 0x4Fu}, + {0xA0u, 0x05u}, + {0xA2u, 0x0Au}, + {0xA6u, 0x80u}, + {0xA9u, 0x01u}, + {0xADu, 0x02u}, + {0xAFu, 0x04u}, + {0xB0u, 0x7Fu}, + {0xB5u, 0x01u}, + {0xB6u, 0x80u}, + {0xB7u, 0x06u}, + {0xBEu, 0x40u}, + {0xBFu, 0x50u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDDu, 0x90u}, + {0xDCu, 0x02u}, {0xDFu, 0x01u}, - {0x01u, 0x40u}, - {0x03u, 0x05u}, - {0x04u, 0x60u}, - {0x05u, 0x09u}, - {0x09u, 0x08u}, - {0x0Au, 0x80u}, - {0x0Bu, 0x40u}, - {0x0Eu, 0xA8u}, + {0x00u, 0x04u}, + {0x01u, 0x02u}, + {0x02u, 0x10u}, + {0x04u, 0xA0u}, + {0x05u, 0x01u}, + {0x06u, 0x20u}, + {0x09u, 0x04u}, + {0x0Au, 0x0Au}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x60u}, + {0x0Eu, 0x20u}, {0x10u, 0x80u}, - {0x12u, 0x05u}, - {0x14u, 0x20u}, + {0x12u, 0x08u}, {0x15u, 0x02u}, - {0x18u, 0x80u}, - {0x1Bu, 0x24u}, - {0x1Cu, 0x40u}, - {0x1Du, 0x40u}, - {0x22u, 0x01u}, - {0x23u, 0x24u}, - {0x24u, 0x02u}, - {0x25u, 0x61u}, - {0x26u, 0x42u}, - {0x28u, 0x01u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x10u}, - {0x2Cu, 0x20u}, - {0x2Fu, 0x86u}, - {0x30u, 0x80u}, - {0x33u, 0x01u}, - {0x34u, 0x02u}, - {0x35u, 0x20u}, - {0x36u, 0x08u}, + {0x17u, 0x04u}, + {0x18u, 0x04u}, + {0x1Au, 0x82u}, + {0x1Du, 0x41u}, + {0x21u, 0x08u}, + {0x22u, 0x10u}, + {0x25u, 0x50u}, + {0x26u, 0x80u}, + {0x27u, 0x01u}, + {0x29u, 0x10u}, + {0x2Cu, 0x40u}, + {0x2Du, 0x41u}, + {0x2Fu, 0x08u}, + {0x30u, 0x08u}, + {0x32u, 0x10u}, + {0x33u, 0x02u}, + {0x37u, 0x08u}, {0x39u, 0x01u}, + {0x3Au, 0x20u}, {0x3Bu, 0x40u}, - {0x3Cu, 0x20u}, - {0x3Du, 0x82u}, - {0x59u, 0x10u}, - {0x5Bu, 0x40u}, - {0x5Cu, 0x40u}, - {0x62u, 0x60u}, - {0x63u, 0x01u}, - {0x82u, 0x02u}, - {0x86u, 0x01u}, - {0x87u, 0x24u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x01u}, - {0x92u, 0x80u}, - {0x93u, 0x28u}, - {0x94u, 0x08u}, - {0x95u, 0x4Cu}, - {0x97u, 0x02u}, - {0x98u, 0x02u}, - {0x99u, 0x28u}, - {0x9Bu, 0x44u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x0Au}, - {0xA0u, 0x2Cu}, - {0xA2u, 0x0Cu}, - {0xA3u, 0x40u}, - {0xA4u, 0x50u}, - {0xA5u, 0x40u}, - {0xA6u, 0x20u}, - {0xA7u, 0x96u}, - {0xAAu, 0x40u}, - {0xABu, 0x40u}, - {0xAEu, 0x09u}, - {0xAFu, 0x01u}, - {0xB0u, 0x04u}, - {0xB3u, 0x0Cu}, - {0xB7u, 0x40u}, - {0xC0u, 0xF3u}, - {0xC2u, 0x7Cu}, - {0xC4u, 0x3Bu}, - {0xCAu, 0xFBu}, - {0xCCu, 0xE9u}, - {0xCEu, 0xB9u}, - {0xD6u, 0x1Cu}, - {0xD8u, 0x0Cu}, - {0xE0u, 0x02u}, - {0xE2u, 0x04u}, - {0xE4u, 0x4Au}, - {0xE6u, 0x20u}, - {0xE8u, 0xA0u}, + {0x3Eu, 0x80u}, + {0x49u, 0x10u}, + {0x4Au, 0x08u}, + {0x58u, 0x18u}, + {0x59u, 0x80u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x08u}, + {0x5Eu, 0x81u}, + {0x5Fu, 0x10u}, + {0x63u, 0x0Au}, + {0x65u, 0x40u}, + {0x69u, 0x40u}, + {0x6Cu, 0x22u}, + {0x6Fu, 0x18u}, + {0x80u, 0x04u}, + {0x81u, 0x10u}, + {0x84u, 0x04u}, + {0x85u, 0x04u}, + {0x8Eu, 0x04u}, + {0x91u, 0xA3u}, + {0x92u, 0x49u}, + {0x93u, 0x88u}, + {0x94u, 0x20u}, + {0x95u, 0x14u}, + {0x96u, 0x82u}, + {0x98u, 0x80u}, + {0x99u, 0x82u}, + {0x9Au, 0xA0u}, + {0x9Bu, 0x0Cu}, + {0x9Du, 0x08u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x11u}, + {0xA0u, 0x89u}, + {0xA1u, 0x04u}, + {0xA2u, 0x51u}, + {0xA4u, 0x70u}, + {0xA5u, 0x01u}, + {0xA6u, 0x0Au}, + {0xA7u, 0x83u}, + {0xA8u, 0x82u}, + {0xADu, 0x60u}, + {0xAFu, 0x02u}, + {0xB5u, 0x41u}, + {0xB6u, 0x09u}, + {0xC0u, 0xFCu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x3Au}, + {0xCAu, 0x34u}, + {0xCCu, 0x47u}, + {0xCEu, 0x1Du}, + {0xD6u, 0xFCu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x48u}, + {0xE4u, 0x03u}, + {0xE8u, 0x10u}, {0xEAu, 0x04u}, - {0xECu, 0xC2u}, + {0xECu, 0x10u}, {0xEEu, 0x09u}, - {0x04u, 0x80u}, - {0x05u, 0x02u}, - {0x07u, 0x01u}, - {0x08u, 0x24u}, - {0x0Au, 0x09u}, - {0x0Cu, 0x40u}, - {0x0Eu, 0x80u}, - {0x12u, 0x18u}, - {0x15u, 0x06u}, - {0x1Au, 0x03u}, - {0x1Cu, 0x40u}, - {0x21u, 0x01u}, - {0x22u, 0x20u}, - {0x23u, 0x04u}, - {0x25u, 0x01u}, - {0x26u, 0x04u}, - {0x27u, 0x02u}, - {0x28u, 0x24u}, - {0x2Au, 0x12u}, - {0x2Eu, 0x24u}, - {0x30u, 0x38u}, - {0x33u, 0x07u}, - {0x34u, 0x07u}, - {0x36u, 0xC0u}, - {0x39u, 0x08u}, - {0x3Eu, 0x40u}, + {0x01u, 0x02u}, + {0x02u, 0xFFu}, + {0x05u, 0x20u}, + {0x06u, 0xFFu}, + {0x07u, 0x40u}, + {0x08u, 0x0Fu}, + {0x09u, 0x01u}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x6Eu}, + {0x11u, 0x64u}, + {0x14u, 0x33u}, + {0x15u, 0x03u}, + {0x16u, 0xCCu}, + {0x17u, 0x74u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0xFFu}, + {0x20u, 0xFFu}, + {0x21u, 0x78u}, + {0x23u, 0x03u}, + {0x26u, 0xFFu}, + {0x27u, 0x7Fu}, + {0x28u, 0x69u}, + {0x29u, 0x20u}, + {0x2Au, 0x96u}, + {0x2Bu, 0x40u}, + {0x2Cu, 0x55u}, + {0x2Eu, 0xAAu}, + {0x2Fu, 0x08u}, + {0x32u, 0xFFu}, + {0x33u, 0x1Fu}, + {0x37u, 0x60u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x80u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x02u}, + {0x5Cu, 0x22u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x40u}, - {0x83u, 0x80u}, - {0x84u, 0x0Fu}, - {0x85u, 0xCAu}, - {0x86u, 0xF0u}, - {0x87u, 0x15u}, - {0x89u, 0x0Bu}, - {0x8Au, 0xFFu}, - {0x8Bu, 0xF4u}, - {0x8Cu, 0x21u}, - {0x8Du, 0x11u}, - {0x8Eu, 0x12u}, - {0x8Fu, 0xECu}, - {0x94u, 0x84u}, - {0x95u, 0x01u}, - {0x96u, 0x48u}, - {0x99u, 0x40u}, - {0x9Au, 0xFFu}, - {0x9Bu, 0x80u}, - {0x9Cu, 0xFFu}, - {0xA0u, 0x11u}, - {0xA1u, 0xE0u}, - {0xA2u, 0x22u}, - {0xA4u, 0x44u}, - {0xA5u, 0x06u}, - {0xA6u, 0x88u}, - {0xABu, 0x10u}, - {0xACu, 0x33u}, - {0xAEu, 0xCCu}, - {0xAFu, 0xFFu}, - {0xB3u, 0x3Fu}, + {0x80u, 0x0Fu}, + {0x81u, 0x0Fu}, + {0x82u, 0xF0u}, + {0x83u, 0xF0u}, + {0x84u, 0x44u}, + {0x86u, 0x88u}, + {0x8Bu, 0xFFu}, + {0x8Cu, 0x33u}, + {0x8Du, 0x33u}, + {0x8Eu, 0xCCu}, + {0x8Fu, 0xCCu}, + {0x91u, 0xFFu}, + {0x92u, 0xFFu}, + {0x96u, 0xFFu}, + {0x97u, 0xFFu}, + {0x98u, 0x11u}, + {0x9Au, 0x22u}, + {0x9Cu, 0x21u}, + {0x9Du, 0xFFu}, + {0x9Eu, 0x12u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x84u}, + {0xA9u, 0x69u}, + {0xAAu, 0x48u}, + {0xABu, 0x96u}, + {0xACu, 0xFFu}, + {0xADu, 0x55u}, + {0xAFu, 0xAAu}, + {0xB1u, 0xFFu}, {0xB4u, 0xFFu}, - {0xB7u, 0xC0u}, - {0xBBu, 0x80u}, + {0xBBu, 0x02u}, {0xBEu, 0x10u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x20u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x20u}, - {0x01u, 0x44u}, - {0x04u, 0x28u}, - {0x06u, 0x02u}, - {0x08u, 0x40u}, - {0x0Au, 0x84u}, - {0x0Bu, 0x02u}, - {0x0Fu, 0x2Au}, - {0x11u, 0x80u}, - {0x12u, 0x08u}, - {0x13u, 0x09u}, - {0x14u, 0x40u}, - {0x15u, 0x44u}, - {0x1Au, 0x86u}, - {0x1Fu, 0x10u}, - {0x21u, 0x08u}, - {0x24u, 0x03u}, + {0x01u, 0x04u}, + {0x03u, 0x82u}, + {0x04u, 0x10u}, + {0x05u, 0x05u}, + {0x08u, 0x28u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x0Du, 0x80u}, + {0x0Fu, 0x20u}, + {0x10u, 0x02u}, + {0x11u, 0x10u}, + {0x14u, 0x06u}, + {0x16u, 0x20u}, + {0x17u, 0x01u}, + {0x1Au, 0x04u}, + {0x1Cu, 0x10u}, + {0x1Eu, 0x20u}, + {0x21u, 0x01u}, {0x25u, 0x04u}, - {0x26u, 0x08u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x28u}, - {0x2Fu, 0xA2u}, - {0x30u, 0x08u}, - {0x31u, 0x08u}, - {0x36u, 0x24u}, - {0x39u, 0x08u}, - {0x3Cu, 0x21u}, - {0x3Du, 0x88u}, - {0x5Au, 0x44u}, - {0x5Bu, 0x04u}, - {0x5Du, 0x88u}, - {0x5Eu, 0x20u}, - {0x5Fu, 0x02u}, - {0x60u, 0x02u}, - {0x65u, 0x40u}, - {0x6Cu, 0x32u}, - {0x6Eu, 0x18u}, - {0x80u, 0x01u}, - {0x81u, 0xA0u}, - {0x83u, 0x03u}, - {0x84u, 0x42u}, - {0x86u, 0x10u}, + {0x26u, 0x04u}, + {0x27u, 0x02u}, + {0x29u, 0x04u}, + {0x2Au, 0x0Cu}, + {0x2Bu, 0x05u}, + {0x2Du, 0x60u}, + {0x2Eu, 0x08u}, + {0x2Fu, 0x40u}, + {0x31u, 0x80u}, + {0x32u, 0x08u}, + {0x33u, 0x01u}, + {0x36u, 0x04u}, + {0x37u, 0x11u}, + {0x39u, 0x02u}, + {0x3Au, 0x60u}, + {0x3Eu, 0x03u}, + {0x3Fu, 0x18u}, + {0x40u, 0x08u}, + {0x43u, 0x10u}, + {0x4Au, 0x08u}, + {0x4Bu, 0x10u}, + {0x59u, 0x40u}, + {0x5Au, 0x20u}, + {0x5Cu, 0x40u}, + {0x5Eu, 0x10u}, + {0x62u, 0x40u}, + {0x63u, 0x08u}, + {0x66u, 0x80u}, + {0x67u, 0x08u}, + {0x80u, 0x40u}, + {0x82u, 0x50u}, + {0x88u, 0x20u}, + {0x89u, 0x80u}, + {0x8Au, 0x40u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x31u}, + {0x8Fu, 0x10u}, + {0x91u, 0x61u}, + {0x92u, 0x08u}, + {0x93u, 0x80u}, + {0x94u, 0x20u}, + {0x96u, 0x84u}, + {0x97u, 0x08u}, + {0x98u, 0x06u}, + {0x99u, 0x02u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x0Cu}, + {0x9Du, 0x08u}, + {0x9Eu, 0xC5u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x89u}, + {0xA1u, 0x80u}, + {0xA4u, 0x70u}, + {0xA5u, 0x04u}, + {0xA6u, 0x02u}, + {0xAAu, 0x24u}, + {0xACu, 0x80u}, + {0xADu, 0x08u}, + {0xB1u, 0x10u}, + {0xB2u, 0x40u}, + {0xB4u, 0x12u}, + {0xB5u, 0x40u}, + {0xB7u, 0x40u}, + {0xC0u, 0x7Du}, + {0xC2u, 0xAFu}, + {0xC4u, 0xF3u}, + {0xCAu, 0xFEu}, + {0xCCu, 0xEBu}, + {0xCEu, 0xEDu}, + {0xD6u, 0x3Cu}, + {0xD8u, 0x3Cu}, + {0xE0u, 0xB0u}, + {0xE2u, 0x01u}, + {0xE6u, 0x40u}, + {0xE8u, 0x40u}, + {0xEAu, 0xA0u}, + {0xECu, 0x20u}, + {0xEEu, 0x40u}, + {0x01u, 0x20u}, + {0x03u, 0x10u}, + {0x04u, 0x02u}, + {0x08u, 0x02u}, + {0x09u, 0x04u}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x02u}, + {0x0Fu, 0x18u}, + {0x11u, 0x20u}, + {0x12u, 0x01u}, + {0x13u, 0x08u}, + {0x17u, 0x20u}, + {0x18u, 0x02u}, + {0x19u, 0x02u}, + {0x1Bu, 0x04u}, + {0x1Du, 0x04u}, + {0x1Fu, 0x02u}, + {0x23u, 0x20u}, + {0x29u, 0x04u}, + {0x2Bu, 0x02u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x03u}, + {0x32u, 0x02u}, + {0x33u, 0x01u}, + {0x34u, 0x01u}, + {0x35u, 0x06u}, + {0x37u, 0x38u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x22u}, + {0x5Fu, 0x01u}, + {0x80u, 0x40u}, + {0x82u, 0x80u}, + {0x84u, 0x40u}, + {0x86u, 0x80u}, + {0x87u, 0x3Fu}, + {0x88u, 0x06u}, + {0x89u, 0x10u}, {0x8Bu, 0x20u}, - {0x8Eu, 0x18u}, - {0xC0u, 0xE7u}, - {0xC2u, 0xEBu}, - {0xC4u, 0xBFu}, - {0xCAu, 0xF3u}, - {0xCCu, 0x62u}, - {0xCEu, 0xF2u}, - {0xD6u, 0xF8u}, - {0xD8u, 0x18u}, - {0xE0u, 0x80u}, - {0xE6u, 0x50u}, - {0x80u, 0x10u}, - {0x84u, 0x01u}, - {0x88u, 0xA2u}, - {0x8Au, 0x08u}, - {0x8Cu, 0x07u}, - {0x8Eu, 0xD8u}, - {0x90u, 0x01u}, - {0x96u, 0x40u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x3Fu}, + {0x90u, 0x0Bu}, + {0x91u, 0x3Fu}, + {0x92u, 0xF4u}, + {0x95u, 0x01u}, + {0x97u, 0x02u}, + {0x98u, 0x01u}, {0x99u, 0x01u}, - {0x9Cu, 0x08u}, - {0x9Eu, 0x61u}, - {0xA0u, 0x01u}, - {0xA4u, 0x01u}, - {0xA5u, 0x01u}, - {0xA8u, 0x04u}, - {0xACu, 0x01u}, - {0xB2u, 0xE0u}, - {0xB3u, 0x01u}, - {0xB4u, 0x3Fu}, - {0xB8u, 0x20u}, - {0xB9u, 0x08u}, - {0xBEu, 0x10u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0xCAu}, + {0x9Du, 0x04u}, + {0x9Eu, 0x15u}, + {0x9Fu, 0x08u}, + {0xA0u, 0xE0u}, + {0xA1u, 0x3Fu}, + {0xA7u, 0x3Fu}, + {0xA9u, 0x10u}, + {0xAAu, 0xFFu}, + {0xABu, 0x20u}, + {0xACu, 0x11u}, + {0xADu, 0x04u}, + {0xAEu, 0xECu}, + {0xAFu, 0x08u}, + {0xB3u, 0x03u}, + {0xB4u, 0xC0u}, + {0xB5u, 0x30u}, + {0xB6u, 0x3Fu}, + {0xB7u, 0x0Cu}, + {0xBAu, 0x20u}, + {0xBBu, 0xA8u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x11u}, + {0xDBu, 0x04u}, + {0xDCu, 0x22u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x01u}, - {0x03u, 0x01u}, - {0x04u, 0x88u}, - {0x05u, 0x11u}, - {0x07u, 0x20u}, - {0x08u, 0x08u}, + {0x00u, 0xA0u}, + {0x01u, 0x08u}, + {0x04u, 0x04u}, + {0x05u, 0x20u}, + {0x06u, 0x42u}, + {0x07u, 0x04u}, {0x0Au, 0x84u}, - {0x0Bu, 0x01u}, - {0x0Du, 0x41u}, - {0x0Eu, 0x10u}, - {0x0Fu, 0x02u}, - {0x12u, 0x01u}, - {0x13u, 0x28u}, - {0x15u, 0x08u}, - {0x16u, 0x02u}, - {0x17u, 0x11u}, - {0x18u, 0xC8u}, - {0x1Au, 0x82u}, - {0x1Bu, 0x08u}, - {0x1Eu, 0x10u}, - {0x1Fu, 0x10u}, - {0x21u, 0x02u}, + {0x0Cu, 0x20u}, + {0x0Du, 0x80u}, + {0x0Fu, 0x80u}, + {0x16u, 0x0Du}, + {0x17u, 0x01u}, + {0x19u, 0x10u}, + {0x1Au, 0x20u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x80u}, + {0x1Fu, 0x50u}, + {0x20u, 0x12u}, + {0x21u, 0x60u}, + {0x22u, 0x04u}, + {0x23u, 0x08u}, + {0x25u, 0x10u}, + {0x26u, 0x64u}, {0x27u, 0x10u}, + {0x29u, 0x10u}, + {0x2Au, 0x81u}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x08u}, + {0x2Fu, 0x44u}, + {0x30u, 0x02u}, + {0x31u, 0x28u}, + {0x32u, 0x40u}, + {0x34u, 0x04u}, + {0x36u, 0x40u}, + {0x37u, 0x11u}, + {0x38u, 0x10u}, + {0x39u, 0x81u}, + {0x3Du, 0x28u}, + {0x3Fu, 0x80u}, + {0x5Cu, 0x40u}, + {0x5Fu, 0x20u}, + {0x64u, 0x07u}, + {0x7Du, 0x01u}, + {0x7Fu, 0x40u}, + {0x81u, 0x20u}, + {0x82u, 0x10u}, + {0x83u, 0x20u}, + {0x84u, 0x08u}, + {0x86u, 0x02u}, + {0x87u, 0x50u}, + {0x89u, 0x02u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x02u}, + {0xC0u, 0xF7u}, + {0xC2u, 0xDAu}, + {0xC4u, 0xD0u}, + {0xCAu, 0xFDu}, + {0xCCu, 0xFFu}, + {0xCEu, 0x7Du}, + {0xD6u, 0x30u}, + {0xD8u, 0x30u}, + {0xE0u, 0x80u}, + {0xE2u, 0x01u}, + {0xE4u, 0x04u}, + {0xE6u, 0x10u}, + {0x89u, 0x07u}, + {0x97u, 0x07u}, + {0x98u, 0x01u}, + {0x99u, 0x01u}, + {0x9Bu, 0x18u}, + {0x9Fu, 0x08u}, + {0xABu, 0x2Au}, + {0xADu, 0x34u}, + {0xB0u, 0x01u}, + {0xB5u, 0x07u}, + {0xB7u, 0x38u}, + {0xBEu, 0x01u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x10u}, + {0xDFu, 0x01u}, + {0x01u, 0xA0u}, + {0x03u, 0x50u}, + {0x0Au, 0x41u}, + {0x0Bu, 0x14u}, + {0x0Cu, 0x03u}, + {0x0Fu, 0x08u}, + {0x11u, 0x40u}, + {0x12u, 0x60u}, + {0x13u, 0x20u}, + {0x19u, 0x80u}, + {0x1Bu, 0x01u}, + {0x1Fu, 0x02u}, + {0x23u, 0x10u}, + {0x26u, 0x40u}, + {0x27u, 0x08u}, + {0x29u, 0x24u}, + {0x2Au, 0x42u}, {0x2Bu, 0x01u}, - {0x2Fu, 0x10u}, - {0x31u, 0x02u}, - {0x36u, 0x10u}, - {0x38u, 0x44u}, - {0x40u, 0x40u}, - {0x41u, 0x40u}, - {0x43u, 0x08u}, - {0x48u, 0x01u}, - {0x49u, 0x15u}, - {0x4Au, 0x80u}, - {0x51u, 0x28u}, - {0x52u, 0x01u}, - {0x61u, 0x02u}, - {0x68u, 0x80u}, - {0x69u, 0x0Bu}, - {0x6Au, 0x4Cu}, - {0x6Bu, 0x09u}, - {0x72u, 0x02u}, - {0x73u, 0x01u}, - {0x80u, 0x40u}, - {0x84u, 0x01u}, - {0x8Au, 0x80u}, - {0x8Bu, 0x10u}, - {0x8Eu, 0x10u}, - {0x90u, 0x04u}, - {0x93u, 0x10u}, - {0x94u, 0xC8u}, + {0x2Du, 0x20u}, + {0x2Eu, 0x40u}, + {0x31u, 0x08u}, + {0x33u, 0x51u}, + {0x36u, 0x48u}, + {0x37u, 0x20u}, + {0x38u, 0x88u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Cu, 0x20u}, + {0x41u, 0x08u}, + {0x42u, 0x44u}, + {0x49u, 0x64u}, + {0x4Au, 0xA0u}, + {0x4Bu, 0x02u}, + {0x51u, 0x04u}, + {0x52u, 0x12u}, + {0x61u, 0x10u}, + {0x68u, 0x62u}, + {0x69u, 0x02u}, + {0x6Au, 0x20u}, + {0x6Bu, 0x04u}, + {0x71u, 0x80u}, + {0x79u, 0x02u}, + {0x7Bu, 0x40u}, + {0x83u, 0x0Cu}, + {0x86u, 0x44u}, + {0x8Au, 0xAAu}, + {0x8Fu, 0x02u}, + {0x90u, 0x88u}, + {0x91u, 0x50u}, + {0x92u, 0x41u}, {0x95u, 0x0Au}, - {0x96u, 0x4Au}, - {0x97u, 0x01u}, - {0x98u, 0x08u}, - {0x99u, 0x10u}, - {0x9Du, 0x05u}, - {0x9Eu, 0x03u}, - {0x9Fu, 0x19u}, - {0xA2u, 0x10u}, - {0xA3u, 0x01u}, - {0xA4u, 0x80u}, - {0xA5u, 0x28u}, - {0xA9u, 0x05u}, - {0xACu, 0x80u}, - {0xB0u, 0x08u}, - {0xB1u, 0x10u}, - {0xB2u, 0x08u}, - {0xB3u, 0x41u}, - {0xB6u, 0x01u}, - {0xC0u, 0xFDu}, - {0xC2u, 0xBFu}, - {0xC4u, 0xF7u}, - {0xCAu, 0x48u}, - {0xCCu, 0x21u}, - {0xCEu, 0x0Au}, - {0xD0u, 0x0Bu}, + {0x96u, 0x20u}, + {0x97u, 0x02u}, + {0x99u, 0x70u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x71u}, + {0x9Cu, 0x01u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x10u}, + {0xA1u, 0x08u}, + {0xA4u, 0x62u}, + {0xA5u, 0x80u}, + {0xA7u, 0x40u}, + {0xACu, 0x20u}, + {0xADu, 0x84u}, + {0xB3u, 0x44u}, + {0xB6u, 0x20u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x4Fu}, + {0xC4u, 0x0Fu}, + {0xCAu, 0x3Fu}, + {0xCCu, 0x7Fu}, + {0xCEu, 0x2Eu}, + {0xD0u, 0x07u}, {0xD2u, 0x0Cu}, - {0xD8u, 0x01u}, - {0xE0u, 0x05u}, - {0xE2u, 0x10u}, - {0xE6u, 0x50u}, - {0x02u, 0x9Fu}, - {0x04u, 0x80u}, - {0x05u, 0x02u}, - {0x08u, 0xC0u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x1Fu}, - {0x0Eu, 0x20u}, - {0x10u, 0xC0u}, - {0x12u, 0x02u}, - {0x14u, 0x7Fu}, - {0x16u, 0x80u}, - {0x1Du, 0x04u}, - {0x1Eu, 0xFFu}, - {0x20u, 0x90u}, - {0x22u, 0x40u}, - {0x24u, 0xC0u}, - {0x26u, 0x04u}, - {0x2Au, 0x60u}, - {0x2Cu, 0xC0u}, - {0x2Eu, 0x01u}, - {0x32u, 0xFFu}, - {0x33u, 0x04u}, + {0xD8u, 0x04u}, + {0xE6u, 0x44u}, + {0xEAu, 0x10u}, + {0xECu, 0x08u}, + {0x00u, 0x1Du}, + {0x04u, 0x1Du}, + {0x08u, 0x02u}, + {0x0Au, 0x04u}, + {0x10u, 0x02u}, + {0x12u, 0x08u}, + {0x14u, 0x02u}, + {0x15u, 0x02u}, + {0x16u, 0x0Du}, + {0x18u, 0x01u}, + {0x1Au, 0x02u}, + {0x20u, 0x0Du}, + {0x22u, 0x10u}, + {0x26u, 0x10u}, + {0x28u, 0x1Du}, + {0x29u, 0x01u}, + {0x2Cu, 0x1Du}, + {0x31u, 0x02u}, + {0x32u, 0x0Fu}, + {0x34u, 0x10u}, {0x35u, 0x01u}, - {0x37u, 0x02u}, - {0x39u, 0x02u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x45u}, + {0x3Au, 0x08u}, + {0x3Eu, 0x10u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x20u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x91u}, + {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x81u, 0x9Cu}, - {0x84u, 0x01u}, - {0x85u, 0x61u}, - {0x86u, 0x5Eu}, - {0x87u, 0x1Eu}, - {0x88u, 0x39u}, - {0x89u, 0x10u}, - {0x8Au, 0x06u}, - {0x8Bu, 0x8Cu}, - {0x8Cu, 0x77u}, - {0x8Du, 0x8Cu}, - {0x8Eu, 0x08u}, - {0x8Fu, 0x10u}, - {0x90u, 0x46u}, - {0x91u, 0xD1u}, - {0x92u, 0x80u}, - {0x93u, 0x22u}, - {0x95u, 0x30u}, - {0x96u, 0x80u}, - {0x97u, 0x8Fu}, - {0x98u, 0xC2u}, - {0x99u, 0x94u}, - {0x9Au, 0x04u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0xC6u}, - {0x9Du, 0xA4u}, - {0x9Fu, 0x10u}, - {0xA0u, 0xC6u}, - {0xA1u, 0x08u}, - {0xA3u, 0x40u}, - {0xA4u, 0x80u}, - {0xA6u, 0x46u}, - {0xA8u, 0x42u}, - {0xACu, 0x04u}, - {0xADu, 0x9Cu}, - {0xAEu, 0x20u}, + {0x80u, 0x11u}, + {0x81u, 0xC6u}, + {0x82u, 0x62u}, + {0x84u, 0x52u}, + {0x85u, 0x01u}, + {0x86u, 0x28u}, + {0x87u, 0x5Eu}, + {0x8Cu, 0x02u}, + {0x8Du, 0x39u}, + {0x8Eu, 0x0Du}, + {0x8Fu, 0x06u}, + {0x90u, 0x0Du}, + {0x91u, 0x77u}, + {0x93u, 0x08u}, + {0x94u, 0x0Du}, + {0x95u, 0x80u}, + {0x97u, 0x46u}, + {0x98u, 0x40u}, + {0x99u, 0xC2u}, + {0x9Au, 0x30u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x0Du}, + {0x9Du, 0xC6u}, + {0xA0u, 0x0Du}, + {0xA3u, 0x80u}, + {0xA4u, 0x0Du}, + {0xA5u, 0x04u}, + {0xA7u, 0x20u}, + {0xA9u, 0x42u}, + {0xACu, 0x32u}, + {0xADu, 0x46u}, + {0xAEu, 0x44u}, + {0xAFu, 0x80u}, {0xB0u, 0x0Fu}, {0xB1u, 0x0Fu}, - {0xB2u, 0x80u}, - {0xB3u, 0xC1u}, + {0xB3u, 0x80u}, {0xB4u, 0x70u}, - {0xB7u, 0x30u}, - {0xB8u, 0x02u}, - {0xBAu, 0x30u}, - {0xBBu, 0x8Cu}, - {0xBEu, 0x04u}, + {0xB5u, 0x70u}, + {0xB7u, 0x01u}, + {0xB9u, 0x02u}, + {0xBAu, 0x22u}, + {0xBBu, 0x30u}, + {0xBFu, 0x44u}, {0xD4u, 0x40u}, {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, - {0xDDu, 0x10u}, {0xDFu, 0x01u}, {0x00u, 0x44u}, - {0x01u, 0x10u}, - {0x04u, 0x88u}, - {0x05u, 0x01u}, - {0x06u, 0x08u}, - {0x07u, 0x28u}, - {0x08u, 0x04u}, - {0x09u, 0x08u}, - {0x0Au, 0x48u}, - {0x0Bu, 0x01u}, - {0x0Du, 0x01u}, - {0x0Fu, 0x22u}, - {0x10u, 0x80u}, - {0x12u, 0x03u}, - {0x13u, 0x28u}, - {0x15u, 0x08u}, - {0x16u, 0x22u}, - {0x17u, 0x11u}, - {0x18u, 0x14u}, + {0x02u, 0x40u}, + {0x05u, 0x20u}, + {0x07u, 0x50u}, + {0x08u, 0x01u}, + {0x09u, 0x80u}, + {0x0Au, 0x28u}, + {0x0Cu, 0x10u}, + {0x0Eu, 0x60u}, + {0x10u, 0x20u}, + {0x11u, 0x01u}, + {0x13u, 0x40u}, + {0x15u, 0x18u}, + {0x16u, 0x02u}, + {0x17u, 0x01u}, + {0x18u, 0x40u}, {0x19u, 0x10u}, - {0x1Bu, 0x11u}, + {0x1Au, 0x08u}, {0x1Eu, 0x20u}, - {0x20u, 0x80u}, - {0x21u, 0x02u}, - {0x22u, 0x48u}, - {0x23u, 0x40u}, - {0x25u, 0x05u}, - {0x26u, 0x40u}, - {0x27u, 0x04u}, - {0x29u, 0x42u}, + {0x1Fu, 0x10u}, + {0x20u, 0x04u}, + {0x22u, 0x88u}, + {0x23u, 0x44u}, + {0x26u, 0x21u}, + {0x28u, 0x01u}, + {0x2Au, 0x04u}, + {0x2Bu, 0x84u}, + {0x2Fu, 0x04u}, {0x30u, 0x20u}, - {0x31u, 0x02u}, - {0x32u, 0x48u}, - {0x37u, 0x80u}, - {0x39u, 0x61u}, - {0x3Bu, 0x04u}, - {0x3Du, 0x20u}, - {0x3Eu, 0x04u}, - {0x60u, 0x90u}, + {0x31u, 0x80u}, + {0x33u, 0x06u}, + {0x37u, 0x08u}, + {0x38u, 0x04u}, + {0x39u, 0x03u}, + {0x3Bu, 0x40u}, + {0x40u, 0x02u}, + {0x43u, 0x80u}, + {0x44u, 0x10u}, + {0x45u, 0x08u}, + {0x60u, 0x02u}, {0x61u, 0x20u}, - {0x62u, 0x40u}, - {0x83u, 0x80u}, - {0x84u, 0x05u}, - {0x86u, 0x40u}, - {0x8Au, 0x40u}, - {0x8Cu, 0x10u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x10u}, - {0x90u, 0x20u}, - {0x91u, 0x61u}, - {0x92u, 0x24u}, - {0x93u, 0x14u}, - {0x94u, 0x80u}, + {0x62u, 0x0Au}, + {0x65u, 0x81u}, + {0x66u, 0x10u}, + {0x67u, 0x20u}, + {0x81u, 0x03u}, + {0x82u, 0x01u}, + {0x86u, 0x02u}, + {0x90u, 0x88u}, + {0x91u, 0x50u}, + {0x92u, 0x41u}, + {0x93u, 0x08u}, + {0x94u, 0x04u}, {0x95u, 0x02u}, - {0x96u, 0x82u}, - {0x98u, 0x01u}, - {0x99u, 0x42u}, - {0x9Du, 0x14u}, - {0x9Eu, 0x2Au}, - {0x9Fu, 0x05u}, - {0xA0u, 0x20u}, - {0xA1u, 0x10u}, - {0xA2u, 0x01u}, - {0xA4u, 0x40u}, - {0xA5u, 0x02u}, - {0xA6u, 0x0Au}, - {0xA7u, 0x01u}, - {0xA8u, 0x08u}, - {0xAAu, 0x12u}, - {0xAEu, 0x10u}, - {0xAFu, 0x04u}, - {0xB6u, 0x01u}, - {0xC0u, 0xF7u}, - {0xC2u, 0xBFu}, - {0xC4u, 0xFFu}, - {0xCAu, 0x09u}, - {0xCCu, 0x1Fu}, - {0xCEu, 0x6Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x02u}, - {0xE2u, 0x21u}, - {0xECu, 0x01u}, - {0xEEu, 0x4Cu}, - {0x00u, 0x11u}, - {0x02u, 0x22u}, - {0x07u, 0xFFu}, - {0x08u, 0x0Fu}, - {0x09u, 0x48u}, - {0x0Au, 0xF0u}, - {0x0Bu, 0x84u}, - {0x0Cu, 0x12u}, - {0x0Du, 0x11u}, - {0x0Eu, 0x21u}, - {0x0Fu, 0x22u}, - {0x10u, 0xFFu}, - {0x11u, 0x33u}, - {0x13u, 0xCCu}, - {0x14u, 0x48u}, - {0x16u, 0x84u}, + {0x97u, 0x46u}, + {0x98u, 0x20u}, + {0x99u, 0x62u}, + {0x9Au, 0x46u}, + {0x9Bu, 0x79u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x10u}, + {0xA1u, 0x28u}, + {0xA3u, 0x86u}, + {0xA4u, 0x62u}, + {0xA5u, 0x80u}, + {0xA6u, 0x80u}, + {0xA7u, 0x40u}, + {0xB1u, 0xA0u}, + {0xB3u, 0x04u}, + {0xB4u, 0x40u}, + {0xB7u, 0x08u}, + {0xC0u, 0x7Du}, + {0xC2u, 0x7Fu}, + {0xC4u, 0xFDu}, + {0xCAu, 0x2Fu}, + {0xCCu, 0x4Fu}, + {0xCEu, 0x0Bu}, + {0xD8u, 0xFFu}, + {0xE2u, 0x01u}, + {0xE4u, 0x04u}, + {0xE6u, 0x32u}, + {0xEAu, 0x08u}, + {0xECu, 0x80u}, + {0xEEu, 0x02u}, + {0x01u, 0x96u}, + {0x03u, 0x69u}, + {0x05u, 0x33u}, + {0x06u, 0x0Cu}, + {0x07u, 0xCCu}, + {0x08u, 0x04u}, + {0x0Au, 0xA3u}, + {0x0Bu, 0xFFu}, + {0x0Du, 0xFFu}, + {0x16u, 0x20u}, {0x17u, 0xFFu}, - {0x18u, 0xFFu}, - {0x1Fu, 0xFFu}, - {0x20u, 0x33u}, - {0x21u, 0x12u}, - {0x22u, 0xCCu}, - {0x23u, 0x21u}, - {0x24u, 0x44u}, - {0x25u, 0x44u}, - {0x26u, 0x88u}, - {0x27u, 0x88u}, - {0x29u, 0x0Fu}, - {0x2Au, 0xFFu}, - {0x2Bu, 0xF0u}, - {0x30u, 0xFFu}, - {0x33u, 0xFFu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x04u}, + {0x1Au, 0x12u}, + {0x1Bu, 0xFFu}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x01u}, + {0x1Fu, 0xF0u}, + {0x21u, 0xFFu}, + {0x28u, 0xC8u}, + {0x29u, 0x55u}, + {0x2Au, 0x03u}, + {0x2Bu, 0xAAu}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x62u}, + {0x31u, 0xFFu}, + {0x32u, 0xE0u}, + {0x34u, 0x0Fu}, + {0x36u, 0x10u}, + {0x3Bu, 0x02u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, + {0x5Cu, 0x20u}, {0x5Fu, 0x01u}, - {0x80u, 0x55u}, - {0x81u, 0x0Fu}, - {0x82u, 0xAAu}, - {0x83u, 0xF0u}, - {0x84u, 0x33u}, - {0x86u, 0xCCu}, - {0x87u, 0xFFu}, - {0x89u, 0x33u}, - {0x8Bu, 0xCCu}, - {0x8Eu, 0xFFu}, - {0x90u, 0x0Fu}, - {0x92u, 0xF0u}, - {0x93u, 0xFFu}, - {0x95u, 0xFFu}, - {0x99u, 0x69u}, - {0x9Au, 0xFFu}, - {0x9Bu, 0x96u}, - {0x9Cu, 0xFFu}, + {0x84u, 0x80u}, + {0x85u, 0x44u}, + {0x87u, 0x88u}, + {0x89u, 0x48u}, + {0x8Bu, 0x84u}, + {0x8Cu, 0x4Du}, + {0x8Du, 0x33u}, + {0x8Eu, 0xB2u}, + {0x8Fu, 0xCCu}, + {0x91u, 0x12u}, + {0x93u, 0x21u}, + {0x98u, 0x40u}, + {0x99u, 0x11u}, + {0x9Bu, 0x22u}, + {0x9Cu, 0x20u}, {0x9Du, 0xFFu}, - {0xA6u, 0xFFu}, - {0xA8u, 0xFFu}, - {0xABu, 0xFFu}, - {0xACu, 0x69u}, - {0xADu, 0x55u}, - {0xAEu, 0x96u}, - {0xAFu, 0xAAu}, - {0xB0u, 0xFFu}, - {0xB1u, 0xFFu}, - {0xBAu, 0x02u}, - {0xBBu, 0x02u}, + {0x9Eu, 0x10u}, + {0xA0u, 0x12u}, + {0xA1u, 0x0Fu}, + {0xA2u, 0x20u}, + {0xA3u, 0xF0u}, + {0xA4u, 0x05u}, + {0xA6u, 0x08u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x08u}, + {0xAAu, 0x04u}, + {0xADu, 0xFFu}, + {0xB0u, 0x3Cu}, + {0xB2u, 0xC0u}, + {0xB3u, 0xFFu}, + {0xB4u, 0x03u}, + {0xB9u, 0x02u}, + {0xBEu, 0x15u}, + {0xBFu, 0x05u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x22u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x02u, 0x40u}, + {0x01u, 0x44u}, {0x03u, 0x02u}, - {0x04u, 0x02u}, - {0x05u, 0x22u}, - {0x06u, 0x02u}, - {0x0Au, 0x81u}, - {0x0Bu, 0x08u}, - {0x0Eu, 0x80u}, - {0x0Fu, 0x28u}, - {0x12u, 0x19u}, - {0x14u, 0x04u}, - {0x15u, 0x04u}, - {0x17u, 0x01u}, - {0x19u, 0x01u}, + {0x04u, 0x04u}, + {0x05u, 0x20u}, + {0x08u, 0x20u}, + {0x0Au, 0x01u}, + {0x0Du, 0x80u}, + {0x0Eu, 0x18u}, + {0x12u, 0x10u}, + {0x13u, 0x21u}, + {0x15u, 0x20u}, + {0x16u, 0x02u}, + {0x18u, 0x08u}, {0x1Au, 0x80u}, - {0x1Eu, 0x40u}, - {0x21u, 0x01u}, - {0x27u, 0x20u}, - {0x28u, 0x02u}, - {0x2Au, 0x10u}, - {0x2Du, 0x24u}, - {0x2Eu, 0x02u}, - {0x32u, 0x28u}, - {0x33u, 0x82u}, - {0x34u, 0x04u}, - {0x36u, 0xC4u}, - {0x37u, 0x01u}, - {0x39u, 0x02u}, - {0x3Bu, 0x18u}, - {0x3Cu, 0x40u}, - {0x3Du, 0x10u}, - {0x3Fu, 0x28u}, - {0x49u, 0x40u}, - {0x4Bu, 0x80u}, - {0x58u, 0x20u}, - {0x5Bu, 0x40u}, - {0x5Cu, 0x80u}, - {0x5Du, 0x01u}, - {0x5Eu, 0x24u}, - {0x60u, 0x08u}, - {0x61u, 0x50u}, - {0x67u, 0x02u}, - {0x80u, 0x08u}, - {0x86u, 0x04u}, - {0x8Cu, 0x40u}, - {0x8Du, 0x06u}, - {0x8Fu, 0x02u}, - {0x90u, 0x04u}, - {0x92u, 0x01u}, - {0x93u, 0x1Au}, - {0x94u, 0x22u}, - {0x95u, 0x0Eu}, - {0x96u, 0x40u}, - {0x98u, 0x12u}, - {0x99u, 0x20u}, - {0x9Au, 0x53u}, - {0x9Bu, 0x11u}, - {0x9Du, 0x51u}, - {0x9Eu, 0x0Cu}, - {0x9Fu, 0x20u}, - {0xA0u, 0x08u}, - {0xA2u, 0xACu}, - {0xA3u, 0xC4u}, - {0xA4u, 0x82u}, - {0xA5u, 0x2Au}, - {0xA6u, 0x41u}, - {0xA7u, 0x10u}, - {0xAAu, 0x40u}, - {0xABu, 0x80u}, - {0xB1u, 0x40u}, - {0xB2u, 0x10u}, - {0xB7u, 0x21u}, - {0xC0u, 0xDDu}, - {0xC2u, 0x7Bu}, - {0xC4u, 0x77u}, - {0xCAu, 0xECu}, - {0xCCu, 0xDFu}, - {0xCEu, 0x77u}, - {0xD6u, 0xFCu}, - {0xD8u, 0x1Cu}, - {0xE0u, 0x50u}, - {0xE4u, 0x40u}, - {0xEEu, 0x08u}, - {0x00u, 0x96u}, - {0x02u, 0x69u}, - {0x05u, 0x88u}, - {0x07u, 0x03u}, - {0x08u, 0x0Fu}, - {0x09u, 0x21u}, - {0x0Au, 0xF0u}, - {0x0Bu, 0x02u}, - {0x0Eu, 0xFFu}, - {0x10u, 0x55u}, - {0x12u, 0xAAu}, - {0x13u, 0x01u}, - {0x14u, 0x33u}, - {0x15u, 0xE0u}, - {0x16u, 0xCCu}, - {0x1Au, 0xFFu}, - {0x1Bu, 0xECu}, - {0x1Cu, 0xFFu}, - {0x21u, 0x04u}, - {0x23u, 0x43u}, - {0x26u, 0xFFu}, - {0x27u, 0x12u}, - {0x28u, 0xFFu}, - {0x31u, 0x10u}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x90u}, + {0x1Eu, 0x10u}, + {0x20u, 0x20u}, + {0x22u, 0x02u}, + {0x24u, 0x80u}, + {0x27u, 0x80u}, + {0x29u, 0x80u}, + {0x2Bu, 0xA0u}, + {0x2Du, 0x01u}, + {0x2Fu, 0x04u}, + {0x32u, 0x51u}, + {0x34u, 0x08u}, + {0x37u, 0x90u}, + {0x39u, 0x54u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x0Au}, + {0x48u, 0x04u}, + {0x4Au, 0x08u}, + {0x58u, 0x80u}, + {0x63u, 0x02u}, + {0x69u, 0x14u}, + {0x6Au, 0x01u}, + {0x6Bu, 0x01u}, + {0x73u, 0x55u}, + {0x80u, 0x20u}, + {0x81u, 0x87u}, + {0x82u, 0x50u}, + {0x87u, 0x10u}, + {0x8Au, 0x02u}, + {0x8Eu, 0x10u}, + {0x91u, 0x81u}, + {0x92u, 0x02u}, + {0x93u, 0x28u}, + {0x94u, 0x88u}, + {0x95u, 0x14u}, + {0x97u, 0xD4u}, + {0x98u, 0x98u}, + {0x99u, 0x02u}, + {0x9Au, 0x32u}, + {0x9Bu, 0x14u}, + {0x9Du, 0x38u}, + {0x9Eu, 0x80u}, + {0xA0u, 0x02u}, + {0xA1u, 0x40u}, + {0xA2u, 0x0Cu}, + {0xA3u, 0xE6u}, + {0xA4u, 0x50u}, + {0xA5u, 0x01u}, + {0xA9u, 0x80u}, + {0xABu, 0x08u}, + {0xAFu, 0x40u}, + {0xB0u, 0x18u}, + {0xB4u, 0x04u}, + {0xB7u, 0x04u}, + {0xC0u, 0x65u}, + {0xC2u, 0xE3u}, + {0xC4u, 0xCEu}, + {0xCAu, 0xABu}, + {0xCCu, 0x7Du}, + {0xCEu, 0xFEu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE0u, 0x04u}, + {0xE6u, 0x30u}, + {0xE8u, 0xA0u}, + {0xECu, 0x50u}, + {0xEEu, 0x02u}, + {0x00u, 0x0Fu}, + {0x02u, 0xF0u}, + {0x05u, 0x44u}, + {0x06u, 0xFFu}, + {0x07u, 0x88u}, + {0x09u, 0x84u}, + {0x0Bu, 0x48u}, + {0x0Cu, 0x33u}, + {0x0Eu, 0xCCu}, + {0x11u, 0x21u}, + {0x12u, 0xFFu}, + {0x13u, 0x12u}, + {0x16u, 0xFFu}, + {0x17u, 0xFFu}, + {0x18u, 0x11u}, + {0x1Au, 0x22u}, + {0x1Bu, 0xFFu}, + {0x1Cu, 0x12u}, + {0x1Du, 0xFFu}, + {0x1Eu, 0x21u}, + {0x21u, 0x0Fu}, + {0x23u, 0xF0u}, + {0x24u, 0x44u}, + {0x25u, 0x11u}, + {0x26u, 0x88u}, + {0x27u, 0x22u}, + {0x28u, 0x48u}, + {0x2Au, 0x84u}, + {0x2Du, 0x33u}, + {0x2Fu, 0xCCu}, + {0x31u, 0xFFu}, {0x32u, 0xFFu}, - {0x35u, 0x0Fu}, - {0x37u, 0xE0u}, - {0x3Au, 0x08u}, - {0x3Fu, 0x40u}, - {0x56u, 0x08u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x02u}, - {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x84u, 0x02u}, - {0x86u, 0x09u}, + {0x81u, 0x10u}, + {0x85u, 0x04u}, {0x87u, 0x01u}, - {0x89u, 0xE0u}, - {0x8Cu, 0x02u}, - {0x8Eu, 0x05u}, - {0x93u, 0xECu}, - {0x94u, 0x01u}, - {0x95u, 0x88u}, - {0x96u, 0x02u}, - {0x97u, 0x03u}, - {0x98u, 0x02u}, + {0x88u, 0x18u}, + {0x8Au, 0x23u}, + {0x8Bu, 0x04u}, + {0x8Fu, 0x04u}, + {0x91u, 0x40u}, + {0x95u, 0x28u}, + {0x96u, 0x0Cu}, + {0x97u, 0x50u}, + {0x99u, 0x08u}, {0x9Au, 0x01u}, - {0x9Cu, 0x02u}, - {0x9Eu, 0x01u}, - {0xA3u, 0x12u}, - {0xA5u, 0x04u}, - {0xA7u, 0x43u}, - {0xA9u, 0x21u}, - {0xABu, 0x02u}, - {0xB2u, 0x03u}, - {0xB3u, 0xE0u}, - {0xB4u, 0x08u}, - {0xB5u, 0x10u}, - {0xB6u, 0x04u}, - {0xB7u, 0x0Fu}, - {0xBAu, 0x08u}, - {0xBFu, 0x04u}, - {0xD6u, 0x08u}, + {0x9Bu, 0x03u}, + {0x9Cu, 0x11u}, + {0x9Du, 0x20u}, + {0x9Eu, 0x22u}, + {0xA1u, 0x04u}, + {0xA2u, 0x42u}, + {0xA3u, 0x02u}, + {0xA4u, 0x34u}, + {0xA6u, 0x03u}, + {0xADu, 0x80u}, + {0xB0u, 0x20u}, + {0xB1u, 0x80u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x60u}, + {0xB4u, 0x40u}, + {0xB5u, 0x07u}, + {0xB6u, 0x10u}, + {0xB7u, 0x18u}, + {0xBEu, 0x41u}, + {0xBFu, 0x45u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x12u}, - {0xDDu, 0x90u}, + {0xDCu, 0x21u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x01u}, - {0x03u, 0x0Au}, - {0x05u, 0x80u}, - {0x07u, 0x10u}, - {0x08u, 0x08u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x88u}, - {0x0Eu, 0x2Au}, - {0x12u, 0x18u}, - {0x18u, 0x20u}, - {0x1Bu, 0x08u}, - {0x1Eu, 0x2Au}, - {0x22u, 0x11u}, - {0x23u, 0x02u}, - {0x24u, 0x04u}, - {0x25u, 0x04u}, - {0x27u, 0x01u}, - {0x28u, 0x10u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x08u}, - {0x2Eu, 0x10u}, - {0x2Fu, 0x80u}, - {0x30u, 0x08u}, - {0x32u, 0x11u}, - {0x35u, 0x04u}, - {0x37u, 0x01u}, - {0x39u, 0x08u}, - {0x3Bu, 0x20u}, - {0x3Cu, 0x24u}, - {0x58u, 0x40u}, - {0x5Eu, 0x40u}, - {0x60u, 0x01u}, - {0x65u, 0x80u}, - {0x68u, 0x82u}, - {0x69u, 0x14u}, - {0x71u, 0x2Au}, - {0x73u, 0x01u}, - {0x82u, 0x50u}, - {0x84u, 0x40u}, + {0x03u, 0xA2u}, + {0x07u, 0x04u}, + {0x08u, 0x20u}, + {0x09u, 0x04u}, + {0x0Au, 0x82u}, + {0x0Du, 0x40u}, + {0x0Eu, 0x18u}, + {0x11u, 0x14u}, + {0x14u, 0x10u}, + {0x15u, 0x02u}, + {0x19u, 0x08u}, + {0x1Cu, 0x20u}, + {0x1Du, 0x40u}, + {0x1Eu, 0x58u}, + {0x20u, 0x80u}, + {0x24u, 0x02u}, + {0x25u, 0x0Eu}, + {0x26u, 0x20u}, + {0x28u, 0x20u}, + {0x2Bu, 0x82u}, + {0x2Cu, 0x02u}, + {0x2Du, 0x01u}, + {0x31u, 0x08u}, + {0x32u, 0x41u}, + {0x33u, 0x20u}, + {0x36u, 0xA8u}, + {0x37u, 0x21u}, + {0x39u, 0x14u}, + {0x3Cu, 0x08u}, + {0x3Eu, 0x21u}, + {0x3Fu, 0x80u}, + {0x5Du, 0x02u}, + {0x5Eu, 0x64u}, + {0x65u, 0x40u}, + {0x67u, 0x80u}, + {0x82u, 0x08u}, + {0x83u, 0x22u}, {0x88u, 0x10u}, - {0x8Bu, 0x80u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x04u}, - {0x8Fu, 0x03u}, - {0x91u, 0x08u}, - {0x92u, 0x01u}, - {0x93u, 0xA8u}, - {0x94u, 0x20u}, - {0x95u, 0x14u}, - {0x98u, 0x18u}, - {0x99u, 0x0Cu}, - {0x9Au, 0x10u}, - {0x9Bu, 0x10u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x08u}, - {0xA2u, 0x08u}, - {0xA3u, 0x42u}, - {0xA4u, 0x82u}, - {0xA5u, 0x2Au}, - {0xA6u, 0x11u}, - {0xABu, 0x40u}, - {0xADu, 0x01u}, - {0xAFu, 0x02u}, - {0xB1u, 0x0Cu}, - {0xB2u, 0x08u}, - {0xB3u, 0x10u}, - {0xB4u, 0xA0u}, - {0xC0u, 0xABu}, + {0x89u, 0x01u}, + {0x8Au, 0x14u}, + {0x8Cu, 0x01u}, + {0x91u, 0x95u}, + {0x92u, 0x83u}, + {0x97u, 0x80u}, + {0x98u, 0x30u}, + {0x99u, 0x02u}, + {0x9Au, 0x20u}, + {0x9Bu, 0x05u}, + {0x9Du, 0x08u}, + {0x9Fu, 0x20u}, + {0xA0u, 0x06u}, + {0xA2u, 0x80u}, + {0xA3u, 0xE2u}, + {0xA4u, 0x40u}, + {0xA5u, 0x06u}, + {0xAEu, 0x80u}, + {0xAFu, 0x08u}, + {0xB1u, 0x30u}, + {0xB2u, 0x80u}, + {0xC0u, 0x4Du}, {0xC2u, 0xEFu}, - {0xC4u, 0x06u}, - {0xCAu, 0xE3u}, - {0xCCu, 0xC7u}, - {0xCEu, 0x66u}, - {0xD6u, 0x18u}, - {0xD8u, 0x18u}, - {0xE0u, 0x80u}, - {0xE2u, 0x10u}, - {0xE4u, 0x80u}, - {0xE6u, 0x48u}, - {0xE8u, 0xB0u}, - {0xECu, 0x80u}, - {0xEEu, 0x01u}, - {0x06u, 0x08u}, - {0x0Cu, 0x10u}, - {0x0Eu, 0x40u}, - {0x11u, 0x10u}, - {0x13u, 0x08u}, - {0x16u, 0x80u}, - {0x17u, 0x40u}, - {0x30u, 0x40u}, + {0xC4u, 0x36u}, + {0xCAu, 0x9Bu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xF6u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x90u}, + {0xE0u, 0xA0u}, + {0xE4u, 0x20u}, + {0xE6u, 0x80u}, + {0xE8u, 0x20u}, + {0xECu, 0x22u}, + {0x04u, 0x40u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x40u}, + {0x12u, 0x20u}, + {0x13u, 0x10u}, + {0x17u, 0x81u}, + {0x19u, 0x01u}, + {0x1Du, 0x04u}, + {0x30u, 0x10u}, {0x33u, 0x01u}, - {0x36u, 0x22u}, - {0x3Au, 0x81u}, - {0x3Du, 0x44u}, - {0x40u, 0x04u}, - {0x53u, 0x02u}, - {0x5Fu, 0x40u}, - {0x6Bu, 0x09u}, - {0x82u, 0x01u}, + {0x36u, 0x20u}, + {0x37u, 0x02u}, + {0x39u, 0x04u}, + {0x3Bu, 0x10u}, + {0x3Du, 0x01u}, + {0x3Eu, 0x80u}, + {0x42u, 0x08u}, + {0x50u, 0x20u}, + {0x56u, 0x20u}, + {0x89u, 0x01u}, {0xC0u, 0x80u}, {0xC2u, 0xA0u}, {0xC4u, 0xF0u}, + {0xC6u, 0x30u}, {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x80u}, - {0xD6u, 0x20u}, - {0xE2u, 0x20u}, - {0x00u, 0x10u}, - {0x0Au, 0x02u}, - {0x30u, 0x08u}, - {0x33u, 0x20u}, - {0x36u, 0x08u}, - {0x37u, 0x40u}, - {0x39u, 0x80u}, - {0x59u, 0x40u}, - {0x61u, 0x20u}, - {0x82u, 0x08u}, - {0x85u, 0x10u}, - {0x86u, 0x02u}, - {0x87u, 0x20u}, - {0x88u, 0x08u}, - {0x89u, 0x40u}, - {0x91u, 0x10u}, - {0x92u, 0x40u}, - {0x94u, 0x04u}, + {0xD4u, 0x60u}, + {0x03u, 0x02u}, + {0x0Au, 0x01u}, + {0x31u, 0x01u}, + {0x32u, 0x40u}, + {0x35u, 0x04u}, + {0x37u, 0x80u}, + {0x39u, 0x08u}, + {0x3Bu, 0x20u}, + {0x3Fu, 0x80u}, + {0x54u, 0x08u}, + {0x5Fu, 0x01u}, + {0x80u, 0x40u}, + {0x90u, 0x40u}, + {0x93u, 0x40u}, {0x95u, 0x04u}, - {0x97u, 0x40u}, - {0x98u, 0x10u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x40u}, - {0xA1u, 0x20u}, - {0xA6u, 0x22u}, - {0xA7u, 0x02u}, - {0xA9u, 0x20u}, - {0xB5u, 0x40u}, + {0x99u, 0x05u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x02u}, + {0xA2u, 0x04u}, + {0xA8u, 0x20u}, + {0xB6u, 0x08u}, {0xC0u, 0x40u}, {0xC2u, 0x40u}, {0xCCu, 0xF0u}, - {0xCEu, 0x10u}, - {0xD4u, 0x80u}, - {0xD8u, 0x40u}, - {0xE2u, 0x60u}, - {0xEAu, 0x20u}, - {0x10u, 0x40u}, - {0x33u, 0x80u}, - {0x81u, 0x20u}, - {0x88u, 0x10u}, - {0x8Eu, 0x20u}, - {0x92u, 0x42u}, - {0x94u, 0x04u}, - {0x95u, 0x84u}, - {0x97u, 0x40u}, - {0x98u, 0x10u}, - {0x9Au, 0x08u}, - {0x9Cu, 0x40u}, - {0xA6u, 0x20u}, - {0xB4u, 0x10u}, - {0xB7u, 0x02u}, + {0xCEu, 0x70u}, + {0xD4u, 0x40u}, + {0xD6u, 0x80u}, + {0xE4u, 0x20u}, + {0xEAu, 0x80u}, + {0x10u, 0x10u}, + {0x33u, 0x10u}, + {0x34u, 0x08u}, + {0x37u, 0x80u}, + {0x52u, 0x20u}, + {0x80u, 0x08u}, + {0x8Au, 0x28u}, + {0x93u, 0x40u}, + {0x95u, 0x0Cu}, + {0x96u, 0x80u}, + {0x97u, 0x21u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x02u}, + {0xA3u, 0x02u}, + {0xA4u, 0x08u}, + {0xA7u, 0x40u}, + {0xAEu, 0x01u}, + {0xB6u, 0x04u}, {0xC4u, 0x10u}, - {0xCCu, 0x10u}, - {0xE6u, 0x80u}, - {0x86u, 0x01u}, - {0x8Du, 0x80u}, - {0x92u, 0x42u}, - {0x94u, 0x04u}, - {0x95u, 0x04u}, - {0x97u, 0x40u}, - {0x99u, 0x20u}, - {0x9Au, 0x08u}, - {0xA7u, 0x80u}, - {0xA9u, 0x40u}, - {0xE4u, 0x40u}, + {0xCCu, 0xB0u}, + {0xD4u, 0x20u}, + {0xE2u, 0x80u}, + {0xE8u, 0x10u}, + {0x80u, 0x08u}, + {0x83u, 0x10u}, + {0x85u, 0x04u}, + {0x95u, 0x0Cu}, + {0x96u, 0x80u}, + {0x97u, 0x21u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x12u}, + {0xA3u, 0x02u}, + {0xA6u, 0x08u}, + {0xA7u, 0x40u}, + {0xABu, 0x80u}, + {0xAFu, 0x40u}, + {0xE2u, 0x20u}, + {0xE6u, 0x60u}, {0xEAu, 0x80u}, - {0x05u, 0x08u}, - {0x06u, 0x08u}, - {0x09u, 0x01u}, - {0x0Bu, 0x02u}, - {0x11u, 0x04u}, - {0x56u, 0x04u}, - {0x5Bu, 0x02u}, - {0x65u, 0x40u}, - {0x78u, 0x80u}, + {0xECu, 0x40u}, + {0x04u, 0x80u}, + {0x05u, 0x04u}, + {0x08u, 0x40u}, + {0x0Au, 0x20u}, + {0x10u, 0x20u}, + {0x53u, 0x01u}, + {0x58u, 0x01u}, + {0x60u, 0x04u}, + {0x80u, 0x20u}, + {0x83u, 0x01u}, + {0x8Eu, 0x10u}, {0xC0u, 0x05u}, {0xC2u, 0x0Au}, {0xC4u, 0x08u}, - {0xD4u, 0x02u}, - {0xD6u, 0x03u}, - {0xDCu, 0x01u}, - {0x01u, 0x42u}, - {0x09u, 0x04u}, - {0x0Au, 0x01u}, - {0x52u, 0x02u}, - {0x57u, 0x01u}, - {0x66u, 0x82u}, - {0x80u, 0x02u}, - {0x86u, 0x82u}, - {0x87u, 0x02u}, - {0x89u, 0x08u}, - {0x8Eu, 0x02u}, - {0x91u, 0x04u}, - {0x93u, 0x02u}, - {0x99u, 0x08u}, - {0x9Au, 0x08u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x04u}, - {0x9Fu, 0x02u}, - {0xA5u, 0x04u}, - {0xA9u, 0x05u}, - {0xACu, 0x80u}, - {0xADu, 0x40u}, + {0xD4u, 0x01u}, + {0xD6u, 0x02u}, + {0xD8u, 0x02u}, + {0xE2u, 0x02u}, + {0x00u, 0x48u}, + {0x08u, 0x40u}, + {0x0Bu, 0x10u}, + {0x57u, 0x0Au}, + {0x61u, 0x90u}, + {0x80u, 0x40u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x40u}, + {0x90u, 0x80u}, + {0x94u, 0x04u}, + {0x99u, 0x04u}, + {0x9Cu, 0x01u}, + {0xB0u, 0x40u}, {0xC0u, 0x0Au}, {0xC2u, 0x0Au}, - {0xD4u, 0x01u}, - {0xD6u, 0x05u}, - {0xD8u, 0x01u}, - {0xE4u, 0x08u}, - {0xE6u, 0x04u}, - {0x54u, 0x20u}, - {0x87u, 0x01u}, - {0x91u, 0x04u}, - {0x92u, 0x01u}, - {0x93u, 0x02u}, - {0x99u, 0x0Au}, - {0x9Au, 0x08u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x20u}, - {0xA4u, 0x02u}, - {0xA5u, 0x08u}, - {0xA7u, 0x01u}, - {0xACu, 0x20u}, - {0xB5u, 0x40u}, {0xD4u, 0x02u}, - {0xEAu, 0x02u}, - {0x09u, 0x08u}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x02u}, - {0x0Fu, 0x02u}, - {0x82u, 0x04u}, - {0x85u, 0x40u}, - {0x86u, 0x01u}, - {0x89u, 0x04u}, - {0x8Fu, 0x01u}, - {0x91u, 0x04u}, - {0x92u, 0x01u}, - {0x93u, 0x02u}, - {0x97u, 0x01u}, - {0x99u, 0x0Au}, - {0x9Au, 0x08u}, - {0x9Du, 0x40u}, - {0x9Eu, 0x04u}, - {0xA4u, 0x02u}, - {0xA5u, 0x08u}, - {0xABu, 0x01u}, + {0xD6u, 0x06u}, + {0xD8u, 0x02u}, + {0xE2u, 0x02u}, + {0xE6u, 0x01u}, + {0xEAu, 0x01u}, + {0x56u, 0x80u}, + {0x81u, 0x80u}, + {0x87u, 0x0Au}, + {0x94u, 0x04u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x10u}, + {0xA0u, 0x04u}, + {0xA5u, 0x80u}, + {0xA7u, 0x0Au}, + {0xA8u, 0x04u}, + {0xA9u, 0x04u}, + {0xACu, 0x40u}, + {0xD4u, 0x02u}, + {0x09u, 0x10u}, + {0x0Bu, 0x40u}, + {0x0Fu, 0x88u}, + {0x83u, 0x44u}, + {0x88u, 0x01u}, + {0x94u, 0x04u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x10u}, + {0xA5u, 0x10u}, + {0xA9u, 0x10u}, + {0xACu, 0x04u}, + {0xAEu, 0x80u}, {0xC2u, 0x0Fu}, - {0xE2u, 0x06u}, - {0x01u, 0x80u}, - {0x65u, 0x04u}, - {0x8Bu, 0x40u}, - {0x92u, 0x40u}, - {0x95u, 0x04u}, - {0x97u, 0x40u}, - {0x99u, 0x20u}, - {0x9Du, 0x80u}, - {0xAAu, 0x08u}, - {0xAFu, 0x80u}, - {0xB4u, 0x04u}, + {0xE4u, 0x04u}, + {0x02u, 0x08u}, + {0x66u, 0x10u}, + {0x82u, 0x40u}, + {0x83u, 0x41u}, + {0x86u, 0x80u}, + {0x87u, 0x10u}, + {0x8Au, 0x10u}, + {0x8Cu, 0x01u}, + {0x96u, 0x80u}, + {0x97u, 0x01u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x02u}, + {0xA6u, 0x08u}, + {0xA7u, 0x40u}, + {0xADu, 0x04u}, + {0xAFu, 0x10u}, + {0xB3u, 0x02u}, {0xC0u, 0x40u}, {0xD8u, 0x80u}, - {0xECu, 0x80u}, - {0xEEu, 0x10u}, - {0x03u, 0x20u}, - {0x51u, 0x02u}, - {0x56u, 0x20u}, - {0x5Bu, 0x02u}, - {0x65u, 0x20u}, - {0x77u, 0x10u}, + {0xE2u, 0xE0u}, + {0xE6u, 0xC0u}, + {0xEAu, 0x10u}, + {0xEEu, 0x40u}, + {0x02u, 0x10u}, + {0x57u, 0x08u}, + {0x5Au, 0x40u}, + {0x5Cu, 0x01u}, + {0x67u, 0x20u}, {0x82u, 0x40u}, - {0x87u, 0x20u}, - {0x8Du, 0x02u}, + {0x86u, 0x10u}, + {0x87u, 0x08u}, {0x8Eu, 0x20u}, - {0x8Fu, 0x02u}, - {0x92u, 0x40u}, - {0x99u, 0x20u}, - {0x9Bu, 0x10u}, - {0xA9u, 0x04u}, - {0xABu, 0x10u}, - {0xADu, 0x04u}, + {0x90u, 0x01u}, + {0x93u, 0x20u}, + {0x9Eu, 0x20u}, + {0xB7u, 0x02u}, {0xC0u, 0x10u}, {0xD4u, 0xC0u}, - {0xD6u, 0x40u}, + {0xD6u, 0x80u}, {0xD8u, 0x80u}, - {0xDEu, 0x20u}, - {0xE0u, 0x20u}, - {0xE4u, 0x10u}, - {0xEAu, 0x20u}, - {0xEEu, 0xC0u}, - {0x99u, 0x0Au}, - {0x9Au, 0x08u}, - {0xAFu, 0x01u}, - {0x85u, 0x08u}, - {0x99u, 0x08u}, - {0xAAu, 0x08u}, - {0xB5u, 0x02u}, - {0xEAu, 0x02u}, + {0xE0u, 0x40u}, + {0xE2u, 0x20u}, + {0xE6u, 0x40u}, + {0x80u, 0x04u}, + {0x94u, 0x04u}, + {0x9Du, 0x10u}, + {0xAFu, 0x40u}, + {0x74u, 0x04u}, + {0x8Du, 0x10u}, + {0x9Du, 0x10u}, + {0xA0u, 0x04u}, + {0xACu, 0x04u}, + {0xDEu, 0x04u}, + {0xE0u, 0x02u}, {0x10u, 0x07u}, {0x11u, 0x01u}, - {0x1Au, 0x07u}, + {0x1Au, 0x03u}, + {0x1Bu, 0x01u}, {0x1Cu, 0x07u}, {0x1Du, 0x01u}, - {0x00u, 0xFFu}, - {0x01u, 0xBFu}, - {0x02u, 0x2Au}, - {0x10u, 0x95u}, + {0x10u, 0x59u}, + {0x11u, 0x09u}, }; @@ -2502,34 +2534,39 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; + /* IDMUX_IRQ Address: CYREG_IDMUX_IRQ_CTL0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IDMUX_IRQ_VAL[] = { + 0xFFu, 0xFFu, 0xABu, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { - 0x00u, 0x24u, 0x00u, 0x12u, 0x08u, 0x00u, 0x61u, 0x20u, 0x00u, 0x00u, 0x40u, 0x04u, 0x07u, 0x00u, 0xD8u, 0x24u, - 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x03u, 0x04u, 0x00u, 0x00u, 0x18u, 0x01u, 0x00u, 0x00u, 0x00u, - 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0xA2u, 0x24u, 0x08u, 0x09u, 0x01u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0xE0u, 0x07u, 0x3Fu, 0x38u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, - 0x63u, 0x04u, 0x50u, 0x00u, 0x02u, 0xCEu, 0xBFu, 0xD0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x20u, 0x00u, 0x00u, 0x01u, + 0x34u, 0x00u, 0x40u, 0x00u, 0x3Du, 0x30u, 0x42u, 0x00u, 0x03u, 0x00u, 0x0Cu, 0x00u, 0x40u, 0x15u, 0x80u, 0x0Au, + 0x10u, 0x00u, 0x20u, 0x00u, 0x00u, 0x09u, 0x00u, 0x16u, 0x00u, 0x04u, 0x77u, 0x03u, 0x10u, 0x00u, 0x20u, 0x00u, + 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x8Bu, 0x0Bu, 0x74u, 0x24u, 0x88u, 0x00u, 0x77u, 0x00u, + 0x30u, 0x00u, 0x00u, 0x38u, 0x0Fu, 0x07u, 0xC0u, 0x00u, 0x00u, 0x08u, 0xA2u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x52u, 0x04u, 0x60u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0xBCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x12u, 0x10u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0x5Cu, 0x00u, 0x00u, 0x00u, 0x30u, 0x05u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x01u, 0x50u, 0x06u, - 0x11u, 0x04u, 0x22u, 0x03u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0x54u, 0x00u, 0x08u, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u, 0x0Cu, 0x00u, 0x24u, 0x00u, 0x10u, 0x00u, 0x08u, 0x03u, 0x00u, 0x04u, - 0x0Fu, 0x07u, 0x40u, 0x00u, 0x30u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x20u, 0x02u, 0x00u, 0x00u, 0x44u, 0x00u, - 0x16u, 0x04u, 0x30u, 0x00u, 0x05u, 0xBEu, 0xF0u, 0xCDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x11u, 0x11u, 0x00u, 0x01u, + 0x02u, 0x00u, 0x00u, 0x00u, 0x02u, 0x80u, 0x00u, 0x00u, 0x10u, 0xC0u, 0x42u, 0x08u, 0x01u, 0x7Fu, 0x00u, 0x80u, + 0x44u, 0x90u, 0x10u, 0x40u, 0x01u, 0x1Fu, 0x00u, 0x20u, 0x02u, 0xC0u, 0x00u, 0x04u, 0x02u, 0xC0u, 0x00u, 0x02u, + 0x08u, 0xC0u, 0x00u, 0x01u, 0x20u, 0x00u, 0x00u, 0x9Fu, 0x0Eu, 0x00u, 0x30u, 0xFFu, 0x02u, 0x00u, 0x00u, 0x60u, + 0x01u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x7Eu, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x04u, + 0x64u, 0x03u, 0x50u, 0x00u, 0x02u, 0xCBu, 0xF0u, 0xEDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x01u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u}; + 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ + {(void CYFAR *)(CYREG_IDMUX_IRQ_CTL0), BS_IDMUX_IRQ_VAL, 8u}, {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, @@ -2561,6 +2598,8 @@ void cyfitter_cfg(void) CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM4_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM4_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM5_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM5_VAL), 4u); /* Enable digital routing */ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 972fcf3..92ae462 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -192,34 +192,34 @@ .set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_MASK, 0x200 +.set USBFS_ep_1__INTC_NUMBER, 9 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_MASK, 0x400 +.set USBFS_ep_2__INTC_NUMBER, 10 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_MASK, 0x800 +.set USBFS_ep_3__INTC_NUMBER, 11 .set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_11 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_MASK, 0x2000 +.set USBFS_ep_4__INTC_NUMBER, 13 .set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_13 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -424,34 +424,34 @@ .set NOR_SO__SLW, CYREG_PRT15_SLW /* SDCard */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -459,9 +459,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -485,8 +485,6 @@ .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -494,9 +492,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1 @@ -567,34 +565,34 @@ .set NOR_SCK__SLW, CYREG_PRT3_SLW /* NOR_SPI */ -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_RxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20 @@ -602,9 +600,9 @@ .set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40 .set NOR_SPI_BSPIM_RxStsReg__6__POS, 6 .set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70 -.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK -.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST +.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST .set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 .set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 .set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 @@ -628,8 +626,8 @@ .set NOR_SPI_BSPIM_TxStsReg__0__POS, 0 .set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02 .set NOR_SPI_BSPIM_TxStsReg__1__POS, 1 -.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04 .set NOR_SPI_BSPIM_TxStsReg__2__POS, 2 .set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08 @@ -637,9 +635,9 @@ .set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_TxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F -.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB03_MSK -.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB03_ST +.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST /* SCSI_In */ .set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1 @@ -1760,15 +1758,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1781,15 +1779,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL @@ -2269,42 +2267,42 @@ .set NOR_Clock__PM_STBY_MSK, 0x01 /* SD_RX_DMA */ -.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SD_RX_DMA__DRQ_NUMBER, 2 +.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL1 +.set SD_RX_DMA__DRQ_NUMBER, 4 .set SD_RX_DMA__NUMBEROF_TDS, 0 .set SD_RX_DMA__PRIORITY, 0 .set SD_RX_DMA__TERMIN_EN, 0 .set SD_RX_DMA__TERMIN_SEL, 0 .set SD_RX_DMA__TERMOUT0_EN, 1 -.set SD_RX_DMA__TERMOUT0_SEL, 2 +.set SD_RX_DMA__TERMOUT0_SEL, 4 .set SD_RX_DMA__TERMOUT1_EN, 0 .set SD_RX_DMA__TERMOUT1_SEL, 0 .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 -.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x80 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 7 .set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SD_TX_DMA */ -.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SD_TX_DMA__DRQ_NUMBER, 3 +.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL1 +.set SD_TX_DMA__DRQ_NUMBER, 5 .set SD_TX_DMA__NUMBEROF_TDS, 0 .set SD_TX_DMA__PRIORITY, 1 .set SD_TX_DMA__TERMIN_EN, 0 .set SD_TX_DMA__TERMIN_SEL, 0 .set SD_TX_DMA__TERMOUT0_EN, 1 -.set SD_TX_DMA__TERMOUT0_SEL, 3 +.set SD_TX_DMA__TERMOUT0_SEL, 5 .set SD_TX_DMA__TERMOUT1_EN, 0 .set SD_TX_DMA__TERMOUT1_SEL, 0 .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 -.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x100 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 8 .set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2341,6 +2339,46 @@ .set nNOR_HOLD__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ .set nNOR_HOLD__SLW, CYREG_PRT12_SLW +/* NOR_RX_DMA */ +.set NOR_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set NOR_RX_DMA__DRQ_NUMBER, 0 +.set NOR_RX_DMA__NUMBEROF_TDS, 0 +.set NOR_RX_DMA__PRIORITY, 2 +.set NOR_RX_DMA__TERMIN_EN, 0 +.set NOR_RX_DMA__TERMIN_SEL, 0 +.set NOR_RX_DMA__TERMOUT0_EN, 1 +.set NOR_RX_DMA__TERMOUT0_SEL, 0 +.set NOR_RX_DMA__TERMOUT1_EN, 0 +.set NOR_RX_DMA__TERMOUT1_SEL, 0 +.set NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set NOR_RX_DMA_COMPLETE__INTC_MASK, 0x02 +.set NOR_RX_DMA_COMPLETE__INTC_NUMBER, 1 +.set NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* NOR_TX_DMA */ +.set NOR_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set NOR_TX_DMA__DRQ_NUMBER, 1 +.set NOR_TX_DMA__NUMBEROF_TDS, 0 +.set NOR_TX_DMA__PRIORITY, 2 +.set NOR_TX_DMA__TERMIN_EN, 0 +.set NOR_TX_DMA__TERMIN_SEL, 0 +.set NOR_TX_DMA__TERMOUT0_EN, 1 +.set NOR_TX_DMA__TERMOUT0_SEL, 1 +.set NOR_TX_DMA__TERMOUT1_EN, 0 +.set NOR_TX_DMA__TERMOUT1_SEL, 0 +.set NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set NOR_TX_DMA_COMPLETE__INTC_MASK, 0x04 +.set NOR_TX_DMA_COMPLETE__INTC_NUMBER, 2 +.set NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + /* SCSI_Noise */ .set SCSI_Noise__0__AG, CYREG_PRT4_AG .set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX @@ -2673,6 +2711,8 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2680,13 +2720,13 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST /* Debug_Timer */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2716,41 +2756,41 @@ /* SCSI_RX_DMA */ .set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__DRQ_NUMBER, 2 .set SCSI_RX_DMA__NUMBEROF_TDS, 0 .set SCSI_RX_DMA__PRIORITY, 2 .set SCSI_RX_DMA__TERMIN_EN, 0 .set SCSI_RX_DMA__TERMIN_SEL, 0 .set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_SEL, 2 .set SCSI_RX_DMA__TERMOUT1_EN, 0 .set SCSI_RX_DMA__TERMOUT1_SEL, 0 .set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 4 .set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 .set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA */ .set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__DRQ_NUMBER, 3 .set SCSI_TX_DMA__NUMBEROF_TDS, 0 .set SCSI_TX_DMA__PRIORITY, 2 .set SCSI_TX_DMA__TERMIN_EN, 0 .set SCSI_TX_DMA__TERMIN_SEL, 0 .set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 3 .set SCSI_TX_DMA__TERMOUT1_EN, 0 .set SCSI_TX_DMA__TERMOUT1_SEL, 0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x40 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 6 .set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 .set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2779,20 +2819,20 @@ /* SCSI_RST_ISR */ .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x02 -.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_MASK, 0x08 +.set SCSI_RST_ISR__INTC_NUMBER, 3 .set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 .set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SCSI_SEL_ISR */ .set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_MASK, 0x20 +.set SCSI_SEL_ISR__INTC_NUMBER, 5 .set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 .set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2801,8 +2841,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2810,58 +2850,71 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK +.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 @@ -3017,7 +3070,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000007F +.set CYDEV_INTR_RISING, 0x000001FF .set CYDEV_IS_EXPORTING_CODE, 0 .set CYDEV_IS_IMPORTING_CODE, 0 .set CYDEV_PROJ_TYPE, 2 @@ -3070,6 +3123,6 @@ .set CYIPBLOCK_S8_SAR_VERSION, 0 .set CYIPBLOCK_S8_SIO_VERSION, 0 .set CYIPBLOCK_S8_UDB_VERSION, 0 -.set DMA_CHANNELS_USED__MASK0, 0x0000000F +.set DMA_CHANNELS_USED__MASK0, 0x0000003F .set CYDEV_BOOTLOADER_ENABLE, 0 .endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index aab8b4c..23043fc 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -191,34 +191,34 @@ USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_MASK EQU 0x200 +USBFS_ep_1__INTC_NUMBER EQU 9 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_MASK EQU 0x400 +USBFS_ep_2__INTC_NUMBER EQU 10 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_MASK EQU 0x800 +USBFS_ep_3__INTC_NUMBER EQU 11 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_MASK EQU 0x2000 +USBFS_ep_4__INTC_NUMBER EQU 13 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -423,34 +423,34 @@ NOR_SO__SHIFT EQU 2 NOR_SO__SLW EQU CYREG_PRT15_SLW /* SDCard */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -458,9 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -484,8 +484,6 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -493,9 +491,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -566,34 +564,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW /* NOR_SPI */ -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -601,9 +599,9 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 @@ -627,8 +625,8 @@ NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -636,9 +634,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F -NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK -NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST /* SCSI_In */ SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -1759,15 +1757,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1780,15 +1778,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL @@ -2268,42 +2266,42 @@ NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 NOR_Clock__PM_STBY_MSK EQU 0x01 /* SD_RX_DMA */ -SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_RX_DMA__DRQ_NUMBER EQU 4 SD_RX_DMA__NUMBEROF_TDS EQU 0 SD_RX_DMA__PRIORITY EQU 0 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 -SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT0_SEL EQU 4 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x80 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 7 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SD_TX_DMA */ -SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_TX_DMA__DRQ_NUMBER EQU 5 SD_TX_DMA__NUMBEROF_TDS EQU 0 SD_TX_DMA__PRIORITY EQU 1 SD_TX_DMA__TERMIN_EN EQU 0 SD_TX_DMA__TERMIN_SEL EQU 0 SD_TX_DMA__TERMOUT0_EN EQU 1 -SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT0_SEL EQU 5 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x100 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 8 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2340,6 +2338,46 @@ nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ nNOR_HOLD__SLW EQU CYREG_PRT12_SLW +/* NOR_RX_DMA */ +NOR_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_RX_DMA__DRQ_NUMBER EQU 0 +NOR_RX_DMA__NUMBEROF_TDS EQU 0 +NOR_RX_DMA__PRIORITY EQU 2 +NOR_RX_DMA__TERMIN_EN EQU 0 +NOR_RX_DMA__TERMIN_SEL EQU 0 +NOR_RX_DMA__TERMOUT0_EN EQU 1 +NOR_RX_DMA__TERMOUT0_SEL EQU 0 +NOR_RX_DMA__TERMOUT1_EN EQU 0 +NOR_RX_DMA__TERMOUT1_SEL EQU 0 +NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_RX_DMA_COMPLETE__INTC_MASK EQU 0x02 +NOR_RX_DMA_COMPLETE__INTC_NUMBER EQU 1 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* NOR_TX_DMA */ +NOR_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_TX_DMA__DRQ_NUMBER EQU 1 +NOR_TX_DMA__NUMBEROF_TDS EQU 0 +NOR_TX_DMA__PRIORITY EQU 2 +NOR_TX_DMA__TERMIN_EN EQU 0 +NOR_TX_DMA__TERMIN_SEL EQU 0 +NOR_TX_DMA__TERMOUT0_EN EQU 1 +NOR_TX_DMA__TERMOUT0_SEL EQU 1 +NOR_TX_DMA__TERMOUT1_EN EQU 0 +NOR_TX_DMA__TERMOUT1_SEL EQU 0 +NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 +NOR_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + /* SCSI_Noise */ SCSI_Noise__0__AG EQU CYREG_PRT4_AG SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX @@ -2672,6 +2710,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2679,13 +2719,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST /* Debug_Timer */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2715,41 +2755,41 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 /* SCSI_RX_DMA */ SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__DRQ_NUMBER EQU 2 SCSI_RX_DMA__NUMBEROF_TDS EQU 0 SCSI_RX_DMA__PRIORITY EQU 2 SCSI_RX_DMA__TERMIN_EN EQU 0 SCSI_RX_DMA__TERMIN_SEL EQU 0 SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_SEL EQU 2 SCSI_RX_DMA__TERMOUT1_EN EQU 0 SCSI_RX_DMA__TERMOUT1_SEL EQU 0 SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA */ SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__DRQ_NUMBER EQU 3 SCSI_TX_DMA__NUMBEROF_TDS EQU 0 SCSI_TX_DMA__PRIORITY EQU 2 SCSI_TX_DMA__TERMIN_EN EQU 0 SCSI_TX_DMA__TERMIN_SEL EQU 0 SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 3 SCSI_TX_DMA__TERMOUT1_EN EQU 0 SCSI_TX_DMA__TERMOUT1_SEL EQU 0 SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2778,20 +2818,20 @@ timer_clock__PM_STBY_MSK EQU 0x08 /* SCSI_RST_ISR */ SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_MASK EQU 0x08 +SCSI_RST_ISR__INTC_NUMBER EQU 3 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_SEL_ISR */ SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_MASK EQU 0x20 +SCSI_SEL_ISR__INTC_NUMBER EQU 5 SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2800,8 +2840,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2809,58 +2849,71 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 @@ -3016,7 +3069,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007F +CYDEV_INTR_RISING EQU 0x000001FF CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 @@ -3069,7 +3122,7 @@ CYIPBLOCK_S8_IRQ_VERSION EQU 0 CYIPBLOCK_S8_SAR_VERSION EQU 0 CYIPBLOCK_S8_SIO_VERSION EQU 0 CYIPBLOCK_S8_UDB_VERSION EQU 0 -DMA_CHANNELS_USED__MASK0 EQU 0x0000000F +DMA_CHANNELS_USED__MASK0 EQU 0x0000003F CYDEV_BOOTLOADER_ENABLE EQU 0 #endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 6f9304d..8641b07 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -191,34 +191,34 @@ USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_MASK EQU 0x200 +USBFS_ep_1__INTC_NUMBER EQU 9 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_MASK EQU 0x400 +USBFS_ep_2__INTC_NUMBER EQU 10 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_MASK EQU 0x800 +USBFS_ep_3__INTC_NUMBER EQU 11 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_MASK EQU 0x2000 +USBFS_ep_4__INTC_NUMBER EQU 13 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -423,34 +423,34 @@ NOR_SO__SHIFT EQU 2 NOR_SO__SLW EQU CYREG_PRT15_SLW ; SDCard -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -458,9 +458,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -484,8 +484,6 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -493,9 +491,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -566,34 +564,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW ; NOR_SPI -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -601,9 +599,9 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 @@ -627,8 +625,8 @@ NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -636,9 +634,9 @@ NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F -NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK -NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST ; SCSI_In SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 @@ -1759,15 +1757,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1780,15 +1778,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL @@ -2268,42 +2266,42 @@ NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 NOR_Clock__PM_STBY_MSK EQU 0x01 ; SD_RX_DMA -SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_RX_DMA__DRQ_NUMBER EQU 4 SD_RX_DMA__NUMBEROF_TDS EQU 0 SD_RX_DMA__PRIORITY EQU 0 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 -SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT0_SEL EQU 4 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x80 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 7 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SD_TX_DMA -SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_TX_DMA__DRQ_NUMBER EQU 5 SD_TX_DMA__NUMBEROF_TDS EQU 0 SD_TX_DMA__PRIORITY EQU 1 SD_TX_DMA__TERMIN_EN EQU 0 SD_TX_DMA__TERMIN_SEL EQU 0 SD_TX_DMA__TERMOUT0_EN EQU 1 -SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT0_SEL EQU 5 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x100 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 8 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2340,6 +2338,46 @@ nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ nNOR_HOLD__SLW EQU CYREG_PRT12_SLW +; NOR_RX_DMA +NOR_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_RX_DMA__DRQ_NUMBER EQU 0 +NOR_RX_DMA__NUMBEROF_TDS EQU 0 +NOR_RX_DMA__PRIORITY EQU 2 +NOR_RX_DMA__TERMIN_EN EQU 0 +NOR_RX_DMA__TERMIN_SEL EQU 0 +NOR_RX_DMA__TERMOUT0_EN EQU 1 +NOR_RX_DMA__TERMOUT0_SEL EQU 0 +NOR_RX_DMA__TERMOUT1_EN EQU 0 +NOR_RX_DMA__TERMOUT1_SEL EQU 0 +NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_RX_DMA_COMPLETE__INTC_MASK EQU 0x02 +NOR_RX_DMA_COMPLETE__INTC_NUMBER EQU 1 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; NOR_TX_DMA +NOR_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_TX_DMA__DRQ_NUMBER EQU 1 +NOR_TX_DMA__NUMBEROF_TDS EQU 0 +NOR_TX_DMA__PRIORITY EQU 2 +NOR_TX_DMA__TERMIN_EN EQU 0 +NOR_TX_DMA__TERMIN_SEL EQU 0 +NOR_TX_DMA__TERMOUT0_EN EQU 1 +NOR_TX_DMA__TERMOUT0_SEL EQU 1 +NOR_TX_DMA__TERMOUT1_EN EQU 0 +NOR_TX_DMA__TERMOUT1_SEL EQU 0 +NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 +NOR_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + ; SCSI_Noise SCSI_Noise__0__AG EQU CYREG_PRT4_AG SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX @@ -2672,6 +2710,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2679,13 +2719,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST ; Debug_Timer Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2715,41 +2755,41 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 ; SCSI_RX_DMA SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__DRQ_NUMBER EQU 2 SCSI_RX_DMA__NUMBEROF_TDS EQU 0 SCSI_RX_DMA__PRIORITY EQU 2 SCSI_RX_DMA__TERMIN_EN EQU 0 SCSI_RX_DMA__TERMIN_SEL EQU 0 SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_SEL EQU 2 SCSI_RX_DMA__TERMOUT1_EN EQU 0 SCSI_RX_DMA__TERMOUT1_SEL EQU 0 SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_TX_DMA SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__DRQ_NUMBER EQU 3 SCSI_TX_DMA__NUMBEROF_TDS EQU 0 SCSI_TX_DMA__PRIORITY EQU 2 SCSI_TX_DMA__TERMIN_EN EQU 0 SCSI_TX_DMA__TERMIN_SEL EQU 0 SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 3 SCSI_TX_DMA__TERMOUT1_EN EQU 0 SCSI_TX_DMA__TERMOUT1_SEL EQU 0 SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2778,20 +2818,20 @@ timer_clock__PM_STBY_MSK EQU 0x08 ; SCSI_RST_ISR SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_MASK EQU 0x08 +SCSI_RST_ISR__INTC_NUMBER EQU 3 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_SEL_ISR SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_MASK EQU 0x20 +SCSI_SEL_ISR__INTC_NUMBER EQU 5 SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2800,8 +2840,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2809,58 +2849,71 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 @@ -3016,7 +3069,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007F +CYDEV_INTR_RISING EQU 0x000001FF CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 @@ -3069,7 +3122,7 @@ CYIPBLOCK_S8_IRQ_VERSION EQU 0 CYIPBLOCK_S8_SAR_VERSION EQU 0 CYIPBLOCK_S8_SIO_VERSION EQU 0 CYIPBLOCK_S8_UDB_VERSION EQU 0 -DMA_CHANNELS_USED__MASK0 EQU 0x0000000F +DMA_CHANNELS_USED__MASK0 EQU 0x0000003F CYDEV_BOOTLOADER_ENABLE EQU 0 ENDIF END diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index e891264..b9c3435 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -85,6 +85,10 @@ #include "nNOR_CS.h" #include "nNOR_WP_aliases.h" #include "nNOR_WP.h" +#include "NOR_RX_DMA_dma.h" +#include "NOR_TX_DMA_dma.h" +#include "NOR_RX_DMA_COMPLETE.h" +#include "NOR_TX_DMA_COMPLETE.h" #include "USBFS_Dm_aliases.h" #include "USBFS_Dm.h" #include "USBFS_Dp_aliases.h" diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx index 678f845..ef7bdae 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,20 +1,20 @@ - \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit index 777cabe..6dec319 100644 Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj index 9a0c457..068706b 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2627,6 +2627,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd index c7a9b7d..11866b9 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd @@ -19,7 +19,7 @@ SCSI_Glitch_Ctl_CONTROL_REG No description available - 0x40006479 + 0x4000647A 8 read-write 0 @@ -28,7 +28,7 @@ - SCSI_Parity_Error + SCSI_Filtered No description available 0x0 @@ -38,27 +38,27 @@ - SCSI_Parity_Error_STATUS_REG + SCSI_Filtered_STATUS_REG No description available - 0x4000646C + 0x40006468 8 read-write 0 0 - SCSI_Parity_Error_MASK_REG + SCSI_Filtered_MASK_REG No description available - 0x4000648C + 0x40006488 8 read-write 0 0 - SCSI_Parity_Error_STATUS_AUX_CTL_REG + SCSI_Filtered_STATUS_AUX_CTL_REG No description available - 0x4000649C + 0x40006498 8 read-write 0 @@ -183,7 +183,7 @@ - SCSI_Filtered + SCSI_Parity_Error No description available 0x0 @@ -193,27 +193,27 @@ - SCSI_Filtered_STATUS_REG + SCSI_Parity_Error_STATUS_REG No description available - 0x40006568 + 0x40006469 8 read-write 0 0 - SCSI_Filtered_MASK_REG + SCSI_Parity_Error_MASK_REG No description available - 0x40006588 + 0x40006489 8 read-write 0 0 - SCSI_Filtered_STATUS_AUX_CTL_REG + SCSI_Parity_Error_STATUS_AUX_CTL_REG No description available - 0x40006598 + 0x40006499 8 read-write 0 @@ -350,7 +350,7 @@ SCSI_CTL_PHASE_CONTROL_REG No description available - 0x4000647F + 0x4000647B 8 read-write 0 @@ -2596,27 +2596,6 @@ - - SCSI_Out_Ctl - No description available - 0x0 - - 0 - 0x0 - registers - - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x40006478 - 8 - read-write - 0 - 0 - - - Debug_Timer No description available @@ -2922,7 +2901,28 @@ SCSI_Out_Bits_CONTROL_REG No description available - 0x4000657A + 0x40006579 + 8 + read-write + 0 + 0 + + + + + SCSI_Out_Ctl + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x40006478 8 read-write 0 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 4b89081..700ec84 100644 Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ