From: Michael McMaster <email@michaelmcmaster.name>
Date: Wed, 15 Dec 2010 23:00:44 +0000 (+1000)
Subject: Random commit
X-Git-Tag: 1.0.0~9
X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=e6aafe3b08a2d6b02bd0f9983007964b974f1dfd;p=glBoy.git

Random commit
---

diff --git a/InstructionSet.opcode b/InstructionSet.opcode
new file mode 100755
index 0000000..10c0b76
--- /dev/null
+++ b/InstructionSet.opcode
@@ -0,0 +1,160 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<opcodes>
+<!--
+	Z80 Core Emulation
+	8 bit LD instructions
+	Copyright 2010, Michael McMaster <email@michaelmcmaster.name>
+-->
+
+code gen expectations:
+masks result in each instruction being unrolled and the mask name being replaced
+with an actual register
+operand = op8();
+operand="UPPERCASE" is 16bit operand. (first 8 bits = low bytes) N = op16()
+
+<registerMask name="r" bits="3">
+	<reg name="A" mask="111">
+	<reg name="B" mask="000">
+	<reg name="C" mask="001">
+	<reg name="D" mask="010">
+	<reg name="E" mask="011">
+	<reg name="H" mask="100">
+	<reg name="L" mask="101">
+</registerMask>
+
+<registerMask name="d" alias="s" bits="2">
+	<reg name="BC" mask="00">
+	<reg name="DE" mask="01">
+	<reg name="HL" mask="10">
+	<reg name="SP" mask="11">
+</registerMask>
+
+<registerMask name="q" bits="2">
+	<reg name="BC" mask="00">
+	<reg name="DE" mask="01">
+	<reg name="HL" mask="10">
+	<reg name="AF" mask="11">
+</registerMask>
+
+<registerMask name="p" bits="2">
+	<reg name="BC" mask="00">
+	<reg name="DE" mask="01">
+	<reg name="IX" mask="10">
+	<reg name="SP" mask="11">
+</registerMask>
+
+<registerMask name="R" bits="2">
+	<reg name="BC" mask="00">
+	<reg name="DE" mask="01">
+	<reg name="IY" mask="10">
+	<reg name="SP" mask="11">
+</registerMask>
+
+<instruction name="LD r,r'" clock="4">
+<opcode mask="01rr" />
+r = r2;
+</instruction>
+
+<instruction name="LD r,n" clock="7">
+<opcode mask="00r110" operand="n"/>
+r = n;
+</instruction>
+
+<instruction name="LD r,(HL)" clock="7">
+<opcode mask="01r110" />
+r = m_mem.read8(m_reg.HL);
+</instruction>
+
+<instruction name="LD r,(IX+d)" clock="19">
+<opcode prefix="0xDD" mask="01r110" operand="d"/>
+r = m_mem.read8(m_reg.IX, d);
+</instruction>
+
+<instruction name="LD r,(IY+d)" clock="19">
+<opcode prefix="0xFD" mask="01r110" operand="d"/>
+r = m_mem.read8(m_reg.IY, d);
+</instruction>
+
+<instruction name="LD (HL),r" clock="7">
+<opcode mask="01110r"/>
+m_mem.write8(m_reg.HL, r);
+</instruction>
+
+<instruction name="LD (IX+d),r" clock="19">
+<opcode prefix="0xDD" mask="01110r" operand="d"/>
+m_mem.write8(m_reg.IX, d, r);
+</instruction>
+
+<instruction name="LD (IY+d),r" clock="19">
+<opcode prefix="0xFD" mask="01110r" operand="d"/>
+m_mem.write8(m_reg.IY, d, r);
+</instruction>
+
+<instruction name="LD (HL),n" clock="10">
+<opcode mask="00110110" operand="n"/>
+m_mem.write8(m_reg.HL, n);
+</instruction>
+
+<instruction name="LD (IX+d),r" clock="19">
+<opcode prefix="0xDD" mask="00110110" operand="dn"/>
+m_mem.write8(m_reg.IX, d, n);
+</instruction>
+
+<instruction name="LD (IY+d),n" clock="19">
+<opcode prefix="0xFD" mask="00110110" operand="dn"/>
+m_mem.write8(m_reg.IY, d, n);
+</instruction>
+
+<instruction name="LD A,(BC)" clock="7">
+<opcode mask="00001010"/>
+m_reg.A = m_mem.read8(m_reg.BC);
+</instruction>
+
+<instruction name="LD A,(DE)" clock="7">
+<opcode mask="00011010"/>
+m_reg.A = m_mem.read8(m_reg.DE);
+</instruction>
+
+<instruction name="LD A,(nn)" clock="13">
+<opcode mask="00111010" operand="N"/>
+m_reg.A = m_mem.read8(N);
+</instruction>
+
+<instruction name="LD (BC),A" clock="7">
+<opcode mask="00000010"/>
+m_mem.write8(m_reg.BC, m_reg.A);
+</instruction>
+
+<instruction name="LD (DE),A" clock="7">
+<opcode mask="00010010"/>
+m_mem.write8(m_reg.DE, m_reg.A);
+</instruction>
+
+<instruction name="LD (nn),A" clock="13">
+<opcode mask="00110010" operand="N"/>
+m_mem.write8(N, m_reg.A);
+</instruction>
+
+<instruction name="LD A,I" clock="9">
+<opcode prefix="0xED" mask="01010111"/>
+m_reg.F.set(m_reg.I, *this);
+m_reg.A = m_reg.I;
+</instruction>
+
+<instruction name="LD A,R" clock="9">
+<opcode prefix="0xED" mask="01011111"/>
+m_reg.F.set(m_reg.R, *this);
+m_reg.A = m_reg.R;
+</instruction>
+
+<instruction name="LD I,A" clock="9">
+<opcode prefix="0xED" mask="01000111"/>
+m_reg.I = m_reg.A;
+</instruction>
+
+<instruction name="LD R,A" clock="9">
+<opcode prefix="0xED" mask="01001111"/>
+m_reg.R = m_reg.A;
+</instruction>
+
+</opcodes>