From: Michael McMaster Date: Thu, 7 Jan 2016 12:15:45 +0000 (+1000) Subject: Lots of bug fixes. X-Git-Tag: v4.6~1 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=ff3ca448a544a23e15903953ed0178176743f7e3;p=SCSI2SD.git Lots of bug fixes. - Reset fix - Overrun fifo on fast scsi host fix - Startup time improvement - Allows overwriting the bootloader - Adds "sticky" sel option - Adds map luns to id option --- diff --git a/CHANGELOG b/CHANGELOG index a7a1ead..c22ae0c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,14 @@ +201601XX 4.6 + - Fixed bug when using sector size that isn't a multiple of 4 + (eg. 522 bytes) + - Fixed a bug that caused hanging or scsi phase errors on + high speed scsi hosts. + - Fixed a hang when processing a SCSI RESET in a data phase. + - scsi2sd-util: Fixed USB connection problems under Windows 10. + - Added option to treat luns as separate devices + - Improved boot up time. + + 20151105 4.5 - Fix bug in SCSI MODE SENSE that returned the wrong mode type - Fixes CDROM emulation diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index 7b4ed82..eed072d 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -33,7 +33,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0450; +static const uint16_t FIRMWARE_VERSION = 0x0460; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = @@ -142,26 +142,14 @@ writeFlashCommand(const uint8_t* cmd, size_t cmdSize) uint8_t flashArray = cmd[257]; uint8_t flashRow = cmd[258]; - // Be very careful not to overwrite the bootloader or other - // code - if ((flashArray != SCSI_CONFIG_ARRAY) || - (flashRow < SCSI_CONFIG_BOARD_ROW) || - (flashRow >= SCSI_CONFIG_3_ROW + SCSI_CONFIG_ROWS)) - { - uint8_t response[] = { CONFIG_STATUS_ERR}; - hidPacket_send(response, sizeof(response)); - } - else - { - CySetTemp(); - int status = CyWriteRowData(flashArray, flashRow, cmd + 1); + CySetTemp(); + int status = CyWriteRowData(flashArray, flashRow, cmd + 1); - uint8_t response[] = - { - status == CYRET_SUCCESS ? CONFIG_STATUS_GOOD : CONFIG_STATUS_ERR - }; - hidPacket_send(response, sizeof(response)); - } + uint8_t response[] = + { + status == CYRET_SUCCESS ? CONFIG_STATUS_GOOD : CONFIG_STATUS_ERR + }; + hidPacket_send(response, sizeof(response)); } static void diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index 2f88cc4..7aecf95 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -76,6 +76,7 @@ static void enter_BusFree() ledOff(); scsiDev.phase = BUS_FREE; + scsiDev.selFlag = 0; } static void enter_MessageIn(uint8 message) @@ -263,10 +264,27 @@ static void process_Command() scsiDev.lun = scsiDev.cdb[1] >> 5; } + // For Philips P2000C with Xebec S1410 SASI/MFM adapter + // http://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf + if ((scsiDev.lun > 0) && (scsiDev.boardCfg.flags & CONFIG_MAP_LUNS_TO_IDS)) + { + int tgtIndex; + for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex) + { + if (scsiDev.targets[tgtIndex].targetId == scsiDev.lun) + { + scsiDev.target = &scsiDev.targets[tgtIndex]; + scsiDev.lun = 0; + break; + } + } + } + + control = scsiDev.cdb[scsiDev.cdbLen - 1]; scsiDev.cmdCount++; - TargetConfig* cfg = scsiDev.target->cfg; + const TargetConfig* cfg = scsiDev.target->cfg; if (unlikely(scsiDev.resetFlag)) { @@ -467,6 +485,7 @@ static void scsiReset() scsiDev.phase = BUS_FREE; scsiDev.atnFlag = 0; scsiDev.resetFlag = 0; + scsiDev.selFlag = 0; scsiDev.lun = -1; scsiDev.compatMode = COMPAT_UNKNOWN; @@ -539,7 +558,9 @@ static void process_SelectionPhase() CyDelay(scsiDev.boardCfg.selectionDelay); } - int sel = SCSI_ReadFilt(SCSI_Filt_SEL); + int selLatchCfg = scsiDev.boardCfg.flags & CONFIG_ENABLE_SEL_LATCH; + int sel = (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL); + int bsy = SCSI_ReadFilt(SCSI_Filt_BSY); int io = SCSI_ReadPin(SCSI_In_IO); @@ -560,7 +581,7 @@ static void process_SelectionPhase() break; } } - sel &= SCSI_ReadFilt(SCSI_Filt_SEL); + sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL); bsy |= SCSI_ReadFilt(SCSI_Filt_BSY); io |= SCSI_ReadPin(SCSI_In_IO); if (!bsy && !io && sel && @@ -638,6 +659,8 @@ static void process_SelectionPhase() { scsiDev.phase = BUS_BUSY; } + + scsiDev.selFlag = 0; } static void process_MessageOut() @@ -812,7 +835,7 @@ void scsiPoll(void) // one initiator in the chain. Support this by moving // straight to selection if SEL is asserted. // ie. the initiator won't assert BSY and it's own ID before moving to selection. - else if (SCSI_ReadFilt(SCSI_Filt_SEL)) + else if (SCSI_ReadFilt(SCSI_Filt_SEL) || scsiDev.selFlag) { enter_SelectionPhase(); } @@ -821,7 +844,7 @@ void scsiPoll(void) case BUS_BUSY: // Someone is using the bus. Perhaps they are trying to // select us. - if (SCSI_ReadFilt(SCSI_Filt_SEL)) + if (SCSI_ReadFilt(SCSI_Filt_SEL) || scsiDev.selFlag) { enter_SelectionPhase(); } @@ -916,6 +939,7 @@ void scsiInit() { scsiDev.atnFlag = 0; scsiDev.resetFlag = 1; + scsiDev.selFlag = 0; scsiDev.phase = BUS_FREE; scsiDev.target = NULL; scsiDev.compatMode = COMPAT_UNKNOWN; diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h index 11fd676..844bbe3 100755 --- a/software/SCSI2SD/src/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -106,6 +106,9 @@ typedef struct // Set to true (1) if the RST flag was set. volatile int resetFlag; + + // Set to true (1) if the SEL flag was set. + volatile int selFlag; // Set to true (1) if a parity error was observed. int parityError; diff --git a/software/SCSI2SD/src/scsiPhy.c b/software/SCSI2SD/src/scsiPhy.c index b3b466f..f9959d5 100755 --- a/software/SCSI2SD/src/scsiPhy.c +++ b/software/SCSI2SD/src/scsiPhy.c @@ -76,6 +76,10 @@ CY_ISR(scsiSelectionISR) // The SEL signal ISR ensures we wake up from a _WFI() (wait-for-interrupt) // call in the main loop without waiting for our 1ms timer to // expire. This is done to meet the 250us selection abort time. + + // selFlag is required for Philips P2000C which releases it after 600ns + // without waiting for BSY. + scsiDev.selFlag = 1; } uint8_t @@ -227,8 +231,7 @@ scsiRead(uint8_t* data, uint32_t count) } else { - uint32_t alignedCount = count & 0xFFFFFFF8; - scsiReadDMA(data, alignedCount); + scsiReadDMA(data, count); // Wait for the next DMA interrupt (or the 1ms systick) // It's beneficial to halt the processor to @@ -240,11 +243,6 @@ scsiRead(uint8_t* data, uint32_t count) { __WFI(); }; - - if (count > alignedCount) - { - scsiReadPIO(data + alignedCount, count - alignedCount); - } } } @@ -364,8 +362,7 @@ scsiWrite(const uint8_t* data, uint32_t count) } else { - uint32_t alignedCount = count & 0xFFFFFFF8; - scsiWriteDMA(data, alignedCount); + scsiWriteDMA(data, count); // Wait for the next DMA interrupt (or the 1ms systick) // It's beneficial to halt the processor to @@ -377,11 +374,6 @@ scsiWrite(const uint8_t* data, uint32_t count) { __WFI(); }; - - if (count > alignedCount) - { - scsiWritePIO(data + alignedCount, count - alignedCount); - } } } @@ -428,8 +420,19 @@ void scsiPhyReset() // CyDmaChGetRequest returns 0 for the relevant bit once the // request is completed. trace(trace_spinDMAReset); - while (CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) {} - while (CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) {} + while ( + (CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) && + !scsiTxDMAComplete + ) + {} + + while (( + CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) && + !scsiRxDMAComplete + ) + {} + + CyDelayUs(1); CyDmaChDisable(scsiDmaTxChan); CyDmaChDisable(scsiDmaRxChan); @@ -468,7 +471,7 @@ static void scsiPhyInitDMA() { scsiDmaRxChan = SCSI_RX_DMA_DmaInitialize( - 4, // Bytes per burst + 1, // Bytes per burst 1, // request per burst HI16(CYDEV_PERIPH_BASE), HI16(CYDEV_SRAM_BASE) @@ -476,7 +479,7 @@ static void scsiPhyInitDMA() scsiDmaTxChan = SCSI_TX_DMA_DmaInitialize( - 4, // Bytes per burst + 1, // Bytes per burst 1, // request per burst HI16(CYDEV_SRAM_BASE), HI16(CYDEV_PERIPH_BASE) diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index 20f2f05..2755754 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -951,6 +951,7 @@ void sdPoll() void sdCheckPresent() { + static int firstCheck = 1; // Check if there's an SD card present. if ((scsiDev.phase == BUS_FREE) && (sdIOState == SD_IDLE) && @@ -973,8 +974,12 @@ void sdCheckPresent() { static int firstInit = 1; - // Debounce - CyDelay(250); + // Debounce, except on startup if the card is present at + // power on + if (!firstCheck) + { + CyDelay(250); + } if (sdInit()) { @@ -1010,6 +1015,7 @@ void sdCheckPresent() } } } + firstCheck = 0; } #pragma GCC pop_options diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 105d7c3..2a56837 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -391,34 +391,34 @@ #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -426,9 +426,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 @@ -450,8 +450,8 @@ #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -459,9 +459,13 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2 @@ -1941,15 +1945,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1962,37 +1966,37 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK /* SCSI_Out_Ctl */ #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK /* SCSI_Out_DBx */ #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG @@ -2818,8 +2822,6 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2827,9 +2829,9 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST /* Debug_Timer_Interrupt */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2950,8 +2952,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2959,67 +2961,67 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 721464b..78594ac 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -122,7 +122,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 42u +#define CY_CFG_BASE_ADDR_COUNT 40u CYPACKED typedef struct { uint8 offset; @@ -384,103 +384,80 @@ void cyfitter_cfg(void) 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */ 0x40006401u, /* Base address: 0x40006400 Count: 1 */ 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x4001003Du, /* Base address: 0x40010000 Count: 61 */ - 0x40010138u, /* Base address: 0x40010100 Count: 56 */ - 0x40010248u, /* Base address: 0x40010200 Count: 72 */ - 0x40010356u, /* Base address: 0x40010300 Count: 86 */ - 0x40010445u, /* Base address: 0x40010400 Count: 69 */ - 0x4001054Au, /* Base address: 0x40010500 Count: 74 */ - 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ - 0x4001074Fu, /* Base address: 0x40010700 Count: 79 */ - 0x40010856u, /* Base address: 0x40010800 Count: 86 */ - 0x40010954u, /* Base address: 0x40010900 Count: 84 */ - 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */ - 0x40010B4Bu, /* Base address: 0x40010B00 Count: 75 */ - 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */ - 0x40010D56u, /* Base address: 0x40010D00 Count: 86 */ - 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */ - 0x40010F42u, /* Base address: 0x40010F00 Count: 66 */ - 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */ - 0x4001154Au, /* Base address: 0x40011500 Count: 74 */ - 0x40011650u, /* Base address: 0x40011600 Count: 80 */ - 0x4001174Au, /* Base address: 0x40011700 Count: 74 */ - 0x40011804u, /* Base address: 0x40011800 Count: 4 */ - 0x40011913u, /* Base address: 0x40011900 Count: 19 */ - 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */ + 0x40010054u, /* Base address: 0x40010000 Count: 84 */ + 0x40010141u, /* Base address: 0x40010100 Count: 65 */ + 0x40010243u, /* Base address: 0x40010200 Count: 67 */ + 0x40010350u, /* Base address: 0x40010300 Count: 80 */ + 0x40010454u, /* Base address: 0x40010400 Count: 84 */ + 0x40010553u, /* Base address: 0x40010500 Count: 83 */ + 0x40010651u, /* Base address: 0x40010600 Count: 81 */ + 0x40010755u, /* Base address: 0x40010700 Count: 85 */ + 0x40010916u, /* Base address: 0x40010900 Count: 22 */ + 0x40010A56u, /* Base address: 0x40010A00 Count: 86 */ + 0x40010B4Du, /* Base address: 0x40010B00 Count: 77 */ + 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */ + 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */ + 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */ + 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */ + 0x40011421u, /* Base address: 0x40011400 Count: 33 */ + 0x40011551u, /* Base address: 0x40011500 Count: 81 */ + 0x4001165Bu, /* Base address: 0x40011600 Count: 91 */ + 0x40011747u, /* Base address: 0x40011700 Count: 71 */ + 0x40011907u, /* Base address: 0x40011900 Count: 7 */ + 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */ - 0x4001411Au, /* Base address: 0x40014100 Count: 26 */ - 0x40014213u, /* Base address: 0x40014200 Count: 19 */ - 0x4001430Au, /* Base address: 0x40014300 Count: 10 */ - 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */ - 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */ - 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */ - 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */ - 0x40014807u, /* Base address: 0x40014800 Count: 7 */ + 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */ + 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ + 0x40014310u, /* Base address: 0x40014300 Count: 16 */ + 0x40014412u, /* Base address: 0x40014400 Count: 18 */ + 0x40014516u, /* Base address: 0x40014500 Count: 22 */ + 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ + 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */ + 0x40014806u, /* Base address: 0x40014800 Count: 6 */ 0x40014909u, /* Base address: 0x40014900 Count: 9 */ 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */ 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */ - 0x40015002u, /* Base address: 0x40015000 Count: 2 */ + 0x40015004u, /* Base address: 0x40015000 Count: 4 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x36u}, - {0x00u, 0x05u}, - {0x01u, 0x13u}, - {0x18u, 0x08u}, + {0x0Au, 0x1Bu}, + {0x00u, 0x11u}, + {0x01u, 0x02u}, + {0x18u, 0x04u}, {0x1Cu, 0x71u}, - {0x20u, 0x50u}, - {0x21u, 0x90u}, + {0x20u, 0x38u}, + {0x21u, 0x60u}, {0x2Cu, 0x0Eu}, {0x30u, 0x0Cu}, - {0x31u, 0x09u}, + {0x31u, 0x0Au}, {0x34u, 0x80u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x87u, 0x0Fu}, + {0x85u, 0x0Fu}, {0x00u, 0x20u}, - {0x02u, 0x40u}, - {0x03u, 0x04u}, {0x04u, 0x01u}, - {0x05u, 0x08u}, - {0x08u, 0x0Au}, - {0x09u, 0x09u}, - {0x0Au, 0x35u}, - {0x0Bu, 0x72u}, - {0x0Cu, 0x48u}, - {0x0Eu, 0x36u}, - {0x10u, 0x07u}, - {0x11u, 0x01u}, - {0x12u, 0x18u}, - {0x13u, 0x66u}, - {0x14u, 0x4Fu}, - {0x16u, 0x30u}, - {0x17u, 0x7Fu}, - {0x1Bu, 0x01u}, - {0x1Du, 0x62u}, - {0x1Eu, 0x02u}, - {0x21u, 0x20u}, - {0x22u, 0x20u}, - {0x23u, 0x40u}, - {0x24u, 0x05u}, - {0x25u, 0x74u}, - {0x27u, 0x09u}, - {0x29u, 0x20u}, - {0x2Au, 0x27u}, - {0x2Bu, 0x40u}, - {0x30u, 0x1Fu}, - {0x31u, 0x60u}, - {0x33u, 0x1Fu}, - {0x36u, 0x60u}, - {0x3Au, 0x82u}, - {0x3Bu, 0x02u}, - {0x40u, 0x32u}, - {0x41u, 0x04u}, - {0x42u, 0x10u}, - {0x45u, 0x2Du}, - {0x46u, 0xFCu}, + {0x08u, 0x51u}, + {0x0Au, 0x2Cu}, + {0x0Eu, 0x3Fu}, + {0x10u, 0x4Au}, + {0x12u, 0x15u}, + {0x1Cu, 0x4Bu}, + {0x1Eu, 0x34u}, + {0x20u, 0x06u}, + {0x22u, 0x40u}, + {0x26u, 0x10u}, + {0x30u, 0x3Fu}, + {0x32u, 0x40u}, + {0x3Eu, 0x04u}, + {0x40u, 0x34u}, + {0x41u, 0x05u}, + {0x42u, 0x20u}, + {0x45u, 0xCFu}, + {0x46u, 0xD2u}, {0x47u, 0x0Eu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, @@ -489,10 +466,9 @@ void cyfitter_cfg(void) {0x4Fu, 0x2Cu}, {0x56u, 0x01u}, {0x58u, 0x04u}, - {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x01u}, {0x5Du, 0x01u}, {0x5Fu, 0x01u}, {0x60u, 0x08u}, @@ -501,243 +477,143 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x02u, 0x04u}, - {0x03u, 0x91u}, - {0x04u, 0x30u}, - {0x0Au, 0x80u}, - {0x0Bu, 0x11u}, - {0x11u, 0x10u}, - {0x12u, 0xA8u}, - {0x1Au, 0x80u}, - {0x1Bu, 0x80u}, - {0x20u, 0x30u}, - {0x23u, 0x90u}, - {0x28u, 0x48u}, - {0x2Au, 0x04u}, - {0x2Bu, 0x10u}, - {0x32u, 0x88u}, - {0x33u, 0x11u}, - {0x38u, 0x10u}, - {0x3Bu, 0x05u}, - {0x40u, 0x10u}, - {0x42u, 0x04u}, - {0x43u, 0x81u}, - {0x4Au, 0x20u}, - {0x4Bu, 0x05u}, - {0x50u, 0x80u}, - {0x53u, 0x28u}, - {0x58u, 0x40u}, - {0x59u, 0x20u}, - {0x5Au, 0x02u}, - {0x5Bu, 0x84u}, - {0x60u, 0x04u}, - {0x61u, 0x49u}, - {0x69u, 0x84u}, - {0x6Au, 0x20u}, - {0x6Bu, 0x40u}, - {0x71u, 0x80u}, - {0x72u, 0x88u}, - {0x73u, 0x20u}, - {0x80u, 0x80u}, - {0x81u, 0xC0u}, - {0x85u, 0x04u}, - {0x8Au, 0x08u}, - {0x8Eu, 0x10u}, - {0x8Fu, 0x22u}, - {0xC0u, 0x0Fu}, - {0xC2u, 0x0Du}, - {0xC4u, 0x0Eu}, - {0xCAu, 0x07u}, - {0xCCu, 0x0Fu}, - {0xCEu, 0x07u}, - {0xD0u, 0x0Fu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x0Fu}, - {0xE0u, 0x05u}, - {0xE2u, 0x02u}, - {0xE4u, 0x03u}, - {0xE6u, 0x08u}, - {0x00u, 0x96u}, - {0x02u, 0x69u}, - {0x04u, 0x55u}, - {0x05u, 0x33u}, - {0x06u, 0xAAu}, - {0x07u, 0xCCu}, - {0x0Au, 0xFFu}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0x33u}, - {0x0Du, 0x0Fu}, - {0x0Eu, 0xCCu}, - {0x0Fu, 0xF0u}, - {0x13u, 0xFFu}, - {0x14u, 0x0Fu}, - {0x16u, 0xF0u}, - {0x17u, 0xFFu}, - {0x18u, 0xFFu}, - {0x1Du, 0xFFu}, - {0x1Eu, 0xFFu}, - {0x25u, 0xFFu}, - {0x29u, 0x55u}, - {0x2Au, 0xFFu}, - {0x2Bu, 0xAAu}, - {0x2Cu, 0xFFu}, - {0x2Du, 0x69u}, - {0x2Fu, 0x96u}, - {0x32u, 0xFFu}, - {0x37u, 0xFFu}, - {0x3Au, 0x08u}, - {0x3Bu, 0x80u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Fu, 0x01u}, - {0x80u, 0xE0u}, + {0x80u, 0xC0u}, + {0x81u, 0x69u}, + {0x82u, 0x18u}, + {0x83u, 0x12u}, {0x84u, 0x40u}, {0x86u, 0x80u}, - {0x89u, 0x44u}, - {0x8Au, 0xFFu}, - {0x8Bu, 0x88u}, - {0x8Cu, 0x06u}, - {0x8Eu, 0xF8u}, - {0x8Fu, 0x80u}, - {0x91u, 0x99u}, - {0x93u, 0x22u}, - {0x94u, 0x01u}, - {0x97u, 0x07u}, - {0x98u, 0xC6u}, - {0x9Au, 0x19u}, - {0x9Bu, 0x70u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x80u}, - {0x9Fu, 0x08u}, - {0xA0u, 0x14u}, - {0xA5u, 0xAAu}, - {0xA6u, 0x09u}, - {0xA7u, 0x55u}, - {0xA8u, 0x09u}, - {0xAAu, 0xF2u}, - {0xB3u, 0x0Fu}, - {0xB4u, 0x3Fu}, - {0xB5u, 0xF0u}, - {0xB6u, 0xC0u}, - {0xBAu, 0x80u}, - {0xD6u, 0x08u}, + {0x8Cu, 0x25u}, + {0x8Du, 0x20u}, + {0x8Eu, 0xD8u}, + {0x8Fu, 0x40u}, + {0x93u, 0x67u}, + {0x94u, 0x10u}, + {0x95u, 0x03u}, + {0x96u, 0x20u}, + {0x97u, 0x1Cu}, + {0x9Bu, 0x01u}, + {0x9Cu, 0xC4u}, + {0x9Du, 0x64u}, + {0x9Eu, 0x18u}, + {0xA0u, 0x02u}, + {0xA1u, 0x08u}, + {0xA2u, 0xD0u}, + {0xA3u, 0x77u}, + {0xA4u, 0x21u}, + {0xA5u, 0x02u}, + {0xA6u, 0xD8u}, + {0xA9u, 0x0Bu}, + {0xAAu, 0x01u}, + {0xABu, 0x74u}, + {0xACu, 0x40u}, + {0xADu, 0x20u}, + {0xAEu, 0x80u}, + {0xAFu, 0x40u}, + {0xB1u, 0x60u}, + {0xB2u, 0x30u}, + {0xB4u, 0xC0u}, + {0xB5u, 0x1Fu}, + {0xB6u, 0x0Fu}, + {0xB8u, 0x80u}, + {0xBAu, 0x28u}, + {0xBBu, 0x22u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, {0xDCu, 0x11u}, - {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x10u}, - {0x02u, 0x90u}, - {0x03u, 0x01u}, - {0x04u, 0x20u}, - {0x05u, 0x04u}, - {0x06u, 0x40u}, - {0x07u, 0x02u}, - {0x09u, 0x04u}, - {0x0Au, 0x06u}, - {0x0Eu, 0x26u}, - {0x10u, 0x80u}, - {0x12u, 0x20u}, - {0x13u, 0x18u}, - {0x15u, 0x90u}, - {0x1Au, 0x06u}, - {0x1Bu, 0x30u}, - {0x1Eu, 0x20u}, - {0x21u, 0x20u}, - {0x22u, 0x04u}, - {0x24u, 0x02u}, - {0x25u, 0x40u}, - {0x2Bu, 0x10u}, - {0x2Eu, 0x20u}, - {0x2Fu, 0x21u}, - {0x31u, 0x20u}, - {0x32u, 0x04u}, - {0x33u, 0x41u}, - {0x36u, 0x89u}, - {0x37u, 0x01u}, - {0x38u, 0x20u}, - {0x3Au, 0x80u}, - {0x3Du, 0x80u}, - {0x3Fu, 0x18u}, - {0x58u, 0x10u}, + {0x03u, 0x59u}, + {0x05u, 0x44u}, + {0x07u, 0x40u}, + {0x0Au, 0x41u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x02u}, + {0x12u, 0x90u}, + {0x14u, 0x02u}, + {0x15u, 0x08u}, + {0x17u, 0x11u}, + {0x1Au, 0xD0u}, + {0x1Bu, 0x01u}, + {0x1Du, 0x40u}, + {0x1Eu, 0x27u}, + {0x1Fu, 0x40u}, + {0x24u, 0x40u}, + {0x27u, 0x88u}, + {0x2Du, 0x08u}, + {0x2Fu, 0x69u}, + {0x36u, 0x20u}, + {0x37u, 0x49u}, + {0x3Cu, 0x40u}, + {0x3Fu, 0x02u}, + {0x40u, 0x08u}, + {0x41u, 0x04u}, + {0x42u, 0x40u}, + {0x43u, 0x08u}, + {0x48u, 0x10u}, + {0x4Au, 0x81u}, + {0x51u, 0x80u}, + {0x52u, 0x18u}, + {0x53u, 0x20u}, + {0x59u, 0x06u}, + {0x5Au, 0x24u}, {0x5Bu, 0x80u}, - {0x5Cu, 0x50u}, - {0x5Du, 0x09u}, - {0x60u, 0x08u}, - {0x62u, 0x40u}, - {0x63u, 0x08u}, - {0x65u, 0x80u}, - {0x81u, 0x08u}, - {0x82u, 0x40u}, - {0x83u, 0x80u}, - {0x85u, 0x20u}, - {0x87u, 0x08u}, - {0x89u, 0x20u}, - {0x8Bu, 0x80u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x04u}, - {0x90u, 0x20u}, - {0x91u, 0x10u}, - {0x93u, 0x10u}, - {0x94u, 0x04u}, - {0x96u, 0x06u}, - {0x98u, 0x04u}, - {0x9Au, 0x80u}, - {0x9Bu, 0x42u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x61u}, - {0x9Fu, 0x15u}, - {0xA0u, 0x80u}, - {0xA2u, 0x28u}, - {0xA3u, 0x08u}, - {0xA5u, 0x08u}, - {0xA6u, 0x80u}, - {0xA7u, 0x10u}, - {0xAAu, 0x40u}, - {0xACu, 0x10u}, - {0xAEu, 0x04u}, - {0xB0u, 0x04u}, - {0xB3u, 0x20u}, - {0xB6u, 0x28u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xE7u}, - {0xC4u, 0xCEu}, - {0xCAu, 0x72u}, - {0xCCu, 0xDFu}, - {0xCEu, 0x7Cu}, - {0xD6u, 0xFCu}, - {0xD8u, 0x1Cu}, - {0xE0u, 0x08u}, - {0xE6u, 0x03u}, - {0xE8u, 0x0Au}, - {0xEAu, 0x10u}, - {0xEEu, 0x06u}, - {0x01u, 0x02u}, - {0x02u, 0x02u}, - {0x03u, 0x01u}, - {0x05u, 0x01u}, - {0x07u, 0x06u}, + {0x61u, 0x10u}, + {0x63u, 0x91u}, + {0x68u, 0x24u}, + {0x69u, 0x40u}, + {0x6Au, 0x02u}, + {0x70u, 0x80u}, + {0x72u, 0xA8u}, + {0x78u, 0x08u}, + {0x7Au, 0x10u}, + {0x82u, 0x50u}, + {0x83u, 0x08u}, + {0x86u, 0x01u}, + {0x88u, 0x14u}, + {0x8Du, 0x40u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x08u}, + {0xC0u, 0xBFu}, + {0xC2u, 0xA9u}, + {0xC4u, 0xFCu}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0x90u}, + {0xD0u, 0x07u}, + {0xD2u, 0x08u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x05u}, + {0xE2u, 0x08u}, + {0xE4u, 0x03u}, + {0xE6u, 0xC0u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x01u}, + {0x10u, 0x0Au}, {0x11u, 0x04u}, + {0x12u, 0x05u}, {0x13u, 0x08u}, - {0x17u, 0x10u}, - {0x1Eu, 0x01u}, - {0x21u, 0x02u}, - {0x23u, 0x01u}, - {0x29u, 0x02u}, - {0x2Bu, 0x01u}, - {0x2Du, 0x02u}, - {0x2Fu, 0x29u}, - {0x30u, 0x01u}, - {0x31u, 0x20u}, + {0x15u, 0x02u}, + {0x16u, 0x07u}, + {0x17u, 0x11u}, + {0x19u, 0x01u}, + {0x1Bu, 0x06u}, + {0x1Cu, 0x09u}, + {0x1Du, 0x02u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x09u}, + {0x22u, 0x08u}, + {0x24u, 0x04u}, + {0x25u, 0x02u}, + {0x26u, 0x08u}, + {0x27u, 0x21u}, + {0x31u, 0x0Cu}, + {0x32u, 0x0Fu}, {0x33u, 0x03u}, - {0x34u, 0x02u}, - {0x35u, 0x10u}, - {0x37u, 0x0Cu}, + {0x35u, 0x20u}, + {0x37u, 0x10u}, {0x3Bu, 0x08u}, - {0x3Fu, 0x40u}, + {0x3Fu, 0x01u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -745,153 +621,161 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x0Du}, - {0x85u, 0x02u}, - {0x87u, 0x54u}, - {0x8Bu, 0x10u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x02u}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x0Du}, - {0x94u, 0x02u}, - {0x95u, 0x62u}, - {0x96u, 0x09u}, - {0x97u, 0x08u}, - {0x98u, 0x01u}, - {0x99u, 0x01u}, - {0x9Au, 0x02u}, - {0x9Bu, 0x32u}, - {0x9Cu, 0x02u}, - {0x9Eu, 0x05u}, - {0xA1u, 0x0Du}, - {0xA5u, 0x0Du}, - {0xA8u, 0x02u}, - {0xA9u, 0x0Du}, - {0xAAu, 0x11u}, - {0xADu, 0x0Du}, - {0xB0u, 0x04u}, - {0xB2u, 0x10u}, + {0x83u, 0x70u}, + {0x86u, 0x01u}, + {0x87u, 0x07u}, + {0x88u, 0x40u}, + {0x8Bu, 0x80u}, + {0x8Eu, 0x10u}, + {0x95u, 0x99u}, + {0x96u, 0x04u}, + {0x97u, 0x22u}, + {0x9Bu, 0x08u}, + {0x9Du, 0xAAu}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x55u}, + {0xA6u, 0x20u}, + {0xA9u, 0x44u}, + {0xAAu, 0x08u}, + {0xABu, 0x88u}, + {0xACu, 0x15u}, + {0xAEu, 0x2Au}, + {0xB0u, 0x40u}, + {0xB1u, 0xF0u}, + {0xB2u, 0x30u}, + {0xB3u, 0x0Fu}, {0xB4u, 0x03u}, - {0xB5u, 0x70u}, - {0xB6u, 0x08u}, - {0xB7u, 0x0Fu}, - {0xBAu, 0x20u}, - {0xBBu, 0x80u}, + {0xB6u, 0x0Cu}, + {0xBEu, 0x54u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x19u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x06u}, - {0x03u, 0x20u}, - {0x04u, 0x40u}, - {0x0Au, 0x02u}, - {0x0Eu, 0x1Au}, - {0x14u, 0x08u}, - {0x19u, 0x22u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x1Au}, - {0x20u, 0x01u}, - {0x21u, 0x45u}, - {0x22u, 0x91u}, - {0x25u, 0x50u}, - {0x28u, 0x02u}, - {0x29u, 0x22u}, - {0x2Cu, 0xA8u}, - {0x2Du, 0x40u}, - {0x30u, 0x02u}, - {0x32u, 0x08u}, - {0x36u, 0x20u}, - {0x37u, 0x08u}, + {0x00u, 0x24u}, + {0x02u, 0x02u}, + {0x08u, 0x80u}, + {0x0Au, 0x10u}, + {0x0Eu, 0x62u}, + {0x0Fu, 0x20u}, + {0x10u, 0x06u}, + {0x12u, 0x20u}, + {0x14u, 0x10u}, + {0x16u, 0x80u}, + {0x18u, 0x20u}, + {0x19u, 0x80u}, + {0x1Bu, 0x22u}, + {0x1Eu, 0x30u}, + {0x21u, 0x05u}, + {0x22u, 0x02u}, + {0x24u, 0x80u}, + {0x25u, 0x41u}, + {0x27u, 0x68u}, + {0x2Bu, 0x08u}, + {0x2Fu, 0x10u}, + {0x30u, 0x20u}, + {0x31u, 0x04u}, + {0x32u, 0x40u}, + {0x36u, 0x80u}, + {0x37u, 0x2Au}, + {0x38u, 0x04u}, {0x39u, 0x0Au}, - {0x3Cu, 0x08u}, - {0x3Du, 0xA0u}, - {0x3Eu, 0x02u}, - {0x58u, 0x10u}, - {0x5Au, 0x84u}, - {0x5Eu, 0x40u}, - {0x5Fu, 0x20u}, - {0x60u, 0x02u}, - {0x61u, 0x24u}, - {0x62u, 0x04u}, - {0x64u, 0x08u}, - {0x67u, 0x02u}, - {0x68u, 0x02u}, - {0x6Du, 0x08u}, - {0x6Fu, 0x1Au}, - {0x83u, 0x0Au}, - {0x84u, 0x10u}, - {0x85u, 0x08u}, - {0x86u, 0x04u}, - {0x8Bu, 0x20u}, - {0x8Du, 0x10u}, - {0x90u, 0x22u}, - {0x92u, 0x80u}, - {0x94u, 0x14u}, - {0x95u, 0x89u}, - {0x97u, 0x02u}, - {0x98u, 0x04u}, - {0x9Du, 0x45u}, - {0x9Eu, 0x30u}, - {0x9Fu, 0x15u}, - {0xA2u, 0x10u}, - {0xA3u, 0x20u}, - {0xA5u, 0x0Cu}, - {0xA6u, 0x84u}, - {0xA7u, 0x80u}, - {0xABu, 0x18u}, - {0xACu, 0x10u}, - {0xAEu, 0x04u}, - {0xB1u, 0x84u}, - {0xB3u, 0x01u}, - {0xC0u, 0x88u}, - {0xC2u, 0xE1u}, - {0xC4u, 0x40u}, - {0xCAu, 0xFDu}, - {0xCCu, 0x63u}, - {0xCEu, 0xF3u}, + {0x3Au, 0x2Au}, + {0x3Du, 0x80u}, + {0x58u, 0x60u}, + {0x5Au, 0x04u}, + {0x5Du, 0x20u}, + {0x5Fu, 0x40u}, + {0x60u, 0x0Au}, + {0x62u, 0x08u}, + {0x67u, 0x0Au}, + {0x6Bu, 0x02u}, + {0x6Cu, 0x04u}, + {0x6Du, 0x40u}, + {0x6Fu, 0x10u}, + {0x80u, 0x04u}, + {0x81u, 0x40u}, + {0x84u, 0xA0u}, + {0x88u, 0x18u}, + {0x8Bu, 0x0Au}, + {0x8Du, 0x0Cu}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x30u}, + {0x92u, 0xC0u}, + {0x93u, 0x40u}, + {0x96u, 0x20u}, + {0x97u, 0x13u}, + {0x99u, 0x20u}, + {0x9Au, 0xB0u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x12u}, + {0x9Fu, 0x50u}, + {0xA0u, 0xA0u}, + {0xA1u, 0x80u}, + {0xA2u, 0x01u}, + {0xA7u, 0x48u}, + {0xA9u, 0x28u}, + {0xAFu, 0x01u}, + {0xB2u, 0x08u}, + {0xB3u, 0x40u}, + {0xB5u, 0x80u}, + {0xB6u, 0xA0u}, + {0xC0u, 0x07u}, + {0xC2u, 0xB5u}, + {0xC4u, 0x37u}, + {0xCAu, 0x44u}, + {0xCCu, 0xFEu}, + {0xCEu, 0x17u}, {0xD6u, 0x3Eu}, {0xD8u, 0x3Eu}, - {0xE2u, 0x22u}, - {0xE6u, 0x16u}, - {0xECu, 0x09u}, - {0xEEu, 0x06u}, - {0x00u, 0x02u}, - {0x02u, 0x01u}, - {0x05u, 0x34u}, - {0x07u, 0x08u}, - {0x09u, 0x01u}, - {0x0Bu, 0x38u}, - {0x11u, 0x05u}, - {0x13u, 0x38u}, - {0x14u, 0x02u}, - {0x15u, 0x10u}, - {0x16u, 0x01u}, - {0x17u, 0x20u}, - {0x1Bu, 0x01u}, - {0x1Cu, 0x01u}, - {0x1Du, 0x30u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x08u}, - {0x21u, 0x02u}, - {0x23u, 0x30u}, - {0x28u, 0x02u}, - {0x2Au, 0x01u}, - {0x2Bu, 0x40u}, - {0x2Cu, 0x02u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x05u}, - {0x2Fu, 0x20u}, - {0x32u, 0x04u}, - {0x33u, 0x40u}, - {0x35u, 0x30u}, - {0x36u, 0x03u}, - {0x37u, 0x0Fu}, - {0x39u, 0x80u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x20u}, + {0xE6u, 0xCAu}, + {0xEAu, 0x02u}, + {0xECu, 0x04u}, + {0xEEu, 0x81u}, + {0x00u, 0x3Fu}, + {0x01u, 0x01u}, + {0x03u, 0x02u}, + {0x04u, 0x04u}, + {0x06u, 0x08u}, + {0x08u, 0x01u}, + {0x09u, 0x10u}, + {0x0Au, 0x02u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x10u}, + {0x0Du, 0x10u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x20u}, + {0x10u, 0x3Fu}, + {0x13u, 0x3Fu}, + {0x14u, 0x04u}, + {0x15u, 0x04u}, + {0x16u, 0x08u}, + {0x17u, 0x08u}, + {0x19u, 0x04u}, + {0x1Au, 0x3Fu}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x10u}, + {0x1Du, 0x3Fu}, + {0x1Eu, 0x20u}, + {0x22u, 0x3Fu}, + {0x23u, 0x3Fu}, + {0x25u, 0x01u}, + {0x27u, 0x02u}, + {0x28u, 0x01u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x3Fu}, + {0x2Du, 0x3Fu}, + {0x2Eu, 0x3Fu}, + {0x30u, 0x03u}, + {0x33u, 0x30u}, + {0x34u, 0x0Cu}, + {0x35u, 0x0Cu}, + {0x36u, 0x30u}, + {0x37u, 0x03u}, + {0x3Au, 0xA2u}, + {0x3Bu, 0xA8u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -899,1286 +783,1237 @@ void cyfitter_cfg(void) {0x5Cu, 0x11u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x01u}, - {0x82u, 0x3Fu}, - {0x84u, 0x04u}, - {0x86u, 0x08u}, - {0x88u, 0x10u}, - {0x8Au, 0x20u}, - {0x8Cu, 0x10u}, - {0x8Eu, 0x20u}, + {0x82u, 0x70u}, + {0x84u, 0x0Fu}, + {0x8Du, 0x02u}, {0x8Fu, 0x01u}, - {0x90u, 0x04u}, - {0x92u, 0x08u}, - {0x95u, 0x01u}, - {0x98u, 0x01u}, - {0x99u, 0x01u}, - {0x9Au, 0x02u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x01u}, - {0x9Eu, 0x02u}, - {0xA0u, 0x3Fu}, - {0xA1u, 0x02u}, - {0xA4u, 0x3Fu}, - {0xAAu, 0x3Fu}, - {0xAEu, 0x3Fu}, - {0xB0u, 0x30u}, - {0xB1u, 0x01u}, - {0xB3u, 0x02u}, - {0xB4u, 0x0Cu}, - {0xB6u, 0x03u}, - {0xBAu, 0xA2u}, - {0xBFu, 0x01u}, - {0xD6u, 0x08u}, + {0x90u, 0x40u}, + {0x91u, 0x01u}, + {0x92u, 0x1Fu}, + {0x93u, 0x02u}, + {0x94u, 0x06u}, + {0x95u, 0x02u}, + {0x96u, 0x09u}, + {0x97u, 0x05u}, + {0x98u, 0x05u}, + {0x99u, 0x02u}, + {0x9Au, 0x0Au}, + {0x9Bu, 0x09u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0x2Fu}, + {0xA4u, 0x03u}, + {0xA6u, 0x0Cu}, + {0xA9u, 0x02u}, + {0xABu, 0x11u}, + {0xACu, 0x20u}, + {0xAEu, 0x4Fu}, + {0xB0u, 0x7Fu}, + {0xB1u, 0x03u}, + {0xB3u, 0x08u}, + {0xB5u, 0x10u}, + {0xB7u, 0x04u}, + {0xBBu, 0x02u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x91u}, - {0xDDu, 0x90u}, + {0xDCu, 0x11u}, {0xDFu, 0x01u}, {0x00u, 0x04u}, - {0x01u, 0x01u}, - {0x02u, 0x04u}, - {0x03u, 0x02u}, - {0x07u, 0x40u}, - {0x08u, 0x02u}, - {0x09u, 0x20u}, - {0x0Au, 0x01u}, - {0x0Eu, 0x12u}, - {0x11u, 0x94u}, - {0x12u, 0x80u}, + {0x01u, 0x60u}, + {0x03u, 0x40u}, + {0x05u, 0x01u}, + {0x07u, 0x13u}, + {0x08u, 0x08u}, + {0x0Au, 0x46u}, + {0x0Cu, 0x60u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x02u}, + {0x0Fu, 0x40u}, + {0x10u, 0x40u}, + {0x11u, 0x10u}, + {0x13u, 0x40u}, {0x14u, 0x01u}, - {0x17u, 0x20u}, + {0x17u, 0x04u}, {0x18u, 0x04u}, - {0x19u, 0x41u}, - {0x1Au, 0x01u}, - {0x1Bu, 0x02u}, - {0x1Eu, 0x12u}, - {0x1Fu, 0x84u}, - {0x21u, 0x01u}, - {0x22u, 0x04u}, + {0x19u, 0x12u}, + {0x1Au, 0x02u}, + {0x1Bu, 0x40u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x80u}, + {0x22u, 0x10u}, + {0x23u, 0x11u}, + {0x24u, 0x40u}, {0x25u, 0x40u}, - {0x27u, 0x25u}, - {0x2Bu, 0x80u}, - {0x2Du, 0x01u}, - {0x2Fu, 0x09u}, - {0x30u, 0xA8u}, - {0x36u, 0x80u}, - {0x37u, 0x15u}, - {0x38u, 0x20u}, - {0x39u, 0x50u}, - {0x3Au, 0x02u}, - {0x3Du, 0x14u}, - {0x58u, 0x84u}, - {0x59u, 0x20u}, - {0x5Eu, 0x40u}, - {0x60u, 0x02u}, - {0x61u, 0x04u}, - {0x62u, 0x18u}, - {0x64u, 0x01u}, - {0x85u, 0x20u}, - {0x8Bu, 0x01u}, - {0x8Du, 0x04u}, + {0x26u, 0x16u}, + {0x28u, 0x51u}, + {0x2Bu, 0x08u}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x04u}, + {0x32u, 0x18u}, + {0x33u, 0x41u}, + {0x36u, 0x16u}, + {0x39u, 0x80u}, + {0x3Bu, 0x11u}, + {0x3Du, 0x80u}, + {0x5Au, 0x80u}, + {0x5Cu, 0x60u}, + {0x5Fu, 0x0Au}, + {0x62u, 0xC0u}, + {0x66u, 0x80u}, + {0x84u, 0x30u}, + {0x85u, 0x12u}, + {0x8Au, 0x08u}, + {0x8Du, 0x40u}, {0x8Eu, 0x40u}, - {0x90u, 0x23u}, - {0x91u, 0x05u}, - {0x92u, 0x20u}, - {0x93u, 0x02u}, - {0x94u, 0x04u}, - {0x95u, 0x40u}, - {0x96u, 0x08u}, - {0x98u, 0x04u}, - {0x9Au, 0x04u}, - {0x9Bu, 0x10u}, - {0x9Du, 0x41u}, - {0x9Eu, 0x12u}, - {0x9Fu, 0x0Du}, - {0xA1u, 0x20u}, - {0xA2u, 0x90u}, - {0xA4u, 0xACu}, - {0xA6u, 0x28u}, - {0xA7u, 0x80u}, - {0xAEu, 0x24u}, - {0xB1u, 0x01u}, - {0xB4u, 0x11u}, - {0xB6u, 0x40u}, - {0xB7u, 0x20u}, - {0xC0u, 0x1Fu}, - {0xC2u, 0xABu}, - {0xC4u, 0xCFu}, - {0xCAu, 0xB1u}, - {0xCCu, 0xFEu}, - {0xCEu, 0x69u}, - {0xD6u, 0x1Eu}, - {0xD8u, 0x1Eu}, - {0xE2u, 0x01u}, - {0xE6u, 0x03u}, - {0xEAu, 0x0Bu}, - {0xEEu, 0x08u}, - {0x01u, 0x02u}, - {0x03u, 0x01u}, - {0x04u, 0x06u}, - {0x09u, 0x02u}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x2Au}, - {0x0Eu, 0x11u}, - {0x10u, 0x19u}, - {0x11u, 0x01u}, - {0x12u, 0x24u}, - {0x13u, 0x02u}, - {0x14u, 0x20u}, - {0x15u, 0x02u}, - {0x16u, 0x18u}, - {0x17u, 0x09u}, - {0x18u, 0x09u}, - {0x19u, 0x02u}, - {0x1Au, 0x32u}, - {0x1Bu, 0x05u}, - {0x23u, 0x10u}, - {0x26u, 0x40u}, - {0x2Au, 0x80u}, - {0x2Cu, 0x40u}, - {0x2Eu, 0x80u}, - {0x31u, 0x08u}, - {0x32u, 0x38u}, - {0x33u, 0x04u}, - {0x34u, 0x07u}, - {0x35u, 0x10u}, - {0x36u, 0xC0u}, - {0x37u, 0x03u}, - {0x38u, 0x20u}, - {0x3Au, 0x08u}, - {0x3Bu, 0x80u}, - {0x3Eu, 0x40u}, - {0x54u, 0x09u}, - {0x56u, 0x04u}, + {0x90u, 0x80u}, + {0x91u, 0x80u}, + {0x92u, 0x40u}, + {0x93u, 0x0Au}, + {0x96u, 0x20u}, + {0x97u, 0x31u}, + {0x98u, 0x0Au}, + {0x9Au, 0x1Au}, + {0x9Bu, 0x70u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x12u}, + {0xA0u, 0x80u}, + {0xA1u, 0x89u}, + {0xA2u, 0x09u}, + {0xA3u, 0x10u}, + {0xA4u, 0x12u}, + {0xA6u, 0xA0u}, + {0xA7u, 0x48u}, + {0xA9u, 0x40u}, + {0xACu, 0x40u}, + {0xB1u, 0x80u}, + {0xB2u, 0x04u}, + {0xB4u, 0x50u}, + {0xC0u, 0x3Fu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xABu}, + {0xCAu, 0x2Fu}, + {0xCCu, 0xEFu}, + {0xCEu, 0x1Du}, + {0xD6u, 0xF8u}, + {0xD8u, 0x18u}, + {0xE2u, 0x02u}, + {0xE6u, 0x02u}, + {0xEAu, 0x03u}, + {0xEEu, 0xC8u}, + {0x00u, 0x01u}, + {0x01u, 0xFFu}, + {0x02u, 0x0Eu}, + {0x04u, 0x02u}, + {0x07u, 0xFFu}, + {0x09u, 0x0Fu}, + {0x0Bu, 0xF0u}, + {0x0Cu, 0x04u}, + {0x0Du, 0xFFu}, + {0x10u, 0x18u}, + {0x11u, 0x69u}, + {0x12u, 0x03u}, + {0x13u, 0x96u}, + {0x14u, 0x03u}, + {0x15u, 0x55u}, + {0x16u, 0x14u}, + {0x17u, 0xAAu}, + {0x1Au, 0x1Fu}, + {0x1Eu, 0x08u}, + {0x22u, 0x20u}, + {0x23u, 0xFFu}, + {0x2Au, 0x01u}, + {0x2Bu, 0xFFu}, + {0x2Du, 0x33u}, + {0x2Fu, 0xCCu}, + {0x32u, 0x1Fu}, + {0x34u, 0x20u}, + {0x35u, 0xFFu}, + {0x3Bu, 0x20u}, + {0x54u, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x10u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x84u, 0x06u}, - {0x86u, 0x09u}, - {0x87u, 0xFFu}, - {0x88u, 0x05u}, - {0x89u, 0x50u}, - {0x8Au, 0x0Au}, - {0x8Bu, 0xA0u}, - {0x8Cu, 0x60u}, - {0x8Eu, 0x90u}, - {0x90u, 0x0Fu}, - {0x91u, 0x90u}, - {0x92u, 0xF0u}, - {0x93u, 0x60u}, - {0x94u, 0x50u}, - {0x95u, 0x30u}, - {0x96u, 0xA0u}, - {0x97u, 0xC0u}, - {0x98u, 0x03u}, - {0x99u, 0x09u}, - {0x9Au, 0x0Cu}, - {0x9Bu, 0x06u}, - {0x9Du, 0x0Fu}, - {0x9Fu, 0xF0u}, - {0xA2u, 0xFFu}, - {0xA3u, 0xFFu}, - {0xA4u, 0x30u}, - {0xA5u, 0x03u}, - {0xA6u, 0xC0u}, - {0xA7u, 0x0Cu}, - {0xA8u, 0xFFu}, - {0xA9u, 0x05u}, - {0xABu, 0x0Au}, - {0xAEu, 0xFFu}, - {0xAFu, 0xFFu}, - {0xB3u, 0xFFu}, - {0xB4u, 0xFFu}, - {0xBEu, 0x10u}, - {0xBFu, 0x04u}, - {0xD4u, 0x01u}, + {0x81u, 0x04u}, + {0x82u, 0x10u}, + {0x83u, 0x20u}, + {0x85u, 0x01u}, + {0x87u, 0x5Eu}, + {0x88u, 0x04u}, + {0x89u, 0x39u}, + {0x8Au, 0x08u}, + {0x8Bu, 0x06u}, + {0x8Du, 0x46u}, + {0x8Eu, 0x07u}, + {0x90u, 0x0Au}, + {0x91u, 0x46u}, + {0x92u, 0x05u}, + {0x97u, 0x46u}, + {0x99u, 0x42u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x09u}, + {0x9Du, 0x46u}, + {0x9Eu, 0x02u}, + {0xA1u, 0x42u}, + {0xA2u, 0x08u}, + {0xA4u, 0x10u}, + {0xA6u, 0x20u}, + {0xAAu, 0x20u}, + {0xADu, 0x77u}, + {0xAFu, 0x08u}, + {0xB0u, 0x0Fu}, + {0xB1u, 0x08u}, + {0xB2u, 0x30u}, + {0xB3u, 0x70u}, + {0xB5u, 0x0Fu}, + {0xB7u, 0x01u}, + {0xB8u, 0x80u}, + {0xB9u, 0x20u}, + {0xBBu, 0x0Cu}, + {0xBEu, 0x44u}, + {0xBFu, 0x41u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDDu, 0x10u}, + {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x01u, 0x10u}, - {0x03u, 0x21u}, - {0x04u, 0x04u}, - {0x05u, 0x80u}, - {0x08u, 0x20u}, - {0x0Au, 0x80u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x10u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x80u}, - {0x11u, 0x04u}, - {0x12u, 0x45u}, - {0x14u, 0x24u}, - {0x17u, 0x40u}, - {0x19u, 0x20u}, - {0x1Cu, 0x04u}, - {0x1Eu, 0x22u}, - {0x1Fu, 0x04u}, - {0x20u, 0x10u}, - {0x24u, 0x08u}, - {0x25u, 0x01u}, - {0x26u, 0x08u}, - {0x27u, 0x02u}, - {0x28u, 0x20u}, - {0x29u, 0x04u}, - {0x2Au, 0x41u}, - {0x2Bu, 0x05u}, - {0x2Du, 0x02u}, - {0x30u, 0x04u}, - {0x32u, 0x44u}, - {0x33u, 0x61u}, - {0x35u, 0x10u}, + {0x00u, 0x40u}, + {0x02u, 0x80u}, + {0x03u, 0x08u}, + {0x04u, 0x80u}, + {0x05u, 0x02u}, + {0x06u, 0x10u}, + {0x0Au, 0x41u}, + {0x0Du, 0x80u}, + {0x0Eu, 0x64u}, + {0x10u, 0x80u}, + {0x13u, 0x28u}, + {0x16u, 0x40u}, + {0x17u, 0x10u}, + {0x18u, 0x40u}, + {0x1Au, 0x20u}, + {0x1Bu, 0x40u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x18u}, + {0x20u, 0x08u}, + {0x21u, 0x14u}, + {0x23u, 0x95u}, + {0x25u, 0x10u}, + {0x27u, 0x04u}, + {0x29u, 0x41u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x09u}, + {0x30u, 0x28u}, + {0x33u, 0x41u}, + {0x34u, 0x02u}, {0x36u, 0x08u}, - {0x37u, 0x02u}, - {0x39u, 0x28u}, - {0x3Au, 0x04u}, - {0x3Bu, 0x20u}, - {0x3Du, 0x02u}, - {0x3Fu, 0x20u}, - {0x59u, 0x40u}, - {0x5Cu, 0x0Au}, - {0x5Eu, 0x90u}, - {0x64u, 0x40u}, - {0x67u, 0x02u}, - {0x8Bu, 0x04u}, - {0x8Fu, 0x10u}, - {0x91u, 0x3Cu}, - {0x92u, 0x88u}, + {0x38u, 0x02u}, + {0x39u, 0x6Au}, + {0x3Du, 0x22u}, + {0x3Eu, 0x44u}, + {0x58u, 0x20u}, + {0x59u, 0x04u}, + {0x5Au, 0x02u}, + {0x5Bu, 0x80u}, + {0x5Du, 0x02u}, + {0x5Eu, 0x83u}, + {0x62u, 0x01u}, + {0x63u, 0x01u}, + {0x68u, 0x02u}, + {0x80u, 0x21u}, + {0x83u, 0x40u}, + {0x8Au, 0xA0u}, + {0x8Cu, 0x40u}, + {0x90u, 0x80u}, + {0x92u, 0x44u}, {0x93u, 0x02u}, - {0x94u, 0x10u}, - {0x97u, 0x80u}, - {0x99u, 0x04u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x40u}, - {0x9Du, 0x20u}, - {0x9Eu, 0x01u}, - {0x9Fu, 0x42u}, - {0xA2u, 0x40u}, - {0xA3u, 0x25u}, - {0xA5u, 0x04u}, - {0xA6u, 0x21u}, - {0xA7u, 0x40u}, - {0xAAu, 0x04u}, - {0xABu, 0x05u}, - {0xACu, 0x40u}, - {0xAEu, 0x40u}, - {0xB2u, 0x01u}, - {0xB6u, 0x82u}, - {0xB7u, 0x02u}, - {0xC0u, 0xA7u}, - {0xC2u, 0x7Eu}, - {0xC4u, 0xEFu}, - {0xCAu, 0x8Fu}, - {0xCCu, 0xEFu}, - {0xCEu, 0xA6u}, - {0xD6u, 0xF8u}, - {0xD8u, 0x90u}, - {0xE0u, 0x10u}, - {0xE2u, 0x81u}, - {0xE6u, 0x43u}, - {0xE8u, 0x40u}, - {0xEAu, 0x12u}, - {0xECu, 0x10u}, - {0xEEu, 0xC0u}, - {0x00u, 0x0Fu}, - {0x02u, 0xF0u}, - {0x04u, 0x09u}, - {0x06u, 0x06u}, - {0x07u, 0xFFu}, - {0x08u, 0x05u}, - {0x09u, 0x50u}, - {0x0Au, 0x0Au}, - {0x0Bu, 0xA0u}, - {0x0Cu, 0x90u}, - {0x0Eu, 0x60u}, - {0x10u, 0x03u}, - {0x11u, 0x60u}, - {0x12u, 0x0Cu}, - {0x13u, 0x90u}, - {0x15u, 0x30u}, - {0x16u, 0xFFu}, - {0x17u, 0xC0u}, - {0x18u, 0xFFu}, - {0x19u, 0x06u}, - {0x1Bu, 0x09u}, - {0x1Du, 0x0Fu}, - {0x1Fu, 0xF0u}, - {0x23u, 0xFFu}, + {0x97u, 0x20u}, + {0x98u, 0x06u}, + {0x9Au, 0x52u}, + {0x9Bu, 0x10u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x80u}, + {0xA1u, 0x81u}, + {0xA2u, 0x49u}, + {0xA3u, 0x10u}, + {0xA4u, 0x12u}, + {0xA6u, 0x20u}, + {0xA7u, 0x08u}, + {0xA8u, 0x20u}, + {0xA9u, 0x20u}, + {0xAAu, 0x80u}, + {0xABu, 0x20u}, + {0xACu, 0x10u}, + {0xAEu, 0x04u}, + {0xAFu, 0x09u}, + {0xB0u, 0x04u}, + {0xB3u, 0x48u}, + {0xB6u, 0x01u}, + {0xB7u, 0x10u}, + {0xC0u, 0xBBu}, + {0xC2u, 0xF9u}, + {0xC4u, 0x5Eu}, + {0xCAu, 0xB9u}, + {0xCCu, 0xCFu}, + {0xCEu, 0xFFu}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x09u}, + {0xE2u, 0x09u}, + {0xE6u, 0x02u}, + {0xEAu, 0x02u}, + {0xEEu, 0x07u}, + {0x88u, 0x04u}, + {0x89u, 0x40u}, + {0x8Fu, 0x04u}, + {0x99u, 0x40u}, + {0x9Cu, 0x84u}, + {0xA0u, 0x24u}, + {0xA7u, 0x04u}, + {0xA8u, 0x02u}, + {0xA9u, 0x10u}, + {0xAAu, 0x40u}, + {0xAEu, 0x20u}, + {0xAFu, 0x04u}, + {0xB0u, 0x42u}, + {0xB6u, 0x08u}, + {0xB7u, 0x08u}, + {0xE0u, 0x40u}, + {0xE2u, 0xA9u}, + {0xE6u, 0x02u}, + {0xE8u, 0x10u}, + {0xEAu, 0x04u}, + {0xECu, 0x40u}, + {0xEEu, 0x80u}, + {0x02u, 0xFFu}, + {0x05u, 0x10u}, + {0x06u, 0xFFu}, + {0x08u, 0x50u}, + {0x0Au, 0xA0u}, + {0x0Bu, 0x08u}, + {0x0Fu, 0x04u}, + {0x10u, 0x05u}, + {0x12u, 0x0Au}, + {0x13u, 0x02u}, + {0x14u, 0x0Fu}, + {0x15u, 0x05u}, + {0x16u, 0xF0u}, + {0x17u, 0x0Au}, + {0x18u, 0x03u}, + {0x1Au, 0x0Cu}, + {0x1Cu, 0x06u}, + {0x1Eu, 0x09u}, + {0x20u, 0xFFu}, + {0x23u, 0x01u}, {0x24u, 0x30u}, - {0x25u, 0x03u}, {0x26u, 0xC0u}, - {0x27u, 0x0Cu}, - {0x28u, 0x50u}, - {0x29u, 0x05u}, - {0x2Au, 0xA0u}, - {0x2Bu, 0x0Au}, - {0x2Cu, 0xFFu}, - {0x2Du, 0xFFu}, - {0x31u, 0xFFu}, - {0x32u, 0xFFu}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, + {0x2Cu, 0x60u}, + {0x2Eu, 0x90u}, + {0x31u, 0x0Cu}, + {0x33u, 0x03u}, + {0x35u, 0x10u}, + {0x36u, 0xFFu}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x05u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x02u}, - {0x84u, 0x04u}, - {0x86u, 0x38u}, - {0x88u, 0x10u}, - {0x8Au, 0x20u}, - {0x8Cu, 0x10u}, - {0x8Du, 0x05u}, - {0x8Eu, 0x20u}, - {0x96u, 0x07u}, - {0x98u, 0x09u}, - {0x99u, 0x01u}, - {0x9Au, 0x32u}, - {0x9Bu, 0x04u}, - {0x9Eu, 0x30u}, - {0xA0u, 0x30u}, - {0xA1u, 0x01u}, - {0xA3u, 0x04u}, - {0xAAu, 0x08u}, - {0xACu, 0x3Au}, - {0xAEu, 0x05u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x01u}, - {0xB4u, 0x30u}, - {0xB5u, 0x02u}, - {0xB7u, 0x04u}, + {0x80u, 0x02u}, + {0x81u, 0x09u}, + {0x82u, 0x01u}, + {0x83u, 0x06u}, + {0x85u, 0x30u}, + {0x86u, 0x80u}, + {0x87u, 0xC0u}, + {0x88u, 0x01u}, + {0x89u, 0x50u}, + {0x8Au, 0x02u}, + {0x8Bu, 0xA0u}, + {0x8Du, 0x03u}, + {0x8Eu, 0x70u}, + {0x8Fu, 0x0Cu}, + {0x93u, 0xFFu}, + {0x94u, 0x02u}, + {0x96u, 0x05u}, + {0x97u, 0xFFu}, + {0x9Cu, 0x02u}, + {0x9Eu, 0x01u}, + {0x9Fu, 0xFFu}, + {0xA0u, 0x40u}, + {0xA1u, 0x05u}, + {0xA2u, 0x80u}, + {0xA3u, 0x0Au}, + {0xA4u, 0xA0u}, + {0xA6u, 0x50u}, + {0xA8u, 0x90u}, + {0xA9u, 0x0Fu}, + {0xAAu, 0x20u}, + {0xABu, 0xF0u}, + {0xACu, 0x02u}, + {0xADu, 0x90u}, + {0xAEu, 0x09u}, + {0xAFu, 0x60u}, + {0xB0u, 0x04u}, + {0xB2u, 0x08u}, + {0xB4u, 0x03u}, + {0xB5u, 0xFFu}, + {0xB6u, 0xF0u}, {0xBAu, 0x20u}, - {0xBFu, 0x44u}, + {0xBFu, 0x10u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x91u}, + {0xDCu, 0x01u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x10u}, - {0x03u, 0x61u}, - {0x05u, 0x90u}, - {0x06u, 0x20u}, - {0x08u, 0x12u}, - {0x09u, 0x04u}, - {0x0Cu, 0x20u}, - {0x0Eu, 0x21u}, - {0x10u, 0x09u}, - {0x11u, 0x04u}, - {0x14u, 0x10u}, - {0x15u, 0x08u}, - {0x16u, 0x8Au}, - {0x19u, 0x08u}, - {0x1Du, 0x14u}, - {0x1Eu, 0x24u}, - {0x21u, 0x01u}, - {0x26u, 0x44u}, + {0x01u, 0x18u}, + {0x03u, 0x40u}, + {0x05u, 0x55u}, + {0x08u, 0x14u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x80u}, + {0x0Du, 0x80u}, + {0x0Eu, 0x20u}, + {0x11u, 0x44u}, + {0x13u, 0x02u}, + {0x15u, 0x82u}, + {0x16u, 0x28u}, + {0x18u, 0x02u}, + {0x1Du, 0x51u}, + {0x1Eu, 0x20u}, + {0x20u, 0x80u}, + {0x22u, 0x28u}, {0x27u, 0x04u}, - {0x28u, 0x01u}, - {0x29u, 0x04u}, - {0x2Au, 0x01u}, - {0x2Bu, 0x05u}, - {0x2Fu, 0x40u}, - {0x32u, 0x44u}, - {0x33u, 0x21u}, - {0x36u, 0x20u}, - {0x39u, 0x28u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x80u}, - {0x5Cu, 0x80u}, - {0x66u, 0x40u}, - {0x68u, 0x88u}, - {0x69u, 0x24u}, - {0x6Au, 0x08u}, - {0x6Bu, 0x01u}, - {0x71u, 0x60u}, - {0x72u, 0x50u}, - {0x79u, 0x10u}, - {0x7Bu, 0x04u}, - {0x80u, 0x80u}, - {0x86u, 0x04u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x04u}, - {0x91u, 0x08u}, - {0x92u, 0x81u}, - {0x94u, 0x10u}, - {0x95u, 0x22u}, - {0x96u, 0x50u}, - {0x99u, 0x80u}, - {0x9Au, 0x28u}, - {0x9Du, 0x68u}, - {0x9Eu, 0xC2u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x20u}, - {0xA3u, 0x25u}, - {0xA4u, 0x80u}, - {0xA5u, 0x20u}, - {0xA6u, 0x01u}, - {0xA8u, 0x81u}, - {0xAFu, 0x80u}, - {0xB0u, 0x20u}, - {0xB1u, 0x08u}, - {0xC0u, 0xEFu}, - {0xC2u, 0xEEu}, - {0xC4u, 0xD7u}, - {0xCAu, 0x8Fu}, - {0xCCu, 0x2Fu}, - {0xCEu, 0x96u}, - {0xD6u, 0x10u}, - {0xD8u, 0x10u}, - {0xE2u, 0x20u}, - {0xE6u, 0x27u}, - {0xECu, 0x20u}, - {0xEEu, 0x02u}, - {0x00u, 0x03u}, - {0x04u, 0x10u}, - {0x06u, 0x23u}, - {0x0Au, 0x20u}, - {0x0Bu, 0x08u}, - {0x0Cu, 0x2Bu}, - {0x0Du, 0x0Au}, - {0x0Eu, 0x14u}, - {0x0Fu, 0x05u}, - {0x13u, 0x20u}, - {0x14u, 0x24u}, - {0x16u, 0x0Bu}, - {0x1Au, 0x5Cu}, - {0x1Bu, 0x17u}, - {0x1Eu, 0x03u}, - {0x20u, 0x01u}, - {0x22u, 0x02u}, - {0x24u, 0x01u}, - {0x25u, 0x09u}, - {0x26u, 0x02u}, - {0x27u, 0x02u}, - {0x29u, 0x04u}, - {0x2Au, 0x80u}, - {0x2Bu, 0x08u}, - {0x2Cu, 0x40u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x80u}, - {0x2Fu, 0x20u}, - {0x32u, 0x03u}, - {0x34u, 0x3Cu}, - {0x35u, 0x0Fu}, - {0x36u, 0xC0u}, - {0x37u, 0x30u}, - {0x3Au, 0x08u}, - {0x3Eu, 0x40u}, + {0x2Au, 0x02u}, + {0x2Cu, 0x04u}, + {0x2Fu, 0x42u}, + {0x30u, 0x04u}, + {0x33u, 0x02u}, + {0x34u, 0x80u}, + {0x35u, 0x08u}, + {0x37u, 0x49u}, + {0x39u, 0x10u}, + {0x3Bu, 0x84u}, + {0x3Du, 0x14u}, + {0x3Eu, 0x03u}, {0x3Fu, 0x40u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Fu, 0x01u}, - {0x81u, 0x10u}, - {0x84u, 0x06u}, - {0x85u, 0x01u}, - {0x86u, 0x09u}, - {0x87u, 0x02u}, - {0x89u, 0x10u}, - {0x8Cu, 0x0Fu}, - {0x8Du, 0x23u}, - {0x8Eu, 0xF0u}, - {0x8Fu, 0x4Cu}, - {0x90u, 0x30u}, - {0x92u, 0xC0u}, - {0x93u, 0x40u}, - {0x94u, 0x50u}, - {0x96u, 0xA0u}, - {0x98u, 0x60u}, - {0x9Au, 0x90u}, - {0x9Bu, 0x20u}, - {0x9Du, 0x08u}, - {0x9Fu, 0x04u}, - {0xA1u, 0x02u}, - {0xA3u, 0x01u}, - {0xA4u, 0x03u}, - {0xA5u, 0x10u}, - {0xA6u, 0x0Cu}, - {0xA8u, 0x05u}, - {0xA9u, 0x10u}, - {0xAAu, 0x0Au}, - {0xADu, 0x04u}, - {0xAFu, 0x08u}, - {0xB0u, 0xFFu}, - {0xB1u, 0x10u}, - {0xB3u, 0x0Fu}, - {0xB5u, 0x60u}, - {0xB9u, 0x02u}, - {0xBEu, 0x01u}, - {0xBFu, 0x15u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x40u}, - {0x05u, 0x10u}, - {0x06u, 0xA2u}, - {0x08u, 0x08u}, - {0x09u, 0x20u}, - {0x0Au, 0x50u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x09u}, - {0x0Fu, 0x08u}, - {0x12u, 0x18u}, - {0x13u, 0x08u}, - {0x14u, 0x10u}, - {0x15u, 0xA0u}, - {0x16u, 0x40u}, - {0x1Bu, 0x01u}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x08u}, - {0x20u, 0x08u}, - {0x21u, 0x04u}, - {0x22u, 0x01u}, - {0x24u, 0x0Au}, - {0x26u, 0x20u}, - {0x28u, 0x01u}, - {0x29u, 0x68u}, - {0x2Bu, 0x80u}, - {0x2Cu, 0x24u}, - {0x2Du, 0x40u}, - {0x2Eu, 0x20u}, - {0x30u, 0x80u}, - {0x33u, 0x21u}, - {0x34u, 0x01u}, - {0x36u, 0x20u}, - {0x38u, 0x18u}, - {0x39u, 0xC2u}, - {0x3Du, 0x80u}, - {0x3Fu, 0x20u}, - {0x5Cu, 0x80u}, - {0x5Du, 0x05u}, - {0x5Eu, 0x20u}, - {0x64u, 0x02u}, - {0x78u, 0x02u}, - {0x7Au, 0x80u}, - {0x84u, 0x10u}, - {0x85u, 0x01u}, - {0x87u, 0x08u}, - {0x88u, 0x05u}, - {0x8Bu, 0x08u}, - {0x90u, 0x04u}, - {0x91u, 0x84u}, - {0x92u, 0x81u}, - {0x96u, 0x42u}, - {0x98u, 0x04u}, - {0x99u, 0x90u}, - {0x9Au, 0x08u}, - {0x9Cu, 0x08u}, - {0x9Eu, 0x10u}, - {0xA1u, 0x40u}, - {0xA2u, 0x98u}, - {0xA3u, 0x30u}, - {0xA4u, 0xA0u}, - {0xA5u, 0x28u}, - {0xA6u, 0x01u}, - {0xA7u, 0x80u}, - {0xAAu, 0x01u}, + {0x58u, 0x40u}, + {0x5Eu, 0x40u}, + {0x5Fu, 0x10u}, + {0x60u, 0x02u}, + {0x63u, 0x02u}, + {0x65u, 0x20u}, + {0x66u, 0x80u}, + {0x67u, 0x02u}, + {0x85u, 0x20u}, + {0x86u, 0x04u}, + {0x88u, 0x50u}, + {0x8Bu, 0x48u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x01u}, + {0x91u, 0xD6u}, + {0x92u, 0x05u}, + {0x93u, 0x94u}, + {0x94u, 0x02u}, + {0x99u, 0x04u}, + {0x9Au, 0x20u}, + {0x9Bu, 0x03u}, + {0x9Cu, 0x14u}, + {0x9Du, 0x28u}, + {0x9Eu, 0x82u}, + {0x9Fu, 0x44u}, + {0xA0u, 0x26u}, + {0xA1u, 0x80u}, + {0xA3u, 0x02u}, + {0xA7u, 0x0Du}, {0xABu, 0x01u}, - {0xACu, 0x04u}, - {0xADu, 0x41u}, - {0xAEu, 0x05u}, - {0xB2u, 0x10u}, - {0xB4u, 0x80u}, - {0xB7u, 0x40u}, - {0xC0u, 0xF5u}, - {0xC2u, 0xEEu}, - {0xC4u, 0xF6u}, - {0xCAu, 0x7Fu}, - {0xCCu, 0xADu}, - {0xCEu, 0x3Fu}, - {0xD6u, 0xF0u}, - {0xD8u, 0x10u}, - {0xE4u, 0x80u}, - {0xE6u, 0x21u}, - {0xE8u, 0x80u}, - {0xECu, 0x09u}, - {0xEEu, 0xC0u}, - {0x00u, 0x80u}, - {0x02u, 0x40u}, - {0x06u, 0x1Cu}, - {0x0Cu, 0x80u}, - {0x0Du, 0x0Au}, - {0x0Eu, 0x41u}, - {0x0Fu, 0x14u}, - {0x14u, 0x24u}, - {0x16u, 0x08u}, - {0x18u, 0x80u}, - {0x1Au, 0x40u}, - {0x1Bu, 0x04u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x80u}, - {0x1Fu, 0x10u}, - {0x20u, 0x80u}, - {0x22u, 0x42u}, - {0x23u, 0x08u}, - {0x26u, 0x20u}, - {0x27u, 0x02u}, - {0x28u, 0x10u}, - {0x2Au, 0x20u}, - {0x2Cu, 0x28u}, - {0x2Eu, 0x14u}, - {0x2Fu, 0x01u}, - {0x30u, 0x01u}, - {0x31u, 0x01u}, - {0x32u, 0x3Cu}, - {0x33u, 0x18u}, - {0x34u, 0x02u}, - {0x36u, 0xC0u}, - {0x37u, 0x06u}, - {0x3Au, 0x80u}, - {0x3Fu, 0x44u}, + {0xAEu, 0x40u}, + {0xAFu, 0x20u}, + {0xB3u, 0x10u}, + {0xB7u, 0x80u}, + {0xC0u, 0xFEu}, + {0xC2u, 0xAFu}, + {0xC4u, 0xFDu}, + {0xCAu, 0xB1u}, + {0xCCu, 0xD3u}, + {0xCEu, 0xFEu}, + {0xD6u, 0x38u}, + {0xD8u, 0x38u}, + {0xE0u, 0x20u}, + {0xE2u, 0x50u}, + {0xECu, 0x10u}, + {0xEEu, 0x2Au}, + {0x04u, 0xFFu}, + {0x05u, 0x01u}, + {0x07u, 0x12u}, + {0x08u, 0x55u}, + {0x0Au, 0xAAu}, + {0x0Du, 0x04u}, + {0x0Fu, 0x28u}, + {0x15u, 0x53u}, + {0x16u, 0xFFu}, + {0x17u, 0xACu}, + {0x18u, 0x0Fu}, + {0x19u, 0x02u}, + {0x1Au, 0xF0u}, + {0x1Bu, 0x41u}, + {0x1Cu, 0x33u}, + {0x1Eu, 0xCCu}, + {0x21u, 0x08u}, + {0x22u, 0xFFu}, + {0x23u, 0x84u}, + {0x24u, 0x69u}, + {0x26u, 0x96u}, + {0x2Au, 0xFFu}, + {0x2Cu, 0xFFu}, + {0x31u, 0xC0u}, + {0x33u, 0x30u}, + {0x34u, 0xFFu}, + {0x37u, 0x0Fu}, + {0x3Au, 0x20u}, + {0x3Fu, 0x45u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x01u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x44u}, - {0x83u, 0x08u}, - {0x86u, 0x10u}, - {0x87u, 0x17u}, - {0x8Bu, 0x40u}, - {0x8Cu, 0x0Au}, - {0x8Du, 0x4Au}, - {0x8Eu, 0x05u}, - {0x8Fu, 0x05u}, - {0x91u, 0x10u}, - {0x92u, 0x20u}, - {0x93u, 0x20u}, - {0x94u, 0x09u}, - {0x96u, 0x02u}, - {0x97u, 0x20u}, - {0x9Au, 0x07u}, - {0xA0u, 0x04u}, - {0xA2u, 0x08u}, - {0xA5u, 0x49u}, - {0xA7u, 0x02u}, - {0xAAu, 0x08u}, - {0xABu, 0x08u}, - {0xACu, 0x10u}, - {0xAEu, 0x20u}, - {0xB0u, 0x30u}, - {0xB1u, 0x30u}, - {0xB3u, 0x0Fu}, - {0xB4u, 0x0Fu}, - {0xB7u, 0x40u}, - {0xBEu, 0x01u}, - {0xBFu, 0x41u}, + {0x80u, 0xFFu}, + {0x81u, 0xFFu}, + {0x85u, 0x30u}, + {0x86u, 0xFFu}, + {0x87u, 0xC0u}, + {0x88u, 0x03u}, + {0x89u, 0x50u}, + {0x8Au, 0x0Cu}, + {0x8Bu, 0xA0u}, + {0x8Du, 0x05u}, + {0x8Fu, 0x0Au}, + {0x90u, 0x05u}, + {0x91u, 0x60u}, + {0x92u, 0x0Au}, + {0x93u, 0x90u}, + {0x94u, 0x0Fu}, + {0x96u, 0xF0u}, + {0x99u, 0x03u}, + {0x9Bu, 0x0Cu}, + {0x9Cu, 0x09u}, + {0x9Eu, 0x06u}, + {0x9Fu, 0xFFu}, + {0xA0u, 0xFFu}, + {0xA1u, 0x06u}, + {0xA3u, 0x09u}, + {0xA4u, 0x30u}, + {0xA6u, 0xC0u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x50u}, + {0xA9u, 0x0Fu}, + {0xAAu, 0xA0u}, + {0xABu, 0xF0u}, + {0xACu, 0x90u}, + {0xAEu, 0x60u}, + {0xB2u, 0xFFu}, + {0xB7u, 0xFFu}, + {0xBEu, 0x04u}, + {0xBFu, 0x40u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x84u}, - {0x01u, 0x08u}, - {0x02u, 0x40u}, - {0x04u, 0x40u}, - {0x06u, 0x10u}, - {0x09u, 0x08u}, - {0x0Au, 0x05u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x48u}, - {0x10u, 0x54u}, - {0x11u, 0x80u}, - {0x15u, 0x85u}, - {0x16u, 0x24u}, - {0x19u, 0x0Au}, - {0x1Au, 0x05u}, - {0x1Bu, 0x40u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x21u}, - {0x20u, 0x82u}, - {0x22u, 0x04u}, - {0x25u, 0x06u}, - {0x26u, 0x88u}, + {0x01u, 0x09u}, + {0x03u, 0x48u}, + {0x05u, 0x20u}, + {0x06u, 0x20u}, + {0x08u, 0x04u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x08u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x22u}, + {0x11u, 0x54u}, + {0x13u, 0x02u}, + {0x14u, 0x20u}, + {0x15u, 0x22u}, + {0x17u, 0x80u}, + {0x18u, 0x20u}, + {0x1Eu, 0x04u}, + {0x22u, 0x40u}, + {0x25u, 0x02u}, + {0x26u, 0x80u}, + {0x27u, 0x23u}, + {0x28u, 0x04u}, {0x29u, 0x08u}, - {0x2Au, 0x40u}, - {0x2Bu, 0x80u}, - {0x2Cu, 0x60u}, - {0x2Du, 0x02u}, - {0x2Eu, 0x10u}, - {0x30u, 0x80u}, - {0x31u, 0x20u}, - {0x34u, 0x08u}, - {0x37u, 0x01u}, - {0x39u, 0x80u}, - {0x3Cu, 0x40u}, - {0x3Du, 0x89u}, - {0x3Eu, 0x20u}, - {0x58u, 0x80u}, - {0x5Du, 0x40u}, - {0x62u, 0x40u}, - {0x64u, 0x02u}, - {0x65u, 0x80u}, - {0x69u, 0x80u}, - {0x6Au, 0x80u}, - {0x6Bu, 0x01u}, - {0x81u, 0x40u}, - {0x82u, 0x24u}, - {0x83u, 0x10u}, - {0x84u, 0x01u}, - {0x85u, 0x02u}, - {0x86u, 0x08u}, - {0x88u, 0x10u}, - {0x8Cu, 0x02u}, + {0x2Au, 0x02u}, + {0x2Cu, 0x80u}, + {0x30u, 0x10u}, + {0x32u, 0x80u}, + {0x33u, 0x02u}, + {0x34u, 0x04u}, + {0x36u, 0x10u}, + {0x39u, 0x15u}, + {0x3Bu, 0x80u}, + {0x3Cu, 0x80u}, + {0x3Fu, 0x08u}, + {0x5Au, 0x40u}, + {0x5Eu, 0x80u}, + {0x61u, 0xC0u}, + {0x64u, 0x01u}, + {0x67u, 0x01u}, + {0x6Cu, 0x80u}, + {0x6Du, 0x54u}, + {0x6Fu, 0x02u}, + {0x74u, 0x66u}, + {0x85u, 0x04u}, + {0x88u, 0x20u}, + {0x89u, 0x03u}, + {0x8Cu, 0x80u}, {0x8Du, 0x10u}, - {0x8Eu, 0x10u}, - {0xC0u, 0xADu}, - {0xC2u, 0x77u}, - {0xC4u, 0xDFu}, - {0xCAu, 0x6Bu}, - {0xCCu, 0xCCu}, - {0xCEu, 0xF8u}, + {0x8Fu, 0x10u}, + {0x91u, 0xA0u}, + {0x92u, 0x41u}, + {0x93u, 0x84u}, + {0x94u, 0x22u}, + {0x96u, 0x80u}, + {0x99u, 0x04u}, + {0x9Au, 0x20u}, + {0x9Cu, 0x81u}, + {0x9Du, 0x40u}, + {0x9Eu, 0x80u}, + {0x9Fu, 0x84u}, + {0xA1u, 0x10u}, + {0xA2u, 0x10u}, + {0xA4u, 0x08u}, + {0xA9u, 0x02u}, + {0xAFu, 0x04u}, + {0xB1u, 0x80u}, + {0xB5u, 0x08u}, + {0xC0u, 0x6Eu}, + {0xC2u, 0xEDu}, + {0xC4u, 0xFFu}, + {0xCAu, 0x87u}, + {0xCCu, 0x6Du}, + {0xCEu, 0x5Fu}, {0xD6u, 0x18u}, {0xD8u, 0x18u}, - {0xE0u, 0x60u}, - {0xE2u, 0x10u}, - {0xE4u, 0x10u}, - {0xE6u, 0x04u}, - {0x01u, 0x5Cu}, - {0x05u, 0x11u}, - {0x07u, 0x22u}, - {0x09u, 0x50u}, - {0x0Bu, 0x0Cu}, - {0x0Du, 0x0Cu}, - {0x0Fu, 0x50u}, - {0x15u, 0x30u}, - {0x17u, 0x0Fu}, - {0x19u, 0x54u}, + {0xE0u, 0xF0u}, + {0xE6u, 0x18u}, + {0xE8u, 0x40u}, + {0xEAu, 0x20u}, + {0xECu, 0x80u}, + {0xEEu, 0x01u}, + {0x01u, 0x10u}, + {0x02u, 0x07u}, + {0x05u, 0x08u}, + {0x07u, 0x06u}, + {0x09u, 0x10u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x10u}, + {0x0Fu, 0x04u}, + {0x10u, 0x04u}, + {0x12u, 0x08u}, + {0x15u, 0x10u}, + {0x19u, 0x04u}, {0x1Bu, 0x08u}, - {0x1Du, 0x5Cu}, + {0x1Du, 0x10u}, + {0x1Eu, 0x20u}, {0x21u, 0x08u}, - {0x27u, 0x40u}, - {0x29u, 0x21u}, - {0x2Bu, 0x1Eu}, - {0x2Du, 0x24u}, - {0x2Fu, 0x10u}, - {0x31u, 0x30u}, - {0x33u, 0x40u}, - {0x35u, 0x0Fu}, - {0x3Bu, 0x02u}, + {0x22u, 0x08u}, + {0x23u, 0x04u}, + {0x28u, 0x09u}, + {0x29u, 0x08u}, + {0x2Au, 0x02u}, + {0x2Bu, 0x04u}, + {0x2Cu, 0x0Au}, + {0x2Eu, 0x05u}, + {0x2Fu, 0x01u}, + {0x30u, 0x20u}, + {0x31u, 0x02u}, + {0x33u, 0x10u}, + {0x34u, 0x10u}, + {0x35u, 0x0Cu}, + {0x36u, 0x0Fu}, + {0x37u, 0x01u}, + {0x39u, 0x08u}, + {0x3Bu, 0x20u}, {0x3Fu, 0x04u}, - {0x40u, 0x23u}, - {0x41u, 0x06u}, - {0x42u, 0x40u}, - {0x44u, 0x01u}, - {0x45u, 0xBDu}, - {0x46u, 0xF0u}, - {0x47u, 0xCEu}, - {0x48u, 0x3Bu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x22u}, - {0x4Eu, 0xF0u}, - {0x4Fu, 0x08u}, - {0x50u, 0x04u}, - {0x54u, 0x40u}, - {0x56u, 0x04u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Au, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x64u, 0x40u}, - {0x65u, 0x01u}, - {0x66u, 0x10u}, - {0x67u, 0x11u}, - {0x68u, 0xC0u}, - {0x69u, 0x01u}, - {0x6Bu, 0x11u}, - {0x6Cu, 0x40u}, - {0x6Du, 0x01u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x80u, 0x20u}, - {0x82u, 0x01u}, - {0x84u, 0x10u}, - {0x85u, 0x04u}, - {0x86u, 0x42u}, - {0x87u, 0x23u}, - {0x89u, 0x48u}, - {0x8Bu, 0x03u}, - {0x8Cu, 0x02u}, - {0x90u, 0x02u}, - {0x91u, 0x80u}, - {0x94u, 0x44u}, - {0x96u, 0x10u}, - {0x97u, 0x7Cu}, - {0x98u, 0x02u}, - {0x99u, 0x11u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x02u}, - {0xA0u, 0x08u}, - {0xA3u, 0x02u}, - {0xA5u, 0x80u}, - {0xA8u, 0x0Eu}, - {0xA9u, 0x70u}, - {0xAAu, 0x30u}, - {0xACu, 0x02u}, - {0xAFu, 0x01u}, - {0xB0u, 0x01u}, - {0xB3u, 0x70u}, - {0xB4u, 0x7Eu}, - {0xB5u, 0x0Fu}, - {0xB7u, 0x80u}, - {0xB8u, 0x20u}, + {0x81u, 0x96u}, + {0x83u, 0x69u}, + {0x84u, 0xAAu}, + {0x86u, 0x55u}, + {0x87u, 0xFFu}, + {0x89u, 0xFFu}, + {0x8Au, 0x80u}, + {0x8Du, 0x55u}, + {0x8Fu, 0xAAu}, + {0x91u, 0x33u}, + {0x93u, 0xCCu}, + {0x95u, 0x0Fu}, + {0x96u, 0x70u}, + {0x97u, 0xF0u}, + {0x9Bu, 0xFFu}, + {0x9Du, 0xFFu}, + {0x9Eu, 0x07u}, + {0xA0u, 0x99u}, + {0xA2u, 0x22u}, + {0xA6u, 0x08u}, + {0xA8u, 0x44u}, + {0xAAu, 0x88u}, + {0xABu, 0xFFu}, + {0xB2u, 0xF0u}, + {0xB5u, 0xFFu}, + {0xB6u, 0x0Fu}, + {0xBBu, 0x20u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x03u, 0x82u}, + {0x05u, 0x20u}, + {0x06u, 0x20u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x0Eu, 0x22u}, + {0x10u, 0x0Au}, + {0x12u, 0x80u}, + {0x14u, 0x80u}, + {0x15u, 0x04u}, + {0x16u, 0x08u}, + {0x19u, 0x11u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x82u}, + {0x1Eu, 0x22u}, + {0x1Fu, 0x40u}, + {0x20u, 0x60u}, + {0x21u, 0x50u}, + {0x22u, 0x31u}, + {0x23u, 0x04u}, + {0x25u, 0x10u}, + {0x27u, 0x08u}, + {0x29u, 0x51u}, + {0x2Cu, 0x08u}, + {0x32u, 0x50u}, + {0x33u, 0x04u}, + {0x34u, 0x01u}, + {0x36u, 0x20u}, + {0x37u, 0x88u}, + {0x38u, 0x66u}, + {0x3Eu, 0xA8u}, + {0x3Fu, 0x02u}, + {0x58u, 0x60u}, + {0x5Du, 0x8Au}, + {0x5Fu, 0x10u}, + {0x60u, 0x04u}, + {0x63u, 0x02u}, + {0x67u, 0x01u}, + {0x80u, 0x02u}, + {0x81u, 0x01u}, + {0x82u, 0x28u}, + {0x83u, 0x01u}, + {0x84u, 0x30u}, + {0x85u, 0x20u}, + {0x88u, 0x40u}, + {0x89u, 0x04u}, + {0x8Bu, 0x10u}, + {0x8Du, 0x04u}, + {0x8Eu, 0xC0u}, + {0xC0u, 0x69u}, + {0xC2u, 0xA9u}, + {0xC4u, 0x7Bu}, + {0xCAu, 0x2Du}, + {0xCCu, 0xFEu}, + {0xCEu, 0xFFu}, + {0xD6u, 0xFCu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x70u}, + {0xE4u, 0x80u}, + {0xE6u, 0x08u}, + {0x85u, 0x0Bu}, + {0x86u, 0x82u}, + {0x87u, 0x24u}, + {0x88u, 0x04u}, + {0x89u, 0x15u}, + {0x8Au, 0x23u}, + {0x8Bu, 0x0Au}, + {0x8Cu, 0x70u}, + {0x91u, 0x30u}, + {0x95u, 0x04u}, + {0x96u, 0x7Cu}, + {0x97u, 0x03u}, + {0x9Au, 0x01u}, + {0x9Cu, 0x11u}, + {0x9Eu, 0x02u}, + {0xA1u, 0x09u}, + {0xA3u, 0x16u}, + {0xA4u, 0x48u}, + {0xA6u, 0x03u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x07u}, + {0xB4u, 0x80u}, + {0xB6u, 0x70u}, + {0xB7u, 0x38u}, {0xB9u, 0x80u}, - {0xBEu, 0x10u}, - {0xBFu, 0x04u}, + {0xBBu, 0x08u}, + {0xBEu, 0x40u}, + {0xD6u, 0x02u}, + {0xD7u, 0x28u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x04u, 0x04u}, - {0x05u, 0x02u}, - {0x06u, 0x02u}, - {0x0Cu, 0xA1u}, - {0x0Du, 0x08u}, - {0x0Fu, 0x40u}, - {0x15u, 0x60u}, - {0x17u, 0x02u}, - {0x1Fu, 0x22u}, - {0x20u, 0x18u}, - {0x21u, 0x10u}, - {0x22u, 0x20u}, - {0x23u, 0x44u}, - {0x26u, 0x84u}, - {0x27u, 0x0Au}, - {0x28u, 0x01u}, - {0x29u, 0x04u}, - {0x2Au, 0x01u}, - {0x2Bu, 0x04u}, - {0x2Du, 0x02u}, - {0x2Eu, 0x20u}, - {0x2Fu, 0x22u}, - {0x30u, 0xA0u}, - {0x31u, 0x08u}, - {0x36u, 0x21u}, - {0x37u, 0x08u}, - {0x39u, 0x50u}, - {0x3Au, 0x02u}, - {0x3Bu, 0x04u}, - {0x3Cu, 0x24u}, - {0x40u, 0x04u}, - {0x41u, 0x09u}, - {0x42u, 0x01u}, + {0x01u, 0x48u}, + {0x03u, 0x40u}, + {0x05u, 0x20u}, + {0x06u, 0x10u}, + {0x07u, 0x01u}, + {0x0Au, 0x41u}, + {0x0Bu, 0x14u}, + {0x0Eu, 0x19u}, + {0x10u, 0x28u}, + {0x13u, 0x02u}, + {0x15u, 0x08u}, + {0x18u, 0x04u}, + {0x19u, 0x08u}, + {0x1Au, 0x42u}, + {0x1Eu, 0x18u}, + {0x1Fu, 0x80u}, + {0x21u, 0x80u}, + {0x26u, 0x08u}, + {0x27u, 0x11u}, + {0x2Au, 0x82u}, + {0x2Bu, 0x10u}, + {0x2Eu, 0x01u}, + {0x30u, 0x06u}, + {0x32u, 0xA0u}, + {0x36u, 0x08u}, + {0x37u, 0x01u}, + {0x3Fu, 0x14u}, + {0x40u, 0x06u}, + {0x41u, 0x04u}, + {0x46u, 0x08u}, + {0x47u, 0x10u}, {0x48u, 0x04u}, - {0x49u, 0x06u}, - {0x51u, 0x20u}, - {0x52u, 0x01u}, - {0x53u, 0x04u}, - {0x60u, 0x92u}, - {0x61u, 0x20u}, - {0x82u, 0x20u}, - {0x84u, 0x04u}, - {0x86u, 0x01u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x04u}, - {0x8Eu, 0x04u}, - {0x90u, 0x04u}, - {0x91u, 0x52u}, - {0x97u, 0x48u}, - {0x9Au, 0x02u}, - {0x9Cu, 0x80u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x01u}, - {0xA0u, 0xB0u}, - {0xA1u, 0x08u}, - {0xA2u, 0x01u}, - {0xA3u, 0x04u}, - {0xA6u, 0xA0u}, - {0xABu, 0x01u}, - {0xB2u, 0x08u}, - {0xB3u, 0x20u}, - {0xB4u, 0x04u}, - {0xC0u, 0xB0u}, - {0xC2u, 0xF0u}, - {0xC4u, 0xD0u}, - {0xCAu, 0xFFu}, - {0xCCu, 0xEEu}, - {0xCEu, 0x6Fu}, - {0xD0u, 0x0Fu}, - {0xD2u, 0x04u}, - {0xD8u, 0x0Fu}, - {0xE2u, 0x44u}, - {0xE4u, 0x02u}, - {0xE8u, 0x01u}, - {0x00u, 0x03u}, - {0x01u, 0xC0u}, - {0x02u, 0x0Cu}, - {0x03u, 0x01u}, - {0x04u, 0x05u}, - {0x06u, 0x0Au}, - {0x07u, 0xFFu}, - {0x08u, 0x40u}, - {0x09u, 0xC0u}, - {0x0Au, 0x1Fu}, + {0x49u, 0x64u}, + {0x4Bu, 0x02u}, + {0x51u, 0x01u}, + {0x52u, 0x11u}, + {0x53u, 0x48u}, + {0x66u, 0x08u}, + {0x6Cu, 0x38u}, + {0x6Du, 0x44u}, + {0x6Eu, 0x20u}, + {0x6Fu, 0x60u}, + {0x77u, 0x02u}, + {0x82u, 0x80u}, + {0x83u, 0x80u}, + {0x89u, 0x80u}, + {0x8Cu, 0x02u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x40u}, + {0x8Fu, 0x01u}, + {0x91u, 0x08u}, + {0x92u, 0x01u}, + {0x93u, 0x14u}, + {0x94u, 0x20u}, + {0x95u, 0x46u}, + {0x96u, 0x02u}, + {0x97u, 0x80u}, + {0x98u, 0x04u}, + {0x99u, 0x40u}, + {0x9Au, 0x02u}, + {0x9Du, 0x14u}, + {0x9Eu, 0x11u}, + {0x9Fu, 0x42u}, + {0xA0u, 0x06u}, + {0xA2u, 0xA0u}, + {0xA3u, 0x10u}, + {0xA4u, 0x28u}, + {0xA6u, 0x10u}, + {0xA7u, 0x28u}, + {0xC0u, 0xEDu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x2Eu}, + {0xCAu, 0x8Bu}, + {0xCCu, 0xCFu}, + {0xCEu, 0x60u}, + {0xD0u, 0x0Eu}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x40u}, + {0xE0u, 0x10u}, + {0xE2u, 0x01u}, + {0xE6u, 0x40u}, + {0x00u, 0xC0u}, + {0x01u, 0x01u}, + {0x02u, 0x02u}, + {0x05u, 0x08u}, + {0x06u, 0x9Fu}, + {0x07u, 0x21u}, + {0x08u, 0xC0u}, + {0x09u, 0x22u}, + {0x0Au, 0x04u}, {0x0Bu, 0x08u}, - {0x0Cu, 0x10u}, - {0x0Du, 0x80u}, - {0x0Eu, 0x2Fu}, - {0x13u, 0x9Fu}, - {0x14u, 0x06u}, - {0x15u, 0x7Fu}, - {0x16u, 0x09u}, - {0x17u, 0x80u}, - {0x19u, 0x1Fu}, - {0x1Au, 0x70u}, - {0x1Bu, 0x20u}, - {0x1Fu, 0x60u}, - {0x21u, 0xC0u}, - {0x23u, 0x02u}, - {0x24u, 0x20u}, - {0x25u, 0xC0u}, - {0x26u, 0x4Fu}, - {0x27u, 0x04u}, - {0x28u, 0x0Fu}, - {0x2Du, 0x90u}, - {0x2Fu, 0x40u}, - {0x31u, 0xFFu}, - {0x34u, 0x7Fu}, - {0x3Fu, 0x01u}, + {0x0Cu, 0x1Fu}, + {0x0Du, 0x04u}, + {0x0Eu, 0x20u}, + {0x11u, 0x01u}, + {0x12u, 0x60u}, + {0x14u, 0xC0u}, + {0x15u, 0x40u}, + {0x16u, 0x08u}, + {0x19u, 0x40u}, + {0x1Au, 0xFFu}, + {0x1Cu, 0x80u}, + {0x1Du, 0x01u}, + {0x20u, 0xC0u}, + {0x21u, 0x07u}, + {0x22u, 0x01u}, + {0x23u, 0x18u}, + {0x24u, 0x7Fu}, + {0x25u, 0x01u}, + {0x26u, 0x80u}, + {0x29u, 0x10u}, + {0x2Cu, 0x90u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x40u}, + {0x33u, 0x3Fu}, + {0x34u, 0xFFu}, + {0x37u, 0x40u}, + {0x39u, 0x88u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x04u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Bu, 0x04u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0xFFu}, + {0x80u, 0x65u}, {0x81u, 0x04u}, - {0x83u, 0x20u}, - {0x84u, 0x33u}, - {0x85u, 0x39u}, - {0x86u, 0xCCu}, - {0x87u, 0x06u}, - {0x88u, 0x0Fu}, - {0x8Au, 0xF0u}, - {0x8Bu, 0x46u}, - {0x8Du, 0x46u}, - {0x8Eu, 0xFFu}, - {0x90u, 0x69u}, - {0x92u, 0x96u}, - {0x95u, 0x01u}, - {0x97u, 0x5Eu}, - {0x98u, 0x55u}, - {0x99u, 0x42u}, - {0x9Au, 0xAAu}, - {0x9Bu, 0x04u}, - {0x9Du, 0x46u}, - {0xA1u, 0x46u}, - {0xA2u, 0xFFu}, - {0xA4u, 0xFFu}, - {0xA5u, 0x77u}, - {0xA7u, 0x08u}, - {0xAAu, 0xFFu}, - {0xADu, 0x42u}, - {0xB3u, 0x70u}, - {0xB4u, 0xFFu}, - {0xB5u, 0x0Fu}, - {0xB9u, 0x20u}, - {0xBAu, 0x20u}, - {0xBBu, 0x0Cu}, - {0xD6u, 0x02u}, - {0xD7u, 0x20u}, + {0x83u, 0x12u}, + {0x84u, 0x25u}, + {0x86u, 0x40u}, + {0x88u, 0x22u}, + {0x8Au, 0x01u}, + {0x8Cu, 0x60u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x05u}, + {0x8Fu, 0x0Au}, + {0x92u, 0x04u}, + {0x94u, 0x03u}, + {0x95u, 0x02u}, + {0x96u, 0x78u}, + {0x97u, 0x04u}, + {0x98u, 0x0Au}, + {0x99u, 0x04u}, + {0x9Au, 0x71u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x09u}, + {0x9Du, 0x04u}, + {0x9Eu, 0x12u}, + {0x9Fu, 0x03u}, + {0xA0u, 0x65u}, + {0xA8u, 0x05u}, + {0xAAu, 0x60u}, + {0xACu, 0x40u}, + {0xB0u, 0x03u}, + {0xB1u, 0x10u}, + {0xB2u, 0x04u}, + {0xB3u, 0x06u}, + {0xB4u, 0x03u}, + {0xB5u, 0x01u}, + {0xB6u, 0x78u}, + {0xB7u, 0x08u}, + {0xBAu, 0x22u}, + {0xBBu, 0x08u}, + {0xBEu, 0x04u}, + {0xD4u, 0x40u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x01u}, - {0x01u, 0x20u}, - {0x02u, 0x10u}, - {0x03u, 0x01u}, - {0x04u, 0x2Au}, - {0x06u, 0x04u}, - {0x07u, 0x01u}, + {0x01u, 0x64u}, + {0x03u, 0x40u}, + {0x04u, 0x20u}, + {0x05u, 0x40u}, + {0x06u, 0x10u}, + {0x07u, 0x40u}, {0x08u, 0x02u}, - {0x09u, 0x20u}, - {0x0Eu, 0x28u}, - {0x11u, 0x05u}, - {0x12u, 0x04u}, - {0x15u, 0x04u}, - {0x17u, 0x10u}, - {0x18u, 0x08u}, - {0x19u, 0x20u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x94u}, + {0x0Eu, 0xA0u}, + {0x0Fu, 0x06u}, + {0x10u, 0x08u}, + {0x12u, 0x01u}, + {0x13u, 0x02u}, + {0x15u, 0x48u}, + {0x17u, 0x03u}, + {0x18u, 0x10u}, + {0x19u, 0x61u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x81u}, {0x1Eu, 0x08u}, - {0x1Fu, 0x20u}, - {0x20u, 0x2Cu}, + {0x20u, 0x60u}, {0x21u, 0x08u}, - {0x22u, 0x08u}, - {0x26u, 0x01u}, - {0x28u, 0x10u}, - {0x2Au, 0x82u}, - {0x2Cu, 0xA0u}, + {0x22u, 0x50u}, + {0x25u, 0x40u}, + {0x26u, 0x40u}, + {0x27u, 0x20u}, {0x2Du, 0x40u}, - {0x30u, 0xA0u}, + {0x2Fu, 0xA8u}, {0x31u, 0x08u}, - {0x34u, 0x10u}, - {0x35u, 0x02u}, - {0x36u, 0xA8u}, - {0x37u, 0x08u}, - {0x38u, 0x04u}, - {0x39u, 0x50u}, - {0x3Au, 0x01u}, - {0x3Bu, 0x01u}, - {0x3Cu, 0x04u}, - {0x3Eu, 0x92u}, - {0x3Fu, 0x48u}, - {0x63u, 0x02u}, - {0x68u, 0xA8u}, - {0x69u, 0x50u}, - {0x6Au, 0x10u}, - {0x72u, 0x02u}, + {0x32u, 0x50u}, + {0x36u, 0x04u}, + {0x37u, 0x62u}, + {0x38u, 0x40u}, + {0x3Bu, 0x02u}, + {0x3Du, 0x80u}, + {0x3Fu, 0x16u}, + {0x5Cu, 0x80u}, + {0x60u, 0x12u}, + {0x61u, 0x10u}, + {0x63u, 0x80u}, + {0x67u, 0x02u}, {0x88u, 0x80u}, - {0x8Bu, 0x04u}, - {0x90u, 0x23u}, - {0x91u, 0x07u}, - {0x95u, 0x40u}, - {0x98u, 0x02u}, - {0x9Au, 0x10u}, - {0x9Bu, 0x11u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x08u}, - {0xA1u, 0x20u}, - {0xA2u, 0x10u}, - {0xA3u, 0x01u}, - {0xA4u, 0xACu}, - {0xA6u, 0x20u}, - {0xABu, 0x58u}, - {0xB1u, 0x01u}, - {0xB3u, 0x04u}, - {0xB4u, 0x80u}, - {0xB6u, 0x10u}, + {0x8Fu, 0x40u}, + {0x91u, 0x08u}, + {0x93u, 0x14u}, + {0x95u, 0x42u}, + {0x96u, 0x02u}, + {0x98u, 0x04u}, + {0x9Au, 0x02u}, + {0x9Du, 0x45u}, + {0x9Fu, 0x41u}, + {0xA0u, 0x06u}, + {0xA2u, 0xA0u}, + {0xA3u, 0x10u}, + {0xA4u, 0x38u}, + {0xB0u, 0x02u}, + {0xB3u, 0x08u}, + {0xB6u, 0x11u}, + {0xB7u, 0x20u}, {0xC0u, 0xFFu}, - {0xC2u, 0x6Au}, - {0xC4u, 0x6Eu}, - {0xCAu, 0xDBu}, + {0xC2u, 0xFFu}, + {0xC4u, 0xBBu}, + {0xCAu, 0xF0u}, {0xCCu, 0xFEu}, - {0xCEu, 0xFFu}, - {0xD8u, 0x08u}, - {0xE2u, 0x28u}, - {0xE8u, 0x04u}, - {0xEEu, 0x01u}, - {0x39u, 0x20u}, - {0x3Fu, 0x10u}, - {0x59u, 0x04u}, - {0x5Fu, 0x01u}, - {0x27u, 0x08u}, - {0x87u, 0x08u}, - {0x88u, 0x08u}, - {0x90u, 0x04u}, - {0x96u, 0x10u}, - {0x97u, 0x80u}, - {0x9Cu, 0x18u}, - {0x9Du, 0xC0u}, - {0xA6u, 0x20u}, - {0xA7u, 0x40u}, - {0xA8u, 0x04u}, - {0xA9u, 0x04u}, - {0xAAu, 0x01u}, - {0xB0u, 0x02u}, - {0xB1u, 0x02u}, - {0xB5u, 0x10u}, - {0xE0u, 0x80u}, - {0xE8u, 0xE0u}, - {0xEAu, 0x10u}, - {0x80u, 0x04u}, - {0x84u, 0x10u}, - {0x86u, 0x20u}, - {0x90u, 0x04u}, - {0x9Cu, 0x10u}, - {0xA6u, 0x20u}, - {0xAAu, 0x10u}, - {0xB1u, 0xC0u}, - {0xB3u, 0x40u}, - {0xB7u, 0x40u}, - {0xE8u, 0x80u}, - {0xECu, 0xC0u}, - {0x12u, 0x08u}, + {0xCEu, 0xF9u}, + {0xD6u, 0x10u}, + {0xD8u, 0x1Fu}, + {0xE6u, 0x40u}, + {0xEAu, 0x40u}, + {0xEEu, 0x48u}, + {0x9Cu, 0x80u}, + {0xA0u, 0x20u}, + {0xB0u, 0x04u}, + {0xB4u, 0x20u}, + {0xE2u, 0x20u}, + {0xECu, 0x80u}, + {0xEEu, 0x18u}, + {0x80u, 0x20u}, + {0x88u, 0x80u}, + {0x9Cu, 0x80u}, + {0xA0u, 0x20u}, + {0xE0u, 0x20u}, + {0x13u, 0x20u}, {0x16u, 0x80u}, - {0x17u, 0x80u}, - {0x33u, 0x04u}, - {0x35u, 0x08u}, + {0x17u, 0x40u}, + {0x33u, 0x08u}, {0x36u, 0x80u}, - {0x3Au, 0x81u}, - {0x3Du, 0x04u}, - {0x3Fu, 0x20u}, - {0x43u, 0x20u}, - {0x52u, 0x20u}, - {0x5Bu, 0x01u}, - {0x60u, 0x20u}, - {0x64u, 0x08u}, - {0x65u, 0x40u}, - {0x82u, 0x01u}, - {0x85u, 0x40u}, - {0x87u, 0x01u}, + {0x37u, 0x08u}, + {0x39u, 0x08u}, + {0x3Au, 0x80u}, + {0x3Cu, 0x04u}, + {0x3Fu, 0x10u}, + {0x41u, 0x20u}, + {0x56u, 0x20u}, + {0x5Au, 0x04u}, + {0x60u, 0x40u}, + {0x65u, 0x01u}, + {0x66u, 0x40u}, + {0x86u, 0x20u}, + {0x8Bu, 0x10u}, + {0x8Eu, 0x40u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x20u}, + {0xD4u, 0x40u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x60u}, - {0xE6u, 0x10u}, - {0x33u, 0x18u}, - {0x35u, 0x04u}, - {0x37u, 0x80u}, - {0x39u, 0x80u}, - {0x54u, 0x02u}, - {0x57u, 0x10u}, - {0x5Bu, 0x40u}, - {0x63u, 0x80u}, - {0x95u, 0x04u}, - {0x9Bu, 0xD0u}, - {0x9Cu, 0x20u}, - {0x9Du, 0x08u}, - {0x9Fu, 0x04u}, + {0xE2u, 0x10u}, + {0x30u, 0x20u}, + {0x32u, 0x01u}, + {0x37u, 0x44u}, + {0x3Bu, 0x10u}, + {0x52u, 0x20u}, + {0x56u, 0x20u}, + {0x5Au, 0x40u}, + {0x5Du, 0x02u}, + {0x68u, 0x20u}, + {0x6Bu, 0x20u}, + {0x81u, 0x02u}, + {0x82u, 0x20u}, + {0x8Bu, 0x08u}, + {0x8Eu, 0x20u}, + {0x92u, 0x40u}, + {0x94u, 0x44u}, + {0x96u, 0x04u}, + {0x9Bu, 0x60u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x08u}, + {0xA5u, 0x20u}, {0xA6u, 0x80u}, - {0xA7u, 0x20u}, - {0xA8u, 0x08u}, - {0xAAu, 0x08u}, - {0xABu, 0x50u}, - {0xAEu, 0x20u}, - {0xB7u, 0x10u}, + {0xA7u, 0x08u}, + {0xB1u, 0x04u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, - {0xD4u, 0xC0u}, - {0xD6u, 0x20u}, - {0xD8u, 0x40u}, - {0xEEu, 0xE0u}, + {0xD4u, 0xE0u}, + {0xD6u, 0x80u}, + {0xE6u, 0xA0u}, {0x12u, 0x80u}, - {0x32u, 0x10u}, - {0x82u, 0x10u}, - {0x83u, 0x50u}, - {0x85u, 0x08u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x20u}, - {0x95u, 0x84u}, - {0x9Du, 0x0Cu}, + {0x33u, 0x80u}, + {0x94u, 0x44u}, + {0x96u, 0x02u}, + {0x97u, 0x10u}, {0x9Fu, 0x04u}, + {0xA5u, 0x20u}, {0xA6u, 0x80u}, - {0xA7u, 0x78u}, - {0xA8u, 0x22u}, + {0xA7u, 0x08u}, + {0xAEu, 0x04u}, + {0xB2u, 0x40u}, + {0xB5u, 0x01u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0xE2u, 0x20u}, - {0xE6u, 0xB0u}, - {0xEAu, 0x20u}, - {0xEEu, 0x20u}, - {0x81u, 0x44u}, - {0x95u, 0x84u}, - {0x9Du, 0x04u}, - {0xA0u, 0x20u}, - {0xABu, 0x04u}, - {0xAFu, 0x20u}, - {0xE2u, 0x80u}, - {0xE6u, 0x80u}, - {0xEAu, 0x80u}, - {0xEEu, 0x10u}, - {0x08u, 0x04u}, - {0x09u, 0x80u}, + {0xEAu, 0x40u}, + {0x61u, 0x01u}, + {0x81u, 0x01u}, + {0x83u, 0x04u}, + {0x86u, 0x01u}, + {0x87u, 0x10u}, + {0x94u, 0x44u}, + {0x96u, 0x02u}, + {0x97u, 0x10u}, + {0x9Fu, 0x04u}, + {0xA5u, 0x20u}, + {0xA7u, 0x80u}, + {0xAFu, 0x08u}, + {0xD8u, 0x40u}, + {0xE2u, 0xB0u}, + {0xE6u, 0x40u}, + {0xEEu, 0x40u}, + {0x09u, 0x04u}, + {0x0Au, 0x08u}, {0x0Fu, 0x20u}, - {0x12u, 0x20u}, - {0x17u, 0x01u}, - {0x50u, 0x04u}, - {0x57u, 0x20u}, - {0x58u, 0x20u}, - {0x5Fu, 0x40u}, - {0x80u, 0x40u}, + {0x10u, 0x10u}, + {0x14u, 0x80u}, + {0x51u, 0x08u}, + {0x53u, 0x01u}, + {0x55u, 0x40u}, + {0x5Du, 0x80u}, + {0x86u, 0x04u}, + {0x8Bu, 0x80u}, + {0x8Du, 0x04u}, {0xC2u, 0x0Eu}, {0xC4u, 0x0Cu}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0x00u, 0x40u}, - {0x02u, 0x10u}, - {0x05u, 0x20u}, - {0x07u, 0x20u}, - {0x08u, 0x02u}, - {0x09u, 0x20u}, - {0x0Du, 0x01u}, - {0x0Eu, 0x02u}, - {0x83u, 0x10u}, - {0x8Au, 0x10u}, - {0x8Bu, 0x60u}, - {0x94u, 0x40u}, - {0x97u, 0x40u}, - {0x9Bu, 0x01u}, - {0xA2u, 0x20u}, + {0xE2u, 0x01u}, + {0xE6u, 0x02u}, + {0x03u, 0x88u}, + {0x05u, 0x40u}, + {0x06u, 0x20u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x80u}, + {0x0Du, 0x10u}, + {0x0Eu, 0x20u}, + {0x85u, 0x40u}, + {0x89u, 0x08u}, + {0x8Fu, 0x01u}, + {0x97u, 0x02u}, + {0x9Du, 0x80u}, {0xA3u, 0x10u}, - {0xA7u, 0x20u}, - {0xA8u, 0x04u}, - {0xACu, 0x20u}, - {0xB0u, 0x04u}, - {0xB5u, 0x80u}, + {0xA5u, 0x48u}, + {0xA7u, 0x80u}, + {0xA8u, 0x80u}, + {0xB0u, 0x10u}, {0xC0u, 0x0Fu}, {0xC2u, 0x0Fu}, - {0xE0u, 0x05u}, - {0xE6u, 0x04u}, - {0xEAu, 0x08u}, - {0xEEu, 0x01u}, - {0x82u, 0x05u}, - {0x84u, 0x02u}, - {0x8Bu, 0x11u}, - {0x91u, 0x02u}, - {0x98u, 0x02u}, - {0x99u, 0x20u}, - {0x9Bu, 0x21u}, - {0xA1u, 0x20u}, - {0xA2u, 0x01u}, - {0xAEu, 0x20u}, - {0xE2u, 0x04u}, - {0xE6u, 0x04u}, - {0x0Bu, 0x21u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x20u}, - {0x83u, 0x11u}, - {0x85u, 0x01u}, + {0xE0u, 0x02u}, + {0xE4u, 0x04u}, + {0xEAu, 0x04u}, + {0x8Au, 0x10u}, + {0x8Du, 0x80u}, + {0x8Fu, 0x10u}, + {0x9Au, 0x20u}, + {0x9Du, 0x80u}, + {0xA2u, 0x10u}, + {0xA3u, 0x10u}, + {0xA5u, 0x40u}, + {0xAEu, 0x04u}, + {0xAFu, 0x08u}, + {0xB1u, 0x10u}, + {0xB3u, 0x40u}, + {0xE2u, 0x09u}, + {0xE4u, 0x02u}, + {0xEEu, 0x05u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x20u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x02u}, + {0x81u, 0x02u}, + {0x86u, 0x01u}, + {0x87u, 0x10u}, + {0xAAu, 0x20u}, + {0xB1u, 0x40u}, + {0xC2u, 0x0Fu}, + {0xECu, 0x04u}, {0x8Cu, 0x04u}, - {0x91u, 0x02u}, - {0x97u, 0x20u}, - {0x99u, 0x20u}, - {0xA6u, 0x04u}, - {0xAFu, 0x20u}, + {0x94u, 0x04u}, + {0xAFu, 0x80u}, + {0xB4u, 0x40u}, {0xB5u, 0x20u}, - {0xC2u, 0x0Fu}, - {0xE6u, 0x02u}, - {0xEEu, 0x02u}, - {0x67u, 0x80u}, - {0x87u, 0x40u}, - {0x89u, 0x04u}, - {0x95u, 0x04u}, - {0xA0u, 0x20u}, - {0xD8u, 0x80u}, - {0xE2u, 0x10u}, - {0x06u, 0x40u}, - {0x50u, 0x20u}, - {0x57u, 0x80u}, - {0x86u, 0x40u}, - {0x8Fu, 0x80u}, - {0xA0u, 0x20u}, + {0xEEu, 0x10u}, + {0x04u, 0x08u}, + {0x52u, 0x80u}, + {0x56u, 0x20u}, + {0x82u, 0x80u}, + {0x8Cu, 0x04u}, + {0x8Eu, 0x20u}, {0xC0u, 0x20u}, {0xD4u, 0x60u}, - {0xE0u, 0x10u}, - {0x94u, 0x04u}, - {0xB5u, 0x20u}, - {0xEAu, 0x08u}, - {0x00u, 0x04u}, - {0x94u, 0x04u}, + {0xE6u, 0x20u}, + {0x88u, 0x04u}, + {0xAFu, 0x01u}, + {0xE2u, 0x04u}, + {0x00u, 0x08u}, + {0xA4u, 0x04u}, {0xC0u, 0x08u}, {0x10u, 0x03u}, + {0x11u, 0x01u}, {0x1Au, 0x03u}, + {0x1Bu, 0x01u}, {0x00u, 0xFDu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, @@ -2204,18 +2039,30 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0x8Du, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Du, 0x00u, 0x80u, 0x00u, + 0x00u, 0x0Fu, 0x10u, 0xF0u, 0x62u, 0x30u, 0x08u, 0xC0u, 0x02u, 0x50u, 0x54u, 0xA0u, 0x01u, 0x06u, 0x32u, 0x09u, + 0x8Du, 0x05u, 0x00u, 0x0Au, 0x8Du, 0x03u, 0x00u, 0x0Cu, 0x8Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x00u, 0x90u, + 0x70u, 0x00u, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x80u, 0xFFu, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x50u, 0x40u, + 0x63u, 0x05u, 0x20u, 0x00u, 0x01u, 0xFEu, 0xBDu, 0xCBu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u}; + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index b6b926e..2a57e06 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -391,34 +391,34 @@ .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -426,9 +426,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 @@ -450,8 +450,8 @@ .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -459,9 +459,13 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2 @@ -1941,15 +1945,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1962,37 +1966,37 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK /* SCSI_Out_Ctl */ .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK /* SCSI_Out_DBx */ .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG @@ -2818,8 +2822,6 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2827,9 +2829,9 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST /* Debug_Timer_Interrupt */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2950,8 +2952,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2959,67 +2961,67 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index bfc5642..48927dd 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -459,9 +459,13 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 @@ -1941,15 +1945,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1962,37 +1966,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK /* SCSI_Out_Ctl */ SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK /* SCSI_Out_DBx */ SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2818,8 +2822,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2827,9 +2829,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST /* Debug_Timer_Interrupt */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2950,8 +2952,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2959,67 +2961,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index b0cda45..b4a739d 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 @@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -459,9 +459,13 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 @@ -1941,15 +1945,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1962,37 +1966,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK ; SCSI_Out_Ctl SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK ; SCSI_Out_DBx SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG @@ -2818,8 +2822,6 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2827,9 +2829,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST ; Debug_Timer_Interrupt Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2950,8 +2952,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2959,67 +2961,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index bae2d8f..140a2c9 100755 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -28,7 +28,7 @@ __attribute__ ((__section__(".cyloadablemeta"), used)) const uint8 cy_meta_loadable[] = { 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x04u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx index 57ece01..555f967 100644 --- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -66,7 +66,7 @@